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authorRamesh Babu K V <ramesh.b.k.v@intel.com>2010-10-04 06:37:53 -0400
committerDan Williams <dan.j.williams@intel.com>2010-10-07 18:03:43 -0400
commit576e3c394a6c427c9a1378ec88ef7eb97e731992 (patch)
tree55cfcf13ac594a63d1f8056bca08c6db66edcb3e /include
parent03b96dca010145f3896abcd443b7fddb9813a0e6 (diff)
intel_mid_dma: Add sg list support to DMA driver
For a very high speed DMA various periphral devices need scatter-gather list support. The DMA hardware support link list items. This list can be circular also (adding new flag DMA_PREP_CIRCULAR_LIST) Right now this flag is in driver header and should be moved to dmaengine header file eventually Signed-off-by: Ramesh Babu K V <ramesh.b.k.v@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/intel_mid_dma.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/intel_mid_dma.h b/include/linux/intel_mid_dma.h
index d9d08b6269b6..befe3fbd9e28 100644
--- a/include/linux/intel_mid_dma.h
+++ b/include/linux/intel_mid_dma.h
@@ -27,6 +27,7 @@
27 27
28#include <linux/dmaengine.h> 28#include <linux/dmaengine.h>
29 29
30#define DMA_PREP_CIRCULAR_LIST (1 << 10)
30/*DMA transaction width, src and dstn width would be same 31/*DMA transaction width, src and dstn width would be same
31The DMA length must be width aligned, 32The DMA length must be width aligned,
32for 32 bit width the length must be 32 bit (4bytes) aligned only*/ 33for 32 bit width the length must be 32 bit (4bytes) aligned only*/
@@ -69,6 +70,7 @@ enum intel_mid_dma_msize {
69 * @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem) 70 * @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem)
70 * @src_msize: Source DMA burst size 71 * @src_msize: Source DMA burst size
71 * @dst_msize: Dst DMA burst size 72 * @dst_msize: Dst DMA burst size
73 * @per_addr: Periphral address
72 * @device_instance: DMA peripheral device instance, we can have multiple 74 * @device_instance: DMA peripheral device instance, we can have multiple
73 * peripheral device connected to single DMAC 75 * peripheral device connected to single DMAC
74 */ 76 */
@@ -80,6 +82,7 @@ struct intel_mid_dma_slave {
80 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/ 82 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
81 enum intel_mid_dma_msize src_msize; /*size if src burst*/ 83 enum intel_mid_dma_msize src_msize; /*size if src burst*/
82 enum intel_mid_dma_msize dst_msize; /*size of dst burst*/ 84 enum intel_mid_dma_msize dst_msize; /*size of dst burst*/
85 dma_addr_t per_addr; /*Peripheral address*/
83 unsigned int device_instance; /*0, 1 for periphral instance*/ 86 unsigned int device_instance; /*0, 1 for periphral instance*/
84}; 87};
85 88