diff options
| author | Andi Kleen <ak@suse.de> | 2006-01-11 16:42:45 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-11 22:01:12 -0500 |
| commit | 39b3a7910556005a7a0d042ecb7ff98bfa84ea57 (patch) | |
| tree | efcb2602e6fd198c9af34e726741eb389fa4e292 /include | |
| parent | 2d52ede9876ba566b583f255fdc43800eea81baa (diff) | |
[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag
Define it for i386 too.
This is a synthetic flag that signifies that the CPU's TSC runs
at a constant P state invariant frequency.
Fix up the logic on x86-64/i386 to set it on all known CPUs.
Use the AMD defined bit to set it on future AMD CPUs.
Cc: venkatesh.pallipadi@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-i386/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index ff1187e80c32..c4ec2a4d8fdf 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h | |||
| @@ -69,6 +69,7 @@ | |||
| 69 | #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ | 69 | #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ |
| 70 | #define X86_FEATURE_P3 (3*32+ 6) /* P3 */ | 70 | #define X86_FEATURE_P3 (3*32+ 6) /* P3 */ |
| 71 | #define X86_FEATURE_P4 (3*32+ 7) /* P4 */ | 71 | #define X86_FEATURE_P4 (3*32+ 7) /* P4 */ |
| 72 | #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ | ||
| 72 | 73 | ||
| 73 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 74 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
| 74 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 75 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |