diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2007-05-26 04:14:43 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-05-29 05:49:49 -0400 |
commit | 22adb358e816ce6aa0afb231ae9d826b0bddc8b0 (patch) | |
tree | 6f9886bf5b4e5c916c72d8d5733211813873c5fc /include | |
parent | 5cbc30737398b49f62ae8603129ce43ac7db1a41 (diff) |
[SPARC64]: Eliminate NR_CPUS limitations.
Cheetah systems can have cpuids as large as 1023, although physical
systems don't have that many cpus.
Only three limitations existed in the kernel preventing arbitrary
NR_CPUS values:
1) dcache dirty cpu state stored in page->flags on
D-cache aliasing platforms. With some build time
calculations and some build-time BUG checks on
page->flags layout, this one was easily solved.
2) The cheetah XCALL delivery code could only handle
a cpumask with up to 32 cpus set. Some simple looping
logic clears that up too.
3) thread_info->cpu was a u8, easily changed to a u16.
There are a few spots in the kernel that still put NR_CPUS
sized arrays on the kernel stack, but that's not a sparc64
specific problem.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-sparc64/cpudata.h | 2 | ||||
-rw-r--r-- | include/asm-sparc64/thread_info.h | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h index f321b1d21227..03c385de7619 100644 --- a/include/asm-sparc64/cpudata.h +++ b/include/asm-sparc64/cpudata.h | |||
@@ -202,7 +202,7 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch, | |||
202 | * the calculations done by the macro mid-stream. | 202 | * the calculations done by the macro mid-stream. |
203 | */ | 203 | */ |
204 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ | 204 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ |
205 | ldub [THR + TI_CPU], REG1; \ | 205 | lduh [THR + TI_CPU], REG1; \ |
206 | sethi %hi(__per_cpu_shift), REG3; \ | 206 | sethi %hi(__per_cpu_shift), REG3; \ |
207 | sethi %hi(__per_cpu_base), REG2; \ | 207 | sethi %hi(__per_cpu_base), REG2; \ |
208 | ldx [REG3 + %lo(__per_cpu_shift)], REG3; \ | 208 | ldx [REG3 + %lo(__per_cpu_shift)], REG3; \ |
diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h index 2ebf7f27bf91..98252cd44dd6 100644 --- a/include/asm-sparc64/thread_info.h +++ b/include/asm-sparc64/thread_info.h | |||
@@ -38,8 +38,8 @@ struct thread_info { | |||
38 | /* D$ line 1 */ | 38 | /* D$ line 1 */ |
39 | struct task_struct *task; | 39 | struct task_struct *task; |
40 | unsigned long flags; | 40 | unsigned long flags; |
41 | __u8 cpu; | ||
42 | __u8 fpsaved[7]; | 41 | __u8 fpsaved[7]; |
42 | __u8 pad; | ||
43 | unsigned long ksp; | 43 | unsigned long ksp; |
44 | 44 | ||
45 | /* D$ line 2 */ | 45 | /* D$ line 2 */ |
@@ -49,7 +49,7 @@ struct thread_info { | |||
49 | int preempt_count; /* 0 => preemptable, <0 => BUG */ | 49 | int preempt_count; /* 0 => preemptable, <0 => BUG */ |
50 | __u8 new_child; | 50 | __u8 new_child; |
51 | __u8 syscall_noerror; | 51 | __u8 syscall_noerror; |
52 | __u16 __pad; | 52 | __u16 cpu; |
53 | 53 | ||
54 | unsigned long *utraps; | 54 | unsigned long *utraps; |
55 | 55 | ||
@@ -83,8 +83,7 @@ struct thread_info { | |||
83 | #define TI_CURRENT_DS (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS) | 83 | #define TI_CURRENT_DS (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS) |
84 | #define TI_FPDEPTH (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH) | 84 | #define TI_FPDEPTH (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH) |
85 | #define TI_WSAVED (TI_FLAGS + TI_FLAG_BYTE_WSAVED) | 85 | #define TI_WSAVED (TI_FLAGS + TI_FLAG_BYTE_WSAVED) |
86 | #define TI_CPU 0x00000010 | 86 | #define TI_FPSAVED 0x00000010 |
87 | #define TI_FPSAVED 0x00000011 | ||
88 | #define TI_KSP 0x00000018 | 87 | #define TI_KSP 0x00000018 |
89 | #define TI_FAULT_ADDR 0x00000020 | 88 | #define TI_FAULT_ADDR 0x00000020 |
90 | #define TI_KREGS 0x00000028 | 89 | #define TI_KREGS 0x00000028 |
@@ -92,6 +91,7 @@ struct thread_info { | |||
92 | #define TI_PRE_COUNT 0x00000038 | 91 | #define TI_PRE_COUNT 0x00000038 |
93 | #define TI_NEW_CHILD 0x0000003c | 92 | #define TI_NEW_CHILD 0x0000003c |
94 | #define TI_SYS_NOERROR 0x0000003d | 93 | #define TI_SYS_NOERROR 0x0000003d |
94 | #define TI_CPU 0x0000003e | ||
95 | #define TI_UTRAPS 0x00000040 | 95 | #define TI_UTRAPS 0x00000040 |
96 | #define TI_REG_WINDOW 0x00000048 | 96 | #define TI_REG_WINDOW 0x00000048 |
97 | #define TI_RWIN_SPTRS 0x000003c8 | 97 | #define TI_RWIN_SPTRS 0x000003c8 |