diff options
| author | Linus Walleij <linus.walleij@stericsson.com> | 2010-06-02 03:13:52 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-27 05:43:47 -0400 |
| commit | ec489aa8f993f8d2ec962ce113071faac482aa27 (patch) | |
| tree | fa7a56687acb12f7bf928da04296a83b5ce0be10 /include | |
| parent | c58bbd39f876955be6e072748fdfe2b671f9d939 (diff) | |
ARM: 6157/2: PL011 TX/RX split of LCR for ST-Ericssons derivative
In the ST-Ericsson version of the PL011 the TX and RX have different
control registers.
Cc: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/amba/serial.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h index 5a5a7fd62490..93c96a66c518 100644 --- a/include/linux/amba/serial.h +++ b/include/linux/amba/serial.h | |||
| @@ -38,10 +38,12 @@ | |||
| 38 | #define UART01x_FR 0x18 /* Flag register (Read only). */ | 38 | #define UART01x_FR 0x18 /* Flag register (Read only). */ |
| 39 | #define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ | 39 | #define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ |
| 40 | #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ | 40 | #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ |
| 41 | #define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */ | ||
| 41 | #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ | 42 | #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ |
| 42 | #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ | 43 | #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ |
| 43 | #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ | 44 | #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ |
| 44 | #define UART011_LCRH 0x2c /* Line control register. */ | 45 | #define UART011_LCRH 0x2c /* Line control register. */ |
| 46 | #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */ | ||
| 45 | #define UART011_CR 0x30 /* Control register. */ | 47 | #define UART011_CR 0x30 /* Control register. */ |
| 46 | #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ | 48 | #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ |
| 47 | #define UART011_IMSC 0x38 /* Interrupt mask. */ | 49 | #define UART011_IMSC 0x38 /* Interrupt mask. */ |