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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2008-03-03 13:35:38 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-03-03 13:35:38 -0500
commit5ce6386b900c83aa31d0490335df421a8d544381 (patch)
treea22ff66d0bf343db369309be84cfeced6275311c /include
parenta64e715fc74b1a7dcc5944f848acc38b2c4d4ee2 (diff)
parent3cecdda3f169f22f324f78fd544beee68e3cc6a4 (diff)
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (24 commits) [POWERPC] Convert the cell IOMMU fixed mapping to 16M IOMMU pages [POWERPC] Allow for different IOMMU page sizes in cell IOMMU code [POWERPC] Cell IOMMU: n_pte_pages is in 4K page units, not IOMMU_PAGE_SIZE [POWERPC] Split setup of IOMMU stab and ptab, allocate dynamic/fixed ptabs separately [POWERPC] Move allocation of cell IOMMU pad page [POWERPC] Remove unused pte_offset variable [POWERPC] Use it_offset not pte_offset in cell IOMMU code [POWERPC] Clearup cell IOMMU fixed mapping terminology [POWERPC] enable hardware watchpoints on cell blades [POWERPC] move celleb DABRX definitions [POWERPC] OProfile: enable callgraph support for Cell [POWERPC] spufs: fix use time accounting on SPE-overcommit [POWERPC] spufs: serialize SLB invalidation against SLB loading [POWERPC] spufs: invalidate SLB translation before adding a new entry [POWERPC] spufs: synchronize IRQ when disabling [POWERPC] spufs: fix order of sputrace thread IDs [POWERPC] Xilinx: hwicap cleanup [POWERPC] 4xx: Use correct board info structure in cuboot wrappers [POWERPC] spufs: fix invalid scheduling of forgotten contexts [POWERPC] 44x: add missing define TARGET_4xx and TARGET_440GX to cuboot-taishan ...
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/reg.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 0d6238987df8..edc0cfd7f6e2 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -153,6 +153,9 @@
153#define CTRL_RUNLATCH 0x1 153#define CTRL_RUNLATCH 0x1
154#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 154#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
155#define DABR_TRANSLATION (1UL << 2) 155#define DABR_TRANSLATION (1UL << 2)
156#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
157#define DABRX_USER (1UL << 0)
158#define DABRX_KERNEL (1UL << 1)
156#define SPRN_DAR 0x013 /* Data Address Register */ 159#define SPRN_DAR 0x013 /* Data Address Register */
157#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 160#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
158#define DSISR_NOHPTE 0x40000000 /* no translation found */ 161#define DSISR_NOHPTE 0x40000000 /* no translation found */