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authorRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:01 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:01 -0400
commite7c4782f92fc4b83d953ce53f77f05ae65dcd773 (patch)
tree8b72472f8653ed55593f52fc10e7eaa9b7b31f1b /include
parent192cca6ef2c49ac5ff46f7a31cb9dd175995658e (diff)
[MIPS] Put an end to <asm/serial.h>'s long and annyoing existence
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/serial.h110
1 files changed, 0 insertions, 110 deletions
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 5b9c8ea977b8..c07ebd8eb9e7 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -19,114 +19,4 @@
19 */ 19 */
20#define BASE_BAUD (1843200 / 16) 20#define BASE_BAUD (1843200 / 16)
21 21
22/* Standard COM flags (except for COM4, because of the 8514 problem) */
23#ifdef CONFIG_SERIAL_DETECT_IRQ
24#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
25#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
26#else
27#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
28#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
29#endif
30
31#ifdef CONFIG_MACH_JAZZ
32#include <asm/jazz.h>
33
34#ifndef CONFIG_OLIVETTI_M700
35 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
36 exactly which ones ... XXX */
37#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
38#else
39/* but the M700 isn't such a strange beast */
40#define JAZZ_BASE_BAUD BASE_BAUD
41#endif
42
43#define _JAZZ_SERIAL_INIT(int, base) \
44 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
45 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
46 .io_type = SERIAL_IO_MEM }
47#define JAZZ_SERIAL_PORT_DEFNS \
48 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
50#else
51#define JAZZ_SERIAL_PORT_DEFNS
52#endif
53
54#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
55#define STD_SERIAL_PORT_DEFNS \
56 /* UART CLK PORT IRQ FLAGS */ \
57 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
58 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
59 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
60 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
61
62#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
63#define STD_SERIAL_PORT_DEFNS
64#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
65
66#ifdef CONFIG_MOMENCO_OCELOT_3
67#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
68#define OCELOT_3_SERIAL_IRQ 6
69#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
70
71#define _OCELOT_3_SERIAL_INIT(int, base) \
72 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
73 .flags = STD_COM_FLAGS, \
74 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
75 io_type: SERIAL_IO_MEM }
76
77#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
78 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
79#else
80#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
81#endif
82
83#ifdef CONFIG_MOMENCO_OCELOT
84/* Ordinary NS16552 duart with a 20MHz crystal. */
85#define OCELOT_BASE_BAUD ( 20000000 / 16 )
86
87#define OCELOT_SERIAL1_IRQ 4
88#define OCELOT_SERIAL1_BASE 0xe0001020
89
90#define _OCELOT_SERIAL_INIT(int, base) \
91 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
92 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
93 .io_type = SERIAL_IO_MEM }
94#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
95 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
96#else
97#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
98#endif
99
100#ifdef CONFIG_DDB5477
101#include <asm/ddb5xxx/ddb5477.h>
102#define DDB5477_SERIAL_PORT_DEFNS \
103 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
104 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
105 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
106 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
107 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
108 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
109#else
110#define DDB5477_SERIAL_PORT_DEFNS
111#endif
112
113#ifdef CONFIG_SGI_IP32
114/*
115 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
116 * They are initialized in ip32_setup
117 */
118#define IP32_SERIAL_PORT_DEFNS \
119 {},{},
120#else
121#define IP32_SERIAL_PORT_DEFNS
122#endif /* CONFIG_SGI_IP32 */
123
124#define SERIAL_PORT_DFNS \
125 DDB5477_SERIAL_PORT_DEFNS \
126 IP32_SERIAL_PORT_DEFNS \
127 JAZZ_SERIAL_PORT_DEFNS \
128 STD_SERIAL_PORT_DEFNS \
129 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
130 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
131
132#endif /* _ASM_SERIAL_H */ 22#endif /* _ASM_SERIAL_H */