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authorChristoph Lameter <clameter@sgi.com>2007-12-18 19:22:46 -0500
committerTony Luck <tony.luck@intel.com>2007-12-18 19:22:46 -0500
commita3ebdb6c423dff420168a3faf25c76e9e5f59258 (patch)
tree397317fda83da7f745d802d5ba87735f163bf1c9 /include
parentc63a1190368771b8207d86c4217ae4afdf1cbd5e (diff)
IA64: Slim down __clear_bit_unlock
__clear_bit_unlock does not need to perform atomic operations on the variable. Avoid a cmpxchg and simply do a store with release semantics. Add a barrier to be safe that the compiler does not do funky things. Tony: Use intrinsic rather than inline assembler Signed-off-by: Christoph Lameter <clameter@sgi.com> Acked-by: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ia64/bitops.h17
-rw-r--r--include/asm-ia64/gcc_intrin.h5
-rw-r--r--include/asm-ia64/intel_intrin.h3
3 files changed, 22 insertions, 3 deletions
diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h
index a977affaebec..a1b9719f5fbb 100644
--- a/include/asm-ia64/bitops.h
+++ b/include/asm-ia64/bitops.h
@@ -124,10 +124,21 @@ clear_bit_unlock (int nr, volatile void *addr)
124/** 124/**
125 * __clear_bit_unlock - Non-atomically clear a bit with release 125 * __clear_bit_unlock - Non-atomically clear a bit with release
126 * 126 *
127 * This is like clear_bit_unlock, but the implementation may use a non-atomic 127 * This is like clear_bit_unlock, but the implementation uses a store
128 * store (this one uses an atomic, however). 128 * with release semantics. See also __raw_spin_unlock().
129 */ 129 */
130#define __clear_bit_unlock clear_bit_unlock 130static __inline__ void
131__clear_bit_unlock(int nr, volatile void *addr)
132{
133 __u32 mask, new;
134 volatile __u32 *m;
135
136 m = (volatile __u32 *)addr + (nr >> 5);
137 mask = ~(1 << (nr & 31));
138 new = *m & mask;
139 barrier();
140 ia64_st4_rel_nta(m, new);
141}
131 142
132/** 143/**
133 * __clear_bit - Clears a bit in memory (non-atomic version) 144 * __clear_bit - Clears a bit in memory (non-atomic version)
diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h
index 4fb4e439b05c..e58d3298fa10 100644
--- a/include/asm-ia64/gcc_intrin.h
+++ b/include/asm-ia64/gcc_intrin.h
@@ -191,6 +191,11 @@ register unsigned long ia64_r13 asm ("r13") __attribute_used__;
191 asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ 191 asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
192}) 192})
193 193
194#define ia64_st4_rel_nta(m, val) \
195({ \
196 asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
197})
198
194#define ia64_stfs(x, regnum) \ 199#define ia64_stfs(x, regnum) \
195({ \ 200({ \
196 register double __f__ asm ("f"#regnum); \ 201 register double __f__ asm ("f"#regnum); \
diff --git a/include/asm-ia64/intel_intrin.h b/include/asm-ia64/intel_intrin.h
index d069b6acddce..a520d103d808 100644
--- a/include/asm-ia64/intel_intrin.h
+++ b/include/asm-ia64/intel_intrin.h
@@ -110,6 +110,9 @@
110#define ia64_st4_rel __st4_rel 110#define ia64_st4_rel __st4_rel
111#define ia64_st8_rel __st8_rel 111#define ia64_st8_rel __st8_rel
112 112
113/* FIXME: need st4.rel.nta intrinsic */
114#define ia64_st4_rel_nta __st4_rel
115
113#define ia64_ld1_acq __ld1_acq 116#define ia64_ld1_acq __ld1_acq
114#define ia64_ld2_acq __ld2_acq 117#define ia64_ld2_acq __ld2_acq
115#define ia64_ld4_acq __ld4_acq 118#define ia64_ld4_acq __ld4_acq