diff options
author | Lucas Correia Villa Real <lucasvr@org.rmk.(none)> | 2005-04-25 13:36:50 -0400 |
---|---|---|
committer | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2005-04-25 13:36:50 -0400 |
commit | a3342421363642d03b2ae3ecd27e3041de043e99 (patch) | |
tree | d90217f63c552f70a9731a1aafed5868fe1ebc9b /include | |
parent | 8e293ada7d6aaee43dd56a8077b83577dd108667 (diff) |
[PATCH] ARM: 2640/1: Adds DRAM/BANKSIZE_MASK definitions for S3C2400
Patch from Lucas Correia Villa Real
Adds DRAM refresh definitions and sets the BANKSIZE_MASK for the S3C2400 on
include/asm-arm/arch-s3c2400/regs-mem.h
Signed-off-by: Lucas Correia Villa Real
Signed-off-by: Ben Dooks
Signed-off-by: Russell King
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-mem.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h index 1a1328ac0d79..a2d7d0cec042 100644 --- a/include/asm-arm/arch-s3c2410/regs-mem.h +++ b/include/asm-arm/arch-s3c2410/regs-mem.h | |||
@@ -12,6 +12,7 @@ | |||
12 | * Changelog: | 12 | * Changelog: |
13 | * 29-Sep-2004 BJD Initial include for Linux | 13 | * 29-Sep-2004 BJD Initial include for Linux |
14 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | 14 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA |
15 | * 04-Apr-2005 LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions | ||
15 | * | 16 | * |
16 | */ | 17 | */ |
17 | 18 | ||
@@ -183,6 +184,12 @@ | |||
183 | #define S3C2410_REFRESH_TRP_3clk (1<<20) | 184 | #define S3C2410_REFRESH_TRP_3clk (1<<20) |
184 | #define S3C2410_REFRESH_TRP_4clk (2<<20) | 185 | #define S3C2410_REFRESH_TRP_4clk (2<<20) |
185 | 186 | ||
187 | #define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20) | ||
188 | #define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20) | ||
189 | #define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20) | ||
190 | #define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20) | ||
191 | #define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20) | ||
192 | |||
186 | #define S3C2410_REFRESH_TSRC_MASK (3<<18) | 193 | #define S3C2410_REFRESH_TSRC_MASK (3<<18) |
187 | #define S3C2410_REFRESH_TSRC_4clk (0<<18) | 194 | #define S3C2410_REFRESH_TSRC_4clk (0<<18) |
188 | #define S3C2410_REFRESH_TSRC_5clk (1<<18) | 195 | #define S3C2410_REFRESH_TSRC_5clk (1<<18) |
@@ -205,6 +212,7 @@ | |||
205 | #define S3C2410_BANKSIZE_4M (0x5 << 0) | 212 | #define S3C2410_BANKSIZE_4M (0x5 << 0) |
206 | #define S3C2410_BANKSIZE_2M (0x4 << 0) | 213 | #define S3C2410_BANKSIZE_2M (0x4 << 0) |
207 | #define S3C2410_BANKSIZE_MASK (0x7 << 0) | 214 | #define S3C2410_BANKSIZE_MASK (0x7 << 0) |
215 | #define S3C2400_BANKSIZE_MASK (0x4 << 0) | ||
208 | #define S3C2410_BANKSIZE_SCLK_EN (1<<4) | 216 | #define S3C2410_BANKSIZE_SCLK_EN (1<<4) |
209 | #define S3C2410_BANKSIZE_SCKE_EN (1<<5) | 217 | #define S3C2410_BANKSIZE_SCKE_EN (1<<5) |
210 | #define S3C2410_BANKSIZE_BURST (1<<7) | 218 | #define S3C2410_BANKSIZE_BURST (1<<7) |