[PATCH] AVR32 MTD: Static Memory Controller driver

This patchset adds the necessary drivers and infrastructure to access the
external flash on the ATSTK1000 board through the MTD subsystem.  With this
stuff in place, it will be possible to use a jffs2 filesystem stored in the
external flash as a root filesystem.  It might also be possible to update the
boot loader if you drop the write protection of partition 0.

As suggested by David Woodhouse, I reworked the patches to use the physmap
driver instead of introducing a separate mapping driver for the ATSTK1000.
I've also cleaned up the hsmc header by removing useless comments and
converting spaces to tabs (my headerfile generator needs some work.)

Unfortunately, I couldn't unlock the flash in fixup_use_atmel_lock because the
erase regions hadn't been set up yet, so I had to do it from cfi_amdstd_setup
instead.

This patch:

This adds a simple API for configuring the static memory controller along with
an implementation for the Atmel HSMC.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 60 insertions, 0 deletions

diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h
new file mode 100644
index 000000000000..3732b328303d
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/smc.h
@@ -0,0 +1,60 @@
+/*
+ * Static Memory Controller for AT32 chips
+ *
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Inspired by the OMAP2 General-Purpose Memory Controller interface
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_AT32AP_SMC_H
+#define __ARCH_AT32AP_SMC_H
+
+/*
+ * All timing parameters are in nanoseconds.
+ */
+struct smc_config {
+        /* Delay from address valid to assertion of given strobe */
+        u16             ncs_read_setup;
+        u16             nrd_setup;
+        u16             ncs_write_setup;
+        u16             nwe_setup;
+
+        /* Pulse length of given strobe */
+        u16             ncs_read_pulse;
+        u16             nrd_pulse;
+        u16             ncs_write_pulse;
+        u16             nwe_pulse;
+
+        /* Total cycle length of given operation */
+        u16             read_cycle;
+        u16             write_cycle;
+
+        /* Bus width in bytes */
+        u8              bus_width;
+
+        /*
+         * 0: Data is sampled on rising edge of NCS
+         * 1: Data is sampled on rising edge of NRD
+         */
+        unsigned int    nrd_controlled:1;
+
+        /*
+         * 0: Data is driven on falling edge of NCS
+         * 1: Data is driven on falling edge of NWR
+         */
+        unsigned int    nwe_controlled:1;
+
+        /*
+         * 0: Byte select access type
+         * 1: Byte write access type
+         */
+        unsigned int    byte_write:1;
+};
+
+extern int smc_set_configuration(int cs, const struct smc_config *config);
+extern struct smc_config *smc_get_configuration(int cs);
+
+#endif /* __ARCH_AT32AP_SMC_H */