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authorRafał Miłecki <zajec5@gmail.com>2011-05-09 12:56:46 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-05-10 15:54:54 -0400
commit8369ae33b705222aa05ab53c7d6b4458f4ed161b (patch)
treece5d592a63134f1283473bc900bf59489b92d8eb /include
parent306fe9384f06d31219778cece2d3c646146e7bb6 (diff)
bcma: add Broadcom specific AMBA bus driver
Broadcom has released cards based on a new AMBA-based bus type. From a programming point of view, this new bus type differs from AMBA and does not use AMBA common registers. It also differs enough from SSB. We decided that a new bus driver is needed to keep the code clean. In its current form, the driver detects devices present on the bus and registers them in the system. It allows registering BCMA drivers for specified bus devices and provides them basic operations. The bus driver itself includes two important bus managing drivers: ChipCommon core driver and PCI(c) core driver. They are early used to allow correct initialization. Currently code is limited to supporting buses on PCI(e) devices, however the driver is designed to be used also on other hosts. The host abstraction layer is implemented and already used for PCI(e). Support for PCI(e) hosts is working and seems to be stable (access to 80211 core was tested successfully on a few devices). We can still optimize it by using some fixed windows, but this can be done later without affecting any external code. Windows are just ranges in MMIO used for accessing cores on the bus. Cc: Greg KH <greg@kroah.com> Cc: Michael Büsch <mb@bu3sch.de> Cc: Larry Finger <Larry.Finger@lwfinger.net> Cc: George Kashperko <george@znau.edu.ua> Cc: Arend van Spriel <arend@broadcom.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <rmk@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andy Botting <andy@andybotting.com> Cc: linuxdriverproject <devel@linuxdriverproject.org> Cc: linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/bcma/bcma.h224
-rw-r--r--include/linux/bcma/bcma_driver_chipcommon.h297
-rw-r--r--include/linux/bcma/bcma_driver_pci.h89
-rw-r--r--include/linux/bcma/bcma_regs.h34
-rw-r--r--include/linux/mod_devicetable.h17
5 files changed, 661 insertions, 0 deletions
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
new file mode 100644
index 000000000000..08763e4e848f
--- /dev/null
+++ b/include/linux/bcma/bcma.h
@@ -0,0 +1,224 @@
1#ifndef LINUX_BCMA_H_
2#define LINUX_BCMA_H_
3
4#include <linux/pci.h>
5#include <linux/mod_devicetable.h>
6
7#include <linux/bcma/bcma_driver_chipcommon.h>
8#include <linux/bcma/bcma_driver_pci.h>
9
10#include "bcma_regs.h"
11
12struct bcma_device;
13struct bcma_bus;
14
15enum bcma_hosttype {
16 BCMA_HOSTTYPE_NONE,
17 BCMA_HOSTTYPE_PCI,
18 BCMA_HOSTTYPE_SDIO,
19};
20
21struct bcma_chipinfo {
22 u16 id;
23 u8 rev;
24 u8 pkg;
25};
26
27struct bcma_host_ops {
28 u8 (*read8)(struct bcma_device *core, u16 offset);
29 u16 (*read16)(struct bcma_device *core, u16 offset);
30 u32 (*read32)(struct bcma_device *core, u16 offset);
31 void (*write8)(struct bcma_device *core, u16 offset, u8 value);
32 void (*write16)(struct bcma_device *core, u16 offset, u16 value);
33 void (*write32)(struct bcma_device *core, u16 offset, u32 value);
34 /* Agent ops */
35 u32 (*aread32)(struct bcma_device *core, u16 offset);
36 void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
37};
38
39/* Core manufacturers */
40#define BCMA_MANUF_ARM 0x43B
41#define BCMA_MANUF_MIPS 0x4A7
42#define BCMA_MANUF_BCM 0x4BF
43
44/* Core class values. */
45#define BCMA_CL_SIM 0x0
46#define BCMA_CL_EROM 0x1
47#define BCMA_CL_CORESIGHT 0x9
48#define BCMA_CL_VERIF 0xB
49#define BCMA_CL_OPTIMO 0xD
50#define BCMA_CL_GEN 0xE
51#define BCMA_CL_PRIMECELL 0xF
52
53/* Core-ID values. */
54#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
55#define BCMA_CORE_INVALID 0x700
56#define BCMA_CORE_CHIPCOMMON 0x800
57#define BCMA_CORE_ILINE20 0x801
58#define BCMA_CORE_SRAM 0x802
59#define BCMA_CORE_SDRAM 0x803
60#define BCMA_CORE_PCI 0x804
61#define BCMA_CORE_MIPS 0x805
62#define BCMA_CORE_ETHERNET 0x806
63#define BCMA_CORE_V90 0x807
64#define BCMA_CORE_USB11_HOSTDEV 0x808
65#define BCMA_CORE_ADSL 0x809
66#define BCMA_CORE_ILINE100 0x80A
67#define BCMA_CORE_IPSEC 0x80B
68#define BCMA_CORE_UTOPIA 0x80C
69#define BCMA_CORE_PCMCIA 0x80D
70#define BCMA_CORE_INTERNAL_MEM 0x80E
71#define BCMA_CORE_MEMC_SDRAM 0x80F
72#define BCMA_CORE_OFDM 0x810
73#define BCMA_CORE_EXTIF 0x811
74#define BCMA_CORE_80211 0x812
75#define BCMA_CORE_PHY_A 0x813
76#define BCMA_CORE_PHY_B 0x814
77#define BCMA_CORE_PHY_G 0x815
78#define BCMA_CORE_MIPS_3302 0x816
79#define BCMA_CORE_USB11_HOST 0x817
80#define BCMA_CORE_USB11_DEV 0x818
81#define BCMA_CORE_USB20_HOST 0x819
82#define BCMA_CORE_USB20_DEV 0x81A
83#define BCMA_CORE_SDIO_HOST 0x81B
84#define BCMA_CORE_ROBOSWITCH 0x81C
85#define BCMA_CORE_PARA_ATA 0x81D
86#define BCMA_CORE_SATA_XORDMA 0x81E
87#define BCMA_CORE_ETHERNET_GBIT 0x81F
88#define BCMA_CORE_PCIE 0x820
89#define BCMA_CORE_PHY_N 0x821
90#define BCMA_CORE_SRAM_CTL 0x822
91#define BCMA_CORE_MINI_MACPHY 0x823
92#define BCMA_CORE_ARM_1176 0x824
93#define BCMA_CORE_ARM_7TDMI 0x825
94#define BCMA_CORE_PHY_LP 0x826
95#define BCMA_CORE_PMU 0x827
96#define BCMA_CORE_PHY_SSN 0x828
97#define BCMA_CORE_SDIO_DEV 0x829
98#define BCMA_CORE_ARM_CM3 0x82A
99#define BCMA_CORE_PHY_HT 0x82B
100#define BCMA_CORE_MIPS_74K 0x82C
101#define BCMA_CORE_MAC_GBIT 0x82D
102#define BCMA_CORE_DDR12_MEM_CTL 0x82E
103#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
104#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
105#define BCMA_CORE_SHARED_COMMON 0x831
106#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
107#define BCMA_CORE_SPI_HOST 0x833
108#define BCMA_CORE_I2S 0x834
109#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
110#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
111#define BCMA_CORE_DEFAULT 0xFFF
112
113#define BCMA_MAX_NR_CORES 16
114
115struct bcma_device {
116 struct bcma_bus *bus;
117 struct bcma_device_id id;
118
119 struct device dev;
120 bool dev_registered;
121
122 u8 core_index;
123
124 u32 addr;
125 u32 wrap;
126
127 void *drvdata;
128 struct list_head list;
129};
130
131static inline void *bcma_get_drvdata(struct bcma_device *core)
132{
133 return core->drvdata;
134}
135static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
136{
137 core->drvdata = drvdata;
138}
139
140struct bcma_driver {
141 const char *name;
142 const struct bcma_device_id *id_table;
143
144 int (*probe)(struct bcma_device *dev);
145 void (*remove)(struct bcma_device *dev);
146 int (*suspend)(struct bcma_device *dev, pm_message_t state);
147 int (*resume)(struct bcma_device *dev);
148 void (*shutdown)(struct bcma_device *dev);
149
150 struct device_driver drv;
151};
152extern
153int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
154static inline int bcma_driver_register(struct bcma_driver *drv)
155{
156 return __bcma_driver_register(drv, THIS_MODULE);
157}
158extern void bcma_driver_unregister(struct bcma_driver *drv);
159
160struct bcma_bus {
161 /* The MMIO area. */
162 void __iomem *mmio;
163
164 const struct bcma_host_ops *ops;
165
166 enum bcma_hosttype hosttype;
167 union {
168 /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
169 struct pci_dev *host_pci;
170 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
171 struct sdio_func *host_sdio;
172 };
173
174 struct bcma_chipinfo chipinfo;
175
176 struct bcma_device *mapped_core;
177 struct list_head cores;
178 u8 nr_cores;
179
180 struct bcma_drv_cc drv_cc;
181 struct bcma_drv_pci drv_pci;
182};
183
184extern inline u32 bcma_read8(struct bcma_device *core, u16 offset)
185{
186 return core->bus->ops->read8(core, offset);
187}
188extern inline u32 bcma_read16(struct bcma_device *core, u16 offset)
189{
190 return core->bus->ops->read16(core, offset);
191}
192extern inline u32 bcma_read32(struct bcma_device *core, u16 offset)
193{
194 return core->bus->ops->read32(core, offset);
195}
196extern inline
197void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
198{
199 core->bus->ops->write8(core, offset, value);
200}
201extern inline
202void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
203{
204 core->bus->ops->write16(core, offset, value);
205}
206extern inline
207void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
208{
209 core->bus->ops->write32(core, offset, value);
210}
211extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
212{
213 return core->bus->ops->aread32(core, offset);
214}
215extern inline
216void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
217{
218 core->bus->ops->awrite32(core, offset, value);
219}
220
221extern bool bcma_core_is_enabled(struct bcma_device *core);
222extern int bcma_core_enable(struct bcma_device *core, u32 flags);
223
224#endif /* LINUX_BCMA_H_ */
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
new file mode 100644
index 000000000000..4f8fd6a4c1e6
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -0,0 +1,297 @@
1#ifndef LINUX_BCMA_DRIVER_CC_H_
2#define LINUX_BCMA_DRIVER_CC_H_
3
4/** ChipCommon core registers. **/
5#define BCMA_CC_ID 0x0000
6#define BCMA_CC_ID_ID 0x0000FFFF
7#define BCMA_CC_ID_ID_SHIFT 0
8#define BCMA_CC_ID_REV 0x000F0000
9#define BCMA_CC_ID_REV_SHIFT 16
10#define BCMA_CC_ID_PKG 0x00F00000
11#define BCMA_CC_ID_PKG_SHIFT 20
12#define BCMA_CC_ID_NRCORES 0x0F000000
13#define BCMA_CC_ID_NRCORES_SHIFT 24
14#define BCMA_CC_ID_TYPE 0xF0000000
15#define BCMA_CC_ID_TYPE_SHIFT 28
16#define BCMA_CC_CAP 0x0004 /* Capabilities */
17#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
18#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
19#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
20#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
21#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
22#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
23#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
24#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
25#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
26#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
27#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
28#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
29#define BCMA_PLLTYPE_NONE 0x00000000
30#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
31#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
32#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
33#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
34#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
35#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
36#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
37#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
38#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
39#define BCMA_CC_CAP_OTPS_SHIFT 19
40#define BCMA_CC_CAP_OTPS_BASE 5
41#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
42#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
43#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
44#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
45#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
46#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
47#define BCMA_CC_CORECTL 0x0008
48#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
49#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
50#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
51#define BCMA_CC_BIST 0x000C
52#define BCMA_CC_OTPS 0x0010 /* OTP status */
53#define BCMA_CC_OTPS_PROGFAIL 0x80000000
54#define BCMA_CC_OTPS_PROTECT 0x00000007
55#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
56#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
57#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
58#define BCMA_CC_OTPC 0x0014 /* OTP control */
59#define BCMA_CC_OTPC_RECWAIT 0xFF000000
60#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
61#define BCMA_CC_OTPC_PRW_SHIFT 8
62#define BCMA_CC_OTPC_MAXFAIL 0x00000038
63#define BCMA_CC_OTPC_VSEL 0x00000006
64#define BCMA_CC_OTPC_SELVL 0x00000001
65#define BCMA_CC_OTPP 0x0018 /* OTP prog */
66#define BCMA_CC_OTPP_COL 0x000000FF
67#define BCMA_CC_OTPP_ROW 0x0000FF00
68#define BCMA_CC_OTPP_ROW_SHIFT 8
69#define BCMA_CC_OTPP_READERR 0x10000000
70#define BCMA_CC_OTPP_VALUE 0x20000000
71#define BCMA_CC_OTPP_READ 0x40000000
72#define BCMA_CC_OTPP_START 0x80000000
73#define BCMA_CC_OTPP_BUSY 0x80000000
74#define BCMA_CC_IRQSTAT 0x0020
75#define BCMA_CC_IRQMASK 0x0024
76#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
77#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
78#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
79#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
80#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
81#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
82#define BCMA_CC_JCMD_START 0x80000000
83#define BCMA_CC_JCMD_BUSY 0x80000000
84#define BCMA_CC_JCMD_PAUSE 0x40000000
85#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
86#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
87#define BCMA_CC_JCMD0_ACC_DR 0x00001000
88#define BCMA_CC_JCMD0_ACC_IR 0x00002000
89#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
90#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
91#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
92#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
93#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
94#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
95#define BCMA_CC_JCMD_ACC_DR 0x00010000
96#define BCMA_CC_JCMD_ACC_IR 0x00020000
97#define BCMA_CC_JCMD_ACC_RESET 0x00030000
98#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
99#define BCMA_CC_JCMD_ACC_PDR 0x00050000
100#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
101#define BCMA_CC_JCMD_IRW_SHIFT 8
102#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
103#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
104#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
105#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
106#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
107#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
108#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
109#define BCMA_CC_FLASHCTL 0x0040
110#define BCMA_CC_FLASHCTL_START 0x80000000
111#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
112#define BCMA_CC_FLASHADDR 0x0044
113#define BCMA_CC_FLASHDATA 0x0048
114#define BCMA_CC_BCAST_ADDR 0x0050
115#define BCMA_CC_BCAST_DATA 0x0054
116#define BCMA_CC_GPIOIN 0x0060
117#define BCMA_CC_GPIOOUT 0x0064
118#define BCMA_CC_GPIOOUTEN 0x0068
119#define BCMA_CC_GPIOCTL 0x006C
120#define BCMA_CC_GPIOPOL 0x0070
121#define BCMA_CC_GPIOIRQ 0x0074
122#define BCMA_CC_WATCHDOG 0x0080
123#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
124#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
125#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
126#define BCMA_CC_CLOCK_N 0x0090
127#define BCMA_CC_CLOCK_SB 0x0094
128#define BCMA_CC_CLOCK_PCI 0x0098
129#define BCMA_CC_CLOCK_M2 0x009C
130#define BCMA_CC_CLOCK_MIPS 0x00A0
131#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
132#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
133#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
134#define BCMA_CC_CLKDIV_OTP 0x000F0000
135#define BCMA_CC_CLKDIV_OTP_SHIFT 16
136#define BCMA_CC_CLKDIV_JTAG 0x00000F00
137#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
138#define BCMA_CC_CLKDIV_UART 0x000000FF
139#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
140#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
141#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
142#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
143#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
144#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
145#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
146#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
147#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
148#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
149#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
150#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
151#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
152#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
153#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
154#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
155#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
156#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
157#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
158#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
159#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
160#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
161#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
162#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
163#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
164#define BCMA_CC_EROM 0x00FC
165#define BCMA_CC_PCMCIA_CFG 0x0100
166#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
167#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
168#define BCMA_CC_PCMCIA_IOWAIT 0x010C
169#define BCMA_CC_IDE_CFG 0x0110
170#define BCMA_CC_IDE_MEMWAIT 0x0114
171#define BCMA_CC_IDE_ATTRWAIT 0x0118
172#define BCMA_CC_IDE_IOWAIT 0x011C
173#define BCMA_CC_PROG_CFG 0x0120
174#define BCMA_CC_PROG_WAITCNT 0x0124
175#define BCMA_CC_FLASH_CFG 0x0128
176#define BCMA_CC_FLASH_WAITCNT 0x012C
177#define BCMA_CC_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
178#define BCMA_CC_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
179#define BCMA_CC_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
180#define BCMA_CC_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
181#define BCMA_CC_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
182#define BCMA_CC_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
183#define BCMA_CC_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
184#define BCMA_CC_CLKCTLST_HAVEHT 0x00010000 /* HT available */
185#define BCMA_CC_CLKCTLST_HAVEALP 0x00020000 /* APL available */
186#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
187#define BCMA_CC_UART0_DATA 0x0300
188#define BCMA_CC_UART0_IMR 0x0304
189#define BCMA_CC_UART0_FCR 0x0308
190#define BCMA_CC_UART0_LCR 0x030C
191#define BCMA_CC_UART0_MCR 0x0310
192#define BCMA_CC_UART0_LSR 0x0314
193#define BCMA_CC_UART0_MSR 0x0318
194#define BCMA_CC_UART0_SCRATCH 0x031C
195#define BCMA_CC_UART1_DATA 0x0400
196#define BCMA_CC_UART1_IMR 0x0404
197#define BCMA_CC_UART1_FCR 0x0408
198#define BCMA_CC_UART1_LCR 0x040C
199#define BCMA_CC_UART1_MCR 0x0410
200#define BCMA_CC_UART1_LSR 0x0414
201#define BCMA_CC_UART1_MSR 0x0418
202#define BCMA_CC_UART1_SCRATCH 0x041C
203/* PMU registers (rev >= 20) */
204#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
205#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
206#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
207#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
208#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
209#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
210#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
211#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
212#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
213#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
214#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
215#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
216#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
217#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
218#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
219#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
220#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
221#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
222#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
223#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
224#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
225#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
226#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
227#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
228#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
229#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
230#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
231#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
232#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
233#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
234#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
235#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
236#define BCMA_CC_CHIPCTL_ADDR 0x0650
237#define BCMA_CC_CHIPCTL_DATA 0x0654
238#define BCMA_CC_REGCTL_ADDR 0x0658
239#define BCMA_CC_REGCTL_DATA 0x065C
240#define BCMA_CC_PLLCTL_ADDR 0x0660
241#define BCMA_CC_PLLCTL_DATA 0x0664
242
243/* Data for the PMU, if available.
244 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
245 */
246struct bcma_chipcommon_pmu {
247 u8 rev; /* PMU revision */
248 u32 crystalfreq; /* The active crystal frequency (in kHz) */
249};
250
251struct bcma_drv_cc {
252 struct bcma_device *core;
253 u32 status;
254 u32 capabilities;
255 u32 capabilities_ext;
256 /* Fast Powerup Delay constant */
257 u16 fast_pwrup_delay;
258 struct bcma_chipcommon_pmu pmu;
259};
260
261/* Register access */
262#define bcma_cc_read32(cc, offset) \
263 bcma_read32((cc)->core, offset)
264#define bcma_cc_write32(cc, offset, val) \
265 bcma_write32((cc)->core, offset, val)
266
267#define bcma_cc_mask32(cc, offset, mask) \
268 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
269#define bcma_cc_set32(cc, offset, set) \
270 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
271#define bcma_cc_maskset32(cc, offset, mask, set) \
272 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
273
274extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
275
276extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
277extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
278
279extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
280 u32 ticks);
281
282void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
283
284u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
285
286/* Chipcommon GPIO pin access. */
287u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
288u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
289u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
290u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
291u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
292u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
293
294/* PMU support */
295extern void bcma_pmu_init(struct bcma_drv_cc *cc);
296
297#endif /* LINUX_BCMA_DRIVER_CC_H_ */
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h
new file mode 100644
index 000000000000..b7e191cf00ec
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -0,0 +1,89 @@
1#ifndef LINUX_BCMA_DRIVER_PCI_H_
2#define LINUX_BCMA_DRIVER_PCI_H_
3
4#include <linux/types.h>
5
6struct pci_dev;
7
8/** PCI core registers. **/
9#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
10#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
11#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
12#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
13#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
14#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
15#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
16#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
17#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
18#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
19#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
20#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
21#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
22#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */
23#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
24#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
25#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
26#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
27#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
28#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */
29#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
30#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
31#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
32#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
33#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
34#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
35#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
36#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
37#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
38#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
39#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
40#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
41#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
42#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
43#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
44#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
45#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
46#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
47#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
48#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
49#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
50#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
51#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
52#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
53#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
54#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
55#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
56#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
57#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
58#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
59#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
60#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
61
62/* SBtoPCIx */
63#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
64#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
65#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
66#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
67#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
68#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */
69#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
70#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
71#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
72#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
73#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
74
75/* PCIcore specific boardflags */
76#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
77
78struct bcma_drv_pci {
79 struct bcma_device *core;
80 u8 setup_done:1;
81};
82
83/* Register access */
84#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
85#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
86
87extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
88
89#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
new file mode 100644
index 000000000000..f82d88a960ce
--- /dev/null
+++ b/include/linux/bcma/bcma_regs.h
@@ -0,0 +1,34 @@
1#ifndef LINUX_BCMA_REGS_H_
2#define LINUX_BCMA_REGS_H_
3
4/* Agent registers (common for every core) */
5#define BCMA_IOCTL 0x0408
6#define BCMA_IOCTL_CLK 0x0001
7#define BCMA_IOCTL_FGC 0x0002
8#define BCMA_IOCTL_CORE_BITS 0x3FFC
9#define BCMA_IOCTL_PME_EN 0x4000
10#define BCMA_IOCTL_BIST_EN 0x8000
11#define BCMA_RESET_CTL 0x0800
12#define BCMA_RESET_CTL_RESET 0x0001
13
14/* BCMA PCI config space registers. */
15#define BCMA_PCI_PMCSR 0x44
16#define BCMA_PCI_PE 0x100
17#define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */
18#define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */
19#define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */
20#define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */
21#define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */
22#define BCMA_PCI_IRQS 0x90 /* PCI interrupts */
23#define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
24#define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
25#define BCMA_PCI_BAR0_WIN2 0xAC
26#define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
27#define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
28#define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
29#define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
30#define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
31#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
32#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
33
34#endif /* LINUX_BCMA_REGS_H_ */
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 48c007dae476..ae28e93fd072 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -382,6 +382,23 @@ struct ssb_device_id {
382#define SSB_ANY_ID 0xFFFF 382#define SSB_ANY_ID 0xFFFF
383#define SSB_ANY_REV 0xFF 383#define SSB_ANY_REV 0xFF
384 384
385/* Broadcom's specific AMBA core, see drivers/bcma/ */
386struct bcma_device_id {
387 __u16 manuf;
388 __u16 id;
389 __u8 rev;
390 __u8 class;
391};
392#define BCMA_CORE(_manuf, _id, _rev, _class) \
393 { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
394#define BCMA_CORETABLE_END \
395 { 0, },
396
397#define BCMA_ANY_MANUF 0xFFFF
398#define BCMA_ANY_ID 0xFFFF
399#define BCMA_ANY_REV 0xFF
400#define BCMA_ANY_CLASS 0xFF
401
385struct virtio_device_id { 402struct virtio_device_id {
386 __u32 device; 403 __u32 device;
387 __u32 vendor; 404 __u32 vendor;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 06:38:54 -0400