aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-10-13 11:25:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:43 -0500
commit56ae58333031bb0564c141f955d1e42276cade55 (patch)
treede1e272dbebb07f268b6d9bc1fd553279f517ac8 /include
parent4e3884fc83f40b5daabceeee3a428a8ebebbbe4a (diff)
[MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE
This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE. This patch tested on Cobalt Qube2. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/gt64120.h14
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h29
-rw-r--r--include/asm-mips/mach-cobalt/mach-gt64120.h28
3 files changed, 43 insertions, 28 deletions
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h
index 2edd171bb6cd..4bf8e28f8850 100644
--- a/include/asm-mips/gt64120.h
+++ b/include/asm-mips/gt64120.h
@@ -451,6 +451,13 @@
451#define GT_SDRAM_OPMODE_OP_MODE 3 451#define GT_SDRAM_OPMODE_OP_MODE 3
452#define GT_SDRAM_OPMODE_OP_CBR 4 452#define GT_SDRAM_OPMODE_OP_CBR 4
453 453
454#define GT_TC_CONTROL_ENTC0_SHF 0
455#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
456#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
457#define GT_TC_CONTROL_SELTC0_SHF 1
458#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
459#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
460
454 461
455#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 462#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
456#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 463#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
@@ -523,6 +530,13 @@
523#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 530#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
524#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 531#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
525 532
533#define GT_INTR_T0EXP_SHF 8
534#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
535#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
536#define GT_INTR_RETRYCTR0_SHF 20
537#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
538#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
539
526/* 540/*
527 * Misc 541 * Misc
528 */ 542 */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index b3c5ecbec03c..00b0fc68d5cb 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -67,34 +67,9 @@
67#define COBALT_BRD_ID_QUBE2 0x5 67#define COBALT_BRD_ID_QUBE2 0x5
68#define COBALT_BRD_ID_RAQ2 0x6 68#define COBALT_BRD_ID_RAQ2 0x6
69 69
70/*
71 * Galileo chipset access macros for the Cobalt. The base address for
72 * the GT64111 chip is 0x14000000
73 *
74 * Most of this really should go into a separate GT64111 header file.
75 */
76#define GT64111_IO_BASE 0x10000000UL
77#define GT64111_IO_END 0x11ffffffUL
78#define GT64111_MEM_BASE 0x12000000UL
79#define GT64111_MEM_END 0x13ffffffUL
80#define GT64111_BASE 0x14000000UL
81#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
82
83#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
84#define GALILEO_OUTL(val, port) \
85do { \
86 *(volatile unsigned int *) GALILEO_REG(port) = (val); \
87} while (0)
88
89#define GALILEO_INTR_T0EXP (1 << 8)
90#define GALILEO_INTR_RETRY_CTR (1 << 20)
91
92#define GALILEO_ENTC0 0x01
93#define GALILEO_SELTC0 0x02
94
95#define PCI_CFG_SET(devfn,where) \ 70#define PCI_CFG_SET(devfn,where) \
96 GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ 71 GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \
97 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) 72 (PCI_FUNC (devfn) << 8) | (where)))
98 73
99#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) 74#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
100# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ 75# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h
index 587fc4378f44..ae9c5523c7ef 100644
--- a/include/asm-mips/mach-cobalt/mach-gt64120.h
+++ b/include/asm-mips/mach-cobalt/mach-gt64120.h
@@ -1 +1,27 @@
1/* there's something here ... in the dark */ 1/*
2 * Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef _COBALT_MACH_GT64120_H
19#define _COBALT_MACH_GT64120_H
20
21/*
22 * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
23 */
24
25#define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
26
27#endif /* _COBALT_MACH_GT64120_H */