[PATCH] powerpc: merge align.c

This patch merges align.c, the result isn't quite what was in ppc64 nor
what was in ppc32 :) It should implement all the functionalities of both
though. Kumar, since you played with that in the past, I suppose you
have some test cases for verifying that it works properly before I dig
out the 601 machine ? :)

Since it's likely that I won't be able to test all scenario, code
inspection is much welcome.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 12 insertions, 10 deletions

diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 04e2726002cf..d1cfa3f515ea 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -90,6 +90,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
+#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 
 #ifdef __powerpc64__
 /* Add the 64b processor unique features in the top half of the word */
@@ -97,7 +98,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
 #define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
-#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000001000000000)
 #define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
 #define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
 #define CPU_FTR_CTRL                    ASM_CONST(0x0000008000000000)
@@ -113,7 +113,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_16M_PAGE                ASM_CONST(0x0)
 #define CPU_FTR_TLBIEL                  ASM_CONST(0x0)
 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x0)
-#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0)
 #define CPU_FTR_IABR                    ASM_CONST(0x0)
 #define CPU_FTR_MMCRA                   ASM_CONST(0x0)
 #define CPU_FTR_CTRL                    ASM_CONST(0x0)
@@ -273,18 +272,21 @@ enum {
         CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
         CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
-            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
         CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
-            CPU_FTR_MAYBE_CAN_NAP,
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
         CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
-        CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
-        CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
-        CPU_FTRS_E200 = CPU_FTR_USE_TB,
-        CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_NODSISRALIGN,
+        CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_NODSISRALIGN,
+        CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
+        CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_NODSISRALIGN,
         CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
-            CPU_FTR_BIG_PHYS,
-        CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
+            CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
+        CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
 #ifdef __powerpc64__
         CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,