Auto merge with /home/aegl/GIT/linus

180 files changed, 3457 insertions, 2963 deletions

diff --git a/include/asm-alpha/agp.h b/include/asm-alpha/agp.h
index c99dbbb5bcb5..ef855a3bc0f5 100644
--- a/include/asm-alpha/agp.h
+++ b/include/asm-alpha/agp.h
@@ -10,4 +10,14 @@
 #define flush_agp_mappings() 
 #define flush_agp_cache() mb()
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif
diff --git a/include/asm-alpha/signal.h b/include/asm-alpha/signal.h
index 4e0842b415aa..1a2c52a056fb 100644
--- a/include/asm-alpha/signal.h
+++ b/include/asm-alpha/signal.h
@@ -113,16 +113,7 @@ typedef unsigned long sigset_t;
 #define SIG_UNBLOCK        2    /* for unblocking signals */
 #define SIG_SETMASK        3    /* for setting the signal mask */
 
-/* Type of a signal handler.  */
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct osf_sigaction {
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index f32c203952cf..93b840e8fa60 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -228,6 +228,30 @@
 #define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
 
 /*
+ * PWM controller
+ */
+#define PWMC    __REG(IMX_PWM_BASE + 0x00)      /* PWM Control Register         */
+#define PWMS    __REG(IMX_PWM_BASE + 0x04)      /* PWM Sample Register          */
+#define PWMP    __REG(IMX_PWM_BASE + 0x08)      /* PWM Period Register          */
+#define PWMCNT  __REG(IMX_PWM_BASE + 0x0C)      /* PWM Counter Register         */
+
+#define PWMC_HCTR               (0x01<<18)              /* Halfword FIFO Data Swapping  */
+#define PWMC_BCTR               (0x01<<17)              /* Byte FIFO Data Swapping      */
+#define PWMC_SWR                (0x01<<16)              /* Software Reset               */
+#define PWMC_CLKSRC             (0x01<<15)              /* Clock Source                 */
+#define PWMC_PRESCALER(x)       (((x-1) & 0x7F) << 8)   /* PRESCALER                    */
+#define PWMC_IRQ                (0x01<< 7)              /* Interrupt Request            */
+#define PWMC_IRQEN              (0x01<< 6)              /* Interrupt Request Enable     */
+#define PWMC_FIFOAV             (0x01<< 5)              /* FIFO Available               */
+#define PWMC_EN                 (0x01<< 4)              /* Enables/Disables the PWM     */
+#define PWMC_REPEAT(x)          (((x) & 0x03) << 2)     /* Sample Repeats               */
+#define PWMC_CLKSEL(x)          (((x) & 0x03) << 0)     /* Clock Selection              */
+
+#define PWMS_SAMPLE(x)          ((x) & 0xFFFF)          /* Contains a two-sample word   */
+#define PWMP_PERIOD(x)          ((x) & 0xFFFF)          /* Represents the PWM's period  */
+#define PWMC_COUNTER(x)         ((x) & 0xFFFF)          /* Represents the current count value   */
+
+/*
  *  DMA Controller
  */
 #define DCR     __REG(IMX_DMAC_BASE +0x00)      /* DMA Control Register */
diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h
new file mode 100644
index 000000000000..2346d454ab9c
--- /dev/null
+++ b/include/asm-arm/arch-imx/imxfb.h
@@ -0,0 +1,35 @@
+/*
+ * This structure describes the machine which we are running on.
+ */
+struct imxfb_mach_info {
+        u_long          pixclock;
+
+        u_short         xres;
+        u_short         yres;
+
+        u_char          bpp;
+        u_char          hsync_len;
+        u_char          left_margin;
+        u_char          right_margin;
+
+        u_char          vsync_len;
+        u_char          upper_margin;
+        u_char          lower_margin;
+        u_char          sync;
+
+        u_int           cmap_greyscale:1,
+                        cmap_inverse:1,
+                        cmap_static:1,
+                        unused:29;
+
+        u_int           pcr;
+        u_int           pwmr;
+        u_int           lscr1;
+
+        u_char * fixed_screen_cpu;
+        dma_addr_t fixed_screen_dma;
+
+        void (*lcd_power)(int);
+        void (*backlight_power)(int);
+};
+void set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info);
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index a8e3c2daefd6..083462668e18 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -75,8 +75,8 @@ static inline void insw(u32 ptr, void *buf, int length)
          * Is this cycle meant for the CS8900?
          */
         if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
-                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
+                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
                 u8 *buf8 = (u8*)buf;
                 register u32 tmp32;
 
@@ -100,8 +100,8 @@ static inline void outsw(u32 ptr, void *buf, int length)
          * Is this cycle meant for the CS8900?
          */
         if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
-                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
+                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
                 register u32 tmp32;
                 u8 *buf8 = (u8*)buf;
                 do {
@@ -124,8 +124,8 @@ static inline u16 inw(u32 ptr)
          * Is this cycle meant for the CS8900?
          */
         if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
-                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
+                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
                 return (u16)(*port);  
         }
 
@@ -137,8 +137,8 @@ static inline void outw(u16 value, u32 ptr)
         register volatile u32 *port = (volatile u32 *)ptr;
 
         if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
-                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
+                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
                 *port = value;  
                 return;
         }
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 39741d3c9a34..b5e54a9e9fa7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1296,6 +1296,7 @@
 #define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
 #define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
 #define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
+#define GPIO113_I2S_SYSCLK      113     /* I2S System Clock (PXA27x) */
 #define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
 
 /* GPIO alternate function mode & direction */
@@ -1428,6 +1429,7 @@
 #define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
 #define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
 #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
 #define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_OUT)
 #define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h
index c443ac834698..7cff235e667a 100644
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ b/include/asm-arm/arch-s3c2410/regs-nand.h
@@ -1,16 +1,17 @@
 /* linux/include/asm-arm/arch-s3c2410/regs-nand.h
  *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * S3C2410 clock register definitions
+ * S3C2410 NAND register definitions
  *
  *  Changelog:
  *    18-Aug-2004    BJD     Copied file from 2.4 and updated
+ *    01-May-2005    BJD     Added definitions for s3c2440 controller
 */
 
 #ifndef __ASM_ARM_REGS_NAND
@@ -26,6 +27,22 @@
 #define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
 #define S3C2410_NFECC   S3C2410_NFREG(0x14)
 
+#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
+#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
+#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
+#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
+#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
+#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
+#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
+#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
+#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
+#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
+#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
+#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
+#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
+#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
+#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
+
 #define S3C2410_NFCONF_EN          (1<<15)
 #define S3C2410_NFCONF_512BYTE     (1<<14)
 #define S3C2410_NFCONF_4STEP       (1<<13)
@@ -37,7 +54,28 @@
 
 #define S3C2410_NFSTAT_BUSY        (1<<0)
 
-/* think ECC can only be 8bit read? */
+#define S3C2440_NFCONF_BUSWIDTH_8       (0<<0)
+#define S3C2440_NFCONF_BUSWIDTH_16      (1<<0)
+#define S3C2440_NFCONF_ADVFLASH         (1<<3)
+#define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
+#define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
+#define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
+
+#define S3C2440_NFCONT_LOCKTIGHT        (1<<13)
+#define S3C2440_NFCONT_SOFTLOCK         (1<<12)
+#define S3C2440_NFCONT_ILLEGALACC_EN    (1<<10)
+#define S3C2440_NFCONT_RNBINT_EN        (1<<9)
+#define S3C2440_NFCONT_RN_FALLING       (1<<8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK    (1<<6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK     (1<<5)
+#define S3C2440_NFCONT_INITECC          (1<<4)
+#define S3C2440_NFCONT_nFCE             (1<<1)
+#define S3C2440_NFCONT_ENABLE           (1<<0)
+
+#define S3C2440_NFSTAT_READY            (1<<0)
+#define S3C2440_NFSTAT_nCE              (1<<1)
+#define S3C2440_NFSTAT_RnB_CHANGE       (1<<2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS   (1<<3)
 
 #endif /* __ASM_ARM_REGS_NAND */
 
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index cbceacbe5afa..a1696ba238d3 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -38,9 +38,9 @@ typedef struct user_fp elf_fpregset_t;
  */
 #define ELF_CLASS       ELFCLASS32
 #ifdef __ARMEB__
-#define ELF_DATA        ELFDATA2MSB;
+#define ELF_DATA        ELFDATA2MSB
 #else
-#define ELF_DATA        ELFDATA2LSB;
+#define ELF_DATA        ELFDATA2LSB
 #endif
 #define ELF_ARCH        EM_ARM
 
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 4ca3a8e9348f..019c45d75730 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -114,19 +114,8 @@ extern void __cpu_copy_user_page(void *to, const void *from,
                                  unsigned long user);
 #endif
 
-#define clear_user_page(addr,vaddr,pg)                  \
-        do {                                            \
-                preempt_disable();                      \
-                __cpu_clear_user_page(addr, vaddr);     \
-                preempt_enable();                       \
-        } while (0)
-
-#define copy_user_page(to,from,vaddr,pg)                \
-        do {                                            \
-                preempt_disable();                      \
-                __cpu_copy_user_page(to, from, vaddr);  \
-                preempt_enable();                       \
-        } while (0)
+#define clear_user_page(addr,vaddr,pg)   __cpu_clear_user_page(addr, vaddr)
+#define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr)
 
 #define clear_page(page)        memzero((void *)(page), PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
@@ -171,6 +160,9 @@ typedef unsigned long pgprot_t;
 
 #endif /* STRICT_MM_TYPECHECKS */
 
+/* the upper-most page table pointer */
+extern pmd_t *top_pmd;
+
 /* Pure 2^n version of get_order */
 static inline int get_order(unsigned long size)
 {
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index 4a9845997a75..7d4118e09054 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -23,8 +23,6 @@
 #include <asm/procinfo.h>
 #include <asm/types.h>
 
-#define KERNEL_STACK_SIZE       PAGE_SIZE
-
 union debug_insn {
         u32     arm;
         u16     thumb;
@@ -87,8 +85,9 @@ unsigned long get_wchan(struct task_struct *p);
  */
 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 
-#define KSTK_EIP(tsk)   (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1019])
-#define KSTK_ESP(tsk)   (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1017])
+#define KSTK_REGS(tsk)  (((struct pt_regs *)(THREAD_START_SP + (unsigned long)(tsk)->thread_info)) - 1)
+#define KSTK_EIP(tsk)   KSTK_REGS(tsk)->ARM_pc
+#define KSTK_ESP(tsk)   KSTK_REGS(tsk)->ARM_sp
 
 /*
  * Prefetching support - only ARMv5.
diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h
index b860dc3c5dc7..46e69ae395af 100644
--- a/include/asm-arm/signal.h
+++ b/include/asm-arm/signal.h
@@ -117,20 +117,7 @@ typedef unsigned long sigset_t;
 #define SA_IRQNOMASK            0x08000000
 #endif
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index a61618fb433c..66c585c50cf9 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -14,6 +14,10 @@
 
 #include <asm/fpstate.h>
 
+#define THREAD_SIZE_ORDER       1
+#define THREAD_SIZE             8192
+#define THREAD_START_SP         (THREAD_SIZE - 8)
+
 #ifndef __ASSEMBLY__
 
 struct task_struct;
@@ -77,8 +81,6 @@ struct thread_info {
 #define init_thread_info        (init_thread_union.thread_info)
 #define init_stack              (init_thread_union.stack)
 
-#define THREAD_SIZE             8192
-
 /*
  * how to get the thread information struct from C
  */
diff --git a/include/asm-arm26/elf.h b/include/asm-arm26/elf.h
index 8b149474db24..5a47fdb3015d 100644
--- a/include/asm-arm26/elf.h
+++ b/include/asm-arm26/elf.h
@@ -36,7 +36,7 @@ typedef struct { void *null; } elf_fpregset_t;
  * These are used to set parameters in the core dumps.
  */
 #define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB;
+#define ELF_DATA        ELFDATA2LSB
 #define ELF_ARCH        EM_ARM
 
 #define USE_ELF_CORE_DUMP
diff --git a/include/asm-arm26/signal.h b/include/asm-arm26/signal.h
index a1aacefa6562..37ad25355591 100644
--- a/include/asm-arm26/signal.h
+++ b/include/asm-arm26/signal.h
@@ -117,16 +117,7 @@ typedef unsigned long sigset_t;
 #define SA_IRQNOMASK            0x08000000
 #endif
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
@@ -175,9 +166,6 @@ typedef struct sigaltstack {
 #include <asm/sigcontext.h>
 
 #define sigmask(sig)    (1UL << ((sig) - 1))
-//FIXME!!!
-//#define HAVE_ARCH_GET_SIGNAL_TO_DELIVER
-
 #endif
 
 
diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h
index 2330769ba55d..dfe039593a78 100644
--- a/include/asm-cris/signal.h
+++ b/include/asm-cris/signal.h
@@ -108,16 +108,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-frv/signal.h b/include/asm-frv/signal.h
index c930bb176875..d407bde57eca 100644
--- a/include/asm-frv/signal.h
+++ b/include/asm-frv/signal.h
@@ -107,16 +107,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 976ac29598b7..195ccdc069e6 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -8,6 +8,8 @@ extern char _data[], _sdata[], _edata[];
 extern char __bss_start[], __bss_stop[];
 extern char __init_begin[], __init_end[];
 extern char _sinittext[], _einittext[];
+extern char _sextratext[] __attribute__((weak));
+extern char _eextratext[] __attribute__((weak));
 extern char _end[];
 
 #endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/asm-generic/signal.h b/include/asm-generic/signal.h
new file mode 100644
index 000000000000..9418d6e9b8cd
--- /dev/null
+++ b/include/asm-generic/signal.h
@@ -0,0 +1,21 @@
+#ifndef SIG_BLOCK
+#define SIG_BLOCK          0    /* for blocking signals */
+#endif
+#ifndef SIG_UNBLOCK
+#define SIG_UNBLOCK        1    /* for unblocking signals */
+#endif
+#ifndef SIG_SETMASK
+#define SIG_SETMASK        2    /* for setting the signal mask */
+#endif
+
+#ifndef __ASSEMBLY__
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+
+typedef void __restorefn_t(void);
+typedef __restorefn_t __user *__sigrestore_t;
+
+#define SIG_DFL ((__force __sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__force __sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__force __sighandler_t)-1)    /* error return from signal */
+#endif
diff --git a/include/asm-h8300/kmap_types.h b/include/asm-h8300/kmap_types.h
index 82431edeb2a1..1ec8a3427120 100644
--- a/include/asm-h8300/kmap_types.h
+++ b/include/asm-h8300/kmap_types.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
+#ifndef _ASM_H8300_KMAP_TYPES_H
+#define _ASM_H8300_KMAP_TYPES_H
 
 enum km_type {
         KM_BOUNCE_READ,
@@ -13,6 +13,8 @@ enum km_type {
         KM_PTE1,
         KM_IRQ0,
         KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
         KM_TYPE_NR
 };
 
diff --git a/include/asm-h8300/mman.h b/include/asm-h8300/mman.h
index abe08856c84f..63f727a59850 100644
--- a/include/asm-h8300/mman.h
+++ b/include/asm-h8300/mman.h
@@ -4,6 +4,7 @@
 #define PROT_READ       0x1             /* page can be read */
 #define PROT_WRITE      0x2             /* page can be written */
 #define PROT_EXEC       0x4             /* page can be executed */
+#define PROT_SEM        0x8             /* page may be used for atomic ops */
 #define PROT_NONE       0x0             /* page can not be accessed */
 #define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
 #define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
@@ -19,6 +20,8 @@
 #define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
 #define MAP_LOCKED      0x2000          /* pages are locked */
 #define MAP_NORESERVE   0x4000          /* don't check for reservations */
+#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
 
 #define MS_ASYNC        1               /* sync memory asynchronously */
 #define MS_INVALIDATE   2               /* invalidate the caches */
diff --git a/include/asm-h8300/signal.h b/include/asm-h8300/signal.h
index ac3e01bd6396..8eccdc176163 100644
--- a/include/asm-h8300/signal.h
+++ b/include/asm-h8300/signal.h
@@ -107,16 +107,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-i386/agp.h b/include/asm-i386/agp.h
index a917ff50354f..b82f5f3ab887 100644
--- a/include/asm-i386/agp.h
+++ b/include/asm-i386/agp.h
@@ -21,4 +21,14 @@ int unmap_page_from_agp(struct page *page);
    worth it. Would need a page for it. */
 #define flush_agp_cache() asm volatile("wbinvd":::"memory")
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif
diff --git a/include/asm-i386/floppy.h b/include/asm-i386/floppy.h
index f4782284807a..79727afb94c9 100644
--- a/include/asm-i386/floppy.h
+++ b/include/asm-i386/floppy.h
@@ -257,7 +257,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
         return 0;
 }
 
-struct fd_routine_l {
+static struct fd_routine_l {
         int (*_request_dma)(unsigned int dmanr, const char * device_id);
         void (*_free_dma)(unsigned int dmanr);
         int (*_get_dma_residue)(unsigned int dummy);
diff --git a/include/asm-i386/linkage.h b/include/asm-i386/linkage.h
index af3d8571c5c7..f4a6ebac0247 100644
--- a/include/asm-i386/linkage.h
+++ b/include/asm-i386/linkage.h
@@ -5,9 +5,7 @@
 #define FASTCALL(x)     x __attribute__((regparm(3)))
 #define fastcall        __attribute__((regparm(3)))
 
-#ifdef CONFIG_REGPARM
-# define prevent_tail_call(ret) __asm__ ("" : "=r" (ret) : "0" (ret))
-#endif
+#define prevent_tail_call(ret) __asm__ ("" : "=r" (ret) : "0" (ret))
 
 #ifdef CONFIG_X86_ALIGNMENT_16
 #define __ALIGN .align 16,0x90
diff --git a/include/asm-i386/mach-numaq/mach_ipi.h b/include/asm-i386/mach-numaq/mach_ipi.h
index 1b46fd3f2ae3..c6044488e9e6 100644
--- a/include/asm-i386/mach-numaq/mach_ipi.h
+++ b/include/asm-i386/mach-numaq/mach_ipi.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_MACH_IPI_H
 #define __ASM_MACH_IPI_H
 
-inline void send_IPI_mask_sequence(cpumask_t, int vector);
+void send_IPI_mask_sequence(cpumask_t, int vector);
 
 static inline void send_IPI_mask(cpumask_t mask, int vector)
 {
diff --git a/include/asm-i386/module.h b/include/asm-i386/module.h
index 508865e26308..eb7f2b4234aa 100644
--- a/include/asm-i386/module.h
+++ b/include/asm-i386/module.h
@@ -52,8 +52,8 @@ struct mod_arch_specific
 #define MODULE_PROC_FAMILY "CYRIXIII "
 #elif defined CONFIG_MVIAC3_2
 #define MODULE_PROC_FAMILY "VIAC3-2 "
-#elif CONFIG_MGEODE
-#define MODULE_PROC_FAMILY "GEODE "
+#elif CONFIG_MGEODEGX1
+#define MODULE_PROC_FAMILY "GEODEGX1 "
 #else
 #error unknown processor family
 #endif
diff --git a/include/asm-i386/signal.h b/include/asm-i386/signal.h
index 0f082bd1c455..cbb47d34aa31 100644
--- a/include/asm-i386/signal.h
+++ b/include/asm-i386/signal.h
@@ -110,20 +110,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-i386/timer.h b/include/asm-i386/timer.h
index 40c54f69780e..c34709849839 100644
--- a/include/asm-i386/timer.h
+++ b/include/asm-i386/timer.h
@@ -53,6 +53,7 @@ extern struct init_timer_opts timer_cyclone_init;
 
 extern unsigned long calibrate_tsc(void);
 extern void init_cpu_khz(void);
+extern int recalibrate_cpu_khz(void);
 #ifdef CONFIG_HPET_TIMER
 extern struct init_timer_opts timer_hpet_init;
 extern unsigned long calibrate_tsc_hpet(unsigned long *tsc_hpet_quotient_ptr);
diff --git a/include/asm-ia64/agp.h b/include/asm-ia64/agp.h
index d1316f1e6ee1..4e517f0e6afa 100644
--- a/include/asm-ia64/agp.h
+++ b/include/asm-ia64/agp.h
@@ -18,4 +18,14 @@
 #define flush_agp_mappings()            /* nothing */
 #define flush_agp_cache()               mb()
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif /* _ASM_IA64_AGP_H */
diff --git a/include/asm-ia64/ioctl32.h b/include/asm-ia64/ioctl32.h
deleted file mode 100644
index d0d227f45e05..000000000000
--- a/include/asm-ia64/ioctl32.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/ioctl32.h>
diff --git a/include/asm-ia64/perfmon.h b/include/asm-ia64/perfmon.h
index ed5416c5b1ac..7f3333dd00e4 100644
--- a/include/asm-ia64/perfmon.h
+++ b/include/asm-ia64/perfmon.h
@@ -177,6 +177,10 @@ typedef union {
 
 extern long perfmonctl(int fd, int cmd, void *arg, int narg);
 
+typedef struct {
+        void (*handler)(int irq, void *arg, struct pt_regs *regs);
+} pfm_intr_handler_desc_t;
+
 extern void pfm_save_regs (struct task_struct *);
 extern void pfm_load_regs (struct task_struct *);
 
@@ -187,6 +191,10 @@ extern void pfm_syst_wide_update_task(struct task_struct *, unsigned long info,
 extern void pfm_inherit(struct task_struct *task, struct pt_regs *regs);
 extern void pfm_init_percpu(void);
 extern void pfm_handle_work(void);
+extern int  pfm_install_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
+extern int  pfm_remove_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
+
+
 
 /*
  * Reset PMD register flags
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index ea121a002309..fcc9c3344ab4 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -8,7 +8,7 @@
  * This hopefully works with any (fixed) IA-64 page-size, as defined
  * in <asm/page.h>.
  *
- * Copyright (C) 1998-2004 Hewlett-Packard Co
+ * Copyright (C) 1998-2005 Hewlett-Packard Co
  *      David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
@@ -551,7 +551,11 @@ do {											\
 
 /* These tell get_user_pages() that the first gate page is accessible from user-level.  */
 #define FIXADDR_USER_START      GATE_ADDR
-#define FIXADDR_USER_END        (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
+#ifdef HAVE_BUGGY_SEGREL
+# define FIXADDR_USER_END       (GATE_ADDR + 2*PAGE_SIZE)
+#else
+# define FIXADDR_USER_END       (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
+#endif
 
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 9e1ba8b7fb68..91bbd1f22461 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -403,7 +403,10 @@ extern void ia64_setreg_unknown_kr (void);
  * task_struct at this point.
  */
 
-/* Return TRUE if task T owns the fph partition of the CPU we're running on. */
+/*
+ * Return TRUE if task T owns the fph partition of the CPU we're running on.
+ * Must be called from code that has preemption disabled.
+ */
 #define ia64_is_local_fpu_owner(t)                                                              \
 ({                                                                                              \
         struct task_struct *__ia64_islfo_task = (t);                                            \
@@ -411,7 +414,10 @@ extern void ia64_setreg_unknown_kr (void);
          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
 })
 
-/* Mark task T as owning the fph partition of the CPU we're running on. */
+/*
+ * Mark task T as owning the fph partition of the CPU we're running on.
+ * Must be called from code that has preemption disabled.
+ */
 #define ia64_set_local_fpu_owner(t) do {                                                \
         struct task_struct *__ia64_slfo_task = (t);                                     \
         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
diff --git a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h
index 85a577ae9146..608168d713d3 100644
--- a/include/asm-ia64/signal.h
+++ b/include/asm-ia64/signal.h
@@ -118,13 +118,7 @@
 
 #endif /* __KERNEL__ */
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 # ifndef __ASSEMBLY__
 
@@ -133,9 +127,6 @@
 /* Avoid too many header ordering problems.  */
 struct siginfo;
 
-/* Type of a signal handler.  */
-typedef void __user (*__sighandler_t)(int);
-
 typedef struct sigaltstack {
         void __user *ss_sp;
         int ss_flags;
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 960d626ee589..1bfdfb4d7b01 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -136,6 +136,7 @@
  */
 #define CAC_BASE                (CACHED   | AS_CAC_SPACE)
 #define AMO_BASE                (UNCACHED | AS_AMO_SPACE)
+#define AMO_PHYS_BASE           (UNCACHED_PHYS | AS_AMO_SPACE)
 #define GET_BASE                (CACHED   | AS_GET_SPACE)
 
 /*
@@ -161,6 +162,13 @@
 
 
 /*
+ * Macros to test for address type.
+ */
+#define IS_AMO_ADDRESS(x)       (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE)
+#define IS_AMO_PHYS_ADDRESS(x)  (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE)
+
+
+/*
  * The following definitions pertain to the IO special address
  * space.  They define the location of the big and little windows
  * of any given node.
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
index 7c349f07916a..635fdce854a8 100644
--- a/include/asm-ia64/sn/arch.h
+++ b/include/asm-ia64/sn/arch.h
@@ -5,7 +5,7 @@
  *
  * SGI specific setup.
  *
- * Copyright (C) 1995-1997,1999,2001-2004 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc.  All rights reserved.
  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
  */
 #ifndef _ASM_IA64_SN_ARCH_H
@@ -47,6 +47,21 @@ DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
 #define MAX_COMPACT_NODES       2048
 #define CPUS_PER_NODE           4
 
+
+/*
+ * Compact node ID to nasid mappings kept in the per-cpu data areas of each
+ * cpu.
+ */
+DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]);
+#define sn_cnodeid_to_nasid     (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
+
+
+
+extern u8 sn_partition_id;
+extern u8 sn_system_size;
+extern u8 sn_sharing_domain_size;
+extern u8 sn_region_size;
+
 extern void sn_flush_all_caches(long addr, long bytes);
 
 #endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h
deleted file mode 100644
index 5f4ad8f4b5d2..000000000000
--- a/include/asm-ia64/sn/fetchop.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_FETCHOP_H
-#define _ASM_IA64_SN_FETCHOP_H
-
-#include <linux/config.h>
-
-#define FETCHOP_BASENAME        "sgi_fetchop"
-#define FETCHOP_FULLNAME        "/dev/sgi_fetchop"
-
-
-
-#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
-
-#define FETCHOP_LOAD            0
-#define FETCHOP_INCREMENT       8
-#define FETCHOP_DECREMENT       16
-#define FETCHOP_CLEAR           24
-
-#define FETCHOP_STORE           0
-#define FETCHOP_AND             24
-#define FETCHOP_OR              32
-
-#define FETCHOP_CLEAR_CACHE     56
-
-#define FETCHOP_LOAD_OP(addr, op) ( \
-         *(volatile long *)((char*) (addr) + (op)))
-
-#define FETCHOP_STORE_OP(addr, op, x) ( \
-         *(volatile long *)((char*) (addr) + (op)) = (long) (x))
-
-#ifdef __KERNEL__
-
-/*
- * Convert a region 6 (kaddr) address to the address of the fetchop variable
- */
-#define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr)      TO_MSPEC(kaddr)
-
-
-/*
- * Each Atomic Memory Operation (AMO formerly known as fetchop)
- * variable is 64 bytes long.  The first 8 bytes are used.  The
- * remaining 56 bytes are unaddressable due to the operation taking
- * that portion of the address.
- * 
- * NOTE: The AMO_t _MUST_ be placed in either the first or second half
- * of the cache line.  The cache line _MUST NOT_ be used for anything
- * other than additional AMO_t entries.  This is because there are two
- * addresses which reference the same physical cache line.  One will
- * be a cached entry with the memory type bits all set.  This address
- * may be loaded into processor cache.  The AMO_t will be referenced
- * uncached via the memory special memory type.  If any portion of the
- * cached cache-line is modified, when that line is flushed, it will
- * overwrite the uncached value in physical memory and lead to
- * inconsistency.
- */
-typedef struct {
-        u64 variable;
-        u64 unused[7];
-} AMO_t;
-
-
-/*
- * The following APIs are externalized to the kernel to allocate/free pages of
- * fetchop variables.
- *      fetchop_kalloc_page     - Allocate/initialize 1 fetchop page on the
- *                                specified cnode. 
- *      fetchop_kfree_page      - Free a previously allocated fetchop page
- */
-
-unsigned long fetchop_kalloc_page(int nid);
-void fetchop_kfree_page(unsigned long maddr);
-
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IA64_SN_FETCHOP_H */
-
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index d5dbd55e44b5..08050d37b662 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -29,8 +29,9 @@
 #define L1_BRICKTYPE_CHI_CG     0x76            /* v */
 #define L1_BRICKTYPE_X          0x78            /* x */
 #define L1_BRICKTYPE_X2         0x79            /* y */
-#define L1_BRICKTYPE_SA         0x5e            /* ^ */ /* TIO bringup brick */
+#define L1_BRICKTYPE_SA         0x5e            /* ^ */
 #define L1_BRICKTYPE_PA         0x6a            /* j */
 #define L1_BRICKTYPE_IA         0x6b            /* k */
+#define L1_BRICKTYPE_ATHENA     0x2b            /* + */
 
 #endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 13cc1002b294..7138b1eafd6b 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -13,7 +13,6 @@
 #include <asm/irq.h>
 #include <asm/sn/arch.h>
 #include <asm/sn/intr.h>
-#include <asm/sn/pda.h>
 #include <asm/sn/bte.h>
 
 /*
@@ -67,20 +66,18 @@ typedef struct nodepda_s nodepda_t;
  * The next set of definitions provides this.
  * Routines are expected to use 
  *
- *      nodepda                 -> to access node PDA for the node on which code is running
- *      subnodepda              -> to access subnode PDA for the subnode on which code is running
- *
- *      NODEPDA(cnode)          -> to access node PDA for cnodeid 
- *      SUBNODEPDA(cnode,sn)    -> to access subnode PDA for cnodeid/subnode
+ *      sn_nodepda   - to access node PDA for the node on which code is running
+ *      NODEPDA(cnodeid)   - to access node PDA for cnodeid
  */
 
-#define nodepda         pda->p_nodepda          /* Ptr to this node's PDA */
-#define NODEPDA(cnode)          (nodepda->pernode_pdaindr[cnode])
+DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
+#define sn_nodepda              (__get_cpu_var(__sn_nodepda))
+#define NODEPDA(cnodeid)        (sn_nodepda->pernode_pdaindr[cnodeid])
 
 /*
  * Check if given a compact node id the corresponding node has all the
  * cpus disabled. 
  */
-#define is_headless_node(cnode)         (nr_cpus_node(cnode) == 0)
+#define is_headless_node(cnodeid)       (nr_cpus_node(cnodeid) == 0)
 
 #endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
index cd19f17bf91a..ea5590c76ca4 100644
--- a/include/asm-ia64/sn/pda.h
+++ b/include/asm-ia64/sn/pda.h
@@ -24,14 +24,6 @@
 
 typedef struct pda_s {
 
-        /* Having a pointer in the begining of PDA tends to increase
-         * the chance of having this pointer in cache. (Yes something
-         * else gets pushed out). Doing this reduces the number of memory
-         * access to all nodepda variables to be one
-         */
-        struct nodepda_s *p_nodepda;            /* Pointer to Per node PDA */
-        struct subnodepda_s *p_subnodepda;      /* Pointer to CPU  subnode PDA */
-
         /*
          * Support for SN LEDs
          */
@@ -49,7 +41,6 @@ typedef struct pda_s {
 
         unsigned long   sn_soft_irr[4];
         unsigned long   sn_in_service_ivecs[4];
-        short           cnodeid_to_nasid_table[MAX_NUMNODES];
         int             sn_lb_int_war_ticks;
         int             sn_last_irq;
         int             sn_first_irq;
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 2f885088e095..323fa0cd8d83 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -385,6 +385,17 @@
 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 
 /* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#define SH1_IPI_ACCESS                           0x0000000110060480
+#define SH2_IPI_ACCESS0                          0x0000000010060c00
+#define SH2_IPI_ACCESS1                          0x0000000010060c80
+#define SH2_IPI_ACCESS2                          0x0000000010060d00
+#define SH2_IPI_ACCESS3                          0x0000000010060d80
+
+/* ==================================================================== */
 /*                        Register "SH_INT_CMPB"                        */
 /*                  RTC Compare Value for Processor B                   */
 /* ==================================================================== */
@@ -429,6 +440,19 @@
 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH1_MD_DQLP_MMR_DIR_PRIVEC0              0x0000000100030300
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH1_MD_DQRP_MMR_DIR_PRIVEC0              0x0000000100050300
 
 /* ==================================================================== */
 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
index fbd880e6bb96..831b72111fdc 100644
--- a/include/asm-ia64/sn/shubio.h
+++ b/include/asm-ia64/sn/shubio.h
@@ -3,292 +3,287 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_IA64_SN_SHUBIO_H
 #define _ASM_IA64_SN_SHUBIO_H
 
-#define HUB_WIDGET_ID_MAX 0xf
-#define IIO_NUM_ITTES   7
-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
-
-#define    IIO_WID                   0x00400000    /* Crosstalk Widget Identification */
-                                                   /* This register is also accessible from
-                                                    * Crosstalk at address 0x0.  */
-#define    IIO_WSTAT                 0x00400008    /* Crosstalk Widget Status */
-#define    IIO_WCR                   0x00400020    /* Crosstalk Widget Control Register */
-#define    IIO_ILAPR                 0x00400100    /* IO Local Access Protection Register */
-#define    IIO_ILAPO                 0x00400108    /* IO Local Access Protection Override */
-#define    IIO_IOWA                  0x00400110    /* IO Outbound Widget Access */
-#define    IIO_IIWA                  0x00400118    /* IO Inbound Widget Access */
-#define    IIO_IIDEM                 0x00400120    /* IO Inbound Device Error Mask */
-#define    IIO_ILCSR                 0x00400128    /* IO LLP Control and Status Register */
-#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
-#define    IIO_IIDSR                 0x00400138    /* IO Interrupt Destination */
-
-#define    IIO_IGFX0                 0x00400140    /* IO Graphics Node-Widget Map 0 */
-#define    IIO_IGFX1                 0x00400148    /* IO Graphics Node-Widget Map 1 */
-
-#define    IIO_ISCR0                 0x00400150    /* IO Scratch Register 0 */
-#define    IIO_ISCR1                 0x00400158    /* IO Scratch Register 1 */
-
-#define    IIO_ITTE1                 0x00400160    /* IO Translation Table Entry 1 */
-#define    IIO_ITTE2                 0x00400168    /* IO Translation Table Entry 2 */
-#define    IIO_ITTE3                 0x00400170    /* IO Translation Table Entry 3 */
-#define    IIO_ITTE4                 0x00400178    /* IO Translation Table Entry 4 */
-#define    IIO_ITTE5                 0x00400180    /* IO Translation Table Entry 5 */
-#define    IIO_ITTE6                 0x00400188    /* IO Translation Table Entry 6 */
-#define    IIO_ITTE7                 0x00400190    /* IO Translation Table Entry 7 */
-
-#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
-#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
-#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
-#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
-#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
-#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
-#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
-#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
-#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
-
-#define    IIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */
-#define    IIO_IMEM                  0x004001E8    /* IO Miscellaneous Error Mask */
-#define    IIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout Threshold */
-#define    IIO_IECLR                 0x004001F8    /* IO Error Clear Register */
-#define    IIO_IBCR                  0x00400200    /* IO BTE Control Register */
-
-#define    IIO_IXSM                  0x00400208    /* IO Crosstalk Spurious Message */
-#define    IIO_IXSS                  0x00400210    /* IO Crosstalk Spurious Sideband */
-
-#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
-
-#define    IIO_IIEPH1                0x00400220    /* IO Incoming Error Packet Header, Part 1 */
-#define    IIO_IIEPH2                0x00400228    /* IO Incoming Error Packet Header, Part 2 */
-
-
-#define    IIO_ISLAPR                0x00400230    /* IO SXB Local Access Protection Regster */
-#define    IIO_ISLAPO                0x00400238    /* IO SXB Local Access Protection Override */
-
-#define    IIO_IWI                   0x00400240    /* IO Wrapper Interrupt Register */
-#define    IIO_IWEL                  0x00400248    /* IO Wrapper Error Log Register */
-#define    IIO_IWC                   0x00400250    /* IO Wrapper Control Register */
-#define    IIO_IWS                   0x00400258    /* IO Wrapper Status Register */
-#define    IIO_IWEIM                 0x00400260    /* IO Wrapper Error Interrupt Masking Register */
-
-#define    IIO_IPCA                  0x00400300    /* IO PRB Counter Adjust */
-
-#define    IIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Table Entry 0, Part A */
-#define    IIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Table Entry 1, Part A */
-#define    IIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Table Entry 2, Part A */
-#define    IIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Table Entry 3, Part A */
-#define    IIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Table Entry 4, Part A */
-#define    IIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Table Entry 5, Part A */
-#define    IIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Table Entry 6, Part A */
-#define    IIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Table Entry 7, Part A */
-
-#define    IIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Table Entry 0, Part B */
-#define    IIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Table Entry 1, Part B */
-#define    IIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Table Entry 2, Part B */
-#define    IIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Table Entry 3, Part B */
-#define    IIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Table Entry 4, Part B */
-#define    IIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Table Entry 5, Part B */
-#define    IIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Table Entry 6, Part B */
-#define    IIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Table Entry 7, Part B */
-
-#define    IIO_IPDR                  0x00400388    /* IO PIO Deallocation Register */
-#define    IIO_ICDR                  0x00400390    /* IO CRB Entry Deallocation Register */
-#define    IIO_IFDR                  0x00400398    /* IO IOQ FIFO Depth Register */
-#define    IIO_IIAP                  0x004003A0    /* IO IIQ Arbitration Parameters */
-#define    IIO_ICMR                  0x004003A8    /* IO CRB Management Register */
-#define    IIO_ICCR                  0x004003B0    /* IO CRB Control Register */
-#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
-#define    IIO_ICTP                  0x004003C0    /* IO CRB Timeout Prescalar */
-
-#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
-#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
-#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
-#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
-#define    IIO_ICRB0_E               0x00400420    /* IO CRB Entry 0_E       */
-
-#define    IIO_ICRB1_A               0x00400430    /* IO CRB Entry 1_A       */
-#define    IIO_ICRB1_B               0x00400438    /* IO CRB Entry 1_B       */
-#define    IIO_ICRB1_C               0x00400440    /* IO CRB Entry 1_C       */
-#define    IIO_ICRB1_D               0x00400448    /* IO CRB Entry 1_D       */
-#define    IIO_ICRB1_E               0x00400450    /* IO CRB Entry 1_E       */
-
-#define    IIO_ICRB2_A               0x00400460    /* IO CRB Entry 2_A       */
-#define    IIO_ICRB2_B               0x00400468    /* IO CRB Entry 2_B       */
-#define    IIO_ICRB2_C               0x00400470    /* IO CRB Entry 2_C       */
-#define    IIO_ICRB2_D               0x00400478    /* IO CRB Entry 2_D       */
-#define    IIO_ICRB2_E               0x00400480    /* IO CRB Entry 2_E       */
-
-#define    IIO_ICRB3_A               0x00400490    /* IO CRB Entry 3_A       */
-#define    IIO_ICRB3_B               0x00400498    /* IO CRB Entry 3_B       */
-#define    IIO_ICRB3_C               0x004004a0    /* IO CRB Entry 3_C       */
-#define    IIO_ICRB3_D               0x004004a8    /* IO CRB Entry 3_D       */
-#define    IIO_ICRB3_E               0x004004b0    /* IO CRB Entry 3_E       */
-
-#define    IIO_ICRB4_A               0x004004c0    /* IO CRB Entry 4_A       */
-#define    IIO_ICRB4_B               0x004004c8    /* IO CRB Entry 4_B       */
-#define    IIO_ICRB4_C               0x004004d0    /* IO CRB Entry 4_C       */
-#define    IIO_ICRB4_D               0x004004d8    /* IO CRB Entry 4_D       */
-#define    IIO_ICRB4_E               0x004004e0    /* IO CRB Entry 4_E       */
-
-#define    IIO_ICRB5_A               0x004004f0    /* IO CRB Entry 5_A       */
-#define    IIO_ICRB5_B               0x004004f8    /* IO CRB Entry 5_B       */
-#define    IIO_ICRB5_C               0x00400500    /* IO CRB Entry 5_C       */
-#define    IIO_ICRB5_D               0x00400508    /* IO CRB Entry 5_D       */
-#define    IIO_ICRB5_E               0x00400510    /* IO CRB Entry 5_E       */
-
-#define    IIO_ICRB6_A               0x00400520    /* IO CRB Entry 6_A       */
-#define    IIO_ICRB6_B               0x00400528    /* IO CRB Entry 6_B       */
-#define    IIO_ICRB6_C               0x00400530    /* IO CRB Entry 6_C       */
-#define    IIO_ICRB6_D               0x00400538    /* IO CRB Entry 6_D       */
-#define    IIO_ICRB6_E               0x00400540    /* IO CRB Entry 6_E       */
-
-#define    IIO_ICRB7_A               0x00400550    /* IO CRB Entry 7_A       */
-#define    IIO_ICRB7_B               0x00400558    /* IO CRB Entry 7_B       */
-#define    IIO_ICRB7_C               0x00400560    /* IO CRB Entry 7_C       */
-#define    IIO_ICRB7_D               0x00400568    /* IO CRB Entry 7_D       */
-#define    IIO_ICRB7_E               0x00400570    /* IO CRB Entry 7_E       */
-
-#define    IIO_ICRB8_A               0x00400580    /* IO CRB Entry 8_A       */
-#define    IIO_ICRB8_B               0x00400588    /* IO CRB Entry 8_B       */
-#define    IIO_ICRB8_C               0x00400590    /* IO CRB Entry 8_C       */
-#define    IIO_ICRB8_D               0x00400598    /* IO CRB Entry 8_D       */
-#define    IIO_ICRB8_E               0x004005a0    /* IO CRB Entry 8_E       */
-
-#define    IIO_ICRB9_A               0x004005b0    /* IO CRB Entry 9_A       */
-#define    IIO_ICRB9_B               0x004005b8    /* IO CRB Entry 9_B       */
-#define    IIO_ICRB9_C               0x004005c0    /* IO CRB Entry 9_C       */
-#define    IIO_ICRB9_D               0x004005c8    /* IO CRB Entry 9_D       */
-#define    IIO_ICRB9_E               0x004005d0    /* IO CRB Entry 9_E       */
-
-#define    IIO_ICRBA_A               0x004005e0    /* IO CRB Entry A_A       */
-#define    IIO_ICRBA_B               0x004005e8    /* IO CRB Entry A_B       */
-#define    IIO_ICRBA_C               0x004005f0    /* IO CRB Entry A_C       */
-#define    IIO_ICRBA_D               0x004005f8    /* IO CRB Entry A_D       */
-#define    IIO_ICRBA_E               0x00400600    /* IO CRB Entry A_E       */
-
-#define    IIO_ICRBB_A               0x00400610    /* IO CRB Entry B_A       */
-#define    IIO_ICRBB_B               0x00400618    /* IO CRB Entry B_B       */
-#define    IIO_ICRBB_C               0x00400620    /* IO CRB Entry B_C       */
-#define    IIO_ICRBB_D               0x00400628    /* IO CRB Entry B_D       */
-#define    IIO_ICRBB_E               0x00400630    /* IO CRB Entry B_E       */
-
-#define    IIO_ICRBC_A               0x00400640    /* IO CRB Entry C_A       */
-#define    IIO_ICRBC_B               0x00400648    /* IO CRB Entry C_B       */
-#define    IIO_ICRBC_C               0x00400650    /* IO CRB Entry C_C       */
-#define    IIO_ICRBC_D               0x00400658    /* IO CRB Entry C_D       */
-#define    IIO_ICRBC_E               0x00400660    /* IO CRB Entry C_E       */
-
-#define    IIO_ICRBD_A               0x00400670    /* IO CRB Entry D_A       */
-#define    IIO_ICRBD_B               0x00400678    /* IO CRB Entry D_B       */
-#define    IIO_ICRBD_C               0x00400680    /* IO CRB Entry D_C       */
-#define    IIO_ICRBD_D               0x00400688    /* IO CRB Entry D_D       */
-#define    IIO_ICRBD_E               0x00400690    /* IO CRB Entry D_E       */
-
-#define    IIO_ICRBE_A               0x004006a0    /* IO CRB Entry E_A       */
-#define    IIO_ICRBE_B               0x004006a8    /* IO CRB Entry E_B       */
-#define    IIO_ICRBE_C               0x004006b0    /* IO CRB Entry E_C       */
-#define    IIO_ICRBE_D               0x004006b8    /* IO CRB Entry E_D       */
-#define    IIO_ICRBE_E               0x004006c0    /* IO CRB Entry E_E       */
-
-#define    IIO_ICSML                 0x00400700    /* IO CRB Spurious Message Low */
-#define    IIO_ICSMM                 0x00400708    /* IO CRB Spurious Message Middle */
-#define    IIO_ICSMH                 0x00400710    /* IO CRB Spurious Message High */
-
-#define    IIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */
-
-#define    IIO_IBLS0                 0x00410000    /* IO BTE Length Status 0 */
-#define    IIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */
-#define    IIO_IBDA0                 0x00410010    /* IO BTE Destination Address 0 */
-#define    IIO_IBCT0                 0x00410018    /* IO BTE Control Terminate 0 */
-#define    IIO_IBNA0                 0x00410020    /* IO BTE Notification Address 0 */
-#define    IIO_IBIA0                 0x00410028    /* IO BTE Interrupt Address 0 */
-#define    IIO_IBLS1                 0x00420000    /* IO BTE Length Status 1 */
-#define    IIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */
-#define    IIO_IBDA1                 0x00420010    /* IO BTE Destination Address 1 */
-#define    IIO_IBCT1                 0x00420018    /* IO BTE Control Terminate 1 */
-#define    IIO_IBNA1                 0x00420020    /* IO BTE Notification Address 1 */
-#define    IIO_IBIA1                 0x00420028    /* IO BTE Interrupt Address 1 */
-
-#define    IIO_IPCR                  0x00430000    /* IO Performance Control */
-#define    IIO_IPPR                  0x00430008    /* IO Performance Profiling */
-
-
-/************************************************************************
- *                                                                      *
+#define HUB_WIDGET_ID_MAX       0xf
+#define IIO_NUM_ITTES           7
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+#define         IIO_WID                 0x00400000      /* Crosstalk Widget Identification */
+                                                        /* This register is also accessible from
+                                                         * Crosstalk at address 0x0.  */
+#define         IIO_WSTAT               0x00400008      /* Crosstalk Widget Status */
+#define         IIO_WCR                 0x00400020      /* Crosstalk Widget Control Register */
+#define         IIO_ILAPR               0x00400100      /* IO Local Access Protection Register */
+#define         IIO_ILAPO               0x00400108      /* IO Local Access Protection Override */
+#define         IIO_IOWA                0x00400110      /* IO Outbound Widget Access */
+#define         IIO_IIWA                0x00400118      /* IO Inbound Widget Access */
+#define         IIO_IIDEM               0x00400120      /* IO Inbound Device Error Mask */
+#define         IIO_ILCSR               0x00400128      /* IO LLP Control and Status Register */
+#define         IIO_ILLR                0x00400130      /* IO LLP Log Register    */
+#define         IIO_IIDSR               0x00400138      /* IO Interrupt Destination */
+
+#define         IIO_IGFX0               0x00400140      /* IO Graphics Node-Widget Map 0 */
+#define         IIO_IGFX1               0x00400148      /* IO Graphics Node-Widget Map 1 */
+
+#define         IIO_ISCR0               0x00400150      /* IO Scratch Register 0 */
+#define         IIO_ISCR1               0x00400158      /* IO Scratch Register 1 */
+
+#define         IIO_ITTE1               0x00400160      /* IO Translation Table Entry 1 */
+#define         IIO_ITTE2               0x00400168      /* IO Translation Table Entry 2 */
+#define         IIO_ITTE3               0x00400170      /* IO Translation Table Entry 3 */
+#define         IIO_ITTE4               0x00400178      /* IO Translation Table Entry 4 */
+#define         IIO_ITTE5               0x00400180      /* IO Translation Table Entry 5 */
+#define         IIO_ITTE6               0x00400188      /* IO Translation Table Entry 6 */
+#define         IIO_ITTE7               0x00400190      /* IO Translation Table Entry 7 */
+
+#define         IIO_IPRB0               0x00400198      /* IO PRB Entry 0   */
+#define         IIO_IPRB8               0x004001A0      /* IO PRB Entry 8   */
+#define         IIO_IPRB9               0x004001A8      /* IO PRB Entry 9   */
+#define         IIO_IPRBA               0x004001B0      /* IO PRB Entry A   */
+#define         IIO_IPRBB               0x004001B8      /* IO PRB Entry B   */
+#define         IIO_IPRBC               0x004001C0      /* IO PRB Entry C   */
+#define         IIO_IPRBD               0x004001C8      /* IO PRB Entry D   */
+#define         IIO_IPRBE               0x004001D0      /* IO PRB Entry E   */
+#define         IIO_IPRBF               0x004001D8      /* IO PRB Entry F   */
+
+#define         IIO_IXCC                0x004001E0      /* IO Crosstalk Credit Count Timeout */
+#define         IIO_IMEM                0x004001E8      /* IO Miscellaneous Error Mask */
+#define         IIO_IXTT                0x004001F0      /* IO Crosstalk Timeout Threshold */
+#define         IIO_IECLR               0x004001F8      /* IO Error Clear Register */
+#define         IIO_IBCR                0x00400200      /* IO BTE Control Register */
+
+#define         IIO_IXSM                0x00400208      /* IO Crosstalk Spurious Message */
+#define         IIO_IXSS                0x00400210      /* IO Crosstalk Spurious Sideband */
+
+#define         IIO_ILCT                0x00400218      /* IO LLP Channel Test    */
+
+#define         IIO_IIEPH1              0x00400220      /* IO Incoming Error Packet Header, Part 1 */
+#define         IIO_IIEPH2              0x00400228      /* IO Incoming Error Packet Header, Part 2 */
+
+#define         IIO_ISLAPR              0x00400230      /* IO SXB Local Access Protection Regster */
+#define         IIO_ISLAPO              0x00400238      /* IO SXB Local Access Protection Override */
+
+#define         IIO_IWI                 0x00400240      /* IO Wrapper Interrupt Register */
+#define         IIO_IWEL                0x00400248      /* IO Wrapper Error Log Register */
+#define         IIO_IWC                 0x00400250      /* IO Wrapper Control Register */
+#define         IIO_IWS                 0x00400258      /* IO Wrapper Status Register */
+#define         IIO_IWEIM               0x00400260      /* IO Wrapper Error Interrupt Masking Register */
+
+#define         IIO_IPCA                0x00400300      /* IO PRB Counter Adjust */
+
+#define         IIO_IPRTE0_A            0x00400308      /* IO PIO Read Address Table Entry 0, Part A */
+#define         IIO_IPRTE1_A            0x00400310      /* IO PIO Read Address Table Entry 1, Part A */
+#define         IIO_IPRTE2_A            0x00400318      /* IO PIO Read Address Table Entry 2, Part A */
+#define         IIO_IPRTE3_A            0x00400320      /* IO PIO Read Address Table Entry 3, Part A */
+#define         IIO_IPRTE4_A            0x00400328      /* IO PIO Read Address Table Entry 4, Part A */
+#define         IIO_IPRTE5_A            0x00400330      /* IO PIO Read Address Table Entry 5, Part A */
+#define         IIO_IPRTE6_A            0x00400338      /* IO PIO Read Address Table Entry 6, Part A */
+#define         IIO_IPRTE7_A            0x00400340      /* IO PIO Read Address Table Entry 7, Part A */
+
+#define         IIO_IPRTE0_B            0x00400348      /* IO PIO Read Address Table Entry 0, Part B */
+#define         IIO_IPRTE1_B            0x00400350      /* IO PIO Read Address Table Entry 1, Part B */
+#define         IIO_IPRTE2_B            0x00400358      /* IO PIO Read Address Table Entry 2, Part B */
+#define         IIO_IPRTE3_B            0x00400360      /* IO PIO Read Address Table Entry 3, Part B */
+#define         IIO_IPRTE4_B            0x00400368      /* IO PIO Read Address Table Entry 4, Part B */
+#define         IIO_IPRTE5_B            0x00400370      /* IO PIO Read Address Table Entry 5, Part B */
+#define         IIO_IPRTE6_B            0x00400378      /* IO PIO Read Address Table Entry 6, Part B */
+#define         IIO_IPRTE7_B            0x00400380      /* IO PIO Read Address Table Entry 7, Part B */
+
+#define         IIO_IPDR                0x00400388      /* IO PIO Deallocation Register */
+#define         IIO_ICDR                0x00400390      /* IO CRB Entry Deallocation Register */
+#define         IIO_IFDR                0x00400398      /* IO IOQ FIFO Depth Register */
+#define         IIO_IIAP                0x004003A0      /* IO IIQ Arbitration Parameters */
+#define         IIO_ICMR                0x004003A8      /* IO CRB Management Register */
+#define         IIO_ICCR                0x004003B0      /* IO CRB Control Register */
+#define         IIO_ICTO                0x004003B8      /* IO CRB Timeout   */
+#define         IIO_ICTP                0x004003C0      /* IO CRB Timeout Prescalar */
+
+#define         IIO_ICRB0_A             0x00400400      /* IO CRB Entry 0_A */
+#define         IIO_ICRB0_B             0x00400408      /* IO CRB Entry 0_B */
+#define         IIO_ICRB0_C             0x00400410      /* IO CRB Entry 0_C */
+#define         IIO_ICRB0_D             0x00400418      /* IO CRB Entry 0_D */
+#define         IIO_ICRB0_E             0x00400420      /* IO CRB Entry 0_E */
+
+#define         IIO_ICRB1_A             0x00400430      /* IO CRB Entry 1_A */
+#define         IIO_ICRB1_B             0x00400438      /* IO CRB Entry 1_B */
+#define         IIO_ICRB1_C             0x00400440      /* IO CRB Entry 1_C */
+#define         IIO_ICRB1_D             0x00400448      /* IO CRB Entry 1_D */
+#define         IIO_ICRB1_E             0x00400450      /* IO CRB Entry 1_E */
+
+#define         IIO_ICRB2_A             0x00400460      /* IO CRB Entry 2_A */
+#define         IIO_ICRB2_B             0x00400468      /* IO CRB Entry 2_B */
+#define         IIO_ICRB2_C             0x00400470      /* IO CRB Entry 2_C */
+#define         IIO_ICRB2_D             0x00400478      /* IO CRB Entry 2_D */
+#define         IIO_ICRB2_E             0x00400480      /* IO CRB Entry 2_E */
+
+#define         IIO_ICRB3_A             0x00400490      /* IO CRB Entry 3_A */
+#define         IIO_ICRB3_B             0x00400498      /* IO CRB Entry 3_B */
+#define         IIO_ICRB3_C             0x004004a0      /* IO CRB Entry 3_C */
+#define         IIO_ICRB3_D             0x004004a8      /* IO CRB Entry 3_D */
+#define         IIO_ICRB3_E             0x004004b0      /* IO CRB Entry 3_E */
+
+#define         IIO_ICRB4_A             0x004004c0      /* IO CRB Entry 4_A */
+#define         IIO_ICRB4_B             0x004004c8      /* IO CRB Entry 4_B */
+#define         IIO_ICRB4_C             0x004004d0      /* IO CRB Entry 4_C */
+#define         IIO_ICRB4_D             0x004004d8      /* IO CRB Entry 4_D */
+#define         IIO_ICRB4_E             0x004004e0      /* IO CRB Entry 4_E */
+
+#define         IIO_ICRB5_A             0x004004f0      /* IO CRB Entry 5_A */
+#define         IIO_ICRB5_B             0x004004f8      /* IO CRB Entry 5_B */
+#define         IIO_ICRB5_C             0x00400500      /* IO CRB Entry 5_C */
+#define         IIO_ICRB5_D             0x00400508      /* IO CRB Entry 5_D */
+#define         IIO_ICRB5_E             0x00400510      /* IO CRB Entry 5_E */
+
+#define         IIO_ICRB6_A             0x00400520      /* IO CRB Entry 6_A */
+#define         IIO_ICRB6_B             0x00400528      /* IO CRB Entry 6_B */
+#define         IIO_ICRB6_C             0x00400530      /* IO CRB Entry 6_C */
+#define         IIO_ICRB6_D             0x00400538      /* IO CRB Entry 6_D */
+#define         IIO_ICRB6_E             0x00400540      /* IO CRB Entry 6_E */
+
+#define         IIO_ICRB7_A             0x00400550      /* IO CRB Entry 7_A */
+#define         IIO_ICRB7_B             0x00400558      /* IO CRB Entry 7_B */
+#define         IIO_ICRB7_C             0x00400560      /* IO CRB Entry 7_C */
+#define         IIO_ICRB7_D             0x00400568      /* IO CRB Entry 7_D */
+#define         IIO_ICRB7_E             0x00400570      /* IO CRB Entry 7_E */
+
+#define         IIO_ICRB8_A             0x00400580      /* IO CRB Entry 8_A */
+#define         IIO_ICRB8_B             0x00400588      /* IO CRB Entry 8_B */
+#define         IIO_ICRB8_C             0x00400590      /* IO CRB Entry 8_C */
+#define         IIO_ICRB8_D             0x00400598      /* IO CRB Entry 8_D */
+#define         IIO_ICRB8_E             0x004005a0      /* IO CRB Entry 8_E */
+
+#define         IIO_ICRB9_A             0x004005b0      /* IO CRB Entry 9_A */
+#define         IIO_ICRB9_B             0x004005b8      /* IO CRB Entry 9_B */
+#define         IIO_ICRB9_C             0x004005c0      /* IO CRB Entry 9_C */
+#define         IIO_ICRB9_D             0x004005c8      /* IO CRB Entry 9_D */
+#define         IIO_ICRB9_E             0x004005d0      /* IO CRB Entry 9_E */
+
+#define         IIO_ICRBA_A             0x004005e0      /* IO CRB Entry A_A */
+#define         IIO_ICRBA_B             0x004005e8      /* IO CRB Entry A_B */
+#define         IIO_ICRBA_C             0x004005f0      /* IO CRB Entry A_C */
+#define         IIO_ICRBA_D             0x004005f8      /* IO CRB Entry A_D */
+#define         IIO_ICRBA_E             0x00400600      /* IO CRB Entry A_E */
+
+#define         IIO_ICRBB_A             0x00400610      /* IO CRB Entry B_A */
+#define         IIO_ICRBB_B             0x00400618      /* IO CRB Entry B_B */
+#define         IIO_ICRBB_C             0x00400620      /* IO CRB Entry B_C */
+#define         IIO_ICRBB_D             0x00400628      /* IO CRB Entry B_D */
+#define         IIO_ICRBB_E             0x00400630      /* IO CRB Entry B_E */
+
+#define         IIO_ICRBC_A             0x00400640      /* IO CRB Entry C_A */
+#define         IIO_ICRBC_B             0x00400648      /* IO CRB Entry C_B */
+#define         IIO_ICRBC_C             0x00400650      /* IO CRB Entry C_C */
+#define         IIO_ICRBC_D             0x00400658      /* IO CRB Entry C_D */
+#define         IIO_ICRBC_E             0x00400660      /* IO CRB Entry C_E */
+
+#define         IIO_ICRBD_A             0x00400670      /* IO CRB Entry D_A */
+#define         IIO_ICRBD_B             0x00400678      /* IO CRB Entry D_B */
+#define         IIO_ICRBD_C             0x00400680      /* IO CRB Entry D_C */
+#define         IIO_ICRBD_D             0x00400688      /* IO CRB Entry D_D */
+#define         IIO_ICRBD_E             0x00400690      /* IO CRB Entry D_E */
+
+#define         IIO_ICRBE_A             0x004006a0      /* IO CRB Entry E_A */
+#define         IIO_ICRBE_B             0x004006a8      /* IO CRB Entry E_B */
+#define         IIO_ICRBE_C             0x004006b0      /* IO CRB Entry E_C */
+#define         IIO_ICRBE_D             0x004006b8      /* IO CRB Entry E_D */
+#define         IIO_ICRBE_E             0x004006c0      /* IO CRB Entry E_E */
+
+#define         IIO_ICSML               0x00400700      /* IO CRB Spurious Message Low */
+#define         IIO_ICSMM               0x00400708      /* IO CRB Spurious Message Middle */
+#define         IIO_ICSMH               0x00400710      /* IO CRB Spurious Message High */
+
+#define         IIO_IDBSS               0x00400718      /* IO Debug Submenu Select */
+
+#define         IIO_IBLS0               0x00410000      /* IO BTE Length Status 0 */
+#define         IIO_IBSA0               0x00410008      /* IO BTE Source Address 0 */
+#define         IIO_IBDA0               0x00410010      /* IO BTE Destination Address 0 */
+#define         IIO_IBCT0               0x00410018      /* IO BTE Control Terminate 0 */
+#define         IIO_IBNA0               0x00410020      /* IO BTE Notification Address 0 */
+#define         IIO_IBIA0               0x00410028      /* IO BTE Interrupt Address 0 */
+#define         IIO_IBLS1               0x00420000      /* IO BTE Length Status 1 */
+#define         IIO_IBSA1               0x00420008      /* IO BTE Source Address 1 */
+#define         IIO_IBDA1               0x00420010      /* IO BTE Destination Address 1 */
+#define         IIO_IBCT1               0x00420018      /* IO BTE Control Terminate 1 */
+#define         IIO_IBNA1               0x00420020      /* IO BTE Notification Address 1 */
+#define         IIO_IBIA1               0x00420028      /* IO BTE Interrupt Address 1 */
+
+#define         IIO_IPCR                0x00430000      /* IO Performance Control */
+#define         IIO_IPPR                0x00430008      /* IO Performance Profiling */
+
+/************************************************************************
+ *                                                                      *
  * Description:  This register echoes some information from the         *
  * LB_REV_ID register. It is available through Crosstalk as described   *
  * above. The REV_NUM and MFG_NUM fields receive their values from      *
  * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
  * The PART_NUM field's value is the Crosstalk device ID number that    *
  * Steve Miller assigned to the SHub chip.                              *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_wid_u {
-        uint64_t        ii_wid_regval;
-        struct  {
-                uint64_t        w_rsvd_1                  :      1;
-                uint64_t        w_mfg_num                 :     11;
-                uint64_t        w_part_num                :     16;
-                uint64_t        w_rev_num                 :      4;
-                uint64_t        w_rsvd                    :     32;
+        uint64_t ii_wid_regval;
+        struct {
+                uint64_t w_rsvd_1:1;
+                uint64_t w_mfg_num:11;
+                uint64_t w_part_num:16;
+                uint64_t w_rev_num:4;
+                uint64_t w_rsvd:32;
         } ii_wid_fld_s;
 } ii_wid_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  The fields in this register are set upon detection of an error      *
  * and cleared by various mechanisms, as explained in the               *
  * description.                                                         *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_wstat_u {
-        uint64_t        ii_wstat_regval;
-        struct  {
-                uint64_t        w_pending                 :      4;
-                uint64_t        w_xt_crd_to               :      1;
-                uint64_t        w_xt_tail_to              :      1;
-                uint64_t        w_rsvd_3                  :      3;
-                uint64_t       w_tx_mx_rty               :      1;
-                uint64_t        w_rsvd_2                  :      6;
-                uint64_t        w_llp_tx_cnt              :      8;
-                uint64_t        w_rsvd_1                  :      8;
-                uint64_t        w_crazy                   :      1;
-                uint64_t        w_rsvd                    :     31;
+        uint64_t ii_wstat_regval;
+        struct {
+                uint64_t w_pending:4;
+                uint64_t w_xt_crd_to:1;
+                uint64_t w_xt_tail_to:1;
+                uint64_t w_rsvd_3:3;
+                uint64_t w_tx_mx_rty:1;
+                uint64_t w_rsvd_2:6;
+                uint64_t w_llp_tx_cnt:8;
+                uint64_t w_rsvd_1:8;
+                uint64_t w_crazy:1;
+                uint64_t w_rsvd:31;
         } ii_wstat_fld_s;
 } ii_wstat_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This is a read-write enabled register. It controls     *
  * various aspects of the Crosstalk flow control.                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_wcr_u {
-        uint64_t        ii_wcr_regval;
-        struct  {
-                uint64_t        w_wid                     :      4;
-                uint64_t        w_tag                     :      1;
-                uint64_t        w_rsvd_1                  :      8;
-                uint64_t        w_dst_crd                 :      3;
-                uint64_t        w_f_bad_pkt               :      1;
-                uint64_t        w_dir_con                 :      1;
-                uint64_t        w_e_thresh                :      5;
-                uint64_t        w_rsvd                    :     41;
+        uint64_t ii_wcr_regval;
+        struct {
+                uint64_t w_wid:4;
+                uint64_t w_tag:1;
+                uint64_t w_rsvd_1:8;
+                uint64_t w_dst_crd:3;
+                uint64_t w_f_bad_pkt:1;
+                uint64_t w_dir_con:1;
+                uint64_t w_e_thresh:5;
+                uint64_t w_rsvd:41;
         } ii_wcr_fld_s;
 } ii_wcr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register's value is a bit vector that guards      *
  * access to local registers within the II as well as to external       *
  * Crosstalk widgets. Each bit in the register corresponds to a         *
@@ -311,21 +306,18 @@ typedef union ii_wcr_u {
  * region ID bits are enabled in this same register. It can also be     *
  * accessed through the IAlias space by the local processors.           *
  * The reset value of this register allows access by all nodes.         *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ilapr_u {
-        uint64_t        ii_ilapr_regval;
-        struct  {
-                uint64_t        i_region                  :     64;
+        uint64_t ii_ilapr_regval;
+        struct {
+                uint64_t i_region:64;
         } ii_ilapr_fld_s;
 } ii_ilapr_u_t;
 
-
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  A write to this register of the 64-bit value           *
  * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
  * corresponding to the region of the requestor to be set (allow        *
@@ -334,59 +326,54 @@ typedef union ii_ilapr_u {
  * This register can also be accessed through the IAlias space.         *
  * However, this access will not change the access permissions in the   *
  * ILAPR.                                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ilapo_u {
-        uint64_t        ii_ilapo_regval;
-        struct  {
-                uint64_t        i_io_ovrride            :       64;
+        uint64_t ii_ilapo_regval;
+        struct {
+                uint64_t i_io_ovrride:64;
         } ii_ilapo_fld_s;
 } ii_ilapo_u_t;
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register qualifies all the PIO and Graphics writes launched    *
  * from the SHUB towards a widget.                                      *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iowa_u {
-        uint64_t        ii_iowa_regval;
-        struct  {
-                uint64_t        i_w0_oac                  :      1;
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t       i_wx_oac                  :      8;
-                uint64_t        i_rsvd                    :     48;
+        uint64_t ii_iowa_regval;
+        struct {
+                uint64_t i_w0_oac:1;
+                uint64_t i_rsvd_1:7;
+                uint64_t i_wx_oac:8;
+                uint64_t i_rsvd:48;
         } ii_iowa_fld_s;
 } ii_iowa_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register qualifies all the requests launched      *
  * from a widget towards the Shub. This register is intended to be      *
  * used by software in case of misbehaving widgets.                     *
- *                                                                      *
- *                                                                      *
+ *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iiwa_u {
-        uint64_t        ii_iiwa_regval;
-        struct  {
-                uint64_t        i_w0_iac                  :      1;
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_wx_iac                  :      8;
-                uint64_t        i_rsvd                    :     48;
+        uint64_t ii_iiwa_regval;
+        struct {
+                uint64_t i_w0_iac:1;
+                uint64_t i_rsvd_1:7;
+                uint64_t i_wx_iac:8;
+                uint64_t i_rsvd:48;
         } ii_iiwa_fld_s;
 } ii_iiwa_u_t;
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register qualifies all the operations launched    *
  * from a widget towards the SHub. It allows individual access          *
  * control for up to 8 devices per widget. A device refers to           *
@@ -401,72 +388,69 @@ typedef union ii_iiwa_u {
  * The bits in this field are set by writing a 1 to them. Incoming      *
  * replies from Crosstalk are not subject to this access control        *
  * mechanism.                                                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iidem_u {
-        uint64_t        ii_iidem_regval;
-        struct  {
-                uint64_t        i_w8_dxs                  :      8;
-                uint64_t        i_w9_dxs                  :      8;
-                uint64_t        i_wa_dxs                  :      8;
-                uint64_t        i_wb_dxs                  :      8;
-                uint64_t        i_wc_dxs                  :      8;
-                uint64_t        i_wd_dxs                  :      8;
-                uint64_t        i_we_dxs                  :      8;
-                uint64_t        i_wf_dxs                  :      8;
+        uint64_t ii_iidem_regval;
+        struct {
+                uint64_t i_w8_dxs:8;
+                uint64_t i_w9_dxs:8;
+                uint64_t i_wa_dxs:8;
+                uint64_t i_wb_dxs:8;
+                uint64_t i_wc_dxs:8;
+                uint64_t i_wd_dxs:8;
+                uint64_t i_we_dxs:8;
+                uint64_t i_wf_dxs:8;
         } ii_iidem_fld_s;
 } ii_iidem_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the various programmable fields necessary    *
  * for controlling and observing the LLP signals.                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ilcsr_u {
-        uint64_t        ii_ilcsr_regval;
-        struct  {
-                uint64_t        i_nullto                  :      6;
-                uint64_t        i_rsvd_4                  :      2;
-                uint64_t        i_wrmrst                  :      1;
-                uint64_t        i_rsvd_3                  :      1;
-                uint64_t        i_llp_en                  :      1;
-                uint64_t        i_bm8                     :      1;
-                uint64_t        i_llp_stat                :      2;
-                uint64_t        i_remote_power            :      1;
-                uint64_t        i_rsvd_2                  :      1;
-                uint64_t        i_maxrtry                 :     10;
-                uint64_t        i_d_avail_sel             :      2;
-                uint64_t        i_rsvd_1                  :      4;
-                uint64_t        i_maxbrst                 :     10;
-                uint64_t       i_rsvd                    :     22;
+        uint64_t ii_ilcsr_regval;
+        struct {
+                uint64_t i_nullto:6;
+                uint64_t i_rsvd_4:2;
+                uint64_t i_wrmrst:1;
+                uint64_t i_rsvd_3:1;
+                uint64_t i_llp_en:1;
+                uint64_t i_bm8:1;
+                uint64_t i_llp_stat:2;
+                uint64_t i_remote_power:1;
+                uint64_t i_rsvd_2:1;
+                uint64_t i_maxrtry:10;
+                uint64_t i_d_avail_sel:2;
+                uint64_t i_rsvd_1:4;
+                uint64_t i_maxbrst:10;
+                uint64_t i_rsvd:22;
 
         } ii_ilcsr_fld_s;
 } ii_ilcsr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This is simply a status registers that monitors the LLP error       *
- * rate.                                                                *
- *                                                                      *
+ * rate.                                                                *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_illr_u {
-        uint64_t        ii_illr_regval;
-        struct  {
-                uint64_t        i_sn_cnt                  :     16;
-                uint64_t        i_cb_cnt                  :     16;
-                uint64_t        i_rsvd                    :     32;
+        uint64_t ii_illr_regval;
+        struct {
+                uint64_t i_sn_cnt:16;
+                uint64_t i_cb_cnt:16;
+                uint64_t i_rsvd:32;
         } ii_illr_fld_s;
 } ii_illr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  All II-detected non-BTE error interrupts are           *
  * specified via this register.                                         *
  * NOTE: The PI interrupt register address is hardcoded in the II. If   *
@@ -476,107 +460,100 @@ typedef union ii_illr_u {
  * PI_ID==1, then the II sends the interrupt request to address         *
  * offset 0x01A0_0090 within the local register address space of PI1    *
  * on the node specified by the NODE field.                             *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iidsr_u {
-        uint64_t        ii_iidsr_regval;
-        struct  {
-                uint64_t        i_level                   :      8;
-                uint64_t        i_pi_id                   :      1;
-                uint64_t        i_node                    :     11;
-                uint64_t       i_rsvd_3                  :      4;
-                uint64_t        i_enable                  :      1;
-                uint64_t        i_rsvd_2                  :      3;
-                uint64_t        i_int_sent                :      2;
-                uint64_t       i_rsvd_1                  :      2;
-                uint64_t        i_pi0_forward_int         :      1;
-                uint64_t        i_pi1_forward_int         :      1;
-                uint64_t        i_rsvd                    :     30;
+        uint64_t ii_iidsr_regval;
+        struct {
+                uint64_t i_level:8;
+                uint64_t i_pi_id:1;
+                uint64_t i_node:11;
+                uint64_t i_rsvd_3:4;
+                uint64_t i_enable:1;
+                uint64_t i_rsvd_2:3;
+                uint64_t i_int_sent:2;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_pi0_forward_int:1;
+                uint64_t i_pi1_forward_int:1;
+                uint64_t i_rsvd:30;
         } ii_iidsr_fld_s;
 } ii_iidsr_u_t;
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are two instances of this register. This register is used     *
  * for matching up the incoming responses from the graphics widget to   *
  * the processor that initiated the graphics operation. The             *
  * write-responses are converted to graphics credits and returned to    *
  * the processor so that the processor interface can manage the flow    *
  * control.                                                             *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_igfx0_u {
-        uint64_t        ii_igfx0_regval;
-        struct  {
-                uint64_t        i_w_num                   :      4;
-                uint64_t       i_pi_id                   :      1;
-                uint64_t        i_n_num                   :     12;
-                uint64_t       i_p_num                   :      1;
-                uint64_t       i_rsvd                    :     46;
+        uint64_t ii_igfx0_regval;
+        struct {
+                uint64_t i_w_num:4;
+                uint64_t i_pi_id:1;
+                uint64_t i_n_num:12;
+                uint64_t i_p_num:1;
+                uint64_t i_rsvd:46;
         } ii_igfx0_fld_s;
 } ii_igfx0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are two instances of this register. This register is used     *
  * for matching up the incoming responses from the graphics widget to   *
  * the processor that initiated the graphics operation. The             *
  * write-responses are converted to graphics credits and returned to    *
  * the processor so that the processor interface can manage the flow    *
  * control.                                                             *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_igfx1_u {
-        uint64_t        ii_igfx1_regval;
-        struct  {
-                uint64_t        i_w_num                   :      4;
-                uint64_t       i_pi_id                   :      1;
-                uint64_t        i_n_num                   :     12;
-                uint64_t       i_p_num                   :      1;
-                uint64_t       i_rsvd                    :     46;
+        uint64_t ii_igfx1_regval;
+        struct {
+                uint64_t i_w_num:4;
+                uint64_t i_pi_id:1;
+                uint64_t i_n_num:12;
+                uint64_t i_p_num:1;
+                uint64_t i_rsvd:46;
         } ii_igfx1_fld_s;
 } ii_igfx1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are two instances of this registers. These registers are      *
  * used as scratch registers for software use.                          *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iscr0_u {
-        uint64_t        ii_iscr0_regval;
-        struct  {
-                uint64_t        i_scratch                 :     64;
+        uint64_t ii_iscr0_regval;
+        struct {
+                uint64_t i_scratch:64;
         } ii_iscr0_fld_s;
 } ii_iscr0_u_t;
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are two instances of this registers. These registers are      *
  * used as scratch registers for software use.                          *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iscr1_u {
-        uint64_t        ii_iscr1_regval;
-        struct  {
-                uint64_t        i_scratch                 :     64;
+        uint64_t ii_iscr1_regval;
+        struct {
+                uint64_t i_scratch:64;
         } ii_iscr1_fld_s;
 } ii_iscr1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -599,23 +576,22 @@ typedef union ii_iscr1_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte1_u {
-        uint64_t        ii_itte1_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_w_num                   :      4;
-                uint64_t        i_iosp                    :      1;
-                uint64_t        i_rsvd                    :     51;
+        uint64_t ii_itte1_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte1_fld_s;
 } ii_itte1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -638,23 +614,22 @@ typedef union ii_itte1_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte2_u {
-        uint64_t        ii_itte2_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_w_num                   :      4;
-                uint64_t        i_iosp                    :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_itte2_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte2_fld_s;
 } ii_itte2_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -677,23 +652,22 @@ typedef union ii_itte2_u {
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte3_u {
-        uint64_t        ii_itte3_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t       i_rsvd_1                  :      3;
-                uint64_t       i_w_num                   :      4;
-                uint64_t       i_iosp                    :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_itte3_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte3_fld_s;
 } ii_itte3_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a SHub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -716,23 +690,22 @@ typedef union ii_itte3_u {
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte4_u {
-        uint64_t        ii_itte4_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t       i_w_num                   :      4;
-                uint64_t       i_iosp                    :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_itte4_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte4_fld_s;
 } ii_itte4_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a SHub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -755,23 +728,22 @@ typedef union ii_itte4_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte5_u {
-        uint64_t        ii_itte5_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t       i_rsvd_1                  :      3;
-                uint64_t       i_w_num                   :      4;
-                uint64_t       i_iosp                    :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_itte5_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte5_fld_s;
 } ii_itte5_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -794,23 +766,22 @@ typedef union ii_itte5_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte6_u {
-        uint64_t        ii_itte6_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t       i_rsvd_1                  :      3;
-                uint64_t       i_w_num                   :      4;
-                uint64_t       i_iosp                    :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_itte6_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte6_fld_s;
 } ii_itte6_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
@@ -833,23 +804,22 @@ typedef union ii_itte6_u {
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_itte7_u {
-        uint64_t        ii_itte7_regval;
-        struct  {
-                uint64_t        i_offset                  :      5;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t       i_w_num                   :      4;
-                uint64_t       i_iosp                    :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_itte7_regval;
+        struct {
+                uint64_t i_offset:5;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_w_num:4;
+                uint64_t i_iosp:1;
+                uint64_t i_rsvd:51;
         } ii_itte7_fld_s;
 } ii_itte7_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -868,33 +838,32 @@ typedef union ii_itte7_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprb0_u {
-        uint64_t        ii_iprb0_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t       i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprb0_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprb0_fld_s;
 } ii_iprb0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -913,33 +882,32 @@ typedef union ii_iprb0_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprb8_u {
-        uint64_t        ii_iprb8_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t       i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t       i_rsvd_1                  :      2;
-                uint64_t       i_m                       :      2;
-                uint64_t       i_f                       :      1;
-                uint64_t       i_of_cnt                  :      5;
-                uint64_t       i_error                   :      1;
-                uint64_t       i_rd_to                   :      1;
-                uint64_t       i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t       i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprb8_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprb8_fld_s;
 } ii_iprb8_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -958,33 +926,32 @@ typedef union ii_iprb8_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprb9_u {
-        uint64_t        ii_iprb9_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t        i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprb9_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprb9_fld_s;
 } ii_iprb9_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.        *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -1003,33 +970,32 @@ typedef union ii_iprb9_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- *                                                                      *
- *                                                                      *
+ *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprba_u {
-        uint64_t        ii_iprba_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t       i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprba_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprba_fld_s;
 } ii_iprba_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -1048,33 +1014,32 @@ typedef union ii_iprba_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprbb_u {
-        uint64_t        ii_iprbb_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t        i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprbb_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprbb_fld_s;
 } ii_iprbb_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -1093,33 +1058,32 @@ typedef union ii_iprbb_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprbc_u {
-        uint64_t        ii_iprbc_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t        i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprbc_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprbc_fld_s;
 } ii_iprbc_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -1138,33 +1102,32 @@ typedef union ii_iprbc_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprbd_u {
-        uint64_t        ii_iprbd_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t        i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprbd_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprbd_fld_s;
 } ii_iprbd_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -1183,33 +1146,32 @@ typedef union ii_iprbd_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprbe_u {
-        uint64_t        ii_iprbe_regval;
-        struct  {
-                uint64_t        i_c                       :      8;
-                uint64_t        i_na                      :     14;
-                uint64_t        i_rsvd_2                  :      2;
-                uint64_t        i_nb                      :     14;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_m                       :      2;
-                uint64_t        i_f                       :      1;
-                uint64_t        i_of_cnt                  :      5;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rd_to                   :      1;
-                uint64_t        i_spur_wr                 :      1;
-                uint64_t        i_spur_rd                 :      1;
-                uint64_t        i_rsvd                    :     11;
-                uint64_t        i_mult_err                :      1;
+        uint64_t ii_iprbe_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
         } ii_iprbe_fld_s;
 } ii_iprbe_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of Shub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
@@ -1228,33 +1190,32 @@ typedef union ii_iprbe_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
+ * .                                                                    *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprbf_u {
-        uint64_t       ii_iprbf_regval;
-        struct  {
-                uint64_t       i_c                       :      8;
-                uint64_t       i_na                      :     14;
-                uint64_t       i_rsvd_2                  :      2;
-                uint64_t       i_nb                      :     14;
-                uint64_t       i_rsvd_1                  :      2;
-                uint64_t       i_m                       :      2;
-                uint64_t       i_f                       :      1;
-                uint64_t       i_of_cnt                  :      5;
-                uint64_t       i_error                   :      1;
-                uint64_t       i_rd_to                   :      1;
-                uint64_t       i_spur_wr                 :      1;
-                uint64_t       i_spur_rd                 :      1;
-                uint64_t       i_rsvd                    :     11;
-                uint64_t       i_mult_err                :      1;
-        } ii_iprbe_fld_s;
+        uint64_t ii_iprbf_regval;
+        struct {
+                uint64_t i_c:8;
+                uint64_t i_na:14;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_nb:14;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_m:2;
+                uint64_t i_f:1;
+                uint64_t i_of_cnt:5;
+                uint64_t i_error:1;
+                uint64_t i_rd_to:1;
+                uint64_t i_spur_wr:1;
+                uint64_t i_spur_rd:1;
+                uint64_t i_rsvd:11;
+                uint64_t i_mult_err:1;
+        } ii_iprbe_fld_s;
 } ii_iprbf_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register specifies the timeout value to use for monitoring     *
  * Crosstalk credits which are used outbound to Crosstalk. An           *
  * internal counter called the Crosstalk Credit Timeout Counter         *
@@ -1267,20 +1228,19 @@ typedef union ii_iprbf_u {
  * Crosstalk Credit Timeout has occurred. The internal counter is not   *
  * readable from software, and stops counting at its maximum value,     *
  * so it cannot cause more than one interrupt.                          *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ixcc_u {
-        uint64_t        ii_ixcc_regval;
-        struct  {
-                uint64_t        i_time_out                :     26;
-                uint64_t        i_rsvd                    :     38;
+        uint64_t ii_ixcc_regval;
+        struct {
+                uint64_t i_time_out:26;
+                uint64_t i_rsvd:38;
         } ii_ixcc_fld_s;
 } ii_ixcc_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register qualifies all the PIO and DMA            *
  * operations launched from widget 0 towards the SHub. In               *
  * addition, it also qualifies accesses by the BTE streams.             *
@@ -1292,27 +1252,25 @@ typedef union ii_ixcc_u {
  * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
  * them. Incoming replies from Crosstalk are not subject to this        *
  * access control mechanism.                                            *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_imem_u {
-        uint64_t        ii_imem_regval;
-        struct  {
-                uint64_t        i_w0_esd                  :      1;
-                uint64_t        i_rsvd_3                  :      3;
-                uint64_t        i_b0_esd                  :      1;
-                uint64_t        i_rsvd_2                  :      3;
-                uint64_t        i_b1_esd                  :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_clr_precise             :      1;
-                uint64_t       i_rsvd                    :     51;
+        uint64_t ii_imem_regval;
+        struct {
+                uint64_t i_w0_esd:1;
+                uint64_t i_rsvd_3:3;
+                uint64_t i_b0_esd:1;
+                uint64_t i_rsvd_2:3;
+                uint64_t i_b1_esd:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_clr_precise:1;
+                uint64_t i_rsvd:51;
         } ii_imem_fld_s;
 } ii_imem_u_t;
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register specifies the timeout value to use for   *
  * monitoring Crosstalk tail flits coming into the Shub in the          *
  * TAIL_TO field. An internal counter associated with this register     *
@@ -1332,90 +1290,87 @@ typedef union ii_imem_u {
  * the value in the RRSP_TO field, a Read Response Timeout has          *
  * occurred, and error handling occurs as described in the Error        *
  * Handling section of this document.                                   *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ixtt_u {
-        uint64_t        ii_ixtt_regval;
-        struct  {
-                uint64_t        i_tail_to                 :     26;
-                uint64_t        i_rsvd_1                  :      6;
-                uint64_t        i_rrsp_ps                 :     23;
-                uint64_t        i_rrsp_to                 :      5;
-                uint64_t        i_rsvd                    :      4;
+        uint64_t ii_ixtt_regval;
+        struct {
+                uint64_t i_tail_to:26;
+                uint64_t i_rsvd_1:6;
+                uint64_t i_rrsp_ps:23;
+                uint64_t i_rrsp_to:5;
+                uint64_t i_rsvd:4;
         } ii_ixtt_fld_s;
 } ii_ixtt_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Writing a 1 to the fields of this register clears the appropriate   *
  * error bits in other areas of SHub. Note that when the                *
  * E_PRB_x bits are used to clear error bits in PRB registers,          *
  * SPUR_RD and SPUR_WR may persist, because they require additional     *
  * action to clear them. See the IPRBx and IXSS Register                *
  * specifications.                                                      *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ieclr_u {
-        uint64_t        ii_ieclr_regval;
-        struct  {
-                uint64_t        i_e_prb_0                 :      1;
-                uint64_t        i_rsvd                    :      7;
-                uint64_t        i_e_prb_8                 :      1;
-                uint64_t        i_e_prb_9                 :      1;
-                uint64_t        i_e_prb_a                 :      1;
-                uint64_t        i_e_prb_b                 :      1;
-                uint64_t        i_e_prb_c                 :      1;
-                uint64_t        i_e_prb_d                 :      1;
-                uint64_t        i_e_prb_e                 :      1;
-                uint64_t        i_e_prb_f                 :      1;
-                uint64_t        i_e_crazy                 :      1;
-                uint64_t        i_e_bte_0                 :      1;
-                uint64_t        i_e_bte_1                 :      1;
-                uint64_t        i_reserved_1              :     10;
-                uint64_t        i_spur_rd_hdr             :      1;
-                uint64_t        i_cam_intr_to             :      1;
-                uint64_t        i_cam_overflow            :      1;
-                uint64_t        i_cam_read_miss           :      1;
-                uint64_t        i_ioq_rep_underflow       :      1;
-                uint64_t        i_ioq_req_underflow       :      1;
-                uint64_t        i_ioq_rep_overflow        :      1;
-                uint64_t        i_ioq_req_overflow        :      1;
-                uint64_t        i_iiq_rep_overflow        :      1;
-                uint64_t        i_iiq_req_overflow        :      1;
-                uint64_t        i_ii_xn_rep_cred_overflow :      1;
-                uint64_t        i_ii_xn_req_cred_overflow :      1;
-                uint64_t        i_ii_xn_invalid_cmd       :      1;
-                uint64_t        i_xn_ii_invalid_cmd       :      1;
-                uint64_t        i_reserved_2              :     21;
+        uint64_t ii_ieclr_regval;
+        struct {
+                uint64_t i_e_prb_0:1;
+                uint64_t i_rsvd:7;
+                uint64_t i_e_prb_8:1;
+                uint64_t i_e_prb_9:1;
+                uint64_t i_e_prb_a:1;
+                uint64_t i_e_prb_b:1;
+                uint64_t i_e_prb_c:1;
+                uint64_t i_e_prb_d:1;
+                uint64_t i_e_prb_e:1;
+                uint64_t i_e_prb_f:1;
+                uint64_t i_e_crazy:1;
+                uint64_t i_e_bte_0:1;
+                uint64_t i_e_bte_1:1;
+                uint64_t i_reserved_1:10;
+                uint64_t i_spur_rd_hdr:1;
+                uint64_t i_cam_intr_to:1;
+                uint64_t i_cam_overflow:1;
+                uint64_t i_cam_read_miss:1;
+                uint64_t i_ioq_rep_underflow:1;
+                uint64_t i_ioq_req_underflow:1;
+                uint64_t i_ioq_rep_overflow:1;
+                uint64_t i_ioq_req_overflow:1;
+                uint64_t i_iiq_rep_overflow:1;
+                uint64_t i_iiq_req_overflow:1;
+                uint64_t i_ii_xn_rep_cred_overflow:1;
+                uint64_t i_ii_xn_req_cred_overflow:1;
+                uint64_t i_ii_xn_invalid_cmd:1;
+                uint64_t i_xn_ii_invalid_cmd:1;
+                uint64_t i_reserved_2:21;
         } ii_ieclr_fld_s;
 } ii_ieclr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register controls both BTEs. SOFT_RESET is intended for        *
  * recovery after an error. COUNT controls the total number of CRBs     *
  * that both BTEs (combined) can use, which affects total BTE           *
  * bandwidth.                                                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibcr_u {
-        uint64_t        ii_ibcr_regval;
-        struct  {
-                uint64_t        i_count                   :      4;
-                uint64_t        i_rsvd_1                  :      4;
-                uint64_t        i_soft_reset              :      1;
-                uint64_t        i_rsvd                    :     55;
+        uint64_t ii_ibcr_regval;
+        struct {
+                uint64_t i_count:4;
+                uint64_t i_rsvd_1:4;
+                uint64_t i_soft_reset:1;
+                uint64_t i_rsvd:55;
         } ii_ibcr_fld_s;
 } ii_ibcr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the header of a spurious read response       *
  * received from Crosstalk. A spurious read response is defined as a    *
  * read response received by II from a widget for which (1) the SIDN    *
@@ -1440,49 +1395,47 @@ typedef union ii_ibcr_u {
  * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
  * spurious messages from other widets which were detected after the    *
  * header was captured..                                                *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ixsm_u {
-        uint64_t        ii_ixsm_regval;
-        struct  {
-                uint64_t        i_byte_en                 :     32;
-                uint64_t        i_reserved                :      1;
-                uint64_t        i_tag                     :      3;
-                uint64_t        i_alt_pactyp              :      4;
-                uint64_t        i_bo                      :      1;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_vbpm                    :      1;
-                uint64_t        i_gbr                     :      1;
-                uint64_t        i_ds                      :      2;
-                uint64_t        i_ct                      :      1;
-                uint64_t        i_tnum                    :      5;
-                uint64_t        i_pactyp                  :      4;
-                uint64_t        i_sidn                    :      4;
-                uint64_t        i_didn                    :      4;
+        uint64_t ii_ixsm_regval;
+        struct {
+                uint64_t i_byte_en:32;
+                uint64_t i_reserved:1;
+                uint64_t i_tag:3;
+                uint64_t i_alt_pactyp:4;
+                uint64_t i_bo:1;
+                uint64_t i_error:1;
+                uint64_t i_vbpm:1;
+                uint64_t i_gbr:1;
+                uint64_t i_ds:2;
+                uint64_t i_ct:1;
+                uint64_t i_tnum:5;
+                uint64_t i_pactyp:4;
+                uint64_t i_sidn:4;
+                uint64_t i_didn:4;
         } ii_ixsm_fld_s;
 } ii_ixsm_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the sideband bits of a spurious read         *
  * response received from Crosstalk.                                    *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ixss_u {
-        uint64_t        ii_ixss_regval;
-        struct  {
-                uint64_t        i_sideband                :      8;
-                uint64_t        i_rsvd                    :     55;
-                uint64_t        i_valid                   :      1;
+        uint64_t ii_ixss_regval;
+        struct {
+                uint64_t i_sideband:8;
+                uint64_t i_rsvd:55;
+                uint64_t i_valid:1;
         } ii_ixss_fld_s;
 } ii_ixss_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register enables software to access the II LLP's test port.    *
  * Refer to the LLP 2.5 documentation for an explanation of the test    *
  * port. Software can write to this register to program the values      *
@@ -1490,27 +1443,26 @@ typedef union ii_ixss_u {
  * TestMask and TestSeed). Similarly, software can read from this       *
  * register to obtain the values of the test port's status outputs      *
  * (TestCBerr, TestValid and TestData).                                 *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ilct_u {
-        uint64_t        ii_ilct_regval;
-        struct  {
-                uint64_t        i_test_seed               :     20;
-                uint64_t        i_test_mask               :      8;
-                uint64_t        i_test_data               :     20;
-                uint64_t        i_test_valid              :      1;
-                uint64_t        i_test_cberr              :      1;
-                uint64_t        i_test_flit               :      3;
-                uint64_t        i_test_clear              :      1;
-                uint64_t        i_test_err_capture        :      1;
-                uint64_t        i_rsvd                    :      9;
+        uint64_t ii_ilct_regval;
+        struct {
+                uint64_t i_test_seed:20;
+                uint64_t i_test_mask:8;
+                uint64_t i_test_data:20;
+                uint64_t i_test_valid:1;
+                uint64_t i_test_cberr:1;
+                uint64_t i_test_flit:3;
+                uint64_t i_test_clear:1;
+                uint64_t i_test_err_capture:1;
+                uint64_t i_rsvd:9;
         } ii_ilct_fld_s;
 } ii_ilct_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  If the II detects an illegal incoming Duplonet packet (request or   *
  * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
  * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
@@ -1526,575 +1478,549 @@ typedef union ii_ilct_u {
  * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
  * the OVERRUN bit to indicate that a subsequent error has happened,    *
  * and does nothing further.                                            *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iieph1_u {
-        uint64_t        ii_iieph1_regval;
-        struct  {
-                uint64_t        i_command                 :      7;
-                uint64_t        i_rsvd_5                  :      1;
-                uint64_t        i_suppl                   :     14;
-                uint64_t        i_rsvd_4                  :      1;
-                uint64_t        i_source                  :     14;
-                uint64_t        i_rsvd_3                  :      1;
-                uint64_t        i_err_type                :      4;
-                uint64_t        i_rsvd_2                  :      4;
-                uint64_t        i_overrun                 :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_valid                   :      1;
-                uint64_t        i_rsvd                    :     13;
+        uint64_t ii_iieph1_regval;
+        struct {
+                uint64_t i_command:7;
+                uint64_t i_rsvd_5:1;
+                uint64_t i_suppl:14;
+                uint64_t i_rsvd_4:1;
+                uint64_t i_source:14;
+                uint64_t i_rsvd_3:1;
+                uint64_t i_err_type:4;
+                uint64_t i_rsvd_2:4;
+                uint64_t i_overrun:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_valid:1;
+                uint64_t i_rsvd:13;
         } ii_iieph1_fld_s;
 } ii_iieph1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register holds the Address field from the header flit of an    *
  * incoming erroneous Duplonet packet, along with the tail bit which    *
  * accompanied this header flit. This register is essentially an        *
  * extension of IIEPH1. Two registers were necessary because the 64     *
  * bits available in only a single register were insufficient to        *
  * capture the entire header flit of an erroneous packet.               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iieph2_u {
-        uint64_t        ii_iieph2_regval;
-        struct  {
-                uint64_t        i_rsvd_0                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_rsvd_1                  :     10;
-                uint64_t        i_tail                    :      1;
-                uint64_t        i_rsvd                    :      3;
+        uint64_t ii_iieph2_regval;
+        struct {
+                uint64_t i_rsvd_0:3;
+                uint64_t i_address:47;
+                uint64_t i_rsvd_1:10;
+                uint64_t i_tail:1;
+                uint64_t i_rsvd:3;
         } ii_iieph2_fld_s;
 } ii_iieph2_u_t;
 
-
 /******************************/
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register's value is a bit vector that guards access from SXBs  *
  * to local registers within the II as well as to external Crosstalk    *
  * widgets                                                              *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_islapr_u {
-        uint64_t        ii_islapr_regval;
-        struct  {
-                uint64_t        i_region                  :     64;
+        uint64_t ii_islapr_regval;
+        struct {
+                uint64_t i_region:64;
         } ii_islapr_fld_s;
 } ii_islapr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  A write to this register of the 56-bit value "Pup+Bun" will cause   *
  * the bit in the ISLAPR register corresponding to the region of the    *
  * requestor to be set (access allowed).                                (
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_islapo_u {
-        uint64_t        ii_islapo_regval;
-        struct  {
-                uint64_t        i_io_sbx_ovrride          :     56;
-                uint64_t        i_rsvd                    :      8;
+        uint64_t ii_islapo_regval;
+        struct {
+                uint64_t i_io_sbx_ovrride:56;
+                uint64_t i_rsvd:8;
         } ii_islapo_fld_s;
 } ii_islapo_u_t;
 
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Determines how long the wrapper will wait aftr an interrupt is      *
  * initially issued from the II before it times out the outstanding     *
  * interrupt and drops it from the interrupt queue.                     * 
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iwi_u {
-        uint64_t        ii_iwi_regval;
-        struct  {
-                uint64_t        i_prescale                :     24;
-                uint64_t        i_rsvd                    :      8;
-                uint64_t        i_timeout                 :      8;
-                uint64_t        i_rsvd1                   :      8;
-                uint64_t        i_intrpt_retry_period     :      8;
-                uint64_t        i_rsvd2                   :      8;
+        uint64_t ii_iwi_regval;
+        struct {
+                uint64_t i_prescale:24;
+                uint64_t i_rsvd:8;
+                uint64_t i_timeout:8;
+                uint64_t i_rsvd1:8;
+                uint64_t i_intrpt_retry_period:8;
+                uint64_t i_rsvd2:8;
         } ii_iwi_fld_s;
 } ii_iwi_u_t;
 
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Log errors which have occurred in the II wrapper. The errors are    *
  * cleared by writing to the IECLR register.                            * 
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iwel_u {
-        uint64_t        ii_iwel_regval;
-        struct  {
-                uint64_t        i_intr_timed_out          :      1;
-                uint64_t        i_rsvd                    :      7;
-                uint64_t        i_cam_overflow            :      1;
-                uint64_t        i_cam_read_miss           :      1;
-                uint64_t        i_rsvd1                   :      2;
-                uint64_t        i_ioq_rep_underflow       :      1;
-                uint64_t        i_ioq_req_underflow       :      1;
-                uint64_t        i_ioq_rep_overflow        :      1;
-                uint64_t        i_ioq_req_overflow        :      1;
-                uint64_t        i_iiq_rep_overflow        :      1;
-                uint64_t        i_iiq_req_overflow        :      1;
-                uint64_t        i_rsvd2                   :      6;
-                uint64_t        i_ii_xn_rep_cred_over_under:     1;
-                uint64_t        i_ii_xn_req_cred_over_under:     1;
-                uint64_t        i_rsvd3                   :      6;
-                uint64_t        i_ii_xn_invalid_cmd       :      1;
-                uint64_t        i_xn_ii_invalid_cmd       :      1;
-                uint64_t        i_rsvd4                   :     30;
+        uint64_t ii_iwel_regval;
+        struct {
+                uint64_t i_intr_timed_out:1;
+                uint64_t i_rsvd:7;
+                uint64_t i_cam_overflow:1;
+                uint64_t i_cam_read_miss:1;
+                uint64_t i_rsvd1:2;
+                uint64_t i_ioq_rep_underflow:1;
+                uint64_t i_ioq_req_underflow:1;
+                uint64_t i_ioq_rep_overflow:1;
+                uint64_t i_ioq_req_overflow:1;
+                uint64_t i_iiq_rep_overflow:1;
+                uint64_t i_iiq_req_overflow:1;
+                uint64_t i_rsvd2:6;
+                uint64_t i_ii_xn_rep_cred_over_under:1;
+                uint64_t i_ii_xn_req_cred_over_under:1;
+                uint64_t i_rsvd3:6;
+                uint64_t i_ii_xn_invalid_cmd:1;
+                uint64_t i_xn_ii_invalid_cmd:1;
+                uint64_t i_rsvd4:30;
         } ii_iwel_fld_s;
 } ii_iwel_u_t;
 
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Controls the II wrapper.                                            * 
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iwc_u {
-        uint64_t        ii_iwc_regval;
-        struct  {
-                uint64_t        i_dma_byte_swap           :      1;
-                uint64_t        i_rsvd                    :      3;
-                uint64_t        i_cam_read_lines_reset    :      1;
-                uint64_t        i_rsvd1                   :      3;
-                uint64_t        i_ii_xn_cred_over_under_log:     1;
-                uint64_t        i_rsvd2                   :     19;
-                uint64_t        i_xn_rep_iq_depth         :      5;
-                uint64_t        i_rsvd3                   :      3;
-                uint64_t        i_xn_req_iq_depth         :      5;
-                uint64_t        i_rsvd4                   :      3;
-                uint64_t        i_iiq_depth               :      6;
-                uint64_t        i_rsvd5                   :     12;
-                uint64_t        i_force_rep_cred          :      1;
-                uint64_t        i_force_req_cred          :      1;
+        uint64_t ii_iwc_regval;
+        struct {
+                uint64_t i_dma_byte_swap:1;
+                uint64_t i_rsvd:3;
+                uint64_t i_cam_read_lines_reset:1;
+                uint64_t i_rsvd1:3;
+                uint64_t i_ii_xn_cred_over_under_log:1;
+                uint64_t i_rsvd2:19;
+                uint64_t i_xn_rep_iq_depth:5;
+                uint64_t i_rsvd3:3;
+                uint64_t i_xn_req_iq_depth:5;
+                uint64_t i_rsvd4:3;
+                uint64_t i_iiq_depth:6;
+                uint64_t i_rsvd5:12;
+                uint64_t i_force_rep_cred:1;
+                uint64_t i_force_req_cred:1;
         } ii_iwc_fld_s;
 } ii_iwc_u_t;
 
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Status in the II wrapper.                                           * 
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iws_u {
-        uint64_t        ii_iws_regval;
-        struct  {
-                uint64_t        i_xn_rep_iq_credits       :      5;
-                uint64_t        i_rsvd                    :      3;
-                uint64_t        i_xn_req_iq_credits       :      5;
-                uint64_t        i_rsvd1                   :     51;
+        uint64_t ii_iws_regval;
+        struct {
+                uint64_t i_xn_rep_iq_credits:5;
+                uint64_t i_rsvd:3;
+                uint64_t i_xn_req_iq_credits:5;
+                uint64_t i_rsvd1:51;
         } ii_iws_fld_s;
 } ii_iws_u_t;
 
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Masks errors in the IWEL register.                                  *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iweim_u {
-        uint64_t        ii_iweim_regval;
-        struct  {
-                uint64_t        i_intr_timed_out          :      1;
-                uint64_t        i_rsvd                    :      7;
-                uint64_t        i_cam_overflow            :      1;
-                uint64_t        i_cam_read_miss           :      1;
-                uint64_t        i_rsvd1                   :      2;
-                uint64_t        i_ioq_rep_underflow       :      1;
-                uint64_t        i_ioq_req_underflow       :      1;
-                uint64_t        i_ioq_rep_overflow        :      1;
-                uint64_t        i_ioq_req_overflow        :      1;
-                uint64_t        i_iiq_rep_overflow        :      1;
-                uint64_t        i_iiq_req_overflow        :      1;
-                uint64_t        i_rsvd2                   :      6;
-                uint64_t        i_ii_xn_rep_cred_overflow :      1;
-                uint64_t        i_ii_xn_req_cred_overflow :      1;
-                uint64_t        i_rsvd3                   :      6;
-                uint64_t        i_ii_xn_invalid_cmd       :      1;
-                uint64_t        i_xn_ii_invalid_cmd       :      1;
-                uint64_t        i_rsvd4                   :     30;
+        uint64_t ii_iweim_regval;
+        struct {
+                uint64_t i_intr_timed_out:1;
+                uint64_t i_rsvd:7;
+                uint64_t i_cam_overflow:1;
+                uint64_t i_cam_read_miss:1;
+                uint64_t i_rsvd1:2;
+                uint64_t i_ioq_rep_underflow:1;
+                uint64_t i_ioq_req_underflow:1;
+                uint64_t i_ioq_rep_overflow:1;
+                uint64_t i_ioq_req_overflow:1;
+                uint64_t i_iiq_rep_overflow:1;
+                uint64_t i_iiq_req_overflow:1;
+                uint64_t i_rsvd2:6;
+                uint64_t i_ii_xn_rep_cred_overflow:1;
+                uint64_t i_ii_xn_req_cred_overflow:1;
+                uint64_t i_rsvd3:6;
+                uint64_t i_ii_xn_invalid_cmd:1;
+                uint64_t i_xn_ii_invalid_cmd:1;
+                uint64_t i_rsvd4:30;
         } ii_iweim_fld_s;
 } ii_iweim_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  A write to this register causes a particular field in the           *
  * corresponding widget's PRB entry to be adjusted up or down by 1.     *
  * This counter should be used when recovering from error and reset     *
  * conditions. Note that software would be capable of causing           *
  * inadvertent overflow or underflow of these counters.                 *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ipca_u {
-        uint64_t        ii_ipca_regval;
-        struct  {
-                uint64_t        i_wid                     :      4;
-                uint64_t        i_adjust                  :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_field                   :      2;
-                uint64_t        i_rsvd                    :     54;
+        uint64_t ii_ipca_regval;
+        struct {
+                uint64_t i_wid:4;
+                uint64_t i_adjust:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_field:2;
+                uint64_t i_rsvd:54;
         } ii_ipca_fld_s;
 } ii_ipca_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
-
 typedef union ii_iprte0a_u {
-        uint64_t        ii_iprte0a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
+        uint64_t ii_iprte0a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte0a_fld_s;
 } ii_iprte0a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte1a_u {
-        uint64_t        ii_iprte1a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
+        uint64_t ii_iprte1a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte1a_fld_s;
 } ii_iprte1a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte2a_u {
-        uint64_t        ii_iprte2a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
+        uint64_t ii_iprte2a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte2a_fld_s;
 } ii_iprte2a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte3a_u {
-        uint64_t        ii_iprte3a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t        i_vld                     :      1;
+        uint64_t ii_iprte3a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte3a_fld_s;
 } ii_iprte3a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte4a_u {
-        uint64_t        ii_iprte4a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t        i_vld                     :      1;
+        uint64_t ii_iprte4a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte4a_fld_s;
 } ii_iprte4a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte5a_u {
-        uint64_t        ii_iprte5a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t        i_vld                     :      1;
+        uint64_t ii_iprte5a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte5a_fld_s;
 } ii_iprte5a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte6a_u {
-        uint64_t        ii_iprte6a_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :     54;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t        i_vld                     :      1;
+        uint64_t ii_iprte6a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } ii_iprte6a_fld_s;
 } ii_iprte6a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte7a_u {
-        uint64_t       ii_iprte7a_regval;
-        struct  {
-                uint64_t       i_rsvd_1                  :     54;
-                uint64_t       i_widget                  :      4;
-                uint64_t       i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
-        } ii_iprtea7_fld_s;
+        uint64_t ii_iprte7a_regval;
+        struct {
+                uint64_t i_rsvd_1:54;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
+        } ii_iprtea7_fld_s;
 } ii_iprte7a_u_t;
 
-
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
-
 typedef union ii_iprte0b_u {
-        uint64_t        ii_iprte0b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte0b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
         } ii_iprte0b_fld_s;
 } ii_iprte0b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte1b_u {
-        uint64_t        ii_iprte1b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte1b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
         } ii_iprte1b_fld_s;
 } ii_iprte1b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte2b_u {
-        uint64_t        ii_iprte2b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte2b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
         } ii_iprte2b_fld_s;
 } ii_iprte2b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte3b_u {
-        uint64_t        ii_iprte3b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte3b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
         } ii_iprte3b_fld_s;
 } ii_iprte3b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte4b_u {
-        uint64_t        ii_iprte4b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte4b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
         } ii_iprte4b_fld_s;
 } ii_iprte4b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte5b_u {
-        uint64_t        ii_iprte5b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte5b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
         } ii_iprte5b_fld_s;
 } ii_iprte5b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte6b_u {
-        uint64_t        ii_iprte6b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
+        uint64_t ii_iprte6b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
 
         } ii_iprte6b_fld_s;
 } ii_iprte6b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iprte7b_u {
-        uint64_t       ii_iprte7b_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_address                 :     47;
-                uint64_t        i_init                    :      3;
-                uint64_t       i_source                  :     11;
-        } ii_iprte7b_fld_s;
+        uint64_t ii_iprte7b_regval;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_address:47;
+                uint64_t i_init:3;
+                uint64_t i_source:11;
+        } ii_iprte7b_fld_s;
 } ii_iprte7b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  SHub II contains a feature which did not exist in      *
  * the Hub which automatically cleans up after a Read Response          *
  * timeout, including deallocation of the IPRTE and recovery of IBuf    *
@@ -2108,23 +2034,22 @@ typedef union ii_iprte7b_u {
  * Note that this register does not affect the contents of the IPRTE    *
  * registers. The Valid bits in those registers have to be              *
  * specifically turned off by software.                                 *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ipdr_u {
-        uint64_t        ii_ipdr_regval;
-        struct  {
-                uint64_t        i_te                      :      3;
-                uint64_t        i_rsvd_1                  :      1;
-                uint64_t        i_pnd                     :      1;
-                uint64_t        i_init_rpcnt              :      1;
-                uint64_t        i_rsvd                    :     58;
+        uint64_t ii_ipdr_regval;
+        struct {
+                uint64_t i_te:3;
+                uint64_t i_rsvd_1:1;
+                uint64_t i_pnd:1;
+                uint64_t i_init_rpcnt:1;
+                uint64_t i_rsvd:58;
         } ii_ipdr_fld_s;
 } ii_ipdr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  A write to this register causes a CRB entry to be returned to the   *
  * queue of free CRBs. The entry should have previously been cleared    *
  * (mark bit) via backdoor access to the pertinent CRB entry. This      *
@@ -2137,21 +2062,20 @@ typedef union ii_ipdr_u {
  * software clears the mark bit, and finally 4) software writes to      *
  * the ICDR register to return the CRB entry to the list of free CRB    *
  * entries.                                                             *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icdr_u {
-        uint64_t        ii_icdr_regval;
-        struct  {
-                uint64_t        i_crb_num                 :      4;
-                uint64_t        i_pnd                     :      1;
-                uint64_t       i_rsvd                    :     59;
+        uint64_t ii_icdr_regval;
+        struct {
+                uint64_t i_crb_num:4;
+                uint64_t i_pnd:1;
+                uint64_t i_rsvd:59;
         } ii_icdr_fld_s;
 } ii_icdr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register provides debug access to two FIFOs inside of II.      *
  * Both IOQ_MAX* fields of this register contain the instantaneous      *
  * depth (in units of the number of available entries) of the           *
@@ -2164,130 +2088,124 @@ typedef union ii_icdr_u {
  * this register is written. If there are any active entries in any     *
  * of these FIFOs when this register is written, the results are        *
  * undefined.                                                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ifdr_u {
-        uint64_t        ii_ifdr_regval;
-        struct  {
-                uint64_t        i_ioq_max_rq              :      7;
-                uint64_t        i_set_ioq_rq              :      1;
-                uint64_t        i_ioq_max_rp              :      7;
-                uint64_t        i_set_ioq_rp              :      1;
-                uint64_t        i_rsvd                    :     48;
+        uint64_t ii_ifdr_regval;
+        struct {
+                uint64_t i_ioq_max_rq:7;
+                uint64_t i_set_ioq_rq:1;
+                uint64_t i_ioq_max_rp:7;
+                uint64_t i_set_ioq_rp:1;
+                uint64_t i_rsvd:48;
         } ii_ifdr_fld_s;
 } ii_ifdr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register allows the II to become sluggish in removing          *
  * messages from its inbound queue (IIQ). This will cause messages to   *
  * back up in either virtual channel. Disabling the "molasses" mode     *
  * subsequently allows the II to be tested under stress. In the         *
  * sluggish ("Molasses") mode, the localized effects of congestion      *
  * can be observed.                                                     *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iiap_u {
-        uint64_t       ii_iiap_regval;
-        struct  {
-                uint64_t       i_rq_mls                  :      6;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_rp_mls                  :      6;
-                uint64_t       i_rsvd                    :     50;
-        } ii_iiap_fld_s;
+        uint64_t ii_iiap_regval;
+        struct {
+                uint64_t i_rq_mls:6;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_rp_mls:6;
+                uint64_t i_rsvd:50;
+        } ii_iiap_fld_s;
 } ii_iiap_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register allows several parameters of CRB operation to be      *
  * set. Note that writing to this register can have catastrophic side   *
  * effects, if the CRB is not quiescent, i.e. if the CRB is             *
  * processing protocol messages when the write occurs.                  *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icmr_u {
-        uint64_t        ii_icmr_regval;
-        struct  {
-                uint64_t        i_sp_msg                  :      1;
-                uint64_t        i_rd_hdr                  :      1;
-                uint64_t        i_rsvd_4                  :      2;
-                uint64_t        i_c_cnt                   :      4;
-                uint64_t        i_rsvd_3                  :      4;
-                uint64_t        i_clr_rqpd                :      1;
-                uint64_t        i_clr_rppd                :      1;
-                uint64_t        i_rsvd_2                  :      2;
-                uint64_t        i_fc_cnt                  :      4;
-                uint64_t        i_crb_vld                 :     15;
-                uint64_t        i_crb_mark                :     15;
-                uint64_t        i_rsvd_1                  :      2;
-                uint64_t        i_precise                 :      1;
-                uint64_t        i_rsvd                    :     11;
+        uint64_t ii_icmr_regval;
+        struct {
+                uint64_t i_sp_msg:1;
+                uint64_t i_rd_hdr:1;
+                uint64_t i_rsvd_4:2;
+                uint64_t i_c_cnt:4;
+                uint64_t i_rsvd_3:4;
+                uint64_t i_clr_rqpd:1;
+                uint64_t i_clr_rppd:1;
+                uint64_t i_rsvd_2:2;
+                uint64_t i_fc_cnt:4;
+                uint64_t i_crb_vld:15;
+                uint64_t i_crb_mark:15;
+                uint64_t i_rsvd_1:2;
+                uint64_t i_precise:1;
+                uint64_t i_rsvd:11;
         } ii_icmr_fld_s;
 } ii_icmr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register allows control of the table portion of the CRB        *
  * logic via software. Control operations from this register have       *
  * priority over all incoming Crosstalk or BTE requests.                *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_iccr_u {
-        uint64_t        ii_iccr_regval;
-        struct  {
-                uint64_t        i_crb_num                 :      4;
-                uint64_t        i_rsvd_1                  :      4;
-                uint64_t        i_cmd                     :      8;
-                uint64_t        i_pending                 :      1;
-                uint64_t        i_rsvd                    :     47;
+        uint64_t ii_iccr_regval;
+        struct {
+                uint64_t i_crb_num:4;
+                uint64_t i_rsvd_1:4;
+                uint64_t i_cmd:8;
+                uint64_t i_pending:1;
+                uint64_t i_rsvd:47;
         } ii_iccr_fld_s;
 } ii_iccr_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register allows the maximum timeout value to be programmed.    *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icto_u {
-        uint64_t        ii_icto_regval;
-        struct  {
-                uint64_t        i_timeout                 :      8;
-                uint64_t        i_rsvd                    :     56;
+        uint64_t ii_icto_regval;
+        struct {
+                uint64_t i_timeout:8;
+                uint64_t i_rsvd:56;
         } ii_icto_fld_s;
 } ii_icto_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register allows the timeout prescalar to be programmed. An     *
  * internal counter is associated with this register. When the          *
  * internal counter reaches the value of the PRESCALE field, the        *
  * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
  * field). The internal counter resets to zero, and then continues      *
  * counting.                                                            *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ictp_u {
-        uint64_t        ii_ictp_regval;
-        struct  {
-                uint64_t        i_prescale                :     24;
-                uint64_t        i_rsvd                    :     40;
+        uint64_t ii_ictp_regval;
+        struct {
+                uint64_t i_prescale:24;
+                uint64_t i_rsvd:40;
         } ii_ictp_fld_s;
 } ii_ictp_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
@@ -2306,243 +2224,234 @@ typedef union ii_ictp_u {
  * recovering any potential error state from before the reset).         *
  * The following four tables summarize the format for the four          *
  * registers that are used for each ICRB# Entry.                        *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icrb0_a_u {
-        uint64_t        ii_icrb0_a_regval;
-        struct  {
-                uint64_t        ia_iow                    :      1;
-                uint64_t        ia_vld                    :      1;
-                uint64_t        ia_addr                   :     47;
-                uint64_t        ia_tnum                   :      5;
-                uint64_t        ia_sidn                   :      4;
-                uint64_t       ia_rsvd                   :      6;
+        uint64_t ii_icrb0_a_regval;
+        struct {
+                uint64_t ia_iow:1;
+                uint64_t ia_vld:1;
+                uint64_t ia_addr:47;
+                uint64_t ia_tnum:5;
+                uint64_t ia_sidn:4;
+                uint64_t ia_rsvd:6;
         } ii_icrb0_a_fld_s;
 } ii_icrb0_a_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icrb0_b_u {
-        uint64_t        ii_icrb0_b_regval;
-        struct  {
-                uint64_t        ib_xt_err                 :      1;
-                uint64_t        ib_mark                   :      1;
-                uint64_t        ib_ln_uce                 :      1;
-                uint64_t        ib_errcode                :      3;
-                uint64_t        ib_error                  :      1;
-                uint64_t        ib_stall__bte_1           :      1;
-                uint64_t        ib_stall__bte_0           :      1;
-                uint64_t        ib_stall__intr            :      1;
-                uint64_t        ib_stall_ib               :      1;
-                uint64_t        ib_intvn                  :      1;
-                uint64_t        ib_wb                     :      1;
-                uint64_t        ib_hold                   :      1;
-                uint64_t        ib_ack                    :      1;
-                uint64_t        ib_resp                   :      1;
-                uint64_t        ib_ack_cnt                :     11;
-                uint64_t        ib_rsvd                   :      7;
-                uint64_t        ib_exc                    :      5;
-                uint64_t        ib_init                   :      3;
-                uint64_t        ib_imsg                   :      8;
-                uint64_t        ib_imsgtype               :      2;
-                uint64_t        ib_use_old                :      1;
-                uint64_t        ib_rsvd_1                 :     11;
+        uint64_t ii_icrb0_b_regval;
+        struct {
+                uint64_t ib_xt_err:1;
+                uint64_t ib_mark:1;
+                uint64_t ib_ln_uce:1;
+                uint64_t ib_errcode:3;
+                uint64_t ib_error:1;
+                uint64_t ib_stall__bte_1:1;
+                uint64_t ib_stall__bte_0:1;
+                uint64_t ib_stall__intr:1;
+                uint64_t ib_stall_ib:1;
+                uint64_t ib_intvn:1;
+                uint64_t ib_wb:1;
+                uint64_t ib_hold:1;
+                uint64_t ib_ack:1;
+                uint64_t ib_resp:1;
+                uint64_t ib_ack_cnt:11;
+                uint64_t ib_rsvd:7;
+                uint64_t ib_exc:5;
+                uint64_t ib_init:3;
+                uint64_t ib_imsg:8;
+                uint64_t ib_imsgtype:2;
+                uint64_t ib_use_old:1;
+                uint64_t ib_rsvd_1:11;
         } ii_icrb0_b_fld_s;
 } ii_icrb0_b_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icrb0_c_u {
-        uint64_t        ii_icrb0_c_regval;
-        struct  {
-                uint64_t        ic_source                 :     15;
-                uint64_t        ic_size                   :      2;
-                uint64_t        ic_ct                     :      1;
-                uint64_t        ic_bte_num                :      1;
-                uint64_t        ic_gbr                    :      1;
-                uint64_t        ic_resprqd                :      1;
-                uint64_t        ic_bo                     :      1;
-                uint64_t        ic_suppl                  :     15;
-                uint64_t        ic_rsvd                   :     27;
+        uint64_t ii_icrb0_c_regval;
+        struct {
+                uint64_t ic_source:15;
+                uint64_t ic_size:2;
+                uint64_t ic_ct:1;
+                uint64_t ic_bte_num:1;
+                uint64_t ic_gbr:1;
+                uint64_t ic_resprqd:1;
+                uint64_t ic_bo:1;
+                uint64_t ic_suppl:15;
+                uint64_t ic_rsvd:27;
         } ii_icrb0_c_fld_s;
 } ii_icrb0_c_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icrb0_d_u {
-        uint64_t        ii_icrb0_d_regval;
-        struct  {
-                uint64_t        id_pa_be                  :     43;
-                uint64_t        id_bte_op                 :      1;
-                uint64_t        id_pr_psc                 :      4;
-                uint64_t        id_pr_cnt                 :      4;
-                uint64_t        id_sleep                  :      1;
-                uint64_t        id_rsvd                   :     11;
+        uint64_t ii_icrb0_d_regval;
+        struct {
+                uint64_t id_pa_be:43;
+                uint64_t id_bte_op:1;
+                uint64_t id_pr_psc:4;
+                uint64_t id_pr_cnt:4;
+                uint64_t id_sleep:1;
+                uint64_t id_rsvd:11;
         } ii_icrb0_d_fld_s;
 } ii_icrb0_d_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icrb0_e_u {
-        uint64_t        ii_icrb0_e_regval;
-        struct  {
-                uint64_t        ie_timeout                :      8;
-                uint64_t        ie_context                :     15;
-                uint64_t        ie_rsvd                   :      1;
-                uint64_t        ie_tvld                   :      1;
-                uint64_t        ie_cvld                   :      1;
-                uint64_t        ie_rsvd_0                 :     38;
+        uint64_t ii_icrb0_e_regval;
+        struct {
+                uint64_t ie_timeout:8;
+                uint64_t ie_context:15;
+                uint64_t ie_rsvd:1;
+                uint64_t ie_tvld:1;
+                uint64_t ie_cvld:1;
+                uint64_t ie_rsvd_0:38;
         } ii_icrb0_e_fld_s;
 } ii_icrb0_e_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the lower 64 bits of the header of the       *
  * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
  * register is set.                                                     *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icsml_u {
-        uint64_t        ii_icsml_regval;
-        struct  {
-                uint64_t        i_tt_addr                 :     47;
-                uint64_t        i_newsuppl_ex             :     14;
-                uint64_t        i_reserved                :      2;
-                uint64_t       i_overflow                :      1;
+        uint64_t ii_icsml_regval;
+        struct {
+                uint64_t i_tt_addr:47;
+                uint64_t i_newsuppl_ex:14;
+                uint64_t i_reserved:2;
+                uint64_t i_overflow:1;
         } ii_icsml_fld_s;
 } ii_icsml_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the middle 64 bits of the header of the      *
  * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
  * register is set.                                                     *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icsmm_u {
-        uint64_t        ii_icsmm_regval;
-        struct  {
-                uint64_t        i_tt_ack_cnt              :     11;
-                uint64_t        i_reserved                :     53;
+        uint64_t ii_icsmm_regval;
+        struct {
+                uint64_t i_tt_ack_cnt:11;
+                uint64_t i_reserved:53;
         } ii_icsmm_fld_s;
 } ii_icsmm_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the microscopic state, all the inputs to     *
  * the protocol table, captured with the spurious message. Valid when   *
  * the SP_MSG bit in the ICMR register is set.                          *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_icsmh_u {
-        uint64_t        ii_icsmh_regval;
-        struct  {
-                uint64_t        i_tt_vld                  :      1;
-                uint64_t        i_xerr                    :      1;
-                uint64_t        i_ft_cwact_o              :      1;
-                uint64_t        i_ft_wact_o               :      1;
-                uint64_t       i_ft_active_o             :      1;
-                uint64_t        i_sync                    :      1;
-                uint64_t        i_mnusg                   :      1;
-                uint64_t        i_mnusz                   :      1;
-                uint64_t        i_plusz                   :      1;
-                uint64_t        i_plusg                   :      1;
-                uint64_t        i_tt_exc                  :      5;
-                uint64_t        i_tt_wb                   :      1;
-                uint64_t        i_tt_hold                 :      1;
-                uint64_t        i_tt_ack                  :      1;
-                uint64_t        i_tt_resp                 :      1;
-                uint64_t        i_tt_intvn                :      1;
-                uint64_t        i_g_stall_bte1            :      1;
-                uint64_t        i_g_stall_bte0            :      1;
-                uint64_t        i_g_stall_il              :      1;
-                uint64_t        i_g_stall_ib              :      1;
-                uint64_t        i_tt_imsg                 :      8;
-                uint64_t        i_tt_imsgtype             :      2;
-                uint64_t        i_tt_use_old              :      1;
-                uint64_t        i_tt_respreqd             :      1;
-                uint64_t        i_tt_bte_num              :      1;
-                uint64_t        i_cbn                     :      1;
-                uint64_t        i_match                   :      1;
-                uint64_t        i_rpcnt_lt_34             :      1;
-                uint64_t        i_rpcnt_ge_34             :      1;
-                uint64_t        i_rpcnt_lt_18             :      1;
-                uint64_t        i_rpcnt_ge_18             :      1;
-                uint64_t       i_rpcnt_lt_2              :      1;
-                uint64_t        i_rpcnt_ge_2              :      1;
-                uint64_t        i_rqcnt_lt_18             :      1;
-                uint64_t        i_rqcnt_ge_18             :      1;
-                uint64_t        i_rqcnt_lt_2              :      1;
-                uint64_t        i_rqcnt_ge_2              :      1;
-                uint64_t        i_tt_device               :      7;
-                uint64_t        i_tt_init                 :      3;
-                uint64_t        i_reserved                :      5;
+        uint64_t ii_icsmh_regval;
+        struct {
+                uint64_t i_tt_vld:1;
+                uint64_t i_xerr:1;
+                uint64_t i_ft_cwact_o:1;
+                uint64_t i_ft_wact_o:1;
+                uint64_t i_ft_active_o:1;
+                uint64_t i_sync:1;
+                uint64_t i_mnusg:1;
+                uint64_t i_mnusz:1;
+                uint64_t i_plusz:1;
+                uint64_t i_plusg:1;
+                uint64_t i_tt_exc:5;
+                uint64_t i_tt_wb:1;
+                uint64_t i_tt_hold:1;
+                uint64_t i_tt_ack:1;
+                uint64_t i_tt_resp:1;
+                uint64_t i_tt_intvn:1;
+                uint64_t i_g_stall_bte1:1;
+                uint64_t i_g_stall_bte0:1;
+                uint64_t i_g_stall_il:1;
+                uint64_t i_g_stall_ib:1;
+                uint64_t i_tt_imsg:8;
+                uint64_t i_tt_imsgtype:2;
+                uint64_t i_tt_use_old:1;
+                uint64_t i_tt_respreqd:1;
+                uint64_t i_tt_bte_num:1;
+                uint64_t i_cbn:1;
+                uint64_t i_match:1;
+                uint64_t i_rpcnt_lt_34:1;
+                uint64_t i_rpcnt_ge_34:1;
+                uint64_t i_rpcnt_lt_18:1;
+                uint64_t i_rpcnt_ge_18:1;
+                uint64_t i_rpcnt_lt_2:1;
+                uint64_t i_rpcnt_ge_2:1;
+                uint64_t i_rqcnt_lt_18:1;
+                uint64_t i_rqcnt_ge_18:1;
+                uint64_t i_rqcnt_lt_2:1;
+                uint64_t i_rqcnt_ge_2:1;
+                uint64_t i_tt_device:7;
+                uint64_t i_tt_init:3;
+                uint64_t i_reserved:5;
         } ii_icsmh_fld_s;
 } ii_icsmh_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
  * II core and a 3-bit selection signal to the fsbclk domain in the II  *
  * wrapper.                                                             *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_idbss_u {
-        uint64_t        ii_idbss_regval;
-        struct  {
-                uint64_t        i_iioclk_core_submenu     :      3;
-                uint64_t        i_rsvd                    :      5;
-                uint64_t        i_fsbclk_wrapper_submenu  :      3;
-                uint64_t        i_rsvd_1                  :      5;
-                uint64_t        i_iioclk_menu             :      5;
-                uint64_t        i_rsvd_2                  :     43;
+        uint64_t ii_idbss_regval;
+        struct {
+                uint64_t i_iioclk_core_submenu:3;
+                uint64_t i_rsvd:5;
+                uint64_t i_fsbclk_wrapper_submenu:3;
+                uint64_t i_rsvd_1:5;
+                uint64_t i_iioclk_menu:5;
+                uint64_t i_rsvd_2:43;
         } ii_idbss_fld_s;
 } ii_idbss_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register is used to set up the length for a       *
  * transfer and then to monitor the progress of that transfer. This     *
  * register needs to be initialized before a transfer is started. A     *
@@ -2553,63 +2462,60 @@ typedef union ii_idbss_u {
  * transfer completes, hardware will clear the Busy bit. The length     *
  * field will also contain the number of cache lines left to be         *
  * transferred.                                                         *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibls0_u {
-        uint64_t        ii_ibls0_regval;
-        struct  {
-                uint64_t        i_length                  :     16;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_busy                    :      1;
-                uint64_t       i_rsvd                    :     43;
+        uint64_t ii_ibls0_regval;
+        struct {
+                uint64_t i_length:16;
+                uint64_t i_error:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_busy:1;
+                uint64_t i_rsvd:43;
         } ii_ibls0_fld_s;
 } ii_ibls0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibsa0_u {
-        uint64_t        ii_ibsa0_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_addr                    :     42;
-                uint64_t       i_rsvd                    :     15;
+        uint64_t ii_ibsa0_regval;
+        struct {
+                uint64_t i_rsvd_1:7;
+                uint64_t i_addr:42;
+                uint64_t i_rsvd:15;
         } ii_ibsa0_fld_s;
 } ii_ibsa0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibda0_u {
-        uint64_t        ii_ibda0_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_addr                    :     42;
-                uint64_t        i_rsvd                    :     15;
+        uint64_t ii_ibda0_regval;
+        struct {
+                uint64_t i_rsvd_1:7;
+                uint64_t i_addr:42;
+                uint64_t i_rsvd:15;
         } ii_ibda0_fld_s;
 } ii_ibda0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Writing to this register sets up the attributes of the transfer     *
  * and initiates the transfer operation. Reading this register has      *
  * the side effect of terminating any transfer in progress. Note:       *
@@ -2617,61 +2523,58 @@ typedef union ii_ibda0_u {
  * other BTE. If a BTE stream has to be stopped (due to error           *
  * handling for example), both BTE streams should be stopped and        *
  * their transfers discarded.                                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibct0_u {
-        uint64_t        ii_ibct0_regval;
-        struct  {
-                uint64_t        i_zerofill                :      1;
-                uint64_t        i_rsvd_2                  :      3;
-                uint64_t        i_notify                  :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t       i_poison                  :      1;
-                uint64_t       i_rsvd                    :     55;
+        uint64_t ii_ibct0_regval;
+        struct {
+                uint64_t i_zerofill:1;
+                uint64_t i_rsvd_2:3;
+                uint64_t i_notify:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_poison:1;
+                uint64_t i_rsvd:55;
         } ii_ibct0_fld_s;
 } ii_ibct0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the address to which the WINV is sent.       *
  * This address has to be cache line aligned.                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibna0_u {
-        uint64_t        ii_ibna0_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_addr                    :     42;
-                uint64_t        i_rsvd                    :     15;
+        uint64_t ii_ibna0_regval;
+        struct {
+                uint64_t i_rsvd_1:7;
+                uint64_t i_addr:42;
+                uint64_t i_rsvd:15;
         } ii_ibna0_fld_s;
 } ii_ibna0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the programmable level as well as the node   *
  * ID and PI unit of the processor to which the interrupt will be       *
- * sent.                                                                *
- *                                                                      *
+ * sent.                                                                *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibia0_u {
-        uint64_t        ii_ibia0_regval;
-        struct  {
-                uint64_t        i_rsvd_2                   :     1;
-                uint64_t        i_node_id                 :     11;
-                uint64_t        i_rsvd_1                  :      4;
-                uint64_t        i_level                   :      7;
-                uint64_t       i_rsvd                    :     41;
+        uint64_t ii_ibia0_regval;
+        struct {
+                uint64_t i_rsvd_2:1;
+                uint64_t i_node_id:11;
+                uint64_t i_rsvd_1:4;
+                uint64_t i_level:7;
+                uint64_t i_rsvd:41;
         } ii_ibia0_fld_s;
 } ii_ibia0_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  * Description:  This register is used to set up the length for a       *
  * transfer and then to monitor the progress of that transfer. This     *
  * register needs to be initialized before a transfer is started. A     *
@@ -2682,63 +2585,60 @@ typedef union ii_ibia0_u {
  * transfer completes, hardware will clear the Busy bit. The length     *
  * field will also contain the number of cache lines left to be         *
  * transferred.                                                         *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibls1_u {
-        uint64_t        ii_ibls1_regval;
-        struct  {
-                uint64_t        i_length                  :     16;
-                uint64_t        i_error                   :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_busy                    :      1;
-                uint64_t       i_rsvd                    :     43;
+        uint64_t ii_ibls1_regval;
+        struct {
+                uint64_t i_length:16;
+                uint64_t i_error:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_busy:1;
+                uint64_t i_rsvd:43;
         } ii_ibls1_fld_s;
 } ii_ibls1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibsa1_u {
-        uint64_t        ii_ibsa1_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_addr                    :     33;
-                uint64_t        i_rsvd                    :     24;
+        uint64_t ii_ibsa1_regval;
+        struct {
+                uint64_t i_rsvd_1:7;
+                uint64_t i_addr:33;
+                uint64_t i_rsvd:24;
         } ii_ibsa1_fld_s;
 } ii_ibsa1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibda1_u {
-        uint64_t        ii_ibda1_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_addr                    :     33;
-                uint64_t        i_rsvd                    :     24;
+        uint64_t ii_ibda1_regval;
+        struct {
+                uint64_t i_rsvd_1:7;
+                uint64_t i_addr:33;
+                uint64_t i_rsvd:24;
         } ii_ibda1_fld_s;
 } ii_ibda1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  Writing to this register sets up the attributes of the transfer     *
  * and initiates the transfer operation. Reading this register has      *
  * the side effect of terminating any transfer in progress. Note:       *
@@ -2746,61 +2646,58 @@ typedef union ii_ibda1_u {
  * other BTE. If a BTE stream has to be stopped (due to error           *
  * handling for example), both BTE streams should be stopped and        *
  * their transfers discarded.                                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibct1_u {
-        uint64_t        ii_ibct1_regval;
-        struct  {
-                uint64_t        i_zerofill                :      1;
-                uint64_t        i_rsvd_2                  :      3;
-                uint64_t        i_notify                  :      1;
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_poison                  :      1;
-                uint64_t        i_rsvd                    :     55;
+        uint64_t ii_ibct1_regval;
+        struct {
+                uint64_t i_zerofill:1;
+                uint64_t i_rsvd_2:3;
+                uint64_t i_notify:1;
+                uint64_t i_rsvd_1:3;
+                uint64_t i_poison:1;
+                uint64_t i_rsvd:55;
         } ii_ibct1_fld_s;
 } ii_ibct1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the address to which the WINV is sent.       *
  * This address has to be cache line aligned.                           *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibna1_u {
-        uint64_t        ii_ibna1_regval;
-        struct  {
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_addr                    :     33;
-                uint64_t       i_rsvd                    :     24;
+        uint64_t ii_ibna1_regval;
+        struct {
+                uint64_t i_rsvd_1:7;
+                uint64_t i_addr:33;
+                uint64_t i_rsvd:24;
         } ii_ibna1_fld_s;
 } ii_ibna1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register contains the programmable level as well as the node   *
  * ID and PI unit of the processor to which the interrupt will be       *
- * sent.                                                                *
- *                                                                      *
+ * sent.                                                                *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ibia1_u {
-        uint64_t        ii_ibia1_regval;
-        struct  {
-                uint64_t        i_pi_id                   :      1;
-                uint64_t        i_node_id                 :      8;
-                uint64_t        i_rsvd_1                  :      7;
-                uint64_t        i_level                   :      7;
-                uint64_t        i_rsvd                    :     41;
+        uint64_t ii_ibia1_regval;
+        struct {
+                uint64_t i_pi_id:1;
+                uint64_t i_node_id:8;
+                uint64_t i_rsvd_1:7;
+                uint64_t i_level:7;
+                uint64_t i_rsvd:41;
         } ii_ibia1_fld_s;
 } ii_ibia1_u_t;
 
-
 /************************************************************************
- *                                                                      *
+ *                                                                      *
  *  This register defines the resources that feed information into      *
  * the two performance counters located in the IO Performance           *
  * Profiling Register. There are 17 different quantities that can be    *
@@ -2811,133 +2708,129 @@ typedef union ii_ibia1_u {
  * other is available from the other performance counter. Hence, the    *
  * II supports all 17*16=272 possible combinations of quantities to     *
  * measure.                                                             *
- *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ipcr_u {
-        uint64_t        ii_ipcr_regval;
-        struct  {
-                uint64_t        i_ippr0_c                 :      4;
-                uint64_t        i_ippr1_c                 :      4;
-                uint64_t        i_icct                    :      8;
-                uint64_t       i_rsvd                    :     48;
+        uint64_t ii_ipcr_regval;
+        struct {
+                uint64_t i_ippr0_c:4;
+                uint64_t i_ippr1_c:4;
+                uint64_t i_icct:8;
+                uint64_t i_rsvd:48;
         } ii_ipcr_fld_s;
 } ii_ipcr_u_t;
 
-
 /************************************************************************
- *                                                                      *
- *                                                                      *
- *                                                                      *
+ *                                                                      *
+ *                                                                      *
+ *                                                                      *
  ************************************************************************/
 
 typedef union ii_ippr_u {
-        uint64_t        ii_ippr_regval;
-        struct  {
-                uint64_t        i_ippr0                   :     32;
-                uint64_t        i_ippr1                   :     32;
+        uint64_t ii_ippr_regval;
+        struct {
+                uint64_t i_ippr0:32;
+                uint64_t i_ippr1:32;
         } ii_ippr_fld_s;
 } ii_ippr_u_t;
 
-
-
-/**************************************************************************
- *                                                                        *
- * The following defines which were not formed into structures are        *
- * probably indentical to another register, and the name of the           *
- * register is provided against each of these registers. This             *
- * information needs to be checked carefully                              *
- *                                                                        *
- *           IIO_ICRB1_A                IIO_ICRB0_A                       *
- *           IIO_ICRB1_B                IIO_ICRB0_B                       *
- *           IIO_ICRB1_C                IIO_ICRB0_C                       *
- *           IIO_ICRB1_D                IIO_ICRB0_D                       *
- *           IIO_ICRB1_E                IIO_ICRB0_E                       *
- *           IIO_ICRB2_A                IIO_ICRB0_A                       *
- *           IIO_ICRB2_B                IIO_ICRB0_B                       *
- *           IIO_ICRB2_C                IIO_ICRB0_C                       *
- *           IIO_ICRB2_D                IIO_ICRB0_D                       *
- *           IIO_ICRB2_E                IIO_ICRB0_E                       *
- *           IIO_ICRB3_A                IIO_ICRB0_A                       *
- *           IIO_ICRB3_B                IIO_ICRB0_B                       *
- *           IIO_ICRB3_C                IIO_ICRB0_C                       *
- *           IIO_ICRB3_D                IIO_ICRB0_D                       *
- *           IIO_ICRB3_E                IIO_ICRB0_E                       *
- *           IIO_ICRB4_A                IIO_ICRB0_A                       *
- *           IIO_ICRB4_B                IIO_ICRB0_B                       *
- *           IIO_ICRB4_C                IIO_ICRB0_C                       *
- *           IIO_ICRB4_D                IIO_ICRB0_D                       *
- *           IIO_ICRB4_E                IIO_ICRB0_E                       *
- *           IIO_ICRB5_A                IIO_ICRB0_A                       *
- *           IIO_ICRB5_B                IIO_ICRB0_B                       *
- *           IIO_ICRB5_C                IIO_ICRB0_C                       *
- *           IIO_ICRB5_D                IIO_ICRB0_D                       *
- *           IIO_ICRB5_E                IIO_ICRB0_E                       *
- *           IIO_ICRB6_A                IIO_ICRB0_A                       *
- *           IIO_ICRB6_B                IIO_ICRB0_B                       *
- *           IIO_ICRB6_C                IIO_ICRB0_C                       *
- *           IIO_ICRB6_D                IIO_ICRB0_D                       *
- *           IIO_ICRB6_E                IIO_ICRB0_E                       *
- *           IIO_ICRB7_A                IIO_ICRB0_A                       *
- *           IIO_ICRB7_B                IIO_ICRB0_B                       *
- *           IIO_ICRB7_C                IIO_ICRB0_C                       *
- *           IIO_ICRB7_D                IIO_ICRB0_D                       *
- *           IIO_ICRB7_E                IIO_ICRB0_E                       *
- *           IIO_ICRB8_A                IIO_ICRB0_A                       *
- *           IIO_ICRB8_B                IIO_ICRB0_B                       *
- *           IIO_ICRB8_C                IIO_ICRB0_C                       *
- *           IIO_ICRB8_D                IIO_ICRB0_D                       *
- *           IIO_ICRB8_E                IIO_ICRB0_E                       *
- *           IIO_ICRB9_A                IIO_ICRB0_A                       *
- *           IIO_ICRB9_B                IIO_ICRB0_B                       *
- *           IIO_ICRB9_C                IIO_ICRB0_C                       *
- *           IIO_ICRB9_D                IIO_ICRB0_D                       *
- *           IIO_ICRB9_E                IIO_ICRB0_E                       *
- *           IIO_ICRBA_A                IIO_ICRB0_A                       *
- *           IIO_ICRBA_B                IIO_ICRB0_B                       *
- *           IIO_ICRBA_C                IIO_ICRB0_C                       *
- *           IIO_ICRBA_D                IIO_ICRB0_D                       *
- *           IIO_ICRBA_E                IIO_ICRB0_E                       *
- *           IIO_ICRBB_A                IIO_ICRB0_A                       *
- *           IIO_ICRBB_B                IIO_ICRB0_B                       *
- *           IIO_ICRBB_C                IIO_ICRB0_C                       *
- *           IIO_ICRBB_D                IIO_ICRB0_D                       *
- *           IIO_ICRBB_E                IIO_ICRB0_E                       *
- *           IIO_ICRBC_A                IIO_ICRB0_A                       *
- *           IIO_ICRBC_B                IIO_ICRB0_B                       *
- *           IIO_ICRBC_C                IIO_ICRB0_C                       *
- *           IIO_ICRBC_D                IIO_ICRB0_D                       *
- *           IIO_ICRBC_E                IIO_ICRB0_E                       *
- *           IIO_ICRBD_A                IIO_ICRB0_A                       *
- *           IIO_ICRBD_B                IIO_ICRB0_B                       *
- *           IIO_ICRBD_C                IIO_ICRB0_C                       *
- *           IIO_ICRBD_D                IIO_ICRB0_D                       *
- *           IIO_ICRBD_E                IIO_ICRB0_E                       *
- *           IIO_ICRBE_A                IIO_ICRB0_A                       *
- *           IIO_ICRBE_B                IIO_ICRB0_B                       *
- *           IIO_ICRBE_C                IIO_ICRB0_C                       *
- *           IIO_ICRBE_D                IIO_ICRB0_D                       *
- *           IIO_ICRBE_E                IIO_ICRB0_E                       *
- *                                                                        *
- **************************************************************************/
-
+/************************************************************************
+ *                                                                      *
+ * The following defines which were not formed into structures are      *
+ * probably indentical to another register, and the name of the         *
+ * register is provided against each of these registers. This           *
+ * information needs to be checked carefully                            *
+ *                                                                      *
+ *              IIO_ICRB1_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB1_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB1_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB1_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB1_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB2_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB2_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB2_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB2_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB2_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB3_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB3_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB3_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB3_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB3_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB4_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB4_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB4_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB4_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB4_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB5_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB5_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB5_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB5_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB5_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB6_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB6_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB6_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB6_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB6_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB7_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB7_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB7_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB7_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB7_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB8_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB8_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB8_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB8_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB8_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB9_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB9_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB9_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB9_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB9_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBA_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBA_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBA_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBA_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBA_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBB_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBB_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBB_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBB_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBB_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBC_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBC_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBC_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBC_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBC_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBD_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBD_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBD_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBD_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBD_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBE_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBE_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBE_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBE_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBE_E             IIO_ICRB0_E                     *
+ *                                                                      *
+ ************************************************************************/
 
 /*
  * Slightly friendlier names for some common registers.
  */
-#define IIO_WIDGET              IIO_WID      /* Widget identification */
-#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
-#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
-#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
-#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
-#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
-#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
-#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
-#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
-#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
-#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
-#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
-#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_WIDGET              IIO_WID         /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT       /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR         /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR       /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO       /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA        /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA        /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM       /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR       /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR        /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC        /* Xtalk credit count timeout */
+#define IIO_XTALKTT_TOUT        IIO_IXTT        /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR       /* IO error clear */
 #define IIO_IGFX_0              IIO_IGFX0
 #define IIO_IGFX_1              IIO_IGFX1
 #define IIO_IBCT_0              IIO_IBCT0
@@ -2957,12 +2850,12 @@ typedef union ii_ippr_u {
 #define IIO_PRTE_A(_x)          (IIO_IPRTE0_A + (8 * (_x)))
 #define IIO_PRTE_B(_x)          (IIO_IPRTE0_B + (8 * (_x)))
 #define IIO_NUM_PRTES           8       /* Total number of PRB table entries */
-#define IIO_WIDPRTE_A(x)        IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
-#define IIO_WIDPRTE_B(x)        IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_A(x)        IIO_PRTE_A(((x) - 8))   /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x)        IIO_PRTE_B(((x) - 8))   /* widget ID to its PRTE num */
 
-#define IIO_NUM_IPRBS           (9) 
+#define IIO_NUM_IPRBS           9
 
-#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_IS_UP               0x00002000
 #define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
 #define IIO_LLP_CSR_LLP_STAT_SHFT       12
 
@@ -2970,30 +2863,29 @@ typedef union ii_ippr_u {
 #define IIO_LLP_SN_MAX  0xffff  /* in ILLR SN_CNT, Max Sequence Number errors */
 
 /* key to IIO_PROTECT_OVRRD */
-#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
 
 /* BTE register names */
-#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
-#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
-#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
-#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
-#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
-#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
-#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
-#define IIO_BTE_OFF_1           (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
+#define IIO_BTE_STAT_0          IIO_IBLS_0      /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0      /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0      /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0      /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0      /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0      /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0       /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1           (IIO_IBLS_1 - IIO_IBLS_0)       /* Offset from base to BTE 1 */
 
 /* BTE register offsets from base */
 #define BTEOFF_STAT             0
-#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
-#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
-#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
-#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
-#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
-
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
 
 /* names used in shub diags */
-#define IIO_BASE_BTE0   IIO_IBLS_0              
-#define IIO_BASE_BTE1   IIO_IBLS_1              
+#define IIO_BASE_BTE0   IIO_IBLS_0
+#define IIO_BASE_BTE1   IIO_IBLS_1
 
 /*
  * Macro which takes the widget number, and returns the
@@ -3001,10 +2893,9 @@ typedef union ii_ippr_u {
  * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */
-#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
-                        (_x) : \
-                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
-
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
 /* GFX Flow Control Node/Widget Register */
 #define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
@@ -3025,7 +2916,6 @@ typedef union ii_ippr_u {
         (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
         (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
 
-
 /* Scratch registers (all bits available) */
 #define IIO_SCRATCH_REG0        IIO_ISCR0
 #define IIO_SCRATCH_REG1        IIO_ISCR1
@@ -3046,21 +2936,21 @@ typedef union ii_ippr_u {
 #define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
 #define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
 /* IO Translation Table Entries */
-#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
-                                        /* Hw manuals number them 1..7! */
+#define IIO_NUM_ITTES   7       /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
 /*
  * IIO_IMEM Register fields.
  */
-#define IIO_IMEM_W0ESD  0x1UL             /* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD  (1UL << 4)        /* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD  (1UL << 8)        /* BTE 1 Shut down due to error */
+#define IIO_IMEM_W0ESD  0x1UL   /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1UL << 4)      /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1UL << 8)      /* BTE 1 Shut down due to error */
 
 /*
  * As a permanent workaround for a bug in the PI side of the shub, we've
  * redefined big window 7 as small window 0.
  XXX does this still apply for SN1??
  */
-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
 
 /*
  * Use the top big window as a surrogate for the first small window
@@ -3071,11 +2961,11 @@ typedef union ii_ippr_u {
 
 /*
  * CRB manipulation macros
- *      The CRB macros are slightly complicated, since there are up to
- *      four registers associated with each CRB entry.
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
  */
-#define IIO_NUM_CRBS            15      /* Number of CRBs */
-#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
 #define IIO_ICRB_OFFSET         8
 #define IIO_ICRB_0              IIO_ICRB0_A
 #define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
@@ -3083,43 +2973,43 @@ typedef union ii_ippr_u {
         #define IIO_FIRST_PC_ENTRY 12
  */
 
-#define IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
-#define IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
-#define IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
-#define IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
-#define IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
+#define IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
+#define IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
+#define IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
+#define IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
+#define IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
 
 #define TNUM_TO_WIDGET_DEV(_tnum)       (_tnum & 0x7)
 
 /*
  * values for "ecode" field
  */
-#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
-#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
-#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
-                                         * e.g. WINV to a Read only line. */
-#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
-#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
-#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
-#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
-#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read  */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
 
 /*
  * Values for field imsgtype
  */
-#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
-#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
-#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
-#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
 
 /*
  * values for field initiator.
  */
-#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
-#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
-#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
-#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
-#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
 
 /*
  * Number of credits Hub widget has while sending req/response to
@@ -3127,8 +3017,8 @@ typedef union ii_ippr_u {
  * Value of 3 is required by Xbow 1.1
  * We may be able to increase this to 4 with Xbow 1.2.
  */
-#define       HUBII_XBOW_CREDIT       3
-#define       HUBII_XBOW_REV2_CREDIT  4
+#define            HUBII_XBOW_CREDIT       3
+#define            HUBII_XBOW_REV2_CREDIT  4
 
 /*
  * Number of credits that xtalk devices should use when communicating
@@ -3159,28 +3049,28 @@ typedef union ii_ippr_u {
  */
 
 #define IIO_ICMR_CRB_VLD_SHFT   20
-#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
 
 #define IIO_ICMR_FC_CNT_SHFT    16
-#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
 
 #define IIO_ICMR_C_CNT_SHFT     4
-#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
 
-#define IIO_ICMR_PRECISE        (1UL << 52)
-#define IIO_ICMR_CLR_RPPD       (1UL << 13)
-#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
 
 /*
  * IIO PIO Deallocation register field masks : (IIO_IPDR)
  XXX present but not needed in bedrock?  See the manual.
  */
-#define IIO_IPDR_PND    (1 << 4)
+#define IIO_IPDR_PND            (1 << 4)
 
 /*
  * IIO CRB deallocation register field masks: (IIO_ICDR)
  */
-#define IIO_ICDR_PND    (1 << 4)
+#define IIO_ICDR_PND            (1 << 4)
 
 /* 
  * IO BTE Length/Status (IIO_IBLS) register bit field definitions
@@ -3223,35 +3113,35 @@ typedef union ii_ippr_u {
 /*
  * IO Error Clear register bit field definitions
  */
-#define IECLR_PI1_FWD_INT       (1UL << 31)  /* clear PI1_FORWARD_INT in iidsr */
-#define IECLR_PI0_FWD_INT       (1UL << 30)  /* clear PI0_FORWARD_INT in iidsr */
-#define IECLR_SPUR_RD_HDR       (1UL << 29)  /* clear valid bit in ixss reg */
-#define IECLR_BTE1              (1UL << 18)  /* clear bte error 1 */
-#define IECLR_BTE0              (1UL << 17)  /* clear bte error 0 */
-#define IECLR_CRAZY             (1UL << 16)  /* clear crazy bit in wstat reg */
-#define IECLR_PRB_F             (1UL << 15)  /* clear err bit in PRB_F reg */
-#define IECLR_PRB_E             (1UL << 14)  /* clear err bit in PRB_E reg */
-#define IECLR_PRB_D             (1UL << 13)  /* clear err bit in PRB_D reg */
-#define IECLR_PRB_C             (1UL << 12)  /* clear err bit in PRB_C reg */
-#define IECLR_PRB_B             (1UL << 11)  /* clear err bit in PRB_B reg */
-#define IECLR_PRB_A             (1UL << 10)  /* clear err bit in PRB_A reg */
-#define IECLR_PRB_9             (1UL << 9)   /* clear err bit in PRB_9 reg */
-#define IECLR_PRB_8             (1UL << 8)   /* clear err bit in PRB_8 reg */
-#define IECLR_PRB_0             (1UL << 0)   /* clear err bit in PRB_0 reg */
+#define IECLR_PI1_FWD_INT       (1UL << 31)     /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT       (1UL << 30)     /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR       (1UL << 29)     /* clear valid bit in ixss reg */
+#define IECLR_BTE1              (1UL << 18)     /* clear bte error 1 */
+#define IECLR_BTE0              (1UL << 17)     /* clear bte error 0 */
+#define IECLR_CRAZY             (1UL << 16)     /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1UL << 15)     /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1UL << 14)     /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1UL << 13)     /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1UL << 12)     /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1UL << 11)     /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1UL << 10)     /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1UL << 9)      /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1UL << 8)      /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1UL << 0)      /* clear err bit in PRB_0 reg */
 
 /*
  * IIO CRB control register Fields: IIO_ICCR 
  */
-#define IIO_ICCR_PENDING        (0x10000)
-#define IIO_ICCR_CMD_MASK       (0xFF)
-#define IIO_ICCR_CMD_SHFT       (7)
-#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
-#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
-#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
-#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory 
+#define IIO_ICCR_PENDING        0x10000
+#define IIO_ICCR_CMD_MASK       0xFF
+#define IIO_ICCR_CMD_SHFT       7
+#define IIO_ICCR_CMD_NOP        0x0     /* No Op */
+#define IIO_ICCR_CMD_WAKE       0x100   /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    0x200   /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      0x400   /* Contents of entry written to memory
                                          * via a WB
                                          */
-#define IIO_ICCR_CMD_FLUSH      (0x800)
+#define IIO_ICCR_CMD_FLUSH      0x800
 
 /*
  *
@@ -3283,8 +3173,8 @@ typedef union ii_ippr_u {
  * Easy access macros for CRBs, all 5 registers (A-E)
  */
 typedef ii_icrb0_a_u_t icrba_t;
-#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
-#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
 #define a_addr          ii_icrb0_a_fld_s.ia_addr
 #define a_valid         ii_icrb0_a_fld_s.ia_vld
 #define a_iow           ii_icrb0_a_fld_s.ia_iow
@@ -3324,14 +3214,13 @@ typedef ii_icrb0_c_u_t icrbc_t;
 #define c_source        ii_icrb0_c_fld_s.ic_source
 #define c_regvalue      ii_icrb0_c_regval
 
-
 typedef ii_icrb0_d_u_t icrbd_t;
 #define d_sleep         ii_icrb0_d_fld_s.id_sleep
 #define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
 #define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
 #define d_bteop         ii_icrb0_d_fld_s.id_bte_op
-#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
-#define d_benable       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
+#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be       /* ic_pa_be fld has 2 names */
+#define d_benable       ii_icrb0_d_fld_s.id_pa_be       /* ic_pa_be fld has 2 names */
 #define d_regvalue      ii_icrb0_d_regval
 
 typedef ii_icrb0_e_u_t icrbe_t;
@@ -3341,7 +3230,6 @@ typedef ii_icrb0_e_u_t icrbe_t;
 #define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
 #define e_regvalue      ii_icrb0_e_regval
 
-
 /* Number of widgets supported by shub */
 #define HUB_NUM_WIDGET          9
 #define HUB_WIDGET_ID_MIN       0x8
@@ -3367,27 +3255,27 @@ typedef ii_icrb0_e_u_t icrbe_t;
 
 #define LNK_STAT_WORKING        0x2             /* LLP is working */
 
-#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
-#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
-#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
-#define IIO_WSTAT_TXRETRY_SHFT  (16)
-#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
-                                          IIO_WSTAT_TXRETRY_MASK)
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  0x7F            /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  16
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                        IIO_WSTAT_TXRETRY_MASK)
 
 /* Number of II perf. counters we can multiplex at once */
 
 #define IO_PERF_SETS    32
 
 /* Bit for the widget in inbound access register */
-#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
 /* Bit for the widget in outbound access register */
-#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
 
 /* NOTE: The following define assumes that we are going to get
  * widget numbers from 8 thru F and the device numbers within
  * widget from 0 thru 7.
  */
-#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
 
 /* IO Interrupt Destination Register */
 #define IIO_IIDSR_SENT_SHIFT    28
@@ -3402,11 +3290,11 @@ typedef ii_icrb0_e_u_t icrbe_t;
 #define IIO_IIDSR_LVL_MASK      0x000000ff
 
 /* Xtalk timeout threshhold register (IIO_IXTT) */
-#define IXTT_RRSP_TO_SHFT       55         /* read response timeout */
+#define IXTT_RRSP_TO_SHFT       55      /* read response timeout */
 #define IXTT_RRSP_TO_MASK       (0x1FULL << IXTT_RRSP_TO_SHFT)
-#define IXTT_RRSP_PS_SHFT       32         /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_SHFT       32      /* read responsed TO prescalar */
 #define IXTT_RRSP_PS_MASK       (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
-#define IXTT_TAIL_TO_SHFT       0          /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_SHFT       0       /* tail timeout counter threshold */
 #define IXTT_TAIL_TO_MASK       (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
 
 /*
@@ -3414,17 +3302,17 @@ typedef ii_icrb0_e_u_t icrbe_t;
  */
 
 typedef union hubii_wcr_u {
-        uint64_t      wcr_reg_value;
-        struct {
-          uint64_t      wcr_widget_id:   4,     /* LLP crossbar credit */
-                        wcr_tag_mode:    1,     /* Tag mode */
-                        wcr_rsvd1:       8,     /* Reserved */
-                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
-                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
-                        wcr_dir_con:     1,     /* widget direct connect */
-                        wcr_e_thresh:    5,     /* elasticity threshold */
-                        wcr_rsvd:       41;     /* unused */
-        } wcr_fields_s;
+        uint64_t wcr_reg_value;
+        struct {
+                uint64_t wcr_widget_id:4,       /* LLP crossbar credit */
+                 wcr_tag_mode:1,        /* Tag mode */
+                 wcr_rsvd1:8,   /* Reserved */
+                 wcr_xbar_crd:3,        /* LLP crossbar credit */
+                 wcr_f_bad_pkt:1,       /* Force bad llp pkt enable */
+                 wcr_dir_con:1, /* widget direct connect */
+                 wcr_e_thresh:5,        /* elasticity threshold */
+                 wcr_rsvd:41;   /* unused */
+        } wcr_fields_s;
 } hubii_wcr_t;
 
 #define iwcr_dir_con    wcr_fields_s.wcr_dir_con
@@ -3436,41 +3324,35 @@ performance registers */
    performed */
 
 typedef union io_perf_sel {
-        uint64_t perf_sel_reg;
-        struct {
-               uint64_t perf_ippr0 :  4,
-                                perf_ippr1 :  4,
-                                perf_icct  :  8,
-                                perf_rsvd  : 48;
-        } perf_sel_bits;
+        uint64_t perf_sel_reg;
+        struct {
+                uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
+        } perf_sel_bits;
 } io_perf_sel_t;
 
 /* io_perf_cnt is to extract the count from the shub registers. Due to
    hardware problems there is only one counter, not two. */
 
 typedef union io_perf_cnt {
-        uint64_t      perf_cnt;
-        struct {
-               uint64_t perf_cnt   : 20,
-                                perf_rsvd2 : 12,
-                                perf_rsvd1 : 32;
-        } perf_cnt_bits;
+        uint64_t perf_cnt;
+        struct {
+                uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
+        } perf_cnt_bits;
 
 } io_perf_cnt_t;
 
 typedef union iprte_a {
-        uint64_t        entry;
-        struct {
-                uint64_t        i_rsvd_1                  :      3;
-                uint64_t        i_addr                    :     38;
-                uint64_t        i_init                    :      3;
-                uint64_t        i_source                  :      8;
-                uint64_t        i_rsvd                    :      2;
-                uint64_t        i_widget                  :      4;
-                uint64_t        i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
+        uint64_t entry;
+        struct {
+                uint64_t i_rsvd_1:3;
+                uint64_t i_addr:38;
+                uint64_t i_init:3;
+                uint64_t i_source:8;
+                uint64_t i_rsvd:2;
+                uint64_t i_widget:4;
+                uint64_t i_to_cnt:5;
+                uint64_t i_vld:1;
         } iprte_fields;
 } iprte_a_t;
 
-#endif /* _ASM_IA64_SN_SHUBIO_H */
-
+#endif                          /* _ASM_IA64_SN_SHUBIO_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
index 685435af170d..20b300187669 100644
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -92,24 +92,24 @@
  * NOTE: on non-MP systems, only cpuid 0 exists
  */
 
-extern short physical_node_map[];                       /* indexed by nasid to get cnode */
+extern short physical_node_map[];       /* indexed by nasid to get cnode */
 
 /*
  * Macros for retrieving info about current cpu
  */
-#define get_nasid()                     (nodepda->phys_cpuid[smp_processor_id()].nasid)
-#define get_subnode()                   (nodepda->phys_cpuid[smp_processor_id()].subnode)
-#define get_slice()                     (nodepda->phys_cpuid[smp_processor_id()].slice)
-#define get_cnode()                     (nodepda->phys_cpuid[smp_processor_id()].cnode)
-#define get_sapicid()                   ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
+#define get_nasid()     (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
+#define get_subnode()   (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
+#define get_slice()     (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
+#define get_cnode()     (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
+#define get_sapicid()   ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
 
 /*
  * Macros for retrieving info about an arbitrary cpu
  *      cpuid - logical cpu id
  */
-#define cpuid_to_nasid(cpuid)           (nodepda->phys_cpuid[cpuid].nasid)
-#define cpuid_to_subnode(cpuid)         (nodepda->phys_cpuid[cpuid].subnode)
-#define cpuid_to_slice(cpuid)           (nodepda->phys_cpuid[cpuid].slice)
+#define cpuid_to_nasid(cpuid)           (sn_nodepda->phys_cpuid[cpuid].nasid)
+#define cpuid_to_subnode(cpuid)         (sn_nodepda->phys_cpuid[cpuid].subnode)
+#define cpuid_to_slice(cpuid)           (sn_nodepda->phys_cpuid[cpuid].slice)
 #define cpuid_to_cnodeid(cpuid)         (physical_node_map[cpuid_to_nasid(cpuid)])
 
 
@@ -123,11 +123,8 @@ extern int nasid_slice_to_cpuid(int, int);
 
 /*
  * cnodeid_to_nasid - convert a cnodeid to a NASID
- *      Macro relies on pg_data for a node being on the node itself.
- *      Just extract the NASID from the pointer.
- *
  */
-#define cnodeid_to_nasid(cnodeid)       pda->cnodeid_to_nasid_table[cnodeid]
+#define cnodeid_to_nasid(cnodeid)       (sn_cnodeid_to_nasid[cnodeid])
  
 /*
  * nasid_to_cnodeid - convert a NASID to a cnodeid
diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h
deleted file mode 100644
index 8c21ac3f0156..000000000000
--- a/include/asm-ia64/sn/sn_fru.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992-1997,1999-2004 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_SN_FRU_H
-#define _ASM_IA64_SN_SN_FRU_H
-
-#define MAX_DIMMS                       8        /* max # of dimm banks */
-#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
-
-typedef unsigned char confidence_t;
-
-typedef struct kf_mem_s {
-        confidence_t km_confidence; /* confidence level that the memory is bad
-                                     * is this necessary ?
-                                     */
-        confidence_t km_dimm[MAX_DIMMS];
-                                    /* confidence level that dimm[i] is bad
-                                     *I think this is the right number
-                                     */
-
-} kf_mem_t;
-
-typedef struct kf_cpu_s {
-        confidence_t    kc_confidence; /* confidence level that cpu is bad */
-        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
-        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
-        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
-        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
-} kf_cpu_t;
-
-
-typedef struct kf_pci_bus_s {
-        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
-        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
-                                        /* confidence level that the pci dev is bad */
-} kf_pci_bus_t;
-
-
-#endif /* _ASM_IA64_SN_SN_FRU_H */
-
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index f914f6da077c..eb0395ad0d6a 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -115,6 +115,13 @@
 #define SAL_IROUTER_INTR_XMIT   SAL_CONSOLE_INTR_XMIT
 #define SAL_IROUTER_INTR_RECV   SAL_CONSOLE_INTR_RECV
 
+/*
+ * Error Handling Features
+ */
+#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV     0x1
+#define SAL_ERR_FEAT_LOG_SBES                   0x2
+#define SAL_ERR_FEAT_MFR_OVERRIDE               0x4
+#define SAL_ERR_FEAT_SBE_THRESHOLD              0xffff0000
 
 /*
  * SAL Error Codes
@@ -342,6 +349,25 @@ ia64_sn_plat_cpei_handler(void)
 }
 
 /*
+ * Set Error Handling Features
+ */
+static inline u64
+ia64_sn_plat_set_error_handling_features(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
+                (SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV | SAL_ERR_FEAT_LOG_SBES),
+                0, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
  * Checks for console input.
  */
 static inline u64
@@ -472,7 +498,7 @@ static inline u64
 ia64_sn_pod_mode(void)
 {
         struct ia64_sal_retval isrv;
-        SAL_CALL(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
+        SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
         if (isrv.status)
                 return 0;
         return isrv.v0;
@@ -557,7 +583,8 @@ static inline u64
 ia64_sn_partition_serial_get(void)
 {
         struct ia64_sal_retval ret_stuff;
-        SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0);
+        ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
+                                   0, 0, 0, 0, 0, 0);
         if (ret_stuff.status != 0)
             return 0;
         return ret_stuff.v0;
@@ -565,11 +592,10 @@ ia64_sn_partition_serial_get(void)
 
 static inline u64
 sn_partition_serial_number_val(void) {
-        if (sn_partition_serial_number) {
-                return(sn_partition_serial_number);
-        } else {
-                return(sn_partition_serial_number = ia64_sn_partition_serial_get());
+        if (unlikely(sn_partition_serial_number == 0)) {
+                sn_partition_serial_number = ia64_sn_partition_serial_get();
         }
+        return sn_partition_serial_number;
 }
 
 /*
@@ -580,8 +606,8 @@ static inline partid_t
 ia64_sn_sysctl_partition_get(nasid_t nasid)
 {
         struct ia64_sal_retval ret_stuff;
-        SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
-                 0, 0, 0, 0, 0, 0);
+        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
+                                0, 0, 0, 0, 0, 0);
         if (ret_stuff.status != 0)
             return INVALID_PARTID;
         return ((partid_t)ret_stuff.v0);
@@ -595,11 +621,38 @@ extern partid_t sn_partid;
 
 static inline partid_t
 sn_local_partid(void) {
-        if (sn_partid < 0) {
-                return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id())));
-        } else {
-                return sn_partid;
+        if (unlikely(sn_partid < 0)) {
+                sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()));
         }
+        return sn_partid;
+}
+
+/*
+ * Returns the physical address of the partition's reserved page through
+ * an iterative number of calls.
+ *
+ * On first call, 'cookie' and 'len' should be set to 0, and 'addr'
+ * set to the nasid of the partition whose reserved page's address is
+ * being sought.
+ * On subsequent calls, pass the values, that were passed back on the
+ * previous call.
+ *
+ * While the return status equals SALRET_MORE_PASSES, keep calling
+ * this function after first copying 'len' bytes starting at 'addr'
+ * into 'buf'. Once the return status equals SALRET_OK, 'addr' will
+ * be the physical address of the partition's reserved page. If the
+ * return status equals neither of these, an error as occurred.
+ */
+static inline s64
+sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
+{
+        struct ia64_sal_retval rv;
+        ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
+                                   *addr, buf, *len, 0, 0, 0);
+        *cookie = rv.v0;
+        *addr = rv.v1;
+        *len = rv.v2;
+        return rv.status;
 }
 
 /*
@@ -621,8 +674,8 @@ static inline int
 sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
 {
         struct ia64_sal_retval ret_stuff;
-        SAL_CALL(ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, (u64)operation,
-                 0, 0, 0, 0);
+        ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
+                         (u64)operation, 0, 0, 0, 0);
         return ret_stuff.status;
 }
 
@@ -646,8 +699,8 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
         } else {
                 call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
         }
-        SAL_CALL(ret_stuff, call, start_addr, end_addr, return_addr, (u64)1,
-                 0, 0, 0);
+        ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
+                         (u64)1, 0, 0, 0);
         return ret_stuff.status;
 }
 
@@ -668,8 +721,8 @@ static inline int
 sn_change_coherence(u64 *new_domain, u64 *old_domain)
 {
         struct ia64_sal_retval ret_stuff;
-        SAL_CALL(ret_stuff, SN_SAL_COHERENCE, new_domain, old_domain, 0, 0,
-                 0, 0, 0);
+        ia64_sal_oemcall(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
+                         (u64)old_domain, 0, 0, 0, 0, 0);
         return ret_stuff.status;
 }
 
@@ -688,8 +741,8 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
         cnodeid = nasid_to_cnodeid(get_node_number(paddr));
         // spin_lock(&NODEPDA(cnodeid)->bist_lock);
         local_irq_save(irq_flags);
-        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_MEMPROTECT, paddr, len, nasid_array,
-                 perms, 0, 0, 0);
+        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
+                                (u64)nasid_array, perms, 0, 0, 0);
         local_irq_restore(irq_flags);
         // spin_unlock(&NODEPDA(cnodeid)->bist_lock);
         return ret_stuff.status;
diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h
deleted file mode 100644
index aa00d42cde32..000000000000
--- a/include/asm-ia64/sn/sndrv.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2002-2004 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#ifndef _ASM_IA64_SN_SNDRV_H
-#define _ASM_IA64_SN_SNDRV_H
-
-/* ioctl commands */
-#define SNDRV_GET_ROUTERINFO            1
-#define SNDRV_GET_INFOSIZE              2
-#define SNDRV_GET_HUBINFO               3
-#define SNDRV_GET_FLASHLOGSIZE          4
-#define SNDRV_SET_FLASHSYNC             5
-#define SNDRV_GET_FLASHLOGDATA          6
-#define SNDRV_GET_FLASHLOGALL           7
-
-#define SNDRV_SET_HISTOGRAM_TYPE        14
-
-#define SNDRV_ELSC_COMMAND              19
-#define SNDRV_CLEAR_LOG                 20
-#define SNDRV_INIT_LOG                  21
-#define SNDRV_GET_PIMM_PSC              22
-#define SNDRV_SET_PARTITION             23
-#define SNDRV_GET_PARTITION             24
-
-/* see synergy_perf_ioctl() */
-#define SNDRV_GET_SYNERGY_VERSION       30
-#define SNDRV_GET_SYNERGY_STATUS        31
-#define SNDRV_GET_SYNERGYINFO           32
-#define SNDRV_SYNERGY_APPEND            33
-#define SNDRV_SYNERGY_ENABLE            34
-#define SNDRV_SYNERGY_FREQ              35
-
-/* Devices */
-#define SNDRV_UKNOWN_DEVICE             -1
-#define SNDRV_ROUTER_DEVICE             1
-#define SNDRV_HUB_DEVICE                2
-#define SNDRV_ELSC_NVRAM_DEVICE         3
-#define SNDRV_ELSC_CONTROLLER_DEVICE    4
-#define SNDRV_SYSCTL_SUBCH              5
-#define SNDRV_SYNERGY_DEVICE            6
-
-#endif /* _ASM_IA64_SN_SNDRV_H */
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h
new file mode 100644
index 000000000000..9902185c0288
--- /dev/null
+++ b/include/asm-ia64/sn/xp.h
@@ -0,0 +1,436 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+/*
+ * External Cross Partition (XP) structures and defines.
+ */
+
+
+#ifndef _ASM_IA64_SN_XP_H
+#define _ASM_IA64_SN_XP_H
+
+
+#include <linux/version.h>
+#include <linux/cache.h>
+#include <linux/hardirq.h>
+#include <asm/sn/types.h>
+#include <asm/sn/bte.h>
+
+
+#ifdef USE_DBUG_ON
+#define DBUG_ON(condition)      BUG_ON(condition)
+#else
+#define DBUG_ON(condition)
+#endif
+
+
+/*
+ * Define the maximum number of logically defined partitions the system
+ * can support. It is constrained by the maximum number of hardware
+ * partitionable regions. The term 'region' in this context refers to the
+ * minimum number of nodes that can comprise an access protection grouping.
+ * The access protection is in regards to memory, IPI and IOI.
+ *
+ * The maximum number of hardware partitionable regions is equal to the
+ * maximum number of nodes in the entire system divided by the minimum number
+ * of nodes that comprise an access protection grouping.
+ */
+#define XP_MAX_PARTITIONS       64
+
+
+/*
+ * Define the number of u64s required to represent all the C-brick nasids
+ * as a bitmap.  The cross-partition kernel modules deal only with
+ * C-brick nasids, thus the need for bitmaps which don't account for
+ * odd-numbered (non C-brick) nasids.
+ */
+#define XP_MAX_PHYSNODE_ID      (MAX_PHYSNODE_ID / 2)
+#define XP_NASID_MASK_BYTES     ((XP_MAX_PHYSNODE_ID + 7) / 8)
+#define XP_NASID_MASK_WORDS     ((XP_MAX_PHYSNODE_ID + 63) / 64)
+
+
+/*
+ * Wrapper for bte_copy() that should it return a failure status will retry
+ * the bte_copy() once in the hope that the failure was due to a temporary
+ * aberration (i.e., the link going down temporarily).
+ *
+ * See bte_copy for definition of the input parameters.
+ *
+ * Note: xp_bte_copy() should never be called while holding a spinlock.
+ */
+static inline bte_result_t
+xp_bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
+{
+        bte_result_t ret;
+
+
+        ret = bte_copy(src, dest, len, mode, notification);
+
+        if (ret != BTE_SUCCESS) {
+                if (!in_interrupt()) {
+                        cond_resched();
+                }
+                ret = bte_copy(src, dest, len, mode, notification);
+        }
+
+        return ret;
+}
+
+
+/*
+ * XPC establishes channel connections between the local partition and any
+ * other partition that is currently up. Over these channels, kernel-level
+ * `users' can communicate with their counterparts on the other partitions.
+ *
+ * The maxinum number of channels is limited to eight. For performance reasons,
+ * the internal cross partition structures require sixteen bytes per channel,
+ * and eight allows all of this interface-shared info to fit in one cache line.
+ *
+ * XPC_NCHANNELS reflects the total number of channels currently defined.
+ * If the need for additional channels arises, one can simply increase
+ * XPC_NCHANNELS accordingly. If the day should come where that number
+ * exceeds the MAXIMUM number of channels allowed (eight), then one will need
+ * to make changes to the XPC code to allow for this.
+ */
+#define XPC_MEM_CHANNEL         0       /* memory channel number */
+#define XPC_NET_CHANNEL         1       /* network channel number */
+
+#define XPC_NCHANNELS           2       /* #of defined channels */
+#define XPC_MAX_NCHANNELS       8       /* max #of channels allowed */
+
+#if XPC_NCHANNELS > XPC_MAX_NCHANNELS
+#error  XPC_NCHANNELS exceeds MAXIMUM allowed.
+#endif
+
+
+/*
+ * The format of an XPC message is as follows:
+ *
+ *      +-------+--------------------------------+
+ *      | flags |////////////////////////////////|
+ *      +-------+--------------------------------+
+ *      |             message #                  |
+ *      +----------------------------------------+
+ *      |     payload (user-defined message)     |
+ *      |                                        |
+ *                      :
+ *      |                                        |
+ *      +----------------------------------------+
+ *
+ * The size of the payload is defined by the user via xpc_connect(). A user-
+ * defined message resides in the payload area.
+ *
+ * The user should have no dealings with the message header, but only the
+ * message's payload. When a message entry is allocated (via xpc_allocate())
+ * a pointer to the payload area is returned and not the actual beginning of
+ * the XPC message. The user then constructs a message in the payload area
+ * and passes that pointer as an argument on xpc_send() or xpc_send_notify().
+ *
+ * The size of a message entry (within a message queue) must be a cacheline
+ * sized multiple in order to facilitate the BTE transfer of messages from one
+ * message queue to another. A macro, XPC_MSG_SIZE(), is provided for the user
+ * that wants to fit as many msg entries as possible in a given memory size
+ * (e.g. a memory page).
+ */
+struct xpc_msg {
+        u8 flags;               /* FOR XPC INTERNAL USE ONLY */
+        u8 reserved[7];         /* FOR XPC INTERNAL USE ONLY */
+        s64 number;             /* FOR XPC INTERNAL USE ONLY */
+
+        u64 payload;            /* user defined portion of message */
+};
+
+
+#define XPC_MSG_PAYLOAD_OFFSET  (u64) (&((struct xpc_msg *)0)->payload)
+#define XPC_MSG_SIZE(_payload_size) \
+                L1_CACHE_ALIGN(XPC_MSG_PAYLOAD_OFFSET + (_payload_size))
+
+
+/*
+ * Define the return values and values passed to user's callout functions.
+ * (It is important to add new value codes at the end just preceding
+ * xpcUnknownReason, which must have the highest numerical value.)
+ */
+enum xpc_retval {
+        xpcSuccess = 0,
+
+        xpcNotConnected,        /*  1: channel is not connected */
+        xpcConnected,           /*  2: channel connected (opened) */
+        xpcRETIRED1,            /*  3: (formerly xpcDisconnected) */
+
+        xpcMsgReceived,         /*  4: message received */
+        xpcMsgDelivered,        /*  5: message delivered and acknowledged */
+
+        xpcRETIRED2,            /*  6: (formerly xpcTransferFailed) */
+
+        xpcNoWait,              /*  7: operation would require wait */
+        xpcRetry,               /*  8: retry operation */
+        xpcTimeout,             /*  9: timeout in xpc_allocate_msg_wait() */
+        xpcInterrupted,         /* 10: interrupted wait */
+
+        xpcUnequalMsgSizes,     /* 11: message size disparity between sides */
+        xpcInvalidAddress,      /* 12: invalid address */
+
+        xpcNoMemory,            /* 13: no memory available for XPC structures */
+        xpcLackOfResources,     /* 14: insufficient resources for operation */
+        xpcUnregistered,        /* 15: channel is not registered */
+        xpcAlreadyRegistered,   /* 16: channel is already registered */
+
+        xpcPartitionDown,       /* 17: remote partition is down */
+        xpcNotLoaded,           /* 18: XPC module is not loaded */
+        xpcUnloading,           /* 19: this side is unloading XPC module */
+
+        xpcBadMagic,            /* 20: XPC MAGIC string not found */
+
+        xpcReactivating,        /* 21: remote partition was reactivated */
+
+        xpcUnregistering,       /* 22: this side is unregistering channel */
+        xpcOtherUnregistering,  /* 23: other side is unregistering channel */
+
+        xpcCloneKThread,        /* 24: cloning kernel thread */
+        xpcCloneKThreadFailed,  /* 25: cloning kernel thread failed */
+
+        xpcNoHeartbeat,         /* 26: remote partition has no heartbeat */
+
+        xpcPioReadError,        /* 27: PIO read error */
+        xpcPhysAddrRegFailed,   /* 28: registration of phys addr range failed */
+
+        xpcBteDirectoryError,   /* 29: maps to BTEFAIL_DIR */
+        xpcBtePoisonError,      /* 30: maps to BTEFAIL_POISON */
+        xpcBteWriteError,       /* 31: maps to BTEFAIL_WERR */
+        xpcBteAccessError,      /* 32: maps to BTEFAIL_ACCESS */
+        xpcBtePWriteError,      /* 33: maps to BTEFAIL_PWERR */
+        xpcBtePReadError,       /* 34: maps to BTEFAIL_PRERR */
+        xpcBteTimeOutError,     /* 35: maps to BTEFAIL_TOUT */
+        xpcBteXtalkError,       /* 36: maps to BTEFAIL_XTERR */
+        xpcBteNotAvailable,     /* 37: maps to BTEFAIL_NOTAVAIL */
+        xpcBteUnmappedError,    /* 38: unmapped BTEFAIL_ error */
+
+        xpcBadVersion,          /* 39: bad version number */
+        xpcVarsNotSet,          /* 40: the XPC variables are not set up */
+        xpcNoRsvdPageAddr,      /* 41: unable to get rsvd page's phys addr */
+        xpcInvalidPartid,       /* 42: invalid partition ID */
+        xpcLocalPartid,         /* 43: local partition ID */
+
+        xpcUnknownReason        /* 44: unknown reason -- must be last in list */
+};
+
+
+/*
+ * Define the callout function types used by XPC to update the user on
+ * connection activity and state changes (via the user function registered by
+ * xpc_connect()) and to notify them of messages received and delivered (via
+ * the user function registered by xpc_send_notify()).
+ *
+ * The two function types are xpc_channel_func and xpc_notify_func and
+ * both share the following arguments, with the exception of "data", which
+ * only xpc_channel_func has.
+ *
+ * Arguments:
+ *
+ *      reason - reason code. (See following table.)
+ *      partid - partition ID associated with condition.
+ *      ch_number - channel # associated with condition.
+ *      data - pointer to optional data. (See following table.)
+ *      key - pointer to optional user-defined value provided as the "key"
+ *            argument to xpc_connect() or xpc_send_notify().
+ *
+ * In the following table the "Optional Data" column applies to callouts made
+ * to functions registered by xpc_connect(). A "NA" in that column indicates
+ * that this reason code can be passed to functions registered by
+ * xpc_send_notify() (i.e. they don't have data arguments).
+ *
+ * Also, the first three reason codes in the following table indicate
+ * success, whereas the others indicate failure. When a failure reason code
+ * is received, one can assume that the channel is not connected.
+ *
+ *
+ * Reason Code          | Cause                          | Optional Data
+ * =====================+================================+=====================
+ * xpcConnected         | connection has been established| max #of entries
+ *                      | to the specified partition on  | allowed in message
+ *                      | the specified channel          | queue
+ * ---------------------+--------------------------------+---------------------
+ * xpcMsgReceived       | an XPC message arrived from    | address of payload
+ *                      | the specified partition on the |
+ *                      | specified channel              | [the user must call
+ *                      |                                | xpc_received() when
+ *                      |                                | finished with the
+ *                      |                                | payload]
+ * ---------------------+--------------------------------+---------------------
+ * xpcMsgDelivered      | notification that the message  | NA
+ *                      | was delivered to the intended  |
+ *                      | recipient and that they have   |
+ *                      | acknowledged its receipt by    |
+ *                      | calling xpc_received()         |
+ * =====================+================================+=====================
+ * xpcUnequalMsgSizes   | can't connect to the specified | NULL
+ *                      | partition on the specified     |
+ *                      | channel because of mismatched  |
+ *                      | message sizes                  |
+ * ---------------------+--------------------------------+---------------------
+ * xpcNoMemory          | insufficient memory avaiable   | NULL
+ *                      | to allocate message queue      |
+ * ---------------------+--------------------------------+---------------------
+ * xpcLackOfResources   | lack of resources to create    | NULL
+ *                      | the necessary kthreads to      |
+ *                      | support the channel            |
+ * ---------------------+--------------------------------+---------------------
+ * xpcUnregistering     | this side's user has           | NULL or NA
+ *                      | unregistered by calling        |
+ *                      | xpc_disconnect()               |
+ * ---------------------+--------------------------------+---------------------
+ * xpcOtherUnregistering| the other side's user has      | NULL or NA
+ *                      | unregistered by calling        |
+ *                      | xpc_disconnect()               |
+ * ---------------------+--------------------------------+---------------------
+ * xpcNoHeartbeat       | the other side's XPC is no     | NULL or NA
+ *                      | longer heartbeating            |
+ *                      |                                |
+ * ---------------------+--------------------------------+---------------------
+ * xpcUnloading         | this side's XPC module is      | NULL or NA
+ *                      | being unloaded                 |
+ *                      |                                |
+ * ---------------------+--------------------------------+---------------------
+ * xpcOtherUnloading    | the other side's XPC module is | NULL or NA
+ *                      | is being unloaded              |
+ *                      |                                |
+ * ---------------------+--------------------------------+---------------------
+ * xpcPioReadError      | xp_nofault_PIOR() returned an  | NULL or NA
+ *                      | error while sending an IPI     |
+ *                      |                                |
+ * ---------------------+--------------------------------+---------------------
+ * xpcInvalidAddress    | the address either received or | NULL or NA
+ *                      | sent by the specified partition|
+ *                      | is invalid                     |
+ * ---------------------+--------------------------------+---------------------
+ * xpcBteNotAvailable   | attempt to pull data from the  | NULL or NA
+ * xpcBtePoisonError    | specified partition over the   |
+ * xpcBteWriteError     | specified channel via a        |
+ * xpcBteAccessError    | bte_copy() failed              |
+ * xpcBteTimeOutError   |                                |
+ * xpcBteXtalkError     |                                |
+ * xpcBteDirectoryError |                                |
+ * xpcBteGenericError   |                                |
+ * xpcBteUnmappedError  |                                |
+ * ---------------------+--------------------------------+---------------------
+ * xpcUnknownReason     | the specified channel to the   | NULL or NA
+ *                      | specified partition was        |
+ *                      | unavailable for unknown reasons|
+ * =====================+================================+=====================
+ */
+
+typedef void (*xpc_channel_func)(enum xpc_retval reason, partid_t partid,
+                int ch_number, void *data, void *key);
+
+typedef void (*xpc_notify_func)(enum xpc_retval reason, partid_t partid,
+                int ch_number, void *key);
+
+
+/*
+ * The following is a registration entry. There is a global array of these,
+ * one per channel. It is used to record the connection registration made
+ * by the users of XPC. As long as a registration entry exists, for any
+ * partition that comes up, XPC will attempt to establish a connection on
+ * that channel. Notification that a connection has been made will occur via
+ * the xpc_channel_func function.
+ *
+ * The 'func' field points to the function to call when aynchronous
+ * notification is required for such events as: a connection established/lost,
+ * or an incomming message received, or an error condition encountered. A
+ * non-NULL 'func' field indicates that there is an active registration for
+ * the channel.
+ */
+struct xpc_registration {
+        struct semaphore sema;
+        xpc_channel_func func;          /* function to call */
+        void *key;                      /* pointer to user's key */
+        u16 nentries;                   /* #of msg entries in local msg queue */
+        u16 msg_size;                   /* message queue's message size */
+        u32 assigned_limit;             /* limit on #of assigned kthreads */
+        u32 idle_limit;                 /* limit on #of idle kthreads */
+} ____cacheline_aligned;
+
+
+#define XPC_CHANNEL_REGISTERED(_c)      (xpc_registrations[_c].func != NULL)
+
+
+/* the following are valid xpc_allocate() flags */
+#define XPC_WAIT        0               /* wait flag */
+#define XPC_NOWAIT      1               /* no wait flag */
+
+
+struct xpc_interface {
+        void (*connect)(int);
+        void (*disconnect)(int);
+        enum xpc_retval (*allocate)(partid_t, int, u32, void **);
+        enum xpc_retval (*send)(partid_t, int, void *);
+        enum xpc_retval (*send_notify)(partid_t, int, void *,
+                                                xpc_notify_func, void *);
+        void (*received)(partid_t, int, void *);
+        enum xpc_retval (*partid_to_nasids)(partid_t, void *);
+};
+
+
+extern struct xpc_interface xpc_interface;
+
+extern void xpc_set_interface(void (*)(int),
+                void (*)(int),
+                enum xpc_retval (*)(partid_t, int, u32, void **),
+                enum xpc_retval (*)(partid_t, int, void *),
+                enum xpc_retval (*)(partid_t, int, void *, xpc_notify_func,
+                                                                void *),
+                void (*)(partid_t, int, void *),
+                enum xpc_retval (*)(partid_t, void *));
+extern void xpc_clear_interface(void);
+
+
+extern enum xpc_retval xpc_connect(int, xpc_channel_func, void *, u16,
+                                                u16, u32, u32);
+extern void xpc_disconnect(int);
+
+static inline enum xpc_retval
+xpc_allocate(partid_t partid, int ch_number, u32 flags, void **payload)
+{
+        return xpc_interface.allocate(partid, ch_number, flags, payload);
+}
+
+static inline enum xpc_retval
+xpc_send(partid_t partid, int ch_number, void *payload)
+{
+        return xpc_interface.send(partid, ch_number, payload);
+}
+
+static inline enum xpc_retval
+xpc_send_notify(partid_t partid, int ch_number, void *payload,
+                        xpc_notify_func func, void *key)
+{
+        return xpc_interface.send_notify(partid, ch_number, payload, func, key);
+}
+
+static inline void
+xpc_received(partid_t partid, int ch_number, void *payload)
+{
+        return xpc_interface.received(partid, ch_number, payload);
+}
+
+static inline enum xpc_retval
+xpc_partid_to_nasids(partid_t partid, void *nasids)
+{
+        return xpc_interface.partid_to_nasids(partid, nasids);
+}
+
+
+extern u64 xp_nofault_PIOR_target;
+extern int xp_nofault_PIOR(void *);
+extern int xp_error_PIOR(void);
+
+
+#endif /* _ASM_IA64_SN_XP_H */
+
diff --git a/include/asm-m32r/signal.h b/include/asm-m32r/signal.h
index 6e55fd421883..95f69b191953 100644
--- a/include/asm-m32r/signal.h
+++ b/include/asm-m32r/signal.h
@@ -114,20 +114,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-m68k/signal.h b/include/asm-m68k/signal.h
index 1d016e9f19bf..a0cdf9082372 100644
--- a/include/asm-m68k/signal.h
+++ b/include/asm-m68k/signal.h
@@ -105,29 +105,20 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
         __sighandler_t sa_handler;
         old_sigset_t sa_mask;
         unsigned long sa_flags;
-        void (*sa_restorer)(void);
+        __sigrestore_t sa_restorer;
 };
 
 struct sigaction {
         __sighandler_t sa_handler;
         unsigned long sa_flags;
-        void (*sa_restorer)(void);
+        __sigrestore_t sa_restorer;
         sigset_t sa_mask;               /* mask last for extensibility */
 };
 
diff --git a/include/asm-m68knommu/signal.h b/include/asm-m68knommu/signal.h
index 37c9c8a024ba..1d13187f6062 100644
--- a/include/asm-m68knommu/signal.h
+++ b/include/asm-m68knommu/signal.h
@@ -105,16 +105,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index d81356731eb6..f2c470f1d369 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -103,14 +103,7 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define SIG_SETMASK     3       /* for setting the signal mask */
 #define SIG_SETMASK32   256     /* Goodie from SGI for BSD compatibility:
                                    set only the low 32 bit of the sigset.  */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-/* Fake signal functions */
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 struct sigaction {
         unsigned int    sa_flags;
diff --git a/include/asm-parisc/floppy.h b/include/asm-parisc/floppy.h
index 47f53df2cef5..ca3aed768cdc 100644
--- a/include/asm-parisc/floppy.h
+++ b/include/asm-parisc/floppy.h
@@ -235,7 +235,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
         return 0;
 }
 
-struct fd_routine_l {
+static struct fd_routine_l {
         int (*_request_dma)(unsigned int dmanr, const char * device_id);
         void (*_free_dma)(unsigned int dmanr);
         int (*_get_dma_residue)(unsigned int dummy);
diff --git a/include/asm-ppc/agp.h b/include/asm-ppc/agp.h
index be27cfa8c5b0..ca9e423307f4 100644
--- a/include/asm-ppc/agp.h
+++ b/include/asm-ppc/agp.h
@@ -10,4 +10,14 @@
 #define flush_agp_mappings()
 #define flush_agp_cache() mb()
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 42fd1068cf2a..c5883dbed63f 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1039,6 +1039,52 @@ typedef struct im_idma {
 #define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
 #define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
 
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register                            4-31
+ */
+#define SIUMCR_BBD      0x80000000      /* Bus Busy Disable             */
+#define SIUMCR_ESE      0x40000000      /* External Snoop Enable        */
+#define SIUMCR_PBSE     0x20000000      /* Parity Byte Select Enable    */
+#define SIUMCR_CDIS     0x10000000      /* Core Disable                 */
+#define SIUMCR_DPPC00   0x00000000      /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01   0x04000000      /* - " -                        */
+#define SIUMCR_DPPC10   0x08000000      /* - " -                        */
+#define SIUMCR_DPPC11   0x0c000000      /* - " -                        */
+#define SIUMCR_L2CPC00  0x00000000      /* L2 Cache Pins Configuration  */
+#define SIUMCR_L2CPC01  0x01000000      /* - " -                        */
+#define SIUMCR_L2CPC10  0x02000000      /* - " -                        */
+#define SIUMCR_L2CPC11  0x03000000      /* - " -                        */
+#define SIUMCR_LBPC00   0x00000000      /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01   0x00400000      /* - " -                        */
+#define SIUMCR_LBPC10   0x00800000      /* - " -                        */
+#define SIUMCR_LBPC11   0x00c00000      /* - " -                        */
+#define SIUMCR_APPC00   0x00000000      /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01   0x00100000      /* - " -                        */
+#define SIUMCR_APPC10   0x00200000      /* - " -                        */
+#define SIUMCR_APPC11   0x00300000      /* - " -                        */
+#define SIUMCR_CS10PC00 0x00000000      /* CS10 Pin Configuration       */
+#define SIUMCR_CS10PC01 0x00040000      /* - " -                        */
+#define SIUMCR_CS10PC10 0x00080000      /* - " -                        */
+#define SIUMCR_CS10PC11 0x000c0000      /* - " -                        */
+#define SIUMCR_BCTLC00  0x00000000      /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01  0x00010000      /* - " -                        */
+#define SIUMCR_BCTLC10  0x00020000      /* - " -                        */
+#define SIUMCR_BCTLC11  0x00030000      /* - " -                        */
+#define SIUMCR_MMR00    0x00000000      /* Mask Masters Requests        */
+#define SIUMCR_MMR01    0x00004000      /* - " -                        */
+#define SIUMCR_MMR10    0x00008000      /* - " -                        */
+#define SIUMCR_MMR11    0x0000c000      /* - " -                        */
+#define SIUMCR_LPBSE    0x00002000      /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register                                  9-8
+*/
+#define SCCR_PCI_MODE   0x00000100      /* PCI Mode     */
+#define SCCR_PCI_MODCK  0x00000080      /* Value of PCI_MODCK pin       */
+#define SCCR_PCIDF_MSK  0x00000078      /* PCI division factor  */
+#define SCCR_PCIDF_SHIFT 3
+
+
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
index 163a6b91d5b2..bf9e05dd54b5 100644
--- a/include/asm-ppc/m8260_pci.h
+++ b/include/asm-ppc/m8260_pci.h
@@ -19,6 +19,7 @@
  * Define the vendor/device ID for the MPC8265.
  */
 #define PCI_DEVICE_ID_MPC8265   ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272   ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
 
 #define M8265_PCIBR0    0x101ac
 #define M8265_PCIBR1    0x101b0
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index d820894e5991..89eb8a2ac693 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -41,7 +41,7 @@
 #endif
 
 #ifdef CONFIG_PCI_8260
-#include <syslib/m8260_pci.h>
+#include <syslib/m82xx_pci.h>
 #endif
 
 /* Make sure the memory translation stuff is there if PCI not used.
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
index f82dcccdee1e..b7a417e0a921 100644
--- a/include/asm-ppc/sigcontext.h
+++ b/include/asm-ppc/sigcontext.h
@@ -2,7 +2,7 @@
 #define _ASM_PPC_SIGCONTEXT_H
 
 #include <asm/ptrace.h>
-
+#include <linux/compiler.h>
 
 struct sigcontext {
         unsigned long   _unused[4];
diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h
index d890dabd5a69..caf6ede3710f 100644
--- a/include/asm-ppc/signal.h
+++ b/include/asm-ppc/signal.h
@@ -100,20 +100,7 @@ typedef struct {
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 struct old_sigaction {
         __sighandler_t sa_handler;
diff --git a/include/asm-ppc64/agp.h b/include/asm-ppc64/agp.h
index be27cfa8c5b0..ca9e423307f4 100644
--- a/include/asm-ppc64/agp.h
+++ b/include/asm-ppc64/agp.h
@@ -10,4 +10,14 @@
 #define flush_agp_mappings()
 #define flush_agp_cache() mb()
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif
diff --git a/include/asm-ppc64/elf.h b/include/asm-ppc64/elf.h
index 6c42d61bedd1..085eedb956fe 100644
--- a/include/asm-ppc64/elf.h
+++ b/include/asm-ppc64/elf.h
@@ -221,9 +221,7 @@ do {								\
                 set_thread_flag(TIF_ABI_PENDING);               \
         else                                                    \
                 clear_thread_flag(TIF_ABI_PENDING);             \
-        if (ibcs2)                                              \
-                set_personality(PER_SVR4);                      \
-        else if (current->personality != PER_LINUX32)           \
+        if (personality(current->personality) != PER_LINUX32)   \
                 set_personality(PER_LINUX);                     \
 } while (0)
 
diff --git a/include/asm-ppc64/iSeries/mf.h b/include/asm-ppc64/iSeries/mf.h
index 2e59a8e15a0b..db333e1ee216 100644
--- a/include/asm-ppc64/iSeries/mf.h
+++ b/include/asm-ppc64/iSeries/mf.h
@@ -52,6 +52,7 @@ extern void mf_clear_src(void);
 extern void mf_init(void);
 
 extern int mf_get_rtc(struct rtc_time *tm);
+extern int mf_get_boot_rtc(struct rtc_time *tm);
 extern int mf_set_rtc(struct rtc_time *tm);
 
 #endif /* _ASM_PPC64_ISERIES_MF_H */
diff --git a/include/asm-ppc64/imalloc.h b/include/asm-ppc64/imalloc.h
new file mode 100644
index 000000000000..3a45e918bf16
--- /dev/null
+++ b/include/asm-ppc64/imalloc.h
@@ -0,0 +1,24 @@
+#ifndef _PPC64_IMALLOC_H
+#define _PPC64_IMALLOC_H
+
+/*
+ * Define the address range of the imalloc VM area.
+ */
+#define PHBS_IO_BASE      IOREGIONBASE
+#define IMALLOC_BASE      (IOREGIONBASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
+#define IMALLOC_END       (IOREGIONBASE + EADDR_MASK)
+
+
+/* imalloc region types */
+#define IM_REGION_UNUSED        0x1
+#define IM_REGION_SUBSET        0x2
+#define IM_REGION_EXISTS        0x4
+#define IM_REGION_OVERLAP       0x8
+#define IM_REGION_SUPERSET      0x10
+
+extern struct vm_struct * im_get_free_area(unsigned long size);
+extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size,
+                        int region_type);
+unsigned long im_free(void *addr);
+
+#endif /* _PPC64_IMALLOC_H */
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 188987e9d9d4..c78282a67d8e 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -15,19 +15,10 @@
 
 #include <linux/config.h>
 #include <asm/page.h>
-#include <linux/stringify.h>
 
-#ifndef __ASSEMBLY__
-
-/* Time to allow for more things here */
-typedef unsigned long mm_context_id_t;
-typedef struct {
-        mm_context_id_t id;
-#ifdef CONFIG_HUGETLB_PAGE
-        pgd_t *huge_pgdir;
-        u16 htlb_segs; /* bitmask */
-#endif
-} mm_context_t;
+/*
+ * Segment table
+ */
 
 #define STE_ESID_V      0x80
 #define STE_ESID_KS     0x20
@@ -36,15 +27,48 @@ typedef struct {
 
 #define STE_VSID_SHIFT  12
 
-struct stab_entry {
-        unsigned long esid_data;
-        unsigned long vsid_data;
-};
+/* Location of cpu0's segment table */
+#define STAB0_PAGE      0x9
+#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
+#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
+
+/*
+ * SLB
+ */
 
-/* Hardware Page Table Entry */
+#define SLB_NUM_BOLTED          3
+#define SLB_CACHE_ENTRIES       8
+
+/* Bits in the SLB ESID word */
+#define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
+
+/* Bits in the SLB VSID word */
+#define SLB_VSID_SHIFT          12
+#define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
+#define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
+#define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
+#define SLB_VSID_L              ASM_CONST(0x0000000000000100) /* largepage 16M */
+#define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
+
+#define SLB_VSID_KERNEL         (SLB_VSID_KP|SLB_VSID_C)
+#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS)
+
+/*
+ * Hash table
+ */
 
 #define HPTES_PER_GROUP 8
 
+/* Values for PP (assumes Ks=0, Kp=1) */
+/* pp0 will always be 0 for linux     */
+#define PP_RWXX 0       /* Supervisor read/write, User none */
+#define PP_RWRX 1       /* Supervisor read/write, User read */
+#define PP_RWRW 2       /* Supervisor read/write, User read/write */
+#define PP_RXRX 3       /* Supervisor read,       User read */
+
+#ifndef __ASSEMBLY__
+
+/* Hardware Page Table Entry */
 typedef struct {
         unsigned long avpn:57; /* vsid | api == avpn  */
         unsigned long :     2; /* Software use */
@@ -90,14 +114,6 @@ typedef struct {
         } dw1;
 } HPTE; 
 
-/* Values for PP (assumes Ks=0, Kp=1) */
-/* pp0 will always be 0 for linux     */
-#define PP_RWXX 0       /* Supervisor read/write, User none */
-#define PP_RWRX 1       /* Supervisor read/write, User read */
-#define PP_RWRW 2       /* Supervisor read/write, User read/write */
-#define PP_RXRX 3       /* Supervisor read,       User read */
-
-
 extern HPTE *           htab_address;
 extern unsigned long    htab_hash_mask;
 
@@ -174,31 +190,70 @@ extern int __hash_page(unsigned long ea, unsigned long access,
 
 extern void htab_finish_init(void);
 
+extern void hpte_init_native(void);
+extern void hpte_init_lpar(void);
+extern void hpte_init_iSeries(void);
+
+extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
+                                     unsigned long va, unsigned long prpn,
+                                     int secondary, unsigned long hpteflags,
+                                     int bolted, int large);
+extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
+                               unsigned long prpn, int secondary,
+                               unsigned long hpteflags, int bolted, int large);
+
 #endif /* __ASSEMBLY__ */
 
 /*
- * Location of cpu0's segment table
+ * VSID allocation
+ *
+ * We first generate a 36-bit "proto-VSID".  For kernel addresses this
+ * is equal to the ESID, for user addresses it is:
+ *      (context << 15) | (esid & 0x7fff)
+ *
+ * The two forms are distinguishable because the top bit is 0 for user
+ * addresses, whereas the top two bits are 1 for kernel addresses.
+ * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
+ * now.
+ *
+ * The proto-VSIDs are then scrambled into real VSIDs with the
+ * multiplicative hash:
+ *
+ *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
+ *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
+ *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
+ *
+ * This scramble is only well defined for proto-VSIDs below
+ * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
+ * reserved.  VSID_MULTIPLIER is prime, so in particular it is
+ * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
+ * Because the modulus is 2^n-1 we can compute it efficiently without
+ * a divide or extra multiply (see below).
+ *
+ * This scheme has several advantages over older methods:
+ *
+ *      - We have VSIDs allocated for every kernel address
+ * (i.e. everything above 0xC000000000000000), except the very top
+ * segment, which simplifies several things.
+ *
+ *      - We allow for 15 significant bits of ESID and 20 bits of
+ * context for user addresses.  i.e. 8T (43 bits) of address space for
+ * up to 1M contexts (although the page table structure and context
+ * allocation will need changes to take advantage of this).
+ *
+ *      - The scramble function gives robust scattering in the hash
+ * table (at least based on some initial results).  The previous
+ * method was more susceptible to pathological cases giving excessive
+ * hash collisions.
+ */
+/*
+ * WARNING - If you change these you must make sure the asm
+ * implementations in slb_allocate (slb_low.S), do_stab_bolted
+ * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
+ *
+ * You'll also need to change the precomputed VSID values in head.S
+ * which are used by the iSeries firmware.
  */
-#define STAB0_PAGE      0x9
-#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
-#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
-
-#define SLB_NUM_BOLTED          3
-#define SLB_CACHE_ENTRIES       8
-
-/* Bits in the SLB ESID word */
-#define SLB_ESID_V              0x0000000008000000      /* entry is valid */
-
-/* Bits in the SLB VSID word */
-#define SLB_VSID_SHIFT          12
-#define SLB_VSID_KS             0x0000000000000800
-#define SLB_VSID_KP             0x0000000000000400
-#define SLB_VSID_N              0x0000000000000200      /* no-execute */
-#define SLB_VSID_L              0x0000000000000100      /* largepage (4M) */
-#define SLB_VSID_C              0x0000000000000080      /* class */
-
-#define SLB_VSID_KERNEL         (SLB_VSID_KP|SLB_VSID_C)
-#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS)
 
 #define VSID_MULTIPLIER ASM_CONST(200730139)    /* 28-bit prime */
 #define VSID_BITS       36
@@ -239,4 +294,50 @@ extern void htab_finish_init(void);
         srdi    rx,rx,VSID_BITS;        /* extract 2^36 bit */          \
         add     rt,rt,rx
 
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+        mm_context_id_t id;
+#ifdef CONFIG_HUGETLB_PAGE
+        pgd_t *huge_pgdir;
+        u16 htlb_segs; /* bitmask */
+#endif
+} mm_context_t;
+
+
+static inline unsigned long vsid_scramble(unsigned long protovsid)
+{
+#if 0
+        /* The code below is equivalent to this function for arguments
+         * < 2^VSID_BITS, which is all this should ever be called
+         * with.  However gcc is not clever enough to compute the
+         * modulus (2^n-1) without a second multiply. */
+        return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
+#else /* 1 */
+        unsigned long x;
+
+        x = protovsid * VSID_MULTIPLIER;
+        x = (x >> VSID_BITS) + (x & VSID_MODULUS);
+        return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
+#endif /* 1 */
+}
+
+/* This is only valid for addresses >= KERNELBASE */
+static inline unsigned long get_kernel_vsid(unsigned long ea)
+{
+        return vsid_scramble(ea >> SID_SHIFT);
+}
+
+/* This is only valid for user addresses (which are below 2^41) */
+static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
+{
+        return vsid_scramble((context << USER_ESID_BITS)
+                             | (ea >> SID_SHIFT));
+}
+
+#endif /* __ASSEMBLY */
+
 #endif /* _PPC64_MMU_H_ */
diff --git a/include/asm-ppc64/mmu_context.h b/include/asm-ppc64/mmu_context.h
index c2e8e0466383..77a743402db4 100644
--- a/include/asm-ppc64/mmu_context.h
+++ b/include/asm-ppc64/mmu_context.h
@@ -84,86 +84,4 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
         local_irq_restore(flags);
 }
 
-/* VSID allocation
- * ===============
- *
- * We first generate a 36-bit "proto-VSID".  For kernel addresses this
- * is equal to the ESID, for user addresses it is:
- *      (context << 15) | (esid & 0x7fff)
- *
- * The two forms are distinguishable because the top bit is 0 for user
- * addresses, whereas the top two bits are 1 for kernel addresses.
- * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
- * now.
- *
- * The proto-VSIDs are then scrambled into real VSIDs with the
- * multiplicative hash:
- *
- *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
- *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
- *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
- *
- * This scramble is only well defined for proto-VSIDs below
- * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
- * reserved.  VSID_MULTIPLIER is prime, so in particular it is
- * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
- * Because the modulus is 2^n-1 we can compute it efficiently without
- * a divide or extra multiply (see below).
- *
- * This scheme has several advantages over older methods:
- *
- *      - We have VSIDs allocated for every kernel address
- * (i.e. everything above 0xC000000000000000), except the very top
- * segment, which simplifies several things.
- *
- *      - We allow for 15 significant bits of ESID and 20 bits of
- * context for user addresses.  i.e. 8T (43 bits) of address space for
- * up to 1M contexts (although the page table structure and context
- * allocation will need changes to take advantage of this).
- *
- *      - The scramble function gives robust scattering in the hash
- * table (at least based on some initial results).  The previous
- * method was more susceptible to pathological cases giving excessive
- * hash collisions.
- */
-
-/*
- * WARNING - If you change these you must make sure the asm
- * implementations in slb_allocate(), do_stab_bolted and mmu.h
- * (ASM_VSID_SCRAMBLE macro) are changed accordingly.
- *
- * You'll also need to change the precomputed VSID values in head.S
- * which are used by the iSeries firmware.
- */
-
-static inline unsigned long vsid_scramble(unsigned long protovsid)
-{
-#if 0
-        /* The code below is equivalent to this function for arguments
-         * < 2^VSID_BITS, which is all this should ever be called
-         * with.  However gcc is not clever enough to compute the
-         * modulus (2^n-1) without a second multiply. */
-        return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
-#else /* 1 */
-        unsigned long x;
-
-        x = protovsid * VSID_MULTIPLIER;
-        x = (x >> VSID_BITS) + (x & VSID_MODULUS);
-        return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
-#endif /* 1 */
-}
-
-/* This is only valid for addresses >= KERNELBASE */
-static inline unsigned long get_kernel_vsid(unsigned long ea)
-{
-        return vsid_scramble(ea >> SID_SHIFT);
-}
-
-/* This is only valid for user addresses (which are below 2^41) */
-static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
-{
-        return vsid_scramble((context << USER_ESID_BITS)
-                             | (ea >> SID_SHIFT));
-}
-
 #endif /* __PPC64_MMU_CONTEXT_H */
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
index 86219574c1a5..bcd21789d3b7 100644
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -23,7 +23,6 @@
 #define PAGE_SHIFT      12
 #define PAGE_SIZE       (ASM_CONST(1) << PAGE_SHIFT)
 #define PAGE_MASK       (~(PAGE_SIZE-1))
-#define PAGE_OFFSET_MASK (PAGE_SIZE-1)
 
 #define SID_SHIFT       28
 #define SID_MASK        0xfffffffffUL
@@ -85,9 +84,6 @@
 /* align addr on a size boundary - adjust address up if needed */
 #define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
 
-/* to align the pointer to the (next) double word boundary */
-#define DOUBLEWORD_ALIGN(addr)  _ALIGN(addr,sizeof(unsigned long))
-
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        _ALIGN(addr, PAGE_SIZE)
 
@@ -100,7 +96,6 @@
 #define REGION_SIZE   4UL
 #define REGION_SHIFT  60UL
 #define REGION_MASK   (((1UL<<REGION_SIZE)-1UL)<<REGION_SHIFT)
-#define REGION_STRIDE (1UL << REGION_SHIFT)
 
 static __inline__ void clear_page(void *addr)
 {
@@ -209,13 +204,13 @@ extern u64 ppc64_pft_size;		/* Log 2 of page table size */
 #define VMALLOCBASE     ASM_CONST(0xD000000000000000)
 #define IOREGIONBASE    ASM_CONST(0xE000000000000000)
 
-#define IO_REGION_ID       (IOREGIONBASE>>REGION_SHIFT)
-#define VMALLOC_REGION_ID  (VMALLOCBASE>>REGION_SHIFT)
-#define KERNEL_REGION_ID   (KERNELBASE>>REGION_SHIFT)
+#define IO_REGION_ID       (IOREGIONBASE >> REGION_SHIFT)
+#define VMALLOC_REGION_ID  (VMALLOCBASE >> REGION_SHIFT)
+#define KERNEL_REGION_ID   (KERNELBASE >> REGION_SHIFT)
 #define USER_REGION_ID     (0UL)
-#define REGION_ID(X)       (((unsigned long)(X))>>REGION_SHIFT)
+#define REGION_ID(ea)      (((unsigned long)(ea)) >> REGION_SHIFT)
 
-#define __bpn_to_ba(x) ((((unsigned long)(x))<<PAGE_SHIFT) + KERNELBASE)
+#define __bpn_to_ba(x) ((((unsigned long)(x)) << PAGE_SHIFT) + KERNELBASE)
 #define __ba_to_bpn(x) ((((unsigned long)(x)) & ~REGION_MASK) >> PAGE_SHIFT)
 
 #define __va(x) ((void *)((unsigned long)(x) + KERNELBASE))
diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h
index b984e2747e0c..264c4f7993be 100644
--- a/include/asm-ppc64/pgtable.h
+++ b/include/asm-ppc64/pgtable.h
@@ -17,16 +17,6 @@
 
 #include <asm-generic/pgtable-nopud.h>
 
-/* PMD_SHIFT determines what a second-level page table entry can map */
-#define PMD_SHIFT       (PAGE_SHIFT + PAGE_SHIFT - 3)
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT - 3) + (PAGE_SHIFT - 2))
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK      (~(PGDIR_SIZE-1))
-
 /*
  * Entries per page directory level.  The PTE level must use a 64b record
  * for each page table entry.  The PMD and PGD level use a 32b record for 
@@ -40,40 +30,30 @@
 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
 
-#define USER_PTRS_PER_PGD       (1024)
-#define FIRST_USER_ADDRESS      0
+/* PMD_SHIFT determines what a second-level page table entry can map */
+#define PMD_SHIFT       (PAGE_SHIFT + PTE_INDEX_SIZE)
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
 
-#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
-                    PGD_INDEX_SIZE + PAGE_SHIFT) 
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     (PMD_SHIFT + PMD_INDEX_SIZE)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+#define FIRST_USER_ADDRESS      0
 
 /*
  * Size of EA range mapped by our pagetables.
  */
-#define PGTABLE_EA_BITS 41
-#define PGTABLE_EA_MASK ((1UL<<PGTABLE_EA_BITS)-1)
+#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
+                    PGD_INDEX_SIZE + PAGE_SHIFT)
+#define EADDR_MASK ((1UL << EADDR_SIZE) - 1)
 
 /*
  * Define the address range of the vmalloc VM area.
  */
 #define VMALLOC_START (0xD000000000000000ul)
-#define VMALLOC_END   (VMALLOC_START + PGTABLE_EA_MASK)
-
-/*
- * Define the address range of the imalloc VM area.
- * (used for ioremap)
- */
-#define IMALLOC_START     (ioremap_bot)
-#define IMALLOC_VMADDR(x) ((unsigned long)(x))
-#define PHBS_IO_BASE      (0xE000000000000000ul)        /* Reserve 2 gigs for PHBs */
-#define IMALLOC_BASE      (0xE000000080000000ul)  
-#define IMALLOC_END       (IMALLOC_BASE + PGTABLE_EA_MASK)
-
-/*
- * Define the user address range
- */
-#define USER_START (0UL)
-#define USER_END   (USER_START + PGTABLE_EA_MASK)
-
+#define VMALLOC_END   (VMALLOC_START + EADDR_MASK)
 
 /*
  * Bits in a linux-style PTE.  These match the bits in the
@@ -168,10 +148,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 /* shift to put page number into pte */
 #define PTE_SHIFT (17)
 
-/* We allow 2^41 bytes of real memory, so we need 29 bits in the PMD
- * to give the PTE page number.  The bottom two bits are for flags. */
-#define PMD_TO_PTEPAGE_SHIFT (2)
-
 #ifdef CONFIG_HUGETLB_PAGE
 
 #ifndef __ASSEMBLY__
@@ -200,13 +176,14 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm);
  */
 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 
-#define pfn_pte(pfn,pgprot)                                             \
-({                                                                      \
-        pte_t pte;                                                      \
-        pte_val(pte) = ((unsigned long)(pfn) << PTE_SHIFT) |            \
-                        pgprot_val(pgprot);                             \
-        pte;                                                            \
-})
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
+{
+        pte_t pte;
+
+
+        pte_val(pte) = (pfn << PTE_SHIFT) | pgprot_val(pgprot);
+        return pte;
+}
 
 #define pte_modify(_pte, newprot) \
   (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
@@ -220,13 +197,12 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm);
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 
 #define pmd_set(pmdp, ptep)     \
-        (pmd_val(*(pmdp)) = (__ba_to_bpn(ptep) << PMD_TO_PTEPAGE_SHIFT))
+        (pmd_val(*(pmdp)) = __ba_to_bpn(ptep))
 #define pmd_none(pmd)           (!pmd_val(pmd))
 #define pmd_bad(pmd)            (pmd_val(pmd) == 0)
 #define pmd_present(pmd)        (pmd_val(pmd) != 0)
 #define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
-#define pmd_page_kernel(pmd)    \
-        (__bpn_to_ba(pmd_val(pmd) >> PMD_TO_PTEPAGE_SHIFT))
+#define pmd_page_kernel(pmd)    (__bpn_to_ba(pmd_val(pmd)))
 #define pmd_page(pmd)           virt_to_page(pmd_page_kernel(pmd))
 
 #define pud_set(pudp, pmdp)     (pud_val(*(pudp)) = (__ba_to_bpn(pmdp)))
@@ -266,8 +242,6 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm);
 /* to find an entry in the ioremap page-table-directory */
 #define pgd_offset_i(address) (ioremap_pgd + pgd_index(address))
 
-#define pages_to_mb(x)          ((x) >> (20-PAGE_SHIFT))
-
 /*
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
@@ -442,7 +416,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
                 pte_clear(mm, addr, ptep);
                 flush_tlb_pending();
         }
-        *ptep = __pte(pte_val(pte)) & ~_PAGE_HPTEFLAGS;
+        *ptep = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
 }
 
 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
@@ -487,18 +461,13 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
 
 extern unsigned long ioremap_bot, ioremap_base;
 
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
 #define pmd_ERROR(e) \
         printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e))
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e))
 
-extern pgd_t swapper_pg_dir[1024];
-extern pgd_t ioremap_dir[1024];
+extern pgd_t swapper_pg_dir[];
+extern pgd_t ioremap_dir[];
 
 extern void paging_init(void);
 
@@ -540,43 +509,11 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
  */
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
-                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
-
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 void pgtable_cache_init(void);
 
-extern void hpte_init_native(void);
-extern void hpte_init_lpar(void);
-extern void hpte_init_iSeries(void);
-
-/* imalloc region types */
-#define IM_REGION_UNUSED        0x1
-#define IM_REGION_SUBSET        0x2
-#define IM_REGION_EXISTS        0x4
-#define IM_REGION_OVERLAP       0x8
-#define IM_REGION_SUPERSET      0x10
-
-extern struct vm_struct * im_get_free_area(unsigned long size);
-extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size,
-                        int region_type);
-unsigned long im_free(void *addr);
-
-extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
-                                     unsigned long va, unsigned long prpn,
-                                     int secondary, unsigned long hpteflags,
-                                     int bolted, int large);
-
-extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
-                               unsigned long prpn, int secondary,
-                               unsigned long hpteflags, int bolted, int large);
-
 /*
  * find_linux_pte returns the address of a linux pte for a given 
  * effective address and directory.  If not found, it returns zero.
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 0035efe2db2b..809c634ba1df 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -120,103 +120,18 @@
 
 /* Special Purpose Registers (SPRNs)*/
 
-#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
 #define SPRN_CTR        0x009   /* Count Register */
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
-#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
-#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
+#define   DABR_TRANSLATION      (1UL << 2)
 #define SPRN_DAR        0x013   /* Data Address Register */
-#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
-#define   DBCR_EDM      0x80000000
-#define   DBCR_IDM      0x40000000
-#define   DBCR_RST(x)   (((x) & 0x3) << 28)
-#define     DBCR_RST_NONE               0
-#define     DBCR_RST_CORE               1
-#define     DBCR_RST_CHIP               2
-#define     DBCR_RST_SYSTEM             3
-#define   DBCR_IC       0x08000000      /* Instruction Completion Debug Evnt */
-#define   DBCR_BT       0x04000000      /* Branch Taken Debug Event */
-#define   DBCR_EDE      0x02000000      /* Exception Debug Event */
-#define   DBCR_TDE      0x01000000      /* TRAP Debug Event */
-#define   DBCR_FER      0x00F80000      /* First Events Remaining Mask */
-#define   DBCR_FT       0x00040000      /* Freeze Timers on Debug Event */
-#define   DBCR_IA1      0x00020000      /* Instr. Addr. Compare 1 Enable */
-#define   DBCR_IA2      0x00010000      /* Instr. Addr. Compare 2 Enable */
-#define   DBCR_D1R      0x00008000      /* Data Addr. Compare 1 Read Enable */
-#define   DBCR_D1W      0x00004000      /* Data Addr. Compare 1 Write Enable */
-#define   DBCR_D1S(x)   (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
-#define     DAC_BYTE    0
-#define     DAC_HALF    1
-#define     DAC_WORD    2
-#define     DAC_QUAD    3
-#define   DBCR_D2R      0x00000800      /* Data Addr. Compare 2 Read Enable */
-#define   DBCR_D2W      0x00000400      /* Data Addr. Compare 2 Write Enable */
-#define   DBCR_D2S(x)   (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
-#define   DBCR_SBT      0x00000040      /* Second Branch Taken Debug Event */
-#define   DBCR_SED      0x00000020      /* Second Exception Debug Event */
-#define   DBCR_STD      0x00000010      /* Second Trap Debug Event */
-#define   DBCR_SIA      0x00000008      /* Second IAC Enable */
-#define   DBCR_SDA      0x00000004      /* Second DAC Enable */
-#define   DBCR_JOI      0x00000002      /* JTAG Serial Outbound Int. Enable */
-#define   DBCR_JII      0x00000001      /* JTAG Serial Inbound Int. Enable */
-#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
-#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */
-#define SPRN_DBSR       0x3F0   /* Debug Status Register */
-#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
-#define   DCCR_NOCACHE          0       /* Noncacheable */
-#define   DCCR_CACHE            1       /* Cacheable */
-#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
-#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
-#define   DCWR_COPY             0       /* Copy-back */
-#define   DCWR_WRITE            1       /* Write-through */
-#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 #define SPRN_DEC        0x016   /* Decrement Register */
-#define SPRN_DMISS      0x3D0   /* Data TLB Miss Register */
 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 #define   DSISR_NOHPTE          0x40000000      /* no translation found */
 #define   DSISR_PROTFAULT       0x08000000      /* protection fault */
 #define   DSISR_ISSTORE         0x02000000      /* access was a store */
 #define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
 #define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
-#define SPRN_EAR        0x11A   /* External Address Register */
-#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
-#define   ESR_IMCP      0x80000000      /* Instr. Machine Check - Protection */
-#define   ESR_IMCN      0x40000000      /* Instr. Machine Check - Non-config */
-#define   ESR_IMCB      0x20000000      /* Instr. Machine Check - Bus error */
-#define   ESR_IMCT      0x10000000      /* Instr. Machine Check - Timeout */
-#define   ESR_PIL       0x08000000      /* Program Exception - Illegal */
-#define   ESR_PPR       0x04000000      /* Program Exception - Priveleged */
-#define   ESR_PTR       0x02000000      /* Program Exception - Trap */
-#define   ESR_DST       0x00800000      /* Storage Exception - Data miss */
-#define   ESR_DIZ       0x00400000      /* Storage Exception - Zone fault */
-#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
-#define SPRN_HASH1      0x3D2   /* Primary Hash Address Register */
-#define SPRN_HASH2      0x3D3   /* Secondary Hash Address Resgister */
 #define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
-#define   HID0_EMCP     (1<<31)         /* Enable Machine Check pin */
-#define   HID0_EBA      (1<<29)         /* Enable Bus Address Parity */
-#define   HID0_EBD      (1<<28)         /* Enable Bus Data Parity */
-#define   HID0_SBCLK    (1<<27)
-#define   HID0_EICE     (1<<26)
-#define   HID0_ECLK     (1<<25)
-#define   HID0_PAR      (1<<24)
-#define   HID0_DOZE     (1<<23)
-#define   HID0_NAP      (1<<22)
-#define   HID0_SLEEP    (1<<21)
-#define   HID0_DPM      (1<<20)
-#define   HID0_ICE      (1<<15)         /* Instruction Cache Enable */
-#define   HID0_DCE      (1<<14)         /* Data Cache Enable */
-#define   HID0_ILOCK    (1<<13)         /* Instruction Cache Lock */
-#define   HID0_DLOCK    (1<<12)         /* Data Cache Lock */
-#define   HID0_ICFI     (1<<11)         /* Instr. Cache Flash Invalidate */
-#define   HID0_DCI      (1<<10)         /* Data Cache Invalidate */
-#define   HID0_SPD      (1<<9)          /* Speculative disable */
-#define   HID0_SGE      (1<<7)          /* Store Gathering Enable */
-#define   HID0_SIED     (1<<7)          /* Serial Instr. Execution [Disable] */
-#define   HID0_BTIC     (1<<5)          /* Branch Target Instruction Cache Enable */
-#define   HID0_ABE      (1<<3)          /* Address Broadcast Enable */
-#define   HID0_BHTE     (1<<2)          /* Branch History Table Enable */
-#define   HID0_BTCD     (1<<1)          /* Branch target cache disable */
 #define SPRN_MSRDORM    0x3F1   /* Hardware Implementation Register 1 */
 #define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
@@ -225,23 +140,8 @@
 #define SPRN_HID5       0x3F6   /* 970 HID5 */
 #define SPRN_TSC        0x3FD   /* Thread switch control */
 #define SPRN_TST        0x3FC   /* Thread switch timeout */
-#define SPRN_IAC1       0x3F4   /* Instruction Address Compare 1 */
-#define SPRN_IAC2       0x3F5   /* Instruction Address Compare 2 */
-#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
-#define   ICCR_NOCACHE          0       /* Noncacheable */
-#define   ICCR_CACHE            1       /* Cacheable */
-#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
-#define SPRN_ICMP       0x3D5   /* Instruction TLB Compare Register */
-#define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
-#define SPRN_IMISS      0x3D4   /* Instruction TLB Miss Register */
-#define SPRN_IMMR       0x27E   /* Internal Memory Map Register */
 #define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
 #define SPRN_LR         0x008   /* Link Register */
-#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
-#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
-#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
-#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
-#define SPRN_PID        0x3B1   /* Process ID */
 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 #define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 #define SPRN_PURR       0x135   /* Processor Utilization of Resources Register */
@@ -249,9 +149,6 @@
 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
 #define SPRN_SDR1       0x019   /* MMU Hash Base Register */
-#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
-#define   SGR_NORMAL            0
-#define   SGR_GUARDED           1
 #define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
 #define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
@@ -264,50 +161,12 @@
 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, W/O) */
 #define SPRN_TBWU       0x11D   /* Time Base Write Upper Register (super, W/O) */
 #define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
-#define SPRN_TCR        0x3DA   /* Timer Control Register */
-#define   TCR_WP(x)             (((x)&0x3)<<30) /* WDT Period */
-#define     WP_2_17             0               /* 2^17 clocks */
-#define     WP_2_21             1               /* 2^21 clocks */
-#define     WP_2_25             2               /* 2^25 clocks */
-#define     WP_2_29             3               /* 2^29 clocks */
-#define   TCR_WRC(x)            (((x)&0x3)<<28) /* WDT Reset Control */
-#define     WRC_NONE            0               /* No reset will occur */
-#define     WRC_CORE            1               /* Core reset will occur */
-#define     WRC_CHIP            2               /* Chip reset will occur */
-#define     WRC_SYSTEM          3               /* System reset will occur */
-#define   TCR_WIE               0x08000000      /* WDT Interrupt Enable */
-#define   TCR_PIE               0x04000000      /* PIT Interrupt Enable */
-#define   TCR_FP(x)             (((x)&0x3)<<24) /* FIT Period */
-#define     FP_2_9              0               /* 2^9 clocks */
-#define     FP_2_13             1               /* 2^13 clocks */
-#define     FP_2_17             2               /* 2^17 clocks */
-#define     FP_2_21             3               /* 2^21 clocks */
-#define   TCR_FIE               0x00800000      /* FIT Interrupt Enable */
-#define   TCR_ARE               0x00400000      /* Auto Reload Enable */
-#define SPRN_THRM1      0x3FC   /* Thermal Management Register 1 */
-#define   THRM1_TIN             (1<<0)
-#define   THRM1_TIV             (1<<1)
-#define   THRM1_THRES           (0x7f<<2)
-#define   THRM1_TID             (1<<29)
-#define   THRM1_TIE             (1<<30)
-#define   THRM1_V               (1<<31)
-#define SPRN_THRM2      0x3FD   /* Thermal Management Register 2 */
-#define SPRN_THRM3      0x3FE   /* Thermal Management Register 3 */
-#define   THRM3_E               (1<<31)
-#define SPRN_TSR        0x3D8   /* Timer Status Register */
-#define   TSR_ENW               0x80000000      /* Enable Next Watchdog */
-#define   TSR_WIS               0x40000000      /* WDT Interrupt Status */
-#define   TSR_WRS(x)            (((x)&0x3)<<28) /* WDT Reset Status */
-#define     WRS_NONE            0               /* No WDT reset occurred */
-#define     WRS_CORE            1               /* WDT forced core reset */
-#define     WRS_CHIP            2               /* WDT forced chip reset */
-#define     WRS_SYSTEM          3               /* WDT forced system reset */
-#define   TSR_PIS               0x08000000      /* PIT Interrupt Status */
-#define   TSR_FIS               0x04000000      /* FIT Interrupt Status */
 #define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
-#define SPRN_ZPR        0x3B0   /* Zone Protection Register */
 #define SPRN_VRSAVE     0x100   /* Vector save */
+#define SPRN_CTRLF      0x088
+#define SPRN_CTRLT      0x098
+#define   CTRL_RUNLATCH 0x1
 
 /* Performance monitor SPRs */
 #define SPRN_SIAR       780
@@ -352,28 +211,19 @@
 #define CTR     SPRN_CTR        /* Counter Register */
 #define DAR     SPRN_DAR        /* Data Address Register */
 #define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
-#define DCMP    SPRN_DCMP       /* Data TLB Compare Register */
 #define DEC     SPRN_DEC        /* Decrement Register */
-#define DMISS   SPRN_DMISS      /* Data TLB Miss Register */
 #define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
-#define EAR     SPRN_EAR        /* External Address Register */
-#define HASH1   SPRN_HASH1      /* Primary Hash Address Register */
-#define HASH2   SPRN_HASH2      /* Secondary Hash Address Register */
 #define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
 #define MSRDORM SPRN_MSRDORM    /* MSR Dormant Register */
 #define NIADORM SPRN_NIADORM    /* NIA Dormant Register */
 #define TSC     SPRN_TSC        /* Thread switch control */
 #define TST     SPRN_TST        /* Thread switch timeout */
 #define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
-#define ICMP    SPRN_ICMP       /* Instruction TLB Compare Register */
-#define IMISS   SPRN_IMISS      /* Instruction TLB Miss Register */
-#define IMMR    SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
 #define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
 #define __LR    SPRN_LR
 #define PVR     SPRN_PVR        /* Processor Version */
 #define PIR     SPRN_PIR        /* Processor ID */
 #define PURR    SPRN_PURR       /* Processor Utilization of Resource Register */
-//#define       RPA     SPRN_RPA        /* Required Physical Address Register */
 #define SDR1    SPRN_SDR1       /* MMU hash base register */
 #define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
 #define SPR1    SPRN_SPRG1
@@ -389,10 +239,6 @@
 #define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
 #define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
 #define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
-#define ICTC    1019
-#define THRM1   SPRN_THRM1      /* Thermal Management Register 1 */
-#define THRM2   SPRN_THRM2      /* Thermal Management Register 2 */
-#define THRM3   SPRN_THRM3      /* Thermal Management Register 3 */
 #define XER     SPRN_XER
 
 /* Processor Version Register (PVR) field extraction */
@@ -436,12 +282,6 @@
 #define XGLUE(a,b) a##b
 #define GLUE(a,b) XGLUE(a,b)
 
-/* iSeries CTRL register (for runlatch) */
-
-#define CTRLT           0x098
-#define CTRLF           0x088
-#define RUNLATCH        0x0001
-
 #ifdef __ASSEMBLY__
 
 #define _GLOBAL(name) \
@@ -656,6 +496,24 @@ static inline void prefetchw(const void *x)
 
 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 
+static inline void ppc64_runlatch_on(void)
+{
+        unsigned long ctrl;
+
+        ctrl = mfspr(SPRN_CTRLF);
+        ctrl |= CTRL_RUNLATCH;
+        mtspr(SPRN_CTRLT, ctrl);
+}
+
+static inline void ppc64_runlatch_off(void)
+{
+        unsigned long ctrl;
+
+        ctrl = mfspr(SPRN_CTRLF);
+        ctrl &= ~CTRL_RUNLATCH;
+        mtspr(SPRN_CTRLT, ctrl);
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index 2440a2c90ae9..04b1a84f7ca3 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -147,9 +147,7 @@ struct device_node {
         struct  device_node *sibling;
         struct  device_node *next;      /* next device of same type */
         struct  device_node *allnext;   /* next in list of all nodes */
-        struct  proc_dir_entry *pde;       /* this node's proc directory */
-        struct  proc_dir_entry *name_link; /* name symlink */
-        struct  proc_dir_entry *addr_link; /* addr symlink */
+        struct  proc_dir_entry *pde;    /* this node's proc directory */
         struct  kref kref;
         unsigned long _flags;
 };
@@ -174,15 +172,6 @@ static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_e
         dn->pde = de;
 }
 
-static void inline set_node_name_link(struct device_node *dn, struct proc_dir_entry *de)
-{
-        dn->name_link = de;
-}
-
-static void inline set_node_addr_link(struct device_node *dn, struct proc_dir_entry *de)
-{
-        dn->addr_link = de;
-}
 
 /* OBSOLETE: Old stlye node lookup */
 extern struct device_node *find_devices(const char *name);
diff --git a/include/asm-ppc64/signal.h b/include/asm-ppc64/signal.h
index a2d7bbb4befd..432df7dd355d 100644
--- a/include/asm-ppc64/signal.h
+++ b/include/asm-ppc64/signal.h
@@ -97,33 +97,19 @@ typedef struct {
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void __sigfunction(int);
-typedef __sigfunction __user * __sighandler_t;
-
-/* Type of the restorer function */
-typedef void __sigrestorer(void);
-typedef __sigrestorer __user * __sigrestorer_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 struct old_sigaction {
         __sighandler_t sa_handler;
         old_sigset_t sa_mask;
         unsigned long sa_flags;
-        __sigrestorer_t sa_restorer;
+        __sigrestore_t sa_restorer;
 };
 
 struct sigaction {
         __sighandler_t sa_handler;
         unsigned long sa_flags;
-        __sigrestorer_t sa_restorer;
+        __sigrestore_t sa_restorer;
         sigset_t sa_mask;               /* mask last for extensibility */
 };
 
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-ppc64/thread_info.h
index 037b5e06083c..48b7900e90ec 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-ppc64/thread_info.h
@@ -96,7 +96,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_POLLING_NRFLAG      4       /* true if poll_idle() is polling
                                            TIF_NEED_RESCHED */
 #define TIF_32BIT               5       /* 32 bit binary */
-#define TIF_RUN_LIGHT           6       /* iSeries run light */
+/* #define SPARE                6 */
 #define TIF_ABI_PENDING         7       /* 32/64 bit switch needed */
 #define TIF_SYSCALL_AUDIT       8       /* syscall auditing active */
 #define TIF_SINGLESTEP          9       /* singlestepping active */
@@ -110,7 +110,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_32BIT              (1<<TIF_32BIT)
-#define _TIF_RUN_LIGHT          (1<<TIF_RUN_LIGHT)
+/* #define _SPARE               (1<<SPARE) */
 #define _TIF_ABI_PENDING        (1<<TIF_ABI_PENDING)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h
index 0027da4364ac..fdec5e7a7af6 100644
--- a/include/asm-ppc64/xics.h
+++ b/include/asm-ppc64/xics.h
@@ -30,7 +30,4 @@ struct xics_ipi_struct {
 
 extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
 
-extern unsigned int default_distrib_server;
-extern unsigned int interrupt_server_size;
-
 #endif /* _PPC64_KERNEL_XICS_H */
diff --git a/include/asm-s390/signal.h b/include/asm-s390/signal.h
index bfed83a818cc..3d6e11c6c1fd 100644
--- a/include/asm-s390/signal.h
+++ b/include/asm-s390/signal.h
@@ -117,16 +117,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-s390/user.h b/include/asm-s390/user.h
index c64f8c181df3..1dc74baf03c4 100644
--- a/include/asm-s390/user.h
+++ b/include/asm-s390/user.h
@@ -10,7 +10,7 @@
 #define _S390_USER_H
 
 #include <asm/page.h>
-#include <linux/ptrace.h>
+#include <asm/ptrace.h>
 /* Core file format: The core file is written in such a way that gdb
    can understand it and provide useful information to the user (under
    linux we use the 'trad-core' bfd).  There are quite a number of
diff --git a/include/asm-sh/floppy.h b/include/asm-sh/floppy.h
index f030ca08052b..38d7a2942476 100644
--- a/include/asm-sh/floppy.h
+++ b/include/asm-sh/floppy.h
@@ -227,7 +227,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
         return 0;
 }
 
-struct fd_routine_l {
+static struct fd_routine_l {
         int (*_request_dma)(unsigned int dmanr, const char * device_id);
         void (*_free_dma)(unsigned int dmanr);
         int (*_get_dma_residue)(unsigned int dummy);
diff --git a/include/asm-sh/signal.h b/include/asm-sh/signal.h
index 29f1ac1bf4df..d6e8eb0e65c7 100644
--- a/include/asm-sh/signal.h
+++ b/include/asm-sh/signal.h
@@ -108,16 +108,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
index d82f883d8e6d..4bbbd9f3c37e 100644
--- a/include/asm-sh/thread_info.h
+++ b/include/asm-sh/thread_info.h
@@ -27,7 +27,7 @@ struct thread_info {
 
 #endif
 
-#define PREEMPT_ACTIVE          0x4000000
+#define PREEMPT_ACTIVE          0x10000000
 
 /*
  * macros/functions for gaining access to the thread information structure
diff --git a/include/asm-sh64/signal.h b/include/asm-sh64/signal.h
index 864c94ecc98c..2400dc688a65 100644
--- a/include/asm-sh64/signal.h
+++ b/include/asm-sh64/signal.h
@@ -107,16 +107,7 @@ typedef struct {
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        THREAD_SIZE
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct old_sigaction {
diff --git a/include/asm-sh64/thread_info.h b/include/asm-sh64/thread_info.h
index e65f394da472..8a32d6bd0b79 100644
--- a/include/asm-sh64/thread_info.h
+++ b/include/asm-sh64/thread_info.h
@@ -73,7 +73,7 @@ static inline struct thread_info *current_thread_info(void)
 
 #define THREAD_SIZE  8192
 
-#define PREEMPT_ACTIVE          0x4000000
+#define PREEMPT_ACTIVE          0x10000000
 
 /* thread information flags */
 #define TIF_SYSCALL_TRACE       0       /* syscall trace active */
diff --git a/include/asm-sparc/floppy.h b/include/asm-sparc/floppy.h
index 780ee7ff9dc3..caf926116506 100644
--- a/include/asm-sparc/floppy.h
+++ b/include/asm-sparc/floppy.h
@@ -227,7 +227,7 @@ static __inline__ void sun_fd_disable_dma(void)
         doing_pdma = 0;
         if (pdma_base) {
                 mmu_unlockarea(pdma_base, pdma_areasize);
-                pdma_base = 0;
+                pdma_base = NULL;
         }
 }
 
diff --git a/include/asm-sparc/signal.h b/include/asm-sparc/signal.h
index f792e10e704f..aa9960ad0ca9 100644
--- a/include/asm-sparc/signal.h
+++ b/include/asm-sparc/signal.h
@@ -174,16 +174,7 @@ struct sigstack {
 #define SA_STATIC_ALLOC         0x80
 #endif
 
-/* Type of a signal handler.  */
-#ifdef __KERNEL__
-typedef void (*__sighandler_t)(int, int, struct sigcontext *, char *);
-#else
-typedef void (*__sighandler_t)(int);
-#endif
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 struct __new_sigaction {
diff --git a/include/asm-sparc/uaccess.h b/include/asm-sparc/uaccess.h
index f461144067ee..0a780e84a12b 100644
--- a/include/asm-sparc/uaccess.h
+++ b/include/asm-sparc/uaccess.h
@@ -41,10 +41,11 @@
  * No one can read/write anything from userland in the kernel space by setting
  * large size and address near to PAGE_OFFSET - a fault will break his intentions.
  */
-#define __user_ok(addr,size) ((addr) < STACK_TOP)
+#define __user_ok(addr, size) ({ (void)(size); (addr) < STACK_TOP; })
 #define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
 #define __access_ok(addr,size) (__user_ok((addr) & get_fs().seg,(size)))
-#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
+#define access_ok(type, addr, size)                                     \
+        ({ (void)(type); __access_ok((unsigned long)(addr), size); })
 
 /* this function will go away soon - use access_ok() instead */
 static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
diff --git a/include/asm-sparc64/agp.h b/include/asm-sparc64/agp.h
index ba05bdf9a211..58f8cb6ae767 100644
--- a/include/asm-sparc64/agp.h
+++ b/include/asm-sparc64/agp.h
@@ -8,4 +8,14 @@
 #define flush_agp_mappings() 
 #define flush_agp_cache() mb()
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif
diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
index 5fd16e42a045..0de7a3da79cd 100644
--- a/include/asm-sparc64/iommu.h
+++ b/include/asm-sparc64/iommu.h
@@ -16,4 +16,6 @@
 #define IOPTE_CACHE   0x0000000000000010UL /* Cached (in UPA E-cache)         */
 #define IOPTE_WRITE   0x0000000000000002UL /* Writeable                       */
 
+#define IOMMU_NUM_CTXS  4096
+
 #endif /* !(_SPARC_IOMMU_H) */
diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h
index ab88349ddadc..b7e635544cec 100644
--- a/include/asm-sparc64/parport.h
+++ b/include/asm-sparc64/parport.h
@@ -13,6 +13,12 @@
 
 #define PARPORT_PC_MAX_PORTS    PARPORT_MAX
 
+/*
+ * While sparc64 doesn't have an ISA DMA API, we provide something that looks
+ * close enough to make parport_pc happy
+ */
+#define HAS_DMA
+
 static struct sparc_ebus_info {
         struct ebus_dma_info info;
         unsigned int addr;
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index 92999631c819..4c15610a2bac 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <asm/page.h>
 #include <asm/oplib.h>
+#include <asm/iommu.h>
 
 /* The abstraction used here is that there are PCI controllers,
  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
@@ -40,9 +41,6 @@ struct pci_iommu {
          */
         spinlock_t      lock;
 
-        /* Context allocator. */
-        unsigned int    iommu_cur_ctx;
-
         /* IOMMU page table, a linear array of ioptes. */
         iopte_t         *page_table;            /* The page table itself. */
         int             page_table_sz_bits;     /* log2 of ow many pages does it map? */
@@ -87,6 +85,10 @@ struct pci_iommu {
                 u16     flush;
         } alloc_info[PBM_NCLUSTERS];
 
+        /* CTX allocation. */
+        unsigned long ctx_lowest_free;
+        unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
+
         /* Here a PCI controller driver describes the areas of
          * PCI memory space where DMA to/from physical memory
          * are addressed.  Drivers interrogate the PCI layer
diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h
index 2c28e1f605b7..b9b1914aae63 100644
--- a/include/asm-sparc64/pgalloc.h
+++ b/include/asm-sparc64/pgalloc.h
@@ -122,17 +122,12 @@ static __inline__ void free_pmd_slow(pmd_t *pmd)
 #define pmd_populate(MM,PMD,PTE_PAGE)           \
         pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
 
-extern pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address);
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
-        return __pte_alloc_one_kernel(mm, address);
-}
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address);
 
 static inline struct page *
 pte_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        pte_t *pte = __pte_alloc_one_kernel(mm, addr);
+        pte_t *pte = pte_alloc_one_kernel(mm, addr);
 
         if (pte)
                 return virt_to_page(pte);
diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h
index 466d021d7038..becdf1bc5924 100644
--- a/include/asm-sparc64/signal.h
+++ b/include/asm-sparc64/signal.h
@@ -177,21 +177,7 @@ struct sigstack {
 #define SA_STATIC_ALLOC         0x80
 #endif
 
-/* Type of a signal handler.  */
-#ifdef __KERNEL__
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-#else
-typedef void (*__sighandler_t)(int);
-typedef void (*__sigrestore_t)(void);
-#endif
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+#include <asm-generic/signal.h>
 
 struct __new_sigaction {
         __sighandler_t          sa_handler;
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index ad78ce64d69e..9d7613eea812 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -48,6 +48,9 @@ enum ultra_tlb_layout {
 
 extern enum ultra_tlb_layout tlb_type;
 
+extern int cheetah_pcache_forced_on;
+extern void cheetah_enable_pcache(void);
+
 #define sparc64_highest_locked_tlbent() \
         (tlb_type == spitfire ? \
          SPITFIRE_HIGHEST_LOCKED_TLBENT : \
diff --git a/include/asm-um/arch-signal-i386.h b/include/asm-um/arch-signal-i386.h
deleted file mode 100644
index 99a9de4728da..000000000000
--- a/include/asm-um/arch-signal-i386.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_ARCH_SIGNAL_I386_H
-#define __UM_ARCH_SIGNAL_I386_H
-
-struct arch_signal_context {
-        unsigned long extrasigs[_NSIG_WORDS];
-};
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/archparam-i386.h b/include/asm-um/archparam-i386.h
index 6f78de5b621b..49e89b8d7e58 100644
--- a/include/asm-um/archparam-i386.h
+++ b/include/asm-um/archparam-i386.h
@@ -6,143 +6,6 @@
 #ifndef __UM_ARCHPARAM_I386_H
 #define __UM_ARCHPARAM_I386_H
 
-/********* Bits for asm-um/elf.h ************/
-
-#include <asm/user.h>
-
-extern char * elf_aux_platform;
-#define ELF_PLATFORM (elf_aux_platform)
-
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-
-typedef struct user_i387_struct elf_fpregset_t;
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_386
-
-#define ELF_PLAT_INIT(regs, load_addr) do { \
-        PT_REGS_EBX(regs) = 0; \
-        PT_REGS_ECX(regs) = 0; \
-        PT_REGS_EDX(regs) = 0; \
-        PT_REGS_ESI(regs) = 0; \
-        PT_REGS_EDI(regs) = 0; \
-        PT_REGS_EBP(regs) = 0; \
-        PT_REGS_EAX(regs) = 0; \
-} while(0)
-
-/* Shamelessly stolen from include/asm-i386/elf.h */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) do {   \
-        pr_reg[0] = PT_REGS_EBX(regs);          \
-        pr_reg[1] = PT_REGS_ECX(regs);          \
-        pr_reg[2] = PT_REGS_EDX(regs);          \
-        pr_reg[3] = PT_REGS_ESI(regs);          \
-        pr_reg[4] = PT_REGS_EDI(regs);          \
-        pr_reg[5] = PT_REGS_EBP(regs);          \
-        pr_reg[6] = PT_REGS_EAX(regs);          \
-        pr_reg[7] = PT_REGS_DS(regs);           \
-        pr_reg[8] = PT_REGS_ES(regs);           \
-        /* fake once used fs and gs selectors? */       \
-        pr_reg[9] = PT_REGS_DS(regs);           \
-        pr_reg[10] = PT_REGS_DS(regs);          \
-        pr_reg[11] = PT_REGS_SYSCALL_NR(regs);  \
-        pr_reg[12] = PT_REGS_IP(regs);          \
-        pr_reg[13] = PT_REGS_CS(regs);          \
-        pr_reg[14] = PT_REGS_EFLAGS(regs);      \
-        pr_reg[15] = PT_REGS_SP(regs);          \
-        pr_reg[16] = PT_REGS_SS(regs);          \
-} while(0);
-
-
-extern unsigned long vsyscall_ehdr;
-extern unsigned long vsyscall_end;
-extern unsigned long __kernel_vsyscall;
-
-#define VSYSCALL_BASE vsyscall_ehdr
-#define VSYSCALL_END vsyscall_end
-
-/*
- * This is the range that is readable by user mode, and things
- * acting like user mode such as get_user_pages.
- */
-#define FIXADDR_USER_START      VSYSCALL_BASE
-#define FIXADDR_USER_END        VSYSCALL_END
-
-/*
- * Architecture-neutral AT_ values in 0-17, leave some room
- * for more of them, start the x86-specific ones at 32.
- */
-#define AT_SYSINFO              32
-#define AT_SYSINFO_EHDR         33
-
-#define ARCH_DLINFO                                             \
-do {                                                            \
-        if ( vsyscall_ehdr ) {                                  \
-                NEW_AUX_ENT(AT_SYSINFO, __kernel_vsyscall);     \
-                NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr);    \
-        }                                                       \
-} while (0)
-
-/*
- * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out
- * extra segments containing the vsyscall DSO contents.  Dumping its
- * contents makes post-mortem fully interpretable later without matching up
- * the same kernel and hardware config to see what PC values meant.
- * Dumping its extra ELF program headers includes all the other information
- * a debugger needs to easily find how the vsyscall DSO was being used.
- */
-#define ELF_CORE_EXTRA_PHDRS                                                  \
-        (vsyscall_ehdr ? (((struct elfhdr *)vsyscall_ehdr)->e_phnum) : 0 )
-
-#define ELF_CORE_WRITE_EXTRA_PHDRS                                            \
-if ( vsyscall_ehdr ) {                                                        \
-        const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr;    \
-        const struct elf_phdr *const phdrp =                                  \
-                (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff);   \
-        int i;                                                                \
-        Elf32_Off ofs = 0;                                                    \
-        for (i = 0; i < ehdrp->e_phnum; ++i) {                                \
-                struct elf_phdr phdr = phdrp[i];                              \
-                if (phdr.p_type == PT_LOAD) {                                 \
-                        ofs = phdr.p_offset = offset;                         \
-                        offset += phdr.p_filesz;                              \
-                }                                                             \
-                else                                                          \
-                        phdr.p_offset += ofs;                                 \
-                phdr.p_paddr = 0; /* match other core phdrs */                \
-                DUMP_WRITE(&phdr, sizeof(phdr));                              \
-        }                                                                     \
-}
-#define ELF_CORE_WRITE_EXTRA_DATA                                             \
-if ( vsyscall_ehdr ) {                                                        \
-        const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr;    \
-        const struct elf_phdr *const phdrp =                                  \
-                (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff);   \
-        int i;                                                                \
-        for (i = 0; i < ehdrp->e_phnum; ++i) {                                \
-                if (phdrp[i].p_type == PT_LOAD)                               \
-                        DUMP_WRITE((void *) phdrp[i].p_vaddr,                 \
-                                   phdrp[i].p_filesz);                        \
-        }                                                                     \
-}
-
-#define R_386_NONE      0
-#define R_386_32        1
-#define R_386_PC32      2
-#define R_386_GOT32     3
-#define R_386_PLT32     4
-#define R_386_COPY      5
-#define R_386_GLOB_DAT  6
-#define R_386_JMP_SLOT  7
-#define R_386_RELATIVE  8
-#define R_386_GOTOFF    9
-#define R_386_GOTPC     10
-#define R_386_NUM       11
-
 /********* Nothing for asm-um/hardirq.h **********/
 
 /********* Nothing for asm-um/hw_irq.h **********/
diff --git a/include/asm-um/archparam-ppc.h b/include/asm-um/archparam-ppc.h
index 0ebced92a762..172cd6ffacc4 100644
--- a/include/asm-um/archparam-ppc.h
+++ b/include/asm-um/archparam-ppc.h
@@ -1,26 +1,6 @@
 #ifndef __UM_ARCHPARAM_PPC_H
 #define __UM_ARCHPARAM_PPC_H
 
-/********* Bits for asm-um/elf.h ************/
-
-#define ELF_PLATFORM (0)
-
-#define ELF_ET_DYN_BASE (0x08000000)
-
-/* the following stolen from asm-ppc/elf.h */
-#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
-#define ELF_NFPREG      33      /* includes fpscr */
-/* General registers */
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* Floating point registers */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-#define ELF_DATA        ELFDATA2MSB
-#define ELF_ARCH        EM_PPC
-
 /********* Bits for asm-um/hw_irq.h **********/
 
 struct hw_interrupt_type;
diff --git a/include/asm-um/archparam-x86_64.h b/include/asm-um/archparam-x86_64.h
index 96321c4892f1..270ed9586b68 100644
--- a/include/asm-um/archparam-x86_64.h
+++ b/include/asm-um/archparam-x86_64.h
@@ -7,42 +7,6 @@
 #ifndef __UM_ARCHPARAM_X86_64_H
 #define __UM_ARCHPARAM_X86_64_H
 
-#include <asm/user.h>
-
-#define ELF_PLATFORM "x86_64"
-
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-
-typedef unsigned long elf_greg_t;
-typedef struct { } elf_fpregset_t;
-
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_X86_64
-
-#define ELF_PLAT_INIT(regs, load_addr)    do { \
-        PT_REGS_RBX(regs) = 0; \
-        PT_REGS_RCX(regs) = 0; \
-        PT_REGS_RDX(regs) = 0; \
-        PT_REGS_RSI(regs) = 0; \
-        PT_REGS_RDI(regs) = 0; \
-        PT_REGS_RBP(regs) = 0; \
-        PT_REGS_RAX(regs) = 0; \
-        PT_REGS_R8(regs) = 0; \
-        PT_REGS_R9(regs) = 0; \
-        PT_REGS_R10(regs) = 0; \
-        PT_REGS_R11(regs) = 0; \
-        PT_REGS_R12(regs) = 0; \
-        PT_REGS_R13(regs) = 0; \
-        PT_REGS_R14(regs) = 0; \
-        PT_REGS_R15(regs) = 0; \
-} while (0)
-
-#ifdef TIF_IA32 /* XXX */
-        clear_thread_flag(TIF_IA32);
-#endif
 
 /* No user-accessible fixmap addresses, i.e. vsyscall */
 #define FIXADDR_USER_START      0
diff --git a/include/asm-um/delay.h b/include/asm-um/delay.h
index 40695576ca60..0985bda66750 100644
--- a/include/asm-um/delay.h
+++ b/include/asm-um/delay.h
@@ -4,4 +4,6 @@
 #include "asm/arch/delay.h"
 #include "asm/archparam.h"
 
+#define MILLION 1000000
+
 #endif
diff --git a/include/asm-um/elf-i386.h b/include/asm-um/elf-i386.h
new file mode 100644
index 000000000000..9bab712dc5c0
--- /dev/null
+++ b/include/asm-um/elf-i386.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2000 - 2003 Jeff Dike (jdike@addtoit.com)
+ * Licensed under the GPL
+ */
+#ifndef __UM_ELF_I386_H
+#define __UM_ELF_I386_H
+
+#include <asm/user.h>
+
+#define R_386_NONE      0
+#define R_386_32        1
+#define R_386_PC32      2
+#define R_386_GOT32     3
+#define R_386_PLT32     4
+#define R_386_COPY      5
+#define R_386_GLOB_DAT  6
+#define R_386_JMP_SLOT  7
+#define R_386_RELATIVE  8
+#define R_386_GOTOFF    9
+#define R_386_GOTPC     10
+#define R_386_NUM       11
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_i387_struct elf_fpregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) \
+        (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
+
+#define ELF_CLASS       ELFCLASS32
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_386
+
+#define ELF_PLAT_INIT(regs, load_addr) do { \
+        PT_REGS_EBX(regs) = 0; \
+        PT_REGS_ECX(regs) = 0; \
+        PT_REGS_EDX(regs) = 0; \
+        PT_REGS_ESI(regs) = 0; \
+        PT_REGS_EDI(regs) = 0; \
+        PT_REGS_EBP(regs) = 0; \
+        PT_REGS_EAX(regs) = 0; \
+} while(0)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
+
+/* Shamelessly stolen from include/asm-i386/elf.h */
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs) do {   \
+        pr_reg[0] = PT_REGS_EBX(regs);          \
+        pr_reg[1] = PT_REGS_ECX(regs);          \
+        pr_reg[2] = PT_REGS_EDX(regs);          \
+        pr_reg[3] = PT_REGS_ESI(regs);          \
+        pr_reg[4] = PT_REGS_EDI(regs);          \
+        pr_reg[5] = PT_REGS_EBP(regs);          \
+        pr_reg[6] = PT_REGS_EAX(regs);          \
+        pr_reg[7] = PT_REGS_DS(regs);           \
+        pr_reg[8] = PT_REGS_ES(regs);           \
+        /* fake once used fs and gs selectors? */       \
+        pr_reg[9] = PT_REGS_DS(regs);           \
+        pr_reg[10] = PT_REGS_DS(regs);          \
+        pr_reg[11] = PT_REGS_SYSCALL_NR(regs);  \
+        pr_reg[12] = PT_REGS_IP(regs);          \
+        pr_reg[13] = PT_REGS_CS(regs);          \
+        pr_reg[14] = PT_REGS_EFLAGS(regs);      \
+        pr_reg[15] = PT_REGS_SP(regs);          \
+        pr_reg[16] = PT_REGS_SS(regs);          \
+} while(0);
+
+extern long elf_aux_hwcap;
+#define ELF_HWCAP (elf_aux_hwcap)
+
+extern char * elf_aux_platform;
+#define ELF_PLATFORM (elf_aux_platform)
+
+#define SET_PERSONALITY(ex, ibcs2) do ; while(0)
+
+extern unsigned long vsyscall_ehdr;
+extern unsigned long vsyscall_end;
+extern unsigned long __kernel_vsyscall;
+
+#define VSYSCALL_BASE vsyscall_ehdr
+#define VSYSCALL_END vsyscall_end
+
+/*
+ * This is the range that is readable by user mode, and things
+ * acting like user mode such as get_user_pages.
+ */
+#define FIXADDR_USER_START      VSYSCALL_BASE
+#define FIXADDR_USER_END        VSYSCALL_END
+
+/*
+ * Architecture-neutral AT_ values in 0-17, leave some room
+ * for more of them, start the x86-specific ones at 32.
+ */
+#define AT_SYSINFO              32
+#define AT_SYSINFO_EHDR         33
+
+#define ARCH_DLINFO                                             \
+do {                                                            \
+        if ( vsyscall_ehdr ) {                                  \
+                NEW_AUX_ENT(AT_SYSINFO, __kernel_vsyscall);     \
+                NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr);    \
+        }                                                       \
+} while (0)
+
+/*
+ * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out
+ * extra segments containing the vsyscall DSO contents.  Dumping its
+ * contents makes post-mortem fully interpretable later without matching up
+ * the same kernel and hardware config to see what PC values meant.
+ * Dumping its extra ELF program headers includes all the other information
+ * a debugger needs to easily find how the vsyscall DSO was being used.
+ */
+#define ELF_CORE_EXTRA_PHDRS                                                  \
+        (vsyscall_ehdr ? (((struct elfhdr *)vsyscall_ehdr)->e_phnum) : 0 )
+
+#define ELF_CORE_WRITE_EXTRA_PHDRS                                            \
+if ( vsyscall_ehdr ) {                                                        \
+        const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr;    \
+        const struct elf_phdr *const phdrp =                                  \
+                (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff);   \
+        int i;                                                                \
+        Elf32_Off ofs = 0;                                                    \
+        for (i = 0; i < ehdrp->e_phnum; ++i) {                                \
+                struct elf_phdr phdr = phdrp[i];                              \
+                if (phdr.p_type == PT_LOAD) {                                 \
+                        ofs = phdr.p_offset = offset;                         \
+                        offset += phdr.p_filesz;                              \
+                }                                                             \
+                else                                                          \
+                        phdr.p_offset += ofs;                                 \
+                phdr.p_paddr = 0; /* match other core phdrs */                \
+                DUMP_WRITE(&phdr, sizeof(phdr));                              \
+        }                                                                     \
+}
+#define ELF_CORE_WRITE_EXTRA_DATA                                             \
+if ( vsyscall_ehdr ) {                                                        \
+        const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr;    \
+        const struct elf_phdr *const phdrp =                                  \
+                (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff);   \
+        int i;                                                                \
+        for (i = 0; i < ehdrp->e_phnum; ++i) {                                \
+                if (phdrp[i].p_type == PT_LOAD)                               \
+                        DUMP_WRITE((void *) phdrp[i].p_vaddr,                 \
+                                   phdrp[i].p_filesz);                        \
+        }                                                                     \
+}
+
+#endif
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only.  This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff --git a/include/asm-um/elf.h b/include/asm-um/elf-ppc.h
index 7908f8fe8231..2998cf925042 100644
--- a/include/asm-um/elf.h
+++ b/include/asm-um/elf-ppc.h
@@ -1,8 +1,7 @@
-#ifndef __UM_ELF_H
-#define __UM_ELF_H
+#ifndef __UM_ELF_PPC_H
+#define __UM_ELF_PPC_H
 
 #include "linux/config.h"
-#include "asm/archparam.h"
 
 extern long elf_aux_hwcap;
 #define ELF_HWCAP (elf_aux_hwcap)
@@ -13,7 +12,7 @@ extern long elf_aux_hwcap;
 
 #define elf_check_arch(x) (1)
 
-#ifdef CONFIG_64BIT
+#ifdef CONFIG_64_BIT
 #define ELF_CLASS ELFCLASS64
 #else
 #define ELF_CLASS ELFCLASS32
@@ -34,4 +33,22 @@ extern long elf_aux_hwcap;
 #define R_386_GOTPC     10
 #define R_386_NUM       11
 
+#define ELF_PLATFORM (0)
+
+#define ELF_ET_DYN_BASE (0x08000000)
+
+/* the following stolen from asm-ppc/elf.h */
+#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
+#define ELF_NFPREG      33      /* includes fpscr */
+/* General registers */
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Floating point registers */
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+#define ELF_DATA        ELFDATA2MSB
+#define ELF_ARCH        EM_PPC
+
 #endif
diff --git a/include/asm-um/elf-x86_64.h b/include/asm-um/elf-x86_64.h
new file mode 100644
index 000000000000..8a8246d03936
--- /dev/null
+++ b/include/asm-um/elf-x86_64.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2003 PathScale, Inc.
+ *
+ * Licensed under the GPL
+ */
+#ifndef __UM_ELF_X86_64_H
+#define __UM_ELF_X86_64_H
+
+#include <asm/user.h>
+
+/* x86-64 relocation types, taken from asm-x86_64/elf.h */
+#define R_X86_64_NONE           0       /* No reloc */
+#define R_X86_64_64             1       /* Direct 64 bit  */
+#define R_X86_64_PC32           2       /* PC relative 32 bit signed */
+#define R_X86_64_GOT32          3       /* 32 bit GOT entry */
+#define R_X86_64_PLT32          4       /* 32 bit PLT address */
+#define R_X86_64_COPY           5       /* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT       6       /* Create GOT entry */
+#define R_X86_64_JUMP_SLOT      7       /* Create PLT entry */
+#define R_X86_64_RELATIVE       8       /* Adjust by program base */
+#define R_X86_64_GOTPCREL       9       /* 32 bit signed pc relative
+                                           offset to GOT */
+#define R_X86_64_32             10      /* Direct 32 bit zero extended */
+#define R_X86_64_32S            11      /* Direct 32 bit sign extended */
+#define R_X86_64_16             12      /* Direct 16 bit zero extended */
+#define R_X86_64_PC16           13      /* 16 bit sign extended pc relative */
+#define R_X86_64_8              14      /* Direct 8 bit sign extended  */
+#define R_X86_64_PC8            15      /* 8 bit sign extended pc relative */
+
+#define R_X86_64_NUM            16
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct { } elf_fpregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) \
+        ((x)->e_machine == EM_X86_64)
+
+#define ELF_CLASS       ELFCLASS64
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_X86_64
+
+#define ELF_PLAT_INIT(regs, load_addr)    do { \
+        PT_REGS_RBX(regs) = 0; \
+        PT_REGS_RCX(regs) = 0; \
+        PT_REGS_RDX(regs) = 0; \
+        PT_REGS_RSI(regs) = 0; \
+        PT_REGS_RDI(regs) = 0; \
+        PT_REGS_RBP(regs) = 0; \
+        PT_REGS_RAX(regs) = 0; \
+        PT_REGS_R8(regs) = 0; \
+        PT_REGS_R9(regs) = 0; \
+        PT_REGS_R10(regs) = 0; \
+        PT_REGS_R11(regs) = 0; \
+        PT_REGS_R12(regs) = 0; \
+        PT_REGS_R13(regs) = 0; \
+        PT_REGS_R14(regs) = 0; \
+        PT_REGS_R15(regs) = 0; \
+} while (0)
+
+#ifdef TIF_IA32 /* XXX */
+#error XXX, indeed
+        clear_thread_flag(TIF_IA32);
+#endif
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
+
+extern long elf_aux_hwcap;
+#define ELF_HWCAP (elf_aux_hwcap)
+
+#define ELF_PLATFORM "x86_64"
+
+#define SET_PERSONALITY(ex, ibcs2) do ; while(0)
+
+#endif
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only.  This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff --git a/include/asm-um/fixmap.h b/include/asm-um/fixmap.h
index 900f3fbb9fab..ae0ca3932d50 100644
--- a/include/asm-um/fixmap.h
+++ b/include/asm-um/fixmap.h
@@ -4,6 +4,7 @@
 #include <linux/config.h>
 #include <asm/kmap_types.h>
 #include <asm/archparam.h>
+#include <asm/elf.h>
 
 /*
  * Here we define all the compile-time 'special' virtual
diff --git a/include/asm-um/ipc.h b/include/asm-um/ipc.h
index e2ddc47f3e52..a46e3d9c2a3f 100644
--- a/include/asm-um/ipc.h
+++ b/include/asm-um/ipc.h
@@ -1,6 +1 @@
-#ifndef __UM_IPC_H
-#define __UM_IPC_H
-
-#include "asm/arch/ipc.h"
-
-#endif
+#include <asm-generic/ipc.h>
diff --git a/include/asm-um/linkage.h b/include/asm-um/linkage.h
index 27011652b015..7dfce37adc8b 100644
--- a/include/asm-um/linkage.h
+++ b/include/asm-um/linkage.h
@@ -1,7 +1,6 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
+#ifndef __ASM_UM_LINKAGE_H
+#define __ASM_UM_LINKAGE_H
 
-#define FASTCALL(x)     x __attribute__((regparm(3)))
-#define fastcall        __attribute__((regparm(3)))
+#include "asm/arch/linkage.h"
 
 #endif
diff --git a/include/asm-um/page.h b/include/asm-um/page.h
index 102eb3df1aaf..5afee8a8cdf3 100644
--- a/include/asm-um/page.h
+++ b/include/asm-um/page.h
@@ -45,6 +45,9 @@ typedef struct { unsigned long pgd; } pgd_t;
         ({ (pte).pte_high = (phys) >> 32; \
            (pte).pte_low = (phys) | pgprot_val(prot); })
 
+#define pmd_val(x)      ((x).pmd)
+#define __pmd(x) ((pmd_t) { (x) } )
+
 typedef unsigned long long pfn_t;
 typedef unsigned long long phys_t;
 
@@ -95,7 +98,13 @@ extern unsigned long uml_physmem;
 
 extern unsigned long to_phys(void *virt);
 extern void *to_virt(unsigned long phys);
-#define __pa(virt) to_phys((void *) virt)
+
+/* Cast to unsigned long before casting to void * to avoid a warning from
+ * mmap_kmem about cutting a long long down to a void *.  Not sure that
+ * casting is the right thing, but 32-bit UML can't have 64-bit virtual
+ * addresses
+ */
+#define __pa(virt) to_phys((void *) (unsigned long) virt)
 #define __va(phys) to_virt((unsigned long) phys)
 
 #define page_to_pfn(page) ((page) - mem_map)
diff --git a/include/asm-um/pgtable-3level.h b/include/asm-um/pgtable-3level.h
index d309f3a9e6f6..65e8bfc55fc4 100644
--- a/include/asm-um/pgtable-3level.h
+++ b/include/asm-um/pgtable-3level.h
@@ -149,7 +149,7 @@ static inline pmd_t pfn_pmd(pfn_t page_nr, pgprot_t pgprot)
 
 #define pte_to_pgoff(p) ((p).pte >> 32)
 
-#define pgoff_to_pte(off) ((pte_t) { ((off) < 32) | _PAGE_FILE })
+#define pgoff_to_pte(off) ((pte_t) { ((off) << 32) | _PAGE_FILE })
 
 #else
 
diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h
index 71f9c0c78c0c..a88040920311 100644
--- a/include/asm-um/pgtable.h
+++ b/include/asm-um/pgtable.h
@@ -106,7 +106,7 @@ extern unsigned long end_iomem;
 /*
  * Define this if things work differently on an i386 and an i486:
  * it will (on an i486) warn about kernel memory accesses that are
- * done without a 'verify_area(VERIFY_WRITE,..)'
+ * done without a 'access_ok(VERIFY_WRITE,..)'
  */
 #undef TEST_VERIFY_AREA
 
@@ -114,17 +114,9 @@ extern unsigned long end_iomem;
 extern unsigned long pg0[1024];
 
 /*
- * BAD_PAGETABLE is used when we need a bogus page-table, while
- * BAD_PAGE is used for a bogus page.
- *
  * ZERO_PAGE is a global shared page that is always zero: used
  * for zero-mapped memory areas etc..
  */
-extern pte_t __bad_page(void);
-extern pte_t * __bad_pagetable(void);
-
-#define BAD_PAGETABLE __bad_pagetable()
-#define BAD_PAGE __bad_page()
 
 #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
 
diff --git a/include/asm-um/processor-generic.h b/include/asm-um/processor-generic.h
index b953b1ad3b02..b2fc94fbc2d9 100644
--- a/include/asm-um/processor-generic.h
+++ b/include/asm-um/processor-generic.h
@@ -24,9 +24,6 @@ struct thread_struct {
         int forking;
         int nsyscalls;
         struct pt_regs regs;
-        unsigned long cr2;
-        int err;
-        unsigned long trap_no;
         int singlestep_syscall;
         void *fault_addr;
         void *fault_catcher;
@@ -74,8 +71,6 @@ struct thread_struct {
         .forking                = 0, \
         .nsyscalls              = 0, \
         .regs                   = EMPTY_REGS, \
-        .cr2                    = 0, \
-        .err                    = 0, \
         .fault_addr             = NULL, \
         .prev_sched             = NULL, \
         .temp_stack             = 0, \
diff --git a/include/asm-um/processor-i386.h b/include/asm-um/processor-i386.h
index 2deb8f1adbf1..431bad3ae9d7 100644
--- a/include/asm-um/processor-i386.h
+++ b/include/asm-um/processor-i386.h
@@ -9,13 +9,18 @@
 extern int host_has_xmm;
 extern int host_has_cmov;
 
+/* include faultinfo structure */
+#include "sysdep/faultinfo.h"
+
 struct arch_thread {
         unsigned long debugregs[8];
         int debugregs_seq;
+        struct faultinfo faultinfo;
 };
 
 #define INIT_ARCH_THREAD { .debugregs           = { [ 0 ... 7 ] = 0 }, \
-                           .debugregs_seq       = 0 }
+                           .debugregs_seq       = 0, \
+                           .faultinfo           = { 0, 0, 0 } }
 
 #include "asm/arch/user.h"
 
diff --git a/include/asm-um/processor-x86_64.h b/include/asm-um/processor-x86_64.h
index a1ae3a4cd938..0beb9a42ae05 100644
--- a/include/asm-um/processor-x86_64.h
+++ b/include/asm-um/processor-x86_64.h
@@ -7,9 +7,13 @@
 #ifndef __UM_PROCESSOR_X86_64_H
 #define __UM_PROCESSOR_X86_64_H
 
-#include "asm/arch/user.h"
+/* include faultinfo structure */
+#include "sysdep/faultinfo.h"
 
 struct arch_thread {
+        unsigned long debugregs[8];
+        int debugregs_seq;
+        struct faultinfo faultinfo;
 };
 
 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
@@ -20,7 +24,11 @@ extern inline void rep_nop(void)
 
 #define cpu_relax()   rep_nop()
 
-#define INIT_ARCH_THREAD { }
+#define INIT_ARCH_THREAD { .debugregs           = { [ 0 ... 7 ] = 0 }, \
+                           .debugregs_seq       = 0, \
+                           .faultinfo           = { 0, 0, 0 } }
+
+#include "asm/arch/user.h"
 
 #define current_text_addr() \
         ({ void *pc; __asm__("movq $1f,%0\n1:":"=g" (pc)); pc; })
diff --git a/include/asm-um/ptrace-i386.h b/include/asm-um/ptrace-i386.h
index 9e47590ec293..04222f35c43e 100644
--- a/include/asm-um/ptrace-i386.h
+++ b/include/asm-um/ptrace-i386.h
@@ -6,6 +6,8 @@
 #ifndef __UM_PTRACE_I386_H
 #define __UM_PTRACE_I386_H
 
+#define HOST_AUDIT_ARCH AUDIT_ARCH_I386
+
 #include "sysdep/ptrace.h"
 #include "asm/ptrace-generic.h"
 
diff --git a/include/asm-um/ptrace-x86_64.h b/include/asm-um/ptrace-x86_64.h
index c34be39b78b2..be51219a8ffe 100644
--- a/include/asm-um/ptrace-x86_64.h
+++ b/include/asm-um/ptrace-x86_64.h
@@ -14,6 +14,8 @@
 #include "asm/ptrace-generic.h"
 #undef signal_fault
 
+#define HOST_AUDIT_ARCH AUDIT_ARCH_X86_64
+
 void signal_fault(struct pt_regs_subarch *regs, void *frame, char *where);
 
 #define FS_BASE (21 * sizeof(unsigned long))
diff --git a/include/asm-um/setup.h b/include/asm-um/setup.h
index c85252e803c1..99f086301f4c 100644
--- a/include/asm-um/setup.h
+++ b/include/asm-um/setup.h
@@ -2,7 +2,8 @@
 #define SETUP_H_INCLUDED
 
 /* POSIX mandated with _POSIX_ARG_MAX that we can rely on 4096 chars in the
- * command line, so this choice is ok.*/
+ * command line, so this choice is ok.
+ */
 
 #define COMMAND_LINE_SIZE 4096
 
diff --git a/include/asm-um/thread_info.h b/include/asm-um/thread_info.h
index bffb577bc54e..1feaaf148ef1 100644
--- a/include/asm-um/thread_info.h
+++ b/include/asm-um/thread_info.h
@@ -41,18 +41,17 @@ struct thread_info {
 #define init_thread_info        (init_thread_union.thread_info)
 #define init_stack              (init_thread_union.stack)
 
+#define THREAD_SIZE ((1 << CONFIG_KERNEL_STACK_ORDER) * PAGE_SIZE)
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
 {
         struct thread_info *ti;
-        unsigned long mask = PAGE_SIZE *
-                (1 << CONFIG_KERNEL_STACK_ORDER) - 1;
-        ti = (struct thread_info *) (((unsigned long) &ti) & ~mask);
+        unsigned long mask = THREAD_SIZE - 1;
+        ti = (struct thread_info *) (((unsigned long) &ti) & ~mask);
         return ti;
 }
 
 /* thread information allocation */
-#define THREAD_SIZE ((1 << CONFIG_KERNEL_STACK_ORDER) * PAGE_SIZE)
 #define alloc_thread_info(tsk) \
         ((struct thread_info *) kmalloc(THREAD_SIZE, GFP_KERNEL))
 #define free_thread_info(ti) kfree(ti)
@@ -62,7 +61,7 @@ static inline struct thread_info *current_thread_info(void)
 
 #endif
 
-#define PREEMPT_ACTIVE          0x4000000
+#define PREEMPT_ACTIVE          0x10000000
 
 #define TIF_SYSCALL_TRACE       0       /* syscall trace active */
 #define TIF_SIGPENDING          1       /* signal pending */
@@ -72,12 +71,14 @@ static inline struct thread_info *current_thread_info(void)
                                          */
 #define TIF_RESTART_BLOCK       4
 #define TIF_MEMDIE              5
+#define TIF_SYSCALL_AUDIT       6
 
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
-#define _TIF_RESTART_BLOCK      (1 << TIF_RESTART_BLOCK)
+#define _TIF_MEMDIE             (1 << TIF_MEMDIE)
+#define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
 
 #endif
 
diff --git a/include/asm-v850/signal.h b/include/asm-v850/signal.h
index ec3566c875d9..cb52caa69925 100644
--- a/include/asm-v850/signal.h
+++ b/include/asm-v850/signal.h
@@ -110,17 +110,7 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
-
-/* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
-
+#include <asm-generic/signal.h>
 
 #ifdef __KERNEL__
 
diff --git a/include/asm-x86_64/agp.h b/include/asm-x86_64/agp.h
index 0bb9019d58aa..06c52ee9c06b 100644
--- a/include/asm-x86_64/agp.h
+++ b/include/asm-x86_64/agp.h
@@ -19,4 +19,14 @@ int unmap_page_from_agp(struct page *page);
    worth it. Would need a page for it. */
 #define flush_agp_cache() asm volatile("wbinvd":::"memory")
 
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
 #endif
diff --git a/include/asm-x86_64/apicdef.h b/include/asm-x86_64/apicdef.h
index 3d7627ffe67d..bfebdb690654 100644
--- a/include/asm-x86_64/apicdef.h
+++ b/include/asm-x86_64/apicdef.h
@@ -112,7 +112,7 @@
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 
-#define MAX_IO_APICS 32
+#define MAX_IO_APICS 128
 
 /*
  * All x86-64 systems are xAPIC compatible.
diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h
index bdbf66eab6ee..3d2a666a5dd5 100644
--- a/include/asm-x86_64/bug.h
+++ b/include/asm-x86_64/bug.h
@@ -21,6 +21,8 @@ struct bug_frame {
         asm volatile("ud2 ; .quad %c1 ; .short %c0" :: \
                      "i"(__LINE__), "i" (__stringify(__FILE__)))
 void out_of_line_bug(void);
+#else
+static inline void out_of_line_bug(void) { }
 #endif
 
 #include <asm-generic/bug.h>
diff --git a/include/asm-x86_64/floppy.h b/include/asm-x86_64/floppy.h
index bca9b28a1a0a..af7ded63b517 100644
--- a/include/asm-x86_64/floppy.h
+++ b/include/asm-x86_64/floppy.h
@@ -223,7 +223,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
         return 0;
 }
 
-struct fd_routine_l {
+static struct fd_routine_l {
         int (*_request_dma)(unsigned int dmanr, const char * device_id);
         void (*_free_dma)(unsigned int dmanr);
         int (*_get_dma_residue)(unsigned int dummy);
diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h
index 7efc932e8f0b..32573749004c 100644
--- a/include/asm-x86_64/io_apic.h
+++ b/include/asm-x86_64/io_apic.h
@@ -202,7 +202,6 @@ extern int skip_ioapic_setup;
 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 
 #ifdef CONFIG_ACPI_BOOT
-extern int io_apic_get_unique_id (int ioapic, int apic_id);
 extern int io_apic_get_version (int ioapic);
 extern int io_apic_get_redir_entries (int ioapic);
 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
diff --git a/include/asm-x86_64/ioctl32.h b/include/asm-x86_64/ioctl32.h
deleted file mode 100644
index d0d227f45e05..000000000000
--- a/include/asm-x86_64/ioctl32.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/ioctl32.h>
diff --git a/include/asm-x86_64/nmi.h b/include/asm-x86_64/nmi.h
index 21d56b086b9d..d3abfc6a8fd5 100644
--- a/include/asm-x86_64/nmi.h
+++ b/include/asm-x86_64/nmi.h
@@ -53,5 +53,7 @@ extern void die_nmi(char *str, struct pt_regs *regs);
 
 extern int panic_on_timeout;
 extern int unknown_nmi_panic;
+
+extern int check_nmi_watchdog(void);
  
 #endif /* ASM_NMI_H */
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index f0581c35628e..d641b19f6da5 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -62,7 +62,6 @@ struct cpuinfo_x86 {
         int     x86_tlbsize;    /* number of 4K pages in DTLB/ITLB combined(in pages)*/
         __u8    x86_virt_bits, x86_phys_bits;
         __u8    x86_num_cores;
-        __u8    x86_apicid;
         __u32   x86_power;      
         __u32   extended_cpuid_level;   /* Max extended CPUID function supported */
         unsigned long loops_per_jiffy;
@@ -159,9 +158,9 @@ static inline void clear_in_cr4 (unsigned long mask)
 
 
 /*
- * User space process size. 47bits.
+ * User space process size. 47bits minus one guard page.
  */
-#define TASK_SIZE       (0x800000000000UL)
+#define TASK_SIZE       (0x800000000000UL - 4096)
 
 /* This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
diff --git a/include/asm-x86_64/proto.h b/include/asm-x86_64/proto.h
index d0f8f8b4c394..f2f073642d62 100644
--- a/include/asm-x86_64/proto.h
+++ b/include/asm-x86_64/proto.h
@@ -30,6 +30,11 @@ extern void ia32_syscall(void);
 extern void iommu_hole_init(void);
 
 extern void time_init_gtod(void);
+extern int pmtimer_mark_offset(void);
+extern unsigned int do_gettimeoffset_pm(void);
+extern u32 pmtmr_ioport;
+extern unsigned long long monotonic_base;
+extern int sysctl_vsyscall;
 
 extern void do_softirq_thunk(void);
 
diff --git a/include/asm-x86_64/signal.h b/include/asm-x86_64/signal.h
index 4987ad8082ba..fe9b96d94815 100644
--- a/include/asm-x86_64/signal.h
+++ b/include/asm-x86_64/signal.h
@@ -116,21 +116,9 @@ typedef unsigned long sigset_t;
 #define MINSIGSTKSZ     2048
 #define SIGSTKSZ        8192
 
-#define SIG_BLOCK          0    /* for blocking signals */
-#define SIG_UNBLOCK        1    /* for unblocking signals */
-#define SIG_SETMASK        2    /* for setting the signal mask */
+#include <asm-generic/signal.h>
 
 #ifndef __ASSEMBLY__
-/* Type of a signal handler.  */
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-
-typedef void __restorefn_t(void);
-typedef __restorefn_t __user *__sigrestore_t;
-
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
 
 struct sigaction {
         __sighandler_t sa_handler;
diff --git a/include/asm-x86_64/vsyscall.h b/include/asm-x86_64/vsyscall.h
index b0c8d4339906..2872da23fc7e 100644
--- a/include/asm-x86_64/vsyscall.h
+++ b/include/asm-x86_64/vsyscall.h
@@ -25,6 +25,7 @@ enum vsyscall_num {
 
 #define VXTIME_TSC      1
 #define VXTIME_HPET     2
+#define VXTIME_PMTMR    3
 
 struct vxtime_data {
         long hpet_address;      /* HPET base address */
@@ -54,6 +55,8 @@ extern struct timezone sys_tz;
 extern int sysctl_vsyscall;
 extern seqlock_t xtime_lock;
 
+extern int sysctl_vsyscall;
+
 #define ARCH_HAVE_XTIME_LOCK 1
 
 #endif /* __KERNEL__ */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index aefe6d051ace..b123cc08773d 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -25,6 +25,10 @@
 #ifndef _LINUX_ACPI_H
 #define _LINUX_ACPI_H
 
+#include <linux/config.h>
+
+#ifdef  CONFIG_ACPI
+
 #ifndef _LINUX
 #define _LINUX
 #endif
@@ -533,4 +537,5 @@ static inline int acpi_get_pxm(acpi_handle handle)
 
 extern int pnpacpi_disabled;
 
-#endif /*_LINUX_ACPI_H*/
+#endif  /* CONFIG_ACPI */
+#endif  /*_LINUX_ACPI_H*/
diff --git a/include/linux/audit.h b/include/linux/audit.h
index 3628f7cfb178..19f04b049798 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -1,4 +1,4 @@
-/* audit.h -- Auditing support -*- linux-c -*-
+/* audit.h -- Auditing support
  *
  * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina.
  * All Rights Reserved.
@@ -24,6 +24,9 @@
 #ifndef _LINUX_AUDIT_H_
 #define _LINUX_AUDIT_H_
 
+#include <linux/sched.h>
+#include <linux/elf.h>
+
 /* Request and reply types */
 #define AUDIT_GET      1000     /* Get status */
 #define AUDIT_SET      1001     /* Set status (enable/disable/auditd) */
@@ -67,6 +70,7 @@
 #define AUDIT_FSGID     8
 #define AUDIT_LOGINUID  9
 #define AUDIT_PERS      10
+#define AUDIT_ARCH      11
 
                                 /* These are ONLY useful when checking
                                  * at syscall exit time (AUDIT_AT_EXIT). */
@@ -96,6 +100,38 @@
 #define AUDIT_FAIL_PRINTK       1
 #define AUDIT_FAIL_PANIC        2
 
+/* distinguish syscall tables */
+#define __AUDIT_ARCH_64BIT 0x80000000
+#define __AUDIT_ARCH_LE    0x40000000
+#define AUDIT_ARCH_ALPHA        (EM_ALPHA|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_ARM          (EM_ARM|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_ARMEB        (EM_ARM)
+#define AUDIT_ARCH_CRIS         (EM_CRIS|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_FRV          (EM_FRV)
+#define AUDIT_ARCH_H8300        (EM_H8_300)
+#define AUDIT_ARCH_I386         (EM_386|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_IA64         (EM_IA_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_M32R         (EM_M32R)
+#define AUDIT_ARCH_M68K         (EM_68K)
+#define AUDIT_ARCH_MIPS         (EM_MIPS)
+#define AUDIT_ARCH_MIPSEL       (EM_MIPS|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_MIPS64       (EM_MIPS|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_MIPSEL64     (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_PARISC       (EM_PARISC)
+#define AUDIT_ARCH_PARISC64     (EM_PARISC|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_PPC          (EM_PPC)
+#define AUDIT_ARCH_PPC64        (EM_PPC64|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_S390         (EM_S390)
+#define AUDIT_ARCH_S390X        (EM_S390|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_SH           (EM_SH)
+#define AUDIT_ARCH_SHEL         (EM_SH|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_SH64         (EM_SH|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_SHEL64       (EM_SH|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_SPARC        (EM_SPARC)
+#define AUDIT_ARCH_SPARC64      (EM_SPARC64|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_V850         (EM_V850|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_X86_64       (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
+
 #ifndef __KERNEL__
 struct audit_message {
         struct nlmsghdr nlh;
@@ -129,32 +165,36 @@ struct audit_buffer;
 struct audit_context;
 struct inode;
 
+#define AUDITSC_INVALID 0
+#define AUDITSC_SUCCESS 1
+#define AUDITSC_FAILURE 2
+#define AUDITSC_RESULT(x) ( ((long)(x))<0?AUDITSC_FAILURE:AUDITSC_SUCCESS )
 #ifdef CONFIG_AUDITSYSCALL
 /* These are defined in auditsc.c */
                                 /* Public API */
 extern int  audit_alloc(struct task_struct *task);
 extern void audit_free(struct task_struct *task);
-extern void audit_syscall_entry(struct task_struct *task,
+extern void audit_syscall_entry(struct task_struct *task, int arch,
                                 int major, unsigned long a0, unsigned long a1,
                                 unsigned long a2, unsigned long a3);
-extern void audit_syscall_exit(struct task_struct *task, int return_code);
+extern void audit_syscall_exit(struct task_struct *task, int failed, long return_code);
 extern void audit_getname(const char *name);
 extern void audit_putname(const char *name);
 extern void audit_inode(const char *name, const struct inode *inode);
 
                                 /* Private API (for audit.c only) */
 extern int  audit_receive_filter(int type, int pid, int uid, int seq,
-                                 void *data);
+                                 void *data, uid_t loginuid);
 extern void audit_get_stamp(struct audit_context *ctx,
-                            struct timespec *t, int *serial);
-extern int  audit_set_loginuid(struct audit_context *ctx, uid_t loginuid);
+                            struct timespec *t, unsigned int *serial);
+extern int  audit_set_loginuid(struct task_struct *task, uid_t loginuid);
 extern uid_t audit_get_loginuid(struct audit_context *ctx);
 extern int audit_ipc_perms(unsigned long qbytes, uid_t uid, gid_t gid, mode_t mode);
 #else
 #define audit_alloc(t) ({ 0; })
 #define audit_free(t) do { ; } while (0)
-#define audit_syscall_entry(t,a,b,c,d,e) do { ; } while (0)
-#define audit_syscall_exit(t,r) do { ; } while (0)
+#define audit_syscall_entry(t,ta,a,b,c,d,e) do { ; } while (0)
+#define audit_syscall_exit(t,f,r) do { ; } while (0)
 #define audit_getname(n) do { ; } while (0)
 #define audit_putname(n) do { ; } while (0)
 #define audit_inode(n,i) do { ; } while (0)
@@ -174,11 +214,15 @@ extern void		    audit_log_format(struct audit_buffer *ab,
                                              const char *fmt, ...)
                             __attribute__((format(printf,2,3)));
 extern void                 audit_log_end(struct audit_buffer *ab);
+extern void                 audit_log_hex(struct audit_buffer *ab,
+                                          const unsigned char *buf,
+                                          size_t len);
+extern void                 audit_log_untrustedstring(struct audit_buffer *ab,
+                                                      const char *string);
 extern void                 audit_log_d_path(struct audit_buffer *ab,
                                              const char *prefix,
                                              struct dentry *dentry,
                                              struct vfsmount *vfsmnt);
-
                                 /* Private API (for auditsc.c only) */
 extern void                 audit_send_reply(int pid, int seq, int type,
                                              int done, int multi,
@@ -190,6 +234,8 @@ extern void		    audit_log_lost(const char *message);
 #define audit_log_vformat(b,f,a) do { ; } while (0)
 #define audit_log_format(b,f,...) do { ; } while (0)
 #define audit_log_end(b) do { ; } while (0)
+#define audit_log_hex(a,b,l) do { ; } while (0)
+#define audit_log_untrustedstring(a,s) do { ; } while (0)
 #define audit_log_d_path(b,p,d,v) do { ; } while (0)
 #endif
 #endif
diff --git a/include/linux/awe_voice.h b/include/linux/awe_voice.h
index da0e27de752c..4bf9f33048e2 100644
--- a/include/linux/awe_voice.h
+++ b/include/linux/awe_voice.h
@@ -29,9 +29,9 @@
 #define SAMPLE_TYPE_AWE32       0x20
 #endif
 
-#ifndef _PATCHKEY
-#define _PATCHKEY(id) ((id<<8)|0xfd)
-#endif
+#define _LINUX_PATCHKEY_H_INDIRECT
+#include <linux/patchkey.h>
+#undef _LINUX_PATCHKEY_H_INDIRECT
 
 /*----------------------------------------------------------------
  * patch information record
diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h
index 54f820832c73..7e736e201c46 100644
--- a/include/linux/binfmts.h
+++ b/include/linux/binfmts.h
@@ -77,7 +77,6 @@ extern int flush_old_exec(struct linux_binprm * bprm);
 extern int setup_arg_pages(struct linux_binprm * bprm,
                            unsigned long stack_top,
                            int executable_stack);
-extern int copy_strings(int argc,char __user * __user * argv,struct linux_binprm *bprm); 
 extern int copy_strings_kernel(int argc,char ** argv,struct linux_binprm *bprm);
 extern void compute_creds(struct linux_binprm *binprm);
 extern int do_coredump(long signr, int exit_code, struct pt_regs * regs);
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index f21af067d015..927daa86c9b3 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -49,7 +49,7 @@ int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list);
 /* Frequency values here are CPU kHz so that hardware which doesn't run 
  * with some frequencies can complain without having to guess what per 
  * cent / per mille means. 
- * Maximum transition latency is in microseconds - if it's unknown,
+ * Maximum transition latency is in nanoseconds - if it's unknown,
  * CPUFREQ_ETERNAL shall be used.
  */
 
diff --git a/include/linux/device.h b/include/linux/device.h
index cf470459fa69..df94c0de53f2 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -273,9 +273,6 @@ struct device {
                                            BIOS data relevant to device) */
         struct dev_pm_info      power;
 
-        u32             detach_state;   /* State to enter when device is
-                                           detached from its driver. */
-
         u64             *dma_mask;      /* dma mask (if dma'able device) */
         u64             coherent_dma_mask;/* Like dma_mask, but for
                                              alloc_coherent mappings as
diff --git a/include/linux/err.h b/include/linux/err.h
index 17c55df13615..ff71d2af5da3 100644
--- a/include/linux/err.h
+++ b/include/linux/err.h
@@ -13,6 +13,8 @@
  * This should be a per-architecture thing, to allow different
  * error and pointer decisions.
  */
+#define IS_ERR_VALUE(x) unlikely((x) > (unsigned long)-1000L)
+
 static inline void *ERR_PTR(long error)
 {
         return (void *) error;
@@ -25,7 +27,7 @@ static inline long PTR_ERR(const void *ptr)
 
 static inline long IS_ERR(const void *ptr)
 {
-        return unlikely((unsigned long)ptr > (unsigned long)-1000L);
+        return IS_ERR_VALUE((unsigned long)ptr);
 }
 
 #endif /* _LINUX_ERR_H */
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index 396c48cbaeb1..a1478258d002 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)eth.h       1.0.4   05/13/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              Relocated to include/linux where it belongs by Alan Cox 
@@ -56,18 +56,32 @@ static inline int is_zero_ether_addr(const u8 *addr)
 }
 
 /**
+ * is_multicast_ether_addr - Determine if the given Ethernet address is a
+ * multicast address.
+ *
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 *addr)
+{
+        return addr[0] & 0x01;
+}
+
+/**
  * is_valid_ether_addr - Determine if the given Ethernet address is valid
  * @addr: Pointer to a six-byte array containing the Ethernet address
  *
  * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
- * a multicast address, and is not FF:FF:FF:FF:FF:FF.  The multicast
- * and FF:FF:... tests are combined into the single test "!(addr[0]&1)".
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
  *
  * Return true if the address is valid.
  */
 static inline int is_valid_ether_addr(const u8 *addr)
 {
-        return !(addr[0]&1) && !is_zero_ether_addr(addr);
+        /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+         * explicitly check for it here. */
+        return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
 }
 
 /**
@@ -83,6 +97,6 @@ static inline void random_ether_addr(u8 *addr)
         addr [0] &= 0xfe;       /* clear multicast bit */
         addr [0] |= 0x02;       /* set local assignment bit (IEEE802) */
 }
-#endif
+#endif  /* __KERNEL__ */
 
 #endif  /* _LINUX_ETHERDEVICE_H */
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index c85b210490ea..a0ab26aab450 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -256,6 +256,7 @@ struct net_device;
 u32 ethtool_op_get_link(struct net_device *dev);
 u32 ethtool_op_get_tx_csum(struct net_device *dev);
 int ethtool_op_set_tx_csum(struct net_device *dev, u32 data);
+int ethtool_op_set_tx_hw_csum(struct net_device *dev, u32 data);
 u32 ethtool_op_get_sg(struct net_device *dev);
 int ethtool_op_set_sg(struct net_device *dev, u32 data);
 u32 ethtool_op_get_tso(struct net_device *dev);
diff --git a/include/linux/fddidevice.h b/include/linux/fddidevice.h
index 2e5ee47f3e1e..002f6367697d 100644
--- a/include/linux/fddidevice.h
+++ b/include/linux/fddidevice.h
@@ -10,7 +10,7 @@
  * Author:      Lawrence V. Stefani, <stefani@lkg.dec.com>
  *
  *              fddidevice.h is based on previous trdevice.h work by
- *                      Ross Biro, <bir7@leland.Stanford.Edu>
+ *                      Ross Biro
  *                      Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *                      Alan Cox, <gw4pts@gw4pts.ampr.org>
  *
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 4edba067a717..0180102dace1 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1341,7 +1341,7 @@ extern int fs_may_remount_ro(struct super_block *);
 
 extern int check_disk_change(struct block_device *);
 extern int invalidate_inodes(struct super_block *);
-extern int __invalidate_device(struct block_device *, int);
+extern int __invalidate_device(struct block_device *);
 extern int invalidate_partition(struct gendisk *, int);
 unsigned long invalidate_mapping_pages(struct address_space *mapping,
                                         pgoff_t start, pgoff_t end);
diff --git a/include/linux/gameport.h b/include/linux/gameport.h
index b1272f822cfa..cd623eccdbea 100644
--- a/include/linux/gameport.h
+++ b/include/linux/gameport.h
@@ -67,6 +67,8 @@ int gameport_open(struct gameport *gameport, struct gameport_driver *drv, int mo
 void gameport_close(struct gameport *gameport);
 void gameport_rescan(struct gameport *gameport);
 
+#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
+
 void __gameport_register_port(struct gameport *gameport, struct module *owner);
 static inline void gameport_register_port(struct gameport *gameport)
 {
@@ -75,6 +77,29 @@ static inline void gameport_register_port(struct gameport *gameport)
 
 void gameport_unregister_port(struct gameport *gameport);
 
+void gameport_set_phys(struct gameport *gameport, const char *fmt, ...)
+        __attribute__ ((format (printf, 2, 3)));
+
+#else
+
+static inline void gameport_register_port(struct gameport *gameport)
+{
+        return;
+}
+
+static inline void gameport_unregister_port(struct gameport *gameport)
+{
+        return;
+}
+
+static inline void gameport_set_phys(struct gameport *gameport,
+                                     const char *fmt, ...)
+{
+        return;
+}
+
+#endif
+
 static inline struct gameport *gameport_allocate_port(void)
 {
         struct gameport *gameport = kcalloc(1, sizeof(struct gameport), GFP_KERNEL);
@@ -92,9 +117,6 @@ static inline void gameport_set_name(struct gameport *gameport, const char *name
         strlcpy(gameport->name, name, sizeof(gameport->name));
 }
 
-void gameport_set_phys(struct gameport *gameport, const char *fmt, ...)
-        __attribute__ ((format (printf, 2, 3)));
-
 /*
  * Use the following fucntions to manipulate gameport's per-port
  * driver-specific data.
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index ebc712e91066..8336dba18971 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -43,13 +43,17 @@
 #define __IRQ_MASK(x)   ((1UL << (x))-1)
 
 #define PREEMPT_MASK    (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT)
-#define HARDIRQ_MASK    (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT)
 #define SOFTIRQ_MASK    (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT)
+#define HARDIRQ_MASK    (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT)
 
 #define PREEMPT_OFFSET  (1UL << PREEMPT_SHIFT)
 #define SOFTIRQ_OFFSET  (1UL << SOFTIRQ_SHIFT)
 #define HARDIRQ_OFFSET  (1UL << HARDIRQ_SHIFT)
 
+#if PREEMPT_ACTIVE < (1 << (HARDIRQ_SHIFT + HARDIRQ_BITS))
+#error PREEMPT_ACTIVE is too low!
+#endif
+
 #define hardirq_count() (preempt_count() & HARDIRQ_MASK)
 #define softirq_count() (preempt_count() & SOFTIRQ_MASK)
 #define irq_count()     (preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK))
diff --git a/include/linux/hippidevice.h b/include/linux/hippidevice.h
index 89b3a4a5b761..9debe6bbe5f0 100644
--- a/include/linux/hippidevice.h
+++ b/include/linux/hippidevice.h
@@ -10,7 +10,7 @@
  * Author:      Jes Sorensen, <Jes.Sorensen@cern.ch>
  *
  *              hippidevice.h is based on previous fddidevice.h work by
- *                      Ross Biro, <bir7@leland.Stanford.Edu>
+ *                      Ross Biro
  *                      Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *                      Alan Cox, <gw4pts@gw4pts.ampr.org>
  *                      Lawrence V. Stefani, <stefani@lkg.dec.com>
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 9cfc0999becb..336d6e509f59 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -664,7 +664,6 @@ typedef struct ide_drive_s {
 
         struct request          *rq;    /* current request */
         struct ide_drive_s      *next;  /* circular list of hwgroup drives */
-        struct ide_driver_s     *driver;/* (ide_driver_t *) */
         void            *driver_data;   /* extra driver data */
         struct hd_driveid       *id;    /* drive model identification info */
         struct proc_dir_entry *proc;    /* /proc/ide/ directory entry */
@@ -758,6 +757,8 @@ typedef struct ide_drive_s {
         struct semaphore gendev_rel_sem;        /* to deal with device release() */
 } ide_drive_t;
 
+#define to_ide_device(dev)container_of(dev, ide_drive_t, gendev)
+
 #define IDE_CHIPSET_PCI_MASK    \
     ((1<<ide_pci)|(1<<ide_cmd646)|(1<<ide_ali14xx))
 #define IDE_CHIPSET_IS_PCI(c)   ((IDE_CHIPSET_PCI_MASK >> (c)) & 1)
@@ -1086,28 +1087,20 @@ enum {
  */
 typedef struct ide_driver_s {
         struct module                   *owner;
-        const char                      *name;
         const char                      *version;
         u8                              media;
-        unsigned busy                   : 1;
         unsigned supports_dsc_overlap   : 1;
-        int             (*cleanup)(ide_drive_t *);
         ide_startstop_t (*do_request)(ide_drive_t *, struct request *, sector_t);
         int             (*end_request)(ide_drive_t *, int, int);
         ide_startstop_t (*error)(ide_drive_t *, struct request *rq, u8, u8);
         ide_startstop_t (*abort)(ide_drive_t *, struct request *rq);
         int             (*ioctl)(ide_drive_t *, struct inode *, struct file *, unsigned int, unsigned long);
         ide_proc_entry_t        *proc;
-        int             (*attach)(ide_drive_t *);
         void            (*ata_prebuilder)(ide_drive_t *);
         void            (*atapi_prebuilder)(ide_drive_t *);
         struct device_driver    gen_driver;
-        struct list_head drives;
-        struct list_head drivers;
 } ide_driver_t;
 
-#define DRIVER(drive)           ((drive)->driver)
-
 int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsigned, unsigned long);
 
 /*
@@ -1328,8 +1321,6 @@ extern void ide_init_subdrivers(void);
 
 void ide_init_disk(struct gendisk *, ide_drive_t *);
 
-extern int ata_attach(ide_drive_t *);
-
 extern int ideprobe_init(void);
 
 extern void ide_scan_pcibus(int scan_direction) __init;
@@ -1342,11 +1333,8 @@ extern void default_hwif_iops(ide_hwif_t *);
 extern void default_hwif_mmiops(ide_hwif_t *);
 extern void default_hwif_transport(ide_hwif_t *);
 
-int ide_register_driver(ide_driver_t *driver);
-void ide_unregister_driver(ide_driver_t *driver);
-int ide_register_subdriver(ide_drive_t *, ide_driver_t *);
-int ide_unregister_subdriver (ide_drive_t *drive);
-int ide_replace_subdriver(ide_drive_t *drive, const char *driver);
+void ide_register_subdriver(ide_drive_t *, ide_driver_t *);
+void ide_unregister_subdriver(ide_drive_t *, ide_driver_t *);
 
 #define ON_BOARD                1
 #define NEVER_BOARD             0
diff --git a/include/linux/if.h b/include/linux/if.h
index 110282dbd3e0..d73a9d62f208 100644
--- a/include/linux/if.h
+++ b/include/linux/if.h
@@ -8,7 +8,7 @@
  * Version:     @(#)if.h        1.0.2   04/18/93
  *
  * Authors:     Original taken from Berkeley UNIX 4.3, (c) UCB 1982-1988
- *              Ross Biro, <bir7@leland.Stanford.Edu>
+ *              Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              This program is free software; you can redistribute it and/or
diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h
index bbf49bcd7705..0856548a2a08 100644
--- a/include/linux/if_arp.h
+++ b/include/linux/if_arp.h
@@ -9,7 +9,7 @@
  *
  * Authors:     Original taken from Berkeley UNIX 4.3, (c) UCB 1986-1988
  *              Portions taken from the KA9Q/NOS (v2.00m PA0GRI) source.
- *              Ross Biro, <bir7@leland.Stanford.Edu>
+ *              Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Florian La Roche,
  *              Jonathan Layes <layes@loran.com>
diff --git a/include/linux/if_ltalk.h b/include/linux/if_ltalk.h
index e75e832b7ff0..76525760ba48 100644
--- a/include/linux/if_ltalk.h
+++ b/include/linux/if_ltalk.h
@@ -6,7 +6,7 @@
 #define LTALK_ALEN              1
 
 #ifdef __KERNEL__
-extern void ltalk_setup(struct net_device *);
+extern struct net_device *alloc_ltalkdev(int sizeof_priv);
 #endif
 
 #endif
diff --git a/include/linux/if_shaper.h b/include/linux/if_shaper.h
index 0485b256d043..004e6f09a6e2 100644
--- a/include/linux/if_shaper.h
+++ b/include/linux/if_shaper.h
@@ -23,7 +23,7 @@ struct shaper
         __u32 shapeclock;
         unsigned long recovery; /* Time we can next clock a packet out on
                                    an empty queue */
-        unsigned long locked;
+        struct semaphore sem;
         struct net_device_stats stats;
         struct net_device *dev;
         int  (*hard_start_xmit) (struct sk_buff *skb,
@@ -38,7 +38,6 @@ struct shaper
         int (*hard_header_cache)(struct neighbour *neigh, struct hh_cache *hh);
         void (*header_cache_update)(struct hh_cache *hh, struct net_device *dev, unsigned char *  haddr);
         struct net_device_stats* (*get_stats)(struct net_device *dev);
-        wait_queue_head_t  wait_queue;
         struct timer_list timer;
 };
 
diff --git a/include/linux/if_tr.h b/include/linux/if_tr.h
index 4fd451f81ccb..3fba9e2f5427 100644
--- a/include/linux/if_tr.h
+++ b/include/linux/if_tr.h
@@ -9,7 +9,7 @@
  *
  * Author:      Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Donald Becker, <becker@super.org>
- *    Peter De Schrijver, <stud11@cc4.kuleuven.ac.be>
+ *              Peter De Schrijver, <stud11@cc4.kuleuven.ac.be>
  *
  *              This program is free software; you can redistribute it and/or
  *              modify it under the terms of the GNU General Public License
@@ -19,24 +19,18 @@
 #ifndef _LINUX_IF_TR_H
 #define _LINUX_IF_TR_H
 
+#include <asm/byteorder.h>      /* For __be16 */
 
 /* IEEE 802.5 Token-Ring magic constants.  The frame sizes omit the preamble
    and FCS/CRC (frame check sequence). */
-#define TR_ALEN 6               /* Octets in one ethernet addr   */
-#define TR_HLEN   (sizeof(struct trh_hdr)+sizeof(struct trllc))
-#define AC                      0x10
-#define LLC_FRAME 0x40
-#if 0
-#define ETH_HLEN        14              /* Total octets in header.       */
-#define ETH_ZLEN        60              /* Min. octets in frame sans FCS */
-#define ETH_DATA_LEN    1500            /* Max. octets in payload        */
-#define ETH_FRAME_LEN   1514            /* Max. octets in frame sans FCS */
-#endif
-
+#define TR_ALEN         6               /* Octets in one token-ring addr */
+#define TR_HLEN         (sizeof(struct trh_hdr)+sizeof(struct trllc))
+#define AC              0x10
+#define LLC_FRAME       0x40
 
 /* LLC and SNAP constants */
-#define EXTENDED_SAP 0xAA
-#define UI_CMD       0x03
+#define EXTENDED_SAP    0xAA
+#define UI_CMD          0x03
 
 /* This is an Token-Ring frame header. */
 struct trh_hdr {
@@ -44,8 +38,8 @@ struct trh_hdr {
         __u8  fc;                       /* frame control field */
         __u8  daddr[TR_ALEN];           /* destination address */
         __u8  saddr[TR_ALEN];           /* source address */
-        __u16 rcf;                      /* route control field */
-        __u16 rseg[8];                  /* routing registers */
+        __be16 rcf;                     /* route control field */
+        __be16 rseg[8];                 /* routing registers */
 };
 
 #ifdef __KERNEL__
@@ -63,7 +57,7 @@ struct trllc {
         __u8  ssap;                     /* source SAP */
         __u8  llc;                      /* LLC control field */
         __u8  protid[3];                /* protocol id */
-        __u16 ethertype;                /* ether type field */
+        __be16 ethertype;               /* ether type field */
 };
 
 /* Token-Ring statistics collection data. */
@@ -96,14 +90,13 @@ struct tr_statistics {
 };
 
 /* source routing stuff */
-
-#define TR_RII 0x80
-#define TR_RCF_DIR_BIT 0x80
-#define TR_RCF_LEN_MASK 0x1f00
-#define TR_RCF_BROADCAST 0x8000         /* all-routes broadcast */
-#define TR_RCF_LIMITED_BROADCAST 0xC000 /* single-route broadcast */
-#define TR_RCF_FRAME2K 0x20
-#define TR_RCF_BROADCAST_MASK 0xC000
-#define TR_MAXRIFLEN 18
+#define TR_RII                  0x80
+#define TR_RCF_DIR_BIT          0x80
+#define TR_RCF_LEN_MASK         0x1f00
+#define TR_RCF_BROADCAST        0x8000  /* all-routes broadcast */
+#define TR_RCF_LIMITED_BROADCAST 0xC000 /* single-route broadcast */
+#define TR_RCF_FRAME2K          0x20
+#define TR_RCF_BROADCAST_MASK   0xC000
+#define TR_MAXRIFLEN            18
 
 #endif  /* _LINUX_IF_TR_H */
diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h
index 6fafb27877a7..7e1e15f934f3 100644
--- a/include/linux/inetdevice.h
+++ b/include/linux/inetdevice.h
@@ -29,6 +29,7 @@ struct ipv4_devconf
         int     no_xfrm;
         int     no_policy;
         int     force_igmp_version;
+        int     promote_secondaries;
         void    *sysctl;
 };
 
@@ -71,6 +72,7 @@ struct in_device
 #define IN_DEV_SEC_REDIRECTS(in_dev)    (ipv4_devconf.secure_redirects || (in_dev)->cnf.secure_redirects)
 #define IN_DEV_IDTAG(in_dev)            ((in_dev)->cnf.tag)
 #define IN_DEV_MEDIUM_ID(in_dev)        ((in_dev)->cnf.medium_id)
+#define IN_DEV_PROMOTE_SECONDARIES(in_dev)      (ipv4_devconf.promote_secondaries || (in_dev)->cnf.promote_secondaries)
 
 #define IN_DEV_RX_REDIRECTS(in_dev) \
         ((IN_DEV_FORWARD(in_dev) && \
diff --git a/include/linux/ixjuser.h b/include/linux/ixjuser.h
index 88121166d715..fd1756d3a47e 100644
--- a/include/linux/ixjuser.h
+++ b/include/linux/ixjuser.h
@@ -42,8 +42,6 @@
  *
  *****************************************************************************/
 
-static char ixjuser_h_rcsid[] = "$Id: ixjuser.h,v 4.1 2001/08/05 00:17:37 craigs Exp $";
-
 #include <linux/telephony.h>
 
 
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index f20c163de4f5..99ddba5a4e00 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -43,6 +43,9 @@ typedef int (*kprobe_fault_handler_t) (struct kprobe *, struct pt_regs *,
 struct kprobe {
         struct hlist_node hlist;
 
+        /* list of kprobes for multi-handler support */
+        struct list_head list;
+
         /* location of the probe point */
         kprobe_opcode_t *addr;
 
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 505160ab472b..b009f801e7c5 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -410,6 +410,7 @@ extern u8 ata_chk_err(struct ata_port *ap);
 extern void ata_exec_command(struct ata_port *ap, struct ata_taskfile *tf);
 extern int ata_port_start (struct ata_port *ap);
 extern void ata_port_stop (struct ata_port *ap);
+extern void ata_host_stop (struct ata_host_set *host_set);
 extern irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 extern void ata_qc_prep(struct ata_queued_cmd *qc);
 extern int ata_qc_issue_prot(struct ata_queued_cmd *qc);
@@ -466,12 +467,34 @@ static inline u8 ata_chk_status(struct ata_port *ap)
         return ap->ops->check_status(ap);
 }
 
+
+/**
+ *      ata_pause - Flush writes and pause 400 nanoseconds.
+ *      @ap: Port to wait for.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+
 static inline void ata_pause(struct ata_port *ap)
 {
         ata_altstatus(ap);
         ndelay(400);
 }
 
+
+/**
+ *      ata_busy_wait - Wait for a port status register
+ *      @ap: Port to wait for.
+ *
+ *      Waits up to max*10 microseconds for the selected bits in the port's
+ *      status register to be cleared.
+ *      Returns final value of status register.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+
 static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits,
                                unsigned int max)
 {
@@ -486,6 +509,18 @@ static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits,
         return status;
 }
 
+
+/**
+ *      ata_wait_idle - Wait for a port to be idle.
+ *      @ap: Port to wait for.
+ *
+ *      Waits up to 10ms for port's BUSY and DRQ signals to clear.
+ *      Returns final value of status register.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+
 static inline u8 ata_wait_idle(struct ata_port *ap)
 {
         u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
@@ -524,6 +559,18 @@ static inline void ata_tf_init(struct ata_port *ap, struct ata_taskfile *tf, uns
                 tf->device = ATA_DEVICE_OBS | ATA_DEV1;
 }
 
+
+/**
+ *      ata_irq_on - Enable interrupts on a port.
+ *      @ap: Port on which interrupts are enabled.
+ *
+ *      Enable interrupts on a legacy IDE device using MMIO or PIO,
+ *      wait for idle, clear any pending interrupts.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+
 static inline u8 ata_irq_on(struct ata_port *ap)
 {
         struct ata_ioports *ioaddr = &ap->ioaddr;
@@ -543,6 +590,18 @@ static inline u8 ata_irq_on(struct ata_port *ap)
         return tmp;
 }
 
+
+/**
+ *      ata_irq_ack - Acknowledge a device interrupt.
+ *      @ap: Port on which interrupts are enabled.
+ *
+ *      Wait up to 10 ms for legacy IDE device to become idle (BUSY
+ *      or BUSY+DRQ clear).  Obtain dma status and port status from
+ *      device.  Clear the interrupt.  Return port status.
+ *
+ *      LOCKING:
+ */
+
 static inline u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq)
 {
         unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
@@ -584,6 +643,13 @@ static inline void scr_write(struct ata_port *ap, unsigned int reg, u32 val)
         ap->ops->scr_write(ap, reg, val);
 }
 
+static inline void scr_write_flush(struct ata_port *ap, unsigned int reg, 
+                                   u32 val)
+{
+        ap->ops->scr_write(ap, reg, val);
+        (void) ap->ops->scr_read(ap, reg);
+}
+
 static inline unsigned int sata_dev_present(struct ata_port *ap)
 {
         return ((scr_read(ap, SCR_STATUS) & 0xf) == 0x3) ? 1 : 0;
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 20971fe78a8d..374b615ea9ea 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -65,9 +65,13 @@
 #define ADVERTISE_SLCT          0x001f  /* Selector bits               */
 #define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
 #define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
 #define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
 #define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
@@ -84,9 +88,13 @@
 /* Link partner ability register. */
 #define LPA_SLCT                0x001f  /* Same as advertise selector  */
 #define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
 #define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
 #define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
 #define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
 #define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
 #define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
 #define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 8b007ad2d450..17518fe0b311 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -637,9 +637,9 @@ extern unsigned long do_mremap(unsigned long addr,
  * These functions are passed a count `nr_to_scan' and a gfpmask.  They should
  * scan `nr_to_scan' objects, attempting to free them.
  *
- * The callback must the number of objects which remain in the cache.
+ * The callback must return the number of objects which remain in the cache.
  *
- * The callback will be passes nr_to_scan == 0 when the VM is querying the
+ * The callback will be passed nr_to_scan == 0 when the VM is querying the
  * cache size, so a fastpath for that case is appropriate.
  */
 typedef int (*shrinker_t)(int nr_to_scan, unsigned int gfp_mask);
diff --git a/include/linux/mmc/protocol.h b/include/linux/mmc/protocol.h
index 7b904c5102f6..896342817b97 100644
--- a/include/linux/mmc/protocol.h
+++ b/include/linux/mmc/protocol.h
@@ -195,6 +195,33 @@ struct _mmc_csd {
 #define MMC_VDD_35_36   0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 #define MMC_CARD_BUSY   0x80000000      /* Card Power up status bit */
 
+/*
+ * Card Command Classes (CCC)
+ */
+#define CCC_BASIC               (1<<0)  /* (0) Basic protocol functions */
+                                        /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
+#define CCC_STREAM_READ         (1<<1)  /* (1) Stream read commands */
+                                        /* (CMD11) */
+#define CCC_BLOCK_READ          (1<<2)  /* (2) Block read commands */
+                                        /* (CMD16,17,18) */
+#define CCC_STREAM_WRITE        (1<<3)  /* (3) Stream write commands */
+                                        /* (CMD20) */
+#define CCC_BLOCK_WRITE         (1<<4)  /* (4) Block write commands */
+                                        /* (CMD16,24,25,26,27) */
+#define CCC_ERASE               (1<<5)  /* (5) Ability to erase blocks */
+                                        /* (CMD32,33,34,35,36,37,38,39) */
+#define CCC_WRITE_PROT          (1<<6)  /* (6) Able to write protect blocks */
+                                        /* (CMD28,29,30) */
+#define CCC_LOCK_CARD           (1<<7)  /* (7) Able to lock down card */
+                                        /* (CMD16,CMD42) */
+#define CCC_APP_SPEC            (1<<8)  /* (8) Application specific */
+                                        /* (CMD55,56,57,ACMD*) */
+#define CCC_IO_MODE             (1<<9)  /* (9) I/O mode */
+                                        /* (CMD5,39,40,52,53) */
+#define CCC_SWITCH              (1<<10) /* (10) High speed switch */
+                                        /* (CMD6,34,35,36,37,50) */
+                                        /* (11) Reserved */
+                                        /* (CMD?) */
 
 /*
  * CSD field definitions
diff --git a/include/linux/mpage.h b/include/linux/mpage.h
index dea1b0083661..3ca880463c47 100644
--- a/include/linux/mpage.h
+++ b/include/linux/mpage.h
@@ -20,9 +20,6 @@ int mpage_writepages(struct address_space *mapping,
                 struct writeback_control *wbc, get_block_t get_block);
 int mpage_writepage(struct page *page, get_block_t *get_block,
                 struct writeback_control *wbc);
-int __mpage_writepages(struct address_space *mapping,
-                struct writeback_control *wbc, get_block_t get_block,
-                writepage_t writepage);
 
 static inline int
 generic_writepages(struct address_space *mapping, struct writeback_control *wbc)
diff --git a/include/linux/net.h b/include/linux/net.h
index e5914c1f0c4d..20cb226b2268 100644
--- a/include/linux/net.h
+++ b/include/linux/net.h
@@ -7,7 +7,7 @@
  * Version:     @(#)net.h       1.0.3   05/25/93
  *
  * Authors:     Orest Zborowski, <obz@Kodak.COM>
- *              Ross Biro, <bir7@leland.Stanford.Edu>
+ *              Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              This program is free software; you can redistribute it and/or
@@ -101,7 +101,6 @@ enum sock_type {
  *  @sk: internal networking protocol agnostic socket representation
  *  @wait: wait queue for several uses
  *  @type: socket type (%SOCK_STREAM, etc)
- *  @passcred: credentials (used only in Unix Sockets (aka PF_LOCAL))
  */
 struct socket {
         socket_state            state;
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 8d775be67833..ba5d1236aa17 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)dev.h       1.0.10  08/12/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Corey Minyard <wf-rch!minyard@relay.EU.net>
  *              Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
@@ -204,7 +204,7 @@ struct hh_cache
         /* cached hardware header; allow for machine alignment needs.        */
 #define HH_DATA_MOD     16
 #define HH_DATA_OFF(__len) \
-        (HH_DATA_MOD - ((__len) & (HH_DATA_MOD - 1)))
+        (HH_DATA_MOD - (((__len - 1) & (HH_DATA_MOD - 1)) + 1))
 #define HH_DATA_ALIGN(__len) \
         (((__len)+(HH_DATA_MOD-1))&~(HH_DATA_MOD - 1))
         unsigned long   hh_data[HH_DATA_ALIGN(LL_MAX_HEADER) / sizeof(long)];
@@ -401,7 +401,7 @@ struct net_device
         } reg_state;
 
         /* Net device features */
-        int                     features;
+        unsigned long           features;
 #define NETIF_F_SG              1       /* Scatter/gather IO. */
 #define NETIF_F_IP_CSUM         2       /* Can checksum only TCP/UDP over IPv4. */
 #define NETIF_F_NO_CSUM         4       /* Does not require checksum. F.e. loopack. */
@@ -503,7 +503,7 @@ static inline void *netdev_priv(struct net_device *dev)
 #define SET_NETDEV_DEV(net, pdev)       ((net)->class_dev.dev = (pdev))
 
 struct packet_type {
-        unsigned short          type;   /* This is really htons(ether_type).    */
+        __be16                  type;   /* This is really htons(ether_type).    */
         struct net_device               *dev;   /* NULL is wildcarded here              */
         int                     (*func) (struct sk_buff *, struct net_device *,
                                          struct packet_type *);
@@ -913,6 +913,7 @@ extern void		dev_mc_discard(struct net_device *dev);
 extern void             dev_set_promiscuity(struct net_device *dev, int inc);
 extern void             dev_set_allmulti(struct net_device *dev, int inc);
 extern void             netdev_state_change(struct net_device *dev);
+extern void             netdev_features_change(struct net_device *dev);
 /* Load a device via the kmod */
 extern void             dev_load(const char *name);
 extern void             dev_mcast_init(void);
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index f731abdc1a29..b2738ac8bc99 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -110,6 +110,7 @@ struct netlink_skb_parms
         __u32                   dst_pid;
         __u32                   dst_groups;
         kernel_cap_t            eff_cap;
+        __u32                   loginuid;       /* Login (audit) uid */
 };
 
 #define NETLINK_CB(skb)         (*(struct netlink_skb_parms*)&((skb)->cb))
diff --git a/include/linux/notifier.h b/include/linux/notifier.h
index 9303a003e9ab..5937dd6053c3 100644
--- a/include/linux/notifier.h
+++ b/include/linux/notifier.h
@@ -56,6 +56,7 @@ extern int notifier_call_chain(struct notifier_block **n, unsigned long val, voi
 #define NETDEV_CHANGEADDR       0x0008
 #define NETDEV_GOING_DOWN       0x0009
 #define NETDEV_CHANGENAME       0x000A
+#define NETDEV_FEAT_CHANGE      0x000B
 
 #define SYS_DOWN        0x0001  /* Notify of system down */
 #define SYS_RESTART     SYS_DOWN
diff --git a/include/linux/patchkey.h b/include/linux/patchkey.h
new file mode 100644
index 000000000000..d974a6e92372
--- /dev/null
+++ b/include/linux/patchkey.h
@@ -0,0 +1,45 @@
+/*
+ * <linux/patchkey.h> -- definition of _PATCHKEY macro
+ *
+ * Copyright (C) 2005 Stuart Brady
+ *
+ * This exists because awe_voice.h defined its own _PATCHKEY and it wasn't
+ * clear whether removing this would break anything in userspace.
+ *
+ * Do not include this file directly.  Please use <sys/soundcard.h> instead.
+ * For kernel code, use <linux/soundcard.h>
+ */
+
+#ifndef _LINUX_PATCHKEY_H_INDIRECT
+#error "patchkey.h included directly"
+#endif
+
+#ifndef _LINUX_PATCHKEY_H
+#define _LINUX_PATCHKEY_H
+
+/* Endian macros. */
+#ifdef __KERNEL__
+#  include <asm/byteorder.h>
+#else
+#  include <endian.h>
+#endif
+
+#if defined(__KERNEL__)
+#  if defined(__BIG_ENDIAN)
+#    define _PATCHKEY(id) (0xfd00|id)
+#  elif defined(__LITTLE_ENDIAN)
+#    define _PATCHKEY(id) ((id<<8)|0x00fd)
+#  else
+#    error "could not determine byte order"
+#  endif
+#elif defined(__BYTE_ORDER)
+#  if __BYTE_ORDER == __BIG_ENDIAN
+#    define _PATCHKEY(id) (0xfd00|id)
+#  elif __BYTE_ORDER == __LITTLE_ENDIAN
+#    define _PATCHKEY(id) ((id<<8)|0x00fd)
+#  else
+#    error "could not determine byte order"
+#  endif
+#endif
+
+#endif /* _LINUX_PATCHKEY_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3c89148ae28a..b5238bd18830 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -671,6 +671,7 @@ struct pci_driver {
         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
         int  (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable);   /* Enable wake event */
+        void (*shutdown) (struct pci_dev *dev);
 
         struct device_driver    driver;
         struct pci_dynids dynids;
@@ -810,7 +811,6 @@ void pci_set_master(struct pci_dev *dev);
 int pci_set_mwi(struct pci_dev *dev);
 void pci_clear_mwi(struct pci_dev *dev);
 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
-int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_assign_resource(struct pci_dev *dev, int i);
 
@@ -941,7 +941,6 @@ static inline void pci_set_master(struct pci_dev *dev) { }
 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
 static inline void pci_disable_device(struct pci_dev *dev) { }
 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
-static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
 static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
 static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
 static inline void pci_unregister_driver(struct pci_driver *drv) { }
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 5d5820a4cf10..b8b4ebf9abf1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -854,6 +854,7 @@
 #define PCI_DEVICE_ID_MYLEX_DAC960_LA   0x0020
 #define PCI_DEVICE_ID_MYLEX_DAC960_LP   0x0050
 #define PCI_DEVICE_ID_MYLEX_DAC960_BA   0xBA56
+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM  0xB166
 
 #define PCI_VENDOR_ID_PICOP             0x1066
 #define PCI_DEVICE_ID_PICOP_PT86C52X    0x0001
@@ -873,6 +874,7 @@
 #define PCI_DEVICE_ID_APPLE_KL_USB_P    0x0026
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e
 #define PCI_DEVICE_ID_APPLE_UNI_N_FW2   0x0030
 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
 #define PCI_DEVIEC_ID_APPLE_UNI_N_ATA   0x0033
@@ -1229,6 +1231,12 @@
 #define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL     0x0258
 #define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL     0x0259
 #define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL     0x025B
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE   0x0265
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA  0x0266
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267
+#define PCI_DEVICE_ID_NVIDIA_NVENET_12          0x0268
+#define PCI_DEVICE_ID_NVIDIA_NVENET_13          0x0269
+#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO        0x026B
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800   0x0280
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
@@ -2063,12 +2071,14 @@
 
 #define PCI_VENDOR_ID_BROADCOM          0x14e4
 #define PCI_DEVICE_ID_TIGON3_5752       0x1600
+#define PCI_DEVICE_ID_TIGON3_5752M      0x1601
 #define PCI_DEVICE_ID_TIGON3_5700       0x1644
 #define PCI_DEVICE_ID_TIGON3_5701       0x1645
 #define PCI_DEVICE_ID_TIGON3_5702       0x1646
 #define PCI_DEVICE_ID_TIGON3_5703       0x1647
 #define PCI_DEVICE_ID_TIGON3_5704       0x1648
 #define PCI_DEVICE_ID_TIGON3_5704S_2    0x1649
+#define PCI_DEVICE_ID_NX2_5706          0x164a
 #define PCI_DEVICE_ID_TIGON3_5702FE     0x164d
 #define PCI_DEVICE_ID_TIGON3_5705       0x1653
 #define PCI_DEVICE_ID_TIGON3_5705_2     0x1654
@@ -2088,6 +2098,7 @@
 #define PCI_DEVICE_ID_TIGON3_5702X      0x16a6
 #define PCI_DEVICE_ID_TIGON3_5703X      0x16a7
 #define PCI_DEVICE_ID_TIGON3_5704S      0x16a8
+#define PCI_DEVICE_ID_NX2_5706S         0x16aa
 #define PCI_DEVICE_ID_TIGON3_5702A3     0x16c6
 #define PCI_DEVICE_ID_TIGON3_5703A3     0x16c7
 #define PCI_DEVICE_ID_TIGON3_5781       0x16dd
@@ -2372,6 +2383,8 @@
 #define PCI_DEVICE_ID_INTEL_82915G_IG   0x2582
 #define PCI_DEVICE_ID_INTEL_82915GM_HB  0x2590
 #define PCI_DEVICE_ID_INTEL_82915GM_IG  0x2592
+#define PCI_DEVICE_ID_INTEL_82945G_HB   0x2770
+#define PCI_DEVICE_ID_INTEL_82945G_IG   0x2772
 #define PCI_DEVICE_ID_INTEL_ICH6_0      0x2640
 #define PCI_DEVICE_ID_INTEL_ICH6_1      0x2641
 #define PCI_DEVICE_ID_INTEL_ICH6_2      0x2642
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index 73d84c071cb1..1d9da36eb9db 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -427,6 +427,7 @@ enum
         TCA_NETEM_UNSPEC,
         TCA_NETEM_CORR,
         TCA_NETEM_DELAY_DIST,
+        TCA_NETEM_REORDER,
         __TCA_NETEM_MAX,
 };
 
@@ -437,7 +438,7 @@ struct tc_netem_qopt
         __u32   latency;        /* added delay (us) */
         __u32   limit;          /* fifo limit (packets) */
         __u32   loss;           /* random packet loss (0=none ~0=100%) */
-        __u32   gap;            /* re-ordering gap (0 for delay all) */
+        __u32   gap;            /* re-ordering gap (0 for none) */
         __u32   duplicate;      /* random packet dup  (0=none ~0=100%) */
         __u32   jitter;         /* random jitter in latency (us) */
 };
@@ -449,6 +450,12 @@ struct tc_netem_corr
         __u32   dup_corr;       /* duplicate correlation  */
 };
 
+struct tc_netem_reorder
+{
+        __u32   probability;
+        __u32   correlation;
+};
+
 #define NETEM_DIST_SCALE        8192
 
 #endif
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 5f868a588581..4dbb109022f3 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -578,7 +578,7 @@ struct task_struct {
         unsigned long flags;    /* per process flags, defined below */
         unsigned long ptrace;
 
-        int lock_depth;         /* Lock depth */
+        int lock_depth;         /* BKL lock depth */
 
         int prio, static_prio;
         struct list_head run_list;
@@ -661,7 +661,10 @@ struct task_struct {
         struct key *thread_keyring;     /* keyring private to this thread */
 #endif
         int oomkilladj; /* OOM kill score adjustment (bit shift). */
-        char comm[TASK_COMM_LEN];
+        char comm[TASK_COMM_LEN]; /* executable name excluding path
+                                     - access with [gs]et_task_comm (which lock
+                                       it with task_lock())
+                                     - initialized normally by flush_old_exec */
 /* file system info */
         int link_count, total_link_count;
 /* ipc stuff */
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index c3fb5984f250..d6025af7efac 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -479,6 +479,25 @@ uart_handle_cts_change(struct uart_port *port, unsigned int status)
         }
 }
 
+#include <linux/tty_flip.h>
+
+static inline void
+uart_insert_char(struct uart_port *port, unsigned int status,
+                 unsigned int overrun, unsigned int ch, unsigned int flag)
+{
+        struct tty_struct *tty = port->info->tty;
+
+        if ((status & port->ignore_status_mask & ~overrun) == 0)
+                tty_insert_flip_char(tty, ch, flag);
+
+        /*
+         * Overrun is special.  Since it's reported immediately,
+         * it doesn't affect the current character.
+         */
+        if (status & ~port->ignore_status_mask & overrun)
+                tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+}
+
 /*
  *      UART_ENABLE_MS - determine if port should enable modem status irqs
  */
diff --git a/include/linux/signal.h b/include/linux/signal.h
index 0a98f5ec5cae..7be18b5e2fb4 100644
--- a/include/linux/signal.h
+++ b/include/linux/signal.h
@@ -231,10 +231,8 @@ extern int __group_send_sig_info(int, struct siginfo *, struct task_struct *);
 extern long do_sigpending(void __user *, unsigned long);
 extern int sigprocmask(int, sigset_t *, sigset_t *);
 
-#ifndef HAVE_ARCH_GET_SIGNAL_TO_DELIVER
 struct pt_regs;
 extern int get_signal_to_deliver(siginfo_t *info, struct k_sigaction *return_ka, struct pt_regs *regs, void *cookie);
-#endif
 
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/sockios.h b/include/linux/sockios.h
index 5eb33205cc04..e6b9d1d36ea2 100644
--- a/include/linux/sockios.h
+++ b/include/linux/sockios.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)sockios.h   1.0.2   03/09/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              This program is free software; you can redistribute it and/or
diff --git a/include/linux/soundcard.h b/include/linux/soundcard.h
index 28d2d1881978..523d069c862c 100644
--- a/include/linux/soundcard.h
+++ b/include/linux/soundcard.h
@@ -39,6 +39,13 @@
 /* In Linux we need to be prepared for cross compiling */
 #include <linux/ioctl.h>
 
+/* Endian macros. */
+#ifdef __KERNEL__
+#  include <asm/byteorder.h>
+#else
+#  include <endian.h>
+#endif
+
 /*
  *      Supported card ID numbers (Should be somewhere else?)
  */
@@ -179,13 +186,26 @@ typedef struct seq_event_rec {
  * Some big endian/little endian handling macros
  */
 
-#if defined(_AIX) || defined(AIX) || defined(sparc) || defined(__sparc__) || defined(HPPA) || defined(PPC) || defined(__mc68000__)
-/* Big endian machines */
-#  define _PATCHKEY(id) (0xfd00|id)
-#  define AFMT_S16_NE AFMT_S16_BE
-#else
-#  define _PATCHKEY(id) ((id<<8)|0xfd)
-#  define AFMT_S16_NE AFMT_S16_LE
+#define _LINUX_PATCHKEY_H_INDIRECT
+#include <linux/patchkey.h>
+#undef _LINUX_PATCHKEY_H_INDIRECT
+
+#if defined(__KERNEL__)
+#  if defined(__BIG_ENDIAN)
+#    define AFMT_S16_NE AFMT_S16_BE
+#  elif defined(__LITTLE_ENDIAN)
+#    define AFMT_S16_NE AFMT_S16_LE
+#  else
+#    error "could not determine byte order"
+#  endif
+#elif defined(__BYTE_ORDER)
+#  if __BYTE_ORDER == __BIG_ENDIAN
+#    define AFMT_S16_NE AFMT_S16_BE
+#  elif __BYTE_ORDER == __LITTLE_ENDIAN
+#    define AFMT_S16_NE AFMT_S16_LE
+#  else
+#    error "could not determine byte order"
+#  endif
 #endif
 
 /*
diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h
index e895f3eaf53a..d6ba068719b6 100644
--- a/include/linux/spinlock.h
+++ b/include/linux/spinlock.h
@@ -248,7 +248,7 @@ typedef struct {
 
 #define _spin_trylock_bh(lock)  ({preempt_disable(); local_bh_disable(); \
                                 _raw_spin_trylock(lock) ? \
-                                1 : ({preempt_enable(); local_bh_enable(); 0;});})
+                                1 : ({preempt_enable_no_resched(); local_bh_enable(); 0;});})
 
 #define _spin_lock(lock)        \
 do { \
@@ -383,7 +383,7 @@ do { \
 #define _spin_unlock_bh(lock) \
 do { \
         _raw_spin_unlock(lock); \
-        preempt_enable(); \
+        preempt_enable_no_resched(); \
         local_bh_enable(); \
         __release(lock); \
 } while (0)
@@ -391,7 +391,7 @@ do { \
 #define _write_unlock_bh(lock) \
 do { \
         _raw_write_unlock(lock); \
-        preempt_enable(); \
+        preempt_enable_no_resched(); \
         local_bh_enable(); \
         __release(lock); \
 } while (0)
@@ -423,8 +423,8 @@ do { \
 #define _read_unlock_bh(lock)   \
 do { \
         _raw_read_unlock(lock); \
+        preempt_enable_no_resched();    \
         local_bh_enable();      \
-        preempt_enable();       \
         __release(lock); \
 } while (0)
 
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 772998147e3e..a17745c80a91 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -346,6 +346,7 @@ enum
         NET_TCP_MODERATE_RCVBUF=106,
         NET_TCP_TSO_WIN_DIVISOR=107,
         NET_TCP_BIC_BETA=108,
+        NET_IPV4_ICMP_ERRORS_USE_INBOUND_IFADDR=109,
 };
 
 enum {
@@ -399,6 +400,7 @@ enum
         NET_IPV4_CONF_FORCE_IGMP_VERSION=17,
         NET_IPV4_CONF_ARP_ANNOUNCE=18,
         NET_IPV4_CONF_ARP_IGNORE=19,
+        NET_IPV4_CONF_PROMOTE_SECONDARIES=20,
         __NET_IPV4_CONF_MAX
 };
 
diff --git a/include/linux/tc_ematch/tc_em_meta.h b/include/linux/tc_ematch/tc_em_meta.h
index aa6b48bb4dcd..a6b2cc530af5 100644
--- a/include/linux/tc_ematch/tc_em_meta.h
+++ b/include/linux/tc_ematch/tc_em_meta.h
@@ -56,6 +56,36 @@ enum
         TCF_META_ID_TCCLASSID,
         TCF_META_ID_RTCLASSID,
         TCF_META_ID_RTIIF,
+        TCF_META_ID_SK_FAMILY,
+        TCF_META_ID_SK_STATE,
+        TCF_META_ID_SK_REUSE,
+        TCF_META_ID_SK_BOUND_IF,
+        TCF_META_ID_SK_REFCNT,
+        TCF_META_ID_SK_SHUTDOWN,
+        TCF_META_ID_SK_PROTO,
+        TCF_META_ID_SK_TYPE,
+        TCF_META_ID_SK_RCVBUF,
+        TCF_META_ID_SK_RMEM_ALLOC,
+        TCF_META_ID_SK_WMEM_ALLOC,
+        TCF_META_ID_SK_OMEM_ALLOC,
+        TCF_META_ID_SK_WMEM_QUEUED,
+        TCF_META_ID_SK_RCV_QLEN,
+        TCF_META_ID_SK_SND_QLEN,
+        TCF_META_ID_SK_ERR_QLEN,
+        TCF_META_ID_SK_FORWARD_ALLOCS,
+        TCF_META_ID_SK_SNDBUF,
+        TCF_META_ID_SK_ALLOCS,
+        TCF_META_ID_SK_ROUTE_CAPS,
+        TCF_META_ID_SK_HASHENT,
+        TCF_META_ID_SK_LINGERTIME,
+        TCF_META_ID_SK_ACK_BACKLOG,
+        TCF_META_ID_SK_MAX_ACK_BACKLOG,
+        TCF_META_ID_SK_PRIO,
+        TCF_META_ID_SK_RCVLOWAT,
+        TCF_META_ID_SK_RCVTIMEO,
+        TCF_META_ID_SK_SNDTIMEO,
+        TCF_META_ID_SK_SENDMSG_OFF,
+        TCF_META_ID_SK_WRITE_PENDING,
         __TCF_META_ID_MAX
 };
 #define TCF_META_ID_MAX (__TCF_META_ID_MAX - 1)
diff --git a/include/linux/trdevice.h b/include/linux/trdevice.h
index aaa1f337edcb..99e02ef54c47 100644
--- a/include/linux/trdevice.h
+++ b/include/linux/trdevice.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)eth.h       1.0.4   05/13/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              Relocated to include/linux where it belongs by Alan Cox 
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 41d1a644c9d4..2d1ac5058534 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -796,6 +796,10 @@ typedef void (*usb_complete_t)(struct urb *, struct pt_regs *);
  * of the iso_frame_desc array, and the number of errors is reported in
  * error_count.  Completion callbacks for ISO transfers will normally
  * (re)submit URBs to ensure a constant transfer rate.
+ *
+ * Note that even fields marked "public" should not be touched by the driver
+ * when the urb is owned by the hcd, that is, since the call to
+ * usb_submit_urb() till the entry into the completion routine.
  */
 struct urb
 {
@@ -803,12 +807,12 @@ struct urb
         struct kref kref;               /* reference count of the URB */
         spinlock_t lock;                /* lock for the URB */
         void *hcpriv;                   /* private data for host controller */
-        struct list_head urb_list;      /* list pointer to all active urbs */
         int bandwidth;                  /* bandwidth for INT/ISO request */
         atomic_t use_count;             /* concurrent submissions counter */
         u8 reject;                      /* submissions will fail */
 
         /* public, documented fields in the urb that can be used by drivers */
+        struct list_head urb_list;      /* list head for use by the urb owner */
         struct usb_device *dev;         /* (in) pointer to associated device */
         unsigned int pipe;              /* (in) pipe information */
         int status;                     /* (return) non-ISO status */
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 3a358c895188..6409d9cf5965 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -41,6 +41,7 @@ extern struct vm_struct *get_vm_area(unsigned long size, unsigned long flags);
 extern struct vm_struct *__get_vm_area(unsigned long size, unsigned long flags,
                                         unsigned long start, unsigned long end);
 extern struct vm_struct *remove_vm_area(void *addr);
+extern struct vm_struct *__remove_vm_area(void *addr);
 extern int map_vm_area(struct vm_struct *area, pgprot_t prot,
                         struct page ***pages);
 extern void unmap_vm_area(struct vm_struct *area);
diff --git a/include/linux/wait.h b/include/linux/wait.h
index 17c874a8eb3f..c9486c3efb4a 100644
--- a/include/linux/wait.h
+++ b/include/linux/wait.h
@@ -386,9 +386,7 @@ int wake_bit_function(wait_queue_t *wait, unsigned mode, int sync, void *key);
         wait_queue_t name = {                                           \
                 .task           = current,                              \
                 .func           = autoremove_wake_function,             \
-                .task_list      = {     .next = &(name).task_list,      \
-                                        .prev = &(name).task_list,      \
-                                },                                      \
+                .task_list      = LIST_HEAD_INIT((name).task_list),     \
         }
 
 #define DEFINE_WAIT_BIT(name, word, bit)                                \
diff --git a/include/media/video-buf-dvb.h b/include/media/video-buf-dvb.h
index 94bd33619aa5..ad0a07a3a895 100644
--- a/include/media/video-buf-dvb.h
+++ b/include/media/video-buf-dvb.h
@@ -16,7 +16,7 @@ struct videobuf_dvb {
         int                        nfeeds;
 
         /* videobuf_dvb_(un)register manges this */
-        struct dvb_adapter         *adapter;
+        struct dvb_adapter         adapter;
         struct dvb_demux           demux;
         struct dmxdev              dmxdev;
         struct dmx_frontend        fe_hw;
diff --git a/include/net/act_generic.h b/include/net/act_generic.h
index 95b120781c14..c9daa7e52300 100644
--- a/include/net/act_generic.h
+++ b/include/net/act_generic.h
@@ -2,8 +2,8 @@
  * include/net/act_generic.h
  *
 */
-#ifndef ACT_GENERIC_H
-#define ACT_GENERIC_H
+#ifndef _NET_ACT_GENERIC_H
+#define _NET_ACT_GENERIC_H
 static inline int tcf_defact_release(struct tcf_defact *p, int bind)
 {
         int ret = 0;
diff --git a/include/net/addrconf.h b/include/net/addrconf.h
index f1e5af4be98e..a0ed93672176 100644
--- a/include/net/addrconf.h
+++ b/include/net/addrconf.h
@@ -17,6 +17,8 @@
 
 #define IPV6_MAX_ADDRESSES              16
 
+#include <linux/in6.h>
+
 struct prefix_info {
         __u8                    type;
         __u8                    length;
@@ -43,7 +45,6 @@ struct prefix_info {
 
 #ifdef __KERNEL__
 
-#include <linux/in6.h>
 #include <linux/netdevice.h>
 #include <net/if_inet6.h>
 #include <net/ipv6.h>
diff --git a/include/net/icmp.h b/include/net/icmp.h
index 3fc192478aa2..e5ef0d15fb45 100644
--- a/include/net/icmp.h
+++ b/include/net/icmp.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)icmp.h      1.0.4   05/13/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              This program is free software; you can redistribute it and/or
diff --git a/include/net/ip.h b/include/net/ip.h
index b4db1375da2c..32360bbe143f 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)ip.h        1.0.2   05/07/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Alan Cox, <gw4pts@gw4pts.ampr.org>
  *
@@ -163,6 +163,7 @@ DECLARE_SNMP_STAT(struct linux_mib, net_statistics);
 
 extern int sysctl_local_port_range[2];
 extern int sysctl_ip_default_ttl;
+extern int sysctl_ip_nonlocal_bind;
 
 #ifdef CONFIG_INET
 /* The function in 2.2 was invalid, producing wrong result for
diff --git a/include/net/route.h b/include/net/route.h
index 22da7579d5de..d34ca8fc6756 100644
--- a/include/net/route.h
+++ b/include/net/route.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)route.h     1.0.4   05/27/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  * Fixes:
  *              Alan Cox        :       Reformatted. Added ip_rt_local()
@@ -181,9 +181,6 @@ static inline int ip_route_newports(struct rtable **rp, u16 sport, u16 dport,
                 memcpy(&fl, &(*rp)->fl, sizeof(fl));
                 fl.fl_ip_sport = sport;
                 fl.fl_ip_dport = dport;
-#if defined(CONFIG_IP_ROUTE_MULTIPATH_CACHED)
-                fl.flags |= FLOWI_FLAG_MULTIPATHOLDROUTE;
-#endif
                 ip_rt_put(*rp);
                 *rp = NULL;
                 return ip_route_output_flow(rp, &fl, sk, 0);
diff --git a/include/net/sock.h b/include/net/sock.h
index cc4c9190b7fd..a9ef3a6a13f3 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)sock.h      1.0.4   05/13/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Corey Minyard <wf-rch!minyard@relay.EU.net>
  *              Florian La Roche <flla@stud.uni-sb.de>
@@ -141,6 +141,7 @@ struct sock_common {
   *     @sk_callback_lock: used with the callbacks in the end of this struct
   *     @sk_error_queue: rarely used
   *     @sk_prot: protocol handlers inside a network family
+  *     @sk_prot_creator: sk_prot of original sock creator (see ipv6_setsockopt, IPV6_ADDRFORM for instance)
   *     @sk_err: last error
   *     @sk_err_soft: errors that don't cause failure but are the cause of a persistent failure not just 'timed out'
   *     @sk_ack_backlog: current listen backlog
@@ -218,6 +219,7 @@ struct sock {
         } sk_backlog;
         struct sk_buff_head     sk_error_queue;
         struct proto            *sk_prot;
+        struct proto            *sk_prot_creator;
         rwlock_t                sk_callback_lock;
         int                     sk_err,
                                 sk_err_soft;
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 9355ae5b1d75..e71f8ba3e101 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)tcp.h       1.0.5   05/23/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  *              This program is free software; you can redistribute it and/or
diff --git a/include/net/udp.h b/include/net/udp.h
index c496d10101db..ac229b761dbc 100644
--- a/include/net/udp.h
+++ b/include/net/udp.h
@@ -7,7 +7,7 @@
  *
  * Version:     @(#)udp.h       1.0.2   05/07/93
  *
- * Authors:     Ross Biro, <bir7@leland.Stanford.Edu>
+ * Authors:     Ross Biro
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *
  * Fixes:
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index e142a256d5dc..d675836ba6c3 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -515,6 +515,8 @@ struct xfrm_dst
         struct dst_entry *route;
         u32 route_mtu_cached;
         u32 child_mtu_cached;
+        u32 route_cookie;
+        u32 path_cookie;
 };
 
 static inline void xfrm_dst_destroy(struct xfrm_dst *xdst)
diff --git a/include/scsi/scsi_transport_spi.h b/include/scsi/scsi_transport_spi.h
index 6dcf497bf46d..a30d6cd4c0e8 100644
--- a/include/scsi/scsi_transport_spi.h
+++ b/include/scsi/scsi_transport_spi.h
@@ -27,8 +27,11 @@ struct scsi_transport_template;
 
 struct spi_transport_attrs {
         int period;             /* value in the PPR/SDTR command */
+        int min_period;
         int offset;
+        int max_offset;
         unsigned int width:1;   /* 0 - narrow, 1 - wide */
+        unsigned int max_width:1;
         unsigned int iu:1;      /* Information Units enabled */
         unsigned int dt:1;      /* DT clocking enabled */
         unsigned int qas:1;     /* Quick Arbitration and Selection enabled */
@@ -63,8 +66,11 @@ struct spi_host_attrs {
 
 /* accessor functions */
 #define spi_period(x)   (((struct spi_transport_attrs *)&(x)->starget_data)->period)
+#define spi_min_period(x) (((struct spi_transport_attrs *)&(x)->starget_data)->min_period)
 #define spi_offset(x)   (((struct spi_transport_attrs *)&(x)->starget_data)->offset)
+#define spi_max_offset(x) (((struct spi_transport_attrs *)&(x)->starget_data)->max_offset)
 #define spi_width(x)    (((struct spi_transport_attrs *)&(x)->starget_data)->width)
+#define spi_max_width(x) (((struct spi_transport_attrs *)&(x)->starget_data)->max_width)
 #define spi_iu(x)       (((struct spi_transport_attrs *)&(x)->starget_data)->iu)
 #define spi_dt(x)       (((struct spi_transport_attrs *)&(x)->starget_data)->dt)
 #define spi_qas(x)      (((struct spi_transport_attrs *)&(x)->starget_data)->qas)