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authorKyle McMartin <kyle@parisc-linux.org>2006-08-24 21:32:49 -0400
committerMatthew Wilcox <willy@parisc-linux.org>2006-10-04 08:49:56 -0400
commit1790cf9111f61d360d861901b97eba4de3b5414c (patch)
tree84a1f7e294a0ab24afd8b9d2010107efa1396e4d /include
parentb0eecc4da9c0a5261711e0d83280fd5d1e3db742 (diff)
[PARISC] Create shared <asm/ropes.h> header
Pull out struct sba_device and struct lba_device into a common ropes.h header. Also fold the parisc portion of iosapic.h into this file. (Then delete the useless portion of iosapic.h) Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-parisc/iosapic.h53
-rw-r--r--include/asm-parisc/ropes.h150
2 files changed, 150 insertions, 53 deletions
diff --git a/include/asm-parisc/iosapic.h b/include/asm-parisc/iosapic.h
deleted file mode 100644
index 613390e6805c..000000000000
--- a/include/asm-parisc/iosapic.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2** This file is private to iosapic driver.
3** If stuff needs to be used by another driver, move it to a common file.
4**
5** WARNING: fields most data structures here are ordered to make sure
6** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
7*/
8
9
10/*
11** I/O SAPIC init function
12** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
13** Call setup as part of per instance initialization.
14** (ie *not* init_module() function unless only one is present.)
15** fixup_irq is to initialize PCI IRQ line support and
16** virtualize pcidev->irq value. To be called by pci_fixup_bus().
17*/
18extern void *iosapic_register(unsigned long hpa);
19extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
20
21
22#ifdef __IA64__
23/*
24** PA: PIB (Processor Interrupt Block) is handled by Runway bus adapter.
25** and is hardcoded to 0xfeeNNNN0 where NNNN is id_eid field.
26**
27** IA64: PIB is handled by "Local SAPIC" (integrated in the processor).
28*/
29struct local_sapic_info {
30 struct local_sapic_info *lsi_next; /* point to next CPU info */
31 int *lsi_cpu_id; /* point to logical CPU id */
32 unsigned long *lsi_id_eid; /* point to IA-64 CPU id */
33 int *lsi_status; /* point to CPU status */
34 void *lsi_private; /* point to special info */
35};
36
37/*
38** "root" data structure which ties everything together.
39** Should always be able to start with sapic_root and locate
40** the desired information.
41*/
42struct sapic_info {
43 struct sapic_info *si_next; /* info is per cell */
44 int si_cellid; /* cell id */
45 unsigned int si_status; /* status */
46 char *si_pib_base; /* intr blk base address */
47 local_sapic_info_t *si_local_info;
48 io_sapic_info_t *si_io_info;
49 extint_info_t *si_extint_info;/* External Intr info */
50};
51
52#endif /* IA64 */
53
diff --git a/include/asm-parisc/ropes.h b/include/asm-parisc/ropes.h
new file mode 100644
index 000000000000..413dfcca15c7
--- /dev/null
+++ b/include/asm-parisc/ropes.h
@@ -0,0 +1,150 @@
1#ifndef _ASM_PARISC_ROPES_H_
2#define _ASM_PARISC_ROPES_H_
3
4#ifdef CONFIG_64BIT
5/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
6#define ZX1_SUPPORT
7#endif
8
9#ifdef CONFIG_PROC_FS
10/* depends on proc fs support. But costs CPU performance */
11#undef SBA_COLLECT_STATS
12#endif
13
14/*
15** The number of pdir entries to "free" before issueing
16** a read to PCOM register to flush out PCOM writes.
17** Interacts with allocation granularity (ie 4 or 8 entries
18** allocated and free'd/purged at a time might make this
19** less interesting).
20*/
21#define DELAYED_RESOURCE_CNT 16
22
23#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
24#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
25
26struct ioc {
27 void __iomem *ioc_hpa; /* I/O MMU base address */
28 char *res_map; /* resource map, bit == pdir entry */
29 u64 *pdir_base; /* physical base address */
30 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
31 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
32#ifdef ZX1_SUPPORT
33 unsigned long iovp_mask; /* help convert IOVA to IOVP */
34#endif
35 unsigned long *res_hint; /* next avail IOVP - circular search */
36 spinlock_t res_lock;
37 unsigned int res_bitshift; /* from the LEFT! */
38 unsigned int res_size; /* size of resource map in bytes */
39#ifdef SBA_HINT_SUPPORT
40/* FIXME : DMA HINTs not used */
41 unsigned long hint_mask_pdir; /* bits used for DMA hints */
42 unsigned int hint_shift_pdir;
43#endif
44#if DELAYED_RESOURCE_CNT > 0
45 int saved_cnt;
46 struct sba_dma_pair {
47 dma_addr_t iova;
48 size_t size;
49 } saved[DELAYED_RESOURCE_CNT];
50#endif
51
52#ifdef SBA_COLLECT_STATS
53#define SBA_SEARCH_SAMPLE 0x100
54 unsigned long avg_search[SBA_SEARCH_SAMPLE];
55 unsigned long avg_idx; /* current index into avg_search */
56 unsigned long used_pages;
57 unsigned long msingle_calls;
58 unsigned long msingle_pages;
59 unsigned long msg_calls;
60 unsigned long msg_pages;
61 unsigned long usingle_calls;
62 unsigned long usingle_pages;
63 unsigned long usg_calls;
64 unsigned long usg_pages;
65#endif
66 /* STUFF We don't need in performance path */
67 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
68};
69
70struct sba_device {
71 struct sba_device *next; /* list of SBA's in system */
72 struct parisc_device *dev; /* dev found in bus walk */
73 const char *name;
74 void __iomem *sba_hpa; /* base address */
75 spinlock_t sba_lock;
76 unsigned int flags; /* state/functionality enabled */
77 unsigned int hw_rev; /* HW revision of chip */
78
79 struct resource chip_resv; /* MMIO reserved for chip */
80 struct resource iommu_resv; /* MMIO reserved for iommu */
81
82 unsigned int num_ioc; /* number of on-board IOC's */
83 struct ioc ioc[MAX_IOC];
84};
85
86#define ASTRO_RUNWAY_PORT 0x582
87#define IKE_MERCED_PORT 0x803
88#define REO_MERCED_PORT 0x804
89#define REOG_MERCED_PORT 0x805
90#define PLUTO_MCKINLEY_PORT 0x880
91
92static inline int IS_ASTRO(struct parisc_device *d) {
93 return d->id.hversion == ASTRO_RUNWAY_PORT;
94}
95
96static inline int IS_IKE(struct parisc_device *d) {
97 return d->id.hversion == IKE_MERCED_PORT;
98}
99
100static inline int IS_PLUTO(struct parisc_device *d) {
101 return d->id.hversion == PLUTO_MCKINLEY_PORT;
102}
103
104#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
105
106/*
107** lba_device: Per instance Elroy data structure
108*/
109struct lba_device {
110 struct pci_hba_data hba;
111
112 spinlock_t lba_lock;
113 void *iosapic_obj;
114
115#ifdef CONFIG_64BIT
116 void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */
117#endif
118
119 int flags; /* state/functionality enabled */
120 int hw_rev; /* HW revision of chip */
121};
122
123#define ELROY_HVERS 0x782
124#define MERCURY_HVERS 0x783
125#define QUICKSILVER_HVERS 0x784
126
127static inline int IS_ELROY(struct parisc_device *d) {
128 return (d->id.hversion == ELROY_HVERS);
129}
130
131static inline int IS_MERCURY(struct parisc_device *d) {
132 return (d->id.hversion == MERCURY_HVERS);
133}
134
135static inline int IS_QUICKSILVER(struct parisc_device *d) {
136 return (d->id.hversion == QUICKSILVER_HVERS);
137}
138
139/*
140** I/O SAPIC init function
141** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
142** Call setup as part of per instance initialization.
143** (ie *not* init_module() function unless only one is present.)
144** fixup_irq is to initialize PCI IRQ line support and
145** virtualize pcidev->irq value. To be called by pci_fixup_bus().
146*/
147extern void *iosapic_register(unsigned long hpa);
148extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
149
150#endif /*_ASM_PARISC_ROPES_H_*/
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