diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:42:51 -0400 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:42:51 -0400 |
| commit | 138f4c359d23d2ec38d18bd70dd9613ae515fe93 (patch) | |
| tree | ad7fafba6eac74d9d92ade839a65171466d67a70 /include | |
| parent | 0403e3827788d878163f9ef0541b748b0f88ca5d (diff) | |
dmaengine, async_tx: add a "no channel switch" allocator
Channel switching is problematic for some dmaengine drivers as the
architecture precludes separating the ->prep from ->submit. In these
cases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify
the async_tx allocator to only return channels that support all of the
required asynchronous operations.
For example MD_RAID456=y selects support for asynchronous xor, xor
validate, pq, pq validate, and memcpy. When
ASYNC_TX_DISABLE_CHANNEL_SWITCH=y any channel with all these
capabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to
quickly locate compatible channels with the guarantee that dependency
chains will remain on one channel. When
ASYNC_TX_DISABLE_CHANNEL_SWITCH=n async_tx_find_channel() may select
channels that lead to operation chains that need to cross channel
boundaries using the async_tx channel switch capability.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/dmaengine.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 4d6c1c925fd4..86853ed7970b 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
| @@ -48,6 +48,9 @@ enum dma_status { | |||
| 48 | 48 | ||
| 49 | /** | 49 | /** |
| 50 | * enum dma_transaction_type - DMA transaction types/indexes | 50 | * enum dma_transaction_type - DMA transaction types/indexes |
| 51 | * | ||
| 52 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | ||
| 53 | * automatically set as dma devices are registered. | ||
| 51 | */ | 54 | */ |
| 52 | enum dma_transaction_type { | 55 | enum dma_transaction_type { |
| 53 | DMA_MEMCPY, | 56 | DMA_MEMCPY, |
| @@ -61,6 +64,7 @@ enum dma_transaction_type { | |||
| 61 | DMA_MEMCPY_CRC32C, | 64 | DMA_MEMCPY_CRC32C, |
| 62 | DMA_INTERRUPT, | 65 | DMA_INTERRUPT, |
| 63 | DMA_PRIVATE, | 66 | DMA_PRIVATE, |
| 67 | DMA_ASYNC_TX, | ||
| 64 | DMA_SLAVE, | 68 | DMA_SLAVE, |
| 65 | }; | 69 | }; |
| 66 | 70 | ||
| @@ -396,7 +400,11 @@ static inline void net_dmaengine_put(void) | |||
| 396 | #ifdef CONFIG_ASYNC_TX_DMA | 400 | #ifdef CONFIG_ASYNC_TX_DMA |
| 397 | #define async_dmaengine_get() dmaengine_get() | 401 | #define async_dmaengine_get() dmaengine_get() |
| 398 | #define async_dmaengine_put() dmaengine_put() | 402 | #define async_dmaengine_put() dmaengine_put() |
| 403 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH | ||
| 404 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) | ||
| 405 | #else | ||
| 399 | #define async_dma_find_channel(type) dma_find_channel(type) | 406 | #define async_dma_find_channel(type) dma_find_channel(type) |
| 407 | #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */ | ||
| 400 | #else | 408 | #else |
| 401 | static inline void async_dmaengine_get(void) | 409 | static inline void async_dmaengine_get(void) |
| 402 | { | 410 | { |
| @@ -409,7 +417,7 @@ async_dma_find_channel(enum dma_transaction_type type) | |||
| 409 | { | 417 | { |
| 410 | return NULL; | 418 | return NULL; |
| 411 | } | 419 | } |
| 412 | #endif | 420 | #endif /* CONFIG_ASYNC_TX_DMA */ |
| 413 | 421 | ||
| 414 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, | 422 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
| 415 | void *dest, void *src, size_t len); | 423 | void *dest, void *src, size_t len); |
