diff options
author | Michael Hennerich <michael.hennerich@analog.com> | 2008-04-24 16:58:29 -0400 |
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committer | Bryan Wu <cooloney@kernel.org> | 2008-04-24 16:58:29 -0400 |
commit | e6c91b64dd6e4c3adf39483c85a936eef9465e19 (patch) | |
tree | fb21af3166c55866dd587dd30c3807e9218054a9 /include | |
parent | fe44193c55e26b9b835722b5ee2519972f59c540 (diff) |
[Blackfin] arch: Functional power management support: Add support for cpu frequency scaling
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-blackfin/time.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h new file mode 100644 index 000000000000..6e5859b6ea32 --- /dev/null +++ b/include/asm-blackfin/time.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * asm-blackfin/time.h: | ||
3 | * | ||
4 | * Copyright 2004-2008 Analog Devices Inc. | ||
5 | * | ||
6 | * Licensed under the GPL-2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef _ASM_BLACKFIN_TIME_H | ||
10 | #define _ASM_BLACKFIN_TIME_H | ||
11 | |||
12 | /* | ||
13 | * The way that the Blackfin core timer works is: | ||
14 | * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) | ||
15 | * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) | ||
16 | * | ||
17 | * If you take the fastest clock (1ns, or 1GHz to make the math work easier) | ||
18 | * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter | ||
19 | * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need | ||
20 | * to use TSCALE, and program it to zero (which is pass CCLK through). | ||
21 | * If you feel like using it, try to keep HZ * TIMESCALE to some | ||
22 | * value that divides easy (like power of 2). | ||
23 | */ | ||
24 | |||
25 | #ifndef CONFIG_CPU_FREQ | ||
26 | #define TIME_SCALE 1 | ||
27 | #else | ||
28 | /* | ||
29 | * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . | ||
30 | * Whenever we change the Core Clock frequency changes we immediately | ||
31 | * adjust the Core Timer Presale Register. This way we don't lose time. | ||
32 | */ | ||
33 | #define TIME_SCALE 4 | ||
34 | #endif | ||
35 | |||
36 | #endif | ||