Merge remote branch 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next into drm-fixes

* 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next: (25 commits)
  nouveau: Acknowledge HPD irq in handler, not bottom half
  drm/nouveau: Fix a few confusions between "chipset" and "card_type".
  drm/nouveau: don't expose backlight control when available through ACPI
  drm/nouveau/pm: improve memtiming mappings
  drm/nouveau: Make PCIE GART size depend on the available RAMIN space.
  drm/nouveau: Return error from nouveau_gpuobj_new if we're out of RAMIN.
  drm/nouveau: Fix compilation issues in nouveau_pm when CONFIG_HWMON is not set
  drm/nouveau: Don't use load detection for connector polling.
  drm/nv10-nv20: Fix instability after MPLL changes.
  drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hang
  drm/nouveau: Don't poll LVDS outputs.
  drm/nouveau: Use "force" to decide if analog load detection is ok or not.
  drm/nv04: Fix scanout over the 16MB mark.
  drm/nouveau: fix nv40 pcie gart size
  drm/nva3: fix overflow in fixed point math used for pll calculation
  drm/nv10: Balance RTs expected to be accessed simultaneously by the 3d engine.
  drm/nouveau: Expose some BO usage flags to userspace.
  drm/nouveau: Reduce severity of the unknown getparam error.
  drm/nouveau: Avoid lock dependency between ramht and ramin spinlocks.
  drm/nouveau: Some random cleanups.
  ...

1 files changed, 7 insertions, 0 deletions

diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index 01a714119506..bc5590b1a1ac 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -80,6 +80,7 @@ struct drm_nouveau_gpuobj_free {
 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
 #define NOUVEAU_GETPARAM_GRAPH_UNITS     13
 #define NOUVEAU_GETPARAM_PTIMER_TIME     14
+#define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
 struct drm_nouveau_getparam {
         uint64_t param;
         uint64_t value;
@@ -95,6 +96,12 @@ struct drm_nouveau_setparam {
 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
 
+#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
+#define NOUVEAU_GEM_TILE_16BPP       0x00000001
+#define NOUVEAU_GEM_TILE_32BPP       0x00000002
+#define NOUVEAU_GEM_TILE_ZETA        0x00000004
+#define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
+
 struct drm_nouveau_gem_info {
         uint32_t handle;
         uint32_t domain;