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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-26 22:05:19 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-26 22:05:19 -0500
commit552d2f841e3f0f45eac86ff93e230db0b0a67a99 (patch)
treec47fabd409b3dd92965017dfc1c82df1d35579a0 /include
parent09cfd929860532f95c9944d39abbb043b8082f36 (diff)
parentb1e3afa001db8845eb60981f6ab925503ed94e53 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] vpe: Add missing "space" [MIPS] Compliment va_start() with va_end(). [MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writel [MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259 [MIPS] 64-bit Sibyte kernels need DMA32. [MIPS] Only build r4k clocksource for systems that work ok with it. [MIPS] Handle R4000/R4400 mfc0 from count register. [MIPS] Fix possible hang in LL/SC futex loops. [MIPS] Fix context DSP context / TLS pointer switching bug for new threads. [MIPS] IP32: More interrupt renumbering fixes. [MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe. [MIPS] time: Fix negated condition in cevt-r4k driver. [MIPS] Fix pcspeaker build.
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/8253pit.h10
-rw-r--r--include/asm-mips/dma.h1
-rw-r--r--include/asm-mips/futex.h6
-rw-r--r--include/asm-mips/i8253.h2
-rw-r--r--include/asm-mips/ip32/ip32_ints.h2
-rw-r--r--include/asm-mips/system.h8
-rw-r--r--include/asm-mips/time.h16
7 files changed, 27 insertions, 18 deletions
diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
deleted file mode 100644
index 285f78488ccb..000000000000
--- a/include/asm-mips/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * 8253/8254 Programmable Interval Timer
3 */
4
5#ifndef _8253PIT_H
6#define _8253PIT_H
7
8#define PIT_TICK_RATE 1193182UL
9
10#endif
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index 833437d31ef1..d6a6c21f16db 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -92,6 +92,7 @@
92#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) 92#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
93#endif 93#endif
94#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) 94#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
95#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
95 96
96/* 8237 DMA controllers */ 97/* 8237 DMA controllers */
97#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 98#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 3e7e30d4f418..17f082cfea85 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -35,7 +35,7 @@
35 " .set mips0 \n" \ 35 " .set mips0 \n" \
36 " .section .fixup,\"ax\" \n" \ 36 " .section .fixup,\"ax\" \n" \
37 "4: li %0, %6 \n" \ 37 "4: li %0, %6 \n" \
38 " j 2b \n" \ 38 " j 3b \n" \
39 " .previous \n" \ 39 " .previous \n" \
40 " .section __ex_table,\"a\" \n" \ 40 " .section __ex_table,\"a\" \n" \
41 " "__UA_ADDR "\t1b, 4b \n" \ 41 " "__UA_ADDR "\t1b, 4b \n" \
@@ -61,7 +61,7 @@
61 " .set mips0 \n" \ 61 " .set mips0 \n" \
62 " .section .fixup,\"ax\" \n" \ 62 " .section .fixup,\"ax\" \n" \
63 "4: li %0, %6 \n" \ 63 "4: li %0, %6 \n" \
64 " j 2b \n" \ 64 " j 3b \n" \
65 " .previous \n" \ 65 " .previous \n" \
66 " .section __ex_table,\"a\" \n" \ 66 " .section __ex_table,\"a\" \n" \
67 " "__UA_ADDR "\t1b, 4b \n" \ 67 " "__UA_ADDR "\t1b, 4b \n" \
@@ -200,4 +200,4 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
200} 200}
201 201
202#endif 202#endif
203#endif 203#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
index 032ca73f181b..5dabc870b322 100644
--- a/include/asm-mips/i8253.h
+++ b/include/asm-mips/i8253.h
@@ -12,6 +12,8 @@
12#define PIT_CH0 0x40 12#define PIT_CH0 0x40
13#define PIT_CH2 0x42 13#define PIT_CH2 0x42
14 14
15#define PIT_TICK_RATE 1193182UL
16
15extern spinlock_t i8253_lock; 17extern spinlock_t i8253_lock;
16 18
17extern void setup_pit_timer(void); 19extern void setup_pit_timer(void);
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index ab5612f90f6f..85bc5302bce0 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,7 +22,7 @@ enum ip32_irq_no {
22 * CPU interrupts are 0 ... 7 22 * CPU interrupts are 0 ... 7
23 */ 23 */
24 24
25 CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE, 25 CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
26 26
27 /* 27 /*
28 * MACE 28 * MACE
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 90e4b403f531..1030562d6ea6 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -68,11 +68,15 @@ do { \
68 if (cpu_has_dsp) \ 68 if (cpu_has_dsp) \
69 __save_dsp(prev); \ 69 __save_dsp(prev); \
70 (last) = resume(prev, next, task_thread_info(next)); \ 70 (last) = resume(prev, next, task_thread_info(next)); \
71} while (0)
72
73#define finish_arch_switch(prev) \
74do { \
71 if (cpu_has_dsp) \ 75 if (cpu_has_dsp) \
72 __restore_dsp(current); \ 76 __restore_dsp(current); \
73 if (cpu_has_userlocal) \ 77 if (cpu_has_userlocal) \
74 write_c0_userlocal(task_thread_info(current)->tp_value);\ 78 write_c0_userlocal(current_thread_info()->tp_value); \
75} while(0) 79} while (0)
76 80
77static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 81static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
78{ 82{
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index ee1663e64da1..7717934f94c3 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -58,10 +58,22 @@ extern int (*perf_irq)(void);
58 * Initialize the calling CPU's compare interrupt as clockevent device 58 * Initialize the calling CPU's compare interrupt as clockevent device
59 */ 59 */
60#ifdef CONFIG_CEVT_R4K 60#ifdef CONFIG_CEVT_R4K
61extern void mips_clockevent_init(void); 61extern int mips_clockevent_init(void);
62extern unsigned int __weak get_c0_compare_int(void); 62extern unsigned int __weak get_c0_compare_int(void);
63#else 63#else
64static inline void mips_clockevent_init(void) 64static inline int mips_clockevent_init(void)
65{
66 return -ENXIO;
67}
68#endif
69
70/*
71 * Initialize the count register as a clocksource
72 */
73#ifdef CONFIG_CEVT_R4K
74extern void init_mips_clocksource(void);
75#else
76static inline void init_mips_clocksource(void)
65{ 77{
66} 78}
67#endif 79#endif