Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

author: Tim Shimmin <tes@chook.melbourne.sgi.com> 2006-09-29 02:45:43 -0400
committer: Tim Shimmin <tes@chook.melbourne.sgi.com> 2006-09-29 02:45:43 -0400
commit: 1b06e7926694178e146ff708b2c15a6da64c9765 (patch)
tree: 30602fa4a854d6956f478212937726ca75ea13ce /include
parent: 65e8697a12e356cd7a6ecafa1149f5c5c6a71593 (diff)
parent: c972398b7871d9fb58c6a317786065a7cc6ca4be (diff)
112 files changed, 2844 insertions, 3040 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 58f40931a5c1..a5a86b1ff886 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -19,67 +19,80 @@
 /*
 * Peripheral identifiers/interrupts.
 */
-#define AT91_ID_FIQ     0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS     1       /* System Peripheral */
+#define AT91_ID_SYS             1       /* System Peripheral */
-#define AT91_ID_PIOA    2       /* Parallel IO Controller A */
+#define AT91RM9200_ID_PIOA      2       /* Parallel IO Controller A */
-#define AT91_ID_PIOB    3       /* Parallel IO Controller B */
+#define AT91RM9200_ID_PIOB      3       /* Parallel IO Controller B */
-#define AT91_ID_PIOC    4       /* Parallel IO Controller C */
+#define AT91RM9200_ID_PIOC      4       /* Parallel IO Controller C */
-#define AT91_ID_PIOD    5       /* Parallel IO Controller D */
+#define AT91RM9200_ID_PIOD      5       /* Parallel IO Controller D */
-#define AT91_ID_US0     6       /* USART 0 */
+#define AT91RM9200_ID_US0       6       /* USART 0 */
-#define AT91_ID_US1     7       /* USART 1 */
+#define AT91RM9200_ID_US1       7       /* USART 1 */
-#define AT91_ID_US2     8       /* USART 2 */
+#define AT91RM9200_ID_US2       8       /* USART 2 */
-#define AT91_ID_US3     9       /* USART 3 */
+#define AT91RM9200_ID_US3       9       /* USART 3 */
-#define AT91_ID_MCI     10      /* Multimedia Card Interface */
+#define AT91RM9200_ID_MCI       10      /* Multimedia Card Interface */
-#define AT91_ID_UDP     11      /* USB Device Port */
+#define AT91RM9200_ID_UDP       11      /* USB Device Port */
-#define AT91_ID_TWI     12      /* Two-Wire Interface */
+#define AT91RM9200_ID_TWI       12      /* Two-Wire Interface */
-#define AT91_ID_SPI     13      /* Serial Peripheral Interface */
+#define AT91RM9200_ID_SPI       13      /* Serial Peripheral Interface */
-#define AT91_ID_SSC0    14      /* Serial Synchronous Controller 0 */
+#define AT91RM9200_ID_SSC0      14      /* Serial Synchronous Controller 0 */
-#define AT91_ID_SSC1    15      /* Serial Synchronous Controller 1 */
+#define AT91RM9200_ID_SSC1      15      /* Serial Synchronous Controller 1 */
-#define AT91_ID_SSC2    16      /* Serial Synchronous Controller 2 */
+#define AT91RM9200_ID_SSC2      16      /* Serial Synchronous Controller 2 */
-#define AT91_ID_TC0     17      /* Timer Counter 0 */
+#define AT91RM9200_ID_TC0       17      /* Timer Counter 0 */
-#define AT91_ID_TC1     18      /* Timer Counter 1 */
+#define AT91RM9200_ID_TC1       18      /* Timer Counter 1 */
-#define AT91_ID_TC2     19      /* Timer Counter 2 */
+#define AT91RM9200_ID_TC2       19      /* Timer Counter 2 */
-#define AT91_ID_TC3     20      /* Timer Counter 3 */
+#define AT91RM9200_ID_TC3       20      /* Timer Counter 3 */
-#define AT91_ID_TC4     21      /* Timer Counter 4 */
+#define AT91RM9200_ID_TC4       21      /* Timer Counter 4 */
-#define AT91_ID_TC5     22      /* Timer Counter 5 */
+#define AT91RM9200_ID_TC5       22      /* Timer Counter 5 */
-#define AT91_ID_UHP     23      /* USB Host port */
+#define AT91RM9200_ID_UHP       23      /* USB Host port */
-#define AT91_ID_EMAC    24      /* Ethernet MAC */
+#define AT91RM9200_ID_EMAC      24      /* Ethernet MAC */
-#define AT91_ID_IRQ0    25      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91RM9200_ID_IRQ0      25      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91_ID_IRQ1    26      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91RM9200_ID_IRQ1      26      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91_ID_IRQ2    27      /* Advanced Interrupt Controller (IRQ2) */
+#define AT91RM9200_ID_IRQ2      27      /* Advanced Interrupt Controller (IRQ2) */
-#define AT91_ID_IRQ3    28      /* Advanced Interrupt Controller (IRQ3) */
+#define AT91RM9200_ID_IRQ3      28      /* Advanced Interrupt Controller (IRQ3) */
-#define AT91_ID_IRQ4    29      /* Advanced Interrupt Controller (IRQ4) */
+#define AT91RM9200_ID_IRQ4      29      /* Advanced Interrupt Controller (IRQ4) */
-#define AT91_ID_IRQ5    30      /* Advanced Interrupt Controller (IRQ5) */
+#define AT91RM9200_ID_IRQ5      30      /* Advanced Interrupt Controller (IRQ5) */
-#define AT91_ID_IRQ6    31      /* Advanced Interrupt Controller (IRQ6) */
+#define AT91RM9200_ID_IRQ6      31      /* Advanced Interrupt Controller (IRQ6) */
 /*
 * Peripheral physical base addresses.
 */
-#define AT91_BASE_TCB0          0xfffa0000
+#define AT91RM9200_BASE_TCB0    0xfffa0000
-#define AT91_BASE_TC0           0xfffa0000
+#define AT91RM9200_BASE_TC0     0xfffa0000
-#define AT91_BASE_TC1           0xfffa0040
+#define AT91RM9200_BASE_TC1     0xfffa0040
-#define AT91_BASE_TC2           0xfffa0080
+#define AT91RM9200_BASE_TC2     0xfffa0080
-#define AT91_BASE_TCB1          0xfffa4000
+#define AT91RM9200_BASE_TCB1    0xfffa4000
-#define AT91_BASE_TC3           0xfffa4000
+#define AT91RM9200_BASE_TC3     0xfffa4000
-#define AT91_BASE_TC4           0xfffa4040
+#define AT91RM9200_BASE_TC4     0xfffa4040
-#define AT91_BASE_TC5           0xfffa4080
+#define AT91RM9200_BASE_TC5     0xfffa4080
-#define AT91_BASE_UDP           0xfffb0000
+#define AT91RM9200_BASE_UDP     0xfffb0000
-#define AT91_BASE_MCI           0xfffb4000
+#define AT91RM9200_BASE_MCI     0xfffb4000
-#define AT91_BASE_TWI           0xfffb8000
+#define AT91RM9200_BASE_TWI     0xfffb8000
-#define AT91_BASE_EMAC          0xfffbc000
+#define AT91RM9200_BASE_EMAC    0xfffbc000
-#define AT91_BASE_US0           0xfffc0000
+#define AT91RM9200_BASE_US0     0xfffc0000
-#define AT91_BASE_US1           0xfffc4000
+#define AT91RM9200_BASE_US1     0xfffc4000
-#define AT91_BASE_US2           0xfffc8000
+#define AT91RM9200_BASE_US2     0xfffc8000
-#define AT91_BASE_US3           0xfffcc000
+#define AT91RM9200_BASE_US3     0xfffcc000
-#define AT91_BASE_SSC0          0xfffd0000
+#define AT91RM9200_BASE_SSC0    0xfffd0000
-#define AT91_BASE_SSC1          0xfffd4000
+#define AT91RM9200_BASE_SSC1    0xfffd4000
-#define AT91_BASE_SSC2          0xfffd8000
+#define AT91RM9200_BASE_SSC2    0xfffd8000
-#define AT91_BASE_SPI           0xfffe0000
+#define AT91RM9200_BASE_SPI     0xfffe0000
 #define AT91_BASE_SYS           0xfffff000
 /*
+ * Internal Memory.
+ */
+#define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
+#define AT91RM9200_ROM_SIZE     SZ_128K         /* Internal ROM size (128Kb) */
+#define AT91RM9200_SRAM_BASE    0x00200000      /* Internal SRAM base address */
+#define AT91RM9200_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
+#define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
+#if 0
+/*
 * PIO pin definitions (peripheral A/B multiplexing).
 */
 #define AT91_PA0_MISO           (1 <<  0)       /* A: SPI Master-In Slave-Out */
@@ -257,5 +270,6 @@
 #define AT91_PD25_TPK13         (1 << 25)       /* B: ETM Trace Packet Port 13 */
 #define AT91_PD26_TPK14         (1 << 26)       /* B: ETM Trace Packet Port 14 */
 #define AT91_PD27_TPK15         (1 << 27)       /* B: ETM Trace Packet Port 15 */
+#endif
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 0f4c12d5f0cd..73693fea76a2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -80,6 +80,9 @@
 #define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
 #define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
+#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
 /*
 * PIO Controllers.
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
new file mode 100644
index 000000000000..93547d7482bd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
@@ -0,0 +1,57 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Two-wire Interface (TWI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_TWI_H
+#define AT91RM9200_TWI_H
+#define AT91_TWI_CR             0x00            /* Control Register */
+#define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
+#define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
+#define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
+#define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
+#define AT91_TWI_MMR            0x04            /* Master Mode Register */
+#define         AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
+#define                 AT91_TWI_IADRSZ_NO              (0 << 8)
+#define                 AT91_TWI_IADRSZ_1               (1 << 8)
+#define                 AT91_TWI_IADRSZ_2               (2 << 8)
+#define                 AT91_TWI_IADRSZ_3               (3 << 8)
+#define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
+#define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
+#define AT91_TWI_IADR           0x0c            /* Internal Address Register */
+#define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
+#define         AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
+#define         AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
+#define         AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
+#define AT91_TWI_SR             0x20            /* Status Register */
+#define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
+#define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
+#define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error */
+#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error */
+#define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+#define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
+#define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
+#define AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
+#define AT91_TWI_RHR            0x30            /* Receive Holding Register */
+#define AT91_TWI_THR            0x34            /* Transmit Holding Register */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index dbde1baaf251..a011d27876a2 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -17,10 +17,9 @@
 #define PIN_BASE                NR_AIC_IRQS
-#define PQFP_GPIO_BANKS         3       /* PQFP package has 3 banks */
+#define MAX_GPIO_BANKS          4
-#define BGA_GPIO_BANKS          4       /* BGA package has 4 banks */
-/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 #define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
 #define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
@@ -180,17 +179,18 @@
 #ifndef __ASSEMBLY__
 /* setup setup routines, called from board init or driver probe() */
-extern int at91_set_A_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
-extern int at91_set_B_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
-extern int at91_set_gpio_input(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
-extern int at91_set_gpio_output(unsigned pin, int value);
+extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
-extern int at91_set_deglitch(unsigned pin, int is_on);
+extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
-extern int at91_set_multi_drive(unsigned pin, int is_on);
+extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
 extern int at91_get_gpio_value(unsigned pin);
+/* callable only from core power-management code */
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 235d39d91107..6551b4d1ff7b 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -34,27 +34,14 @@
 * Virtual to Physical Address mapping for IO devices.
 */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91_BASE_SPI)
+#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91RM9200_BASE_SPI)
-#define AT91_VA_BASE_SSC2       AT91_IO_P2V(AT91_BASE_SSC2)
+#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
-#define AT91_VA_BASE_SSC1       AT91_IO_P2V(AT91_BASE_SSC1)
+#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91RM9200_BASE_TWI)
-#define AT91_VA_BASE_SSC0       AT91_IO_P2V(AT91_BASE_SSC0)
+#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91RM9200_BASE_MCI)
-#define AT91_VA_BASE_US3        AT91_IO_P2V(AT91_BASE_US3)
+#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91RM9200_BASE_UDP)
-#define AT91_VA_BASE_US2        AT91_IO_P2V(AT91_BASE_US2)
-#define AT91_VA_BASE_US1        AT91_IO_P2V(AT91_BASE_US1)
-#define AT91_VA_BASE_US0        AT91_IO_P2V(AT91_BASE_US0)
-#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91_BASE_EMAC)
-#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91_BASE_TWI)
-#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91_BASE_MCI)
-#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91_BASE_UDP)
-#define AT91_VA_BASE_TCB1       AT91_IO_P2V(AT91_BASE_TCB1)
-#define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
-/* Internal SRAM */
-#define AT91_SRAM_BASE          0x00200000      /* Internal SRAM base address */
-#define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
 /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
+#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
 /* Serial ports */
 #define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
@@ -71,9 +58,6 @@
 /* Compact Flash */
 #define AT91_CF_BASE            0x50000000      /* NCS4-NCS6: Compact Flash physical base address */
-/* Multi-Master Memory controller */
-#define AT91_UHP_BASE           0x00300000      /* USB Host controller */
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index f63842c2c093..763cb96c418b 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -32,7 +32,7 @@
 /*
- * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
+ * IRQ interrupt symbols are the AT91xxx_ID_* symbols
 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
 * symbols in gpio.h for ones handled indirectly as GPIOs.
 * We make provision for 4 banks of GPIO.
diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S
new file mode 100644
index 000000000000..9022b6849e23
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-iop32x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+                .macro  addruart, rx
+                mov     \rx, #0xfe000000        @ physical as well as virtual
+                orr     \rx, \rx, #0x00800000   @ location of the UART
+                .endm
+#define UART_SHIFT      0
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop32x/dma.h
index 1e808db8af2a..e977a9ef3160 100644
--- a/include/asm-arm/arch-iop3xx/dma.h
+++ b/include/asm-arm/arch-iop32x/dma.h
@@ -1,7 +1,7 @@
 /*
- * linux/include/asm-arm/arch-iop3xx/dma.h
+ * include/asm-arm/arch-iop32x/dma.h
 *
- *  Copyright (C) 2004 Intel Corp.
+ * Copyright (C) 2004 Intel Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
new file mode 100644
index 000000000000..1500cbbd2295
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/entry-macro.S
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-iop32x/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IOP32x-based platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/arch/iop32x.h>
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IOP3XX_REG_ADDR(0x07D8)
+                ldr     \irqstat, [\base]               @ Read IINTSRC
+                cmp     \irqstat, #0
+                clzne   \irqnr, \irqstat
+                rsbne   \irqnr, \irqnr, #31
+                .endm
diff --git a/include/asm-arm/arch-iop32x/glantank.h b/include/asm-arm/arch-iop32x/glantank.h
new file mode 100644
index 000000000000..3b065618dd00
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/glantank.h
@@ -0,0 +1,13 @@
+/*
+ * include/asm/arch-iop32x/glantank.h
+ *
+ * IO-Data GLAN Tank board registers
+ */
+#ifndef __GLANTANK_H
+#define __GLANTANK_H
+#define GLANTANK_UART           0xfe800000      /* UART */
+#endif
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h
new file mode 100644
index 000000000000..6556ed5eee31
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/hardware.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-arm/arch-iop32x/hardware.h
+ */
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+#include <asm/types.h>
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000. The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses. See
+ * arch/arm/plat-iop/pci.c.
+ */
+#define pcibios_assign_all_busses() 1
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+#ifndef __ASSEMBLY__
+void iop32x_init_irq(void);
+#endif
+/*
+ * Generic chipset bits
+ */
+#include "iop32x.h"
+/*
+ * Board specific bits
+ */
+#include "glantank.h"
+#include "iq80321.h"
+#include "iq31244.h"
+#include "n2100.h"
+#endif
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop32x/io.h
index 36adbdf5055a..12d9ee02cde3 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop32x/io.h
@@ -1,21 +1,22 @@
 /*
- * linux/include/asm-arm/arch-iop3xx/io.h
+ * include/asm-arm/arch-iop32x/io.h
 *
- *  Copyright (C) 2001  MontaVista Software, Inc.
+ * Copyright (C) 2001 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARM_ARCH_IO_H
+#ifndef __IO_H
-#define __ASM_ARM_ARCH_IO_H
+#define __IO_H
 #include <asm/hardware.h>
-#define IO_SPACE_LIMIT 0xffffffff
+#define IO_SPACE_LIMIT          0xffffffff
 #define __io(p)                 ((void __iomem *)(p))
 #define __mem_pci(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h
new file mode 100644
index 000000000000..4bbd85f3ed2a
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/iop32x.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-arm/arch-iop32x/iop32x.h
+ *
+ * Intel IOP32X Chip definitions
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IOP32X_H
+#define __IOP32X_H
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
+#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
+#include <asm/hardware/iop3xx.h>
+#endif
diff --git a/include/asm-arm/arch-iop3xx/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h
index 4177cfa8100f..fff4eafa1f6b 100644
--- a/include/asm-arm/arch-iop3xx/iq31244.h
+++ b/include/asm-arm/arch-iop32x/iq31244.h
@@ -1,15 +1,11 @@
 /*
- * linux/include/asm/arch-iop3xx/iq31244.h
+ * include/asm-arm/arch-iop32x/iq31244.h
 *
 * Intel IQ31244 evaluation board registers
 */
-#ifndef _IQ31244_H_
+#ifndef __IQ31244_H
-#define _IQ31244_H_
+#define __IQ31244_H
-#define IQ31244_FLASHBASE       0xf0000000      /* Flash */
-#define IQ31244_FLASHSIZE       0x00800000
-#define IQ31244_FLASHWIDTH      2
 #define IQ31244_UART            0xfe800000      /* UART #1 */
 #define IQ31244_7SEG_1          0xfe840000      /* 7-Segment MSB */
@@ -17,8 +13,5 @@
 #define IQ31244_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
 #define IQ31244_BATT_STAT       0xfe8f0000      /* Battery Status */
-#ifndef __ASSEMBLY__
-extern void iq31244_map_io(void);
-#endif
-#endif  // _IQ31244_H_
+#endif
diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h
index cb8725979ffa..eb69db9b9a06 100644
--- a/include/asm-arm/arch-iop3xx/iq80321.h
+++ b/include/asm-arm/arch-iop32x/iq80321.h
@@ -1,15 +1,11 @@
 /*
- * linux/include/asm/arch-iop3xx/iq80321.h
+ * include/asm-arm/arch-iop32x/iq80321.h
 *
 * Intel IQ80321 evaluation board registers
 */
-#ifndef _IQ80321_H_
+#ifndef __IQ80321_H
-#define _IQ80321_H_
+#define __IQ80321_H
-#define IQ80321_FLASHBASE       0xf0000000      /* Flash */
-#define IQ80321_FLASHSIZE       0x00800000
-#define IQ80321_FLASHWIDTH      1
 #define IQ80321_UART            0xfe800000      /* UART #1 */
 #define IQ80321_7SEG_1          0xfe840000      /* 7-Segment MSB */
@@ -17,8 +13,5 @@
 #define IQ80321_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
 #define IQ80321_BATT_STAT       0xfe8f0000      /* Battery Status */
-#ifndef __ASSEMBLY__
-extern void iq80321_map_io(void);
-#endif
-#endif  // _IQ80321_H_
+#endif
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h
new file mode 100644
index 000000000000..bbaef873afce
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/irqs.h
@@ -0,0 +1,50 @@
+/*
+ * include/asm-arm/arch-iop32x/irqs.h
+ *
+ * Author:      Rory Bolt <rorybolt@pacbell.net>
+ * Copyright:   (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IRQS_H
+#define __IRQS_H
+/*
+ * IOP80321 chipset interrupts
+ */
+#define IRQ_IOP32X_DMA0_EOT     0
+#define IRQ_IOP32X_DMA0_EOC     1
+#define IRQ_IOP32X_DMA1_EOT     2
+#define IRQ_IOP32X_DMA1_EOC     3
+#define IRQ_IOP32X_AA_EOT       6
+#define IRQ_IOP32X_AA_EOC       7
+#define IRQ_IOP32X_CORE_PMON    8
+#define IRQ_IOP32X_TIMER0       9
+#define IRQ_IOP32X_TIMER1       10
+#define IRQ_IOP32X_I2C_0        11
+#define IRQ_IOP32X_I2C_1        12
+#define IRQ_IOP32X_MESSAGING    13
+#define IRQ_IOP32X_ATU_BIST     14
+#define IRQ_IOP32X_PERFMON      15
+#define IRQ_IOP32X_CORE_PMU     16
+#define IRQ_IOP32X_BIU_ERR      17
+#define IRQ_IOP32X_ATU_ERR      18
+#define IRQ_IOP32X_MCU_ERR      19
+#define IRQ_IOP32X_DMA0_ERR     20
+#define IRQ_IOP32X_DMA1_ERR     21
+#define IRQ_IOP32X_AA_ERR       23
+#define IRQ_IOP32X_MSG_ERR      24
+#define IRQ_IOP32X_SSP          25
+#define IRQ_IOP32X_XINT0        27
+#define IRQ_IOP32X_XINT1        28
+#define IRQ_IOP32X_XINT2        29
+#define IRQ_IOP32X_XINT3        30
+#define IRQ_IOP32X_HPI          31
+#define NR_IRQS                 32
+#endif
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
new file mode 100644
index 000000000000..764cd3f0d416
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-iop32x/memory.h
+ */
+#ifndef __MEMORY_H
+#define __MEMORY_H
+#include <asm/hardware.h>
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0xa0000000)
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
+#define __bus_to_virt(x)        (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
+#endif
diff --git a/include/asm-arm/arch-iop32x/n2100.h b/include/asm-arm/arch-iop32x/n2100.h
new file mode 100644
index 000000000000..fed31a648425
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/n2100.h
@@ -0,0 +1,19 @@
+/*
+ * include/asm/arch-iop32x/n2100.h
+ *
+ * Thecus N2100 board registers
+ */
+#ifndef __N2100_H
+#define __N2100_H
+#define N2100_UART              0xfe800000      /* UART */
+#define N2100_COPY_BUTTON       IOP3XX_GPIO_LINE(0)
+#define N2100_PCA9532_RESET     IOP3XX_GPIO_LINE(2)
+#define N2100_RESET_BUTTON      IOP3XX_GPIO_LINE(3)
+#define N2100_HARDWARE_RESET    IOP3XX_GPIO_LINE(4)
+#define N2100_POWER_BUTTON      IOP3XX_GPIO_LINE(5)
+#endif
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h
new file mode 100644
index 000000000000..17b7eb7e9c0d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/system.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-iop32x/system.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/mach-types.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        local_irq_disable();
+        if (machine_is_n2100()) {
+                gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
+                gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
+                while (1)
+                        ;
+        }
+        *IOP3XX_PCSR = 0x30;
+        /* Jump into ROM at address 0 */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h
new file mode 100644
index 000000000000..9934b087311b
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/timex.h
@@ -0,0 +1,9 @@
+/*
+ * include/asm-arm/arch-iop32x/timex.h
+ *
+ * IOP32x architecture timex specifications
+ */
+#include <asm/hardware.h>
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
new file mode 100644
index 000000000000..e64f52bf2bce
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-iop32x/uncompress.h
+ */
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+#include <asm/hardware.h>
+static volatile u8 *uart_base;
+#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
+static inline void putc(char c)
+{
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+        uart_base[UART_TX] = c;
+}
+static inline void flush(void)
+{
+}
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        if (machine_is_iq80321())
+                uart_base = (volatile u8 *)IQ80321_UART;
+        else if (machine_is_iq31244())
+                uart_base = (volatile u8 *)IQ31244_UART;
+        else
+                uart_base = (volatile u8 *)0xfe800000;
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h
new file mode 100644
index 000000000000..0a70baa19517
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-iop32x/vmalloc.h
+ */
+#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S
new file mode 100644
index 000000000000..9e7132ebe6a7
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/debug-macro.S
@@ -0,0 +1,24 @@
+/*
+ * include/asm-arm/arch-iop33x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+                .macro  addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ mmu enabled?
+                moveq   \rx, #0xff000000        @ physical
+                movne   \rx, #0xfe000000        @ virtual
+                orr     \rx, \rx, #0x00ff0000
+                orr     \rx, \rx, #0x0000f700
+                .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h
new file mode 100644
index 000000000000..b7775fdc5ad3
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/dma.h
@@ -0,0 +1,9 @@
+/*
+ * include/asm-arm/arch-iop33x/dma.h
+ *
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
new file mode 100644
index 000000000000..92b791702e34
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/entry-macro.S
@@ -0,0 +1,22 @@
+/*
+ * include/asm-arm/arch-iop33x/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IOP33x-based platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/arch/iop33x.h>
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IOP3XX_REG_ADDR(0x07C8)
+                ldr     \irqstat, [\base]               @ Read IINTVEC
+                cmp     \irqstat, #0
+                ldreq   \irqstat, [\base]               @ erratum 63 workaround
+                adds    \irqnr, \irqstat, #1
+                movne   \irqnr, \irqstat, lsr #2
+                .endm
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
new file mode 100644
index 000000000000..0659cf94d040
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/hardware.h
@@ -0,0 +1,46 @@
+/*
+ * include/asm-arm/arch-iop33x/hardware.h
+ */
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+#include <asm/types.h>
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000.  The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses.  See
+ * arch/arm/mach-iop3xx/iop3xx-pci.c
+ */
+#define pcibios_assign_all_busses()     1
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+#ifndef __ASSEMBLY__
+void iop33x_init_irq(void);
+extern struct platform_device iop33x_uart0_device;
+extern struct platform_device iop33x_uart1_device;
+#endif
+/*
+ * Generic chipset bits
+ *
+ */
+#include "iop33x.h"
+/*
+ * Board specific bits
+ */
+#include "iq80331.h"
+#include "iq80332.h"
+#endif
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h
new file mode 100644
index 000000000000..c017402bab96
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/io.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-iop33x/io.h
+ *
+ * Copyright (C) 2001  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IO_H
+#define __IO_H
+#include <asm/hardware.h>
+#define IO_SPACE_LIMIT          0xffffffff
+#define __io(p)                 ((void __iomem *)(p))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h
new file mode 100644
index 000000000000..7ac6e93db5ff
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/iop33x.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-iop33x/iop33x.h
+ *
+ * Intel IOP33X Chip definitions
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2003, 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IOP33X_H
+#define __IOP33X_H
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
+#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
+#include <asm/hardware/iop3xx.h>
+/* UARTs  */
+#define IOP33X_UART0_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
+#define IOP33X_UART0_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
+#define IOP33X_UART1_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
+#define IOP33X_UART1_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
+#endif
diff --git a/include/asm-arm/arch-iop3xx/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h
index 0668e78d483e..79b9302017ea 100644
--- a/include/asm-arm/arch-iop3xx/iq80331.h
+++ b/include/asm-arm/arch-iop33x/iq80331.h
@@ -1,23 +1,16 @@
 /*
- * linux/include/asm/arch-iop3xx/iq80331.h
+ * include/asm-arm/arch-iop33x/iq80331.h
 *
 * Intel IQ80331 evaluation board registers
 */
-#ifndef _IQ80331_H_
+#ifndef __IQ80331_H
-#define _IQ80331_H_
+#define __IQ80331_H
-#define IQ80331_FLASHBASE       0xc0000000      /* Flash */
-#define IQ80331_FLASHSIZE       0x00800000
-#define IQ80331_FLASHWIDTH      1
 #define IQ80331_7SEG_1          0xce840000      /* 7-Segment MSB */
 #define IQ80331_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
 #define IQ80331_ROTARY_SW       0xce8d0000      /* Rotary Switch */
 #define IQ80331_BATT_STAT       0xce8f0000      /* Battery Status */
-#ifndef __ASSEMBLY__
-extern void iq80331_map_io(void);
-#endif
-#endif  // _IQ80331_H_
+#endif
diff --git a/include/asm-arm/arch-iop3xx/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h
index e5fff1775d1a..053165629492 100644
--- a/include/asm-arm/arch-iop3xx/iq80332.h
+++ b/include/asm-arm/arch-iop33x/iq80332.h
@@ -1,23 +1,16 @@
 /*
- * linux/include/asm/arch-iop3xx/iq80332.h
+ * include/asm-arm/arch-iop33x/iq80332.h
 *
 * Intel IQ80332 evaluation board registers
 */
-#ifndef _IQ80332_H_
+#ifndef __IQ80332_H
-#define _IQ80332_H_
+#define __IQ80332_H
-#define IQ80332_FLASHBASE       0xc0000000      /* Flash */
-#define IQ80332_FLASHSIZE       0x00800000
-#define IQ80332_FLASHWIDTH      1
 #define IQ80332_7SEG_1          0xce840000      /* 7-Segment MSB */
 #define IQ80332_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
 #define IQ80332_ROTARY_SW       0xce8d0000      /* Rotary Switch */
 #define IQ80332_BATT_STAT       0xce8f0000      /* Battery Status */
-#ifndef __ASSEMBLY__
-extern void iq80332_map_io(void);
-#endif
-#endif  // _IQ80332_H_
+#endif
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h
new file mode 100644
index 000000000000..d045f8403396
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/irqs.h
@@ -0,0 +1,60 @@
+/*
+ * include/asm-arm/arch-iop33x/irqs.h
+ *
+ * Author:      Dave Jiang (dave.jiang@intel.com)
+ * Copyright:   (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IRQS_H
+#define __IRQS_H
+/*
+ * IOP80331 chipset interrupts
+ */
+#define IRQ_IOP33X_DMA0_EOT     0
+#define IRQ_IOP33X_DMA0_EOC     1
+#define IRQ_IOP33X_DMA1_EOT     2
+#define IRQ_IOP33X_DMA1_EOC     3
+#define IRQ_IOP33X_AA_EOT       6
+#define IRQ_IOP33X_AA_EOC       7
+#define IRQ_IOP33X_TIMER0       8
+#define IRQ_IOP33X_TIMER1       9
+#define IRQ_IOP33X_I2C_0        10
+#define IRQ_IOP33X_I2C_1        11
+#define IRQ_IOP33X_MSG          12
+#define IRQ_IOP33X_MSGIBQ       13
+#define IRQ_IOP33X_ATU_BIST     14
+#define IRQ_IOP33X_PERFMON      15
+#define IRQ_IOP33X_CORE_PMU     16
+#define IRQ_IOP33X_XINT0        24
+#define IRQ_IOP33X_XINT1        25
+#define IRQ_IOP33X_XINT2        26
+#define IRQ_IOP33X_XINT3        27
+#define IRQ_IOP33X_XINT8        32
+#define IRQ_IOP33X_XINT9        33
+#define IRQ_IOP33X_XINT10       34
+#define IRQ_IOP33X_XINT11       35
+#define IRQ_IOP33X_XINT12       36
+#define IRQ_IOP33X_XINT13       37
+#define IRQ_IOP33X_XINT14       38
+#define IRQ_IOP33X_XINT15       39
+#define IRQ_IOP33X_UART0        51
+#define IRQ_IOP33X_UART1        52
+#define IRQ_IOP33X_PBIE         53
+#define IRQ_IOP33X_ATU_CRW      54
+#define IRQ_IOP33X_ATU_ERR      55
+#define IRQ_IOP33X_MCU_ERR      56
+#define IRQ_IOP33X_DMA0_ERR     57
+#define IRQ_IOP33X_DMA1_ERR     58
+#define IRQ_IOP33X_AA_ERR       60
+#define IRQ_IOP33X_MSG_ERR      62
+#define IRQ_IOP33X_HPI          63
+#define NR_IRQS                 64
+#endif
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
new file mode 100644
index 000000000000..0d39139b241e
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-iop33x/memory.h
+ */
+#ifndef __MEMORY_H
+#define __MEMORY_H
+#include <asm/hardware.h>
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
+#define __bus_to_virt(x)        (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
+#endif
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h
new file mode 100644
index 000000000000..00dd07ece262
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/system.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-arm/arch-iop33x/system.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        *IOP3XX_PCSR = 0x30;
+        /* Jump into ROM at address 0 */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h
new file mode 100644
index 000000000000..fe3e1e369ff9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/timex.h
@@ -0,0 +1,9 @@
+/*
+ * include/asm-arm/arch-iop33x/timex.h
+ *
+ * IOP3xx architecture timex specifications
+ */
+#include <asm/hardware.h>
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h
new file mode 100644
index 000000000000..e17fbc05877b
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/uncompress.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-iop33x/uncompress.h
+ */
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+#include <asm/hardware.h>
+static volatile u32 *uart_base;
+#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
+static inline void putc(char c)
+{
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+        uart_base[UART_TX] = c;
+}
+static inline void flush(void)
+{
+}
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        if (machine_is_iq80331() || machine_is_iq80332())
+                uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
+        else
+                uart_base = (volatile u32 *)0xfe800000;
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h
new file mode 100644
index 000000000000..66f545a7f4fc
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-iop33x/vmalloc.h
+ */
+#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S
deleted file mode 100644
index ce007e531994..000000000000
--- a/include/asm-arm/arch-iop3xx/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/* linux/include/asm-arm/arch-iop3xx/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-                .macro  addruart,rx
-                mov     \rx, #0xfe000000        @ physical
-#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
-                orr     \rx, \rx, #0x00800000   @ location of the UART
-#elif defined(CONFIG_ARCH_IOP331)
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x000fe000        @ Physical Base
-                movne   \rx, #0
-                orr     \rx, \rx, #0xfe000000
-                orr     \rx, \rx, #0x00f00000   @ Virtual Base
-                orr     \rx, \rx, #0x00001700   @ location of the UART
-#else
-#error Unknown IOP3XX implementation
-#endif
-                .endm
-#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331)
-#define FLOW_CONTROL
-#endif
-#define UART_SHIFT      0
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S
deleted file mode 100644
index 926668c098a5..000000000000
--- a/include/asm-arm/arch-iop3xx/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-arm/arch-iop3xx/entry-macro.S
- *
- * Low-level IRQ helper macros for IOP3xx-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/irqs.h>
-#if defined(CONFIG_ARCH_IOP321)
-                .macro  disable_fiq
-                .endm
-                /*
-                 * Note: only deal with normal interrupts, not FIQ
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqnr, #0
-                mrc     p6, 0, \irqstat, c8, c0, 0      @ Read IINTSRC
-                cmp     \irqstat, #0
-                beq     1001f
-                clz     \irqnr, \irqstat
-                mov     \base, #31
-                subs    \irqnr,\base,\irqnr
-                add     \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
-1001:
-                .endm
-#elif defined(CONFIG_ARCH_IOP331)
-                .macro  disable_fiq
-                .endm
-                /*
-                 * Note: only deal with normal interrupts, not FIQ
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqnr, #0
-                mrc     p6, 0, \irqstat, c4, c0, 0      @ Read IINTSRC0
-                cmp     \irqstat, #0
-                bne     1002f
-                mrc     p6, 0, \irqstat, c5, c0, 0      @ Read IINTSRC1
-                cmp     \irqstat, #0
-                beq     1001f
-                clz     \irqnr, \irqstat
-                rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
-                add     \irqnr,\irqnr,#IRQ_IOP331_XINT8
-                b       1001f
-1002:   clz     \irqnr, \irqstat
-                rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
-                add     \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
-1001:
-                .endm
-#endif
diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h
deleted file mode 100644
index 3b138171d086..000000000000
--- a/include/asm-arm/arch-iop3xx/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/hardware.h
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/types.h>
-/*
- * Note about PCI IO space mappings
- *
- * To make IO space accesses efficient, we store virtual addresses in
- * the IO resources.
- *
- * The PCI IO space is located at virtual 0xfe000000 from physical
- * 0x90000000.  The PCI BARs must be programmed with physical addresses,
- * but when we read them, we convert them to virtual addresses.  See
- * arch/arm/mach-iop3xx/iop3xx-pci.c
- */
-#define pcibios_assign_all_busses() 1
-/*
- * The min PCI I/O and MEM space are dependent on what specific
- * chipset/platform we are running on, so instead of hardcoding with
- * #ifdefs, we just fill these in the platform level PCI init code.
- */
-#ifndef __ASSEMBLY__
-extern unsigned long iop3xx_pcibios_min_io;
-extern unsigned long iop3xx_pcibios_min_mem;
-extern unsigned int processor_id;
-#endif
-/*
- * We just set these to zero since they are really bogus anyways
- */
-#define PCIBIOS_MIN_IO      (iop3xx_pcibios_min_io)
-#define PCIBIOS_MIN_MEM     (iop3xx_pcibios_min_mem)
-/*
- * Generic chipset bits
- *
- */
-#include "iop321.h"
-#include "iop331.h"
-/*
- * Board specific bits
- */
-#include "iq80321.h"
-#include "iq31244.h"
-#include "iq80331.h"
-#include "iq80332.h"
-#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h
deleted file mode 100644
index 2fcc1654cb9d..000000000000
--- a/include/asm-arm/arch-iop3xx/iop321-irqs.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/irqs.h
- *
- * Author:      Rory Bolt <rorybolt@pacbell.net>
- * Copyright:   (C) 2002 Rory Bolt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#ifndef _IOP321_IRQS_H_
-#define _IOP321_IRQS_H_
-/*
- * IOP80321 chipset interrupts
- */
-#define IOP321_IRQ_OFS          0
-#define IOP321_IRQ(x)           (IOP321_IRQ_OFS + (x))
-/*
- * On IRQ or FIQ register
- */
-#define IRQ_IOP321_DMA0_EOT     IOP321_IRQ(0)
-#define IRQ_IOP321_DMA0_EOC     IOP321_IRQ(1)
-#define IRQ_IOP321_DMA1_EOT     IOP321_IRQ(2)
-#define IRQ_IOP321_DMA1_EOC     IOP321_IRQ(3)
-#define IRQ_IOP321_RSVD_4       IOP321_IRQ(4)
-#define IRQ_IOP321_RSVD_5       IOP321_IRQ(5)
-#define IRQ_IOP321_AA_EOT       IOP321_IRQ(6)
-#define IRQ_IOP321_AA_EOC       IOP321_IRQ(7)
-#define IRQ_IOP321_CORE_PMON    IOP321_IRQ(8)
-#define IRQ_IOP321_TIMER0       IOP321_IRQ(9)
-#define IRQ_IOP321_TIMER1       IOP321_IRQ(10)
-#define IRQ_IOP321_I2C_0        IOP321_IRQ(11)
-#define IRQ_IOP321_I2C_1        IOP321_IRQ(12)
-#define IRQ_IOP321_MESSAGING    IOP321_IRQ(13)
-#define IRQ_IOP321_ATU_BIST     IOP321_IRQ(14)
-#define IRQ_IOP321_PERFMON      IOP321_IRQ(15)
-#define IRQ_IOP321_CORE_PMU     IOP321_IRQ(16)
-#define IRQ_IOP321_BIU_ERR      IOP321_IRQ(17)
-#define IRQ_IOP321_ATU_ERR      IOP321_IRQ(18)
-#define IRQ_IOP321_MCU_ERR      IOP321_IRQ(19)
-#define IRQ_IOP321_DMA0_ERR     IOP321_IRQ(20)
-#define IRQ_IOP321_DMA1_ERR     IOP321_IRQ(21)
-#define IRQ_IOP321_RSVD_22      IOP321_IRQ(22)
-#define IRQ_IOP321_AA_ERR       IOP321_IRQ(23)
-#define IRQ_IOP321_MSG_ERR      IOP321_IRQ(24)
-#define IRQ_IOP321_SSP          IOP321_IRQ(25)
-#define IRQ_IOP321_RSVD_26      IOP321_IRQ(26)
-#define IRQ_IOP321_XINT0        IOP321_IRQ(27)
-#define IRQ_IOP321_XINT1        IOP321_IRQ(28)
-#define IRQ_IOP321_XINT2        IOP321_IRQ(29)
-#define IRQ_IOP321_XINT3        IOP321_IRQ(30)
-#define IRQ_IOP321_HPI          IOP321_IRQ(31)
-#define NR_IOP321_IRQS          (IOP321_IRQ(31) + 1)
-#define NR_IRQS                 NR_IOP321_IRQS
-/*
- * Interrupts available on the IQ80321 board
- */
-/*
- * On board devices
- */
-#define IRQ_IQ80321_I82544      IRQ_IOP321_XINT0
-#define IRQ_IQ80321_UART        IRQ_IOP321_XINT1
-/*
- * PCI interrupts
- */
-#define IRQ_IQ80321_INTA        IRQ_IOP321_XINT0
-#define IRQ_IQ80321_INTB        IRQ_IOP321_XINT1
-#define IRQ_IQ80321_INTC        IRQ_IOP321_XINT2
-#define IRQ_IQ80321_INTD        IRQ_IOP321_XINT3
-/*
- * Interrupts on the IQ31244 board
- */
-/*
- * On board devices
- */
-#define IRQ_IQ31244_UART        IRQ_IOP321_XINT1
-#define IRQ_IQ31244_I82546      IRQ_IOP321_XINT0
-#define IRQ_IQ31244_SATA        IRQ_IOP321_XINT2
-#define IRQ_IQ31244_PCIX_SLOT   IRQ_IOP321_XINT3
-/*
- * PCI interrupts
- */
-#define IRQ_IQ31244_INTA        IRQ_IOP321_XINT0
-#define IRQ_IQ31244_INTB        IRQ_IOP321_XINT1
-#define IRQ_IQ31244_INTC        IRQ_IOP321_XINT2
-#define IRQ_IQ31244_INTD        IRQ_IOP321_XINT3
-#endif // _IOP321_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
deleted file mode 100644
index f8df778a356f..000000000000
--- a/include/asm-arm/arch-iop3xx/iop321.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * linux/include/asm/arch-iop3xx/iop321.h
- *
- * Intel IOP321 Chip definitions
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _IOP321_HW_H_
-#define _IOP321_HW_H_
-/*
- * This is needed for mixed drivers that need to work on all
- * IOP3xx variants but behave slightly differently on each.
- */
-#ifndef __ASSEMBLY__
-#ifdef  CONFIG_ARCH_IOP321
-#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
-#else
-#define iop_is_321()    0
-#endif
-#endif
-/*
- * IOP321 I/O and Mem space regions for PCI autoconfiguration
- */
-#define IOP321_PCI_IO_WINDOW_SIZE   0x00010000
-#define IOP321_PCI_LOWER_IO_PA      0x90000000
-#define IOP321_PCI_LOWER_IO_VA      0xfe000000
-#define IOP321_PCI_LOWER_IO_BA      (*IOP321_OIOWTVR)
-#define IOP321_PCI_UPPER_IO_PA      (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
-#define IOP321_PCI_UPPER_IO_VA      (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
-#define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
-#define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
-/* #define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1) */
-#define IOP321_PCI_MEM_WINDOW_SIZE  0x04000000 /* 64M outbound window */
-#define IOP321_PCI_LOWER_MEM_PA     0x80000000
-#define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
-#define IOP321_PCI_UPPER_MEM_PA     (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
-#define IOP321_PCI_UPPER_MEM_BA     (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
-#define IOP321_PCI_MEM_OFFSET       (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
-/*
- * IOP321 chipset registers
- */
-#define IOP321_VIRT_MEM_BASE 0xfeffe000  /* chip virtual mem address*/
-#define IOP321_PHYS_MEM_BASE 0xffffe000  /* chip physical memory address */
-#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
-/* Reserved 0x00000000 through 0x000000FF */
-/* Address Translation Unit 0x00000100 through 0x000001FF */
-#define IOP321_ATUVID     (volatile u16 *)IOP321_REG_ADDR(0x00000100)
-#define IOP321_ATUDID     (volatile u16 *)IOP321_REG_ADDR(0x00000102)
-#define IOP321_ATUCMD     (volatile u16 *)IOP321_REG_ADDR(0x00000104)
-#define IOP321_ATUSR      (volatile u16 *)IOP321_REG_ADDR(0x00000106)
-#define IOP321_ATURID     (volatile u8  *)IOP321_REG_ADDR(0x00000108)
-#define IOP321_ATUCCR     (volatile u32 *)IOP321_REG_ADDR(0x00000109)
-#define IOP321_ATUCLSR    (volatile u8  *)IOP321_REG_ADDR(0x0000010C)
-#define IOP321_ATULT      (volatile u8  *)IOP321_REG_ADDR(0x0000010D)
-#define IOP321_ATUHTR     (volatile u8  *)IOP321_REG_ADDR(0x0000010E)
-#define IOP321_ATUBIST    (volatile u8  *)IOP321_REG_ADDR(0x0000010F)
-#define IOP321_IABAR0     (volatile u32 *)IOP321_REG_ADDR(0x00000110)
-#define IOP321_IAUBAR0    (volatile u32 *)IOP321_REG_ADDR(0x00000114)
-#define IOP321_IABAR1     (volatile u32 *)IOP321_REG_ADDR(0x00000118)
-#define IOP321_IAUBAR1    (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
-#define IOP321_IABAR2     (volatile u32 *)IOP321_REG_ADDR(0x00000120)
-#define IOP321_IAUBAR2    (volatile u32 *)IOP321_REG_ADDR(0x00000124)
-#define IOP321_ASVIR      (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
-#define IOP321_ASIR       (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
-#define IOP321_ERBAR      (volatile u32 *)IOP321_REG_ADDR(0x00000130)
-/* Reserved 0x00000134 through 0x0000013B */
-#define IOP321_ATUILR     (volatile u8  *)IOP321_REG_ADDR(0x0000013C)
-#define IOP321_ATUIPR     (volatile u8  *)IOP321_REG_ADDR(0x0000013D)
-#define IOP321_ATUMGNT    (volatile u8  *)IOP321_REG_ADDR(0x0000013E)
-#define IOP321_ATUMLAT    (volatile u8  *)IOP321_REG_ADDR(0x0000013F)
-#define IOP321_IALR0      (volatile u32 *)IOP321_REG_ADDR(0x00000140)
-#define IOP321_IATVR0     (volatile u32 *)IOP321_REG_ADDR(0x00000144)
-#define IOP321_ERLR       (volatile u32 *)IOP321_REG_ADDR(0x00000148)
-#define IOP321_ERTVR      (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
-#define IOP321_IALR1      (volatile u32 *)IOP321_REG_ADDR(0x00000150)
-#define IOP321_IALR2      (volatile u32 *)IOP321_REG_ADDR(0x00000154)
-#define IOP321_IATVR2     (volatile u32 *)IOP321_REG_ADDR(0x00000158)
-#define IOP321_OIOWTVR    (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
-#define IOP321_OMWTVR0    (volatile u32 *)IOP321_REG_ADDR(0x00000160)
-#define IOP321_OUMWTVR0   (volatile u32 *)IOP321_REG_ADDR(0x00000164)
-#define IOP321_OMWTVR1    (volatile u32 *)IOP321_REG_ADDR(0x00000168)
-#define IOP321_OUMWTVR1   (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
-/* Reserved 0x00000170 through 0x00000177*/
-#define IOP321_OUDWTVR    (volatile u32 *)IOP321_REG_ADDR(0x00000178)
-/* Reserved 0x0000017C through 0x0000017F*/
-#define IOP321_ATUCR      (volatile u32 *)IOP321_REG_ADDR(0x00000180)
-#define IOP321_PCSR       (volatile u32 *)IOP321_REG_ADDR(0x00000184)
-#define IOP321_ATUISR     (volatile u32 *)IOP321_REG_ADDR(0x00000188)
-#define IOP321_ATUIMR     (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
-#define IOP321_IABAR3     (volatile u32 *)IOP321_REG_ADDR(0x00000190)
-#define IOP321_IAUBAR3    (volatile u32 *)IOP321_REG_ADDR(0x00000194)
-#define IOP321_IALR3      (volatile u32 *)IOP321_REG_ADDR(0x00000198)
-#define IOP321_IATVR3     (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
-/* Reserved 0x000001A0 through 0x000001A3*/
-#define IOP321_OCCAR      (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
-/* Reserved 0x000001A8 through 0x000001AB*/
-#define IOP321_OCCDR      (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
-/* Reserved 0x000001B0 through 0x000001BB*/
-#define IOP321_PDSCR      (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
-#define IOP321_PMCAPID    (volatile u8  *)IOP321_REG_ADDR(0x000001C0)
-#define IOP321_PMNEXT     (volatile u8  *)IOP321_REG_ADDR(0x000001C1)
-#define IOP321_APMCR      (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
-#define IOP321_APMCSR     (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
-/* Reserved 0x000001C6 through 0x000001DF */
-#define IOP321_PCIXCAPID  (volatile u8  *)IOP321_REG_ADDR(0x000001E0)
-#define IOP321_PCIXNEXT   (volatile u8  *)IOP321_REG_ADDR(0x000001E1)
-#define IOP321_PCIXCMD    (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
-#define IOP321_PCIXSR     (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
-#define IOP321_PCIIRSR    (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
-/* Messaging Unit 0x00000300 through 0x000003FF */
-/* Reserved 0x00000300 through 0x0000030c */
-#define IOP321_IMR0       (volatile u32 *)IOP321_REG_ADDR(0x00000310)
-#define IOP321_IMR1       (volatile u32 *)IOP321_REG_ADDR(0x00000314)
-#define IOP321_OMR0       (volatile u32 *)IOP321_REG_ADDR(0x00000318)
-#define IOP321_OMR1       (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
-#define IOP321_IDR        (volatile u32 *)IOP321_REG_ADDR(0x00000320)
-#define IOP321_IISR       (volatile u32 *)IOP321_REG_ADDR(0x00000324)
-#define IOP321_IIMR       (volatile u32 *)IOP321_REG_ADDR(0x00000328)
-#define IOP321_ODR        (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
-#define IOP321_OISR       (volatile u32 *)IOP321_REG_ADDR(0x00000330)
-#define IOP321_OIMR       (volatile u32 *)IOP321_REG_ADDR(0x00000334)
-/* Reserved 0x00000338 through 0x0000034F */
-#define IOP321_MUCR       (volatile u32 *)IOP321_REG_ADDR(0x00000350)
-#define IOP321_QBAR       (volatile u32 *)IOP321_REG_ADDR(0x00000354)
-/* Reserved 0x00000358 through 0x0000035C */
-#define IOP321_IFHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000360)
-#define IOP321_IFTPR      (volatile u32 *)IOP321_REG_ADDR(0x00000364)
-#define IOP321_IPHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000368)
-#define IOP321_IPTPR      (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
-#define IOP321_OFHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000370)
-#define IOP321_OFTPR      (volatile u32 *)IOP321_REG_ADDR(0x00000374)
-#define IOP321_OPHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000378)
-#define IOP321_OPTPR      (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
-#define IOP321_IAR        (volatile u32 *)IOP321_REG_ADDR(0x00000380)
-#define IOP321_IIxR_MASK        0x7f /* masks all */
-#define IOP321_IIxR_IRI         0x40 /* RC Index Register Interrupt */
-#define IOP321_IIxR_OFQF        0x20 /* RC Output Free Q Full (ERROR) */
-#define IOP321_IIxR_ipq         0x10 /* RC Inbound Post Q (post) */
-#define IOP321_IIxR_ERRDI       0x08 /* RO Error Doorbell Interrupt */
-#define IOP321_IIxR_IDI         0x04 /* RO Inbound Doorbell Interrupt */
-#define IOP321_IIxR_IM1         0x02 /* RC Inbound Message 1 Interrupt */
-#define IOP321_IIxR_IM0         0x01 /* RC Inbound Message 0 Interrupt */
-/* Reserved 0x00000384 through 0x000003FF */
-/* DMA Controller 0x00000400 through 0x000004FF */
-#define IOP321_DMA0_CCR   (volatile u32 *)IOP321_REG_ADDR(0x00000400)
-#define IOP321_DMA0_CSR   (volatile u32 *)IOP321_REG_ADDR(0x00000404)
-#define IOP321_DMA0_DAR   (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
-#define IOP321_DMA0_NDAR  (volatile u32 *)IOP321_REG_ADDR(0x00000410)
-#define IOP321_DMA0_PADR  (volatile u32 *)IOP321_REG_ADDR(0x00000414)
-#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
-#define IOP321_DMA0_LADR  (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
-#define IOP321_DMA0_BCR   (volatile u32 *)IOP321_REG_ADDR(0x00000420)
-#define IOP321_DMA0_DCR   (volatile u32 *)IOP321_REG_ADDR(0x00000424)
-/* Reserved 0x00000428 through 0x0000043C */
-#define IOP321_DMA1_CCR   (volatile u32 *)IOP321_REG_ADDR(0x00000440)
-#define IOP321_DMA1_CSR   (volatile u32 *)IOP321_REG_ADDR(0x00000444)
-#define IOP321_DMA1_DAR   (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
-#define IOP321_DMA1_NDAR  (volatile u32 *)IOP321_REG_ADDR(0x00000450)
-#define IOP321_DMA1_PADR  (volatile u32 *)IOP321_REG_ADDR(0x00000454)
-#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
-#define IOP321_DMA1_LADR  (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
-#define IOP321_DMA1_BCR   (volatile u32 *)IOP321_REG_ADDR(0x00000460)
-#define IOP321_DMA1_DCR   (volatile u32 *)IOP321_REG_ADDR(0x00000464)
-/* Reserved 0x00000468 through 0x000004FF */
-/* Memory controller 0x00000500 through 0x0005FF */
-/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
-#define IOP321_PBCR       (volatile u32 *)IOP321_REG_ADDR(0x00000680)
-#define IOP321_PBISR      (volatile u32 *)IOP321_REG_ADDR(0x00000684)
-#define IOP321_PBBAR0     (volatile u32 *)IOP321_REG_ADDR(0x00000688)
-#define IOP321_PBLR0      (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
-#define IOP321_PBBAR1     (volatile u32 *)IOP321_REG_ADDR(0x00000690)
-#define IOP321_PBLR1      (volatile u32 *)IOP321_REG_ADDR(0x00000694)
-#define IOP321_PBBAR2     (volatile u32 *)IOP321_REG_ADDR(0x00000698)
-#define IOP321_PBLR2      (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
-#define IOP321_PBBAR3     (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
-#define IOP321_PBLR3      (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
-#define IOP321_PBBAR4     (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
-#define IOP321_PBLR4      (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
-#define IOP321_PBBAR5     (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
-#define IOP321_PBLR5      (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
-#define IOP321_PBDSCR     (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
-/* Reserved 0x000006BC */
-#define IOP321_PMBR0      (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
-/* Reserved 0x000006C4 through 0x000006DC */
-#define IOP321_PMBR1      (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
-#define IOP321_PMBR2      (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
-#define IOP321_PBCR_EN    0x1
-#define IOP321_PBISR_BOOR_ERR 0x1
-/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
-#define IOP321_GTMR     (volatile u32 *)IOP321_REG_ADDR(0x00000700)
-#define IOP321_ESR      (volatile u32 *)IOP321_REG_ADDR(0x00000704)
-#define IOP321_EMISR    (volatile u32 *)IOP321_REG_ADDR(0x00000708)
-/* reserved 0x00000070c */
-#define IOP321_GTSR     (volatile u32 *)IOP321_REG_ADDR(0x00000710)
-/* PERC0 DOESN'T EXIST - index from 1! */
-#define IOP321_PERCR0   (volatile u32 *)IOP321_REG_ADDR(0x00000710)
-#define IOP321_GTMR_NGCE        0x04 /* (Not) Global Counter Enable */
-/* Internal arbitration unit 0x00000780 through 0x0007BF */
-#define IOP321_IACR     (volatile u32 *)IOP321_REG_ADDR(0x00000780)
-#define IOP321_MTTR1    (volatile u32 *)IOP321_REG_ADDR(0x00000784)
-#define IOP321_MTTR2    (volatile u32 *)IOP321_REG_ADDR(0x00000788)
-/* General Purpose I/O Registers */
-#define IOP321_GPOE       (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
-#define IOP321_GPID       (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
-#define IOP321_GPOD       (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
-/* Interrupt Controller */
-#define IOP321_INTCTL     (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
-#define IOP321_INTSTR     (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
-#define IOP321_IINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
-#define IOP321_FINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
-/* Timers */
-#define IOP321_TU_TMR0          (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
-#define IOP321_TU_TMR1          (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
-#ifdef CONFIG_ARCH_IQ80321
-#define IOP321_TICK_RATE        200000000       /* 200 MHz clock */
-#elif defined(CONFIG_ARCH_IQ31244)
-#define IOP321_TICK_RATE        198000000       /* 33.000 MHz crystal */
-#endif
-#ifdef CONFIG_ARCH_EP80219
-#undef IOP321_TICK_RATE
-#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
-#endif
-#define IOP321_TMR_TC           0x01
-#define IOP321_TMR_EN           0x02
-#define IOP321_TMR_RELOAD       0x04
-#define IOP321_TMR_PRIVILEGED   0x09
-#define IOP321_TMR_RATIO_1_1    0x00
-#define IOP321_TMR_RATIO_4_1    0x10
-#define IOP321_TMR_RATIO_8_1    0x20
-#define IOP321_TMR_RATIO_16_1   0x30
-#define IOP321_TU_TCR0    (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
-#define IOP321_TU_TCR1    (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
-#define IOP321_TU_TRR0    (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
-#define IOP321_TU_TRR1    (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
-#define IOP321_TU_TISR    (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
-#define IOP321_TU_WDTCR   (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
-/* Application accelerator unit 0x00000800 - 0x000008FF */
-#define IOP321_AAU_ACR     (volatile u32 *)IOP321_REG_ADDR(0x00000800)
-#define IOP321_AAU_ASR     (volatile u32 *)IOP321_REG_ADDR(0x00000804)
-#define IOP321_AAU_ADAR    (volatile u32 *)IOP321_REG_ADDR(0x00000808)
-#define IOP321_AAU_ANDAR   (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
-#define IOP321_AAU_SAR1    (volatile u32 *)IOP321_REG_ADDR(0x00000810)
-#define IOP321_AAU_SAR2    (volatile u32 *)IOP321_REG_ADDR(0x00000814)
-#define IOP321_AAU_SAR3    (volatile u32 *)IOP321_REG_ADDR(0x00000818)
-#define IOP321_AAU_SAR4    (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
-#define IOP321_AAU_SAR5    (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
-#define IOP321_AAU_SAR6    (volatile u32 *)IOP321_REG_ADDR(0x00000830)
-#define IOP321_AAU_SAR7    (volatile u32 *)IOP321_REG_ADDR(0x00000834)
-#define IOP321_AAU_SAR8    (volatile u32 *)IOP321_REG_ADDR(0x00000838)
-#define IOP321_AAU_SAR9    (volatile u32 *)IOP321_REG_ADDR(0x00000840)
-#define IOP321_AAU_SAR10   (volatile u32 *)IOP321_REG_ADDR(0x00000844)
-#define IOP321_AAU_SAR11   (volatile u32 *)IOP321_REG_ADDR(0x00000848)
-#define IOP321_AAU_SAR12   (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
-#define IOP321_AAU_SAR13   (volatile u32 *)IOP321_REG_ADDR(0x00000850)
-#define IOP321_AAU_SAR14   (volatile u32 *)IOP321_REG_ADDR(0x00000854)
-#define IOP321_AAU_SAR15   (volatile u32 *)IOP321_REG_ADDR(0x00000858)
-#define IOP321_AAU_SAR16   (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
-#define IOP321_AAU_SAR17   (volatile u32 *)IOP321_REG_ADDR(0x00000864)
-#define IOP321_AAU_SAR18   (volatile u32 *)IOP321_REG_ADDR(0x00000868)
-#define IOP321_AAU_SAR19   (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
-#define IOP321_AAU_SAR20   (volatile u32 *)IOP321_REG_ADDR(0x00000870)
-#define IOP321_AAU_SAR21   (volatile u32 *)IOP321_REG_ADDR(0x00000874)
-#define IOP321_AAU_SAR22   (volatile u32 *)IOP321_REG_ADDR(0x00000878)
-#define IOP321_AAU_SAR23   (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
-#define IOP321_AAU_SAR24   (volatile u32 *)IOP321_REG_ADDR(0x00000880)
-#define IOP321_AAU_SAR25   (volatile u32 *)IOP321_REG_ADDR(0x00000888)
-#define IOP321_AAU_SAR26   (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
-#define IOP321_AAU_SAR27   (volatile u32 *)IOP321_REG_ADDR(0x00000890)
-#define IOP321_AAU_SAR28   (volatile u32 *)IOP321_REG_ADDR(0x00000894)
-#define IOP321_AAU_SAR29   (volatile u32 *)IOP321_REG_ADDR(0x00000898)
-#define IOP321_AAU_SAR30   (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
-#define IOP321_AAU_SAR31   (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
-#define IOP321_AAU_SAR32   (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
-#define IOP321_AAU_DAR     (volatile u32 *)IOP321_REG_ADDR(0x00000820)
-#define IOP321_AAU_ABCR    (volatile u32 *)IOP321_REG_ADDR(0x00000824)
-#define IOP321_AAU_ADCR    (volatile u32 *)IOP321_REG_ADDR(0x00000828)
-#define IOP321_AAU_EDCR0   (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
-#define IOP321_AAU_EDCR1   (volatile u32 *)IOP321_REG_ADDR(0x00000860)
-#define IOP321_AAU_EDCR2   (volatile u32 *)IOP321_REG_ADDR(0x00000884)
-/* SSP serial port unit 0x00001600 - 0x0000167F */
-/* I2C bus interface unit 0x00001680 - 0x000016FF */
-#define IOP321_ICR0       (volatile u32 *)IOP321_REG_ADDR(0x00001680)
-#define IOP321_ISR0       (volatile u32 *)IOP321_REG_ADDR(0x00001684)
-#define IOP321_ISAR0      (volatile u32 *)IOP321_REG_ADDR(0x00001688)
-#define IOP321_IDBR0      (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
-/* Reserved 0x00001690 */
-#define IOP321_IBMR0      (volatile u32 *)IOP321_REG_ADDR(0x00001694)
-/* Reserved 0x00001698 */
-/* Reserved 0x0000169C */
-#define IOP321_ICR1       (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
-#define IOP321_ISR1       (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
-#define IOP321_ISAR1      (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
-#define IOP321_IDBR1      (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
-#define IOP321_IBMR1      (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
-/* Reserved 0x000016B8 through 0x000016FC */
-/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
-#ifndef __ASSEMBLY__
-extern void iop321_map_io(void);
-extern void iop321_init_irq(void);
-extern void iop321_time_init(void);
-#endif
-#endif // _IOP321_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331-irqs.h b/include/asm-arm/arch-iop3xx/iop331-irqs.h
deleted file mode 100644
index 7135ad7e335e..000000000000
--- a/include/asm-arm/arch-iop3xx/iop331-irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/irqs.h
- *
- * Author:      Dave Jiang (dave.jiang@intel.com)
- * Copyright:   (C) 2003 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#ifndef _IOP331_IRQS_H_
-#define _IOP331_IRQS_H_
-/*
- * IOP80331 chipset interrupts
- */
-#define IOP331_IRQ_OFS          0
-#define IOP331_IRQ(x)           (IOP331_IRQ_OFS + (x))
-/*
- * On IRQ or FIQ register
- */
-#define IRQ_IOP331_DMA0_EOT     IOP331_IRQ(0)
-#define IRQ_IOP331_DMA0_EOC     IOP331_IRQ(1)
-#define IRQ_IOP331_DMA1_EOT     IOP331_IRQ(2)
-#define IRQ_IOP331_DMA1_EOC     IOP331_IRQ(3)
-#define IRQ_IOP331_RSVD_4       IOP331_IRQ(4)
-#define IRQ_IOP331_RSVD_5       IOP331_IRQ(5)
-#define IRQ_IOP331_AA_EOT       IOP331_IRQ(6)
-#define IRQ_IOP331_AA_EOC       IOP331_IRQ(7)
-#define IRQ_IOP331_TIMER0       IOP331_IRQ(8)
-#define IRQ_IOP331_TIMER1       IOP331_IRQ(9)
-#define IRQ_IOP331_I2C_0        IOP331_IRQ(10)
-#define IRQ_IOP331_I2C_1        IOP331_IRQ(11)
-#define IRQ_IOP331_MSG      IOP331_IRQ(12)
-#define IRQ_IOP331_MSGIBQ   IOP331_IRQ(13)
-#define IRQ_IOP331_ATU_BIST     IOP331_IRQ(14)
-#define IRQ_IOP331_PERFMON      IOP331_IRQ(15)
-#define IRQ_IOP331_CORE_PMU     IOP331_IRQ(16)
-#define IRQ_IOP331_RSVD_17      IOP331_IRQ(17)
-#define IRQ_IOP331_RSVD_18      IOP331_IRQ(18)
-#define IRQ_IOP331_RSVD_19      IOP331_IRQ(19)
-#define IRQ_IOP331_RSVD_20      IOP331_IRQ(20)
-#define IRQ_IOP331_RSVD_21      IOP331_IRQ(21)
-#define IRQ_IOP331_RSVD_22      IOP331_IRQ(22)
-#define IRQ_IOP331_RSVD_23      IOP331_IRQ(23)
-#define IRQ_IOP331_XINT0        IOP331_IRQ(24)
-#define IRQ_IOP331_XINT1        IOP331_IRQ(25)
-#define IRQ_IOP331_XINT2        IOP331_IRQ(26)
-#define IRQ_IOP331_XINT3        IOP331_IRQ(27)
-#define IRQ_IOP331_RSVD_28  IOP331_IRQ(28)
-#define IRQ_IOP331_RSVD_29  IOP331_IRQ(29)
-#define IRQ_IOP331_RSVD_30  IOP331_IRQ(30)
-#define IRQ_IOP331_RSVD_31  IOP331_IRQ(31)
-#define IRQ_IOP331_XINT8    IOP331_IRQ(32)  // 0
-#define IRQ_IOP331_XINT9    IOP331_IRQ(33)  // 1
-#define IRQ_IOP331_XINT10   IOP331_IRQ(34)  // 2
-#define IRQ_IOP331_XINT11   IOP331_IRQ(35)  // 3
-#define IRQ_IOP331_XINT12   IOP331_IRQ(36)  // 4
-#define IRQ_IOP331_XINT13   IOP331_IRQ(37)  // 5
-#define IRQ_IOP331_XINT14   IOP331_IRQ(38)  // 6
-#define IRQ_IOP331_XINT15   IOP331_IRQ(39)  // 7
-#define IRQ_IOP331_RSVD_40  IOP331_IRQ(40)  // 8
-#define IRQ_IOP331_RSVD_41  IOP331_IRQ(41)  // 9
-#define IRQ_IOP331_RSVD_42  IOP331_IRQ(42)  // 10
-#define IRQ_IOP331_RSVD_43  IOP331_IRQ(43)  // 11
-#define IRQ_IOP331_RSVD_44  IOP331_IRQ(44)  // 12
-#define IRQ_IOP331_RSVD_45  IOP331_IRQ(45)  // 13
-#define IRQ_IOP331_RSVD_46  IOP331_IRQ(46)  // 14
-#define IRQ_IOP331_RSVD_47  IOP331_IRQ(47)  // 15
-#define IRQ_IOP331_RSVD_48  IOP331_IRQ(48)  // 16
-#define IRQ_IOP331_RSVD_49  IOP331_IRQ(49)  // 17
-#define IRQ_IOP331_RSVD_50  IOP331_IRQ(50)  // 18
-#define IRQ_IOP331_UART0    IOP331_IRQ(51)  // 19
-#define IRQ_IOP331_UART1    IOP331_IRQ(52)  // 20
-#define IRQ_IOP331_PBIE     IOP331_IRQ(53)  // 21
-#define IRQ_IOP331_ATU_CRW  IOP331_IRQ(54)  // 22
-#define IRQ_IOP331_ATU_ERR      IOP331_IRQ(55)  // 23
-#define IRQ_IOP331_MCU_ERR      IOP331_IRQ(56)  // 24
-#define IRQ_IOP331_DMA0_ERR     IOP331_IRQ(57)  // 25
-#define IRQ_IOP331_DMA1_ERR     IOP331_IRQ(58)  // 26
-#define IRQ_IOP331_RSVD_59  IOP331_IRQ(59)  // 27
-#define IRQ_IOP331_AA_ERR       IOP331_IRQ(60)  // 28
-#define IRQ_IOP331_RSVD_61  IOP331_IRQ(61)  // 29
-#define IRQ_IOP331_MSG_ERR      IOP331_IRQ(62)  // 30
-#define IRQ_IOP331_HPI          IOP331_IRQ(63)  // 31
-#define NR_IOP331_IRQS          (IOP331_IRQ(63) + 1)
-#define NR_IRQS                 NR_IOP331_IRQS
-/*
- * Interrupts available on the IQ80331 board
- */
-/*
- * On board devices
- */
-#define IRQ_IQ80331_I82544      IRQ_IOP331_XINT0
-#define IRQ_IQ80331_UART0       IRQ_IOP331_UART0
-#define IRQ_IQ80331_UART1       IRQ_IOP331_UART1
-/*
- * PCI interrupts
- */
-#define IRQ_IQ80331_INTA        IRQ_IOP331_XINT0
-#define IRQ_IQ80331_INTB        IRQ_IOP331_XINT1
-#define IRQ_IQ80331_INTC        IRQ_IOP331_XINT2
-#define IRQ_IQ80331_INTD        IRQ_IOP331_XINT3
-/*
- * Interrupts available on the IQ80332 board
- */
-/*
- * On board devices
- */
-#define IRQ_IQ80332_I82544      IRQ_IOP331_XINT0
-#define IRQ_IQ80332_UART0       IRQ_IOP331_UART0
-#define IRQ_IQ80332_UART1       IRQ_IOP331_UART1
-/*
- * PCI interrupts
- */
-#define IRQ_IQ80332_INTA        IRQ_IOP331_XINT0
-#define IRQ_IQ80332_INTB        IRQ_IOP331_XINT1
-#define IRQ_IQ80332_INTC        IRQ_IOP331_XINT2
-#define IRQ_IQ80332_INTD        IRQ_IOP331_XINT3
-#endif // _IOP331_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h
deleted file mode 100644
index fbf0cc11bdd9..000000000000
--- a/include/asm-arm/arch-iop3xx/iop331.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * linux/include/asm/arch-iop3xx/iop331.h
- *
- * Intel IOP331 Chip definitions
- *
- * Author: Dave Jiang (dave.jiang@intel.com)
- * Copyright (C) 2003, 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _IOP331_HW_H_
-#define _IOP331_HW_H_
-/*
- * This is needed for mixed drivers that need to work on all
- * IOP3xx variants but behave slightly differently on each.
- */
-#ifndef __ASSEMBLY__
-#ifdef  CONFIG_ARCH_IOP331
-/*#define       iop_is_331()    ((processor_id & 0xffffffb0) == 0x69054090) */
-#define iop_is_331()    ((processor_id & 0xffffff30) == 0x69054010)
-#else
-#define iop_is_331()    0
-#endif
-#endif
-/*
- * IOP331 I/O and Mem space regions for PCI autoconfiguration
- */
-#define IOP331_PCI_IO_WINDOW_SIZE   0x00010000
-#define IOP331_PCI_LOWER_IO_PA      0x90000000
-#define IOP331_PCI_LOWER_IO_VA      0xfe000000
-#define IOP331_PCI_LOWER_IO_BA      (*IOP331_OIOWTVR)
-#define IOP331_PCI_UPPER_IO_PA      (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
-#define IOP331_PCI_UPPER_IO_VA      (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
-#define IOP331_PCI_UPPER_IO_BA      (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
-#define IOP331_PCI_IO_OFFSET        (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
-/* this can be 128M if OMWTVR1 is set */
-#define IOP331_PCI_MEM_WINDOW_SIZE      0x04000000 /* 64M outbound window */
-/* #define IOP331_PCI_MEM_WINDOW_SIZE  (~*IOP331_IALR1 + 1) */
-#define IOP331_PCI_LOWER_MEM_PA     0x80000000
-#define IOP331_PCI_LOWER_MEM_BA     (*IOP331_OMWTVR0)
-#define IOP331_PCI_UPPER_MEM_PA     (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
-#define IOP331_PCI_UPPER_MEM_BA     (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
-#define IOP331_PCI_MEM_OFFSET       (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
-/*
- * IOP331 chipset registers
- */
-#define IOP331_VIRT_MEM_BASE  0xfeffe000  /* chip virtual mem address*/
-#define IOP331_PHYS_MEM_BASE  0xffffe000  /* chip physical memory address */
-#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
-/* Reserved 0x00000000 through 0x000000FF */
-/* Address Translation Unit 0x00000100 through 0x000001FF */
-#define IOP331_ATUVID     (volatile u16 *)IOP331_REG_ADDR(0x00000100)
-#define IOP331_ATUDID     (volatile u16 *)IOP331_REG_ADDR(0x00000102)
-#define IOP331_ATUCMD     (volatile u16 *)IOP331_REG_ADDR(0x00000104)
-#define IOP331_ATUSR      (volatile u16 *)IOP331_REG_ADDR(0x00000106)
-#define IOP331_ATURID     (volatile u8  *)IOP331_REG_ADDR(0x00000108)
-#define IOP331_ATUCCR     (volatile u32 *)IOP331_REG_ADDR(0x00000109)
-#define IOP331_ATUCLSR    (volatile u8  *)IOP331_REG_ADDR(0x0000010C)
-#define IOP331_ATULT      (volatile u8  *)IOP331_REG_ADDR(0x0000010D)
-#define IOP331_ATUHTR     (volatile u8  *)IOP331_REG_ADDR(0x0000010E)
-#define IOP331_ATUBIST    (volatile u8  *)IOP331_REG_ADDR(0x0000010F)
-#define IOP331_IABAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000110)
-#define IOP331_IAUBAR0    (volatile u32 *)IOP331_REG_ADDR(0x00000114)
-#define IOP331_IABAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000118)
-#define IOP331_IAUBAR1    (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
-#define IOP331_IABAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000120)
-#define IOP331_IAUBAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000124)
-#define IOP331_ASVIR      (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
-#define IOP331_ASIR       (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
-#define IOP331_ERBAR      (volatile u32 *)IOP331_REG_ADDR(0x00000130)
-#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
-/* Reserved 0x00000138 through 0x0000013B */
-#define IOP331_ATUILR     (volatile u8  *)IOP331_REG_ADDR(0x0000013C)
-#define IOP331_ATUIPR     (volatile u8  *)IOP331_REG_ADDR(0x0000013D)
-#define IOP331_ATUMGNT    (volatile u8  *)IOP331_REG_ADDR(0x0000013E)
-#define IOP331_ATUMLAT    (volatile u8  *)IOP331_REG_ADDR(0x0000013F)
-#define IOP331_IALR0      (volatile u32 *)IOP331_REG_ADDR(0x00000140)
-#define IOP331_IATVR0     (volatile u32 *)IOP331_REG_ADDR(0x00000144)
-#define IOP331_ERLR       (volatile u32 *)IOP331_REG_ADDR(0x00000148)
-#define IOP331_ERTVR      (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
-#define IOP331_IALR1      (volatile u32 *)IOP331_REG_ADDR(0x00000150)
-#define IOP331_IALR2      (volatile u32 *)IOP331_REG_ADDR(0x00000154)
-#define IOP331_IATVR2     (volatile u32 *)IOP331_REG_ADDR(0x00000158)
-#define IOP331_OIOWTVR    (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
-#define IOP331_OMWTVR0    (volatile u32 *)IOP331_REG_ADDR(0x00000160)
-#define IOP331_OUMWTVR0   (volatile u32 *)IOP331_REG_ADDR(0x00000164)
-#define IOP331_OMWTVR1    (volatile u32 *)IOP331_REG_ADDR(0x00000168)
-#define IOP331_OUMWTVR1   (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
-/* Reserved 0x00000170 through 0x00000177*/
-#define IOP331_OUDWTVR    (volatile u32 *)IOP331_REG_ADDR(0x00000178)
-/* Reserved 0x0000017C through 0x0000017F*/
-#define IOP331_ATUCR      (volatile u32 *)IOP331_REG_ADDR(0x00000180)
-#define IOP331_PCSR       (volatile u32 *)IOP331_REG_ADDR(0x00000184)
-#define IOP331_ATUISR     (volatile u32 *)IOP331_REG_ADDR(0x00000188)
-#define IOP331_ATUIMR     (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
-#define IOP331_IABAR3     (volatile u32 *)IOP331_REG_ADDR(0x00000190)
-#define IOP331_IAUBAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000194)
-#define IOP331_IALR3      (volatile u32 *)IOP331_REG_ADDR(0x00000198)
-#define IOP331_IATVR3     (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
-/* Reserved 0x000001A0 through 0x000001A3*/
-#define IOP331_OCCAR      (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
-/* Reserved 0x000001A8 through 0x000001AB*/
-#define IOP331_OCCDR      (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
-/* Reserved 0x000001B0 through 0x000001BB*/
-#define IOP331_VPDCAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
-#define IOP331_VPDNXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
-#define IOP331_VPDAR      (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
-#define IOP331_VPDDR      (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
-#define IOP331_PMCAPID    (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
-#define IOP331_PMNEXT     (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
-#define IOP331_APMCR      (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
-#define IOP331_APMCSR     (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
-/* Reserved 0x000001C6 through 0x000001CF */
-#define IOP331_MSICAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
-#define IOP331_MSINXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
-#define IOP331_MSIMCR     (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
-#define IOP331_MSIMAR     (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
-#define IOP331_MSIMUAR    (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
-#define IOP331_MSIMDR     (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
-#define IOP331_PCIXCAPID  (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
-#define IOP331_PCIXNEXT   (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
-#define IOP331_PCIXCMD    (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
-#define IOP331_PCIXSR     (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
-#define IOP331_PCIIRSR    (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
-/* Messaging Unit 0x00000300 through 0x000003FF */
-/* Reserved 0x00000300 through 0x0000030c */
-#define IOP331_IMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000310)
-#define IOP331_IMR1       (volatile u32 *)IOP331_REG_ADDR(0x00000314)
-#define IOP331_OMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000318)
-#define IOP331_OMR1       (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
-#define IOP331_IDR        (volatile u32 *)IOP331_REG_ADDR(0x00000320)
-#define IOP331_IISR       (volatile u32 *)IOP331_REG_ADDR(0x00000324)
-#define IOP331_IIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000328)
-#define IOP331_ODR        (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
-#define IOP331_OISR       (volatile u32 *)IOP331_REG_ADDR(0x00000330)
-#define IOP331_OIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000334)
-/* Reserved 0x00000338 through 0x0000034F */
-#define IOP331_MUCR       (volatile u32 *)IOP331_REG_ADDR(0x00000350)
-#define IOP331_QBAR       (volatile u32 *)IOP331_REG_ADDR(0x00000354)
-/* Reserved 0x00000358 through 0x0000035C */
-#define IOP331_IFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000360)
-#define IOP331_IFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000364)
-#define IOP331_IPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000368)
-#define IOP331_IPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
-#define IOP331_OFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000370)
-#define IOP331_OFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000374)
-#define IOP331_OPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000378)
-#define IOP331_OPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
-#define IOP331_IAR        (volatile u32 *)IOP331_REG_ADDR(0x00000380)
-/* Reserved 0x00000384 through 0x000003FF */
-/* DMA Controller 0x00000400 through 0x000004FF */
-#define IOP331_DMA0_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000400)
-#define IOP331_DMA0_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000404)
-#define IOP331_DMA0_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
-#define IOP331_DMA0_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000410)
-#define IOP331_DMA0_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000414)
-#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
-#define IOP331_DMA0_LADR  (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
-#define IOP331_DMA0_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000420)
-#define IOP331_DMA0_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000424)
-/* Reserved 0x00000428 through 0x0000043C */
-#define IOP331_DMA1_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000440)
-#define IOP331_DMA1_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000444)
-#define IOP331_DMA1_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
-#define IOP331_DMA1_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000450)
-#define IOP331_DMA1_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000454)
-#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
-#define IOP331_DMA1_LADR  (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
-#define IOP331_DMA1_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000460)
-#define IOP331_DMA1_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000464)
-/* Reserved 0x00000468 through 0x000004FF */
-/* Memory controller 0x00000500 through 0x0005FF */
-/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
-#define IOP331_PBCR       (volatile u32 *)IOP331_REG_ADDR(0x00000680)
-#define IOP331_PBISR      (volatile u32 *)IOP331_REG_ADDR(0x00000684)
-#define IOP331_PBBAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000688)
-#define IOP331_PBLR0      (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
-#define IOP331_PBBAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000690)
-#define IOP331_PBLR1      (volatile u32 *)IOP331_REG_ADDR(0x00000694)
-#define IOP331_PBBAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000698)
-#define IOP331_PBLR2      (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
-#define IOP331_PBBAR3     (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
-#define IOP331_PBLR3      (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
-#define IOP331_PBBAR4     (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
-#define IOP331_PBLR4      (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
-#define IOP331_PBBAR5     (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
-#define IOP331_PBLR5      (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
-#define IOP331_PBDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
-/* Reserved 0x000006BC */
-#define IOP331_PMBR0      (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
-/* Reserved 0x000006C4 through 0x000006DC */
-#define IOP331_PMBR1      (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
-#define IOP331_PMBR2      (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
-#define IOP331_PBCR_EN    0x1
-#define IOP331_PBISR_BOOR_ERR 0x1
-/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
-/* Internal arbitration unit 0x00000780 through 0x0007BF */
-/* Interrupt Controller */
-#define IOP331_INTCTL0    (volatile u32 *)IOP331_REG_ADDR(0x00000790)
-#define IOP331_INTCTL1    (volatile u32 *)IOP331_REG_ADDR(0x00000794)
-#define IOP331_INTSTR0    (volatile u32 *)IOP331_REG_ADDR(0x00000798)
-#define IOP331_INTSTR1    (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
-#define IOP331_IINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
-#define IOP331_IINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
-#define IOP331_FINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
-#define IOP331_FINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
-#define IOP331_IPR0       (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
-#define IOP331_IPR1       (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
-#define IOP331_IPR2       (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
-#define IOP331_IPR3       (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
-#define IOP331_INTBASE    (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
-#define IOP331_INTSIZE    (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
-#define IOP331_IINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
-#define IOP331_FINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
-/* Timers */
-#define IOP331_TU_TMR0          (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
-#define IOP331_TU_TMR1          (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
-#define IOP331_TMR_TC           0x01
-#define IOP331_TMR_EN           0x02
-#define IOP331_TMR_RELOAD       0x04
-#define IOP331_TMR_PRIVILEGED   0x09
-#define IOP331_TMR_RATIO_1_1    0x00
-#define IOP331_TMR_RATIO_4_1    0x10
-#define IOP331_TMR_RATIO_8_1    0x20
-#define IOP331_TMR_RATIO_16_1   0x30
-#define IOP331_TU_TCR0    (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
-#define IOP331_TU_TCR1    (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
-#define IOP331_TU_TRR0    (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
-#define IOP331_TU_TRR1    (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
-#define IOP331_TU_TISR    (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
-#define IOP331_TU_WDTCR   (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
-#if defined(CONFIG_ARCH_IOP331)
-#define IOP331_TICK_RATE        266000000       /* 266 MHz IB clock */
-#endif
-#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
-#undef IOP331_TICK_RATE
-#define IOP331_TICK_RATE        333000000       /* 333 Mhz IB clock */
-#endif
-/* Application accelerator unit 0x00000800 - 0x000008FF */
-#define IOP331_AAU_ACR     (volatile u32 *)IOP331_REG_ADDR(0x00000800)
-#define IOP331_AAU_ASR     (volatile u32 *)IOP331_REG_ADDR(0x00000804)
-#define IOP331_AAU_ADAR    (volatile u32 *)IOP331_REG_ADDR(0x00000808)
-#define IOP331_AAU_ANDAR   (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
-#define IOP331_AAU_SAR1    (volatile u32 *)IOP331_REG_ADDR(0x00000810)
-#define IOP331_AAU_SAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000814)
-#define IOP331_AAU_SAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000818)
-#define IOP331_AAU_SAR4    (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
-#define IOP331_AAU_SAR5    (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
-#define IOP331_AAU_SAR6    (volatile u32 *)IOP331_REG_ADDR(0x00000830)
-#define IOP331_AAU_SAR7    (volatile u32 *)IOP331_REG_ADDR(0x00000834)
-#define IOP331_AAU_SAR8    (volatile u32 *)IOP331_REG_ADDR(0x00000838)
-#define IOP331_AAU_SAR9    (volatile u32 *)IOP331_REG_ADDR(0x00000840)
-#define IOP331_AAU_SAR10   (volatile u32 *)IOP331_REG_ADDR(0x00000844)
-#define IOP331_AAU_SAR11   (volatile u32 *)IOP331_REG_ADDR(0x00000848)
-#define IOP331_AAU_SAR12   (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
-#define IOP331_AAU_SAR13   (volatile u32 *)IOP331_REG_ADDR(0x00000850)
-#define IOP331_AAU_SAR14   (volatile u32 *)IOP331_REG_ADDR(0x00000854)
-#define IOP331_AAU_SAR15   (volatile u32 *)IOP331_REG_ADDR(0x00000858)
-#define IOP331_AAU_SAR16   (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
-#define IOP331_AAU_SAR17   (volatile u32 *)IOP331_REG_ADDR(0x00000864)
-#define IOP331_AAU_SAR18   (volatile u32 *)IOP331_REG_ADDR(0x00000868)
-#define IOP331_AAU_SAR19   (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
-#define IOP331_AAU_SAR20   (volatile u32 *)IOP331_REG_ADDR(0x00000870)
-#define IOP331_AAU_SAR21   (volatile u32 *)IOP331_REG_ADDR(0x00000874)
-#define IOP331_AAU_SAR22   (volatile u32 *)IOP331_REG_ADDR(0x00000878)
-#define IOP331_AAU_SAR23   (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
-#define IOP331_AAU_SAR24   (volatile u32 *)IOP331_REG_ADDR(0x00000880)
-#define IOP331_AAU_SAR25   (volatile u32 *)IOP331_REG_ADDR(0x00000888)
-#define IOP331_AAU_SAR26   (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
-#define IOP331_AAU_SAR27   (volatile u32 *)IOP331_REG_ADDR(0x00000890)
-#define IOP331_AAU_SAR28   (volatile u32 *)IOP331_REG_ADDR(0x00000894)
-#define IOP331_AAU_SAR29   (volatile u32 *)IOP331_REG_ADDR(0x00000898)
-#define IOP331_AAU_SAR30   (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
-#define IOP331_AAU_SAR31   (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
-#define IOP331_AAU_SAR32   (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
-#define IOP331_AAU_DAR     (volatile u32 *)IOP331_REG_ADDR(0x00000820)
-#define IOP331_AAU_ABCR    (volatile u32 *)IOP331_REG_ADDR(0x00000824)
-#define IOP331_AAU_ADCR    (volatile u32 *)IOP331_REG_ADDR(0x00000828)
-#define IOP331_AAU_EDCR0   (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
-#define IOP331_AAU_EDCR1   (volatile u32 *)IOP331_REG_ADDR(0x00000860)
-#define IOP331_AAU_EDCR2   (volatile u32 *)IOP331_REG_ADDR(0x00000884)
-#define IOP331_SPDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
-#define IOP331_PPDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
-/* SSP serial port unit 0x00001600 - 0x0000167F */
-/* I2C bus interface unit 0x00001680 - 0x000016FF */
-/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
-#define IOP331_ICR0       (volatile u32 *)IOP331_REG_ADDR(0x00001680)
-#define IOP331_ISR0       (volatile u32 *)IOP331_REG_ADDR(0x00001684)
-#define IOP331_ISAR0      (volatile u32 *)IOP331_REG_ADDR(0x00001688)
-#define IOP331_IDBR0      (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
-/* Reserved 0x00001690 */
-#define IOP331_IBMR0      (volatile u32 *)IOP331_REG_ADDR(0x00001694)
-/* Reserved 0x00001698 */
-/* Reserved 0x0000169C */
-#define IOP331_ICR1       (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
-#define IOP331_ISR1       (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
-#define IOP331_ISAR1      (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
-#define IOP331_IDBR1      (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
-#define IOP331_IBMR1      (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
-/* Reserved 0x000016B8 through 0x000016FF */
-/* 0x00001700 through 0x0000172C  UART 0 */
-/* Reserved 0x00001730 through 0x0000173F */
-/* 0x00001740 through 0x0000176C UART 1 */
-#define IOP331_UART0_PHYS  (IOP331_PHYS_MEM_BASE | 0x00001700)  /* UART #1 physical */
-#define IOP331_UART1_PHYS  (IOP331_PHYS_MEM_BASE | 0x00001740)  /* UART #2 physical */
-#define IOP331_UART0_VIRT  (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
-#define IOP331_UART1_VIRT  (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
-/* Reserved 0x00001770 through 0x0000177F */
-/* General Purpose I/O Registers */
-#define IOP331_GPOE       (volatile u32 *)IOP331_REG_ADDR(0x00001780)
-#define IOP331_GPID       (volatile u32 *)IOP331_REG_ADDR(0x00001784)
-#define IOP331_GPOD       (volatile u32 *)IOP331_REG_ADDR(0x00001788)
-/* Reserved 0x0000178c through 0x000019ff */
-#ifndef __ASSEMBLY__
-extern void iop331_map_io(void);
-extern void iop331_init_irq(void);
-extern void iop331_time_init(void);
-#endif
-#endif // _IOP331_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h
deleted file mode 100644
index b2c03f4c269c..000000000000
--- a/include/asm-arm/arch-iop3xx/irqs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/irqs.h
- *
- * Copyright:   (C) 2001-2003 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-/*
- * Chipset-specific bits
- */
-#ifdef CONFIG_ARCH_IOP321
-#include "iop321-irqs.h"
-#endif
-#ifdef CONFIG_ARCH_IOP331
-#include "iop331-irqs.h"
-#endif
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
deleted file mode 100644
index e43ebd984745..000000000000
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/memory.h
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-#include <asm/hardware.h>
-/*
- * Physical DRAM offset.
- */
-#ifndef CONFIG_ARCH_IOP331
-#define PHYS_OFFSET     UL(0xa0000000)
-#else
-#define PHYS_OFFSET     UL(0x00000000)
-#endif
-/*
- * Virtual view <-> PCI DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#if defined(CONFIG_ARCH_IOP321)
-#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
-#define __bus_to_virt(x)    (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
-#elif defined(CONFIG_ARCH_IOP331)
-#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
-#define __bus_to_virt(x)    (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
-#endif
-#endif
diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h
deleted file mode 100644
index af6ae8cd36c9..000000000000
--- a/include/asm-arm/arch-iop3xx/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/system.h
- *
- *  Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-static inline void arch_reset(char mode)
-{
-#ifdef CONFIG_ARCH_IOP321
-    *IOP321_PCSR = 0x30;
-#endif
-#ifdef CONFIG_ARCH_IOP331
-    *IOP331_PCSR = 0x30;
-#endif
-        if ( 1 && mode == 's') {
-                /* Jump into ROM at address 0 */
-                cpu_reset(0);
-        } else {
-                /* No on-chip reset capability */
-                cpu_reset(0);
-        }
-}
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h
deleted file mode 100644
index 14ca8d0f7b29..000000000000
--- a/include/asm-arm/arch-iop3xx/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/timex.h
- *
- * IOP3xx architecture timex specifications
- */
-#include <asm/hardware.h>
-#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
-#define CLOCK_TICK_RATE IOP321_TICK_RATE
-#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
-#define CLOCK_TICK_RATE IOP331_TICK_RATE
-#else
-#error "No IOP3xx timex information for this architecture"
-#endif
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
deleted file mode 100644
index fbdd5af644fe..000000000000
--- a/include/asm-arm/arch-iop3xx/uncompress.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-iop3xx/uncompress.h
- */
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-#include <asm/hardware.h>
-#ifdef CONFIG_ARCH_IOP321
-#define UTYPE unsigned char *
-#elif defined(CONFIG_ARCH_IOP331)
-#define UTYPE u32 *
-#else
-#error "Missing IOP3xx arch type def"
-#endif
-static volatile UTYPE uart_base;
-#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
-static inline void putc(char c)
-{
-        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
-                barrier();
-        *uart_base = c;
-}
-static inline void flush(void)
-{
-}
-static __inline__ void __arch_decomp_setup(unsigned long arch_id)
-{
-        if(machine_is_iq80321())
-                        uart_base = (volatile UTYPE)IQ80321_UART;
-                else if(machine_is_iq31244())
-                        uart_base = (volatile UTYPE)IQ31244_UART;
-                else if(machine_is_iq80331() || machine_is_iq80332())
-                        uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
-                else
-                        uart_base = (volatile UTYPE)0xfe800000;
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h
deleted file mode 100644
index 0f2f6847f93c..000000000000
--- a/include/asm-arm/arch-iop3xx/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop3xx/vmalloc.h
- */
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-//#define VMALLOC_END       (0xe8000000)
-/* increase usable physical RAM to ~992M per RMK */
-#define VMALLOC_END       (0xfe000000)
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 13aee17b0475..8d10a9187693 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -90,6 +90,11 @@ struct ixp4xx_i2c_pins {
 struct sys_timer;
 /*
+ * Frequency of clock used for primary clocksource
+ */
+extern unsigned long ixp4xx_timer_freq;
+/*
 * Functions used by platform-level setup code
 */
 extern void ixp4xx_map_io(void);
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index cd080d8384d9..d744d97c18a5 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -31,9 +31,9 @@
 static inline unsigned int __arch_getw(unsigned long a)
 {
        unsigned int value;
-        __asm__ __volatile__("ldr%?h    %0, [%1, #0]    @ getw"
+        __asm__ __volatile__("ldrh    %0, [%1, #0]    @ getw"
                : "=&r" (value)
-                : "r" (a));
+                : "r" (a) : "cc");
        return value;
 }
@@ -42,8 +42,8 @@ static inline unsigned int __arch_getw(unsigned long a)
 static inline void __arch_putw(unsigned int value, unsigned long a)
 {
-        __asm__ __volatile__("str%?h    %0, [%1, #0]    @ putw"
+        __asm__ __volatile__("strh    %0, [%1, #0]    @ putw"
-                : : "r" (value), "r" (a));
+                : : "r" (value), "r" (a) : "cc");
 }
 /*
diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h
index 0070f6d3b75c..9aee15d97145 100644
--- a/include/asm-arm/arch-omap/board-ams-delta.h
+++ b/include/asm-arm/arch-omap/board-ams-delta.h
@@ -50,9 +50,20 @@
 #define AMS_DELTA_LATCH2_NAND_NWE       0x0020
 #define AMS_DELTA_LATCH2_NAND_ALE       0x0040
 #define AMS_DELTA_LATCH2_NAND_CLE       0x0080
+#define AMD_DELTA_LATCH2_KEYBRD_PWR     0x0100
+#define AMD_DELTA_LATCH2_KEYBRD_DATA    0x0200
+#define AMD_DELTA_LATCH2_SCARD_RSTIN    0x0400
+#define AMD_DELTA_LATCH2_SCARD_CMDVCC   0x0800
 #define AMS_DELTA_LATCH2_MODEM_NRESET   0x1000
 #define AMS_DELTA_LATCH2_MODEM_CODEC    0x2000
+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA  0
+#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK   1
+#define AMS_DELTA_GPIO_PIN_MODEM_IRQ    2
+#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH  4
+#define AMS_DELTA_GPIO_PIN_SCARD_NOFF   6
+#define AMS_DELTA_GPIO_PIN_SCARD_IO     7
+#define AMS_DELTA_GPIO_PIN_CONFIG       11
 #define AMS_DELTA_GPIO_PIN_NAND_RB      12
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index f83003f5287b..fa6881049903 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -45,6 +45,7 @@ struct clk_functions {
        struct clk *    (*clk_get_parent)(struct clk *clk);
        void            (*clk_allow_idle)(struct clk *clk);
        void            (*clk_deny_idle)(struct clk *clk);
+        void            (*clk_disable_unused)(struct clk *clk);
 };
 extern unsigned int mpurate;
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 1b1b02307e77..d591d0585bba 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -331,6 +331,12 @@ enum omap_dma_color_mode {
        OMAP_DMA_TRANSPARENT_COPY
 };
+enum omap_dma_write_mode {
+        OMAP_DMA_WRITE_NON_POSTED = 0,
+        OMAP_DMA_WRITE_POSTED,
+        OMAP_DMA_WRITE_LAST_NON_POSTED
+};
 struct omap_dma_channel_params {
        int data_type;          /* data type 8,16,32 */
        int elem_count;         /* number of elements in a frame */
@@ -338,13 +344,13 @@ struct omap_dma_channel_params {
        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
        int src_amode;          /* constant , post increment, indexed , double indexed */
-        int src_start;          /* source address : physical */
+        unsigned long src_start;        /* source address : physical */
        int src_ei;             /* source element index */
        int src_fi;             /* source frame index */
        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
        int dst_amode;          /* constant , post increment, indexed , double indexed */
-        int dst_start;          /* source address : physical */
+        unsigned long dst_start;        /* source address : physical */
        int dst_ei;             /* source element index */
        int dst_fi;             /* source frame index */
@@ -356,7 +362,7 @@ struct omap_dma_channel_params {
 };
-extern void omap_set_dma_priority(int dst_port, int priority);
+extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
                            void (* callback)(int lch, u16 ch_status, void *data),
                            void *data, int *dma_ch);
@@ -371,6 +377,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
                                         int dma_trigger, int src_or_dst_synch);
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                    u32 color);
+extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                                    unsigned long src_start,
@@ -394,6 +401,9 @@ extern void omap_set_dma_params(int lch,
 extern void omap_dma_link_lch (int lch_head, int lch_queue);
 extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
+extern int omap_set_dma_callback(int lch,
+                        void (* callback)(int lch, u16 ch_status, void *data),
+                        void *data);
 extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
 extern int omap_get_dma_src_addr_counter(int lch);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index 7a289ff07404..b5f3a71b899d 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -52,6 +52,8 @@ int omap_dm_timer_init(void);
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 void omap_dm_timer_free(struct omap_dm_timer *timer);
+void omap_dm_timer_enable(struct omap_dm_timer *timer);
+void omap_dm_timer_disable(struct omap_dm_timer *timer);
 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index 1a0a5207822d..7c03ef6c14c4 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -85,7 +85,7 @@ extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
 extern u32 gpmc_cs_read_reg(int cs, int idx);
 extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
-extern unsigned long gpmc_cs_get_base_addr(int cs);
+extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
+extern void gpmc_cs_free(int cs);
 #endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 2542495d8a43..c5bb05a69b81 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -237,6 +237,7 @@
 #define INT_24XX_SDMA_IRQ1      13
 #define INT_24XX_SDMA_IRQ2      14
 #define INT_24XX_SDMA_IRQ3      15
+#define INT_24XX_CAM_IRQ        24
 #define INT_24XX_DSS_IRQ        25
 #define INT_24XX_GPIO_BANK1     29
 #define INT_24XX_GPIO_BANK2     30
@@ -261,6 +262,7 @@
 #define INT_24XX_UART1_IRQ      72
 #define INT_24XX_UART2_IRQ      73
 #define INT_24XX_UART3_IRQ      74
+#define INT_24XX_MMC_IRQ        83
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
 * 16 MPUIO lines */
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 679869c5e68f..828cc5c114e1 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -320,6 +320,17 @@ enum omap1xxx_index {
        P15_1610_UWIRE_CS3,
        N15_1610_UWIRE_CS1,
+        /* OMAP-1610 SPI */
+        U19_1610_SPIF_SCK,
+        U18_1610_SPIF_DIN,
+        P20_1610_SPIF_DIN,
+        W21_1610_SPIF_DOUT,
+        R18_1610_SPIF_DOUT,
+        N14_1610_SPIF_CS0,
+        N15_1610_SPIF_CS1,
+        T19_1610_SPIF_CS2,
+        P15_1610_SPIF_CS3,
        /* OMAP-1610 Flash */
        L3_1610_FLASH_CS2B_OE,
        M8_1610_FLASH_CS2B_WE,
@@ -461,6 +472,20 @@ enum omap24xx_index {
        K15_24XX_UART3_TX,
        K14_24XX_UART3_RX,
+        /* MMC/SDIO */
+        G19_24XX_MMC_CLKO,
+        H18_24XX_MMC_CMD,
+        F20_24XX_MMC_DAT0,
+        H14_24XX_MMC_DAT1,
+        E19_24XX_MMC_DAT2,
+        D19_24XX_MMC_DAT3,
+        F19_24XX_MMC_DAT_DIR0,
+        E20_24XX_MMC_DAT_DIR1,
+        F18_24XX_MMC_DAT_DIR2,
+        E18_24XX_MMC_DAT_DIR3,
+        G18_24XX_MMC_CMD_DIR,
+        H15_24XX_MMC_CLKI,
        /* Keypad GPIO*/
        T19_24XX_KBR0,
        R19_24XX_KBR1,
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 3661e465b0a5..7ac224836971 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -23,6 +23,39 @@
 #define MAX_DMA_ADDRESS         0x40000000
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
+/* We use `virtual` dma channels to hide the fact we have only a limited
+ * number of DMA channels, and not of all of them (dependant on the device)
+ * can be attached to any DMA source. We therefore let the DMA core handle
+ * the allocation of hardware channels to clients.
+*/
+enum dma_ch {
+        DMACH_XD0,
+        DMACH_XD1,
+        DMACH_SDI,
+        DMACH_SPI0,
+        DMACH_SPI1,
+        DMACH_UART0,
+        DMACH_UART1,
+        DMACH_UART2,
+        DMACH_TIMER,
+        DMACH_I2S_IN,
+        DMACH_I2S_OUT,
+        DMACH_PCM_IN,
+        DMACH_PCM_OUT,
+        DMACH_MIC_IN,
+        DMACH_USB_EP1,
+        DMACH_USB_EP2,
+        DMACH_USB_EP3,
+        DMACH_USB_EP4,
+        DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
+        DMACH_UART1_SRC2,
+        DMACH_UART2_SRC2,
+        DMACH_MAX,              /* the end entry */
+};
+#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
 /* we have 4 dma channels */
 #define S3C2410_DMA_CHANNELS        (4)
@@ -149,6 +182,8 @@ struct s3c2410_dma_stats {
        unsigned long           timeout_failed;
 };
+struct s3c2410_dma_map;
 /* struct s3c2410_dma_chan
 *
 * full state information for each DMA channel
@@ -174,6 +209,8 @@ struct s3c2410_dma_chan {
        unsigned long            load_timeout;
        unsigned int             flags;         /* channel flags */
+        struct s3c24xx_dma_map  *map;           /* channel hw maps */
        /* channel's hardware position and configuration */
        void __iomem            *regs;          /* channels registers */
        void __iomem            *addr_reg;      /* data address register */
@@ -283,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
 #define S3C2410_DMA_DCSRC       (0x18)
 #define S3C2410_DMA_DCDST       (0x1C)
 #define S3C2410_DMA_DMASKTRIG   (0x20)
+#define S3C2412_DMA_DMAREQSEL   (0x24)
 #define S3C2410_DISRCC_INC      (1<<0)
 #define S3C2410_DISRCC_APB      (1<<1)
@@ -349,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
 #define S3C2440_DCON_CH3_PCMOUT (6<<24)
 #endif
+#ifdef CONFIG_CPU_S3C2412
+#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
+#define S3C2412_DMAREQSEL_HW            (1)
+#define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
+#define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
+#define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
+#define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
+#define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
+#define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
+#define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
+#define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
+#define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
+#define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
+#define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
+#define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
+#define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
+#define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
+#define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
+#define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
+#define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
+#define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
+#define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
+#define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
+#endif
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 27ba0ac3fdd5..7895042d176b 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -160,6 +160,11 @@
 #define S3C2440_PA_CAMIF   (0x4F000000)
 #define S3C2440_SZ_CAMIF   SZ_1M
+/* AC97 */
+#define S3C2440_PA_AC97    (0x5B000000)
+#define S3C2440_SZ_AC97    SZ_1M
 /* ISA style IO, for each machine to sort out mappings for, if it
 * implements it. We reserve two 16M regions for ISA.
 */
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
index e2d406218ae5..a14164dfa525 100644
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ b/include/asm-arm/arch-s3c2410/osiris-map.h
@@ -18,22 +18,22 @@
 /* start peripherals off after the S3C2410 */
-#define OSIRIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x05000000))
+#define OSIRIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x04000000))
-#define OSIRIS_PA_CPLD          (S3C2410_CS1 | (3<<25))
+#define OSIRIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
 /* we put the CPLD registers next, to get them out of the way */
-#define OSIRIS_VA_CTRL1     OSIRIS_IOADDR(0x00000000)    /* 0x01300000 */
+#define OSIRIS_VA_CTRL1     OSIRIS_IOADDR(0x00000000)
 #define OSIRIS_PA_CTRL1     (OSIRIS_PA_CPLD)
-#define OSIRIS_VA_CTRL2     OSIRIS_IOADDR(0x00100000)    /* 0x01400000 */
+#define OSIRIS_VA_CTRL2     OSIRIS_IOADDR(0x00100000)
-#define OSIRIS_PA_CTRL2     (OSIRIS_PA_CPLD + (1<<24))
+#define OSIRIS_PA_CTRL2     (OSIRIS_PA_CPLD + (1<<23))
-#define OSIRIS_VA_CTRL3     OSIRIS_IOADDR(0x00200000)    /* 0x01500000 */
+#define OSIRIS_VA_CTRL3     OSIRIS_IOADDR(0x00200000)
-#define OSIRIS_PA_CTRL3     (OSIRIS_PA_CPLD + (2<<24))
+#define OSIRIS_PA_CTRL3     (OSIRIS_PA_CPLD + (2<<23))
-#define OSIRIS_VA_CTRL4     OSIRIS_IOADDR(0x00300000)    /* 0x01600000 */
+#define OSIRIS_VA_CTRL4     OSIRIS_IOADDR(0x00300000)
-#define OSIRIS_PA_CTRL4     (OSIRIS_PA_CPLD + (3<<24))
+#define OSIRIS_PA_CTRL4     (OSIRIS_PA_CPLD + (3<<23))
 #endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/arch-s3c2410/regs-ac97.h
new file mode 100644
index 000000000000..bdd6a4f93d7f
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-ac97.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
+ *
+ * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 AC97 Controller
+*/
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H __FILE__
+#define S3C_AC97_GLBCTRL        (0x00)
+#define S3C_AC97_GLBSTAT        (0x04)
+#define S3C_AC97_CODEC_CMD      (0x08)
+#define S3C_AC97_PCM_ADDR       (0x10)
+#define S3C_AC97_PCM_DATA       (0x18)
+#define S3C_AC97_MIC_DATA       (0x1C)
+#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b306d6e3135d..6d7881c8cfc8 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -63,6 +63,8 @@
 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
+/* LDCCON4 changes for STN mode on the S3C2412 */
 #define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
 #define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
 #define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
@@ -113,10 +115,38 @@
 #define S3C2410_LCDINT_FRSYNC   (1<<1)
 #define S3C2410_LCDINT_FICNT    (1<<0)
+/* s3c2442 extra stn registers */
+#define S3C2442_REDLUT          S3C2410_LCDREG(0x20)
+#define S3C2442_GREENLUT        S3C2410_LCDREG(0x24)
+#define S3C2442_BLUELUT         S3C2410_LCDREG(0x28)
+#define S3C2442_DITHMODE        S3C2410_LCDREG(0x20)
 #define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
 #define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
+/* S3C2412 registers */
+#define S3C2412_TPAL            S3C2410_LCDREG(0x20)
+#define S3C2412_LCDINTPND       S3C2410_LCDREG(0x24)
+#define S3C2412_LCDSRCPND       S3C2410_LCDREG(0x28)
+#define S3C2412_LCDINTMSK       S3C2410_LCDREG(0x2C)
+#define S3C2412_TCONSEL         S3C2410_LCDREG(0x30)
+#define S3C2412_LCDCON6         S3C2410_LCDREG(0x34)
+#define S3C2412_LCDCON7         S3C2410_LCDREG(0x38)
+#define S3C2412_LCDCON8         S3C2410_LCDREG(0x3C)
+#define S3C2412_LCDCON9         S3C2410_LCDREG(0x40)
+#define S3C2412_REDLUT(x)       S3C2410_LCDREG(0x44 + ((x)*4))
+#define S3C2412_GREENLUT(x)     S3C2410_LCDREG(0x60 + ((x)*4))
+#define S3C2412_BLUELUT(x)      S3C2410_LCDREG(0x98 + ((x)*4))
+#define S3C2412_FRCPAT(x)       S3C2410_LCDREG(0xB4 + ((x)*4))
 #endif /* ___ASM_ARCH_REGS_LCD_H */
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index 4b0ce3e7de9a..ea88aa6bfc78 100644
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -128,10 +128,10 @@ static inline int atomic_add_return(int i, atomic_t *v)
        unsigned long flags;
        int val;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        val = v->counter;
        v->counter = val += i;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
        return val;
 }
@@ -141,10 +141,10 @@ static inline int atomic_sub_return(int i, atomic_t *v)
        unsigned long flags;
        int val;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        val = v->counter;
        v->counter = val -= i;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
        return val;
 }
@@ -154,11 +154,11 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
        int ret;
        unsigned long flags;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        ret = v->counter;
        if (likely(ret == old))
                v->counter = new;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
        return ret;
 }
@@ -167,9 +167,9 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 {
        unsigned long flags;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        *addr &= ~mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
 }
 #endif /* __LINUX_ARM_ARCH__ */
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 0ac54b1a8bad..b41831b6432f 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -37,9 +37,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *
        p += bit >> 5;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        *p |= mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
 }
 static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
@@ -49,9 +49,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long
        p += bit >> 5;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        *p &= ~mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
 }
 static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
@@ -61,9 +61,9 @@ static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned lon
        p += bit >> 5;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        *p ^= mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
 }
 static inline int
@@ -75,10 +75,10 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
        p += bit >> 5;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        res = *p;
        *p = res | mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
        return res & mask;
 }
@@ -92,10 +92,10 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
        p += bit >> 5;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        res = *p;
        *p = res & ~mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
        return res & mask;
 }
@@ -109,10 +109,10 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
        p += bit >> 5;
-        local_irq_save(flags);
+        raw_local_irq_save(flags);
        res = *p;
        *p = res ^ mask;
-        local_irq_restore(flags);
+        raw_local_irq_restore(flags);
        return res & mask;
 }
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index e4a2569c636c..f0845646aacb 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -25,7 +25,7 @@
 #undef _CACHE
 #undef MULTI_CACHE
-#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
+#if defined(CONFIG_CPU_CACHE_V3)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
 # else
@@ -33,7 +33,7 @@
 # endif
 #endif
-#if defined(CONFIG_CPU_ARM720T)
+#if defined(CONFIG_CPU_CACHE_V4)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
 # else
@@ -54,7 +54,23 @@
 # endif
 #endif
-#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
+#if defined(CONFIG_CPU_ARM940T)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE arm940
+# endif
+#endif
+#if defined(CONFIG_CPU_ARM946E)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE arm946
+# endif
+#endif
+#if defined(CONFIG_CPU_CACHE_V4WB)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
 # else
diff --git a/include/asm-arm/flat.h b/include/asm-arm/flat.h
new file mode 100644
index 000000000000..966946478589
--- /dev/null
+++ b/include/asm-arm/flat.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-arm/flat.h -- uClinux flat-format executables
+ */
+#ifndef __ARM_FLAT_H__
+#define __ARM_FLAT_H__
+#define flat_stack_align(sp)                    /* nothing needed */
+#define flat_argvp_envp_on_stack()              1
+#define flat_old_ram_flag(flags)                (flags)
+#define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
+#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp)
+#define flat_put_addr_at_rp(rp, val, relval)    put_unaligned(val,rp)
+#define flat_get_relocate_addr(rel)             (rel)
+#endif /* __ARM_FLAT_H__ */
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
new file mode 100644
index 000000000000..1018a7486ab7
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -0,0 +1,301 @@
+/*
+ * include/asm-arm/hardware/iop3xx.h
+ *
+ * Intel IOP32X and IOP33X register definitions
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IOP3XX_H
+#define __IOP3XX_H
+/*
+ * IOP3XX GPIO handling
+ */
+#define GPIO_IN                 0
+#define GPIO_OUT                1
+#define GPIO_LOW                0
+#define GPIO_HIGH               1
+#define IOP3XX_GPIO_LINE(x)     (x)
+#ifndef __ASSEMBLY__
+extern void gpio_line_config(int line, int direction);
+extern int  gpio_line_get(int line);
+extern void gpio_line_set(int line, int value);
+#endif
+/*
+ * IOP3XX processor registers
+ */
+#define IOP3XX_PERIPHERAL_PHYS_BASE     0xffffe000
+#define IOP3XX_PERIPHERAL_VIRT_BASE     0xfeffe000
+#define IOP3XX_PERIPHERAL_SIZE          0x00002000
+#define IOP3XX_REG_ADDR(reg)            (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
+/* Address Translation Unit  */
+#define IOP3XX_ATUVID           (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
+#define IOP3XX_ATUDID           (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
+#define IOP3XX_ATUCMD           (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
+#define IOP3XX_ATUSR            (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
+#define IOP3XX_ATURID           (volatile u8  *)IOP3XX_REG_ADDR(0x0108)
+#define IOP3XX_ATUCCR           (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
+#define IOP3XX_ATUCLSR          (volatile u8  *)IOP3XX_REG_ADDR(0x010c)
+#define IOP3XX_ATULT            (volatile u8  *)IOP3XX_REG_ADDR(0x010d)
+#define IOP3XX_ATUHTR           (volatile u8  *)IOP3XX_REG_ADDR(0x010e)
+#define IOP3XX_ATUBIST          (volatile u8  *)IOP3XX_REG_ADDR(0x010f)
+#define IOP3XX_IABAR0           (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
+#define IOP3XX_IAUBAR0          (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
+#define IOP3XX_IABAR1           (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
+#define IOP3XX_IAUBAR1          (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
+#define IOP3XX_IABAR2           (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
+#define IOP3XX_IAUBAR2          (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
+#define IOP3XX_ASVIR            (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
+#define IOP3XX_ASIR             (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
+#define IOP3XX_ERBAR            (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
+#define IOP3XX_ATUILR           (volatile u8  *)IOP3XX_REG_ADDR(0x013c)
+#define IOP3XX_ATUIPR           (volatile u8  *)IOP3XX_REG_ADDR(0x013d)
+#define IOP3XX_ATUMGNT          (volatile u8  *)IOP3XX_REG_ADDR(0x013e)
+#define IOP3XX_ATUMLAT          (volatile u8  *)IOP3XX_REG_ADDR(0x013f)
+#define IOP3XX_IALR0            (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
+#define IOP3XX_IATVR0           (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
+#define IOP3XX_ERLR             (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
+#define IOP3XX_ERTVR            (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
+#define IOP3XX_IALR1            (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
+#define IOP3XX_IALR2            (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
+#define IOP3XX_IATVR2           (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
+#define IOP3XX_OIOWTVR          (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
+#define IOP3XX_OMWTVR0          (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
+#define IOP3XX_OUMWTVR0         (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
+#define IOP3XX_OMWTVR1          (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
+#define IOP3XX_OUMWTVR1         (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
+#define IOP3XX_OUDWTVR          (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
+#define IOP3XX_ATUCR            (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
+#define IOP3XX_PCSR             (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
+#define IOP3XX_ATUISR           (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
+#define IOP3XX_ATUIMR           (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
+#define IOP3XX_IABAR3           (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
+#define IOP3XX_IAUBAR3          (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
+#define IOP3XX_IALR3            (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
+#define IOP3XX_IATVR3           (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
+#define IOP3XX_OCCAR            (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
+#define IOP3XX_OCCDR            (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
+#define IOP3XX_PDSCR            (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
+#define IOP3XX_PMCAPID          (volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
+#define IOP3XX_PMNEXT           (volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
+#define IOP3XX_APMCR            (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
+#define IOP3XX_APMCSR           (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
+#define IOP3XX_PCIXCAPID        (volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
+#define IOP3XX_PCIXNEXT         (volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
+#define IOP3XX_PCIXCMD          (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
+#define IOP3XX_PCIXSR           (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
+#define IOP3XX_PCIIRSR          (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
+/* Messaging Unit  */
+#define IOP3XX_IMR0             (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
+#define IOP3XX_IMR1             (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
+#define IOP3XX_OMR0             (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
+#define IOP3XX_OMR1             (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
+#define IOP3XX_IDR              (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
+#define IOP3XX_IISR             (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
+#define IOP3XX_IIMR             (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
+#define IOP3XX_ODR              (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
+#define IOP3XX_OISR             (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
+#define IOP3XX_OIMR             (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
+#define IOP3XX_MUCR             (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
+#define IOP3XX_QBAR             (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
+#define IOP3XX_IFHPR            (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
+#define IOP3XX_IFTPR            (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
+#define IOP3XX_IPHPR            (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
+#define IOP3XX_IPTPR            (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
+#define IOP3XX_OFHPR            (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
+#define IOP3XX_OFTPR            (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
+#define IOP3XX_OPHPR            (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
+#define IOP3XX_OPTPR            (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
+#define IOP3XX_IAR              (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
+/* DMA Controller  */
+#define IOP3XX_DMA0_CCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
+#define IOP3XX_DMA0_CSR         (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
+#define IOP3XX_DMA0_DAR         (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
+#define IOP3XX_DMA0_NDAR        (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
+#define IOP3XX_DMA0_PADR        (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
+#define IOP3XX_DMA0_PUADR       (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
+#define IOP3XX_DMA0_LADR        (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
+#define IOP3XX_DMA0_BCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
+#define IOP3XX_DMA0_DCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
+#define IOP3XX_DMA1_CCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
+#define IOP3XX_DMA1_CSR         (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
+#define IOP3XX_DMA1_DAR         (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
+#define IOP3XX_DMA1_NDAR        (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
+#define IOP3XX_DMA1_PADR        (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
+#define IOP3XX_DMA1_PUADR       (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
+#define IOP3XX_DMA1_LADR        (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
+#define IOP3XX_DMA1_BCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
+#define IOP3XX_DMA1_DCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
+/* Peripheral bus interface  */
+#define IOP3XX_PBCR             (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
+#define IOP3XX_PBISR            (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
+#define IOP3XX_PBBAR0           (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
+#define IOP3XX_PBLR0            (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
+#define IOP3XX_PBBAR1           (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
+#define IOP3XX_PBLR1            (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
+#define IOP3XX_PBBAR2           (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
+#define IOP3XX_PBLR2            (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
+#define IOP3XX_PBBAR3           (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
+#define IOP3XX_PBLR3            (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
+#define IOP3XX_PBBAR4           (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
+#define IOP3XX_PBLR4            (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
+#define IOP3XX_PBBAR5           (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
+#define IOP3XX_PBLR5            (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
+#define IOP3XX_PMBR0            (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
+#define IOP3XX_PMBR1            (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
+#define IOP3XX_PMBR2            (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
+/* Peripheral performance monitoring unit  */
+#define IOP3XX_GTMR             (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
+#define IOP3XX_ESR              (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
+#define IOP3XX_EMISR            (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
+#define IOP3XX_GTSR             (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
+/* PERCR0 DOESN'T EXIST - index from 1! */
+#define IOP3XX_PERCR0           (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
+/* General Purpose I/O  */
+#define IOP3XX_GPOE             (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
+#define IOP3XX_GPID             (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
+#define IOP3XX_GPOD             (volatile u32 *)IOP3XX_GPIO_REG(0x000c)
+/* Timers  */
+#define IOP3XX_TU_TMR0          (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
+#define IOP3XX_TU_TMR1          (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
+#define IOP3XX_TU_TCR0          (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
+#define IOP3XX_TU_TCR1          (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
+#define IOP3XX_TU_TRR0          (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
+#define IOP3XX_TU_TRR1          (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
+#define IOP3XX_TU_TISR          (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
+#define IOP3XX_TU_WDTCR         (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
+#define IOP3XX_TMR_TC           0x01
+#define IOP3XX_TMR_EN           0x02
+#define IOP3XX_TMR_RELOAD       0x04
+#define IOP3XX_TMR_PRIVILEGED   0x09
+#define IOP3XX_TMR_RATIO_1_1    0x00
+#define IOP3XX_TMR_RATIO_4_1    0x10
+#define IOP3XX_TMR_RATIO_8_1    0x20
+#define IOP3XX_TMR_RATIO_16_1   0x30
+/* Application accelerator unit  */
+#define IOP3XX_AAU_ACR          (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
+#define IOP3XX_AAU_ASR          (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
+#define IOP3XX_AAU_ADAR         (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
+#define IOP3XX_AAU_ANDAR        (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
+#define IOP3XX_AAU_SAR1         (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
+#define IOP3XX_AAU_SAR2         (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
+#define IOP3XX_AAU_SAR3         (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
+#define IOP3XX_AAU_SAR4         (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
+#define IOP3XX_AAU_DAR          (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
+#define IOP3XX_AAU_ABCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
+#define IOP3XX_AAU_ADCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
+#define IOP3XX_AAU_SAR5         (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
+#define IOP3XX_AAU_SAR6         (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
+#define IOP3XX_AAU_SAR7         (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
+#define IOP3XX_AAU_SAR8         (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
+#define IOP3XX_AAU_EDCR0        (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
+#define IOP3XX_AAU_SAR9         (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
+#define IOP3XX_AAU_SAR10        (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
+#define IOP3XX_AAU_SAR11        (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
+#define IOP3XX_AAU_SAR12        (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
+#define IOP3XX_AAU_SAR13        (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
+#define IOP3XX_AAU_SAR14        (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
+#define IOP3XX_AAU_SAR15        (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
+#define IOP3XX_AAU_SAR16        (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
+#define IOP3XX_AAU_EDCR1        (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
+#define IOP3XX_AAU_SAR17        (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
+#define IOP3XX_AAU_SAR18        (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
+#define IOP3XX_AAU_SAR19        (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
+#define IOP3XX_AAU_SAR20        (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
+#define IOP3XX_AAU_SAR21        (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
+#define IOP3XX_AAU_SAR22        (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
+#define IOP3XX_AAU_SAR23        (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
+#define IOP3XX_AAU_SAR24        (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
+#define IOP3XX_AAU_EDCR2        (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
+#define IOP3XX_AAU_SAR25        (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
+#define IOP3XX_AAU_SAR26        (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
+#define IOP3XX_AAU_SAR27        (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
+#define IOP3XX_AAU_SAR28        (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
+#define IOP3XX_AAU_SAR29        (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
+#define IOP3XX_AAU_SAR30        (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
+#define IOP3XX_AAU_SAR31        (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
+#define IOP3XX_AAU_SAR32        (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
+/* I2C bus interface unit  */
+#define IOP3XX_ICR0             (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
+#define IOP3XX_ISR0             (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
+#define IOP3XX_ISAR0            (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
+#define IOP3XX_IDBR0            (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
+#define IOP3XX_IBMR0            (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
+#define IOP3XX_ICR1             (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
+#define IOP3XX_ISR1             (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
+#define IOP3XX_ISAR1            (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
+#define IOP3XX_IDBR1            (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
+#define IOP3XX_IBMR1            (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
+/*
+ * IOP3XX I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP3XX_PCI_MEM_WINDOW_SIZE      0x04000000
+#define IOP3XX_PCI_LOWER_MEM_PA         0x80000000
+#define IOP3XX_PCI_LOWER_MEM_BA         (*IOP3XX_OMWTVR0)
+#define IOP3XX_PCI_IO_WINDOW_SIZE       0x00010000
+#define IOP3XX_PCI_LOWER_IO_PA          0x90000000
+#define IOP3XX_PCI_LOWER_IO_VA          0xfe000000
+#define IOP3XX_PCI_LOWER_IO_BA          (*IOP3XX_OIOWTVR)
+#ifndef __ASSEMBLY__
+void iop3xx_map_io(void);
+void iop3xx_init_time(unsigned long);
+unsigned long iop3xx_gettimeoffset(void);
+extern struct platform_device iop3xx_i2c0_device;
+extern struct platform_device iop3xx_i2c1_device;
+extern inline void iop3xx_cp6_enable(void)
+{
+        u32 temp;
+        asm volatile (
+                "mrc    p15, 0, %0, c15, c1, 0\n\t"
+                "orr    %0, %0, #(1 << 6)\n\t"
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                "mrc    p15, 0, %0, c15, c1, 0\n\t"
+                "mov    %0, %0\n\t"
+                "sub    pc, pc, #4\n\t"
+                : "=r" (temp) );
+}
+extern inline void iop3xx_cp6_disable(void)
+{
+        u32 temp;
+        asm volatile (
+                "mrc    p15, 0, %0, c15, c1, 0\n\t"
+                "bic    %0, %0, #(1 << 6)\n\t"
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                "mrc    p15, 0, %0, c15, c1, 0\n\t"
+                "mov    %0, %0\n\t"
+                "sub    pc, pc, #4\n\t"
+                : "=r" (temp) );
+}
+#endif
+#endif
diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h
index 22dfb1737768..adab77780ed3 100644
--- a/include/asm-arm/hardware/locomo.h
+++ b/include/asm-arm/hardware/locomo.h
@@ -54,17 +54,18 @@
 #define LOCOMO_DAC_SDAOEB       0x01    /* SDA pin output data       */
 /* SPI interface */
-#define LOCOMO_SPIMD    0x60            /* SPI mode setting */
+#define LOCOMO_SPI      0x60
-#define LOCOMO_SPICT    0x64            /* SPI mode control */
+#define LOCOMO_SPIMD    0x00            /* SPI mode setting */
-#define LOCOMO_SPIST    0x68            /* SPI status */
+#define LOCOMO_SPICT    0x04            /* SPI mode control */
-#define LOCOMO_SPIIS    0x70            /* SPI interrupt status */
+#define LOCOMO_SPIST    0x08            /* SPI status */
-#define LOCOMO_SPIWE    0x74            /* SPI interrupt status write enable */
+#define LOCOMO_SPIIS    0x10            /* SPI interrupt status */
-#define LOCOMO_SPIIE    0x78            /* SPI interrupt enable */
+#define LOCOMO_SPIWE    0x14            /* SPI interrupt status write enable */
-#define LOCOMO_SPIIR    0x7c            /* SPI interrupt request */
+#define LOCOMO_SPIIE    0x18            /* SPI interrupt enable */
-#define LOCOMO_SPITD    0x80            /* SPI transfer data write */
+#define LOCOMO_SPIIR    0x1c            /* SPI interrupt request */
-#define LOCOMO_SPIRD    0x84            /* SPI receive data read */
+#define LOCOMO_SPITD    0x20            /* SPI transfer data write */
-#define LOCOMO_SPITS    0x88            /* SPI transfer data shift */
+#define LOCOMO_SPIRD    0x24            /* SPI receive data read */
-#define LOCOMO_SPIRS    0x8C            /* SPI receive data shift */
+#define LOCOMO_SPITS    0x28            /* SPI transfer data shift */
+#define LOCOMO_SPIRS    0x2C            /* SPI receive data shift */
 #define LOCOMO_SPI_TEND (1 << 3)        /* Transfer end bit */
 #define LOCOMO_SPI_OVRN (1 << 2)        /* Over Run bit */
 #define LOCOMO_SPI_RFW  (1 << 1)        /* write buffer bit */
@@ -161,6 +162,7 @@ extern struct bus_type locomo_bus_type;
 #define LOCOMO_DEVID_AUDIO      3
 #define LOCOMO_DEVID_LED        4
 #define LOCOMO_DEVID_UART       5
+#define LOCOMO_DEVID_SPI                6
 struct locomo_dev {
        struct device   dev;
@@ -197,10 +199,11 @@ int locomo_driver_register(struct locomo_driver *);
 void locomo_driver_unregister(struct locomo_driver *);
 /* GPIO control functions */
-void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir);
+void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
-unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits);
+int locomo_gpio_read_level(struct device *dev, unsigned int bits);
-unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits);
+int locomo_gpio_read_output(struct device *dev, unsigned int bits);
-void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set);
+void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
 /* M62332 control function */
 void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
diff --git a/include/asm-arm/hardware/sharpsl_pm.h b/include/asm-arm/hardware/sharpsl_pm.h
index ecf15b83956f..a836e76a14f7 100644
--- a/include/asm-arm/hardware/sharpsl_pm.h
+++ b/include/asm-arm/hardware/sharpsl_pm.h
@@ -25,6 +25,7 @@ struct sharpsl_charger_machinfo {
        void (*measure_temp)(int);
        void (*presuspend)(void);
        void (*postsuspend)(void);
+        void (*earlyresume)(void);
        unsigned long (*read_devdata)(int);
 #define SHARPSL_BATT_VOLT       1
 #define SHARPSL_BATT_TEMP       2
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index bf7b9dea30f1..8076a85c3675 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -280,6 +280,10 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 #define BIOVEC_MERGEABLE(vec1, vec2)    \
        ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
+#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
+extern int valid_phys_addr_range(unsigned long addr, size_t size);
+extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 /*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
diff --git a/include/asm-arm/irqflags.h b/include/asm-arm/irqflags.h
new file mode 100644
index 000000000000..6d09974e6646
--- /dev/null
+++ b/include/asm-arm/irqflags.h
@@ -0,0 +1,132 @@
+#ifndef __ASM_ARM_IRQFLAGS_H
+#define __ASM_ARM_IRQFLAGS_H
+#ifdef __KERNEL__
+#include <asm/ptrace.h>
+/*
+ * CPU interrupt mask handling.
+ */
+#if __LINUX_ARM_ARCH__ >= 6
+#define raw_local_irq_save(x)                                   \
+        ({                                                      \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_save\n"     \
+        "cpsid  i"                                              \
+        : "=r" (x) : : "memory", "cc");                         \
+        })
+#define raw_local_irq_enable()  __asm__("cpsie i        @ __sti" : : : "memory", "cc")
+#define raw_local_irq_disable() __asm__("cpsid i        @ __cli" : : : "memory", "cc")
+#define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
+#define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
+#else
+/*
+ * Save the current interrupt enable state & disable IRQs
+ */
+#define raw_local_irq_save(x)                                   \
+        ({                                                      \
+                unsigned long temp;                             \
+                (void) (&temp == &x);                           \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_save\n"     \
+"       orr     %1, %0, #128\n"                                 \
+"       msr     cpsr_c, %1"                                     \
+        : "=r" (x), "=r" (temp)                                 \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+        
+/*
+ * Enable IRQs
+ */
+#define raw_local_irq_enable()                                  \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_enable\n"   \
+"       bic     %0, %0, #128\n"                                 \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+/*
+ * Disable IRQs
+ */
+#define raw_local_irq_disable()                                 \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_disable\n"  \
+"       orr     %0, %0, #128\n"                                 \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+/*
+ * Enable FIQs
+ */
+#define local_fiq_enable()                                      \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ stf\n"                \
+"       bic     %0, %0, #64\n"                                  \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+/*
+ * Disable FIQs
+ */
+#define local_fiq_disable()                                     \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ clf\n"                \
+"       orr     %0, %0, #64\n"                                  \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+#endif
+/*
+ * Save the current interrupt enable state.
+ */
+#define raw_local_save_flags(x)                                 \
+        ({                                                      \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_save_flags"     \
+        : "=r" (x) : : "memory", "cc");                         \
+        })
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define raw_local_irq_restore(x)                                \
+        __asm__ __volatile__(                                   \
+        "msr    cpsr_c, %0              @ local_irq_restore\n"  \
+        :                                                       \
+        : "r" (x)                                               \
+        : "memory", "cc")
+#define raw_irqs_disabled_flags(flags)  \
+({                                      \
+        (int)((flags) & PSR_I_BIT);     \
+})
+#endif
+#endif
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index 923e0ca66200..24621c49a0c7 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -52,13 +52,9 @@ void pci_common_init(struct hw_pci *);
 /*
 * PCI controllers
 */
-extern int iop321_setup(int nr, struct pci_sys_data *);
+extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
+extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
-extern void iop321_init(void);
+extern void iop3xx_pci_preinit(void);
-extern int iop331_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
-extern void iop331_init(void);
 extern int dc21285_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index dee0bc336fe8..1eb93f5c0d6c 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -38,7 +38,9 @@ struct sys_timer {
        void                    (*init)(void);
        void                    (*suspend)(void);
        void                    (*resume)(void);
+#ifndef CONFIG_GENERIC_TIME
        unsigned long           (*offset)(void);
+#endif
 #ifdef CONFIG_NO_IDLE_HZ
        struct dyn_tick_timer   *dyn_tick;
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 02bd3ee935b0..7e85db77d99b 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -174,9 +174,6 @@ typedef unsigned long pgprot_t;
 #endif /* STRICT_MM_TYPECHECKS */
-/* the upper-most page table pointer */
-extern pmd_t *top_pmd;
 #endif /* CONFIG_MMU */
 #include <asm/memory.h>
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 4d10d319fa34..ed8cb5963e99 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -136,6 +136,13 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define USER_PTRS_PER_PGD       ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
 /*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT           20
+#define SECTION_SIZE            (1UL << SECTION_SHIFT)
+#define SECTION_MASK            (~(SECTION_SIZE-1))
+/*
 * ARMv6 supersection address mask and size definitions.
 */
 #define SUPERSECTION_SHIFT      24
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 1bde92cdaebd..ea7e54c319be 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -33,6 +33,14 @@
 #   define CPU_NAME cpu_arm6
 #  endif
 # endif
+# ifdef CONFIG_CPU_ARM7TDMI
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm7tdmi
+#  endif
+# endif
 # ifdef CONFIG_CPU_ARM710
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
@@ -49,6 +57,22 @@
 #   define CPU_NAME cpu_arm720
 #  endif
 # endif
+# ifdef CONFIG_CPU_ARM740T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm740
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM9TDMI
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm9tdmi
+#  endif
+# endif
 # ifdef CONFIG_CPU_ARM920T
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
@@ -81,6 +105,22 @@
 #   define CPU_NAME cpu_arm926
 #  endif
 # endif
+# ifdef CONFIG_CPU_ARM940T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm940
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM946E
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm946
+#  endif
+# endif
 # ifdef CONFIG_CPU_SA110
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h
index ea3ed2465233..aa4b5782f0c9 100644
--- a/include/asm-arm/setup.h
+++ b/include/asm-arm/setup.h
@@ -194,13 +194,15 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 # define NR_BANKS 8
 #endif
+struct membank {
+        unsigned long start;
+        unsigned long size;
+        int           node;
+};
 struct meminfo {
        int nr_banks;
-        struct {
+        struct membank bank[NR_BANKS];
-                unsigned long start;
-                unsigned long size;
-                int           node;
-        } bank[NR_BANKS];
 };
 /*
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 0947cbf9b69a..f05fbe31576c 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -46,6 +46,7 @@
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
+#ifdef CONFIG_CPU_CP15
 #define read_cpuid(reg)                                                 \
        ({                                                              \
                unsigned int __val;                                     \
@@ -55,6 +56,9 @@
                    : "cc");                                            \
                __val;                                                  \
        })
+#else
+#define read_cpuid(reg) (processor_id)
+#endif
 /*
 * This is used to ensure the compiler did actually allocate the register we
@@ -207,130 +211,7 @@ static inline void sched_cacheflush(void)
 {
 }
-/*
+#include <linux/irqflags.h>
- * CPU interrupt mask handling.
- */
-#if __LINUX_ARM_ARCH__ >= 6
-#define local_irq_save(x)                                       \
-        ({                                                      \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_save\n"     \
-        "cpsid  i"                                              \
-        : "=r" (x) : : "memory", "cc");                         \
-        })
-#define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
-#define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
-#define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
-#define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
-#else
-/*
- * Save the current interrupt enable state & disable IRQs
- */
-#define local_irq_save(x)                                       \
-        ({                                                      \
-                unsigned long temp;                             \
-                (void) (&temp == &x);                           \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_save\n"     \
-"       orr     %1, %0, #128\n"                                 \
-"       msr     cpsr_c, %1"                                     \
-        : "=r" (x), "=r" (temp)                                 \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
-        
-/*
- * Enable IRQs
- */
-#define local_irq_enable()                                      \
-        ({                                                      \
-                unsigned long temp;                             \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_enable\n"   \
-"       bic     %0, %0, #128\n"                                 \
-"       msr     cpsr_c, %0"                                     \
-        : "=r" (temp)                                           \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
-/*
- * Disable IRQs
- */
-#define local_irq_disable()                                     \
-        ({                                                      \
-                unsigned long temp;                             \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_disable\n"  \
-"       orr     %0, %0, #128\n"                                 \
-"       msr     cpsr_c, %0"                                     \
-        : "=r" (temp)                                           \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
-/*
- * Enable FIQs
- */
-#define local_fiq_enable()                                      \
-        ({                                                      \
-                unsigned long temp;                             \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ stf\n"                \
-"       bic     %0, %0, #64\n"                                  \
-"       msr     cpsr_c, %0"                                     \
-        : "=r" (temp)                                           \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
-/*
- * Disable FIQs
- */
-#define local_fiq_disable()                                     \
-        ({                                                      \
-                unsigned long temp;                             \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ clf\n"                \
-"       orr     %0, %0, #64\n"                                  \
-"       msr     cpsr_c, %0"                                     \
-        : "=r" (temp)                                           \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
-#endif
-/*
- * Save the current interrupt enable state.
- */
-#define local_save_flags(x)                                     \
-        ({                                                      \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_save_flags"     \
-        : "=r" (x) : : "memory", "cc");                         \
-        })
-/*
- * restore saved IRQ & FIQ state
- */
-#define local_irq_restore(x)                                    \
-        __asm__ __volatile__(                                   \
-        "msr    cpsr_c, %0              @ local_irq_restore\n"  \
-        :                                                       \
-        : "r" (x)                                               \
-        : "memory", "cc")
-#define irqs_disabled()                 \
-({                                      \
-        unsigned long flags;            \
-        local_save_flags(flags);        \
-        (int)(flags & PSR_I_BIT);       \
-})
 #ifdef CONFIG_SMP
@@ -405,17 +286,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 #error SMP is not supported on this platform
 #endif
        case 1:
-                local_irq_save(flags);
+                raw_local_irq_save(flags);
                ret = *(volatile unsigned char *)ptr;
                *(volatile unsigned char *)ptr = x;
-                local_irq_restore(flags);
+                raw_local_irq_restore(flags);
                break;
        case 4:
-                local_irq_save(flags);
+                raw_local_irq_save(flags);
                ret = *(volatile unsigned long *)ptr;
                *(volatile unsigned long *)ptr = x;
-                local_irq_restore(flags);
+                raw_local_irq_restore(flags);
                break;
 #else
        case 1:
diff --git a/include/asm-arm/timeofday.h b/include/asm-arm/timeofday.h
new file mode 100644
index 000000000000..27254bd5b94f
--- /dev/null
+++ b/include/asm-arm/timeofday.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_ARM_TIMEOFDAY_H
+#define _ASM_ARM_TIMEOFDAY_H
+#include <asm-generic/timeofday.h>
+#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index d97fc76189a5..cd10a0b5f8ae 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -247,16 +247,16 @@ static inline void local_flush_tlb_all(void)
        const unsigned int __tlb_flag = __cpu_tlb_flags;
        if (tlb_flag(TLB_WB))
-                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V3_FULL))
-                asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
+                asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
-                asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
+                asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
-                asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
+                asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
-                asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+                asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 }
 static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -266,25 +266,25 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
        const unsigned int __tlb_flag = __cpu_tlb_flags;
        if (tlb_flag(TLB_WB))
-                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
        if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
                if (tlb_flag(TLB_V3_FULL))
-                        asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
+                        asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
                if (tlb_flag(TLB_V4_U_FULL))
-                        asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
+                        asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
                if (tlb_flag(TLB_V4_D_FULL))
-                        asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
+                        asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
                if (tlb_flag(TLB_V4_I_FULL))
-                        asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+                        asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
        }
        if (tlb_flag(TLB_V6_U_ASID))
-                asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid));
+                asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
        if (tlb_flag(TLB_V6_D_ASID))
-                asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid));
+                asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
        if (tlb_flag(TLB_V6_I_ASID))
-                asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid));
+                asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
 }
 static inline void
@@ -296,27 +296,27 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
        uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
        if (tlb_flag(TLB_WB))
-                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));
        if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
                if (tlb_flag(TLB_V3_PAGE))
-                        asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr));
+                        asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
                if (tlb_flag(TLB_V4_U_PAGE))
-                        asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
+                        asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
                if (tlb_flag(TLB_V4_D_PAGE))
-                        asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
+                        asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
                if (tlb_flag(TLB_V4_I_PAGE))
-                        asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
+                        asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
                if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
-                        asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+                        asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
        }
        if (tlb_flag(TLB_V6_U_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
+                asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
        if (tlb_flag(TLB_V6_D_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
+                asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
        if (tlb_flag(TLB_V6_I_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
+                asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 }
 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -327,31 +327,31 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
        kaddr &= PAGE_MASK;
        if (tlb_flag(TLB_WB))
-                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V3_PAGE))
-                asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_V4_U_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_V4_D_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_V4_I_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
        if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
-                asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+                asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V6_U_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_V6_D_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_V6_I_PAGE))
-                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+                asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
        /* The ARM ARM states that the completion of a TLB maintenance
         * operation is only guaranteed by a DSB instruction
         */
        if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
-                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
 }
 /*
@@ -373,11 +373,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
        const unsigned int __tlb_flag = __cpu_tlb_flags;
        if (tlb_flag(TLB_DCLEAN))
-                asm("mcr%?      p15, 0, %0, c7, c10, 1  @ flush_pmd"
+                asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
-                        : : "r" (pmd));
+                        : : "r" (pmd) : "cc");
        if (tlb_flag(TLB_WB))
-                asm("mcr%?      p15, 0, %0, c7, c10, 4  @ flush_pmd"
+                asm("mcr        p15, 0, %0, c7, c10, 4  @ flush_pmd"
-                        : : "r" (zero));
+                        : : "r" (zero) : "cc");
 }
 static inline void clean_pmd_entry(pmd_t *pmd)
@@ -385,8 +385,8 @@ static inline void clean_pmd_entry(pmd_t *pmd)
        const unsigned int __tlb_flag = __cpu_tlb_flags;
        if (tlb_flag(TLB_DCLEAN))
-                asm("mcr%?      p15, 0, %0, c7, c10, 1  @ flush_pmd"
+                asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
-                        : : "r" (pmd));
+                        : : "r" (pmd) : "cc");
 }
 #undef tlb_flag
diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h
index 1b39c2f322c9..795b9e5b9e6a 100644
--- a/include/asm-arm/unaligned.h
+++ b/include/asm-arm/unaligned.h
@@ -3,7 +3,7 @@
 #include <asm/types.h>
-extern int __bug_unaligned_x(void *ptr);
+extern int __bug_unaligned_x(const void *ptr);
 /*
 * What is the most efficient way of loading/storing an unaligned value?
@@ -51,44 +51,32 @@ extern int __bug_unaligned_x(void *ptr);
 #define __get_unaligned_4_be(__p)                                       \
        (__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3])
-#define __get_unaligned_le(ptr)                                 \
+#define __get_unaligned_8_le(__p)                                       \
-        ({                                                      \
+        ((unsigned long long)__get_unaligned_4_le((__p+4)) << 32 |      \
-                __typeof__(*(ptr)) __v;                         \
+                __get_unaligned_4_le(__p))
-                __u8 *__p = (__u8 *)(ptr);                      \
-                switch (sizeof(*(ptr))) {                       \
+#define __get_unaligned_8_be(__p)                                       \
-                case 1: __v = *(ptr);                   break;  \
+        ((unsigned long long)__get_unaligned_4_be(__p) << 32 |          \
-                case 2: __v = __get_unaligned_2_le(__p);        break;  \
+                __get_unaligned_4_be((__p+4)))
-                case 4: __v = __get_unaligned_4_le(__p);        break;  \
-                case 8: {                                       \
+#define __get_unaligned_le(ptr)                                         \
-                                unsigned int __v1, __v2;        \
+        ({                                                              \
-                                __v2 = __get_unaligned_4_le((__p+4)); \
+                const __u8 *__p = (const __u8 *)(ptr);                  \
-                                __v1 = __get_unaligned_4_le(__p);       \
+                __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p,        \
-                                __v = ((unsigned long long)__v2 << 32 | __v1);  \
+                  __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_le(__p), \
-                        }                                       \
+                  __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_le(__p), \
-                        break;                                  \
+                  __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_le(__p), \
-                default: __v = __bug_unaligned_x(__p);  break;  \
+                    (void)__bug_unaligned_x(__p)))));                   \
-                }                                               \
-                __v;                                            \
        })
-#define __get_unaligned_be(ptr)                                 \
+#define __get_unaligned_be(ptr)                                         \
-        ({                                                      \
+        ({                                                              \
-                __typeof__(*(ptr)) __v;                         \
+                const __u8 *__p = (const __u8 *)(ptr);                  \
-                __u8 *__p = (__u8 *)(ptr);                      \
+                __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p,        \
-                switch (sizeof(*(ptr))) {                       \
+                  __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_be(__p), \
-                case 1: __v = *(ptr);                   break;  \
+                  __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_be(__p), \
-                case 2: __v = __get_unaligned_2_be(__p);        break;  \
+                  __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_be(__p), \
-                case 4: __v = __get_unaligned_4_be(__p);        break;  \
+                    (void)__bug_unaligned_x(__p)))));                   \
-                case 8: {                                       \
-                                unsigned int __v1, __v2;        \
-                                __v2 = __get_unaligned_4_be(__p); \
-                                __v1 = __get_unaligned_4_be((__p+4));   \
-                                __v = ((unsigned long long)__v2 << 32 | __v1);  \
-                        }                                       \
-                        break;                                  \
-                default: __v = __bug_unaligned_x(__p);  break;  \
-                }                                               \
-                __v;                                            \
        })
diff --git a/include/asm-s390/appldata.h b/include/asm-s390/appldata.h
index b1770703b706..79283dac8281 100644
--- a/include/asm-s390/appldata.h
+++ b/include/asm-s390/appldata.h
@@ -80,7 +80,7 @@ static inline int appldata_asm(struct appldata_product_id *id,
        parm_list.product_id_addr = (unsigned long) id;
        parm_list.buffer_addr = virt_to_phys(buffer);
        asm volatile(
-                "diag %1,%0,0xdc"
+                "       diag    %1,%0,0xdc"
                : "=d" (ry)
                : "d" (&parm_list), "m" (parm_list), "m" (*id)
                : "cc");
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
index 399bf02894dd..af20c7462485 100644
--- a/include/asm-s390/atomic.h
+++ b/include/asm-s390/atomic.h
@@ -30,20 +30,43 @@ typedef struct {
 #ifdef __KERNEL__
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
 #define __CS_LOOP(ptr, op_val, op_string) ({                            \
        typeof(ptr->counter) old_val, new_val;                          \
-        __asm__ __volatile__("   l     %0,0(%3)\n"                      \
+        asm volatile(                                                   \
-                             "0: lr    %1,%0\n"                         \
+                "       l       %0,%2\n"                                \
-                             op_string "  %1,%4\n"                      \
+                "0:     lr      %1,%0\n"                                \
-                             "   cs    %0,%1,0(%3)\n"                   \
+                op_string "     %1,%3\n"                                \
-                             "   jl    0b"                              \
+                "       cs      %0,%1,%2\n"                             \
-                             : "=&d" (old_val), "=&d" (new_val),        \
+                "       jl      0b"                                     \
-                               "=m" (((atomic_t *)(ptr))->counter)      \
+                : "=&d" (old_val), "=&d" (new_val),                     \
-                             : "a" (ptr), "d" (op_val),                 \
+                  "=Q" (((atomic_t *)(ptr))->counter)                   \
-                               "m" (((atomic_t *)(ptr))->counter)       \
+                : "d" (op_val),  "Q" (((atomic_t *)(ptr))->counter)     \
-                             : "cc", "memory" );                        \
+                : "cc", "memory");                                      \
        new_val;                                                        \
 })
+#else /* __GNUC__ */
+#define __CS_LOOP(ptr, op_val, op_string) ({                            \
+        typeof(ptr->counter) old_val, new_val;                          \
+        asm volatile(                                                   \
+                "       l       %0,0(%3)\n"                             \
+                "0:     lr      %1,%0\n"                                \
+                op_string "     %1,%4\n"                                \
+                "       cs      %0,%1,0(%3)\n"                          \
+                "       jl      0b"                                     \
+                : "=&d" (old_val), "=&d" (new_val),                     \
+                  "=m" (((atomic_t *)(ptr))->counter)                   \
+                : "a" (ptr), "d" (op_val),                              \
+                  "m" (((atomic_t *)(ptr))->counter)                    \
+                : "cc", "memory");                                      \
+        new_val;                                                        \
+})
+#endif /* __GNUC__ */
 #define atomic_read(v)          ((v)->counter)
 #define atomic_set(v,i)         (((v)->counter) = (i))
@@ -81,10 +104,19 @@ static __inline__ void atomic_set_mask(unsigned long mask, atomic_t * v)
 static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new)
 {
-        __asm__ __volatile__("  cs   %0,%3,0(%2)\n"
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-                             : "+d" (old), "=m" (v->counter)
+        asm volatile(
-                             : "a" (v), "d" (new), "m" (v->counter)
+                "       cs      %0,%2,%1"
-                             : "cc", "memory" );
+                : "+d" (old), "=Q" (v->counter)
+                : "d" (new), "Q" (v->counter)
+                : "cc", "memory");
+#else /* __GNUC__ */
+        asm volatile(
+                "       cs      %0,%3,0(%2)"
+                : "+d" (old), "=m" (v->counter)
+                : "a" (v), "d" (new), "m" (v->counter)
+                : "cc", "memory");
+#endif /* __GNUC__ */
        return old;
 }
@@ -113,20 +145,43 @@ typedef struct {
 } __attribute__ ((aligned (8))) atomic64_t;
 #define ATOMIC64_INIT(i)  { (i) }
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
 #define __CSG_LOOP(ptr, op_val, op_string) ({                           \
        typeof(ptr->counter) old_val, new_val;                          \
-        __asm__ __volatile__("   lg    %0,0(%3)\n"                      \
+        asm volatile(                                                   \
-                             "0: lgr   %1,%0\n"                         \
+                "       lg      %0,%2\n"                                \
-                             op_string "  %1,%4\n"                      \
+                "0:     lgr     %1,%0\n"                                \
-                             "   csg   %0,%1,0(%3)\n"                   \
+                op_string "     %1,%3\n"                                \
-                             "   jl    0b"                              \
+                "       csg     %0,%1,%2\n"                             \
-                             : "=&d" (old_val), "=&d" (new_val),        \
+                "       jl      0b"                                     \
-                               "=m" (((atomic_t *)(ptr))->counter)      \
+                : "=&d" (old_val), "=&d" (new_val),                     \
-                             : "a" (ptr), "d" (op_val),                 \
+                  "=Q" (((atomic_t *)(ptr))->counter)                   \
-                               "m" (((atomic_t *)(ptr))->counter)       \
+                : "d" (op_val), "Q" (((atomic_t *)(ptr))->counter)      \
-                             : "cc", "memory" );                        \
+                : "cc", "memory" );                                     \
        new_val;                                                        \
 })
+#else /* __GNUC__ */
+#define __CSG_LOOP(ptr, op_val, op_string) ({                           \
+        typeof(ptr->counter) old_val, new_val;                          \
+        asm volatile(                                                   \
+                "       lg      %0,0(%3)\n"                             \
+                "0:     lgr     %1,%0\n"                                \
+                op_string "     %1,%4\n"                                \
+                "       csg     %0,%1,0(%3)\n"                          \
+                "       jl      0b"                                     \
+                : "=&d" (old_val), "=&d" (new_val),                     \
+                  "=m" (((atomic_t *)(ptr))->counter)                   \
+                : "a" (ptr), "d" (op_val),                              \
+                  "m" (((atomic_t *)(ptr))->counter)                    \
+                : "cc", "memory" );                                     \
+        new_val;                                                        \
+})
+#endif /* __GNUC__ */
 #define atomic64_read(v)          ((v)->counter)
 #define atomic64_set(v,i)         (((v)->counter) = (i))
@@ -163,10 +218,19 @@ static __inline__ void atomic64_set_mask(unsigned long mask, atomic64_t * v)
 static __inline__ long long atomic64_cmpxchg(atomic64_t *v,
                                             long long old, long long new)
 {
-        __asm__ __volatile__("  csg  %0,%3,0(%2)\n"
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-                             : "+d" (old), "=m" (v->counter)
+        asm volatile(
-                             : "a" (v), "d" (new), "m" (v->counter)
+                "       csg     %0,%2,%1"
-                             : "cc", "memory" );
+                : "+d" (old), "=Q" (v->counter)
+                : "d" (new), "Q" (v->counter)
+                : "cc", "memory");
+#else /* __GNUC__ */
+        asm volatile(
+                "       csg     %0,%3,0(%2)"
+                : "+d" (old), "=m" (v->counter)
+                : "a" (v), "d" (new), "m" (v->counter)
+                : "cc", "memory");
+#endif /* __GNUC__ */
        return old;
 }
diff --git a/include/asm-s390/bitops.h b/include/asm-s390/bitops.h
index 0ddcdba79e4a..f79c9b792af1 100644
--- a/include/asm-s390/bitops.h
+++ b/include/asm-s390/bitops.h
@@ -67,16 +67,35 @@ extern const char _sb_findmap[];
 #define __BITOPS_AND            "nr"
 #define __BITOPS_XOR            "xr"
-#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string)         \
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-        __asm__ __volatile__("   l   %0,0(%4)\n"                        \
-                             "0: lr  %1,%0\n"                           \
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
-                             __op_string "  %1,%3\n"                    \
+        asm volatile(                                           \
-                             "   cs  %0,%1,0(%4)\n"                     \
+                "       l       %0,%2\n"                        \
-                             "   jl  0b"                                \
+                "0:     lr      %1,%0\n"                        \
-                             : "=&d" (__old), "=&d" (__new),            \
+                __op_string "   %1,%3\n"                        \
-                               "=m" (*(unsigned long *) __addr)         \
+                "       cs      %0,%1,%2\n"                     \
-                             : "d" (__val), "a" (__addr),               \
+                "       jl      0b"                             \
-                               "m" (*(unsigned long *) __addr) : "cc" );
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=Q" (*(unsigned long *) __addr)              \
+                : "d" (__val), "Q" (*(unsigned long *) __addr)  \
+                : "cc");
+#else /* __GNUC__ */
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
+        asm volatile(                                           \
+                "       l       %0,0(%4)\n"                     \
+                "0:     lr      %1,%0\n"                        \
+                __op_string "   %1,%3\n"                        \
+                "       cs      %0,%1,0(%4)\n"                  \
+                "       jl      0b"                             \
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=m" (*(unsigned long *) __addr)              \
+                : "d" (__val), "a" (__addr),                    \
+                  "m" (*(unsigned long *) __addr) : "cc");
+#endif /* __GNUC__ */
 #else /* __s390x__ */
@@ -86,21 +105,41 @@ extern const char _sb_findmap[];
 #define __BITOPS_AND            "ngr"
 #define __BITOPS_XOR            "xgr"
-#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string)         \
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-        __asm__ __volatile__("   lg  %0,0(%4)\n"                        \
-                             "0: lgr %1,%0\n"                           \
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
-                             __op_string "  %1,%3\n"                    \
+        asm volatile(                                           \
-                             "   csg %0,%1,0(%4)\n"                     \
+                "       lg      %0,%2\n"                        \
-                             "   jl  0b"                                \
+                "0:     lgr     %1,%0\n"                        \
-                             : "=&d" (__old), "=&d" (__new),            \
+                __op_string "   %1,%3\n"                        \
-                               "=m" (*(unsigned long *) __addr)         \
+                "       csg     %0,%1,%2\n"                     \
-                             : "d" (__val), "a" (__addr),               \
+                "       jl      0b"                             \
-                               "m" (*(unsigned long *) __addr) : "cc" );
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=Q" (*(unsigned long *) __addr)              \
+                : "d" (__val), "Q" (*(unsigned long *) __addr)  \
+                : "cc");
+#else /* __GNUC__ */
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
+        asm volatile(                                           \
+                "       lg      %0,0(%4)\n"                     \
+                "0:     lgr     %1,%0\n"                        \
+                __op_string "   %1,%3\n"                        \
+                "       csg     %0,%1,0(%4)\n"                  \
+                "       jl      0b"                             \
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=m" (*(unsigned long *) __addr)              \
+                : "d" (__val), "a" (__addr),                    \
+                  "m" (*(unsigned long *) __addr) : "cc");
+#endif /* __GNUC__ */
 #endif /* __s390x__ */
 #define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
-#define __BITOPS_BARRIER() __asm__ __volatile__ ( "" : : : "memory" )
+#define __BITOPS_BARRIER() asm volatile("" : : : "memory")
 #ifdef CONFIG_SMP
 /*
@@ -217,10 +256,10 @@ static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
        unsigned long addr;
        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
-        asm volatile("oc 0(1,%1),0(%2)"
+        asm volatile(
-                     : "=m" (*(char *) addr)
+                "       oc      0(1,%1),0(%2)"
-                     : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                : "=m" (*(char *) addr) : "a" (addr),
-                       "m" (*(char *) addr) : "cc" );
+                  "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
 }
 static inline void 
@@ -229,40 +268,7 @@ __constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
        unsigned long addr;
        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
-        switch (nr&7) {
+        *(unsigned char *) addr |= 1 << (nr & 7);
-        case 0:
-                asm volatile ("oi 0(%1),0x01" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 1:
-                asm volatile ("oi 0(%1),0x02" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 2:
-                asm volatile ("oi 0(%1),0x04" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 3:
-                asm volatile ("oi 0(%1),0x08" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 4:
-                asm volatile ("oi 0(%1),0x10" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 5:
-                asm volatile ("oi 0(%1),0x20" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 6:
-                asm volatile ("oi 0(%1),0x40" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 7:
-                asm volatile ("oi 0(%1),0x80" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        }
 }
 #define set_bit_simple(nr,addr) \
@@ -279,10 +285,10 @@ __clear_bit(unsigned long nr, volatile unsigned long *ptr)
        unsigned long addr;
        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
-        asm volatile("nc 0(1,%1),0(%2)"
+        asm volatile(
-                     : "=m" (*(char *) addr)
+                "       nc      0(1,%1),0(%2)"
-                     : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
+                : "=m" (*(char *) addr) : "a" (addr),
-                       "m" (*(char *) addr) : "cc" );
+                  "a" (_ni_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc");
 }
 static inline void 
@@ -291,40 +297,7 @@ __constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
        unsigned long addr;
        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
-        switch (nr&7) {
+        *(unsigned char *) addr &= ~(1 << (nr & 7));
-        case 0:
-                asm volatile ("ni 0(%1),0xFE" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 1:
-                asm volatile ("ni 0(%1),0xFD": "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 2:
-                asm volatile ("ni 0(%1),0xFB" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 3:
-                asm volatile ("ni 0(%1),0xF7" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 4:
-                asm volatile ("ni 0(%1),0xEF" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 5:
-                asm volatile ("ni 0(%1),0xDF" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 6:
-                asm volatile ("ni 0(%1),0xBF" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 7:
-                asm volatile ("ni 0(%1),0x7F" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        }
 }
 #define clear_bit_simple(nr,addr) \
@@ -340,10 +313,10 @@ static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
        unsigned long addr;
        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
-        asm volatile("xc 0(1,%1),0(%2)"
+        asm volatile(
-                     :  "=m" (*(char *) addr)
+                "       xc      0(1,%1),0(%2)"
-                     : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                :  "=m" (*(char *) addr) : "a" (addr),
-                       "m" (*(char *) addr) : "cc" );
+                   "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
 }
 static inline void 
@@ -352,40 +325,7 @@ __constant_change_bit(const unsigned long nr, volatile unsigned long *ptr)
        unsigned long addr;
        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
-        switch (nr&7) {
+        *(unsigned char *) addr ^= 1 << (nr & 7);
-        case 0:
-                asm volatile ("xi 0(%1),0x01" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 1:
-                asm volatile ("xi 0(%1),0x02" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 2:
-                asm volatile ("xi 0(%1),0x04" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 3:
-                asm volatile ("xi 0(%1),0x08" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 4:
-                asm volatile ("xi 0(%1),0x10" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 5:
-                asm volatile ("xi 0(%1),0x20" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 6:
-                asm volatile ("xi 0(%1),0x40" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        case 7:
-                asm volatile ("xi 0(%1),0x80" : "=m" (*(char *) addr)
-                              : "a" (addr), "m" (*(char *) addr) : "cc" );
-                break;
-        }
 }
 #define change_bit_simple(nr,addr) \
@@ -404,10 +344,11 @@ test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
        ch = *(unsigned char *) addr;
-        asm volatile("oc 0(1,%1),0(%2)"
+        asm volatile(
-                     : "=m" (*(char *) addr)
+                "       oc      0(1,%1),0(%2)"
-                     : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                : "=m" (*(char *) addr)
-                       "m" (*(char *) addr) : "cc", "memory" );
+                : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                  "m" (*(char *) addr) : "cc", "memory");
        return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_set_bit(X,Y)         test_and_set_bit_simple(X,Y)
@@ -423,10 +364,11 @@ test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
        ch = *(unsigned char *) addr;
-        asm volatile("nc 0(1,%1),0(%2)"
+        asm volatile(
-                     : "=m" (*(char *) addr)
+                "       nc      0(1,%1),0(%2)"
-                     : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
+                : "=m" (*(char *) addr)
-                       "m" (*(char *) addr) : "cc", "memory" );
+                : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
+                  "m" (*(char *) addr) : "cc", "memory");
        return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_clear_bit(X,Y)       test_and_clear_bit_simple(X,Y)
@@ -442,10 +384,11 @@ test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
        ch = *(unsigned char *) addr;
-        asm volatile("xc 0(1,%1),0(%2)"
+        asm volatile(
-                     : "=m" (*(char *) addr)
+                "       xc      0(1,%1),0(%2)"
-                     : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                : "=m" (*(char *) addr)
-                       "m" (*(char *) addr) : "cc", "memory" );
+                : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                  "m" (*(char *) addr) : "cc", "memory");
        return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_change_bit(X,Y)      test_and_change_bit_simple(X,Y)
@@ -557,35 +500,36 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size)
        if (!size)
                return 0;
-        __asm__("   lhi  %1,-1\n"
+        asm volatile(
-                "   lr   %2,%3\n"
+                "       lhi     %1,-1\n"
-                "   slr  %0,%0\n"
+                "       lr      %2,%3\n"
-                "   ahi  %2,31\n"
+                "       slr     %0,%0\n"
-                "   srl  %2,5\n"
+                "       ahi     %2,31\n"
-                "0: c    %1,0(%0,%4)\n"
+                "       srl     %2,5\n"
-                "   jne  1f\n"
+                "0:     c       %1,0(%0,%4)\n"
-                "   la   %0,4(%0)\n"
+                "       jne     1f\n"
-                "   brct %2,0b\n"
+                "       la      %0,4(%0)\n"
-                "   lr   %0,%3\n"
+                "       brct    %2,0b\n"
-                "   j    4f\n"
+                "       lr      %0,%3\n"
-                "1: l    %2,0(%0,%4)\n"
+                "       j       4f\n"
-                "   sll  %0,3\n"
+                "1:     l       %2,0(%0,%4)\n"
-                "   lhi  %1,0xff\n"
+                "       sll     %0,3\n"
-                "   tml  %2,0xffff\n"
+                "       lhi     %1,0xff\n"
-                "   jno  2f\n"
+                "       tml     %2,0xffff\n"
-                "   ahi  %0,16\n"
+                "       jno     2f\n"
-                "   srl  %2,16\n"
+                "       ahi     %0,16\n"
-                "2: tml  %2,0x00ff\n"
+                "       srl     %2,16\n"
-                "   jno  3f\n"
+                "2:     tml     %2,0x00ff\n"
-                "   ahi  %0,8\n"
+                "       jno     3f\n"
-                "   srl  %2,8\n"
+                "       ahi     %0,8\n"
-                "3: nr   %2,%1\n"
+                "       srl     %2,8\n"
-                "   ic   %2,0(%2,%5)\n"
+                "3:     nr      %2,%1\n"
-                "   alr  %0,%2\n"
+                "       ic      %2,0(%2,%5)\n"
-                "4:"
+                "       alr     %0,%2\n"
-                : "=&a" (res), "=&d" (cmp), "=&a" (count)
+                "4:"
-                : "a" (size), "a" (addr), "a" (&_zb_findmap),
+                : "=&a" (res), "=&d" (cmp), "=&a" (count)
-                  "m" (*(addrtype *) addr) : "cc" );
+                : "a" (size), "a" (addr), "a" (&_zb_findmap),
+                  "m" (*(addrtype *) addr) : "cc");
        return (res < size) ? res : size;
 }
@@ -598,35 +542,36 @@ find_first_bit(const unsigned long * addr, unsigned long size)
        if (!size)
                return 0;
-        __asm__("   slr  %1,%1\n"
+        asm volatile(
-                "   lr   %2,%3\n"
+                "       slr     %1,%1\n"
-                "   slr  %0,%0\n"
+                "       lr      %2,%3\n"
-                "   ahi  %2,31\n"
+                "       slr     %0,%0\n"
-                "   srl  %2,5\n"
+                "       ahi     %2,31\n"
-                "0: c    %1,0(%0,%4)\n"
+                "       srl     %2,5\n"
-                "   jne  1f\n"
+                "0:     c       %1,0(%0,%4)\n"
-                "   la   %0,4(%0)\n"
+                "       jne     1f\n"
-                "   brct %2,0b\n"
+                "       la      %0,4(%0)\n"
-                "   lr   %0,%3\n"
+                "       brct    %2,0b\n"
-                "   j    4f\n"
+                "       lr      %0,%3\n"
-                "1: l    %2,0(%0,%4)\n"
+                "       j       4f\n"
-                "   sll  %0,3\n"
+                "1:     l       %2,0(%0,%4)\n"
-                "   lhi  %1,0xff\n"
+                "       sll     %0,3\n"
-                "   tml  %2,0xffff\n"
+                "       lhi     %1,0xff\n"
-                "   jnz  2f\n"
+                "       tml     %2,0xffff\n"
-                "   ahi  %0,16\n"
+                "       jnz     2f\n"
-                "   srl  %2,16\n"
+                "       ahi     %0,16\n"
-                "2: tml  %2,0x00ff\n"
+                "       srl     %2,16\n"
-                "   jnz  3f\n"
+                "2:     tml     %2,0x00ff\n"
-                "   ahi  %0,8\n"
+                "       jnz     3f\n"
-                "   srl  %2,8\n"
+                "       ahi     %0,8\n"
-                "3: nr   %2,%1\n"
+                "       srl     %2,8\n"
-                "   ic   %2,0(%2,%5)\n"
+                "3:     nr      %2,%1\n"
-                "   alr  %0,%2\n"
+                "       ic      %2,0(%2,%5)\n"
-                "4:"
+                "       alr     %0,%2\n"
-                : "=&a" (res), "=&d" (cmp), "=&a" (count)
+                "4:"
-                : "a" (size), "a" (addr), "a" (&_sb_findmap),
+                : "=&a" (res), "=&d" (cmp), "=&a" (count)
-                  "m" (*(addrtype *) addr) : "cc" );
+                : "a" (size), "a" (addr), "a" (&_sb_findmap),
+                  "m" (*(addrtype *) addr) : "cc");
        return (res < size) ? res : size;
 }
@@ -640,39 +585,40 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size)
        if (!size)
                return 0;
-        __asm__("   lghi  %1,-1\n"
+        asm volatile(
-                "   lgr   %2,%3\n"
+                "       lghi    %1,-1\n"
-                "   slgr  %0,%0\n"
+                "       lgr     %2,%3\n"
-                "   aghi  %2,63\n"
+                "       slgr    %0,%0\n"
-                "   srlg  %2,%2,6\n"
+                "       aghi    %2,63\n"
-                "0: cg    %1,0(%0,%4)\n"
+                "       srlg    %2,%2,6\n"
-                "   jne   1f\n"
+                "0:     cg      %1,0(%0,%4)\n"
-                "   la    %0,8(%0)\n"
+                "       jne     1f\n"
-                "   brct  %2,0b\n"
+                "       la      %0,8(%0)\n"
-                "   lgr   %0,%3\n"
+                "       brct    %2,0b\n"
-                "   j     5f\n"
+                "       lgr     %0,%3\n"
-                "1: lg    %2,0(%0,%4)\n"
+                "       j       5f\n"
-                "   sllg  %0,%0,3\n"
+                "1:     lg      %2,0(%0,%4)\n"
-                "   clr   %2,%1\n"
+                "       sllg    %0,%0,3\n"
-                "   jne   2f\n"
+                "       clr     %2,%1\n"
-                "   aghi  %0,32\n"
+                "       jne     2f\n"
-                "   srlg  %2,%2,32\n"
+                "       aghi    %0,32\n"
-                "2: lghi  %1,0xff\n"
+                "       srlg    %2,%2,32\n"
-                "   tmll  %2,0xffff\n"
+                "2:     lghi    %1,0xff\n"
-                "   jno   3f\n"
+                "       tmll    %2,0xffff\n"
-                "   aghi  %0,16\n"
+                "       jno     3f\n"
-                "   srl   %2,16\n"
+                "       aghi    %0,16\n"
-                "3: tmll  %2,0x00ff\n"
+                "       srl     %2,16\n"
-                "   jno   4f\n"
+                "3:     tmll    %2,0x00ff\n"
-                "   aghi  %0,8\n"
+                "       jno     4f\n"
-                "   srl   %2,8\n"
+                "       aghi    %0,8\n"
-                "4: ngr   %2,%1\n"
+                "       srl     %2,8\n"
-                "   ic    %2,0(%2,%5)\n"
+                "4:     ngr     %2,%1\n"
-                "   algr  %0,%2\n"
+                "       ic      %2,0(%2,%5)\n"
-                "5:"
+                "       algr    %0,%2\n"
-                : "=&a" (res), "=&d" (cmp), "=&a" (count)
+                "5:"
+                : "=&a" (res), "=&d" (cmp), "=&a" (count)
                : "a" (size), "a" (addr), "a" (&_zb_findmap),
-                  "m" (*(addrtype *) addr) : "cc" );
+                  "m" (*(addrtype *) addr) : "cc");
        return (res < size) ? res : size;
 }
@@ -684,39 +630,40 @@ find_first_bit(const unsigned long * addr, unsigned long size)
        if (!size)
                return 0;
-        __asm__("   slgr  %1,%1\n"
+        asm volatile(
-                "   lgr   %2,%3\n"
+                "       slgr    %1,%1\n"
-                "   slgr  %0,%0\n"
+                "       lgr     %2,%3\n"
-                "   aghi  %2,63\n"
+                "       slgr    %0,%0\n"
-                "   srlg  %2,%2,6\n"
+                "       aghi    %2,63\n"
-                "0: cg    %1,0(%0,%4)\n"
+                "       srlg    %2,%2,6\n"
-                "   jne   1f\n"
+                "0:     cg      %1,0(%0,%4)\n"
-                "   aghi  %0,8\n"
+                "       jne     1f\n"
-                "   brct  %2,0b\n"
+                "       aghi    %0,8\n"
-                "   lgr   %0,%3\n"
+                "       brct    %2,0b\n"
-                "   j     5f\n"
+                "       lgr     %0,%3\n"
-                "1: lg    %2,0(%0,%4)\n"
+                "       j       5f\n"
-                "   sllg  %0,%0,3\n"
+                "1:     lg      %2,0(%0,%4)\n"
-                "   clr   %2,%1\n"
+                "       sllg    %0,%0,3\n"
-                "   jne   2f\n"
+                "       clr     %2,%1\n"
-                "   aghi  %0,32\n"
+                "       jne     2f\n"
-                "   srlg  %2,%2,32\n"
+                "       aghi    %0,32\n"
-                "2: lghi  %1,0xff\n"
+                "       srlg    %2,%2,32\n"
-                "   tmll  %2,0xffff\n"
+                "2:     lghi    %1,0xff\n"
-                "   jnz   3f\n"
+                "       tmll    %2,0xffff\n"
-                "   aghi  %0,16\n"
+                "       jnz     3f\n"
-                "   srl   %2,16\n"
+                "       aghi    %0,16\n"
-                "3: tmll  %2,0x00ff\n"
+                "       srl     %2,16\n"
-                "   jnz   4f\n"
+                "3:     tmll    %2,0x00ff\n"
-                "   aghi  %0,8\n"
+                "       jnz     4f\n"
-                "   srl   %2,8\n"
+                "       aghi    %0,8\n"
-                "4: ngr   %2,%1\n"
+                "       srl     %2,8\n"
-                "   ic    %2,0(%2,%5)\n"
+                "4:     ngr     %2,%1\n"
-                "   algr  %0,%2\n"
+                "       ic      %2,0(%2,%5)\n"
-                "5:"
+                "       algr    %0,%2\n"
-                : "=&a" (res), "=&d" (cmp), "=&a" (count)
+                "5:"
+                : "=&a" (res), "=&d" (cmp), "=&a" (count)
                : "a" (size), "a" (addr), "a" (&_sb_findmap),
-                  "m" (*(addrtype *) addr) : "cc" );
+                  "m" (*(addrtype *) addr) : "cc");
        return (res < size) ? res : size;
 }
@@ -832,36 +779,37 @@ ext2_find_first_zero_bit(void *vaddr, unsigned int size)
        if (!size)
                return 0;
-        __asm__("   lhi  %1,-1\n"
+        asm volatile(
-                "   lr   %2,%3\n"
+                "       lhi     %1,-1\n"
-                "   ahi  %2,31\n"
+                "       lr      %2,%3\n"
-                "   srl  %2,5\n"
+                "       ahi     %2,31\n"
-                "   slr  %0,%0\n"
+                "       srl     %2,5\n"
-                "0: cl   %1,0(%0,%4)\n"
+                "       slr     %0,%0\n"
-                "   jne  1f\n"
+                "0:     cl      %1,0(%0,%4)\n"
-                "   ahi  %0,4\n"
+                "       jne     1f\n"
-                "   brct %2,0b\n"
+                "       ahi     %0,4\n"
-                "   lr   %0,%3\n"
+                "       brct    %2,0b\n"
-                "   j    4f\n"
+                "       lr      %0,%3\n"
-                "1: l    %2,0(%0,%4)\n"
+                "       j       4f\n"
-                "   sll  %0,3\n"
+                "1:     l       %2,0(%0,%4)\n"
-                "   ahi  %0,24\n"
+                "       sll     %0,3\n"
-                "   lhi  %1,0xff\n"
+                "       ahi     %0,24\n"
-                "   tmh  %2,0xffff\n"
+                "       lhi     %1,0xff\n"
-                "   jo   2f\n"
+                "       tmh     %2,0xffff\n"
-                "   ahi  %0,-16\n"
+                "       jo      2f\n"
-                "   srl  %2,16\n"
+                "       ahi     %0,-16\n"
-                "2: tml  %2,0xff00\n"
+                "       srl     %2,16\n"
-                "   jo   3f\n"
+                "2:     tml     %2,0xff00\n"
-                "   ahi  %0,-8\n"
+                "       jo      3f\n"
-                "   srl  %2,8\n"
+                "       ahi     %0,-8\n"
-                "3: nr   %2,%1\n"
+                "       srl     %2,8\n"
-                "   ic   %2,0(%2,%5)\n"
+                "3:     nr      %2,%1\n"
-                "   alr  %0,%2\n"
+                "       ic      %2,0(%2,%5)\n"
-                "4:"
+                "       alr     %0,%2\n"
-                : "=&a" (res), "=&d" (cmp), "=&a" (count)
+                "4:"
-                : "a" (size), "a" (vaddr), "a" (&_zb_findmap),
+                : "=&a" (res), "=&d" (cmp), "=&a" (count)
-                  "m" (*(addrtype *) vaddr) : "cc" );
+                : "a" (size), "a" (vaddr), "a" (&_zb_findmap),
+                  "m" (*(addrtype *) vaddr) : "cc");
        return (res < size) ? res : size;
 }
@@ -875,39 +823,40 @@ ext2_find_first_zero_bit(void *vaddr, unsigned long size)
        if (!size)
                return 0;
-        __asm__("   lghi  %1,-1\n"
+        asm volatile(
-                "   lgr   %2,%3\n"
+                "       lghi    %1,-1\n"
-                "   aghi  %2,63\n"
+                "       lgr     %2,%3\n"
-                "   srlg  %2,%2,6\n"
+                "       aghi    %2,63\n"
-                "   slgr  %0,%0\n"
+                "       srlg    %2,%2,6\n"
-                "0: clg   %1,0(%0,%4)\n"
+                "       slgr    %0,%0\n"
-                "   jne   1f\n"
+                "0:     clg     %1,0(%0,%4)\n"
-                "   aghi  %0,8\n"
+                "       jne     1f\n"
-                "   brct  %2,0b\n"
+                "       aghi    %0,8\n"
-                "   lgr   %0,%3\n"
+                "       brct    %2,0b\n"
-                "   j     5f\n"
+                "       lgr     %0,%3\n"
-                "1: cl    %1,0(%0,%4)\n"
+                "       j       5f\n"
-                "   jne   2f\n"
+                "1:     cl      %1,0(%0,%4)\n"
-                "   aghi  %0,4\n"
+                "       jne     2f\n"
-                "2: l     %2,0(%0,%4)\n"
+                "       aghi    %0,4\n"
-                "   sllg  %0,%0,3\n"
+                "2:     l       %2,0(%0,%4)\n"
-                "   aghi  %0,24\n"
+                "       sllg    %0,%0,3\n"
-                "   lghi  %1,0xff\n"
+                "       aghi    %0,24\n"
-                "   tmlh  %2,0xffff\n"
+                "       lghi    %1,0xff\n"
-                "   jo    3f\n"
+                "       tmlh    %2,0xffff\n"
-                "   aghi  %0,-16\n"
+                "       jo      3f\n"
-                "   srl   %2,16\n"
+                "       aghi    %0,-16\n"
-                "3: tmll  %2,0xff00\n"
+                "       srl     %2,16\n"
-                "   jo    4f\n"
+                "3:     tmll    %2,0xff00\n"
-                "   aghi  %0,-8\n"
+                "       jo      4f\n"
-                "   srl   %2,8\n"
+                "       aghi    %0,-8\n"
-                "4: ngr   %2,%1\n"
+                "       srl     %2,8\n"
-                "   ic    %2,0(%2,%5)\n"
+                "4:     ngr     %2,%1\n"
-                "   algr  %0,%2\n"
+                "       ic      %2,0(%2,%5)\n"
-                "5:"
+                "       algr    %0,%2\n"
-                : "=&a" (res), "=&d" (cmp), "=&a" (count)
+                "5:"
+                : "=&a" (res), "=&d" (cmp), "=&a" (count)
                : "a" (size), "a" (vaddr), "a" (&_zb_findmap),
-                  "m" (*(addrtype *) vaddr) : "cc" );
+                  "m" (*(addrtype *) vaddr) : "cc");
        return (res < size) ? res : size;
 }
@@ -927,13 +876,16 @@ ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset)
        p = addr + offset / __BITOPS_WORDSIZE;
        if (bit) {
 #ifndef __s390x__
-                asm("   ic   %0,0(%1)\n"
+                asm volatile(
-                    "   icm  %0,2,1(%1)\n"
+                        "       ic      %0,0(%1)\n"
-                    "   icm  %0,4,2(%1)\n"
+                        "       icm     %0,2,1(%1)\n"
-                    "   icm  %0,8,3(%1)"
+                        "       icm     %0,4,2(%1)\n"
-                    : "=&a" (word) : "a" (p), "m" (*p) : "cc" );
+                        "       icm     %0,8,3(%1)"
+                        : "=&a" (word) : "a" (p), "m" (*p) : "cc");
 #else
-                asm("   lrvg %0,%1" : "=a" (word) : "m" (*p) );
+                asm volatile(
+                        "       lrvg    %0,%1"
+                        : "=a" (word) : "m" (*p) );
 #endif
                /*
                 * s390 version of ffz returns __BITOPS_WORDSIZE
diff --git a/include/asm-s390/byteorder.h b/include/asm-s390/byteorder.h
index 2cc35a0e188e..1fe2492baa8d 100644
--- a/include/asm-s390/byteorder.h
+++ b/include/asm-s390/byteorder.h
@@ -14,60 +14,54 @@
 #ifdef __GNUC__
 #ifdef __s390x__
-static __inline__ __u64 ___arch__swab64p(const __u64 *x)
+static inline __u64 ___arch__swab64p(const __u64 *x)
 {
        __u64 result;
-        __asm__ __volatile__ (
+        asm volatile("lrvg %0,%1" : "=d" (result) : "m" (*x));
-                "   lrvg %0,%1"
-                : "=d" (result) : "m" (*x) );
        return result;
 }
-static __inline__ __u64 ___arch__swab64(__u64 x)
+static inline __u64 ___arch__swab64(__u64 x)
 {
        __u64 result;
-        __asm__ __volatile__ (
+        asm volatile("lrvgr %0,%1" : "=d" (result) : "d" (x));
-                "   lrvgr %0,%1"
-                : "=d" (result) : "d" (x) );
        return result;
 }
-static __inline__ void ___arch__swab64s(__u64 *x)
+static inline void ___arch__swab64s(__u64 *x)
 {
        *x = ___arch__swab64p(x);
 }
 #endif /* __s390x__ */
-static __inline__ __u32 ___arch__swab32p(const __u32 *x)
+static inline __u32 ___arch__swab32p(const __u32 *x)
 {
        __u32 result;
        
-        __asm__ __volatile__ (
+        asm volatile(
 #ifndef __s390x__
-                "        icm   %0,8,3(%1)\n"
+                "       icm     %0,8,3(%1)\n"
-                "        icm   %0,4,2(%1)\n"
+                "       icm     %0,4,2(%1)\n"
-                "        icm   %0,2,1(%1)\n"
+                "       icm     %0,2,1(%1)\n"
-                "        ic    %0,0(%1)"
+                "       ic      %0,0(%1)"
-                : "=&d" (result) : "a" (x), "m" (*x) : "cc" );
+                : "=&d" (result) : "a" (x), "m" (*x) : "cc");
 #else /* __s390x__ */
-                "   lrv  %0,%1"
+                "       lrv     %0,%1"
-                : "=d" (result) : "m" (*x) );
+                : "=d" (result) : "m" (*x));
 #endif /* __s390x__ */
        return result;
 }
-static __inline__ __u32 ___arch__swab32(__u32 x)
+static inline __u32 ___arch__swab32(__u32 x)
 {
 #ifndef __s390x__
        return ___arch__swab32p(&x);
 #else /* __s390x__ */
        __u32 result;
        
-        __asm__ __volatile__ (
+        asm volatile("lrvr  %0,%1" : "=d" (result) : "d" (x));
-                "   lrvr  %0,%1"
-                : "=d" (result) : "d" (x) );
        return result;
 #endif /* __s390x__ */
 }
@@ -81,14 +75,14 @@ static __inline__ __u16 ___arch__swab16p(const __u16 *x)
 {
        __u16 result;
        
-        __asm__ __volatile__ (
+        asm volatile(
 #ifndef __s390x__
-                "        icm   %0,2,1(%1)\n"
+                "       icm     %0,2,1(%1)\n"
-                "        ic    %0,0(%1)\n"
+                "       ic      %0,0(%1)\n"
-                : "=&d" (result) : "a" (x), "m" (*x) : "cc" );
+                : "=&d" (result) : "a" (x), "m" (*x) : "cc");
 #else /* __s390x__ */
-                "   lrvh %0,%1"
+                "       lrvh    %0,%1"
-                : "=d" (result) : "m" (*x) );
+                : "=d" (result) : "m" (*x));
 #endif /* __s390x__ */
        return result;
 }
diff --git a/include/asm-s390/checksum.h b/include/asm-s390/checksum.h
index 471f2af2b16a..37c362d89fad 100644
--- a/include/asm-s390/checksum.h
+++ b/include/asm-s390/checksum.h
@@ -30,57 +30,13 @@
 static inline unsigned int
 csum_partial(const unsigned char * buff, int len, unsigned int sum)
 {
-        /*
+        register unsigned long reg2 asm("2") = (unsigned long) buff;
-         * Experiments with ethernet and slip connections show that buf
+        register unsigned long reg3 asm("3") = (unsigned long) len;
-         * is aligned on either a 2-byte or 4-byte boundary.
-         */
-#ifndef __s390x__
-        register_pair rp;
-        rp.subreg.even = (unsigned long) buff;
-        rp.subreg.odd = (unsigned long) len;
-        __asm__ __volatile__ (
-                "0:  cksm %0,%1\n"      /* do checksum on longs */
-                "    jo   0b\n"
-                : "+&d" (sum), "+&a" (rp) : : "cc", "memory" );
-#else /* __s390x__ */
-        __asm__ __volatile__ (
-                "    lgr  2,%1\n"    /* address in gpr 2 */
-                "    lgfr 3,%2\n"    /* length in gpr 3 */
-                "0:  cksm %0,2\n"    /* do checksum on longs */
-                "    jo   0b\n"
-                : "+&d" (sum)
-                : "d" (buff), "d" (len)
-                : "cc", "memory", "2", "3" );
-#endif /* __s390x__ */
-        return sum;
-}
-/*
- * csum_partial as an inline function
- */
-static inline unsigned int 
-csum_partial_inline(const unsigned char * buff, int len, unsigned int sum)
-{
-#ifndef __s390x__
-        register_pair rp;
-        rp.subreg.even = (unsigned long) buff;
+        asm volatile(
-        rp.subreg.odd = (unsigned long) len;
+                "0:     cksm    %0,%1\n"        /* do checksum on longs */
-        __asm__ __volatile__ (
+                "       jo      0b\n"
-                "0:  cksm %0,%1\n"    /* do checksum on longs */
+                : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
-                "    jo   0b\n"
-                : "+&d" (sum), "+&a" (rp) : : "cc", "memory" );
-#else /* __s390x__ */
-        __asm__ __volatile__ (
-                "    lgr  2,%1\n"    /* address in gpr 2 */
-                "    lgfr 3,%2\n"    /* length in gpr 3 */
-                "0:  cksm %0,2\n"    /* do checksum on longs */
-                "    jo   0b\n"
-                : "+&d" (sum)
-                : "d" (buff), "d" (len)
-                : "cc", "memory", "2", "3" );
-#endif /* __s390x__ */
        return sum;
 }
@@ -114,7 +70,7 @@ static inline unsigned int
 csum_partial_copy_nocheck (const char *src, char *dst, int len, unsigned int sum)
 {
        memcpy(dst,src,len);
-        return csum_partial_inline(dst, len, sum);
+        return csum_partial(dst, len, sum);
 }
 /*
@@ -126,22 +82,22 @@ csum_fold(unsigned int sum)
 #ifndef __s390x__
        register_pair rp;
-        __asm__ __volatile__ (
+        asm volatile(
-                "    slr  %N1,%N1\n" /* %0 = H L */
+                "       slr     %N1,%N1\n"      /* %0 = H L */
-                "    lr   %1,%0\n"   /* %0 = H L, %1 = H L 0 0 */
+                "       lr      %1,%0\n"        /* %0 = H L, %1 = H L 0 0 */
-                "    srdl %1,16\n"   /* %0 = H L, %1 = 0 H L 0 */
+                "       srdl    %1,16\n"        /* %0 = H L, %1 = 0 H L 0 */
-                "    alr  %1,%N1\n"  /* %0 = H L, %1 = L H L 0 */
+                "       alr     %1,%N1\n"       /* %0 = H L, %1 = L H L 0 */
-                "    alr  %0,%1\n"   /* %0 = H+L+C L+H */
+                "       alr     %0,%1\n"        /* %0 = H+L+C L+H */
-                "    srl  %0,16\n"   /* %0 = H+L+C */
+                "       srl     %0,16\n"        /* %0 = H+L+C */
-                : "+&d" (sum), "=d" (rp) : : "cc" );
+                : "+&d" (sum), "=d" (rp) : : "cc");
 #else /* __s390x__ */
-        __asm__ __volatile__ (
+        asm volatile(
-                "    sr   3,3\n"   /* %0 = H*65536 + L */
+                "       sr      3,3\n"          /* %0 = H*65536 + L */
-                "    lr   2,%0\n"  /* %0 = H L, R2/R3 = H L / 0 0 */
+                "       lr      2,%0\n"         /* %0 = H L, 2/3 = H L / 0 0 */
-                "    srdl 2,16\n"  /* %0 = H L, R2/R3 = 0 H / L 0 */
+                "       srdl    2,16\n"         /* %0 = H L, 2/3 = 0 H / L 0 */
-                "    alr  2,3\n"   /* %0 = H L, R2/R3 = L H / L 0 */
+                "       alr     2,3\n"          /* %0 = H L, 2/3 = L H / L 0 */
-                "    alr  %0,2\n"  /* %0 = H+L+C L+H */
+                "       alr     %0,2\n"         /* %0 = H+L+C L+H */
-                "    srl  %0,16\n" /* %0 = H+L+C */
+                "       srl     %0,16\n"        /* %0 = H+L+C */
                : "+&d" (sum) : : "cc", "2", "3");
 #endif /* __s390x__ */
        return ((unsigned short) ~sum);
@@ -155,29 +111,7 @@ csum_fold(unsigned int sum)
 static inline unsigned short
 ip_fast_csum(unsigned char *iph, unsigned int ihl)
 {
-        unsigned long sum;
+        return csum_fold(csum_partial(iph, ihl*4, 0));
-#ifndef __s390x__
-        register_pair rp;
-        rp.subreg.even = (unsigned long) iph;
-        rp.subreg.odd = (unsigned long) ihl*4;
-        __asm__ __volatile__ (
-                "    sr   %0,%0\n"   /* set sum to zero */
-                "0:  cksm %0,%1\n"   /* do checksum on longs */
-                "    jo   0b\n"
-                : "=&d" (sum), "+&a" (rp) : : "cc", "memory" );
-#else /* __s390x__ */
-        __asm__ __volatile__ (
-                "    slgr %0,%0\n"   /* set sum to zero */
-                "    lgr  2,%1\n"    /* address in gpr 2 */
-                "    lgfr 3,%2\n"    /* length in gpr 3 */
-                "0:  cksm %0,2\n"    /* do checksum on ints */
-                "    jo   0b\n"
-                : "=&d" (sum)
-                : "d" (iph), "d" (ihl*4)
-                : "cc", "memory", "2", "3" );
-#endif /* __s390x__ */
-        return csum_fold(sum);
 }
 /*
@@ -190,47 +124,47 @@ csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr,
                   unsigned int sum)
 {
 #ifndef __s390x__
-        __asm__ __volatile__ (
+        asm volatile(
-                "    alr   %0,%1\n"  /* sum += saddr */
+                "       alr     %0,%1\n" /* sum += saddr */
-                "    brc   12,0f\n"
+                "       brc     12,0f\n"
-                "    ahi   %0,1\n"   /* add carry */
+                "       ahi     %0,1\n"  /* add carry */
                "0:"
-                : "+&d" (sum) : "d" (saddr) : "cc" );
+                : "+&d" (sum) : "d" (saddr) : "cc");
-        __asm__ __volatile__ (
+        asm volatile(
-                "    alr   %0,%1\n"  /* sum += daddr */
+                "       alr     %0,%1\n" /* sum += daddr */
-                "    brc   12,1f\n"
+                "       brc     12,1f\n"
-                "    ahi   %0,1\n"   /* add carry */
+                "       ahi     %0,1\n"  /* add carry */
                "1:"
-                : "+&d" (sum) : "d" (daddr) : "cc" );
+                : "+&d" (sum) : "d" (daddr) : "cc");
-        __asm__ __volatile__ (
+        asm volatile(
-                "    alr   %0,%1\n"  /* sum += (len<<16) + (proto<<8) */
+                "       alr     %0,%1\n" /* sum += (len<<16) + (proto<<8) */
-                "    brc   12,2f\n"
+                "       brc     12,2f\n"
-                "    ahi   %0,1\n"   /* add carry */
+                "       ahi     %0,1\n"  /* add carry */
                "2:"
                : "+&d" (sum)
                : "d" (((unsigned int) len<<16) + (unsigned int) proto)
-                : "cc" );
+                : "cc");
 #else /* __s390x__ */
-        __asm__ __volatile__ (
+        asm volatile(
-                "    lgfr  %0,%0\n"
+                "       lgfr    %0,%0\n"
-                "    algr  %0,%1\n"  /* sum += saddr */
+                "       algr    %0,%1\n"  /* sum += saddr */
-                "    brc   12,0f\n"
+                "       brc     12,0f\n"
-                "    aghi  %0,1\n"   /* add carry */
+                "       aghi    %0,1\n"   /* add carry */
-                "0:  algr  %0,%2\n"  /* sum += daddr */
+                "0:     algr    %0,%2\n"  /* sum += daddr */
-                "    brc   12,1f\n"
+                "       brc     12,1f\n"
-                "    aghi  %0,1\n"   /* add carry */
+                "       aghi    %0,1\n"   /* add carry */
-                "1:  algfr %0,%3\n"  /* sum += (len<<16) + proto */
+                "1:     algfr   %0,%3\n"  /* sum += (len<<16) + proto */
-                "    brc   12,2f\n"
+                "       brc     12,2f\n"
-                "    aghi  %0,1\n"   /* add carry */
+                "       aghi    %0,1\n"   /* add carry */
-                "2:  srlg  0,%0,32\n"
+                "2:     srlg    0,%0,32\n"
-                "    alr   %0,0\n"   /* fold to 32 bits */
+                "       alr     %0,0\n"   /* fold to 32 bits */
-                "    brc   12,3f\n"
+                "       brc     12,3f\n"
-                "    ahi   %0,1\n"   /* add carry */
+                "       ahi     %0,1\n"   /* add carry */
-                "3:  llgfr %0,%0"
+                "3:     llgfr   %0,%0"
                : "+&d" (sum)
                : "d" (saddr), "d" (daddr),
                  "d" (((unsigned int) len<<16) + (unsigned int) proto)
-                : "cc", "0" );
+                : "cc", "0");
 #endif /* __s390x__ */
        return sum;
 }
diff --git a/include/asm-s390/div64.h b/include/asm-s390/div64.h
index af098dc3cf59..6cd978cefb28 100644
--- a/include/asm-s390/div64.h
+++ b/include/asm-s390/div64.h
@@ -1,49 +1 @@
-#ifndef __S390_DIV64
-#define __S390_DIV64
-#ifndef __s390x__
-/* for do_div "base" needs to be smaller than 2^31-1 */
-#define do_div(n, base) ({                                      \
-        unsigned long long __n = (n);                           \
-        unsigned long __r;                                      \
-                                                                \
-        asm ("   slr  0,0\n"                                    \
-             "   l    1,%1\n"                                   \
-             "   srdl 0,1\n"                                    \
-             "   dr   0,%2\n"                                   \
-             "   alr  1,1\n"                                    \
-             "   alr  0,0\n"                                    \
-             "   lhi  2,1\n"                                    \
-             "   n    2,%1\n"                                   \
-             "   alr  0,2\n"                                    \
-             "   clr  0,%2\n"                                   \
-             "   jl   0f\n"                                     \
-             "   slr  0,%2\n"                                   \
-             "   ahi  1,1\n"                                    \
-             "0: st   1,%1\n"                                   \
-             "   l    1,4+%1\n"                                 \
-             "   srdl 0,1\n"                                    \
-             "   dr   0,%2\n"                                   \
-             "   alr  1,1\n"                                    \
-             "   alr  0,0\n"                                    \
-             "   lhi  2,1\n"                                    \
-             "   n    2,4+%1\n"                                 \
-             "   alr  0,2\n"                                    \
-             "   clr  0,%2\n"                                   \
-             "   jl   1f\n"                                     \
-             "   slr  0,%2\n"                                   \
-             "   ahi  1,1\n"                                    \
-             "1: st   1,4+%1\n"                                 \
-             "   lr   %0,0"                                     \
-             : "=d" (__r), "=m" (__n)                           \
-             : "d" (base), "m" (__n) : "0", "1", "2", "cc" );   \
-        (n) = (__n);                                            \
-        __r;                                                    \
-})
-#else /* __s390x__ */
 #include <asm-generic/div64.h>
-#endif /* __s390x__ */
-#endif
diff --git a/include/asm-s390/ebcdic.h b/include/asm-s390/ebcdic.h
index 15fd2eda6c90..7f6f641d32f4 100644
--- a/include/asm-s390/ebcdic.h
+++ b/include/asm-s390/ebcdic.h
@@ -26,16 +26,16 @@ codepage_convert(const __u8 *codepage, volatile __u8 * addr, unsigned long nr)
 {
        if (nr-- <= 0)
                return;
-        __asm__ __volatile__(
+        asm volatile(
-                "   bras 1,1f\n"
+                "       bras    1,1f\n"
-                "   tr   0(1,%0),0(%2)\n"
+                "       tr      0(1,%0),0(%2)\n"
-                "0: tr   0(256,%0),0(%2)\n"
+                "0:     tr      0(256,%0),0(%2)\n"
-                "   la   %0,256(%0)\n"
+                "       la      %0,256(%0)\n"
-                "1: ahi  %1,-256\n"
+                "1:     ahi     %1,-256\n"
-                "   jnm  0b\n"
+                "       jnm     0b\n"
-                "   ex   %1,0(1)"
+                "       ex      %1,0(1)"
-                : "+&a" (addr), "+&a" (nr)
+                : "+&a" (addr), "+&a" (nr)
-                : "a" (codepage) : "cc", "memory", "1" );
+                : "a" (codepage) : "cc", "memory", "1");
 }
 #define ASCEBC(addr,nr) codepage_convert(_ascebc, addr, nr)
diff --git a/include/asm-s390/io.h b/include/asm-s390/io.h
index a6cc27e77007..63c78b9399c4 100644
--- a/include/asm-s390/io.h
+++ b/include/asm-s390/io.h
@@ -27,18 +27,16 @@
 static inline unsigned long virt_to_phys(volatile void * address)
 {
        unsigned long real_address;
-        __asm__ (
+        asm volatile(
 #ifndef __s390x__
-                 "   lra    %0,0(%1)\n"
+                 "      lra     %0,0(%1)\n"
-                 "   jz     0f\n"
-                 "   sr     %0,%0\n"
 #else /* __s390x__ */
-                 "   lrag   %0,0(%1)\n"
+                 "      lrag    %0,0(%1)\n"
-                 "   jz     0f\n"
-                 "   slgr   %0,%0\n"
 #endif /* __s390x__ */
+                 "      jz      0f\n"
+                 "      la      %0,0\n"
                 "0:"
-                 : "=a" (real_address) : "a" (address) : "cc" );
+                 : "=a" (real_address) : "a" (address) : "cc");
        return real_address;
 }
diff --git a/include/asm-s390/irqflags.h b/include/asm-s390/irqflags.h
index 3b566a5b3cc7..3f26131120b7 100644
--- a/include/asm-s390/irqflags.h
+++ b/include/asm-s390/irqflags.h
@@ -10,43 +10,93 @@
 #ifdef __KERNEL__
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+/* store then or system mask. */
+#define __raw_local_irq_stosm(__or)                                     \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stosm   %0,%1"                                  \
+                : "=Q" (__mask) : "i" (__or) : "memory");               \
+        __mask;                                                         \
+})
+/* store then and system mask. */
+#define __raw_local_irq_stnsm(__and)                                    \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stnsm   %0,%1"                                  \
+                : "=Q" (__mask) : "i" (__and) : "memory");              \
+        __mask;                                                         \
+})
+/* set system mask. */
+#define __raw_local_irq_ssm(__mask)                                     \
+({                                                                      \
+        asm volatile("ssm   %0" : : "Q" (__mask) : "memory");           \
+})
+#else /* __GNUC__ */
+/* store then or system mask. */
+#define __raw_local_irq_stosm(__or)                                     \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stosm   0(%1),%2"                               \
+                : "=m" (__mask)                                         \
+                : "a" (&__mask), "i" (__or) : "memory");                \
+        __mask;                                                         \
+})
+/* store then and system mask. */
+#define __raw_local_irq_stnsm(__and)                                    \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stnsm   0(%1),%2"                               \
+                : "=m" (__mask)                                         \
+                : "a" (&__mask), "i" (__and) : "memory");               \
+        __mask;                                                         \
+})
+/* set system mask. */
+#define __raw_local_irq_ssm(__mask)                                     \
+({                                                                      \
+        asm volatile(                                                   \
+                "       ssm     0(%0)"                                  \
+                : : "a" (&__mask), "m" (__mask) : "memory");            \
+})
+#endif /* __GNUC__ */
 /* interrupt control.. */
-#define raw_local_irq_enable() ({ \
+static inline unsigned long raw_local_irq_enable(void)
-        unsigned long  __dummy; \
+{
-        __asm__ __volatile__ ( \
+        return __raw_local_irq_stosm(0x03);
-                "stosm 0(%1),0x03" \
+}
-                : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
-        })
-#define raw_local_irq_disable() ({ \
-        unsigned long __flags; \
-        __asm__ __volatile__ ( \
-                "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
-        __flags; \
-        })
-#define raw_local_save_flags(x)                                                 \
-do {                                                                            \
-        typecheck(unsigned long, x);                                            \
-        __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) );  \
-} while (0)
-#define raw_local_irq_restore(x)                                                \
+static inline unsigned long raw_local_irq_disable(void)
-do {                                                                            \
+{
-        typecheck(unsigned long, x);                                            \
+        return __raw_local_irq_stnsm(0xfc);
-        __asm__ __volatile__("ssm   0(%0)" : : "a" (&x), "m" (x) : "memory");   \
+}
+#define raw_local_save_flags(x)                                         \
+do {                                                                    \
+        typecheck(unsigned long, x);                                    \
+        (x) = __raw_local_irq_stosm(0x00);                              \
 } while (0)
-#define raw_irqs_disabled()             \
+static inline void raw_local_irq_restore(unsigned long flags)
-({                                      \
+{
-        unsigned long flags;            \
+        __raw_local_irq_ssm(flags);
-        raw_local_save_flags(flags);    \
+}
-        !((flags >> __FLAG_SHIFT) & 3); \
-})
 static inline int raw_irqs_disabled_flags(unsigned long flags)
 {
-        return !((flags >> __FLAG_SHIFT) & 3);
+        return !(flags & (3UL << (BITS_PER_LONG - 8)));
 }
 /* For spinlocks etc */
diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h
index 18695d10dedf..06583ed0bde7 100644
--- a/include/asm-s390/lowcore.h
+++ b/include/asm-s390/lowcore.h
@@ -359,7 +359,7 @@ extern struct _lowcore *lowcore_ptr[];
 static inline void set_prefix(__u32 address)
 {
-        __asm__ __volatile__ ("spx %0" : : "m" (address) : "memory" );
+        asm volatile("spx %0" : : "m" (address) : "memory");
 }
 #define __PANIC_MAGIC           0xDEADC0DE
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h
index b2628dc5c490..796c400f2b79 100644
--- a/include/asm-s390/page.h
+++ b/include/asm-s390/page.h
@@ -22,89 +22,45 @@
 #include <asm/setup.h>
 #ifndef __ASSEMBLY__
-#ifndef __s390x__
-static inline void clear_page(void *page)
-{
-        register_pair rp;
-        rp.subreg.even = (unsigned long) page;
-        rp.subreg.odd = (unsigned long) 4096;
-        asm volatile ("   slr  1,1\n"
-                      "   mvcl %0,0"
-                      : "+&a" (rp) : : "memory", "cc", "1" );
-}
-static inline void copy_page(void *to, void *from)
-{
-        if (MACHINE_HAS_MVPG)
-                asm volatile ("   sr   0,0\n"
-                              "   mvpg %0,%1"
-                              : : "a" ((void *)(to)), "a" ((void *)(from))
-                              : "memory", "cc", "0" );
-        else
-                asm volatile ("   mvc  0(256,%0),0(%1)\n"
-                              "   mvc  256(256,%0),256(%1)\n"
-                              "   mvc  512(256,%0),512(%1)\n"
-                              "   mvc  768(256,%0),768(%1)\n"
-                              "   mvc  1024(256,%0),1024(%1)\n"
-                              "   mvc  1280(256,%0),1280(%1)\n"
-                              "   mvc  1536(256,%0),1536(%1)\n"
-                              "   mvc  1792(256,%0),1792(%1)\n"
-                              "   mvc  2048(256,%0),2048(%1)\n"
-                              "   mvc  2304(256,%0),2304(%1)\n"
-                              "   mvc  2560(256,%0),2560(%1)\n"
-                              "   mvc  2816(256,%0),2816(%1)\n"
-                              "   mvc  3072(256,%0),3072(%1)\n"
-                              "   mvc  3328(256,%0),3328(%1)\n"
-                              "   mvc  3584(256,%0),3584(%1)\n"
-                              "   mvc  3840(256,%0),3840(%1)\n"
-                              : : "a"((void *)(to)),"a"((void *)(from)) 
-                              : "memory" );
-}
-#else /* __s390x__ */
 static inline void clear_page(void *page)
 {
-        asm volatile ("   lgr  2,%0\n"
+        register unsigned long reg1 asm ("1") = 0;
-                      "   lghi 3,4096\n"
+        register void *reg2 asm ("2") = page;
-                      "   slgr 1,1\n"
+        register unsigned long reg3 asm ("3") = 4096;
-                      "   mvcl 2,0"
+        asm volatile(
-                      : : "a" ((void *) (page))
+                "       mvcl    2,0"
-                      : "memory", "cc", "1", "2", "3" );
+                : "+d" (reg2), "+d" (reg3) : "d" (reg1) : "memory", "cc");
 }
 static inline void copy_page(void *to, void *from)
 {
-        if (MACHINE_HAS_MVPG)
+        if (MACHINE_HAS_MVPG) {
-                asm volatile ("   sgr  0,0\n"
+                register unsigned long reg0 asm ("0") = 0;
-                              "   mvpg %0,%1"
+                asm volatile(
-                              : : "a" ((void *)(to)), "a" ((void *)(from))
+                        "       mvpg    %0,%1"
-                              : "memory", "cc", "0" );
+                        : : "a" (to), "a" (from), "d" (reg0)
-        else
+                        : "memory", "cc");
-                asm volatile ("   mvc  0(256,%0),0(%1)\n"
+        } else
-                              "   mvc  256(256,%0),256(%1)\n"
+                asm volatile(
-                              "   mvc  512(256,%0),512(%1)\n"
+                        "       mvc     0(256,%0),0(%1)\n"
-                              "   mvc  768(256,%0),768(%1)\n"
+                        "       mvc     256(256,%0),256(%1)\n"
-                              "   mvc  1024(256,%0),1024(%1)\n"
+                        "       mvc     512(256,%0),512(%1)\n"
-                              "   mvc  1280(256,%0),1280(%1)\n"
+                        "       mvc     768(256,%0),768(%1)\n"
-                              "   mvc  1536(256,%0),1536(%1)\n"
+                        "       mvc     1024(256,%0),1024(%1)\n"
-                              "   mvc  1792(256,%0),1792(%1)\n"
+                        "       mvc     1280(256,%0),1280(%1)\n"
-                              "   mvc  2048(256,%0),2048(%1)\n"
+                        "       mvc     1536(256,%0),1536(%1)\n"
-                              "   mvc  2304(256,%0),2304(%1)\n"
+                        "       mvc     1792(256,%0),1792(%1)\n"
-                              "   mvc  2560(256,%0),2560(%1)\n"
+                        "       mvc     2048(256,%0),2048(%1)\n"
-                              "   mvc  2816(256,%0),2816(%1)\n"
+                        "       mvc     2304(256,%0),2304(%1)\n"
-                              "   mvc  3072(256,%0),3072(%1)\n"
+                        "       mvc     2560(256,%0),2560(%1)\n"
-                              "   mvc  3328(256,%0),3328(%1)\n"
+                        "       mvc     2816(256,%0),2816(%1)\n"
-                              "   mvc  3584(256,%0),3584(%1)\n"
+                        "       mvc     3072(256,%0),3072(%1)\n"
-                              "   mvc  3840(256,%0),3840(%1)\n"
+                        "       mvc     3328(256,%0),3328(%1)\n"
-                              : : "a"((void *)(to)),"a"((void *)(from)) 
+                        "       mvc     3584(256,%0),3584(%1)\n"
-                              : "memory" );
+                        "       mvc     3840(256,%0),3840(%1)\n"
+                        : : "a" (to), "a" (from) : "memory");
 }
-#endif /* __s390x__ */
 #define clear_user_page(page, vaddr, pg)        clear_page(page)
 #define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
@@ -159,7 +115,7 @@ extern unsigned int default_storage_key;
 static inline void
 page_set_storage_key(unsigned long addr, unsigned int skey)
 {
-        asm volatile ( "sske %0,%1" : : "d" (skey), "a" (addr) );
+        asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
 }
 static inline unsigned int
@@ -167,8 +123,7 @@ page_get_storage_key(unsigned long addr)
 {
        unsigned int skey;
-        asm volatile ( "iske %0,%1" : "=d" (skey) : "a" (addr), "0" (0) );
+        asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr), "0" (0));
        return skey;
 }
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index e965309fedac..83425cdefc91 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -554,9 +554,10 @@ static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
                /* ipte in zarch mode can do the math */
                pte_t *pto = ptep;
 #endif
-                asm volatile ("ipte %2,%3"
+                asm volatile(
-                              : "=m" (*ptep) : "m" (*ptep),
+                        "       ipte    %2,%3"
-                                "a" (pto), "a" (address) );
+                        : "=m" (*ptep) : "m" (*ptep),
+                          "a" (pto), "a" (address));
        }
        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
 }
@@ -609,16 +610,17 @@ ptep_establish(struct vm_area_struct *vma,
 /*
 * Test and clear referenced bit in storage key.
 */
-#define page_test_and_clear_young(page)                                   \
+#define page_test_and_clear_young(page)                                 \
-({                                                                        \
+({                                                                      \
-        struct page *__page = (page);                                     \
+        struct page *__page = (page);                                   \
-        unsigned long __physpage = __pa((__page-mem_map) << PAGE_SHIFT);  \
+        unsigned long __physpage = __pa((__page-mem_map) << PAGE_SHIFT);\
-        int __ccode;                                                      \
+        int __ccode;                                                    \
-        asm volatile ("rrbe 0,%1\n\t"                                     \
+        asm volatile(                                                   \
-                      "ipm  %0\n\t"                                       \
+                "       rrbe    0,%1\n"                                 \
-                      "srl  %0,28\n\t"                                    \
+                "       ipm     %0\n"                                   \
-                      : "=d" (__ccode) : "a" (__physpage) : "cc" );       \
+                "       srl     %0,28\n"                                \
-        (__ccode & 2);                                                    \
+                : "=d" (__ccode) : "a" (__physpage) : "cc");            \
+        (__ccode & 2);                                                  \
 })
 /*
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index 578c2209fa76..cbbedc63ba25 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -13,7 +13,6 @@
 #ifndef __ASM_S390_PROCESSOR_H
 #define __ASM_S390_PROCESSOR_H
-#include <asm/page.h>
 #include <asm/ptrace.h>
 #ifdef __KERNEL__
@@ -21,7 +20,7 @@
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
-#define current_text_addr() ({ void *pc; __asm__("basr %0,0":"=a"(pc)); pc; })
+#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
 /*
 *  CPU type and hardware bug flags. Kept separately for each CPU.
@@ -202,7 +201,7 @@ unsigned long get_wchan(struct task_struct *p);
 static inline void cpu_relax(void)
 {
        if (MACHINE_HAS_DIAG44)
-                asm volatile ("diag 0,0,68" : : : "memory");
+                asm volatile("diag 0,0,68" : : : "memory");
        else
                barrier();
 }
@@ -213,9 +212,9 @@ static inline void cpu_relax(void)
 static inline void __load_psw(psw_t psw)
 {
 #ifndef __s390x__
-        asm volatile ("lpsw  0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
+        asm volatile("lpsw  0(%0)" : : "a" (&psw), "m" (psw) : "cc");
 #else
-        asm volatile ("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
+        asm volatile("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
 #endif
 }
@@ -232,20 +231,20 @@ static inline void __load_psw_mask (unsigned long mask)
        psw.mask = mask;
 #ifndef __s390x__
-        asm volatile (
+        asm volatile(
-                "    basr %0,0\n"
+                "       basr    %0,0\n"
-                "0:  ahi  %0,1f-0b\n"
+                "0:     ahi     %0,1f-0b\n"
-                "    st   %0,4(%1)\n"
+                "       st      %0,4(%1)\n"
-                "    lpsw 0(%1)\n"
+                "       lpsw    0(%1)\n"
                "1:"
-                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc" );
+                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
 #else /* __s390x__ */
-        asm volatile (
+        asm volatile(
-                "    larl  %0,1f\n"
+                "       larl    %0,1f\n"
-                "    stg   %0,8(%1)\n"
+                "       stg     %0,8(%1)\n"
-                "    lpswe 0(%1)\n"
+                "       lpswe   0(%1)\n"
                "1:"
-                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc" );
+                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
 #endif /* __s390x__ */
 }
 
@@ -274,56 +273,57 @@ static inline void disabled_wait(unsigned long code)
         * the processor is dead afterwards
         */
 #ifndef __s390x__
-        asm volatile ("    stctl 0,0,0(%2)\n"
+        asm volatile(
-                      "    ni    0(%2),0xef\n" /* switch off protection */
+                "       stctl   0,0,0(%2)\n"
-                      "    lctl  0,0,0(%2)\n"
+                "       ni      0(%2),0xef\n"   /* switch off protection */
-                      "    stpt  0xd8\n"       /* store timer */
+                "       lctl    0,0,0(%2)\n"
-                      "    stckc 0xe0\n"       /* store clock comparator */
+                "       stpt    0xd8\n"         /* store timer */
-                      "    stpx  0x108\n"      /* store prefix register */
+                "       stckc   0xe0\n"         /* store clock comparator */
-                      "    stam  0,15,0x120\n" /* store access registers */
+                "       stpx    0x108\n"        /* store prefix register */
-                      "    std   0,0x160\n"    /* store f0 */
+                "       stam    0,15,0x120\n"   /* store access registers */
-                      "    std   2,0x168\n"    /* store f2 */
+                "       std     0,0x160\n"      /* store f0 */
-                      "    std   4,0x170\n"    /* store f4 */
+                "       std     2,0x168\n"      /* store f2 */
-                      "    std   6,0x178\n"    /* store f6 */
+                "       std     4,0x170\n"      /* store f4 */
-                      "    stm   0,15,0x180\n" /* store general registers */
+                "       std     6,0x178\n"      /* store f6 */
-                      "    stctl 0,15,0x1c0\n" /* store control registers */
+                "       stm     0,15,0x180\n"   /* store general registers */
-                      "    oi    0x1c0,0x10\n" /* fake protection bit */
+                "       stctl   0,15,0x1c0\n"   /* store control registers */
-                      "    lpsw 0(%1)"
+                "       oi      0x1c0,0x10\n"   /* fake protection bit */
-                      : "=m" (ctl_buf)
+                "       lpsw    0(%1)"
-                      : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc" );
+                : "=m" (ctl_buf)
+                : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 #else /* __s390x__ */
-        asm volatile ("    stctg 0,0,0(%2)\n"
+        asm volatile(
-                      "    ni    4(%2),0xef\n" /* switch off protection */
+                "       stctg   0,0,0(%2)\n"
-                      "    lctlg 0,0,0(%2)\n"
+                "       ni      4(%2),0xef\n"   /* switch off protection */
-                      "    lghi  1,0x1000\n"
+                "       lctlg   0,0,0(%2)\n"
-                      "    stpt  0x328(1)\n"      /* store timer */
+                "       lghi    1,0x1000\n"
-                      "    stckc 0x330(1)\n"      /* store clock comparator */
+                "       stpt    0x328(1)\n"     /* store timer */
-                      "    stpx  0x318(1)\n"      /* store prefix register */
+                "       stckc   0x330(1)\n"     /* store clock comparator */
-                      "    stam  0,15,0x340(1)\n" /* store access registers */
+                "       stpx    0x318(1)\n"     /* store prefix register */
-                      "    stfpc 0x31c(1)\n"      /* store fpu control */
+                "       stam    0,15,0x340(1)\n"/* store access registers */
-                      "    std   0,0x200(1)\n"    /* store f0 */
+                "       stfpc   0x31c(1)\n"     /* store fpu control */
-                      "    std   1,0x208(1)\n"    /* store f1 */
+                "       std     0,0x200(1)\n"   /* store f0 */
-                      "    std   2,0x210(1)\n"    /* store f2 */
+                "       std     1,0x208(1)\n"   /* store f1 */
-                      "    std   3,0x218(1)\n"    /* store f3 */
+                "       std     2,0x210(1)\n"   /* store f2 */
-                      "    std   4,0x220(1)\n"    /* store f4 */
+                "       std     3,0x218(1)\n"   /* store f3 */
-                      "    std   5,0x228(1)\n"    /* store f5 */
+                "       std     4,0x220(1)\n"   /* store f4 */
-                      "    std   6,0x230(1)\n"    /* store f6 */
+                "       std     5,0x228(1)\n"   /* store f5 */
-                      "    std   7,0x238(1)\n"    /* store f7 */
+                "       std     6,0x230(1)\n"   /* store f6 */
-                      "    std   8,0x240(1)\n"    /* store f8 */
+                "       std     7,0x238(1)\n"   /* store f7 */
-                      "    std   9,0x248(1)\n"    /* store f9 */
+                "       std     8,0x240(1)\n"   /* store f8 */
-                      "    std   10,0x250(1)\n"   /* store f10 */
+                "       std     9,0x248(1)\n"   /* store f9 */
-                      "    std   11,0x258(1)\n"   /* store f11 */
+                "       std     10,0x250(1)\n"  /* store f10 */
-                      "    std   12,0x260(1)\n"   /* store f12 */
+                "       std     11,0x258(1)\n"  /* store f11 */
-                      "    std   13,0x268(1)\n"   /* store f13 */
+                "       std     12,0x260(1)\n"  /* store f12 */
-                      "    std   14,0x270(1)\n"   /* store f14 */
+                "       std     13,0x268(1)\n"  /* store f13 */
-                      "    std   15,0x278(1)\n"   /* store f15 */
+                "       std     14,0x270(1)\n"  /* store f14 */
-                      "    stmg  0,15,0x280(1)\n" /* store general registers */
+                "       std     15,0x278(1)\n"  /* store f15 */
-                      "    stctg 0,15,0x380(1)\n" /* store control registers */
+                "       stmg    0,15,0x280(1)\n"/* store general registers */
-                      "    oi    0x384(1),0x10\n" /* fake protection bit */
+                "       stctg   0,15,0x380(1)\n"/* store control registers */
-                      "    lpswe 0(%1)"
+                "       oi      0x384(1),0x10\n"/* fake protection bit */
-                      : "=m" (ctl_buf)
+                "       lpswe   0(%1)"
-                      : "a" (&dw_psw), "a" (&ctl_buf),
+                : "=m" (ctl_buf)
-                        "m" (dw_psw) : "cc", "0", "1");
+                : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0");
 #endif /* __s390x__ */
 }
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index 4d75d77b0f99..8d2bf65b0b64 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -479,7 +479,7 @@ extern void show_regs(struct pt_regs * regs);
 static inline void
 psw_set_key(unsigned int key)
 {
-        asm volatile ( "spka 0(%0)" : : "d" (key) );
+        asm volatile("spka 0(%0)" : : "d" (key));
 }
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-s390/rwsem.h b/include/asm-s390/rwsem.h
index 13ec16965150..90f4eccaa290 100644
--- a/include/asm-s390/rwsem.h
+++ b/include/asm-s390/rwsem.h
@@ -122,23 +122,23 @@ static inline void __down_read(struct rw_semaphore *sem)
 {
        signed long old, new;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   ahi  %1,%5\n"
+                "       ahi     %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   aghi %1,%5\n"
+                "       aghi    %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count),
-                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory" );
+                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
        if (old < 0)
                rwsem_down_read_failed(sem);
 }
@@ -150,27 +150,27 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
 {
        signed long old, new;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: ltr  %1,%0\n"
+                "0:     ltr     %1,%0\n"
-                "   jm   1f\n"
+                "       jm      1f\n"
-                "   ahi  %1,%5\n"
+                "       ahi     %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b\n"
+                "       jl      0b\n"
                "1:"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: ltgr %1,%0\n"
+                "0:     ltgr    %1,%0\n"
-                "   jm   1f\n"
+                "       jm      1f\n"
-                "   aghi %1,%5\n"
+                "       aghi    %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b\n"
+                "       jl      0b\n"
                "1:"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count),
-                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory" );
+                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
        return old >= 0 ? 1 : 0;
 }
@@ -182,23 +182,23 @@ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
        signed long old, new, tmp;
        tmp = RWSEM_ACTIVE_WRITE_BIAS;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   a    %1,%5\n"
+                "       a       %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   ag   %1,%5\n"
+                "       ag      %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
-                : "cc", "memory" );
+                : "cc", "memory");
        if (old != 0)
                rwsem_down_write_failed(sem);
 }
@@ -215,24 +215,24 @@ static inline int __down_write_trylock(struct rw_semaphore *sem)
 {
        signed long old;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%2)\n"
+                "       l       %0,0(%2)\n"
-                "0: ltr  %0,%0\n"
+                "0:     ltr     %0,%0\n"
-                "   jnz  1f\n"
+                "       jnz     1f\n"
-                "   cs   %0,%4,0(%2)\n"
+                "       cs      %0,%4,0(%2)\n"
-                "   jl   0b\n"
+                "       jl      0b\n"
 #else /* __s390x__ */
-                "   lg   %0,0(%2)\n"
+                "       lg      %0,0(%2)\n"
-                "0: ltgr %0,%0\n"
+                "0:     ltgr    %0,%0\n"
-                "   jnz  1f\n"
+                "       jnz     1f\n"
-                "   csg  %0,%4,0(%2)\n"
+                "       csg     %0,%4,0(%2)\n"
-                "   jl   0b\n"
+                "       jl      0b\n"
 #endif /* __s390x__ */
                "1:"
-                : "=&d" (old), "=m" (sem->count)
+                : "=&d" (old), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count),
-                  "d" (RWSEM_ACTIVE_WRITE_BIAS) : "cc", "memory" );
+                  "d" (RWSEM_ACTIVE_WRITE_BIAS) : "cc", "memory");
        return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0;
 }
@@ -243,24 +243,24 @@ static inline void __up_read(struct rw_semaphore *sem)
 {
        signed long old, new;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   ahi  %1,%5\n"
+                "       ahi     %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   aghi %1,%5\n"
+                "       aghi    %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count),
                  "i" (-RWSEM_ACTIVE_READ_BIAS)
-                : "cc", "memory" );
+                : "cc", "memory");
        if (new < 0)
                if ((new & RWSEM_ACTIVE_MASK) == 0)
                        rwsem_wake(sem);
@@ -274,23 +274,23 @@ static inline void __up_write(struct rw_semaphore *sem)
        signed long old, new, tmp;
        tmp = -RWSEM_ACTIVE_WRITE_BIAS;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   a    %1,%5\n"
+                "       a       %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   ag   %1,%5\n"
+                "       ag      %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
-                : "cc", "memory" );
+                : "cc", "memory");
        if (new < 0)
                if ((new & RWSEM_ACTIVE_MASK) == 0)
                        rwsem_wake(sem);
@@ -304,23 +304,23 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
        signed long old, new, tmp;
        tmp = -RWSEM_WAITING_BIAS;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   a    %1,%5\n"
+                "       a       %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   ag   %1,%5\n"
+                "       ag      %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
-                : "cc", "memory" );
+                : "cc", "memory");
        if (new > 1)
                rwsem_downgrade_wake(sem);
 }
@@ -332,23 +332,23 @@ static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
 {
        signed long old, new;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   ar   %1,%5\n"
+                "       ar      %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   agr  %1,%5\n"
+                "       agr     %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count), "d" (delta)
-                : "cc", "memory" );
+                : "cc", "memory");
 }
 /*
@@ -358,23 +358,23 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
 {
        signed long old, new;
-        __asm__ __volatile__(
+        asm volatile(
 #ifndef __s390x__
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: lr   %1,%0\n"
+                "0:     lr      %1,%0\n"
-                "   ar   %1,%5\n"
+                "       ar      %1,%5\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #else /* __s390x__ */
-                "   lg   %0,0(%3)\n"
+                "       lg      %0,0(%3)\n"
-                "0: lgr  %1,%0\n"
+                "0:     lgr     %1,%0\n"
-                "   agr  %1,%5\n"
+                "       agr     %1,%5\n"
-                "   csg  %0,%1,0(%3)\n"
+                "       csg     %0,%1,0(%3)\n"
-                "   jl   0b"
+                "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
                : "a" (&sem->count), "m" (sem->count), "d" (delta)
-                : "cc", "memory" );
+                : "cc", "memory");
        return new;
 }
diff --git a/include/asm-s390/semaphore.h b/include/asm-s390/semaphore.h
index 32cdc69f39f4..dbce058aefa9 100644
--- a/include/asm-s390/semaphore.h
+++ b/include/asm-s390/semaphore.h
@@ -85,17 +85,17 @@ static inline int down_trylock(struct semaphore * sem)
         *       sem->count.counter = --new_val;
         * In the ppc code this is called atomic_dec_if_positive.
         */
-        __asm__ __volatile__ (
+        asm volatile(
-                "   l    %0,0(%3)\n"
+                "       l       %0,0(%3)\n"
-                "0: ltr  %1,%0\n"
+                "0:     ltr     %1,%0\n"
-                "   jle  1f\n"
+                "       jle     1f\n"
-                "   ahi  %1,-1\n"
+                "       ahi     %1,-1\n"
-                "   cs   %0,%1,0(%3)\n"
+                "       cs      %0,%1,0(%3)\n"
-                "   jl   0b\n"
+                "       jl      0b\n"
                "1:"
                : "=&d" (old_val), "=&d" (new_val), "=m" (sem->count.counter)
                : "a" (&sem->count.counter), "m" (sem->count.counter)
-                : "cc", "memory" );
+                : "cc", "memory");
        return old_val <= 0;
 }
diff --git a/include/asm-s390/sfp-machine.h b/include/asm-s390/sfp-machine.h
index de69dfa46fbb..8ca8c77b2d04 100644
--- a/include/asm-s390/sfp-machine.h
+++ b/include/asm-s390/sfp-machine.h
@@ -76,21 +76,23 @@
        unsigned int __r2 = (x2) + (y2);                        \
        unsigned int __r1 = (x1);                               \
        unsigned int __r0 = (x0);                               \
-        __asm__ ("   alr %2,%3\n"                               \
+        asm volatile(                                           \
-                 "   brc 12,0f\n"                               \
+                "       alr     %2,%3\n"                        \
-                 "   lhi 0,1\n"                                 \
+                "       brc     12,0f\n"                        \
-                 "   alr %1,0\n"                                \
+                "       lhi     0,1\n"                          \
-                 "   brc 12,0f\n"                               \
+                "       alr     %1,0\n"                         \
-                 "   alr %0,0\n"                                \
+                "       brc     12,0f\n"                        \
-                 "0:"                                           \
+                "       alr     %0,0\n"                         \
-                 : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0)     \
+                "0:"                                            \
-                 : "d" (y0), "i" (1) : "cc", "0" );             \
+                : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0)      \
-        __asm__ ("   alr %1,%2\n"                               \
+                : "d" (y0), "i" (1) : "cc", "0" );              \
-                 "   brc 12,0f\n"                               \
+        asm volatile(                                           \
-                 "   ahi %0,1\n"                                \
+                "       alr     %1,%2\n"                        \
-                 "0:"                                           \
+                "       brc     12,0f\n"                        \
-                 : "+&d" (__r2), "+&d" (__r1)                   \
+                "       ahi     %0,1\n"                         \
-                 : "d" (y1) : "cc" );                           \
+                "0:"                                            \
+                : "+&d" (__r2), "+&d" (__r1)                    \
+                : "d" (y1) : "cc");                             \
        (r2) = __r2;                                            \
        (r1) = __r1;                                            \
        (r0) = __r0;                                            \
@@ -100,21 +102,23 @@
        unsigned int __r2 = (x2) - (y2);                        \
        unsigned int __r1 = (x1);                               \
        unsigned int __r0 = (x0);                               \
-        __asm__ ("   slr %2,%3\n"                               \
+        asm volatile(                                           \
-                 "   brc 3,0f\n"                                \
+                "       slr   %2,%3\n"                          \
-                 "   lhi 0,1\n"                                 \
+                "       brc     3,0f\n"                         \
-                 "   slr %1,0\n"                                \
+                "       lhi     0,1\n"                          \
-                 "   brc 3,0f\n"                                \
+                "       slr     %1,0\n"                         \
-                 "   slr %0,0\n"                                \
+                "       brc     3,0f\n"                         \
-                 "0:"                                           \
+                "       slr     %0,0\n"                         \
-                 : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0)     \
+                "0:"                                            \
-                 : "d" (y0) : "cc", "0" );                      \
+                : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0)      \
-        __asm__ ("   slr %1,%2\n"                               \
+                : "d" (y0) : "cc", "0");                        \
-                 "   brc 3,0f\n"                                \
+        asm volatile(                                           \
-                 "   ahi %0,-1\n"                               \
+                "       slr     %1,%2\n"                        \
-                 "0:"                                           \
+                "       brc     3,0f\n"                         \
-                 : "+&d" (__r2), "+&d" (__r1)                   \
+                "       ahi     %0,-1\n"                        \
-                 : "d" (y1) : "cc" );                           \
+                "0:"                                            \
+                : "+&d" (__r2), "+&d" (__r1)                    \
+                : "d" (y1) : "cc");                             \
        (r2) = __r2;                                            \
        (r1) = __r1;                                            \
        (r0) = __r0;                                            \
diff --git a/include/asm-s390/sigp.h b/include/asm-s390/sigp.h
index fc56458aff66..e16d56f8dfe1 100644
--- a/include/asm-s390/sigp.h
+++ b/include/asm-s390/sigp.h
@@ -70,16 +70,16 @@ typedef enum
 static inline sigp_ccode
 signal_processor(__u16 cpu_addr, sigp_order_code order_code)
 {
+        register unsigned long reg1 asm ("1") = 0;
        sigp_ccode ccode;
-        __asm__ __volatile__(
+        asm volatile(
-                "    sr     1,1\n"        /* parameter=0 in gpr 1 */
+                "       sigp    %1,%2,0(%3)\n"
-                "    sigp   1,%1,0(%2)\n"
+                "       ipm     %0\n"
-                "    ipm    %0\n"
+                "       srl     %0,28\n"
-                "    srl    %0,28\n"
+                :       "=d"    (ccode)
-                : "=d" (ccode)
+                : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
-                : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
+                  "a" (order_code) : "cc" , "memory");
-                : "cc" , "memory", "1" );
        return ccode;
 }
@@ -87,20 +87,18 @@ signal_processor(__u16 cpu_addr, sigp_order_code order_code)
 * Signal processor with parameter
 */
 static inline sigp_ccode
-signal_processor_p(__u32 parameter, __u16 cpu_addr,
+signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
-                   sigp_order_code order_code)
 {
+        register unsigned int reg1 asm ("1") = parameter;
        sigp_ccode ccode;
-        
-        __asm__ __volatile__(
+        asm volatile(
-                "    lr     1,%1\n"       /* parameter in gpr 1 */
+                "       sigp    %1,%2,0(%3)\n"
-                "    sigp   1,%2,0(%3)\n"
+                "       ipm     %0\n"
-                "    ipm    %0\n"
+                "       srl     %0,28\n"
-                "    srl    %0,28\n"
                : "=d" (ccode)
-                : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]),
+                : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
-                  "a" (order_code)
+                  "a" (order_code) : "cc" , "memory");
-                : "cc" , "memory", "1" );
        return ccode;
 }
@@ -108,24 +106,21 @@ signal_processor_p(__u32 parameter, __u16 cpu_addr,
 * Signal processor with parameter and return status
 */
 static inline sigp_ccode
-signal_processor_ps(__u32 *statusptr, __u32 parameter,
+signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
-                    __u16 cpu_addr, sigp_order_code order_code)
+                    sigp_order_code order_code)
 {
+        register unsigned int reg1 asm ("1") = parameter;
        sigp_ccode ccode;
-        
-        __asm__ __volatile__(
+        asm volatile(
-                "    sr     2,2\n"        /* clear status */
+                "       sigp    %1,%2,0(%3)\n"
-                "    lr     3,%2\n"       /* parameter in gpr 3 */
+                "       ipm     %0\n"
-                "    sigp   2,%3,0(%4)\n"
+                "       srl     %0,28\n"
-                "    st     2,%1\n"
+                : "=d" (ccode), "+d" (reg1)
-                "    ipm    %0\n"
+                : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
-                "    srl    %0,28\n"
+                : "cc" , "memory");
-                : "=d" (ccode), "=m" (*statusptr)
+        *statusptr = reg1;
-                : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]),
+        return ccode;
-                  "a" (order_code)
-                : "cc" , "memory", "2" , "3"
-                );
-   return ccode;
 }
 #endif /* __SIGP__ */
diff --git a/include/asm-s390/smp.h b/include/asm-s390/smp.h
index 9fb02e9779c9..c3cf030ada4d 100644
--- a/include/asm-s390/smp.h
+++ b/include/asm-s390/smp.h
@@ -56,7 +56,7 @@ static inline __u16 hard_smp_processor_id(void)
 {
        __u16 cpu_address;
 
-        __asm__ ("stap %0\n" : "=m" (cpu_address));
+        asm volatile("stap %0" : "=m" (cpu_address));
        return cpu_address;
 }
diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
index 273dbecf8ace..ce3edf6d63b3 100644
--- a/include/asm-s390/spinlock.h
+++ b/include/asm-s390/spinlock.h
@@ -11,17 +11,36 @@
 #ifndef __ASM_SPINLOCK_H
 #define __ASM_SPINLOCK_H
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+static inline int
+_raw_compare_and_swap(volatile unsigned int *lock,
+                      unsigned int old, unsigned int new)
+{
+        asm volatile(
+                "       cs      %0,%3,%1"
+                : "=d" (old), "=Q" (*lock)
+                : "0" (old), "d" (new), "Q" (*lock)
+                : "cc", "memory" );
+        return old;
+}
+#else /* __GNUC__ */
 static inline int
 _raw_compare_and_swap(volatile unsigned int *lock,
                      unsigned int old, unsigned int new)
 {
-        asm volatile ("cs %0,%3,0(%4)"
+        asm volatile(
-                      : "=d" (old), "=m" (*lock)
+                "       cs      %0,%3,0(%4)"
-                      : "0" (old), "d" (new), "a" (lock), "m" (*lock)
+                : "=d" (old), "=m" (*lock)
-                      : "cc", "memory" );
+                : "0" (old), "d" (new), "a" (lock), "m" (*lock)
+                : "cc", "memory" );
        return old;
 }
+#endif /* __GNUC__ */
 /*
 * Simple spin lock operations.  There are two variants, one clears IRQ's
 * on the local processor, one does not.
diff --git a/include/asm-s390/string.h b/include/asm-s390/string.h
index 23a4c390489f..d074673a6d9b 100644
--- a/include/asm-s390/string.h
+++ b/include/asm-s390/string.h
@@ -60,12 +60,13 @@ static inline void *memchr(const void * s, int c, size_t n)
        register int r0 asm("0") = (char) c;
        const void *ret = s + n;
-        asm volatile ("0: srst  %0,%1\n"
+        asm volatile(
-                      "   jo    0b\n"
+                "0:     srst    %0,%1\n"
-                      "   jl    1f\n"
+                "       jo      0b\n"
-                      "   la    %0,0\n"
+                "       jl      1f\n"
-                      "1:"
+                "       la      %0,0\n"
-                      : "+a" (ret), "+&a" (s) : "d" (r0) : "cc" );
+                "1:"
+                : "+a" (ret), "+&a" (s) : "d" (r0) : "cc");
        return (void *) ret;
 }
@@ -74,9 +75,10 @@ static inline void *memscan(void *s, int c, size_t n)
        register int r0 asm("0") = (char) c;
        const void *ret = s + n;
-        asm volatile ("0: srst  %0,%1\n"
+        asm volatile(
-                      "   jo    0b\n"
+                "0:     srst    %0,%1\n"
-                      : "+a" (ret), "+&a" (s) : "d" (r0) : "cc" );
+                "       jo      0b\n"
+                : "+a" (ret), "+&a" (s) : "d" (r0) : "cc");
        return (void *) ret;
 }
@@ -86,12 +88,13 @@ static inline char *strcat(char *dst, const char *src)
        unsigned long dummy;
        char *ret = dst;
-        asm volatile ("0: srst  %0,%1\n"
+        asm volatile(
-                      "   jo    0b\n"
+                "0:     srst    %0,%1\n"
-                      "1: mvst  %0,%2\n"
+                "       jo      0b\n"
-                      "   jo    1b"
+                "1:     mvst    %0,%2\n"
-                      : "=&a" (dummy), "+a" (dst), "+a" (src)
+                "       jo      1b"
-                      : "d" (r0), "0" (0) : "cc", "memory" );
+                : "=&a" (dummy), "+a" (dst), "+a" (src)
+                : "d" (r0), "0" (0) : "cc", "memory" );
        return ret;
 }
@@ -100,10 +103,11 @@ static inline char *strcpy(char *dst, const char *src)
        register int r0 asm("0") = 0;
        char *ret = dst;
-        asm volatile ("0: mvst  %0,%1\n"
+        asm volatile(
-                      "   jo    0b"
+                "0:     mvst    %0,%1\n"
-                      : "+&a" (dst), "+&a" (src) : "d" (r0)
+                "       jo      0b"
-                      : "cc", "memory" );
+                : "+&a" (dst), "+&a" (src) : "d" (r0)
+                : "cc", "memory");
        return ret;
 }
@@ -112,9 +116,10 @@ static inline size_t strlen(const char *s)
        register unsigned long r0 asm("0") = 0;
        const char *tmp = s;
-        asm volatile ("0: srst  %0,%1\n"
+        asm volatile(
-                      "   jo    0b"
+                "0:     srst    %0,%1\n"
-                      : "+d" (r0), "+a" (tmp) :  : "cc" );
+                "       jo      0b"
+                : "+d" (r0), "+a" (tmp) :  : "cc");
        return r0 - (unsigned long) s;
 }
@@ -124,9 +129,10 @@ static inline size_t strnlen(const char * s, size_t n)
        const char *tmp = s;
        const char *end = s + n;
-        asm volatile ("0: srst  %0,%1\n"
+        asm volatile(
-                      "   jo    0b"
+                "0:     srst    %0,%1\n"
-                      : "+a" (end), "+a" (tmp) : "d" (r0)  : "cc" );
+                "       jo      0b"
+                : "+a" (end), "+a" (tmp) : "d" (r0)  : "cc");
        return end - s;
 }
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index 16040048cd1b..ccbafe4bf2cb 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -23,74 +23,68 @@ struct task_struct;
 extern struct task_struct *__switch_to(void *, void *);
-#ifdef __s390x__
-#define __FLAG_SHIFT 56
-#else /* ! __s390x__ */
-#define __FLAG_SHIFT 24
-#endif /* ! __s390x__ */
 static inline void save_fp_regs(s390_fp_regs *fpregs)
 {
-        asm volatile (
+        asm volatile(
-                "   std   0,8(%1)\n"
+                "       std     0,8(%1)\n"
-                "   std   2,24(%1)\n"
+                "       std     2,24(%1)\n"
-                "   std   4,40(%1)\n"
+                "       std     4,40(%1)\n"
-                "   std   6,56(%1)"
+                "       std     6,56(%1)"
-                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
+                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
        if (!MACHINE_HAS_IEEE)
                return;
        asm volatile(
-                "   stfpc 0(%1)\n"
+                "       stfpc   0(%1)\n"
-                "   std   1,16(%1)\n"
+                "       std     1,16(%1)\n"
-                "   std   3,32(%1)\n"
+                "       std     3,32(%1)\n"
-                "   std   5,48(%1)\n"
+                "       std     5,48(%1)\n"
-                "   std   7,64(%1)\n"
+                "       std     7,64(%1)\n"
-                "   std   8,72(%1)\n"
+                "       std     8,72(%1)\n"
-                "   std   9,80(%1)\n"
+                "       std     9,80(%1)\n"
-                "   std   10,88(%1)\n"
+                "       std     10,88(%1)\n"
-                "   std   11,96(%1)\n"
+                "       std     11,96(%1)\n"
-                "   std   12,104(%1)\n"
+                "       std     12,104(%1)\n"
-                "   std   13,112(%1)\n"
+                "       std     13,112(%1)\n"
-                "   std   14,120(%1)\n"
+                "       std     14,120(%1)\n"
-                "   std   15,128(%1)\n"
+                "       std     15,128(%1)\n"
-                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
+                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
 }
 static inline void restore_fp_regs(s390_fp_regs *fpregs)
 {
-        asm volatile (
+        asm volatile(
-                "   ld    0,8(%0)\n"
+                "       ld      0,8(%0)\n"
-                "   ld    2,24(%0)\n"
+                "       ld      2,24(%0)\n"
-                "   ld    4,40(%0)\n"
+                "       ld      4,40(%0)\n"
-                "   ld    6,56(%0)"
+                "       ld      6,56(%0)"
-                : : "a" (fpregs), "m" (*fpregs) );
+                : : "a" (fpregs), "m" (*fpregs));
        if (!MACHINE_HAS_IEEE)
                return;
        asm volatile(
-                "   lfpc  0(%0)\n"
+                "       lfpc    0(%0)\n"
-                "   ld    1,16(%0)\n"
+                "       ld      1,16(%0)\n"
-                "   ld    3,32(%0)\n"
+                "       ld      3,32(%0)\n"
-                "   ld    5,48(%0)\n"
+                "       ld      5,48(%0)\n"
-                "   ld    7,64(%0)\n"
+                "       ld      7,64(%0)\n"
-                "   ld    8,72(%0)\n"
+                "       ld      8,72(%0)\n"
-                "   ld    9,80(%0)\n"
+                "       ld      9,80(%0)\n"
-                "   ld    10,88(%0)\n"
+                "       ld      10,88(%0)\n"
-                "   ld    11,96(%0)\n"
+                "       ld      11,96(%0)\n"
-                "   ld    12,104(%0)\n"
+                "       ld      12,104(%0)\n"
-                "   ld    13,112(%0)\n"
+                "       ld      13,112(%0)\n"
-                "   ld    14,120(%0)\n"
+                "       ld      14,120(%0)\n"
-                "   ld    15,128(%0)\n"
+                "       ld      15,128(%0)\n"
-                : : "a" (fpregs), "m" (*fpregs) );
+                : : "a" (fpregs), "m" (*fpregs));
 }
 static inline void save_access_regs(unsigned int *acrs)
 {
-        asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
+        asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
 }
 static inline void restore_access_regs(unsigned int *acrs)
 {
-        asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
+        asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
 }
 #define switch_to(prev,next,last) do {                                       \
@@ -126,7 +120,7 @@ extern void account_system_vtime(struct task_struct *);
        account_vtime(prev);                                                 \
 } while (0)
-#define nop() __asm__ __volatile__ ("nop")
+#define nop() asm volatile("nop")
 #define xchg(ptr,x)                                                       \
 ({                                                                        \
@@ -147,15 +141,15 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
                shift = (3 ^ (addr & 3)) << 3;
                addr ^= addr & 3;
                asm volatile(
-                        "    l   %0,0(%4)\n"
+                        "       l       %0,0(%4)\n"
-                        "0:  lr  0,%0\n"
+                        "0:     lr      0,%0\n"
-                        "    nr  0,%3\n"
+                        "       nr      0,%3\n"
-                        "    or  0,%2\n"
+                        "       or      0,%2\n"
-                        "    cs  %0,0,0(%4)\n"
+                        "       cs      %0,0,0(%4)\n"
-                        "    jl  0b\n"
+                        "       jl      0b\n"
                        : "=&d" (old), "=m" (*(int *) addr)
                        : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
-                          "m" (*(int *) addr) : "memory", "cc", "0" );
+                          "m" (*(int *) addr) : "memory", "cc", "0");
                x = old >> shift;
                break;
        case 2:
@@ -163,36 +157,36 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
                shift = (2 ^ (addr & 2)) << 3;
                addr ^= addr & 2;
                asm volatile(
-                        "    l   %0,0(%4)\n"
+                        "       l       %0,0(%4)\n"
-                        "0:  lr  0,%0\n"
+                        "0:     lr      0,%0\n"
-                        "    nr  0,%3\n"
+                        "       nr      0,%3\n"
-                        "    or  0,%2\n"
+                        "       or      0,%2\n"
-                        "    cs  %0,0,0(%4)\n"
+                        "       cs      %0,0,0(%4)\n"
-                        "    jl  0b\n"
+                        "       jl      0b\n"
                        : "=&d" (old), "=m" (*(int *) addr)
                        : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
-                          "m" (*(int *) addr) : "memory", "cc", "0" );
+                          "m" (*(int *) addr) : "memory", "cc", "0");
                x = old >> shift;
                break;
        case 4:
-                asm volatile (
+                asm volatile(
-                        "    l   %0,0(%3)\n"
+                        "       l       %0,0(%3)\n"
-                        "0:  cs  %0,%2,0(%3)\n"
+                        "0:     cs      %0,%2,0(%3)\n"
-                        "    jl  0b\n"
+                        "       jl      0b\n"
                        : "=&d" (old), "=m" (*(int *) ptr)
                        : "d" (x), "a" (ptr), "m" (*(int *) ptr)
-                        : "memory", "cc" );
+                        : "memory", "cc");
                x = old;
                break;
 #ifdef __s390x__
        case 8:
-                asm volatile (
+                asm volatile(
-                        "    lg  %0,0(%3)\n"
+                        "       lg      %0,0(%3)\n"
-                        "0:  csg %0,%2,0(%3)\n"
+                        "0:     csg     %0,%2,0(%3)\n"
-                        "    jl  0b\n"
+                        "       jl      0b\n"
                        : "=&d" (old), "=m" (*(long *) ptr)
                        : "d" (x), "a" (ptr), "m" (*(long *) ptr)
-                        : "memory", "cc" );
+                        : "memory", "cc");
                x = old;
                break;
 #endif /* __s390x__ */
@@ -224,55 +218,55 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
                shift = (3 ^ (addr & 3)) << 3;
                addr ^= addr & 3;
                asm volatile(
-                        "    l   %0,0(%4)\n"
+                        "       l       %0,0(%4)\n"
-                        "0:  nr  %0,%5\n"
+                        "0:     nr      %0,%5\n"
-                        "    lr  %1,%0\n"
+                        "       lr      %1,%0\n"
-                        "    or  %0,%2\n"
+                        "       or      %0,%2\n"
-                        "    or  %1,%3\n"
+                        "       or      %1,%3\n"
-                        "    cs  %0,%1,0(%4)\n"
+                        "       cs      %0,%1,0(%4)\n"
-                        "    jnl 1f\n"
+                        "       jnl     1f\n"
-                        "    xr  %1,%0\n"
+                        "       xr      %1,%0\n"
-                        "    nr  %1,%5\n"
+                        "       nr      %1,%5\n"
-                        "    jnz 0b\n"
+                        "       jnz     0b\n"
                        "1:"
                        : "=&d" (prev), "=&d" (tmp)
                        : "d" (old << shift), "d" (new << shift), "a" (ptr),
                          "d" (~(255 << shift))
-                        : "memory", "cc" );
+                        : "memory", "cc");
                return prev >> shift;
        case 2:
                addr = (unsigned long) ptr;
                shift = (2 ^ (addr & 2)) << 3;
                addr ^= addr & 2;
                asm volatile(
-                        "    l   %0,0(%4)\n"
+                        "       l       %0,0(%4)\n"
-                        "0:  nr  %0,%5\n"
+                        "0:     nr      %0,%5\n"
-                        "    lr  %1,%0\n"
+                        "       lr      %1,%0\n"
-                        "    or  %0,%2\n"
+                        "       or      %0,%2\n"
-                        "    or  %1,%3\n"
+                        "       or      %1,%3\n"
-                        "    cs  %0,%1,0(%4)\n"
+                        "       cs      %0,%1,0(%4)\n"
-                        "    jnl 1f\n"
+                        "       jnl     1f\n"
-                        "    xr  %1,%0\n"
+                        "       xr      %1,%0\n"
-                        "    nr  %1,%5\n"
+                        "       nr      %1,%5\n"
-                        "    jnz 0b\n"
+                        "       jnz     0b\n"
                        "1:"
                        : "=&d" (prev), "=&d" (tmp)
                        : "d" (old << shift), "d" (new << shift), "a" (ptr),
                          "d" (~(65535 << shift))
-                        : "memory", "cc" );
+                        : "memory", "cc");
                return prev >> shift;
        case 4:
-                asm volatile (
+                asm volatile(
-                        "    cs  %0,%2,0(%3)\n"
+                        "       cs      %0,%2,0(%3)\n"
                        : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
-                        : "memory", "cc" );
+                        : "memory", "cc");
                return prev;
 #ifdef __s390x__
        case 8:
-                asm volatile (
+                asm volatile(
-                        "    csg %0,%2,0(%3)\n"
+                        "       csg     %0,%2,0(%3)\n"
                        : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
-                        : "memory", "cc" );
+                        : "memory", "cc");
                return prev;
 #endif /* __s390x__ */
        }
@@ -289,8 +283,8 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 */
-#define eieio()  __asm__ __volatile__ ( "bcr 15,0" : : : "memory" ) 
+#define eieio() asm volatile("bcr 15,0" : : : "memory")
-# define SYNC_OTHER_CORES(x)   eieio() 
+#define SYNC_OTHER_CORES(x)   eieio()
 #define mb()    eieio()
 #define rmb()   eieio()
 #define wmb()   eieio()
@@ -307,117 +301,56 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 #ifdef __s390x__
-#define __ctl_load(array, low, high) ({ \
+#define __ctl_load(array, low, high) ({                         \
-        typedef struct { char _[sizeof(array)]; } addrtype; \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
-        __asm__ __volatile__ ( \
+        asm volatile(                                           \
-                "   bras  1,0f\n" \
+                "       lctlg   %1,%2,0(%0)\n"                  \
-                "   lctlg 0,0,0(%0)\n" \
+                : : "a" (&array), "i" (low), "i" (high),        \
-                "0: ex    %1,0(1)" \
+                    "m" (*(addrtype *)(array)));                \
-                : : "a" (&array), "a" (((low)<<4)+(high)), \
-                    "m" (*(addrtype *)(array)) : "1" ); \
        })
-#define __ctl_store(array, low, high) ({ \
+#define __ctl_store(array, low, high) ({                        \
-        typedef struct { char _[sizeof(array)]; } addrtype; \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
-        __asm__ __volatile__ ( \
+        asm volatile(                                           \
-                "   bras  1,0f\n" \
+                "       stctg   %2,%3,0(%1)\n"                  \
-                "   stctg 0,0,0(%1)\n" \
+                : "=m" (*(addrtype *)(array))                   \
-                "0: ex    %2,0(1)" \
+                : "a" (&array), "i" (low), "i" (high));         \
-                : "=m" (*(addrtype *)(array)) \
-                : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
        })
-#define __ctl_set_bit(cr, bit) ({ \
-        __u8 __dummy[24]; \
-        __asm__ __volatile__ ( \
-                "    bras  1,0f\n"       /* skip indirect insns */ \
-                "    stctg 0,0,0(%1)\n" \
-                "    lctlg 0,0,0(%1)\n" \
-                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
-                "    lg    0,0(%1)\n" \
-                "    ogr   0,%3\n"       /* set the bit */ \
-                "    stg   0,0(%1)\n" \
-                "1:  ex    %2,6(1)"      /* execute lctl */ \
-                : "=m" (__dummy) \
-                : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
-                  "a" (cr*17), "a" (1L<<(bit)) \
-                : "cc", "0", "1" ); \
-        })
-#define __ctl_clear_bit(cr, bit) ({ \
-        __u8 __dummy[16]; \
-        __asm__ __volatile__ ( \
-                "    bras  1,0f\n"       /* skip indirect insns */ \
-                "    stctg 0,0,0(%1)\n" \
-                "    lctlg 0,0,0(%1)\n" \
-                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
-                "    lg    0,0(%1)\n" \
-                "    ngr   0,%3\n"       /* set the bit */ \
-                "    stg   0,0(%1)\n" \
-                "1:  ex    %2,6(1)"      /* execute lctl */ \
-                : "=m" (__dummy) \
-                : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
-                  "a" (cr*17), "a" (~(1L<<(bit))) \
-                : "cc", "0", "1" ); \
-        })
 #else /* __s390x__ */
-#define __ctl_load(array, low, high) ({ \
+#define __ctl_load(array, low, high) ({                         \
-        typedef struct { char _[sizeof(array)]; } addrtype; \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
-        __asm__ __volatile__ ( \
+        asm volatile(                                           \
-                "   bras  1,0f\n" \
+                "       lctl    %1,%2,0(%0)\n"                  \
-                "   lctl 0,0,0(%0)\n" \
+                : : "a" (&array), "i" (low), "i" (high),        \
-                "0: ex    %1,0(1)" \
+                    "m" (*(addrtype *)(array)));                \
-                : : "a" (&array), "a" (((low)<<4)+(high)), \
+})
-                    "m" (*(addrtype *)(array)) : "1" ); \
-        })
-#define __ctl_store(array, low, high) ({ \
+#define __ctl_store(array, low, high) ({                        \
-        typedef struct { char _[sizeof(array)]; } addrtype; \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
-        __asm__ __volatile__ ( \
+        asm volatile(                                           \
-                "   bras  1,0f\n" \
+                "       stctl   %2,%3,0(%1)\n"                  \
-                "   stctl 0,0,0(%1)\n" \
+                : "=m" (*(addrtype *)(array))                   \
-                "0: ex    %2,0(1)" \
+                : "a" (&array), "i" (low), "i" (high));         \
-                : "=m" (*(addrtype *)(array)) \
-                : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
        })
-#define __ctl_set_bit(cr, bit) ({ \
-        __u8 __dummy[16]; \
-        __asm__ __volatile__ ( \
-                "    bras  1,0f\n"       /* skip indirect insns */ \
-                "    stctl 0,0,0(%1)\n" \
-                "    lctl  0,0,0(%1)\n" \
-                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
-                "    l     0,0(%1)\n" \
-                "    or    0,%3\n"       /* set the bit */ \
-                "    st    0,0(%1)\n" \
-                "1:  ex    %2,4(1)"      /* execute lctl */ \
-                : "=m" (__dummy) \
-                : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
-                  "a" (cr*17), "a" (1<<(bit)) \
-                : "cc", "0", "1" ); \
-        })
-#define __ctl_clear_bit(cr, bit) ({ \
-        __u8 __dummy[16]; \
-        __asm__ __volatile__ ( \
-                "    bras  1,0f\n"       /* skip indirect insns */ \
-                "    stctl 0,0,0(%1)\n" \
-                "    lctl  0,0,0(%1)\n" \
-                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
-                "    l     0,0(%1)\n" \
-                "    nr    0,%3\n"       /* set the bit */ \
-                "    st    0,0(%1)\n" \
-                "1:  ex    %2,4(1)"      /* execute lctl */ \
-                : "=m" (__dummy) \
-                : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
-                  "a" (cr*17), "a" (~(1<<(bit))) \
-                : "cc", "0", "1" ); \
-        })
 #endif /* __s390x__ */
+#define __ctl_set_bit(cr, bit) ({       \
+        unsigned long __dummy;          \
+        __ctl_store(__dummy, cr, cr);   \
+        __dummy |= 1UL << (bit);        \
+        __ctl_load(__dummy, cr, cr);    \
+})
+#define __ctl_clear_bit(cr, bit) ({     \
+        unsigned long __dummy;          \
+        __ctl_store(__dummy, cr, cr);   \
+        __dummy &= ~(1UL << (bit));     \
+        __ctl_load(__dummy, cr, cr);    \
+})
 #include <linux/irqflags.h>
 /*
@@ -427,8 +360,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 static inline void
 __set_psw_mask(unsigned long mask)
 {
-        local_save_flags(mask);
+        __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
-        __load_psw_mask(mask);
 }
 #define local_mcck_enable()  __set_psw_mask(PSW_KERNEL_BITS)
diff --git a/include/asm-s390/timex.h b/include/asm-s390/timex.h
index 5d0332a4c2bd..4df4a41029a3 100644
--- a/include/asm-s390/timex.h
+++ b/include/asm-s390/timex.h
@@ -15,20 +15,21 @@
 typedef unsigned long long cycles_t;
-static inline cycles_t get_cycles(void)
-{
-        cycles_t cycles;
-        __asm__ __volatile__ ("stck 0(%1)" : "=m" (cycles) : "a" (&cycles) : "cc");
-        return cycles >> 2;
-}
 static inline unsigned long long get_clock (void)
 {
        unsigned long long clk;
-        __asm__ __volatile__ ("stck 0(%1)" : "=m" (clk) : "a" (&clk) : "cc");
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+        asm volatile("stck %0" : "=Q" (clk) : : "cc");
+#else /* __GNUC__ */
+        asm volatile("stck 0(%1)" : "=m" (clk) : "a" (&clk) : "cc");
+#endif /* __GNUC__ */
        return clk;
 }
+static inline cycles_t get_cycles(void)
+{
+        return (cycles_t) get_clock() >> 2;
+}
 #endif
diff --git a/include/asm-s390/tlbflush.h b/include/asm-s390/tlbflush.h
index 73cd85bebfb2..fa4dc916a9bf 100644
--- a/include/asm-s390/tlbflush.h
+++ b/include/asm-s390/tlbflush.h
@@ -25,7 +25,7 @@
 */
 #define local_flush_tlb() \
-do {  __asm__ __volatile__("ptlb": : :"memory"); } while (0)
+do {  asm volatile("ptlb": : :"memory"); } while (0)
 #ifndef CONFIG_SMP
@@ -68,24 +68,24 @@ extern void smp_ptlb_all(void);
 static inline void global_flush_tlb(void)
 {
+        register unsigned long reg2 asm("2");
+        register unsigned long reg3 asm("3");
+        register unsigned long reg4 asm("4");
+        long dummy;
 #ifndef __s390x__
        if (!MACHINE_HAS_CSP) {
                smp_ptlb_all();
                return;
        }
 #endif /* __s390x__ */
-        {
-                register unsigned long addr asm("4");
+        dummy = 0;
-                long dummy;
+        reg2 = reg3 = 0;
+        reg4 = ((unsigned long) &dummy) + 1;
-                dummy = 0;
+        asm volatile(
-                addr = ((unsigned long) &dummy) + 1;
+                "       csp     %0,%2"
-                __asm__ __volatile__ (
+                : : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
-                        "    slr  2,2\n"
-                        "    slr  3,3\n"
-                        "    csp  2,%0"
-                        : : "a" (addr), "m" (dummy) : "cc", "2", "3" );
-        }
 }
 /*
@@ -102,9 +102,9 @@ static inline void __flush_tlb_mm(struct mm_struct * mm)
        if (unlikely(cpus_empty(mm->cpu_vm_mask)))
                return;
        if (MACHINE_HAS_IDTE) {
-                asm volatile (".insn rrf,0xb98e0000,0,%0,%1,0"
+                asm volatile(
-                              : : "a" (2048),
+                        "       .insn   rrf,0xb98e0000,0,%0,%1,0"
-                              "a" (__pa(mm->pgd)&PAGE_MASK) : "cc" );
+                        : : "a" (2048), "a" (__pa(mm->pgd)&PAGE_MASK) : "cc");
                return;
        }
        preempt_disable();
diff --git a/include/asm-s390/uaccess.h b/include/asm-s390/uaccess.h
index e2047b0c9092..72ae4efddb49 100644
--- a/include/asm-s390/uaccess.h
+++ b/include/asm-s390/uaccess.h
@@ -38,25 +38,14 @@
 #define get_ds()        (KERNEL_DS)
 #define get_fs()        (current->thread.mm_segment)
-#ifdef __s390x__
 #define set_fs(x) \
 ({                                                                      \
        unsigned long __pto;                                            \
        current->thread.mm_segment = (x);                               \
        __pto = current->thread.mm_segment.ar4 ?                        \
                S390_lowcore.user_asce : S390_lowcore.kernel_asce;      \
-        asm volatile ("lctlg 7,7,%0" : : "m" (__pto) );                 \
+        __ctl_load(__pto, 7, 7);                                        \
 })
-#else /* __s390x__ */
-#define set_fs(x) \
-({                                                                      \
-        unsigned long __pto;                                            \
-        current->thread.mm_segment = (x);                               \
-        __pto = current->thread.mm_segment.ar4 ?                        \
-                S390_lowcore.user_asce : S390_lowcore.kernel_asce;      \
-        asm volatile ("lctl  7,7,%0" : : "m" (__pto) );                 \
-})
-#endif /* __s390x__ */
 #define segment_eq(a,b) ((a).ar4 == (b).ar4)
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index d49c54cb5505..0361ac5dcde3 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -355,145 +355,145 @@ do {							     \
 #define _svc_clobber "1", "cc", "memory"
-#define _syscall0(type,name)                                 \
+#define _syscall0(type,name)                                    \
-type name(void) {                                            \
+type name(void) {                                               \
-        register long __svcres asm("2");                     \
+        register long __svcres asm("2");                        \
-        long __res;                                          \
+        long __res;                                             \
-        __asm__ __volatile__ (                               \
+        asm volatile(                                           \
-                "    .if %1 < 256\n"                         \
+                "       .if     %1 < 256\n"                     \
-                "    svc %b1\n"                              \
+                "       svc     %b1\n"                          \
-                "    .else\n"                                \
+                "       .else\n"                                \
-                "    la  %%r1,%1\n"                          \
+                "       la      %%r1,%1\n"                      \
-                "    svc 0\n"                                \
+                "       svc     0\n"                            \
-                "    .endif"                                 \
+                "       .endif"                                 \
-                : "=d" (__svcres)                            \
+                : "=d" (__svcres)                               \
-                : "i" (__NR_##name)                          \
+                : "i" (__NR_##name)                             \
-                : _svc_clobber );                            \
+                : _svc_clobber);                                \
-        __res = __svcres;                                    \
+        __res = __svcres;                                       \
-        __syscall_return(type,__res);                        \
+        __syscall_return(type,__res);                           \
 }
-#define _syscall1(type,name,type1,arg1)                      \
+#define _syscall1(type,name,type1,arg1)                         \
-type name(type1 arg1) {                                      \
+type name(type1 arg1) {                                         \
-        register type1 __arg1 asm("2") = arg1;               \
+        register type1 __arg1 asm("2") = arg1;                  \
-        register long __svcres asm("2");                     \
+        register long __svcres asm("2");                        \
-        long __res;                                          \
+        long __res;                                             \
-        __asm__ __volatile__ (                               \
+        asm volatile(                                           \
-                "    .if %1 < 256\n"                         \
+                "       .if     %1 < 256\n"                     \
-                "    svc %b1\n"                              \
+                "       svc     %b1\n"                          \
-                "    .else\n"                                \
+                "       .else\n"                                \
-                "    la  %%r1,%1\n"                          \
+                "       la      %%r1,%1\n"                      \
-                "    svc 0\n"                                \
+                "       svc     0\n"                            \
-                "    .endif"                                 \
+                "       .endif"                                 \
-                : "=d" (__svcres)                            \
+                : "=d" (__svcres)                               \
-                : "i" (__NR_##name),                         \
+                : "i" (__NR_##name),                            \
-                  "0" (__arg1)                               \
+                  "0" (__arg1)                                  \
-                : _svc_clobber );                            \
+                : _svc_clobber);                                \
-        __res = __svcres;                                    \
+        __res = __svcres;                                       \
-        __syscall_return(type,__res);                        \
+        __syscall_return(type,__res);                           \
 }
-#define _syscall2(type,name,type1,arg1,type2,arg2)           \
+#define _syscall2(type,name,type1,arg1,type2,arg2)              \
-type name(type1 arg1, type2 arg2) {                          \
+type name(type1 arg1, type2 arg2) {                             \
-        register type1 __arg1 asm("2") = arg1;               \
+        register type1 __arg1 asm("2") = arg1;                  \
-        register type2 __arg2 asm("3") = arg2;               \
+        register type2 __arg2 asm("3") = arg2;                  \
-        register long __svcres asm("2");                     \
+        register long __svcres asm("2");                        \
-        long __res;                                          \
+        long __res;                                             \
-        __asm__ __volatile__ (                               \
+        asm volatile(                                           \
-                "    .if %1 < 256\n"                         \
+                "       .if     %1 < 256\n"                     \
-                "    svc %b1\n"                              \
+                "       svc     %b1\n"                          \
-                "    .else\n"                                \
+                "       .else\n"                                \
-                "    la %%r1,%1\n"                           \
+                "       la      %%r1,%1\n"                      \
-                "    svc 0\n"                                \
+                "       svc     0\n"                            \
-                "    .endif"                                 \
+                "       .endif"                                 \
-                : "=d" (__svcres)                            \
+                : "=d" (__svcres)                               \
-                : "i" (__NR_##name),                         \
+                : "i" (__NR_##name),                            \
-                  "0" (__arg1),                              \
+                  "0" (__arg1),                                 \
-                  "d" (__arg2)                               \
+                  "d" (__arg2)                                  \
-                : _svc_clobber );                            \
+                : _svc_clobber );                               \
-        __res = __svcres;                                    \
+        __res = __svcres;                                       \
-        __syscall_return(type,__res);                        \
+        __syscall_return(type,__res);                           \
 }
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)\
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)   \
-type name(type1 arg1, type2 arg2, type3 arg3) {              \
+type name(type1 arg1, type2 arg2, type3 arg3) {                 \
-        register type1 __arg1 asm("2") = arg1;               \
+        register type1 __arg1 asm("2") = arg1;                  \
-        register type2 __arg2 asm("3") = arg2;               \
+        register type2 __arg2 asm("3") = arg2;                  \
-        register type3 __arg3 asm("4") = arg3;               \
+        register type3 __arg3 asm("4") = arg3;                  \
-        register long __svcres asm("2");                     \
+        register long __svcres asm("2");                        \
-        long __res;                                          \
+        long __res;                                             \
-        __asm__ __volatile__ (                               \
+        asm volatile(                                           \
-                "    .if %1 < 256\n"                         \
+                "       .if     %1 < 256\n"                     \
-                "    svc %b1\n"                              \
+                "       svc     %b1\n"                          \
-                "    .else\n"                                \
+                "       .else\n"                                \
-                "    la  %%r1,%1\n"                          \
+                "       la      %%r1,%1\n"                      \
-                "    svc 0\n"                                \
+                "       svc     0\n"                            \
-                "    .endif"                                 \
+                "       .endif"                                 \
-                : "=d" (__svcres)                            \
+                : "=d" (__svcres)                               \
-                : "i" (__NR_##name),                         \
+                : "i" (__NR_##name),                            \
-                  "0" (__arg1),                              \
+                  "0" (__arg1),                                 \
-                  "d" (__arg2),                              \
+                  "d" (__arg2),                                 \
-                  "d" (__arg3)                               \
+                  "d" (__arg3)                                  \
-                : _svc_clobber );                            \
+                : _svc_clobber);                                \
-        __res = __svcres;                                    \
+        __res = __svcres;                                       \
-        __syscall_return(type,__res);                        \
+        __syscall_return(type,__res);                           \
 }
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,\
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,   \
-                  type4,name4)                               \
+                  type4,name4)                                  \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) {  \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) {     \
-        register type1 __arg1 asm("2") = arg1;               \
+        register type1 __arg1 asm("2") = arg1;                  \
-        register type2 __arg2 asm("3") = arg2;               \
+        register type2 __arg2 asm("3") = arg2;                  \
-        register type3 __arg3 asm("4") = arg3;               \
+        register type3 __arg3 asm("4") = arg3;                  \
-        register type4 __arg4 asm("5") = arg4;               \
+        register type4 __arg4 asm("5") = arg4;                  \
-        register long __svcres asm("2");                     \
+        register long __svcres asm("2");                        \
-        long __res;                                          \
+        long __res;                                             \
-        __asm__ __volatile__ (                               \
+        asm volatile(                                           \
-                "    .if %1 < 256\n"                         \
+                "       .if     %1 < 256\n"                     \
-                "    svc %b1\n"                              \
+                "       svc     %b1\n"                          \
-                "    .else\n"                                \
+                "       .else\n"                                \
-                "    la  %%r1,%1\n"                          \
+                "       la      %%r1,%1\n"                      \
-                "    svc 0\n"                                \
+                "       svc     0\n"                            \
-                "    .endif"                                 \
+                "       .endif"                                 \
-                : "=d" (__svcres)                            \
+                : "=d" (__svcres)                               \
-                : "i" (__NR_##name),                         \
+                : "i" (__NR_##name),                            \
-                  "0" (__arg1),                              \
+                  "0" (__arg1),                                 \
-                  "d" (__arg2),                              \
+                  "d" (__arg2),                                 \
-                  "d" (__arg3),                              \
+                  "d" (__arg3),                                 \
-                  "d" (__arg4)                               \
+                  "d" (__arg4)                                  \
-                : _svc_clobber );                            \
+                : _svc_clobber);                                \
-        __res = __svcres;                                    \
+        __res = __svcres;                                       \
-        __syscall_return(type,__res);                        \
+        __syscall_return(type,__res);                           \
 }
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,\
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,   \
-                  type4,name4,type5,name5)                   \
+                  type4,name4,type5,name5)                      \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4,    \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4,       \
-          type5 arg5) {                                      \
+          type5 arg5) {                                         \
-        register type1 __arg1 asm("2") = arg1;               \
+        register type1 __arg1 asm("2") = arg1;                  \
-        register type2 __arg2 asm("3") = arg2;               \
+        register type2 __arg2 asm("3") = arg2;                  \
-        register type3 __arg3 asm("4") = arg3;               \
+        register type3 __arg3 asm("4") = arg3;                  \
-        register type4 __arg4 asm("5") = arg4;               \
+        register type4 __arg4 asm("5") = arg4;                  \
-        register type5 __arg5 asm("6") = arg5;               \
+        register type5 __arg5 asm("6") = arg5;                  \
-        register long __svcres asm("2");                     \
+        register long __svcres asm("2");                        \
-        long __res;                                          \
+        long __res;                                             \
-        __asm__ __volatile__ (                               \
+        asm volatile(                                           \
-                "    .if %1 < 256\n"                         \
+                "       .if     %1 < 256\n"                     \
-                "    svc %b1\n"                              \
+                "       svc     %b1\n"                          \
-                "    .else\n"                                \
+                "       .else\n"                                \
-                "    la  %%r1,%1\n"                          \
+                "       la      %%r1,%1\n"                      \
-                "    svc 0\n"                                \
+                "       svc     0\n"                            \
-                "    .endif"                                 \
+                "       .endif"                                 \
-                : "=d" (__svcres)                            \
+                : "=d" (__svcres)                               \
-                : "i" (__NR_##name),                         \
+                : "i" (__NR_##name),                            \
-                  "0" (__arg1),                              \
+                  "0" (__arg1),                                 \
-                  "d" (__arg2),                              \
+                  "d" (__arg2),                                 \
-                  "d" (__arg3),                              \
+                  "d" (__arg3),                                 \
-                  "d" (__arg4),                              \
+                  "d" (__arg4),                                 \
-                  "d" (__arg5)                               \
+                  "d" (__arg5)                                  \
-                : _svc_clobber );                            \
+                : _svc_clobber);                                \
-        __res = __svcres;                                    \
+        __res = __svcres;                                       \
-        __syscall_return(type,__res);                        \
+        __syscall_return(type,__res);                           \
 }
 #define __ARCH_WANT_IPC_PARSE_VERSION
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index ba095aebedff..587264a58d56 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -85,6 +85,8 @@ struct mmc_host {
        unsigned long           caps;           /* Host capabilities */
 #define MMC_CAP_4_BIT_DATA      (1 << 0)        /* Can the host do 4 bit transfers */
+#define MMC_CAP_MULTIWRITE      (1 << 1)        /* Can accurately report bytes sent to card on error */
+#define MMC_CAP_BYTEBLOCK       (1 << 2)        /* Can do non-log2 block sizes */
        /* host specific block data */
        unsigned int            max_seg_size;   /* see blk_queue_max_segment_size */
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 627e2c08ce41..a3594dfd6963 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -68,7 +68,6 @@ struct mmc_command {
 struct mmc_data {
        unsigned int            timeout_ns;     /* data timeout (in ns, max 80ms) */
        unsigned int            timeout_clks;   /* data timeout (in clocks) */
-        unsigned int            blksz_bits;     /* data block size */
        unsigned int            blksz;          /* data block size */
        unsigned int            blocks;         /* number of blocks */
        unsigned int            error;          /* data error */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab032ceafa84..61db1907f06f 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -479,6 +479,7 @@
 #define PCI_VENDOR_ID_AMD               0x1022
 #define PCI_DEVICE_ID_AMD_K8_NB         0x1100
+#define PCI_DEVICE_ID_AMD_K8_NB_MISC    0x1103
 #define PCI_DEVICE_ID_AMD_LANCE         0x2000
 #define PCI_DEVICE_ID_AMD_LANCE_HOME    0x2001
 #define PCI_DEVICE_ID_AMD_SCSI          0x2020
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 0da15b0b02be..190cc1b78fe2 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -380,10 +380,10 @@ struct usb_device {
        int maxchild;                   /* Number of ports if hub */
        struct usb_device *children[USB_MAXCHILDREN];
+        int pm_usage_cnt;               /* usage counter for autosuspend */
 #ifdef CONFIG_PM
        struct work_struct autosuspend; /* for delayed autosuspends */
        struct mutex pm_mutex;          /* protects PM operations */
-        int pm_usage_cnt;               /* usage counter for autosuspend */
        unsigned auto_pm:1;             /* autosuspend/resume in progress */
        unsigned do_remote_wakeup:1;    /* remote wakeup should be enabled */
author	Tim Shimmin <tes@chook.melbourne.sgi.com>	2006-09-29 02:45:43 -0400
committer	Tim Shimmin <tes@chook.melbourne.sgi.com>	2006-09-29 02:45:43 -0400
commit	1b06e7926694178e146ff708b2c15a6da64c9765 (patch)
tree	30602fa4a854d6956f478212937726ca75ea13ce /include
parent	65e8697a12e356cd7a6ecafa1149f5c5c6a71593 (diff)
parent	c972398b7871d9fb58c6a317786065a7cc6ca4be (diff)