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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-01-28 08:21:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-28 08:21:38 -0500
commit0ff66f0c7a5f1f4f5a0d91341b6f71fd2a49f0fa (patch)
tree7c4d74a76bf4f49e87d769c236fdd2db77fb241d /include
parentc00d4ffdbace1bdc9fdd888e4ba6d207ffa3b679 (diff)
parent4e4fc05a2b6e7bd2e0facd96e0c18dceb34d9349 (diff)
Merge branch 'pxa-plat' into devel
* pxa-plat: (53 commits) [ARM] 4762/1: Basic support for Toradex Colibri module [ARM] pxa: fix mci_init functions returning -1 [ARM] 4737/1: Refactor corgi_lcd to improve readability + bugfix [ARM] 4747/1: pcm027: support for pcm990 baseboard for phyCORE-PXA270 [ARM] 4746/1: pcm027: network support for phyCORE-PXA270 [ARM] 4745/1: pcm027: default configuration [ARM] 4744/1: pcm027: add support for phyCORE-PXA270 CPU module [NET] smc91x: Make smc91x use IRQ resource trigger flags [ARM] pxa: add default config for littleton [ARM] pxa: add basic support for Littleton (PXA3xx Form Factor Platform) [ARM] 4664/1: Add basic support for HTC Magician PDA phones [ARM] 4649/1: Base support for pxa-based Toshiba e-series PDAs. [ARM] pxa: skip registers saving/restoring if entering standby mode [ARM] pxa: fix PXA27x resume [ARM] pxa: Avoid fiddling with CKEN register on suspend [ARM] pxa: Add PXA3 standby code hooked into the IRQ wake scheme [ARM] pxa: Add zylonite MFP wakeup configurations [ARM] pxa: program MFPs for low power mode when suspending [ARM] pxa: make MFP configuration processor independent [ARM] pxa: remove un-used pxa3xx_mfp_set_xxx() functions ... Conflicts: arch/arm/mach-pxa/ssp.c Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-pxa/colibri.h19
-rw-r--r--include/asm-arm/arch-pxa/corgi.h1
-rw-r--r--include/asm-arm/arch-pxa/irqs.h10
-rw-r--r--include/asm-arm/arch-pxa/littleton.h6
-rw-r--r--include/asm-arm/arch-pxa/magician.h111
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa300.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa320.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa3xx.h252
-rw-r--r--include/asm-arm/arch-pxa/mfp.h409
-rw-r--r--include/asm-arm/arch-pxa/mmc.h2
-rw-r--r--include/asm-arm/arch-pxa/pcm027.h75
-rw-r--r--include/asm-arm/arch-pxa/pcm990_baseboard.h275
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h370
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h84
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx_spi.h24
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h86
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h112
-rw-r--r--include/asm-arm/arch-pxa/sharpsl.h2
-rw-r--r--include/asm-arm/arch-pxa/spitz.h2
-rw-r--r--include/asm-arm/arch-pxa/ssp.h36
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h14
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h9
22 files changed, 1224 insertions, 677 deletions
diff --git a/include/asm-arm/arch-pxa/colibri.h b/include/asm-arm/arch-pxa/colibri.h
new file mode 100644
index 000000000000..2ae373fb5675
--- /dev/null
+++ b/include/asm-arm/arch-pxa/colibri.h
@@ -0,0 +1,19 @@
1#ifndef _COLIBRI_H_
2#define _COLIBRI_H_
3
4/* physical memory regions */
5#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
6#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
7#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
8
9/* virtual memory regions */
10#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
11
12/* size of flash */
13#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
14
15/* Ethernet Controller Davicom DM9000 */
16#define GPIO_DM9000 114
17#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
18
19#endif /* _COLIBRI_H_ */
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index e554caa0d18b..bf856503baf6 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -104,7 +104,6 @@
104 */ 104 */
105extern struct platform_device corgiscoop_device; 105extern struct platform_device corgiscoop_device;
106extern struct platform_device corgissp_device; 106extern struct platform_device corgissp_device;
107extern struct platform_device corgifb_device;
108 107
109#endif /* __ASM_ARCH_CORGI_H */ 108#endif /* __ASM_ARCH_CORGI_H */
110 109
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index b76ee6d1f5b4..c562b972a4a6 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -180,7 +180,8 @@
180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
181#elif defined(CONFIG_ARCH_LUBBOCK) || \ 181#elif defined(CONFIG_ARCH_LUBBOCK) || \
182 defined(CONFIG_MACH_LOGICPD_PXA270) || \ 182 defined(CONFIG_MACH_LOGICPD_PXA270) || \
183 defined(CONFIG_MACH_MAINSTONE) 183 defined(CONFIG_MACH_MAINSTONE) || \
184 defined(CONFIG_MACH_PCM027)
184#define NR_IRQS (IRQ_BOARD_END) 185#define NR_IRQS (IRQ_BOARD_END)
185#else 186#else
186#define NR_IRQS (IRQ_BOARD_START) 187#define NR_IRQS (IRQ_BOARD_START)
@@ -227,6 +228,13 @@
227#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) 228#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
228#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) 229#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
229 230
231/* phyCORE-PXA270 (PCM027) Interrupts */
232#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
233#define PCM027_BTDET_IRQ PCM027_IRQ(0)
234#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
235#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
236#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
237
230/* ITE8152 irqs */ 238/* ITE8152 irqs */
231/* add IT8152 IRQs beyond BOARD_END */ 239/* add IT8152 IRQs beyond BOARD_END */
232#ifdef CONFIG_PCI_HOST_ITE8152 240#ifdef CONFIG_PCI_HOST_ITE8152
diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h
new file mode 100644
index 000000000000..79d209b826f4
--- /dev/null
+++ b/include/asm-arm/arch-pxa/littleton.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_ZYLONITE_H
2#define __ASM_ARCH_ZYLONITE_H
3
4#define LITTLETON_ETH_PHYS 0x30000000
5
6#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
new file mode 100644
index 000000000000..337f51f06b3a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/magician.h
@@ -0,0 +1,111 @@
1/*
2 * GPIO and IRQ definitions for HTC Magician PDA phones
3 *
4 * Copyright (c) 2007 Philipp Zabel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef _MAGICIAN_H_
13#define _MAGICIAN_H_
14
15#include <asm/arch/pxa-regs.h>
16
17/*
18 * PXA GPIOs
19 */
20
21#define GPIO0_MAGICIAN_KEY_POWER 0
22#define GPIO9_MAGICIAN_UNKNOWN 9
23#define GPIO10_MAGICIAN_GSM_IRQ 10
24#define GPIO11_MAGICIAN_GSM_OUT1 11
25#define GPIO13_MAGICIAN_CPLD_IRQ 13
26#define GPIO18_MAGICIAN_UNKNOWN 18
27#define GPIO22_MAGICIAN_VIBRA_EN 22
28#define GPIO26_MAGICIAN_GSM_POWER 26
29#define GPIO27_MAGICIAN_USBC_PUEN 27
30#define GPIO30_MAGICIAN_nCHARGE_EN 30
31#define GPIO37_MAGICIAN_KEY_HANGUP 37
32#define GPIO38_MAGICIAN_KEY_CONTACTS 38
33#define GPIO40_MAGICIAN_GSM_OUT2 40
34#define GPIO48_MAGICIAN_UNKNOWN 48
35#define GPIO56_MAGICIAN_UNKNOWN 56
36#define GPIO57_MAGICIAN_CAM_RESET 57
37#define GPIO83_MAGICIAN_nIR_EN 83
38#define GPIO86_MAGICIAN_GSM_RESET 86
39#define GPIO87_MAGICIAN_GSM_SELECT 87
40#define GPIO90_MAGICIAN_KEY_CALENDAR 90
41#define GPIO91_MAGICIAN_KEY_CAMERA 91
42#define GPIO93_MAGICIAN_KEY_UP 93
43#define GPIO94_MAGICIAN_KEY_DOWN 94
44#define GPIO95_MAGICIAN_KEY_LEFT 95
45#define GPIO96_MAGICIAN_KEY_RIGHT 96
46#define GPIO97_MAGICIAN_KEY_ENTER 97
47#define GPIO98_MAGICIAN_KEY_RECORD 98
48#define GPIO99_MAGICIAN_HEADPHONE_IN 99
49#define GPIO100_MAGICIAN_KEY_VOL_UP 100
50#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
51#define GPIO102_MAGICIAN_KEY_PHONE 102
52#define GPIO103_MAGICIAN_LED_KP 103
53#define GPIO104_MAGICIAN_LCD_POWER_1 104
54#define GPIO105_MAGICIAN_LCD_POWER_2 105
55#define GPIO106_MAGICIAN_LCD_POWER_3 106
56#define GPIO107_MAGICIAN_DS1WM_IRQ 107
57#define GPIO108_MAGICIAN_GSM_READY 108
58#define GPIO114_MAGICIAN_UNKNOWN 114
59#define GPIO115_MAGICIAN_nPEN_IRQ 115
60#define GPIO116_MAGICIAN_nCAM_EN 116
61#define GPIO119_MAGICIAN_UNKNOWN 119
62#define GPIO120_MAGICIAN_UNKNOWN 120
63
64/*
65 * PXA GPIO alternate function mode & direction
66 */
67
68#define GPIO0_MAGICIAN_KEY_POWER_MD (0 | GPIO_IN)
69#define GPIO9_MAGICIAN_UNKNOWN_MD (9 | GPIO_IN)
70#define GPIO10_MAGICIAN_GSM_IRQ_MD (10 | GPIO_IN)
71#define GPIO11_MAGICIAN_GSM_OUT1_MD (11 | GPIO_OUT)
72#define GPIO13_MAGICIAN_CPLD_IRQ_MD (13 | GPIO_IN)
73#define GPIO18_MAGICIAN_UNKNOWN_MD (18 | GPIO_OUT)
74#define GPIO22_MAGICIAN_VIBRA_EN_MD (22 | GPIO_OUT)
75#define GPIO26_MAGICIAN_GSM_POWER_MD (26 | GPIO_OUT)
76#define GPIO27_MAGICIAN_USBC_PUEN_MD (27 | GPIO_OUT)
77#define GPIO30_MAGICIAN_nCHARGE_EN_MD (30 | GPIO_OUT)
78#define GPIO37_MAGICIAN_KEY_HANGUP_MD (37 | GPIO_OUT)
79#define GPIO38_MAGICIAN_KEY_CONTACTS_MD (38 | GPIO_OUT)
80#define GPIO40_MAGICIAN_GSM_OUT2_MD (40 | GPIO_OUT)
81#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT)
82#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT)
83#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT)
84#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT)
85#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT)
86#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT)
87#define GPIO90_MAGICIAN_KEY_CALENDAR_MD (90 | GPIO_OUT)
88#define GPIO91_MAGICIAN_KEY_CAMERA_MD (91 | GPIO_OUT)
89#define GPIO93_MAGICIAN_KEY_UP_MD (93 | GPIO_IN)
90#define GPIO94_MAGICIAN_KEY_DOWN_MD (94 | GPIO_IN)
91#define GPIO95_MAGICIAN_KEY_LEFT_MD (95 | GPIO_IN)
92#define GPIO96_MAGICIAN_KEY_RIGHT_MD (96 | GPIO_IN)
93#define GPIO97_MAGICIAN_KEY_ENTER_MD (97 | GPIO_IN)
94#define GPIO98_MAGICIAN_KEY_RECORD_MD (98 | GPIO_IN)
95#define GPIO99_MAGICIAN_HEADPHONE_IN_MD (99 | GPIO_IN)
96#define GPIO100_MAGICIAN_KEY_VOL_UP_MD (100 | GPIO_IN)
97#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD (101 | GPIO_IN)
98#define GPIO102_MAGICIAN_KEY_PHONE_MD (102 | GPIO_IN)
99#define GPIO103_MAGICIAN_LED_KP_MD (103 | GPIO_OUT)
100#define GPIO104_MAGICIAN_LCD_POWER_1_MD (104 | GPIO_OUT)
101#define GPIO105_MAGICIAN_LCD_POWER_2_MD (105 | GPIO_OUT)
102#define GPIO106_MAGICIAN_LCD_POWER_3_MD (106 | GPIO_OUT)
103#define GPIO107_MAGICIAN_DS1WM_IRQ_MD (107 | GPIO_IN)
104#define GPIO108_MAGICIAN_GSM_READY_MD (108 | GPIO_IN)
105#define GPIO114_MAGICIAN_UNKNOWN_MD (114 | GPIO_OUT)
106#define GPIO115_MAGICIAN_nPEN_IRQ_MD (115 | GPIO_IN)
107#define GPIO116_MAGICIAN_nCAM_EN_MD (116 | GPIO_OUT)
108#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT)
109#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT)
110
111#endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
index a20996649889..bb410313556f 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa300.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -16,6 +16,7 @@
16#define __ASM_ARCH_MFP_PXA300_H 16#define __ASM_ARCH_MFP_PXA300_H
17 17
18#include <asm/arch/mfp.h> 18#include <asm/arch/mfp.h>
19#include <asm/arch/mfp-pxa3xx.h>
19 20
20/* GPIO */ 21/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) 22#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
index 52deedcaf3bd..576aa46d90fc 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa320.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -16,6 +16,7 @@
16#define __ASM_ARCH_MFP_PXA320_H 16#define __ASM_ARCH_MFP_PXA320_H
17 17
18#include <asm/arch/mfp.h> 18#include <asm/arch/mfp.h>
19#include <asm/arch/mfp-pxa3xx.h>
19 20
20/* GPIO */ 21/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) 22#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
new file mode 100644
index 000000000000..1f6b35c015d0
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
@@ -0,0 +1,252 @@
1#ifndef __ASM_ARCH_MFP_PXA3XX_H
2#define __ASM_ARCH_MFP_PXA3XX_H
3
4#define MFPR_BASE (0x40e10000)
5#define MFPR_SIZE (PAGE_SIZE)
6
7/* MFPR register bit definitions */
8#define MFPR_PULL_SEL (0x1 << 15)
9#define MFPR_PULLUP_EN (0x1 << 14)
10#define MFPR_PULLDOWN_EN (0x1 << 13)
11#define MFPR_SLEEP_SEL (0x1 << 9)
12#define MFPR_SLEEP_OE_N (0x1 << 7)
13#define MFPR_EDGE_CLEAR (0x1 << 6)
14#define MFPR_EDGE_FALL_EN (0x1 << 5)
15#define MFPR_EDGE_RISE_EN (0x1 << 4)
16
17#define MFPR_SLEEP_DATA(x) ((x) << 8)
18#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
19#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
20
21#define MFPR_EDGE_NONE (0)
22#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
23#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
24#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
25
26/*
27 * Table that determines the low power modes outputs, with actual settings
28 * used in parentheses for don't-care values. Except for the float output,
29 * the configured driven and pulled levels match, so if there is a need for
30 * non-LPM pulled output, the same configuration could probably be used.
31 *
32 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
33 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
34 *
35 * Input 0 X(0) X(0) X(0) 0
36 * Drive 0 0 0 0 X(1) 0
37 * Drive 1 0 1 X(1) 0 0
38 * Pull hi (1) 1 X(1) 1 0 0
39 * Pull lo (0) 1 X(0) 0 1 0
40 * Z (float) 1 X(0) 0 0 0
41 */
42#define MFPR_LPM_INPUT (0)
43#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
44#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
45#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
46#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
47#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
48#define MFPR_LPM_MASK (0xe080)
49
50/*
51 * The pullup and pulldown state of the MFP pin at run mode is by default
52 * determined by the selected alternate function. In case that some buggy
53 * devices need to override this default behavior, the definitions below
54 * indicates the setting of corresponding MFPR bits
55 *
56 * Definition pull_sel pullup_en pulldown_en
57 * MFPR_PULL_NONE 0 0 0
58 * MFPR_PULL_LOW 1 0 1
59 * MFPR_PULL_HIGH 1 1 0
60 * MFPR_PULL_BOTH 1 1 1
61 */
62#define MFPR_PULL_NONE (0)
63#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
64#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
65#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
66
67/* PXA3xx common MFP configurations - processor specific ones defined
68 * in mfp-pxa300.h and mfp-pxa320.h
69 */
70#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
71#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
72#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
73#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
74#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
75#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
76#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
77#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
78#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
79#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
80#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
81#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
82#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
83#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
84#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
85#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
86#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
87#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
88#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
89#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
90#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
91#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
92#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
93#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
94#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
95#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
96#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
97#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
98#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
99#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
100#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
101#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
102#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
103#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
104#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
105#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
106#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
107#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
108#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
109#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
110#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
111#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
112#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
113#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
114#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
115#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
116
117#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
118#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
119
120#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
121#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
122#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
123
124#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
125
126#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
127#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
128#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
129#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
130#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
131#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
132#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
133#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
134#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
135#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
136#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
137#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
138#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
139#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
140#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
141#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
142#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
143#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
144#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
145#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
146#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
147#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
148#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
149#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
150#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
151#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
152#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
153#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
154#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
155#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
156#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
157#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
158#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
159#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
160#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
161#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
162#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
163#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
164#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
165#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
166#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
167#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
168#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
169#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
170#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
171#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
172#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
173#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
174#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
175#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
176#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
177#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
178#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
179#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
180#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
181#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
182#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
183#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
184#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
185#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
186#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
187#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
188#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
189#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
190#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
191
192#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
193#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
194#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
195#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
196#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
197#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
198#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
199
200/*
201 * each MFP pin will have a MFPR register, since the offset of the
202 * register varies between processors, the processor specific code
203 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
204 *
205 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
206 * structure, which represents a range of MFP pins from "start" to
207 * "end", with the offset begining at "offset", to define a single
208 * pin, let "end" = -1
209 *
210 * use
211 *
212 * MFP_ADDR_X() to define a range of pins
213 * MFP_ADDR() to define a single pin
214 * MFP_ADDR_END to signal the end of pin offset definitions
215 */
216struct pxa3xx_mfp_addr_map {
217 unsigned int start;
218 unsigned int end;
219 unsigned long offset;
220};
221
222#define MFP_ADDR_X(start, end, offset) \
223 { MFP_PIN_##start, MFP_PIN_##end, offset }
224
225#define MFP_ADDR(pin, offset) \
226 { MFP_PIN_##pin, -1, offset }
227
228#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
229
230/*
231 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
232 * to the MFPR register
233 */
234unsigned long pxa3xx_mfp_read(int mfp);
235void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
236
237/*
238 * pxa3xx_mfp_config - configure the MFPR registers
239 *
240 * used by board specific initialization code
241 */
242void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
243
244/*
245 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
246 * index and MFPR register offset
247 *
248 * used by processor specific code
249 */
250void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
251void __init pxa3xx_init_mfp(void);
252#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 03c508d94f0e..02f6157396d3 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -16,9 +16,6 @@
16#ifndef __ASM_ARCH_MFP_H 16#ifndef __ASM_ARCH_MFP_H
17#define __ASM_ARCH_MFP_H 17#define __ASM_ARCH_MFP_H
18 18
19#define MFPR_BASE (0x40e10000)
20#define MFPR_SIZE (PAGE_SIZE)
21
22#define mfp_to_gpio(m) ((m) % 128) 19#define mfp_to_gpio(m) ((m) % 128)
23 20
24/* list of all the configurable MFP pins */ 21/* list of all the configurable MFP pins */
@@ -217,114 +214,21 @@ enum {
217}; 214};
218 215
219/* 216/*
220 * Table that determines the low power modes outputs, with actual settings
221 * used in parentheses for don't-care values. Except for the float output,
222 * the configured driven and pulled levels match, so if there is a need for
223 * non-LPM pulled output, the same configuration could probably be used.
224 *
225 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
226 * (bit 7) (bit 8) (bit 14d) (bit 13d)
227 *
228 * Drive 0 0 0 0 X (1) 0
229 * Drive 1 0 1 X (1) 0 0
230 * Pull hi (1) 1 X(1) 1 0 0
231 * Pull lo (0) 1 X(0) 0 1 0
232 * Z (float) 1 X(0) 0 0 0
233 */
234#define MFP_LPM_DRIVE_LOW 0x8
235#define MFP_LPM_DRIVE_HIGH 0x6
236#define MFP_LPM_PULL_HIGH 0x7
237#define MFP_LPM_PULL_LOW 0x9
238#define MFP_LPM_FLOAT 0x1
239#define MFP_LPM_PULL_NEITHER 0x0
240
241/*
242 * The pullup and pulldown state of the MFP pin is by default determined by
243 * selected alternate function. In case some buggy devices need to override
244 * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
245 * the following definition as the parameter.
246 *
247 * Definition pull_sel pullup_en pulldown_en
248 * MFP_PULL_HIGH 1 1 0
249 * MFP_PULL_LOW 1 0 1
250 * MFP_PULL_BOTH 1 1 1
251 * MFP_PULL_NONE 1 0 0
252 * MFP_PULL_DEFAULT 0 X X
253 *
254 * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
255 * bits, which will cause potential conflicts with the low power mode
256 * setting, device drivers should take care of this
257 */
258#define MFP_PULL_BOTH (0x7u)
259#define MFP_PULL_HIGH (0x6u)
260#define MFP_PULL_LOW (0x5u)
261#define MFP_PULL_NONE (0x4u)
262#define MFP_PULL_DEFAULT (0x0u)
263
264#define MFP_AF0 (0)
265#define MFP_AF1 (1)
266#define MFP_AF2 (2)
267#define MFP_AF3 (3)
268#define MFP_AF4 (4)
269#define MFP_AF5 (5)
270#define MFP_AF6 (6)
271#define MFP_AF7 (7)
272
273#define MFP_DS01X (0)
274#define MFP_DS02X (1)
275#define MFP_DS03X (2)
276#define MFP_DS04X (3)
277#define MFP_DS06X (4)
278#define MFP_DS08X (5)
279#define MFP_DS10X (6)
280#define MFP_DS12X (7)
281
282#define MFP_EDGE_BOTH 0x3
283#define MFP_EDGE_RISE 0x2
284#define MFP_EDGE_FALL 0x1
285#define MFP_EDGE_NONE 0x0
286
287#define MFPR_AF_MASK 0x0007
288#define MFPR_DRV_MASK 0x1c00
289#define MFPR_RDH_MASK 0x0200
290#define MFPR_LPM_MASK 0xe180
291#define MFPR_PULL_MASK 0xe000
292#define MFPR_EDGE_MASK 0x0070
293
294#define MFPR_ALT_OFFSET 0
295#define MFPR_ERE_OFFSET 4
296#define MFPR_EFE_OFFSET 5
297#define MFPR_EC_OFFSET 6
298#define MFPR_SON_OFFSET 7
299#define MFPR_SD_OFFSET 8
300#define MFPR_SS_OFFSET 9
301#define MFPR_DRV_OFFSET 10
302#define MFPR_PD_OFFSET 13
303#define MFPR_PU_OFFSET 14
304#define MFPR_PS_OFFSET 15
305
306#define MFPR(af, drv, rdh, lpm, edge) \
307 (((af) & 0x7) | (((drv) & 0x7) << 10) |\
308 (((rdh) & 0x1) << 9) |\
309 (((lpm) & 0x3) << 7) |\
310 (((lpm) & 0x4) << 12)|\
311 (((lpm) & 0x8) << 10)|\
312 ((!(edge)) << 6) |\
313 (((edge) & 0x1) << 5) |\
314 (((edge) & 0x2) << 3))
315
316/*
317 * a possible MFP configuration is represented by a 32-bit integer 217 * a possible MFP configuration is represented by a 32-bit integer
318 * bit 0..15 - MFPR value (16-bit) 218 *
319 * bit 16..31 - mfp pin index (used to obtain the MFPR offset) 219 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
220 * bit 10..12 - Alternate Function Selection
221 * bit 13..15 - Drive Strength
222 * bit 16..18 - Low Power Mode State
223 * bit 19..20 - Low Power Mode Edge Detection
224 * bit 21..22 - Run Mode Pull State
320 * 225 *
321 * to facilitate the definition, the following macros are provided 226 * to facilitate the definition, the following macros are provided
322 * 227 *
323 * MFPR_DEFAULT - default MFPR value, with 228 * MFP_CFG_DEFAULT - default MFP configuration value, with
324 * alternate function = 0, 229 * alternate function = 0,
325 * drive strength = fast 1mA (MFP_DS01X) 230 * drive strength = fast 3mA (MFP_DS03X)
326 * low power mode = default 231 * low power mode = default
327 * release dalay hold = false (RDH bit)
328 * edge detection = none 232 * edge detection = none
329 * 233 *
330 * MFP_CFG - default MFPR value with alternate function 234 * MFP_CFG - default MFPR value with alternate function
@@ -334,251 +238,74 @@ enum {
334 * low power mode 238 * low power mode
335 * MFP_CFG_X - default MFPR value with alternate function, 239 * MFP_CFG_X - default MFPR value with alternate function,
336 * pin drive strength and low power mode 240 * pin drive strength and low power mode
337 *
338 * use
339 *
340 * MFP_CFG_PIN - to get the MFP pin index
341 * MFP_CFG_VAL - to get the corresponding MFPR value
342 */ 241 */
343 242
344typedef uint32_t mfp_cfg_t; 243typedef unsigned long mfp_cfg_t;
345 244
346#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff) 245#define MFP_PIN(x) ((x) & 0x3ff)
347#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff) 246
348 247#define MFP_AF0 (0x0 << 10)
349/* 248#define MFP_AF1 (0x1 << 10)
350 * MFP register defaults to 249#define MFP_AF2 (0x2 << 10)
351 * drive strength fast 3mA (010'b) 250#define MFP_AF3 (0x3 << 10)
352 * edge detection logic disabled 251#define MFP_AF4 (0x4 << 10)
353 * alternate function 0 252#define MFP_AF5 (0x5 << 10)
354 */ 253#define MFP_AF6 (0x6 << 10)
355#define MFPR_DEFAULT (0x0840) 254#define MFP_AF7 (0x7 << 10)
255#define MFP_AF_MASK (0x7 << 10)
256#define MFP_AF(x) (((x) >> 10) & 0x7)
257
258#define MFP_DS01X (0x0 << 13)
259#define MFP_DS02X (0x1 << 13)
260#define MFP_DS03X (0x2 << 13)
261#define MFP_DS04X (0x3 << 13)
262#define MFP_DS06X (0x4 << 13)
263#define MFP_DS08X (0x5 << 13)
264#define MFP_DS10X (0x6 << 13)
265#define MFP_DS13X (0x7 << 13)
266#define MFP_DS_MASK (0x7 << 13)
267#define MFP_DS(x) (((x) >> 13) & 0x7)
268
269#define MFP_LPM_INPUT (0x0 << 16)
270#define MFP_LPM_DRIVE_LOW (0x1 << 16)
271#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
272#define MFP_LPM_PULL_LOW (0x3 << 16)
273#define MFP_LPM_PULL_HIGH (0x4 << 16)
274#define MFP_LPM_FLOAT (0x5 << 16)
275#define MFP_LPM_STATE_MASK (0x7 << 16)
276#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
277
278#define MFP_LPM_EDGE_NONE (0x0 << 19)
279#define MFP_LPM_EDGE_RISE (0x1 << 19)
280#define MFP_LPM_EDGE_FALL (0x2 << 19)
281#define MFP_LPM_EDGE_BOTH (0x3 << 19)
282#define MFP_LPM_EDGE_MASK (0x3 << 19)
283#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
284
285#define MFP_PULL_NONE (0x0 << 21)
286#define MFP_PULL_LOW (0x1 << 21)
287#define MFP_PULL_HIGH (0x2 << 21)
288#define MFP_PULL_BOTH (0x3 << 21)
289#define MFP_PULL_MASK (0x3 << 21)
290#define MFP_PULL(x) (((x) >> 21) & 0x3)
291
292#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
293 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
356 294
357#define MFP_CFG(pin, af) \ 295#define MFP_CFG(pin, af) \
358 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af)) 296 ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
297 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
359 298
360#define MFP_CFG_DRV(pin, af, drv) \ 299#define MFP_CFG_DRV(pin, af, drv) \
361 ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_DRV_MASK) |\ 300 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
362 ((MFP_##drv) << 10) | (MFP_##af)) 301 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
363 302
364#define MFP_CFG_LPM(pin, af, lpm) \ 303#define MFP_CFG_LPM(pin, af, lpm) \
365 ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_LPM_MASK) |\ 304 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
366 (((MFP_LPM_##lpm) & 0x3) << 7) |\ 305 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
367 (((MFP_LPM_##lpm) & 0x4) << 12) |\
368 (((MFP_LPM_##lpm) & 0x8) << 10) |\
369 (MFP_##af))
370 306
371#define MFP_CFG_X(pin, af, drv, lpm) \ 307#define MFP_CFG_X(pin, af, drv, lpm) \
372 ((MFP_PIN_##pin << 16) |\ 308 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
373 (MFPR_DEFAULT & ~(MFPR_DRV_MASK | MFPR_LPM_MASK)) |\ 309 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
374 ((MFP_##drv) << 10) | (MFP_##af) |\
375 (((MFP_LPM_##lpm) & 0x3) << 7) |\
376 (((MFP_LPM_##lpm) & 0x4) << 12) |\
377 (((MFP_LPM_##lpm) & 0x8) << 10))
378
379/* common MFP configurations - processor specific ones defined
380 * in mfp-pxa3xx.h
381 */
382#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
383#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
384#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
385#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
386#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
387#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
388#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
389#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
390#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
391#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
392#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
393#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
394#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
395#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
396#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
397#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
398#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
399#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
400#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
401#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
402#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
403#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
404#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
405#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
406#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
407#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
408#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
409#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
410#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
411#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
412#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
413#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
414#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
415#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
416#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
417#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
418#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
419#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
420#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
421#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
422#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
423#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
424#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
425#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
426#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
427#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
428
429#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
430#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
431
432#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
433#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
434#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
435
436#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
437
438#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
439#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
440#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
441#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
442#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
443#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
444#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
445#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
446#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
447#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
448#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
449#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
450#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
451#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
452#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
453#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
454#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
455#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
456#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
457#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
458#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
459#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
460#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
461#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
462#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
463#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
464#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
465#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
466#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
467#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
468#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
469#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
470#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
471#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
472#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
473#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
474#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
475#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
476#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
477#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
478#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
479#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
480#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
481#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
482#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
483#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
484#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
485#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
486#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
487#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
488#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
489#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
490#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
491#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
492#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
493#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
494#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
495#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
496#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
497#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
498#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
499#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
500#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
501#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
502#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
503
504#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
505#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
506#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
507#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
508#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
509#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
510#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
511
512/*
513 * each MFP pin will have a MFPR register, since the offset of the
514 * register varies between processors, the processor specific code
515 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
516 *
517 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
518 * structure, which represents a range of MFP pins from "start" to
519 * "end", with the offset begining at "offset", to define a single
520 * pin, let "end" = -1
521 *
522 * use
523 *
524 * MFP_ADDR_X() to define a range of pins
525 * MFP_ADDR() to define a single pin
526 * MFP_ADDR_END to signal the end of pin offset definitions
527 */
528struct pxa3xx_mfp_addr_map {
529 unsigned int start;
530 unsigned int end;
531 unsigned long offset;
532};
533
534#define MFP_ADDR_X(start, end, offset) \
535 { MFP_PIN_##start, MFP_PIN_##end, offset }
536
537#define MFP_ADDR(pin, offset) \
538 { MFP_PIN_##pin, -1, offset }
539
540#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
541
542struct pxa3xx_mfp_pin {
543 unsigned long mfpr_off; /* MFPRxx register offset */
544 unsigned long mfpr_val; /* MFPRxx register value */
545};
546
547/*
548 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
549 * to the MFPR register
550 */
551unsigned long pxa3xx_mfp_read(int mfp);
552void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
553
554/*
555 * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
556 * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
557 * pxa3xx_mfp_set_lpm - set MFP low power mode state
558 * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
559 *
560 * use these functions to override/change the default configuration
561 * done by pxa3xx_mfp_set_config(s)
562 */
563void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
564void pxa3xx_mfp_set_rdh(int mfp, int rdh);
565void pxa3xx_mfp_set_lpm(int mfp, int lpm);
566void pxa3xx_mfp_set_edge(int mfp, int edge);
567
568/*
569 * pxa3xx_mfp_config - configure the MFPR registers
570 *
571 * used by board specific initialization code
572 */
573void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
574
575/*
576 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
577 * index and MFPR register offset
578 *
579 * used by processor specific code
580 */
581void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
582void __init pxa3xx_init_mfp(void);
583 310
584#endif /* __ASM_ARCH_MFP_H */ 311#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index ef4f570381d1..6d1304c9270f 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -17,5 +17,7 @@ struct pxamci_platform_data {
17}; 17};
18 18
19extern void pxa_set_mci_info(struct pxamci_platform_data *info); 19extern void pxa_set_mci_info(struct pxamci_platform_data *info);
20extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
21extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
20 22
21#endif 23#endif
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h
new file mode 100644
index 000000000000..7beae1472c3e
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm027.h
@@ -0,0 +1,75 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pcm027.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * Definitions of CPU card resources only
24 */
25
26/* I2C RTC */
27#define PCM027_RTC_IRQ_GPIO 0
28#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
29#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
30#define ADR_PCM027_RTC 0x51 /* I2C address */
31
32/* I2C EEPROM */
33#define ADR_PCM027_EEPROM 0x54 /* I2C address */
34
35/* Ethernet chip (SMSC91C111) */
36#define PCM027_ETH_IRQ_GPIO 52
37#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
38#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING
39#define PCM027_ETH_PHYS PXA_CS5_PHYS
40#define PCM027_ETH_SIZE (1*1024*1024)
41
42/* CAN controller SJA1000 (unsupported yet) */
43#define PCM027_CAN_IRQ_GPIO 114
44#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
45#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
46#define PCM027_CAN_PHYS 0x22000000
47#define PCM027_CAN_SIZE 0x100
48
49/* SPI GPIO expander (unsupported yet) */
50#define PCM027_EGPIO_IRQ_GPIO 27
51#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
52#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
53#define PCM027_EGPIO_CS 24
54/*
55 * TODO: Switch this pin from dedicated usage to GPIO if
56 * more than the MAX7301 device is connected to this SPI bus
57 */
58#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD
59
60/* Flash memory */
61#define PCM027_FLASH_PHYS 0x00000000
62#define PCM027_FLASH_SIZE 0x02000000
63
64/* onboard LEDs connected to GPIO */
65#define PCM027_LED_CPU 90
66#define PCM027_LED_HEARD_BEAT 91
67
68/*
69 * This CPU module needs a baseboard to work. After basic initializing
70 * its own devices, it calls baseboard's init function.
71 * TODO: Add your own basebaord init function and call it from
72 * inside pcm027_init(). This example here is for the developmen board.
73 * Refer pcm990-baseboard.c
74 */
75extern void pcm990_baseboard_init(void);
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
new file mode 100644
index 000000000000..b699d0d7bdb2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h
@@ -0,0 +1,275 @@
1/*
2 * include/asm-arm/arch-pxa/pcm990_baseboard.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <asm/arch/pcm027.h>
23
24/*
25 * definitions relevant only when the PCM-990
26 * development base board is in use
27 */
28
29/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
30#define PCM990_CTRL_INT_IRQ_GPIO 9
31#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
32#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
34#define PCM990_CTRL_BASE 0xea000000
35#define PCM990_CTRL_SIZE (1*1024*1024)
36
37#define PCM990_CTRL_PWR_IRQ_GPIO 14
38#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
39#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
40
41/* visible CPLD (U7) registers */
42#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
43#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
44#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
45#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
46
47#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
48#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
49#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
50#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
51
52#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
53#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
54#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
55#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
56
57#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
58#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
59#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
60#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
61#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
62
63#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
64#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
65
66#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
67#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
68#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
69#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
70#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
71
72#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */
73#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
74#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
75#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
76#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
77
78#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */
79#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
80#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
81#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
82#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
83
84#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
85#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
86#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
87#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
88#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
89
90#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
91#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
92#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
93#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
94
95#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
96#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
97#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
98
99#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
100#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
101#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
102#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
103#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
104
105#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
106#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
107
108#ifndef __ASSEMBLY__
109# define __PCM990_CTRL_REG(x) \
110 (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
111#else
112# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
113#endif
114
115#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
116#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
117#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
118#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
119#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
120#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
121#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
122#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
123#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
124#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
125#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
126#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
127#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
128#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
129
130
131/*
132 * IDE
133 */
134#define PCM990_IDE_IRQ_GPIO 13
135#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
136#define PCM990_IDE_IRQ_EDGE IRQT_RISING
137#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
138#define PCM990_IDE_PLD_BASE 0xee000000
139#define PCM990_IDE_PLD_SIZE (1*1024*1024)
140
141/* visible CPLD (U6) registers */
142#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
143#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
144#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
145
146#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
147#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
148#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
149#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
150
151#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
152#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
153#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
154#define PCM990_IDE_RDY 0x0008 /* RDY */
155
156#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
157#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
158#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
159#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
160
161#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
162#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
163#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
164#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
165
166#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
167#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
168
169#ifndef __ASSEMBLY__
170# define __PCM990_IDE_PLD_REG(x) \
171 (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
172#else
173# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
174#endif
175
176#define PCM990_IDE0 \
177 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
178#define PCM990_IDE1 \
179 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
180#define PCM990_IDE2 \
181 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
182#define PCM990_IDE3 \
183 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
184#define PCM990_IDE4 \
185 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
186
187/*
188 * Compact Flash
189 */
190#define PCM990_CF_IRQ_GPIO 11
191#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
192#define PCM990_CF_IRQ_EDGE IRQT_RISING
193
194#define PCM990_CF_CD_GPIO 12
195#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
196#define PCM990_CF_CD_EDGE IRQT_RISING
197
198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
199#define PCM990_CF_PLD_BASE 0xef000000
200#define PCM990_CF_PLD_SIZE (1*1024*1024)
201#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
202#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
203
204/* visible CPLD (U6) registers */
205#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
206#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
207#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
208#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
209#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
210
211#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
212#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
213#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
214
215#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
216#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
217#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
218#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
219
220#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
221#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
222#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
223#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
224#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
225
226#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
227#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
228#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
229#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
230#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
231
232#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
233#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
234#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
235#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
236#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
237
238#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
239#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
240#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
241
242#ifndef __ASSEMBLY__
243# define __PCM990_CF_PLD_REG(x) \
244 (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
245#else
246# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
247#endif
248
249#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
250#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
251#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
252#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
253#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
254#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
255#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
256
257/*
258 * Wolfson AC97 Touch
259 */
260#define PCM990_AC97_IRQ_GPIO 10
261#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
262#define PCM990_AC97_IRQ_EDGE IRQT_RISING
263
264/*
265 * MMC phyCORE
266 */
267#define PCM990_MMC0_IRQ_GPIO 9
268#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
269#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
270
271/*
272 * USB phyCore
273 */
274#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
275#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 1bd398da07da..442494d71f12 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1597,176 +1597,10 @@
1597#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 1597#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1598#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 1598#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1599 1599
1600
1601/* 1600/*
1602 * SSP Serial Port Registers 1601 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1603 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
1604 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
1605 */ 1602 */
1606 1603
1607 /* Common PXA2xx bits first */
1608#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
1609#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
1610#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
1611#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
1612#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
1613#define SSCR0_National (0x2 << 4) /* National Microwire */
1614#define SSCR0_ECS (1 << 6) /* External clock select */
1615#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1616#if defined(CONFIG_PXA25x)
1617#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1618#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1619#elif defined(CONFIG_PXA27x)
1620#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
1621#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
1622#define SSCR0_EDSS (1 << 20) /* Extended data size select */
1623#define SSCR0_NCS (1 << 21) /* Network clock select */
1624#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
1625#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
1626#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
1627#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
1628#define SSCR0_ADC (1 << 30) /* Audio clock select */
1629#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
1630#endif
1631
1632#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1633#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
1634#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
1635#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
1636#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1637#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
1638#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
1639#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1640#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
1641#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1642
1643#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
1644#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
1645#define SSSR_BSY (1 << 4) /* SSP Busy */
1646#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
1647#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
1648#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
1649
1650#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
1651#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
1652#define SSCR0_NCS (1 << 21) /* Network Clock Select */
1653#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
1654
1655/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
1656#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
1657#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
1658#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
1659#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
1660#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
1661#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
1662#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
1663#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
1664#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
1665#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
1666#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
1667#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
1668#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
1669#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
1670#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
1671#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
1672#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
1673#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
1674
1675#define SSSR_BCE (1 << 23) /* Bit Count Error */
1676#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
1677#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
1678#define SSSR_EOC (1 << 20) /* End Of Chain */
1679#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
1680#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
1681
1682#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
1683#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
1684#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
1685#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
1686#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
1687#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
1688#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
1689#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
1690#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
1691
1692#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
1693#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
1694#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
1695
1696#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
1697#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
1698#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
1699#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
1700#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
1701
1702/* Support existing PXA25x drivers */
1703#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
1704#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
1705#define SSSR SSSR_P1 /* SSP Status Register */
1706#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
1707#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1708
1709/* PXA27x ports */
1710#if defined (CONFIG_PXA27x)
1711#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1712#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1713#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
1714#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
1715#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
1716#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
1717#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
1718#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
1719#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
1720#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
1721#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1722#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
1723#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
1724#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
1725#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
1726#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
1727#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
1728#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
1729#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
1730#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
1731#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
1732#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1733#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
1734#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
1735#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
1736#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
1737#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
1738#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
1739#else /* PXA255 (only port 2) and PXA26x ports*/
1740#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1741#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1742#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
1743#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
1744#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
1745#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
1746#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1747#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
1748#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
1749#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
1750#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
1751#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
1752#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
1753#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1754#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
1755#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
1756#endif
1757
1758#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
1759#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
1760#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
1761#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
1762#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
1763#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
1764#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
1765#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
1766#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
1767#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
1768#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
1769
1770/* 1604/*
1771 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h 1605 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
1772 */ 1606 */
@@ -2014,71 +1848,8 @@
2014 1848
2015#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 1849#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2016 1850
2017/*
2018 * Memory controller
2019 */
2020
2021#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
2022#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
2023#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
2024#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
2025#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
2026#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2027#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2028#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
2029#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
2030#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
2031#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
2032#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2033#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
2034#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2035#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
2036#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
2037#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2038
2039/*
2040 * More handy macros for PCMCIA
2041 *
2042 * Arg is socket number
2043 */
2044#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
2045#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
2046#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
2047
2048/* MECR register defines */
2049#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
2050#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
2051
2052#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
2053#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2054#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2055#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2056#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2057#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2058#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2059#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2060#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2061#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2062#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2063#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2064#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2065#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2066
2067
2068#ifdef CONFIG_PXA27x 1851#ifdef CONFIG_PXA27x
2069 1852
2070#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
2071
2072#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
2073#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
2074#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
2075#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
2076#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
2077#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
2078#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
2079#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2080#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2081
2082/* 1853/*
2083 * Keypad 1854 * Keypad
2084 */ 1855 */
@@ -2135,74 +1906,6 @@
2135#define KPAS_SO (0x1 << 31) 1906#define KPAS_SO (0x1 << 31)
2136#define KPASMKPx_SO (0x1 << 31) 1907#define KPASMKPx_SO (0x1 << 31)
2137 1908
2138/*
2139 * UHC: USB Host Controller (OHCI-like) register definitions
2140 */
2141#define UHC_BASE_PHYS (0x4C000000)
2142#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2143#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2144#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2145#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2146#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2147#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2148#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2149#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2150#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2151#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2152#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2153#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2154#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2155#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2156#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2157#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2158#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2159#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2160
2161#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2162#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2163
2164#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2165#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2166#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2167#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2168#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2169
2170#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2171#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2172#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2173#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2174#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2175#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2176#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2177#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2178#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2179#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2180
2181#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2182#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2183#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2184#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2185#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2186#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2187#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2188#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2189#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2190#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2191#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2192#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2193
2194#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2195#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2196#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2197#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2198#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2199#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2200 Interrupt Enable*/
2201#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2202#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2203
2204#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2205
2206/* Camera Interface */ 1909/* Camera Interface */
2207#define CICR0 __REG(0x50000000) 1910#define CICR0 __REG(0x50000000)
2208#define CICR1 __REG(0x50000004) 1911#define CICR1 __REG(0x50000004)
@@ -2350,6 +2053,77 @@
2350 2053
2351#endif 2054#endif
2352 2055
2056#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
2057/*
2058 * UHC: USB Host Controller (OHCI-like) register definitions
2059 */
2060#define UHC_BASE_PHYS (0x4C000000)
2061#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2062#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2063#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2064#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2065#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2066#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2067#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2068#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2069#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2070#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2071#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2072#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2073#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2074#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2075#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2076#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2077#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2078#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2079
2080#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2081#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2082
2083#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2084#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2085#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2086#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2087#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2088
2089#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2090#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2091#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2092#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2093#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2094#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2095#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2096#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2097#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2098#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2099
2100#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2101#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2102#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2103#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2104#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2105#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2106#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2107#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2108#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2109#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2110#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2111#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2112
2113#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2114#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2115#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2116#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2117#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2118#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2119 Interrupt Enable*/
2120#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2121#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2122
2123#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2124
2125#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
2126
2353/* PWRMODE register M field values */ 2127/* PWRMODE register M field values */
2354 2128
2355#define PWRMODE_IDLE 0x1 2129#define PWRMODE_IDLE 0x1
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
new file mode 100644
index 000000000000..9553b54fa5bc
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -0,0 +1,84 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
3 *
4 * Taken from pxa-regs.h by Russell King
5 *
6 * Author: Nicolas Pitre
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H
16
17/*
18 * Memory controller
19 */
20
21#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
22#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
23#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
24#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
25#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
26#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
27#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
28#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
29#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
30#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
31#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
32#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
33#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
34#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
35#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
36#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
37#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
38
39/*
40 * More handy macros for PCMCIA
41 *
42 * Arg is socket number
43 */
44#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
45#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
46#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
47
48/* MECR register defines */
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
55#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
56#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
57#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
58#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
59#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
60#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
61#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
62#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
63#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
64#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
65#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
66
67
68#ifdef CONFIG_PXA27x
69
70#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
71
72#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
73#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
74#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
75#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
76#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
77#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
78#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
79#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
80#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
81
82#endif
83
84#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index acc7ec7a84a1..3459fb26ce97 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -22,32 +22,8 @@
22#define PXA2XX_CS_ASSERT (0x01) 22#define PXA2XX_CS_ASSERT (0x01)
23#define PXA2XX_CS_DEASSERT (0x02) 23#define PXA2XX_CS_DEASSERT (0x02)
24 24
25#if defined(CONFIG_PXA25x)
26#define CLOCK_SPEED_HZ 3686400
27#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
28#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
29#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
30#elif defined(CONFIG_PXA27x)
31#define CLOCK_SPEED_HZ 13000000
32#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
33#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
34#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
35#endif
36
37#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
38#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
39#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
40
41enum pxa_ssp_type {
42 SSP_UNDEFINED = 0,
43 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
44 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
45 PXA27x_SSP,
46};
47
48/* device.platform_data for SSP controller devices */ 25/* device.platform_data for SSP controller devices */
49struct pxa2xx_spi_master { 26struct pxa2xx_spi_master {
50 enum pxa_ssp_type ssp_type;
51 u32 clock_enable; 27 u32 clock_enable;
52 u16 num_chipselect; 28 u16 num_chipselect;
53 u8 enable_dma; 29 u8 enable_dma;
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 3900a0ca0bc0..66d54119757c 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -14,6 +14,92 @@
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15 15
16/* 16/*
17 * Slave Power Managment Unit
18 */
19#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
20#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
21#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
22#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
23#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
24#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
25#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
26#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
27#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
28#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
29#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
30#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
31#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
32#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
33
34/*
35 * Application Subsystem Configuration bits.
36 */
37#define ASCR_RDH (1 << 31)
38#define ASCR_D1S (1 << 2)
39#define ASCR_D2S (1 << 1)
40#define ASCR_D3S (1 << 0)
41
42/*
43 * Application Reset Status bits.
44 */
45#define ARSR_GPR (1 << 3)
46#define ARSR_LPMR (1 << 2)
47#define ARSR_WDT (1 << 1)
48#define ARSR_HWR (1 << 0)
49
50/*
51 * Application Subsystem Wake-Up bits.
52 */
53#define ADXER_WRTC (1 << 31) /* RTC */
54#define ADXER_WOST (1 << 30) /* OS Timer */
55#define ADXER_WTSI (1 << 29) /* Touchscreen */
56#define ADXER_WUSBH (1 << 28) /* USB host */
57#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
58#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
59#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
60#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
61#define ADXER_WKP (1 << 21) /* Keypad */
62#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
63#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
64#define ADXER_WOTG (1 << 16) /* USBOTG input */
65#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
66#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
67#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
68#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
69#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
70#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
71#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
72#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
73#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
74#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
75#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
76#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
77#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
78#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
79#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
80#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
81
82/*
83 * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
84 */
85#define ADXR_L2 (1 << 8)
86#define ADXR_R5 (1 << 5)
87#define ADXR_R4 (1 << 4)
88#define ADXR_R3 (1 << 3)
89#define ADXR_R2 (1 << 2)
90#define ADXR_R1 (1 << 1)
91#define ADXR_R0 (1 << 0)
92
93/*
94 * Values for PWRMODE CP15 register
95 */
96#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
97#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
98#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
99#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
100#define PXA3xx_PM_S0D0C1 0x01
101
102/*
17 * Application Subsystem Clock 103 * Application Subsystem Clock
18 */ 104 */
19#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ 105#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
new file mode 100644
index 000000000000..991cb688db75
--- /dev/null
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -0,0 +1,112 @@
1#ifndef __ASM_ARCH_REGS_SSP_H
2#define __ASM_ARCH_REGS_SSP_H
3
4/*
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */
9
10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23/* Common PXA2xx bits first */
24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
26#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
27#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
28#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
29#define SSCR0_National (0x2 << 4) /* National Microwire */
30#define SSCR0_ECS (1 << 6) /* External clock select */
31#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
32#if defined(CONFIG_PXA25x)
33#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
34#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
35#elif defined(CONFIG_PXA27x)
36#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
37#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
38#define SSCR0_EDSS (1 << 20) /* Extended data size select */
39#define SSCR0_NCS (1 << 21) /* Network clock select */
40#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
41#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
42#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
43#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
44#define SSCR0_ADC (1 << 30) /* Audio clock select */
45#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
46#endif
47
48#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
49#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
50#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
51#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
52#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
53#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
54#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
55#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
56#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
57#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
58
59#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
60#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
61#define SSSR_BSY (1 << 4) /* SSP Busy */
62#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
63#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
64#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
65
66#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
67#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
68#define SSCR0_NCS (1 << 21) /* Network Clock Select */
69#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
70
71/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
72#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
73#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
74#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
75#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
76#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
77#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
78#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
79#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
80#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
81#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
82#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
83#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
84#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
85#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
86#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
87#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
88#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
89#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
90
91#define SSSR_BCE (1 << 23) /* Bit Count Error */
92#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
93#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
94#define SSSR_EOC (1 << 20) /* End Of Chain */
95#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
96#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
97
98#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
99#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
100#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
101#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
102#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
103#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
104#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
105#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
106#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
107
108#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
109#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
110#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
111
112#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
index 2b0fe773213a..3b1d4a72d4d1 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/include/asm-arm/arch-pxa/sharpsl.h
@@ -16,7 +16,7 @@ int corgi_ssp_max1111_get(unsigned long data);
16 */ 16 */
17 17
18struct corgits_machinfo { 18struct corgits_machinfo {
19 unsigned long (*get_hsync_len)(void); 19 unsigned long (*get_hsync_invperiod)(void);
20 void (*put_hsync)(void); 20 void (*put_hsync)(void);
21 void (*wait_hsync)(void); 21 void (*wait_hsync)(void);
22}; 22};
diff --git a/include/asm-arm/arch-pxa/spitz.h b/include/asm-arm/arch-pxa/spitz.h
index 4953dd324d4d..bd14365f7ed5 100644
--- a/include/asm-arm/arch-pxa/spitz.h
+++ b/include/asm-arm/arch-pxa/spitz.h
@@ -156,5 +156,3 @@ extern struct platform_device spitzscoop_device;
156extern struct platform_device spitzscoop2_device; 156extern struct platform_device spitzscoop2_device;
157extern struct platform_device spitzssp_device; 157extern struct platform_device spitzssp_device;
158extern struct sharpsl_charger_machinfo spitz_pm_machinfo; 158extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
159
160extern void spitz_lcd_power(int on, struct fb_var_screeninfo *var);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
index ea200551a75f..a012882c9ee6 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -13,10 +13,37 @@
13 * PXA255 SSP, NSSP 13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP 14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3 15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4
16 */ 17 */
17 18
18#ifndef SSP_H 19#ifndef __ASM_ARCH_SSP_H
19#define SSP_H 20#define __ASM_ARCH_SSP_H
21
22#include <linux/list.h>
23
24enum pxa_ssp_type {
25 SSP_UNDEFINED = 0,
26 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
27 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
28 PXA27x_SSP,
29};
30
31struct ssp_device {
32 struct platform_device *pdev;
33 struct list_head node;
34
35 struct clk *clk;
36 void __iomem *mmio_base;
37 unsigned long phys_base;
38
39 const char *label;
40 int port_id;
41 int type;
42 int use_count;
43 int irq;
44 int drcmr_rx;
45 int drcmr_tx;
46};
20 47
21/* 48/*
22 * SSP initialisation flags 49 * SSP initialisation flags
@@ -31,6 +58,7 @@ struct ssp_state {
31}; 58};
32 59
33struct ssp_dev { 60struct ssp_dev {
61 struct ssp_device *ssp;
34 u32 port; 62 u32 port;
35 u32 mode; 63 u32 mode;
36 u32 flags; 64 u32 flags;
@@ -50,4 +78,6 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
50int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); 78int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
51void ssp_exit(struct ssp_dev *dev); 79void ssp_exit(struct ssp_dev *dev);
52 80
53#endif 81struct ssp_device *ssp_request(int port, const char *label);
82void ssp_free(struct ssp_device *);
83#endif /* __ASM_ARCH_SSP_H */
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 178aa2e073ac..dadf4c20b622 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -9,19 +9,21 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#define FFUART ((volatile unsigned long *)0x40100000) 12#include <linux/serial_reg.h>
13#define BTUART ((volatile unsigned long *)0x40200000) 13#include <asm/arch/pxa-regs.h>
14#define STUART ((volatile unsigned long *)0x40700000) 14
15#define HWUART ((volatile unsigned long *)0x41600000) 15#define __REG(x) ((volatile unsigned long *)x)
16 16
17#define UART FFUART 17#define UART FFUART
18 18
19 19
20static inline void putc(char c) 20static inline void putc(char c)
21{ 21{
22 while (!(UART[5] & 0x20)) 22 if (!(UART[UART_IER] & IER_UUE))
23 return;
24 while (!(UART[UART_LSR] & LSR_TDRQ))
23 barrier(); 25 barrier();
24 UART[0] = c; 26 UART[UART_TX] = c;
25} 27}
26 28
27/* 29/*
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index f58b59162b82..5f717d64ea7d 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -3,9 +3,18 @@
3 3
4#define ZYLONITE_ETH_PHYS 0x14000000 4#define ZYLONITE_ETH_PHYS 0x14000000
5 5
6#define EXT_GPIO(x) (128 + (x))
7
6/* the following variables are processor specific and initialized 8/* the following variables are processor specific and initialized
7 * by the corresponding zylonite_pxa3xx_init() 9 * by the corresponding zylonite_pxa3xx_init()
8 */ 10 */
11struct platform_mmc_slot {
12 int gpio_cd;
13 int gpio_wp;
14};
15
16extern struct platform_mmc_slot zylonite_mmc_slot[];
17
9extern int gpio_backlight; 18extern int gpio_backlight;
10extern int gpio_eth_irq; 19extern int gpio_eth_irq;
11 20
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 02:33:37 -0500