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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2009-06-11 08:19:11 -0400
committerIngo Molnar <mingo@elte.hu>2009-06-11 11:54:17 -0400
commit8be6e8f3c3a13900169f1141870562d0c723b010 (patch)
tree0041b2557561ada3566bd309f0b3153e31a9854c /include
parentf4dbfa8f3131a84257223393905f7efad0ca5996 (diff)
perf_counter: Rename L2 to LL cache
The top (fastest) and last level (biggest) caches are the most interesting ones, performance wise. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> [ Fixed the Nehalem LL table to LLC Reference/Miss events ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
-rw-r--r--include/linux/perf_counter.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/perf_counter.h b/include/linux/perf_counter.h
index 887df88a9c2a..20cf5af27ade 100644
--- a/include/linux/perf_counter.h
+++ b/include/linux/perf_counter.h
@@ -56,14 +56,14 @@ enum perf_hw_id {
56/* 56/*
57 * Generalized hardware cache counters: 57 * Generalized hardware cache counters:
58 * 58 *
59 * { L1-D, L1-I, L2, LLC, ITLB, DTLB, BPU } x 59 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x
60 * { read, write, prefetch } x 60 * { read, write, prefetch } x
61 * { accesses, misses } 61 * { accesses, misses }
62 */ 62 */
63enum perf_hw_cache_id { 63enum perf_hw_cache_id {
64 PERF_COUNT_HW_CACHE_L1D = 0, 64 PERF_COUNT_HW_CACHE_L1D = 0,
65 PERF_COUNT_HW_CACHE_L1I = 1, 65 PERF_COUNT_HW_CACHE_L1I = 1,
66 PERF_COUNT_HW_CACHE_L2 = 2, 66 PERF_COUNT_HW_CACHE_LL = 2,
67 PERF_COUNT_HW_CACHE_DTLB = 3, 67 PERF_COUNT_HW_CACHE_DTLB = 3,
68 PERF_COUNT_HW_CACHE_ITLB = 4, 68 PERF_COUNT_HW_CACHE_ITLB = 4,
69 PERF_COUNT_HW_CACHE_BPU = 5, 69 PERF_COUNT_HW_CACHE_BPU = 5,