drm/radeon: introduce kernel modesetting for radeon hardware

Add kernel modesetting support to radeon driver, use the ttm memory
manager to manage memory and DRM/GEM to provide userspace API.
In order to avoid backward compatibility issue and to allow clean
design and code the radeon kernel modesetting use different code path
than old radeon/drm driver.

When kernel modesetting is enabled the IOCTL of radeon/drm
driver are considered as invalid and an error message is printed
in the log and they return failure.

KMS enabled userspace will use new API to talk with the radeon/drm
driver. The new API provide functions to create/destroy/share/mmap
buffer object which are then managed by the kernel memory manager
(here TTM). In order to submit command to the GPU the userspace
provide a buffer holding the command stream, along this buffer
userspace have to provide a list of buffer object used by the
command stream. The kernel radeon driver will then place buffer
in GPU accessible memory and will update command stream to reflect
the position of the different buffers.

The kernel will also perform security check on command stream
provided by the user, we want to catch and forbid any illegal use
of the GPU such as DMA into random system memory or into memory
not owned by the process supplying the command stream. This part
of the code is still incomplete and this why we propose that patch
as a staging driver addition, future security might forbid current
experimental userspace to run.

This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX
(radeon up to X1950). Works is underway to provide support for R6XX,
R7XX and newer hardware (radeon from HD2XXX to HD4XXX).

Authors:
    Jerome Glisse <jglisse@redhat.com>
    Dave Airlie <airlied@redhat.com>
    Alex Deucher <alexdeucher@gmail.com>

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 130 insertions, 0 deletions

diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index fe3e3a4b4aed..41862e9a4c20 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -496,6 +496,16 @@ typedef struct {
 #define DRM_RADEON_SETPARAM   0x19
 #define DRM_RADEON_SURF_ALLOC 0x1a
 #define DRM_RADEON_SURF_FREE  0x1b
+/* KMS ioctl */
+#define DRM_RADEON_GEM_INFO             0x1c
+#define DRM_RADEON_GEM_CREATE           0x1d
+#define DRM_RADEON_GEM_MMAP             0x1e
+#define DRM_RADEON_GEM_PREAD            0x21
+#define DRM_RADEON_GEM_PWRITE           0x22
+#define DRM_RADEON_GEM_SET_DOMAIN       0x23
+#define DRM_RADEON_GEM_WAIT_IDLE        0x24
+#define DRM_RADEON_CS                   0x26
+#define DRM_RADEON_INFO                 0x27
 
 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -524,6 +534,17 @@ typedef struct {
 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
+/* KMS */
+#define DRM_IOCTL_RADEON_GEM_INFO       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
+#define DRM_IOCTL_RADEON_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
+#define DRM_IOCTL_RADEON_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
+#define DRM_IOCTL_RADEON_GEM_PREAD      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
+#define DRM_IOCTL_RADEON_GEM_PWRITE     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
+#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
+#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE  DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
+#define DRM_IOCTL_RADEON_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
+#define DRM_IOCTL_RADEON_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
+
 
 typedef struct drm_radeon_init {
         enum {
@@ -682,6 +703,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
+#define RADEON_PARAM_DEVICE_ID             16
 
 typedef struct drm_radeon_getparam {
         int param;
@@ -751,4 +773,112 @@ typedef struct drm_radeon_surface_free {
 #define DRM_RADEON_VBLANK_CRTC1         1
 #define DRM_RADEON_VBLANK_CRTC2         2
 
+/*
+ * Kernel modesetting world below.
+ */
+#define RADEON_GEM_DOMAIN_CPU           0x1
+#define RADEON_GEM_DOMAIN_GTT           0x2
+#define RADEON_GEM_DOMAIN_VRAM          0x4
+
+struct drm_radeon_gem_info {
+        uint64_t        gart_size;
+        uint64_t        vram_size;
+        uint64_t        vram_visible;
+};
+
+#define RADEON_GEM_NO_BACKING_STORE 1
+
+struct drm_radeon_gem_create {
+        uint64_t        size;
+        uint64_t        alignment;
+        uint32_t        handle;
+        uint32_t        initial_domain;
+        uint32_t        flags;
+};
+
+struct drm_radeon_gem_mmap {
+        uint32_t        handle;
+        uint32_t        pad;
+        uint64_t        offset;
+        uint64_t        size;
+        uint64_t        addr_ptr;
+};
+
+struct drm_radeon_gem_set_domain {
+        uint32_t        handle;
+        uint32_t        read_domains;
+        uint32_t        write_domain;
+};
+
+struct drm_radeon_gem_wait_idle {
+        uint32_t        handle;
+        uint32_t        pad;
+};
+
+struct drm_radeon_gem_busy {
+        uint32_t        handle;
+        uint32_t        busy;
+};
+
+struct drm_radeon_gem_pread {
+        /** Handle for the object being read. */
+        uint32_t handle;
+        uint32_t pad;
+        /** Offset into the object to read from */
+        uint64_t offset;
+        /** Length of data to read */
+        uint64_t size;
+        /** Pointer to write the data into. */
+        /* void *, but pointers are not 32/64 compatible */
+        uint64_t data_ptr;
+};
+
+struct drm_radeon_gem_pwrite {
+        /** Handle for the object being written to. */
+        uint32_t handle;
+        uint32_t pad;
+        /** Offset into the object to write to */
+        uint64_t offset;
+        /** Length of data to write */
+        uint64_t size;
+        /** Pointer to read the data from. */
+        /* void *, but pointers are not 32/64 compatible */
+        uint64_t data_ptr;
+};
+
+#define RADEON_CHUNK_ID_RELOCS  0x01
+#define RADEON_CHUNK_ID_IB      0x02
+
+struct drm_radeon_cs_chunk {
+        uint32_t                chunk_id;
+        uint32_t                length_dw;
+        uint64_t                chunk_data;
+};
+
+struct drm_radeon_cs_reloc {
+        uint32_t                handle;
+        uint32_t                read_domains;
+        uint32_t                write_domain;
+        uint32_t                flags;
+};
+
+struct drm_radeon_cs {
+        uint32_t                num_chunks;
+        uint32_t                cs_id;
+        /* this points to uint64_t * which point to cs chunks */
+        uint64_t                chunks;
+        /* updates to the limits after this CS ioctl */
+        uint64_t                gart_limit;
+        uint64_t                vram_limit;
+};
+
+#define RADEON_INFO_DEVICE_ID           0x00
+#define RADEON_INFO_NUM_GB_PIPES        0x01
+
+struct drm_radeon_info {
+        uint32_t                request;
+        uint32_t                pad;
+        uint64_t                value;
+};
+
 #endif