diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-12-10 12:26:17 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-12-10 19:53:32 -0500 |
commit | 6c34bc2976b30dc8b56392c020e25bae1f363cab (patch) | |
tree | a739c6f82ffd3a3658220b9cc0f9daedb88d683c /include | |
parent | 8b1fae4e4200388b64dd88065639413cb3f1051c (diff) |
Revert "radeonfb: accelerate imageblit and other improvements"
This reverts commit b1ee26bab14886350ba12a5c10cbc0696ac679bf, along with
the "fixes" for it that all just caused problems:
- c4c6fa9891f3d1bcaae4f39fb751d5302965b566 "radeonfb: fix problem with
color expansion & alignment"
- f3179748a157c21d44d929fd3779421ebfbeaa93 "radeonfb: Disable new color
expand acceleration unless explicitely enabled"
because even when disabled, it breaks for people. See
http://bugzilla.kernel.org/show_bug.cgi?id=12191
for the latest example.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Cc: James Cloos <cloos@jhcloos.com>
Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
Cc: Krzysztof Helt <krzysztof.h1@poczta.fm>
Cc: Jean-Luc Coulon <jean.luc.coulon@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/video/radeon.h | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/include/video/radeon.h b/include/video/radeon.h index d5dcaf154ba4..1cd09cc5b169 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h | |||
@@ -525,9 +525,6 @@ | |||
525 | #define CRTC_DISPLAY_DIS (1 << 10) | 525 | #define CRTC_DISPLAY_DIS (1 << 10) |
526 | #define CRTC_CRT_ON (1 << 15) | 526 | #define CRTC_CRT_ON (1 << 15) |
527 | 527 | ||
528 | /* DSTCACHE_MODE bits constants */ | ||
529 | #define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) | ||
530 | #define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17) | ||
531 | 528 | ||
532 | /* DSTCACHE_CTLSTAT bit constants */ | 529 | /* DSTCACHE_CTLSTAT bit constants */ |
533 | #define RB2D_DC_FLUSH_2D (1 << 0) | 530 | #define RB2D_DC_FLUSH_2D (1 << 0) |
@@ -869,10 +866,15 @@ | |||
869 | #define GMC_DST_16BPP_YVYU422 0x00000c00 | 866 | #define GMC_DST_16BPP_YVYU422 0x00000c00 |
870 | #define GMC_DST_32BPP_AYUV444 0x00000e00 | 867 | #define GMC_DST_32BPP_AYUV444 0x00000e00 |
871 | #define GMC_DST_16BPP_ARGB4444 0x00000f00 | 868 | #define GMC_DST_16BPP_ARGB4444 0x00000f00 |
869 | #define GMC_SRC_MONO 0x00000000 | ||
870 | #define GMC_SRC_MONO_LBKGD 0x00001000 | ||
871 | #define GMC_SRC_DSTCOLOR 0x00003000 | ||
872 | #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 | 872 | #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 |
873 | #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 | 873 | #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 |
874 | #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 | 874 | #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 |
875 | #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 | 875 | #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 |
876 | #define GMC_DP_SRC_RECT 0x02000000 | ||
877 | #define GMC_DP_SRC_HOST 0x03000000 | ||
876 | #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 | 878 | #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 |
877 | #define GMC_3D_FCN_EN_CLR 0x00000000 | 879 | #define GMC_3D_FCN_EN_CLR 0x00000000 |
878 | #define GMC_3D_FCN_EN_SET 0x08000000 | 880 | #define GMC_3D_FCN_EN_SET 0x08000000 |
@@ -883,9 +885,6 @@ | |||
883 | #define GMC_WRITE_MASK_LEAVE 0x00000000 | 885 | #define GMC_WRITE_MASK_LEAVE 0x00000000 |
884 | #define GMC_WRITE_MASK_SET 0x40000000 | 886 | #define GMC_WRITE_MASK_SET 0x40000000 |
885 | #define GMC_CLR_CMP_CNTL_DIS (1 << 28) | 887 | #define GMC_CLR_CMP_CNTL_DIS (1 << 28) |
886 | #define GMC_SRC_DATATYPE_MASK (3 << 12) | ||
887 | #define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) | ||
888 | #define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) | ||
889 | #define GMC_SRC_DATATYPE_COLOR (3 << 12) | 888 | #define GMC_SRC_DATATYPE_COLOR (3 << 12) |
890 | #define ROP3_S 0x00cc0000 | 889 | #define ROP3_S 0x00cc0000 |
891 | #define ROP3_SRCCOPY 0x00cc0000 | 890 | #define ROP3_SRCCOPY 0x00cc0000 |
@@ -894,7 +893,6 @@ | |||
894 | #define DP_SRC_SOURCE_MASK (7 << 24) | 893 | #define DP_SRC_SOURCE_MASK (7 << 24) |
895 | #define GMC_BRUSH_NONE (15 << 4) | 894 | #define GMC_BRUSH_NONE (15 << 4) |
896 | #define DP_SRC_SOURCE_MEMORY (2 << 24) | 895 | #define DP_SRC_SOURCE_MEMORY (2 << 24) |
897 | #define DP_SRC_SOURCE_HOST_DATA (3 << 24) | ||
898 | #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 | 896 | #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 |
899 | 897 | ||
900 | /* DP_MIX bit constants */ | 898 | /* DP_MIX bit constants */ |
@@ -980,12 +978,6 @@ | |||
980 | #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) | 978 | #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) |
981 | #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) | 979 | #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) |
982 | 980 | ||
983 | /* RBBM_GUICNTL constants */ | ||
984 | #define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0) | ||
985 | #define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0) | ||
986 | #define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0) | ||
987 | #define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0) | ||
988 | |||
989 | /* masks */ | 981 | /* masks */ |
990 | 982 | ||
991 | #define CONFIG_MEMSIZE_MASK 0x1f000000 | 983 | #define CONFIG_MEMSIZE_MASK 0x1f000000 |