diff options
author | David S. Miller <davem@davemloft.net> | 2005-07-24 22:36:13 -0400 |
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committer | David S. Miller <davem@davemloft.net> | 2005-07-24 22:36:13 -0400 |
commit | cdd5186f753b23ab51f86679bdc4cc698ab0b893 (patch) | |
tree | 9de741421a4303d936687784d5a703641962c5d7 /include | |
parent | c5019a578f18cf3a76829626e91e5469dbd4a738 (diff) |
[SPARC64]: Privatize sun5_timer.
It is only used by some localized code in irq.c, and also
delete enable_prom_timer() as that is totally unused.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-sparc64/timer.h | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h index ba33a2b6b7bd..edc8e08c3a39 100644 --- a/include/asm-sparc64/timer.h +++ b/include/asm-sparc64/timer.h | |||
@@ -9,49 +9,8 @@ | |||
9 | 9 | ||
10 | #include <linux/types.h> | 10 | #include <linux/types.h> |
11 | 11 | ||
12 | /* How timers work: | ||
13 | * | ||
14 | * On uniprocessors we just use counter zero for the system wide | ||
15 | * ticker, this performs thread scheduling, clock book keeping, | ||
16 | * and runs timer based events. Previously we used the Ultra | ||
17 | * %tick interrupt for this purpose. | ||
18 | * | ||
19 | * On multiprocessors we pick one cpu as the master level 10 tick | ||
20 | * processor. Here this counter zero tick handles clock book | ||
21 | * keeping and timer events only. Each Ultra has it's level | ||
22 | * 14 %tick interrupt set to fire off as well, even the master | ||
23 | * tick cpu runs this locally. This ticker performs thread | ||
24 | * scheduling, system/user tick counting for the current thread, | ||
25 | * and also profiling if enabled. | ||
26 | */ | ||
27 | |||
28 | #include <linux/config.h> | 12 | #include <linux/config.h> |
29 | 13 | ||
30 | /* Two timers, traditionally steered to PIL's 10 and 14 respectively. | ||
31 | * But since INO packets are used on sun5, we could use any PIL level | ||
32 | * we like, however for now we use the normal ones. | ||
33 | * | ||
34 | * The 'reg' and 'interrupts' properties for these live in nodes named | ||
35 | * 'counter-timer'. The first of three 'reg' properties describe where | ||
36 | * the sun5_timer registers are. The other two I have no idea. (XXX) | ||
37 | */ | ||
38 | struct sun5_timer { | ||
39 | u64 count0; | ||
40 | u64 limit0; | ||
41 | u64 count1; | ||
42 | u64 limit1; | ||
43 | }; | ||
44 | |||
45 | #define SUN5_LIMIT_ENABLE 0x80000000 | ||
46 | #define SUN5_LIMIT_TOZERO 0x40000000 | ||
47 | #define SUN5_LIMIT_ZRESTART 0x20000000 | ||
48 | #define SUN5_LIMIT_CMASK 0x1fffffff | ||
49 | |||
50 | /* Given a HZ value, set the limit register to so that the timer IRQ | ||
51 | * gets delivered that often. | ||
52 | */ | ||
53 | #define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz)) | ||
54 | |||
55 | struct sparc64_tick_ops { | 14 | struct sparc64_tick_ops { |
56 | void (*init_tick)(unsigned long); | 15 | void (*init_tick)(unsigned long); |
57 | unsigned long (*get_tick)(void); | 16 | unsigned long (*get_tick)(void); |