diff options
author | Becky Bruce <becky.bruce@freescale.com> | 2007-05-09 15:31:19 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-05-10 00:00:37 -0400 |
commit | 828765269efaafbf8973bb6e41d10970ee4effc3 (patch) | |
tree | 8a9339789b562d2bb086e7926f390207350398cc /include | |
parent | c9ec87e5121b1777172fc07a14322ebb32a04ba9 (diff) |
[POWERPC] Move reg_booke.h to include/asm-powerpc
This patch moves a copy of reg_booke.h to include/asm-powerpc and fixes
up the ifdef protection.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-powerpc/reg_booke.h | 469 |
1 files changed, 469 insertions, 0 deletions
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h new file mode 100644 index 000000000000..064405c207bf --- /dev/null +++ b/include/asm-powerpc/reg_booke.h | |||
@@ -0,0 +1,469 @@ | |||
1 | /* | ||
2 | * Contains register definitions common to the Book E PowerPC | ||
3 | * specification. Notice that while the IBM-40x series of CPUs | ||
4 | * are not true Book E PowerPCs, they borrowed a number of features | ||
5 | * before Book E was finalized, and are included here as well. Unfortunatly, | ||
6 | * they sometimes used different locations than true Book E CPUs did. | ||
7 | */ | ||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef __ASM_POWERPC_REG_BOOKE_H__ | ||
10 | #define __ASM_POWERPC_REG_BOOKE_H__ | ||
11 | |||
12 | #ifndef __ASSEMBLY__ | ||
13 | /* Performance Monitor Registers */ | ||
14 | #define mfpmr(rn) ({unsigned int rval; \ | ||
15 | asm volatile("mfpmr %0," __stringify(rn) \ | ||
16 | : "=r" (rval)); rval;}) | ||
17 | #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) | ||
18 | #endif /* __ASSEMBLY__ */ | ||
19 | |||
20 | /* Freescale Book E Performance Monitor APU Registers */ | ||
21 | #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ | ||
22 | #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ | ||
23 | #define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ | ||
24 | #define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ | ||
25 | #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ | ||
26 | #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ | ||
27 | #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ | ||
28 | #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ | ||
29 | |||
30 | #define PMLCA_FC 0x80000000 /* Freeze Counter */ | ||
31 | #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ | ||
32 | #define PMLCA_FCU 0x20000000 /* Freeze in User */ | ||
33 | #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ | ||
34 | #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ | ||
35 | #define PMLCA_CE 0x04000000 /* Condition Enable */ | ||
36 | |||
37 | #define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ | ||
38 | #define PMLCA_EVENT_SHIFT 16 | ||
39 | |||
40 | #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ | ||
41 | #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ | ||
42 | #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ | ||
43 | #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ | ||
44 | |||
45 | #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ | ||
46 | #define PMLCB_THRESHMUL_SHIFT 8 | ||
47 | |||
48 | #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ | ||
49 | #define PMLCB_THRESHOLD_SHIFT 0 | ||
50 | |||
51 | #define PMRN_PMGC0 0x190 /* PM Global Control 0 */ | ||
52 | |||
53 | #define PMGC0_FAC 0x80000000 /* Freeze all Counters */ | ||
54 | #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ | ||
55 | #define PMGC0_FCECE 0x20000000 /* Freeze countes on | ||
56 | Enabled Condition or | ||
57 | Event */ | ||
58 | |||
59 | #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ | ||
60 | #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ | ||
61 | #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ | ||
62 | #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ | ||
63 | #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ | ||
64 | #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ | ||
65 | #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ | ||
66 | #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ | ||
67 | #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ | ||
68 | #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ | ||
69 | #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ | ||
70 | #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ | ||
71 | #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ | ||
72 | |||
73 | |||
74 | /* Machine State Register (MSR) Fields */ | ||
75 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ | ||
76 | #define MSR_SPE (1<<25) /* Enable SPE */ | ||
77 | #define MSR_DWE (1<<10) /* Debug Wait Enable */ | ||
78 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | ||
79 | #define MSR_IS MSR_IR /* Instruction Space */ | ||
80 | #define MSR_DS MSR_DR /* Data Space */ | ||
81 | #define MSR_PMM (1<<2) /* Performance monitor mark bit */ | ||
82 | |||
83 | /* Default MSR for kernel mode. */ | ||
84 | #if defined (CONFIG_40x) | ||
85 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) | ||
86 | #elif defined(CONFIG_BOOKE) | ||
87 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) | ||
88 | #endif | ||
89 | |||
90 | /* Special Purpose Registers (SPRNs)*/ | ||
91 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | ||
92 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ | ||
93 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ | ||
94 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ | ||
95 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | ||
96 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | ||
97 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | ||
98 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | ||
99 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | ||
100 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | ||
101 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | ||
102 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ | ||
103 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ | ||
104 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | ||
105 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ | ||
106 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | ||
107 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ | ||
108 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | ||
109 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | ||
110 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | ||
111 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | ||
112 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | ||
113 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | ||
114 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | ||
115 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | ||
116 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | ||
117 | #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ | ||
118 | #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ | ||
119 | #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ | ||
120 | #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ | ||
121 | #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ | ||
122 | #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ | ||
123 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ | ||
124 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ | ||
125 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | ||
126 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ | ||
127 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | ||
128 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | ||
129 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | ||
130 | #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ | ||
131 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ | ||
132 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ | ||
133 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ | ||
134 | #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ | ||
135 | #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ | ||
136 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ | ||
137 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | ||
138 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | ||
139 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | ||
140 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | ||
141 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | ||
142 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | ||
143 | #define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */ | ||
144 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ | ||
145 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ | ||
146 | #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ | ||
147 | #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ | ||
148 | #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ | ||
149 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ | ||
150 | #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ | ||
151 | #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ | ||
152 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ | ||
153 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | ||
154 | #define SPRN_SLER 0x3BB /* Little-endian real mode */ | ||
155 | #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ | ||
156 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ | ||
157 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | ||
158 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | ||
159 | #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ | ||
160 | #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ | ||
161 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ | ||
162 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ | ||
163 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ | ||
164 | #define SPRN_SVR 0x3FF /* System Version Register */ | ||
165 | |||
166 | /* | ||
167 | * SPRs which have conflicting definitions on true Book E versus classic, | ||
168 | * or IBM 40x. | ||
169 | */ | ||
170 | #ifdef CONFIG_BOOKE | ||
171 | #define SPRN_PID 0x030 /* Process ID */ | ||
172 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | ||
173 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ | ||
174 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ | ||
175 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ | ||
176 | #define SPRN_ESR 0x03E /* Exception Syndrome Register */ | ||
177 | #define SPRN_PIR 0x11E /* Processor Identification Register */ | ||
178 | #define SPRN_DBSR 0x130 /* Debug Status Register */ | ||
179 | #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ | ||
180 | #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ | ||
181 | #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ | ||
182 | #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ | ||
183 | #define SPRN_DAC1 0x13C /* Data Address Compare 1 */ | ||
184 | #define SPRN_DAC2 0x13D /* Data Address Compare 2 */ | ||
185 | #define SPRN_TSR 0x150 /* Timer Status Register */ | ||
186 | #define SPRN_TCR 0x154 /* Timer Control Register */ | ||
187 | #endif /* Book E */ | ||
188 | #ifdef CONFIG_40x | ||
189 | #define SPRN_PID 0x3B1 /* Process ID */ | ||
190 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ | ||
191 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ | ||
192 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ | ||
193 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ | ||
194 | #define SPRN_TCR 0x3DA /* Timer Control Register */ | ||
195 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | ||
196 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ | ||
197 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | ||
198 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ | ||
199 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ | ||
200 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | ||
201 | #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ | ||
202 | #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ | ||
203 | #endif | ||
204 | |||
205 | /* Bit definitions for CCR1. */ | ||
206 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ | ||
207 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | ||
208 | |||
209 | /* Bit definitions for the MCSR. */ | ||
210 | #ifdef CONFIG_440A | ||
211 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ | ||
212 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | ||
213 | #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ | ||
214 | #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ | ||
215 | #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ | ||
216 | #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ | ||
217 | #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ | ||
218 | #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ | ||
219 | #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ | ||
220 | #endif | ||
221 | #ifdef CONFIG_E500 | ||
222 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | ||
223 | #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ | ||
224 | #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ | ||
225 | #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ | ||
226 | #define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */ | ||
227 | #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ | ||
228 | #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ | ||
229 | #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ | ||
230 | #define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ | ||
231 | #define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ | ||
232 | #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ | ||
233 | #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ | ||
234 | #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ | ||
235 | #endif | ||
236 | #ifdef CONFIG_E200 | ||
237 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | ||
238 | #define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ | ||
239 | #define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ | ||
240 | #define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn | ||
241 | fetch for an exception handler */ | ||
242 | #define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ | ||
243 | #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ | ||
244 | #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered | ||
245 | store or cache line push */ | ||
246 | #endif | ||
247 | |||
248 | /* Bit definitions for the DBSR. */ | ||
249 | /* | ||
250 | * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. | ||
251 | */ | ||
252 | #ifdef CONFIG_BOOKE | ||
253 | #define DBSR_IC 0x08000000 /* Instruction Completion */ | ||
254 | #define DBSR_BT 0x04000000 /* Branch Taken */ | ||
255 | #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ | ||
256 | #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ | ||
257 | #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ | ||
258 | #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ | ||
259 | #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ | ||
260 | #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ | ||
261 | #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ | ||
262 | #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ | ||
263 | #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ | ||
264 | #endif | ||
265 | #ifdef CONFIG_40x | ||
266 | #define DBSR_IC 0x80000000 /* Instruction Completion */ | ||
267 | #define DBSR_BT 0x40000000 /* Branch taken */ | ||
268 | #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ | ||
269 | #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ | ||
270 | #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ | ||
271 | #define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ | ||
272 | #define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ | ||
273 | #define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ | ||
274 | #define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ | ||
275 | #define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ | ||
276 | #define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ | ||
277 | #endif | ||
278 | |||
279 | /* Bit definitions related to the ESR. */ | ||
280 | #define ESR_MCI 0x80000000 /* Machine Check - Instruction */ | ||
281 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ | ||
282 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | ||
283 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | ||
284 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | ||
285 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | ||
286 | #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ | ||
287 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ | ||
288 | #define ESR_FP 0x01000000 /* Floating Point Operation */ | ||
289 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | ||
290 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | ||
291 | #define ESR_ST 0x00800000 /* Store Operation */ | ||
292 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ | ||
293 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ | ||
294 | #define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ | ||
295 | #define ESR_BO 0x00020000 /* Byte Ordering */ | ||
296 | |||
297 | /* Bit definitions related to the DBCR0. */ | ||
298 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ | ||
299 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ | ||
300 | #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ | ||
301 | #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ | ||
302 | #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ | ||
303 | #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ | ||
304 | #define DBCR0_RST_NONE 0x00000000 /* No Reset */ | ||
305 | #define DBCR0_IC 0x08000000 /* Instruction Completion */ | ||
306 | #define DBCR0_BT 0x04000000 /* Branch Taken */ | ||
307 | #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ | ||
308 | #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ | ||
309 | #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ | ||
310 | #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ | ||
311 | #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ | ||
312 | #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ | ||
313 | #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ | ||
314 | #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ | ||
315 | #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ | ||
316 | #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ | ||
317 | #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ | ||
318 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ | ||
319 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | ||
320 | |||
321 | /* Bit definitions related to the TCR. */ | ||
322 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ | ||
323 | #define TCR_WP_MASK TCR_WP(3) | ||
324 | #define WP_2_17 0 /* 2^17 clocks */ | ||
325 | #define WP_2_21 1 /* 2^21 clocks */ | ||
326 | #define WP_2_25 2 /* 2^25 clocks */ | ||
327 | #define WP_2_29 3 /* 2^29 clocks */ | ||
328 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | ||
329 | #define TCR_WRC_MASK TCR_WRC(3) | ||
330 | #define WRC_NONE 0 /* No reset will occur */ | ||
331 | #define WRC_CORE 1 /* Core reset will occur */ | ||
332 | #define WRC_CHIP 2 /* Chip reset will occur */ | ||
333 | #define WRC_SYSTEM 3 /* System reset will occur */ | ||
334 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | ||
335 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | ||
336 | #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ | ||
337 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | ||
338 | #define TCR_FP_MASK TCR_FP(3) | ||
339 | #define FP_2_9 0 /* 2^9 clocks */ | ||
340 | #define FP_2_13 1 /* 2^13 clocks */ | ||
341 | #define FP_2_17 2 /* 2^17 clocks */ | ||
342 | #define FP_2_21 3 /* 2^21 clocks */ | ||
343 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | ||
344 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | ||
345 | |||
346 | /* Bit definitions for the TSR. */ | ||
347 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ | ||
348 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | ||
349 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | ||
350 | #define WRS_NONE 0 /* No WDT reset occurred */ | ||
351 | #define WRS_CORE 1 /* WDT forced core reset */ | ||
352 | #define WRS_CHIP 2 /* WDT forced chip reset */ | ||
353 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | ||
354 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | ||
355 | #define TSR_DIS TSR_PIS /* DEC Interrupt Status */ | ||
356 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | ||
357 | |||
358 | /* Bit definitions for the DCCR. */ | ||
359 | #define DCCR_NOCACHE 0 /* Noncacheable */ | ||
360 | #define DCCR_CACHE 1 /* Cacheable */ | ||
361 | |||
362 | /* Bit definitions for DCWR. */ | ||
363 | #define DCWR_COPY 0 /* Copy-back */ | ||
364 | #define DCWR_WRITE 1 /* Write-through */ | ||
365 | |||
366 | /* Bit definitions for ICCR. */ | ||
367 | #define ICCR_NOCACHE 0 /* Noncacheable */ | ||
368 | #define ICCR_CACHE 1 /* Cacheable */ | ||
369 | |||
370 | /* Bit definitions for L1CSR0. */ | ||
371 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ | ||
372 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | ||
373 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | ||
374 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | ||
375 | |||
376 | /* Bit definitions for L1CSR1. */ | ||
377 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | ||
378 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | ||
379 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | ||
380 | |||
381 | /* Bit definitions for SGR. */ | ||
382 | #define SGR_NORMAL 0 /* Speculative fetching allowed. */ | ||
383 | #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ | ||
384 | |||
385 | /* Bit definitions for SPEFSCR. */ | ||
386 | #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ | ||
387 | #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ | ||
388 | #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ | ||
389 | #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ | ||
390 | #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ | ||
391 | #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ | ||
392 | #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ | ||
393 | #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ | ||
394 | #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ | ||
395 | #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ | ||
396 | #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ | ||
397 | #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ | ||
398 | #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ | ||
399 | #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ | ||
400 | #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ | ||
401 | #define SPEFSCR_OV 0x00004000 /* Integer overflow */ | ||
402 | #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ | ||
403 | #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ | ||
404 | #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ | ||
405 | #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ | ||
406 | #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ | ||
407 | #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ | ||
408 | #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ | ||
409 | #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ | ||
410 | #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ | ||
411 | #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ | ||
412 | #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ | ||
413 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ | ||
414 | |||
415 | /* | ||
416 | * The IBM-403 is an even more odd special case, as it is much | ||
417 | * older than the IBM-405 series. We put these down here incase someone | ||
418 | * wishes to support these machines again. | ||
419 | */ | ||
420 | #ifdef CONFIG_403GCX | ||
421 | /* Special Purpose Registers (SPRNs)*/ | ||
422 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | ||
423 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | ||
424 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ | ||
425 | #define SPRN_TBHI 0x3DC /* Time Base High */ | ||
426 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | ||
427 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ | ||
428 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ | ||
429 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | ||
430 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | ||
431 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | ||
432 | |||
433 | |||
434 | /* Bit definitions for the DBCR. */ | ||
435 | #define DBCR_EDM DBCR0_EDM | ||
436 | #define DBCR_IDM DBCR0_IDM | ||
437 | #define DBCR_RST(x) (((x) & 0x3) << 28) | ||
438 | #define DBCR_RST_NONE 0 | ||
439 | #define DBCR_RST_CORE 1 | ||
440 | #define DBCR_RST_CHIP 2 | ||
441 | #define DBCR_RST_SYSTEM 3 | ||
442 | #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ | ||
443 | #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ | ||
444 | #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ | ||
445 | #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ | ||
446 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | ||
447 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | ||
448 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | ||
449 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | ||
450 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | ||
451 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | ||
452 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | ||
453 | #define DAC_BYTE 0 | ||
454 | #define DAC_HALF 1 | ||
455 | #define DAC_WORD 2 | ||
456 | #define DAC_QUAD 3 | ||
457 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | ||
458 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | ||
459 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | ||
460 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | ||
461 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | ||
462 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | ||
463 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | ||
464 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | ||
465 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | ||
466 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | ||
467 | #endif /* 403GCX */ | ||
468 | #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ | ||
469 | #endif /* __KERNEL__ */ | ||