Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Update defconfigs
  [MIPS] Support for several more SNI RM models.
  [MIPS] Include <asm/bugs> to for declaration of check_bugs32.
  [MIPS] Add external declaration of pagetable_init() to pgalloc.h
  [MIPS] Make kernel_thread_helper() static
  [MIPS] Make __declare_dbe_table static and avoid it getting optimized away
  [MIPS] Use MIPS R2 instructions for bitops.
  [MIPS] signals: Share even more code.
  [MIPS] Fix CONFIG_MIPS32_N32=y CONFIG_MIPS32_O32=n build
  [MIPS] Iomap implementation.
  [MIPS] <asm/compat-signal.h> needs to include <asm/uaccess.h>.
  [MIPS] IP27: Fix warning.
  [MIPS] Fix sigset_t endianess swapping issues in 32-bit compat code.

10 files changed, 216 insertions, 63 deletions

diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h
index 1ce0518ace2e..1dd74fbdc09b 100644
--- a/include/asm-mips/abi.h
+++ b/include/asm-mips/abi.h
@@ -13,13 +13,13 @@
 #include <asm/siginfo.h>
 
 struct mips_abi {
-        void (* const do_signal)(struct pt_regs *regs);
         int (* const setup_frame)(struct k_sigaction * ka,
                                   struct pt_regs *regs, int signr,
                                   sigset_t *set);
         int (* const setup_rt_frame)(struct k_sigaction * ka,
                                struct pt_regs *regs, int signr,
                                sigset_t *set, siginfo_t *info);
+        const unsigned long     restart;
 };
 
 #endif /* _ASM_ABI_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 06c08228a525..89436b96ad66 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1994 - 1997, 1999, 2000, 06  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (c) 1994 - 1997, 99, 2000, 06, 07  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
  */
 #ifndef _ASM_BITOPS_H
@@ -24,11 +24,15 @@
 #define SZLONG_MASK 31UL
 #define __LL            "ll     "
 #define __SC            "sc     "
+#define __INS           "ins    "
+#define __EXT           "ext    "
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL            "lld    "
 #define __SC            "scd    "
+#define __INS           "dins    "
+#define __EXT           "dext    "
 #endif
 
 /*
@@ -62,6 +66,19 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+#ifdef CONFIG_CPU_MIPSR2
+        } else if (__builtin_constant_p(nr)) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # set_bit       \n"
+                "       " __INS "%0, %4, %2, 1                          \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0));
+#endif /* CONFIG_CPU_MIPSR2 */
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
                 "       .set    mips3                                   \n"
@@ -113,6 +130,19 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+#ifdef CONFIG_CPU_MIPSR2
+        } else if (__builtin_constant_p(nr)) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # clear_bit     \n"
+                "       " __INS "%0, $0, %2, 1                          \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (nr & SZLONG_MASK), "m" (*m));
+#endif /* CONFIG_CPU_MIPSR2 */
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
                 "       .set    mips3                                   \n"
@@ -291,6 +321,26 @@ static inline int test_and_clear_bit(unsigned long nr,
                 : "memory");
 
                 return res != 0;
+#ifdef CONFIG_CPU_MIPSR2
+        } else if (__builtin_constant_p(nr)) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
+                "       " __EXT "%2, %0, %3, 1                          \n"
+                "       " __INS "%0, $0, %3, 1                          \n"
+                "       " __SC  "%0, %1                                 \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "ri" (nr & SZLONG_MASK), "m" (*m)
+                : "memory");
+
+                return res;
+#endif
         } else if (cpu_has_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp, res;
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h
index 672077084aa1..6599a901b63e 100644
--- a/include/asm-mips/compat-signal.h
+++ b/include/asm-mips/compat-signal.h
@@ -5,6 +5,11 @@
 #include <linux/compat.h>
 #include <linux/compiler.h>
 
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+
+#include <asm/uaccess.h>
+
 static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
         const sigset_t *s)
 {
@@ -33,9 +38,6 @@ static inline int __copy_conv_sigset_from_user(sigset_t *d,
         BUG_ON(sizeof(*d) != sizeof(*s));
         BUG_ON(_NSIG_WORDS != 2);
 
-        if (unlikely(!access_ok(VERIFY_READ, d, sizeof(*d))))
-                return -EFAULT;
-
 #ifdef CONFIG_CPU_BIG_ENDIAN
         err  = __get_user(u->c.sig[1], &s->sig[0]);
         err |= __get_user(u->c.sig[0], &s->sig[1]);
diff --git a/include/asm-mips/ds1216.h b/include/asm-mips/ds1216.h
new file mode 100644
index 000000000000..1ff8b73f7a6a
--- /dev/null
+++ b/include/asm-mips/ds1216.h
@@ -0,0 +1,31 @@
+#ifndef _DS1216_H
+#define _DS1216_H
+
+extern volatile unsigned char *ds1216_base;
+unsigned long ds1216_get_cmos_time(void);
+int ds1216_set_rtc_mmss(unsigned long nowtime);
+
+#define DS1216_SEC_BYTE         1
+#define DS1216_MIN_BYTE         2
+#define DS1216_HOUR_BYTE        3
+#define DS1216_HOUR_MASK        (0x1f)
+#define DS1216_AMPM_MASK        (1<<5)
+#define DS1216_1224_MASK        (1<<7)
+#define DS1216_DAY_BYTE         4
+#define DS1216_DAY_MASK         (0x7)
+#define DS1216_DATE_BYTE        5
+#define DS1216_DATE_MASK        (0x3f)
+#define DS1216_MONTH_BYTE       6
+#define DS1216_MONTH_MASK       (0x1f)
+#define DS1216_YEAR_BYTE        7
+
+#define DS1216_SEC(buf)         (buf[DS1216_SEC_BYTE])
+#define DS1216_MIN(buf)         (buf[DS1216_MIN_BYTE])
+#define DS1216_HOUR(buf)        (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK)
+#define DS1216_AMPM(buf)        (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK)
+#define DS1216_1224(buf)        (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK)
+#define DS1216_DATE(buf)        (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK)
+#define DS1216_MONTH(buf)       (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK)
+#define DS1216_YEAR(buf)        (buf[DS1216_YEAR_BYTE])
+
+#endif
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index b6a2eb816628..92ec2618560c 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -20,6 +20,7 @@
 #include <asm/byteorder.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
+#include <asm-generic/iomap.h>
 #include <asm/page.h>
 #include <asm/pgtable-bits.h>
 #include <asm/processor.h>
@@ -518,34 +519,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
 }
 
 /*
- * Memory Mapped I/O
- */
-#define ioread8(addr)           readb(addr)
-#define ioread16(addr)          readw(addr)
-#define ioread32(addr)          readl(addr)
-
-#define iowrite8(b,addr)        writeb(b,addr)
-#define iowrite16(w,addr)       writew(w,addr)
-#define iowrite32(l,addr)       writel(l,addr)
-
-#define ioread8_rep(a,b,c)      readsb(a,b,c)
-#define ioread16_rep(a,b,c)     readsw(a,b,c)
-#define ioread32_rep(a,b,c)     readsl(a,b,c)
-
-#define iowrite8_rep(a,b,c)     writesb(a,b,c)
-#define iowrite16_rep(a,b,c)    writesw(a,b,c)
-#define iowrite32_rep(a,b,c)    writesl(a,b,c)
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-/*
  * ISA space is 'always mapped' on currently supported MIPS systems, no need
  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h
index 11410ae10d36..7e07283140a3 100644
--- a/include/asm-mips/mach-rm/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h
@@ -21,9 +21,7 @@
 #define cpu_has_watch           0
 #define cpu_has_mips16          0
 #define cpu_has_divec           0
-#define cpu_has_vce             0
 #define cpu_has_cache_cdex_p    1
-#define cpu_has_cache_cdex_s    0
 #define cpu_has_prefetch        0
 #define cpu_has_mcheck          0
 #define cpu_has_ejtag           0
@@ -35,9 +33,6 @@
 #define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-
 #define cpu_has_mips32r1        0
 #define cpu_has_mips32r2        0
 #define cpu_has_mips64r1        0
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 7f0f120ca07c..3eea3ba0fca5 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -32,6 +32,7 @@ struct pci_controller {
         unsigned long mem_offset;
         struct resource *io_resource;
         unsigned long io_offset;
+        unsigned long io_map_base;
 
         unsigned int index;
         /* For compatibility with current (as of July 2003) pciutils
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index af121c67dc71..5685d4fc7881 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -130,4 +130,6 @@ static inline void pmd_free(pmd_t *pmd)
 
 #define check_pgt_cache()       do { } while (0)
 
+extern void pagetable_init(void);
+
 #endif /* _ASM_PGALLOC_H */
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 8b391a2f0814..7a28989f7ee3 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -137,23 +137,6 @@ typedef struct sigaltstack {
 
 #define ptrace_signal_deliver(regs, cookie) do { } while (0)
 
-struct pt_regs;
-extern void do_signal(struct pt_regs *regs);
-extern void do_signal32(struct pt_regs *regs);
-
-extern int setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
-        int signr, sigset_t *set);
-extern int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
-        int signr, sigset_t *set, siginfo_t *info);
-
-extern int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
-        int signr, sigset_t *set);
-extern int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
-        int signr, sigset_t *set, siginfo_t *info);
-
-extern int setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs,
-        int signr, sigset_t *set, siginfo_t *info);
-
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_SIGNAL_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index b9ba54d0dd35..62f9be6f7320 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -6,12 +6,72 @@
  * for more details.
  *
  * Copyright (C) 1997, 1998 by Ralf Baechle
+ * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
  */
 #ifndef __ASM_SNI_H
 #define __ASM_SNI_H
 
+extern unsigned int sni_brd_type;
+
+#define SNI_BRD_10                 2
+#define SNI_BRD_10NEW              3
+#define SNI_BRD_TOWER_OASIC        4
+#define SNI_BRD_MINITOWER          5
+#define SNI_BRD_PCI_TOWER          6
+#define SNI_BRD_RM200              7
+#define SNI_BRD_PCI_MTOWER         8
+#define SNI_BRD_PCI_DESKTOP        9
+#define SNI_BRD_PCI_TOWER_CPLUS   10
+#define SNI_BRD_PCI_MTOWER_CPLUS  11
+
+/* RM400 cpu types */
+#define SNI_CPU_M8021           0x01
+#define SNI_CPU_M8030           0x04
+#define SNI_CPU_M8031           0x06
+#define SNI_CPU_M8034           0x0f
+#define SNI_CPU_M8037           0x07
+#define SNI_CPU_M8040           0x05
+#define SNI_CPU_M8043           0x09
+#define SNI_CPU_M8050           0x0b
+#define SNI_CPU_M8053           0x0d
+
 #define SNI_PORT_BASE           0xb4000000
 
+#ifndef __MIPSEL__
+/*
+ * ASIC PCI registers for big endian configuration.
+ */
+#define PCIMT_UCONF             0xbfff0004
+#define PCIMT_IOADTIMEOUT2      0xbfff000c
+#define PCIMT_IOMEMCONF         0xbfff0014
+#define PCIMT_IOMMU             0xbfff001c
+#define PCIMT_IOADTIMEOUT1      0xbfff0024
+#define PCIMT_DMAACCESS         0xbfff002c
+#define PCIMT_DMAHIT            0xbfff0034
+#define PCIMT_ERRSTATUS         0xbfff003c
+#define PCIMT_ERRADDR           0xbfff0044
+#define PCIMT_SYNDROME          0xbfff004c
+#define PCIMT_ITPEND            0xbfff0054
+#define  IT_INT2                0x01
+#define  IT_INTD                0x02
+#define  IT_INTC                0x04
+#define  IT_INTB                0x08
+#define  IT_INTA                0x10
+#define  IT_EISA                0x20
+#define  IT_SCSI                0x40
+#define  IT_ETH                 0x80
+#define PCIMT_IRQSEL            0xbfff005c
+#define PCIMT_TESTMEM           0xbfff0064
+#define PCIMT_ECCREG            0xbfff006c
+#define PCIMT_CONFIG_ADDRESS    0xbfff0074
+#define PCIMT_ASIC_ID           0xbfff007c      /* read */
+#define PCIMT_SOFT_RESET        0xbfff007c      /* write */
+#define PCIMT_PIA_OE            0xbfff0084
+#define PCIMT_PIA_DATAOUT       0xbfff008c
+#define PCIMT_PIA_DATAIN        0xbfff0094
+#define PCIMT_CACHECONF         0xbfff009c
+#define PCIMT_INVSPACE          0xbfff00a4
+#else
 /*
  * ASIC PCI registers for little endian configuration.
  */
@@ -45,6 +105,8 @@
 #define PCIMT_PIA_DATAIN        0xbfff0090
 #define PCIMT_CACHECONF         0xbfff0098
 #define PCIMT_INVSPACE          0xbfff00a0
+#endif
+
 #define PCIMT_PCI_CONF          0xbfff0100
 
 /*
@@ -73,6 +135,36 @@
 #define PCIMT_PWDN              0xbfdf0000
 
 /*
+ * A20R based boards
+ */
+#define A20R_PT_CLOCK_BASE      0xbc040000
+#define A20R_PT_TIM0_ACK        0xbc050000
+#define A20R_PT_TIM1_ACK        0xbc060000
+
+#define SNI_MIPS_IRQ_CPU_BASE   16
+#define SNI_MIPS_IRQ_CPU_TIMER  (SNI_MIPS_IRQ_CPU_BASE+7)
+
+#define SNI_A20R_IRQ_BASE       SNI_MIPS_IRQ_CPU_BASE
+#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
+
+#define SNI_DS1216_A20R_BASE    0xbc081ffc
+#define SNI_DS1216_RM200_BASE   0xbcd41ffc
+
+#define SNI_PCIT_INT_REG        0xbfff000c
+
+#define SNI_PCIT_INT_START      24
+#define SNI_PCIT_INT_END        30
+
+#define PCIT_IRQ_ETHERNET       (SNI_MIPS_IRQ_CPU_BASE + 5)
+#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
+#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
+#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
+#define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
+#define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
+#define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
+
+
+/*
  * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
  * to the other interrupts generated by ASIC PCI.
  *
@@ -80,18 +172,22 @@
  * ASIC PCI interrupt.
  */
 #define PCIMT_KEYBOARD_IRQ       1
-#define PCIMT_IRQ_INT2          16
-#define PCIMT_IRQ_INTD          17
-#define PCIMT_IRQ_INTC          18
-#define PCIMT_IRQ_INTB          19
-#define PCIMT_IRQ_INTA          20
-#define PCIMT_IRQ_EISA          21
-#define PCIMT_IRQ_SCSI          22
-#define PCIMT_IRQ_ETHERNET      23
+#define PCIMT_IRQ_INT2          24
+#define PCIMT_IRQ_INTD          25
+#define PCIMT_IRQ_INTC          26
+#define PCIMT_IRQ_INTB          27
+#define PCIMT_IRQ_INTA          28
+#define PCIMT_IRQ_EISA          29
+#define PCIMT_IRQ_SCSI          30
+
+#define PCIMT_IRQ_ETHERNET      (SNI_MIPS_IRQ_CPU_BASE+6)
+
+#if 0
 #define PCIMT_IRQ_TEMPERATURE   24
 #define PCIMT_IRQ_EISA_NMI      25
 #define PCIMT_IRQ_POWER_OFF     26
 #define PCIMT_IRQ_BUTTON        27
+#endif
 
 /*
  * Base address for the mapped 16mb EISA bus segment.
@@ -101,4 +197,24 @@
 /* PCI EISA Interrupt acknowledge  */
 #define PCIMT_INT_ACKNOWLEDGE   0xba000000
 
+/* board specific init functions */
+extern void sni_a20r_init (void);
+extern void sni_pcit_init (void);
+extern void sni_rm200_init (void);
+extern void sni_pcimt_init (void);
+
+/* board specific irq init functions */
+extern void sni_a20r_irq_init (void);
+extern void sni_pcit_irq_init (void);
+extern void sni_pcit_cplus_irq_init (void);
+extern void sni_rm200_irq_init (void);
+extern void sni_pcimt_irq_init (void);
+
+/* timer inits */
+extern void sni_cpu_time_init(void);
+
+/* common irq stuff */
+extern void (*sni_hwint)(void);
+extern struct irqaction sni_isa_irq;
+
 #endif /* __ASM_SNI_H */