aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-10-10 09:46:52 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-10-11 14:30:59 -0400
commit9b95e629eab59ee140fe2b17bbd7fea6821c6085 (patch)
treecda9a07874bd1c7ba3254addbff24bcc7f91ac7d /include
parentdff9262ed1491a1e531dc56e687605b5e4cd488d (diff)
[MIPS] Optimize and cleanup get_saved_sp, set_saved_sp
If CONFIG_BUILD_ELF64 was not selected and gcc had -msym32 option (i.e. 4.0 or newer), there is no point to use %highest, %higher for kernel symbols. This patch also fixes 64-bit SMTC version of get_saved_sp() which is broken but harmless since there is no such CPUs for now. A bonus is set_saved_sp() and SMP version of get_saved_sp() are more readable now. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/stackframe.h64
1 files changed, 19 insertions, 45 deletions
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 158a4cd12e46..1fae5dc58138 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -59,69 +59,43 @@
59 .endm 59 .endm
60 60
61#ifdef CONFIG_SMP 61#ifdef CONFIG_SMP
62 .macro get_saved_sp /* SMP variation */
63#ifdef CONFIG_32BIT
64#ifdef CONFIG_MIPS_MT_SMTC 62#ifdef CONFIG_MIPS_MT_SMTC
65 .set mips32 63#define PTEBASE_SHIFT 19 /* TCBIND */
66 mfc0 k0, CP0_TCBIND;
67 .set mips0
68 lui k1, %hi(kernelsp)
69 srl k0, k0, 19
70 /* No need to shift down and up to clear bits 0-1 */
71#else 64#else
72 mfc0 k0, CP0_CONTEXT 65#define PTEBASE_SHIFT 23 /* CONTEXT */
73 lui k1, %hi(kernelsp)
74 srl k0, k0, 23
75#endif
76 addu k1, k0
77 LONG_L k1, %lo(kernelsp)(k1)
78#endif 66#endif
79#ifdef CONFIG_64BIT 67 .macro get_saved_sp /* SMP variation */
80#ifdef CONFIG_MIPS_MT_SMTC 68#ifdef CONFIG_MIPS_MT_SMTC
81 .set mips64 69 mfc0 k0, CP0_TCBIND
82 mfc0 k0, CP0_TCBIND;
83 .set mips0
84 lui k0, %highest(kernelsp)
85 dsrl k1, 19
86 /* No need to shift down and up to clear bits 0-2 */
87#else 70#else
88 MFC0 k1, CP0_CONTEXT 71 MFC0 k0, CP0_CONTEXT
89 lui k0, %highest(kernelsp) 72#endif
90 dsrl k1, 23 73#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
91 daddiu k0, %higher(kernelsp) 74 lui k1, %highest(kernelsp)
92 dsll k0, k0, 16 75 daddiu k1, %higher(kernelsp)
93 daddiu k0, %hi(kernelsp) 76 dsll k1, 16
94 dsll k0, k0, 16 77 daddiu k1, %hi(kernelsp)
95#endif /* CONFIG_MIPS_MT_SMTC */ 78 dsll k1, 16
96 daddu k1, k1, k0 79#else
80 lui k1, %hi(kernelsp)
81#endif
82 LONG_SRL k0, PTEBASE_SHIFT
83 LONG_ADDU k1, k0
97 LONG_L k1, %lo(kernelsp)(k1) 84 LONG_L k1, %lo(kernelsp)(k1)
98#endif /* CONFIG_64BIT */
99 .endm 85 .endm
100 86
101 .macro set_saved_sp stackp temp temp2 87 .macro set_saved_sp stackp temp temp2
102#ifdef CONFIG_32BIT
103#ifdef CONFIG_MIPS_MT_SMTC
104 mfc0 \temp, CP0_TCBIND
105 srl \temp, 19
106#else
107 mfc0 \temp, CP0_CONTEXT
108 srl \temp, 23
109#endif
110#endif
111#ifdef CONFIG_64BIT
112#ifdef CONFIG_MIPS_MT_SMTC 88#ifdef CONFIG_MIPS_MT_SMTC
113 mfc0 \temp, CP0_TCBIND 89 mfc0 \temp, CP0_TCBIND
114 dsrl \temp, 19
115#else 90#else
116 MFC0 \temp, CP0_CONTEXT 91 MFC0 \temp, CP0_CONTEXT
117 dsrl \temp, 23
118#endif
119#endif 92#endif
93 LONG_SRL \temp, PTEBASE_SHIFT
120 LONG_S \stackp, kernelsp(\temp) 94 LONG_S \stackp, kernelsp(\temp)
121 .endm 95 .endm
122#else 96#else
123 .macro get_saved_sp /* Uniprocessor variation */ 97 .macro get_saved_sp /* Uniprocessor variation */
124#ifdef CONFIG_64BIT 98#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
125 lui k1, %highest(kernelsp) 99 lui k1, %highest(kernelsp)
126 daddiu k1, %higher(kernelsp) 100 daddiu k1, %higher(kernelsp)
127 dsll k1, k1, 16 101 dsll k1, k1, 16