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authorBen Dooks <ben-linux@fluff.org>2006-06-24 16:21:27 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-24 16:21:27 -0400
commit68d9ab394f06f95fd4ca612c08edf13e410fd8d0 (patch)
treead5fc04b5b3c319134db680bebc9a552d88375fc /include
parenta3ff55026e59687040f00fc35680fc0e774859f4 (diff)
[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
Patch from Ben Dooks Add support for the Samsung S3C2412 and S3C2413 range of SoCs. This patch contains the core identification, debug macros, and basic register updates to get these to build. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S10
-rw-r--r--include/asm-arm/arch-s3c2410/map.h16
-rw-r--r--include/asm-arm/arch-s3c2410/regs-dsc.h3
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h63
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpioj.h5
5 files changed, 92 insertions, 5 deletions
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 5f8223e700d3..b7d15d125458 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -33,7 +33,7 @@
33 .endm 33 .endm
34 34
35 .macro senduart,rd,rx 35 .macro senduart,rd,rx
36 str \rd, [\rx, # S3C2410_UTXH ] 36 strb \rd, [\rx, # S3C2410_UTXH ]
37 .endm 37 .endm
38 38
39 .macro busyuart, rd, rx 39 .macro busyuart, rd, rx
@@ -42,6 +42,12 @@
42 beq 1001f @ 42 beq 1001f @
43 @ FIFO enabled... 43 @ FIFO enabled...
441003: 441003:
45 @ check for arm920 vs arm926. currently assume all arm926
46 @ devices have an 64 byte FIFO identical to the s3c2440
47 mrc p15, 0, \rd, c0, c0
48 and \rd, \rd, #0xff0
49 teq \rd, #0x260
50 beq 1004f
45 mrc p15, 0, \rd, c1, c0 51 mrc p15, 0, \rd, c1, c0
46 tst \rd, #1 52 tst \rd, #1
47 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 53 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -50,7 +56,7 @@
50 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] 56 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
51 and \rd, \rd, #0x00ff0000 57 and \rd, \rd, #0x00ff0000
52 teq \rd, #0x00440000 @ is it 2440? 58 teq \rd, #0x00440000 @ is it 2440?
53 591004:
54 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 60 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
55 moveq \rd, \rd, lsr #SHIFT_2440TXF 61 moveq \rd, \rd, lsr #SHIFT_2440TXF
56 tst \rd, #S3C2410_UFSTAT_TXFULL 62 tst \rd, #S3C2410_UFSTAT_TXFULL
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 5e4c8c37bc66..fae2766ff32b 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -236,4 +236,20 @@
236#define S3C24XX_PA_SPI S3C2410_PA_SPI 236#define S3C24XX_PA_SPI S3C2410_PA_SPI
237#endif 237#endif
238 238
239/* deal with the registers that move under the 2412/2413 */
240
241#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
242#ifndef __ASSEMBLY__
243extern void __iomem *s3c24xx_va_gpio2;
244#endif
245#ifdef CONFIG_CPU_S3C2412_ONLY
246#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
247#else
248#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
249#endif
250#else
251#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
252#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
253#endif
254
239#endif /* __ASM_ARCH_MAP_H */ 255#endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index ba13a2c9e547..84aca61cbaa3 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -23,6 +23,9 @@
23#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) 23#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
24#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) 24#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
25 25
26#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
27#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
28
26#define S3C2440_SELECT_DSC0 (0) 29#define S3C2440_SELECT_DSC0 (0)
27#define S3C2440_SELECT_DSC1 (1<<31) 30#define S3C2440_SELECT_DSC1 (1<<31)
28 31
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 5f10334f06bf..6dd17f0f84e0 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -45,7 +45,7 @@
45#define S3C24XX_MISCCR S3C2400_MISCCR 45#define S3C24XX_MISCCR S3C2400_MISCCR
46#else 46#else
47#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) 47#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
48#define S3C24XX_MISCCR S3C2410_MISCCR 48#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
49#endif /* CONFIG_CPU_S3C2400 */ 49#endif /* CONFIG_CPU_S3C2400 */
50 50
51 51
@@ -73,9 +73,15 @@
73#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */ 73#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
74#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ 74#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
75 75
76/* configure GPIO ports A..G */ 76/* register address for the GPIO registers.
77 * S3C24XX_GPIOREG2 is for the second set of registers in the
78 * GPIO which move between s3c2410 and s3c2412 type systems */
77 79
78#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 80#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
81#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
82
83
84/* configure GPIO ports A..G */
79 85
80/* port A - S3C2410: 22bits, zero in bit X makes pin X output 86/* port A - S3C2410: 22bits, zero in bit X makes pin X output
81 * S3C2400: 18bits, zero in bit X makes pin X output 87 * S3C2400: 18bits, zero in bit X makes pin X output
@@ -953,11 +959,18 @@
953#define S3C2410_GPH10_OUTP (0x01 << 20) 959#define S3C2410_GPH10_OUTP (0x01 << 20)
954#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 960#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
955 961
962/* The S3C2412 and S3C2413 move the GPJ register set to after
963 * GPH, which means all registers after 0x80 are now offset by 0x10
964 * for the 2412/2413 from the 2410/2440/2442
965*/
966
956/* miscellaneous control */ 967/* miscellaneous control */
957#define S3C2400_MISCCR S3C2410_GPIOREG(0x54) 968#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
958#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 969#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
959#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 970#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
960 971
972#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
973
961/* see clock.h for dclk definitions */ 974/* see clock.h for dclk definitions */
962 975
963/* pullup control on databus */ 976/* pullup control on databus */
@@ -985,6 +998,8 @@
985#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) 998#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
986#define S3C2410_MISCCR_CLK0_MASK (7<<4) 999#define S3C2410_MISCCR_CLK0_MASK (7<<4)
987 1000
1001#define S3C2412_MISCCR_CLK0_RTC (2<<4)
1002
988#define S3C2410_MISCCR_CLK1_MPLL (0<<8) 1003#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
989#define S3C2410_MISCCR_CLK1_UPLL (1<<8) 1004#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
990#define S3C2410_MISCCR_CLK1_FCLK (2<<8) 1005#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
@@ -993,6 +1008,8 @@
993#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) 1008#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
994#define S3C2410_MISCCR_CLK1_MASK (7<<8) 1009#define S3C2410_MISCCR_CLK1_MASK (7<<8)
995 1010
1011#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
1012
996#define S3C2410_MISCCR_USBSUSPND0 (1<<12) 1013#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
997#define S3C2410_MISCCR_USBSUSPND1 (1<<13) 1014#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
998 1015
@@ -1000,7 +1017,7 @@
1000 1017
1001#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) 1018#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
1002#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) 1019#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
1003#define S3C2410_MISCCR_nEN_SCLKE (1<<19) 1020#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
1004#define S3C2410_MISCCR_SDSLEEP (7<<17) 1021#define S3C2410_MISCCR_SDSLEEP (7<<17)
1005 1022
1006/* external interrupt control... */ 1023/* external interrupt control... */
@@ -1017,6 +1034,10 @@
1017#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 1034#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
1018#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 1035#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
1019 1036
1037#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
1038#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
1039#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
1040
1020/* values for S3C2410_EXTINT0/1/2 */ 1041/* values for S3C2410_EXTINT0/1/2 */
1021#define S3C2410_EXTINT_LOWLEV (0x00) 1042#define S3C2410_EXTINT_LOWLEV (0x00)
1022#define S3C2410_EXTINT_HILEV (0x01) 1043#define S3C2410_EXTINT_HILEV (0x01)
@@ -1030,6 +1051,11 @@
1030#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) 1051#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
1031#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) 1052#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
1032 1053
1054#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
1055#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
1056#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
1057#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
1058
1033/* values for interrupt filtering */ 1059/* values for interrupt filtering */
1034#define S3C2410_EINTFLT_PCLK (0x00) 1060#define S3C2410_EINTFLT_PCLK (0x00)
1035#define S3C2410_EINTFLT_EXTCLK (1<<7) 1061#define S3C2410_EINTFLT_EXTCLK (1<<7)
@@ -1039,6 +1065,7 @@
1039 1065
1040/* GSTATUS have miscellaneous information in them 1066/* GSTATUS have miscellaneous information in them
1041 * 1067 *
1068 * These move between s3c2410 and s3c2412 style systems.
1042 */ 1069 */
1043 1070
1044#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) 1071#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
@@ -1047,6 +1074,18 @@
1047#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) 1074#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
1048#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) 1075#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
1049 1076
1077#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
1078#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
1079#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
1080#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
1081#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
1082
1083#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
1084#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
1085#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
1086#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
1087#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
1088
1050#define S3C2410_GSTATUS0_nWAIT (1<<3) 1089#define S3C2410_GSTATUS0_nWAIT (1<<3)
1051#define S3C2410_GSTATUS0_NCON (1<<2) 1090#define S3C2410_GSTATUS0_NCON (1<<2)
1052#define S3C2410_GSTATUS0_RnB (1<<1) 1091#define S3C2410_GSTATUS0_RnB (1<<1)
@@ -1054,6 +1093,7 @@
1054 1093
1055#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 1094#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
1056#define S3C2410_GSTATUS1_2410 (0x32410000) 1095#define S3C2410_GSTATUS1_2410 (0x32410000)
1096#define S3C2410_GSTATUS1_2412 (0x32412001)
1057#define S3C2410_GSTATUS1_2440 (0x32440000) 1097#define S3C2410_GSTATUS1_2440 (0x32440000)
1058#define S3C2410_GSTATUS1_2442 (0x32440aaa) 1098#define S3C2410_GSTATUS1_2442 (0x32440aaa)
1059 1099
@@ -1077,5 +1117,22 @@
1077#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) 1117#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
1078#define S3C2400_OPENCR_OPC_MOSIEN (1<<5) 1118#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
1079 1119
1120/* 2412/2413 sleep configuration registers */
1121
1122#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
1123#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
1124#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
1125#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
1126#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
1127#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
1128#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
1129
1130/* definitions for each pin bit */
1131#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
1132#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2))
1133#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
1134#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2))
1135#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
1136
1080#endif /* __ASM_ARCH_REGS_GPIO_H */ 1137#endif /* __ASM_ARCH_REGS_GPIO_H */
1081 1138
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
index 3ad2324acc39..18edae50d0b8 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -32,6 +32,11 @@
32#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4) 32#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
33#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8) 33#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
34 34
35#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
36#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
37#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
38#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
39
35#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0) 40#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
36#define S3C2440_GPJ0_INP (0x00 << 0) 41#define S3C2440_GPJ0_INP (0x00 << 0)
37#define S3C2440_GPJ0_OUTP (0x01 << 0) 42#define S3C2440_GPJ0_OUTP (0x01 << 0)