Merge branch 'linus' into x86/pci-ioapic-boot-irq-quirks

Conflicts:

	drivers/pci/quirks.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>

573 files changed, 18702 insertions, 22523 deletions

diff --git a/include/Kbuild b/include/Kbuild
index b52288774345..bdca155028ec 100644
--- a/include/Kbuild
+++ b/include/Kbuild
@@ -4,5 +4,6 @@ header-y += sound/
 header-y += mtd/
 header-y += rdma/
 header-y += video/
+header-y += drm/
 
 header-y += asm-$(ARCH)/
diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h
index 28fe8bae1037..4eb75a88795a 100644
--- a/include/acpi/acconfig.h
+++ b/include/acpi/acconfig.h
@@ -63,7 +63,7 @@
 
 /* Current ACPICA subsystem version in YYYYMMDD format */
 
-#define ACPI_CA_VERSION                 0x20080321
+#define ACPI_CA_VERSION                 0x20080609
 
 /*
  * OS name, used for the _OS object.  The _OS object is essentially obsolete,
diff --git a/include/acpi/acdisasm.h b/include/acpi/acdisasm.h
index 788f88782012..f53faca8ec80 100644
--- a/include/acpi/acdisasm.h
+++ b/include/acpi/acdisasm.h
@@ -162,6 +162,7 @@ extern struct acpi_dmtable_info acpi_dm_table_info_dmar_hdr[];
 extern struct acpi_dmtable_info acpi_dm_table_info_dmar_scope[];
 extern struct acpi_dmtable_info acpi_dm_table_info_dmar0[];
 extern struct acpi_dmtable_info acpi_dm_table_info_dmar1[];
+extern struct acpi_dmtable_info acpi_dm_table_info_dmar2[];
 extern struct acpi_dmtable_info acpi_dm_table_info_ecdt[];
 extern struct acpi_dmtable_info acpi_dm_table_info_einj[];
 extern struct acpi_dmtable_info acpi_dm_table_info_einj0[];
diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h
index 910f018d92c7..21a73a105d0a 100644
--- a/include/acpi/acdispat.h
+++ b/include/acpi/acdispat.h
@@ -221,7 +221,7 @@ acpi_ds_method_error(acpi_status status, struct acpi_walk_state *walk_state);
  * dsinit
  */
 acpi_status
-acpi_ds_initialize_objects(acpi_native_uint table_index,
+acpi_ds_initialize_objects(u32 table_index,
                            struct acpi_namespace_node *start_node);
 
 /*
diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h
index 1f591171bf31..e5a890ffeb02 100644
--- a/include/acpi/acexcep.h
+++ b/include/acpi/acexcep.h
@@ -108,8 +108,9 @@
 #define AE_BAD_HEX_CONSTANT             (acpi_status) (0x0007 | AE_CODE_PROGRAMMER)
 #define AE_BAD_OCTAL_CONSTANT           (acpi_status) (0x0008 | AE_CODE_PROGRAMMER)
 #define AE_BAD_DECIMAL_CONSTANT         (acpi_status) (0x0009 | AE_CODE_PROGRAMMER)
+#define AE_MISSING_ARGUMENTS            (acpi_status) (0x000A | AE_CODE_PROGRAMMER)
 
-#define AE_CODE_PGM_MAX                 0x0009
+#define AE_CODE_PGM_MAX                 0x000A
 
 /*
  * Acpi table exceptions
@@ -225,6 +226,7 @@ char const *acpi_gbl_exception_names_env[] = {
 };
 
 char const *acpi_gbl_exception_names_pgm[] = {
+        NULL,
         "AE_BAD_PARAMETER",
         "AE_BAD_CHARACTER",
         "AE_BAD_PATHNAME",
@@ -233,10 +235,12 @@ char const *acpi_gbl_exception_names_pgm[] = {
         "AE_ALIGNMENT",
         "AE_BAD_HEX_CONSTANT",
         "AE_BAD_OCTAL_CONSTANT",
-        "AE_BAD_DECIMAL_CONSTANT"
+        "AE_BAD_DECIMAL_CONSTANT",
+        "AE_MISSING_ARGUMENTS"
 };
 
 char const *acpi_gbl_exception_names_tbl[] = {
+        NULL,
         "AE_BAD_SIGNATURE",
         "AE_BAD_HEADER",
         "AE_BAD_CHECKSUM",
@@ -246,6 +250,7 @@ char const *acpi_gbl_exception_names_tbl[] = {
 };
 
 char const *acpi_gbl_exception_names_aml[] = {
+        NULL,
         "AE_AML_ERROR",
         "AE_AML_PARSE",
         "AE_AML_BAD_OPCODE",
@@ -283,6 +288,7 @@ char const *acpi_gbl_exception_names_aml[] = {
 };
 
 char const *acpi_gbl_exception_names_ctrl[] = {
+        NULL,
         "AE_CTRL_RETURN_VALUE",
         "AE_CTRL_PENDING",
         "AE_CTRL_TERMINATE",
diff --git a/include/acpi/acglobal.h b/include/acpi/acglobal.h
index 74ad971241db..15dda46b70d1 100644
--- a/include/acpi/acglobal.h
+++ b/include/acpi/acglobal.h
@@ -140,7 +140,7 @@ ACPI_EXTERN u32 acpi_gbl_trace_flags;
  */
 ACPI_EXTERN struct acpi_internal_rsdt acpi_gbl_root_table_list;
 ACPI_EXTERN struct acpi_table_fadt acpi_gbl_FADT;
-extern acpi_native_uint acpi_gbl_permanent_mmap;
+extern u8 acpi_gbl_permanent_mmap;
 
 /* These addresses are calculated from FADT address values */
 
diff --git a/include/acpi/achware.h b/include/acpi/achware.h
index d4fb9bbc903c..97a72b193276 100644
--- a/include/acpi/achware.h
+++ b/include/acpi/achware.h
@@ -87,6 +87,8 @@ acpi_status acpi_hw_clear_acpi_status(void);
 /*
  * hwgpe - GPE support
  */
+acpi_status acpi_hw_low_disable_gpe(struct acpi_gpe_event_info *gpe_event_info);
+
 acpi_status
 acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info *gpe_event_info);
 
@@ -100,11 +102,9 @@ acpi_status
 acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
                         struct acpi_gpe_block_info *gpe_block);
 
-#ifdef  ACPI_FUTURE_USAGE
 acpi_status
 acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
                        acpi_event_status * event_status);
-#endif                          /* ACPI_FUTURE_USAGE */
 
 acpi_status acpi_hw_disable_all_gpes(void);
 
diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h
index e249ce5d3300..e8db7a3143a5 100644
--- a/include/acpi/acinterp.h
+++ b/include/acpi/acinterp.h
@@ -366,10 +366,7 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth);
 
 void
 acpi_ex_dump_operands(union acpi_operand_object **operands,
-                      acpi_interpreter_mode interpreter_mode,
-                      char *ident,
-                      u32 num_levels,
-                      char *note, char *module_name, u32 line_number);
+                      const char *opcode_name, u32 num_opcodes);
 
 #ifdef  ACPI_FUTURE_USAGE
 void
diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h
index c5cdc32ac2f8..b221c8583ddd 100644
--- a/include/acpi/aclocal.h
+++ b/include/acpi/aclocal.h
@@ -98,8 +98,8 @@ union acpi_parse_object;
 
 static char *acpi_gbl_mutex_names[ACPI_NUM_MUTEX] = {
         "ACPI_MTX_Interpreter",
-        "ACPI_MTX_Tables",
         "ACPI_MTX_Namespace",
+        "ACPI_MTX_Tables",
         "ACPI_MTX_Events",
         "ACPI_MTX_Caches",
         "ACPI_MTX_Memory",
@@ -282,8 +282,8 @@ struct acpi_predefined_names {
 /* Info structure used to convert external<->internal namestrings */
 
 struct acpi_namestring_info {
-        char *external_name;
-        char *next_external_char;
+        const char *external_name;
+        const char *next_external_char;
         char *internal_name;
         u32 length;
         u32 num_segments;
diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h
index fb41a3b802fc..57ab9e9d7593 100644
--- a/include/acpi/acmacros.h
+++ b/include/acpi/acmacros.h
@@ -80,12 +80,12 @@
  */
 #define ACPI_CAST_PTR(t, p)             ((t *) (acpi_uintptr_t) (p))
 #define ACPI_CAST_INDIRECT_PTR(t, p)    ((t **) (acpi_uintptr_t) (p))
-#define ACPI_ADD_PTR(t,a,b)             ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_native_uint)(b)))
-#define ACPI_PTR_DIFF(a,b)              (acpi_native_uint) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b)))
+#define ACPI_ADD_PTR(t, a, b)           ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_size)(b)))
+#define ACPI_PTR_DIFF(a, b)             (acpi_size) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b)))
 
 /* Pointer/Integer type conversions */
 
-#define ACPI_TO_POINTER(i)              ACPI_ADD_PTR (void,(void *) NULL,(acpi_native_uint) i)
+#define ACPI_TO_POINTER(i)              ACPI_ADD_PTR (void, (void *) NULL, (acpi_size) i)
 #define ACPI_TO_INTEGER(p)              ACPI_PTR_DIFF (p,(void *) NULL)
 #define ACPI_OFFSET(d,f)                (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f),(void *) NULL)
 #define ACPI_PHYSADDR_TO_PTR(i)         ACPI_TO_POINTER(i)
@@ -296,22 +296,22 @@ struct acpi_integer_overlay {
 /*
  * Rounding macros (Power of two boundaries only)
  */
-#define ACPI_ROUND_DOWN(value,boundary)     (((acpi_native_uint)(value)) & \
-                                                                                                (~(((acpi_native_uint) boundary)-1)))
+#define ACPI_ROUND_DOWN(value, boundary)     (((acpi_size)(value)) & \
+                                                (~(((acpi_size) boundary)-1)))
 
-#define ACPI_ROUND_UP(value,boundary)       ((((acpi_native_uint)(value)) + \
-                                                                                                (((acpi_native_uint) boundary)-1)) & \
-                                                                                                (~(((acpi_native_uint) boundary)-1)))
+#define ACPI_ROUND_UP(value, boundary)       ((((acpi_size)(value)) + \
+                                                (((acpi_size) boundary)-1)) & \
+                                                (~(((acpi_size) boundary)-1)))
 
-/* Note: sizeof(acpi_native_uint) evaluates to either 2, 4, or 8 */
+/* Note: sizeof(acpi_size) evaluates to either 4 or 8 (32- vs 64-bit mode) */
 
 #define ACPI_ROUND_DOWN_TO_32BIT(a)         ACPI_ROUND_DOWN(a,4)
 #define ACPI_ROUND_DOWN_TO_64BIT(a)         ACPI_ROUND_DOWN(a,8)
-#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a)   ACPI_ROUND_DOWN(a,sizeof(acpi_native_uint))
+#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a)   ACPI_ROUND_DOWN(a,sizeof(acpi_size))
 
 #define ACPI_ROUND_UP_TO_32BIT(a)           ACPI_ROUND_UP(a,4)
 #define ACPI_ROUND_UP_TO_64BIT(a)           ACPI_ROUND_UP(a,8)
-#define ACPI_ROUND_UP_TO_NATIVE_WORD(a)     ACPI_ROUND_UP(a,sizeof(acpi_native_uint))
+#define ACPI_ROUND_UP_TO_NATIVE_WORD(a)     ACPI_ROUND_UP(a,sizeof(acpi_size))
 
 #define ACPI_ROUND_BITS_UP_TO_BYTES(a)      ACPI_DIV_8((a) + 7)
 #define ACPI_ROUND_BITS_DOWN_TO_BYTES(a)    ACPI_DIV_8((a))
@@ -322,7 +322,7 @@ struct acpi_integer_overlay {
 
 #define ACPI_ROUND_UP_TO(value,boundary)    (((value) + ((boundary)-1)) / (boundary))
 
-#define ACPI_IS_MISALIGNED(value)           (((acpi_native_uint)value) & (sizeof(acpi_native_uint)-1))
+#define ACPI_IS_MISALIGNED(value)           (((acpi_size)value) & (sizeof(acpi_size)-1))
 
 /*
  * Bitmask creation
@@ -414,7 +414,7 @@ struct acpi_integer_overlay {
  * error messages. The __FILE__ macro is not very useful for this, because it
  * often includes the entire pathname to the module
  */
-#define ACPI_MODULE_NAME(name)          static char ACPI_UNUSED_VAR *_acpi_module_name = name;
+#define ACPI_MODULE_NAME(name)          static const char ACPI_UNUSED_VAR _acpi_module_name[] = name;
 #else
 #define ACPI_MODULE_NAME(name)
 #endif
@@ -467,19 +467,17 @@ struct acpi_integer_overlay {
 /*
  * If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header,
  * define it now. This is the case where there the compiler does not support
- * a __FUNCTION__ macro or equivalent. We save the function name on the
- * local stack.
+ * a __FUNCTION__ macro or equivalent.
  */
 #ifndef ACPI_GET_FUNCTION_NAME
 #define ACPI_GET_FUNCTION_NAME          _acpi_function_name
 /*
  * The Name parameter should be the procedure name as a quoted string.
- * This is declared as a local string ("MyFunctionName") so that it can
- * be also used by the function exit macros below.
+ * The function name is also used by the function exit macros below.
  * Note: (const char) is used to be compatible with the debug interfaces
  * and macros such as __FUNCTION__.
  */
-#define ACPI_FUNCTION_NAME(name)        const char *_acpi_function_name = #name;
+#define ACPI_FUNCTION_NAME(name)        static const char _acpi_function_name[] = #name;
 
 #else
 /* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */
@@ -599,7 +597,7 @@ struct acpi_integer_overlay {
 /* Stack and buffer dumping */
 
 #define ACPI_DUMP_STACK_ENTRY(a)        acpi_ex_dump_operand((a),0)
-#define ACPI_DUMP_OPERANDS(a,b,c,d,e)   acpi_ex_dump_operands(a,b,c,d,e,_acpi_module_name,__LINE__)
+#define ACPI_DUMP_OPERANDS(a,b,c)       acpi_ex_dump_operands(a,b,c)
 
 #define ACPI_DUMP_ENTRY(a,b)            acpi_ns_dump_entry (a,b)
 #define ACPI_DUMP_PATHNAME(a,b,c,d)     acpi_ns_dump_pathname(a,b,c,d)
@@ -635,7 +633,7 @@ struct acpi_integer_overlay {
 #define ACPI_FUNCTION_VALUE_EXIT(s)     do { } while(0)
 #define ACPI_FUNCTION_ENTRY()           do { } while(0)
 #define ACPI_DUMP_STACK_ENTRY(a)        do { } while(0)
-#define ACPI_DUMP_OPERANDS(a,b,c,d,e)   do { } while(0)
+#define ACPI_DUMP_OPERANDS(a,b,c)      do { } while(0)
 #define ACPI_DUMP_ENTRY(a,b)            do { } while(0)
 #define ACPI_DUMP_TABLES(a,b)           do { } while(0)
 #define ACPI_DUMP_PATHNAME(a,b,c,d)     do { } while(0)
diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h
index 713b30903fe5..9ed70a050580 100644
--- a/include/acpi/acnamesp.h
+++ b/include/acpi/acnamesp.h
@@ -86,8 +86,7 @@ acpi_status acpi_ns_initialize_devices(void);
 acpi_status acpi_ns_load_namespace(void);
 
 acpi_status
-acpi_ns_load_table(acpi_native_uint table_index,
-                   struct acpi_namespace_node *node);
+acpi_ns_load_table(u32 table_index, struct acpi_namespace_node *node);
 
 /*
  * nswalk - walk the namespace
@@ -108,12 +107,11 @@ struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type, struct
  * nsparse - table parsing
  */
 acpi_status
-acpi_ns_parse_table(acpi_native_uint table_index,
-                    struct acpi_namespace_node *start_node);
+acpi_ns_parse_table(u32 table_index, struct acpi_namespace_node *start_node);
 
 acpi_status
-acpi_ns_one_complete_parse(acpi_native_uint pass_number,
-                           acpi_native_uint table_index,
+acpi_ns_one_complete_parse(u32 pass_number,
+                           u32 table_index,
                            struct acpi_namespace_node *start_node);
 
 /*
@@ -201,7 +199,7 @@ acpi_ns_pattern_match(struct acpi_namespace_node *obj_node, char *search_for);
 
 acpi_status
 acpi_ns_get_node(struct acpi_namespace_node *prefix_node,
-                 char *external_pathname,
+                 const char *external_pathname,
                  u32 flags, struct acpi_namespace_node **out_node);
 
 acpi_size acpi_ns_get_pathname_length(struct acpi_namespace_node *node);
@@ -265,28 +263,30 @@ acpi_object_type acpi_ns_get_type(struct acpi_namespace_node *node);
 u32 acpi_ns_local(acpi_object_type type);
 
 void
-acpi_ns_report_error(char *module_name,
+acpi_ns_report_error(const char *module_name,
                      u32 line_number,
-                     char *internal_name, acpi_status lookup_status);
+                     const char *internal_name, acpi_status lookup_status);
 
 void
-acpi_ns_report_method_error(char *module_name,
+acpi_ns_report_method_error(const char *module_name,
                             u32 line_number,
-                            char *message,
+                            const char *message,
                             struct acpi_namespace_node *node,
-                            char *path, acpi_status lookup_status);
+                            const char *path, acpi_status lookup_status);
 
-void acpi_ns_print_node_pathname(struct acpi_namespace_node *node, char *msg);
+void
+acpi_ns_print_node_pathname(struct acpi_namespace_node *node, const char *msg);
 
 acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info);
 
 void acpi_ns_get_internal_name_length(struct acpi_namestring_info *info);
 
-acpi_status acpi_ns_internalize_name(char *dotted_name, char **converted_name);
+acpi_status
+acpi_ns_internalize_name(const char *dotted_name, char **converted_name);
 
 acpi_status
 acpi_ns_externalize_name(u32 internal_name_length,
-                         char *internal_name,
+                         const char *internal_name,
                          u32 * converted_name_length, char **converted_name);
 
 struct acpi_namespace_node *acpi_ns_map_handle_to_node(acpi_handle handle);
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index 2f1c68c7a727..a5ac0bc7f52e 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -259,6 +259,7 @@ struct acpi_device_perf {
 /* Wakeup Management */
 struct acpi_device_wakeup_flags {
         u8 valid:1;             /* Can successfully enable wakeup? */
+        u8 prepared:1;          /* Has the wake-up capability been enabled? */
         u8 run_wake:1;          /* Run-Wake GPE devices */
 };
 
@@ -335,6 +336,8 @@ void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context);
 int acpi_bus_get_status(struct acpi_device *device);
 int acpi_bus_get_power(acpi_handle handle, int *state);
 int acpi_bus_set_power(acpi_handle handle, int state);
+bool acpi_bus_power_manageable(acpi_handle handle);
+bool acpi_bus_can_wakeup(acpi_handle handle);
 #ifdef CONFIG_ACPI_PROC_EVENT
 int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data);
 int acpi_bus_generate_proc_event4(const char *class, const char *bid, u8 type, int data);
@@ -376,14 +379,19 @@ acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int);
 #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle))
 
 #ifdef CONFIG_PM_SLEEP
-int acpi_pm_device_sleep_state(struct device *, int, int *);
+int acpi_pm_device_sleep_state(struct device *, int *);
+int acpi_pm_device_sleep_wake(struct device *, bool);
 #else /* !CONFIG_PM_SLEEP */
-static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p)
+static inline int acpi_pm_device_sleep_state(struct device *d, int *p)
 {
         if (p)
                 *p = ACPI_STATE_D0;
         return ACPI_STATE_D3;
 }
+static inline int acpi_pm_device_sleep_wake(struct device *dev, bool enable)
+{
+        return -ENODEV;
+}
 #endif /* !CONFIG_PM_SLEEP */
 
 #endif                          /* CONFIG_ACPI */
diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h
index 9757a040a505..e5f38e5ce86f 100644
--- a/include/acpi/acpi_drivers.h
+++ b/include/acpi/acpi_drivers.h
@@ -87,7 +87,9 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain,
    -------------------------------------------------------------------------- */
 
 #ifdef CONFIG_ACPI_POWER
-int acpi_enable_wakeup_device_power(struct acpi_device *dev);
+int acpi_device_sleep_wake(struct acpi_device *dev,
+                           int enable, int sleep_state, int dev_state);
+int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state);
 int acpi_disable_wakeup_device_power(struct acpi_device *dev);
 int acpi_power_get_inferred_state(struct acpi_device *device);
 int acpi_power_transition(struct acpi_device *device, int state);
diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h
index d4a560d2deb6..3f93a6b4e17f 100644
--- a/include/acpi/acpiosxf.h
+++ b/include/acpi/acpiosxf.h
@@ -144,7 +144,7 @@ void acpi_os_release_mutex(acpi_mutex handle);
 void *acpi_os_allocate(acpi_size size);
 
 void __iomem *acpi_os_map_memory(acpi_physical_address where,
-                                 acpi_native_uint length);
+                                acpi_size length);
 
 void acpi_os_unmap_memory(void __iomem * logical_address, acpi_size size);
 
diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index 2c3806e6546f..94d94e126e9f 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -98,7 +98,7 @@ void acpi_free(void *address);
  */
 acpi_status acpi_reallocate_root_table(void);
 
-acpi_status acpi_find_root_pointer(acpi_native_uint * rsdp_address);
+acpi_status acpi_find_root_pointer(acpi_size *rsdp_address);
 
 acpi_status acpi_load_tables(void);
 
@@ -108,15 +108,15 @@ acpi_status acpi_unload_table_id(acpi_owner_id id);
 
 acpi_status
 acpi_get_table_header(acpi_string signature,
-                      acpi_native_uint instance,
+                      u32 instance,
                       struct acpi_table_header *out_table_header);
 
 acpi_status
 acpi_get_table(acpi_string signature,
-               acpi_native_uint instance, struct acpi_table_header **out_table);
+               u32 instance, struct acpi_table_header **out_table);
 
 acpi_status
-acpi_get_table_by_index(acpi_native_uint table_index,
+acpi_get_table_by_index(u32 table_index,
                         struct acpi_table_header **out_table);
 
 acpi_status
@@ -248,9 +248,7 @@ acpi_status acpi_disable_event(u32 event, u32 flags);
 
 acpi_status acpi_clear_event(u32 event);
 
-#ifdef ACPI_FUTURE_USAGE
 acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status);
-#endif                          /*  ACPI_FUTURE_USAGE  */
 
 acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type);
 
@@ -260,12 +258,10 @@ acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
 
 acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
 
-#ifdef ACPI_FUTURE_USAGE
 acpi_status
 acpi_get_gpe_status(acpi_handle gpe_device,
                     u32 gpe_number,
                     u32 flags, acpi_event_status * event_status);
-#endif                          /*  ACPI_FUTURE_USAGE  */
 
 acpi_status
 acpi_install_gpe_block(acpi_handle gpe_device,
diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h
index a907c67d651e..7980a26bad35 100644
--- a/include/acpi/acstruct.h
+++ b/include/acpi/acstruct.h
@@ -108,7 +108,6 @@ struct acpi_walk_state {
         union acpi_operand_object **caller_return_desc;
         union acpi_generic_state *control_state;        /* List of control states (nested IFs) */
         struct acpi_namespace_node *deferred_node;      /* Used when executing deferred opcodes */
-        struct acpi_gpe_event_info *gpe_event_info;     /* Info for GPE (_Lxx/_Exx methods only */
         union acpi_operand_object *implicit_return_obj;
         struct acpi_namespace_node *method_call_node;   /* Called method Node */
         union acpi_parse_object *method_call_op;        /* method_call Op if running a method */
@@ -143,7 +142,7 @@ struct acpi_init_walk_info {
         u16 package_init;
         u16 object_count;
         acpi_owner_id owner_id;
-        acpi_native_uint table_index;
+        u32 table_index;
 };
 
 struct acpi_get_devices_info {
@@ -189,17 +188,12 @@ struct acpi_evaluate_info {
         union acpi_operand_object **parameters;
         struct acpi_namespace_node *resolved_node;
         union acpi_operand_object *return_object;
+        u8 param_count;
         u8 pass_number;
-        u8 parameter_type;
         u8 return_object_type;
         u8 flags;
 };
 
-/* Types for parameter_type above */
-
-#define ACPI_PARAM_ARGS                 0
-#define ACPI_PARAM_GPE                  1
-
 /* Values for Flags above */
 
 #define ACPI_IGNORE_RETURN_VALUE        1
diff --git a/include/acpi/actables.h b/include/acpi/actables.h
index 4b36a55b0b3b..0cbe1b9ab522 100644
--- a/include/acpi/actables.h
+++ b/include/acpi/actables.h
@@ -49,7 +49,7 @@ acpi_status acpi_allocate_root_table(u32 initial_table_count);
 /*
  * tbfadt - FADT parse/convert/validate
  */
-void acpi_tb_parse_fadt(acpi_native_uint table_index, u8 flags);
+void acpi_tb_parse_fadt(u32 table_index, u8 flags);
 
 void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length);
 
@@ -58,8 +58,7 @@ void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length);
  */
 acpi_status
 acpi_tb_find_table(char *signature,
-                   char *oem_id,
-                   char *oem_table_id, acpi_native_uint * table_index);
+                   char *oem_id, char *oem_table_id, u32 *table_index);
 
 /*
  * tbinstal - Table removal and deletion
@@ -69,30 +68,28 @@ acpi_status acpi_tb_resize_root_table_list(void);
 acpi_status acpi_tb_verify_table(struct acpi_table_desc *table_desc);
 
 acpi_status
-acpi_tb_add_table(struct acpi_table_desc *table_desc,
-                  acpi_native_uint * table_index);
+acpi_tb_add_table(struct acpi_table_desc *table_desc, u32 *table_index);
 
 acpi_status
 acpi_tb_store_table(acpi_physical_address address,
                     struct acpi_table_header *table,
-                    u32 length, u8 flags, acpi_native_uint * table_index);
+                    u32 length, u8 flags, u32 *table_index);
 
 void acpi_tb_delete_table(struct acpi_table_desc *table_desc);
 
 void acpi_tb_terminate(void);
 
-void acpi_tb_delete_namespace_by_owner(acpi_native_uint table_index);
+void acpi_tb_delete_namespace_by_owner(u32 table_index);
 
-acpi_status acpi_tb_allocate_owner_id(acpi_native_uint table_index);
+acpi_status acpi_tb_allocate_owner_id(u32 table_index);
 
-acpi_status acpi_tb_release_owner_id(acpi_native_uint table_index);
+acpi_status acpi_tb_release_owner_id(u32 table_index);
 
-acpi_status
-acpi_tb_get_owner_id(acpi_native_uint table_index, acpi_owner_id * owner_id);
+acpi_status acpi_tb_get_owner_id(u32 table_index, acpi_owner_id *owner_id);
 
-u8 acpi_tb_is_table_loaded(acpi_native_uint table_index);
+u8 acpi_tb_is_table_loaded(u32 table_index);
 
-void acpi_tb_set_table_loaded_flag(acpi_native_uint table_index, u8 is_loaded);
+void acpi_tb_set_table_loaded_flag(u32 table_index, u8 is_loaded);
 
 /*
  * tbutils - table manager utilities
@@ -103,14 +100,14 @@ void
 acpi_tb_print_table_header(acpi_physical_address address,
                            struct acpi_table_header *header);
 
-u8 acpi_tb_checksum(u8 * buffer, acpi_native_uint length);
+u8 acpi_tb_checksum(u8 *buffer, u32 length);
 
 acpi_status
 acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length);
 
 void
 acpi_tb_install_table(acpi_physical_address address,
-                      u8 flags, char *signature, acpi_native_uint table_index);
+                      u8 flags, char *signature, u32 table_index);
 
 acpi_status
 acpi_tb_parse_root_table(acpi_physical_address rsdp_address, u8 flags);
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 9af239bd1153..d38f9be2f6ee 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -300,6 +300,7 @@ struct acpi_table_dbgp {
 /*******************************************************************************
  *
  * DMAR - DMA Remapping table
+ *        From "Intel Virtualization Technology for Directed I/O", Sept. 2007
  *
  ******************************************************************************/
 
@@ -310,6 +311,10 @@ struct acpi_table_dmar {
         u8 reserved[10];
 };
 
+/* Flags */
+
+#define ACPI_DMAR_INTR_REMAP        (1)
+
 /* DMAR subtable header */
 
 struct acpi_dmar_header {
@@ -382,6 +387,20 @@ struct acpi_dmar_reserved_memory {
 
 #define ACPI_DMAR_ALLOW_ALL         (1)
 
+
+/* 2: Root Port ATS Capability Reporting Structure */
+
+struct acpi_dmar_atsr {
+       struct acpi_dmar_header header;
+       u8 flags;
+       u8 reserved;
+       u16 segment;
+};
+
+/* Flags */
+
+#define ACPI_DMAR_ALL_PORTS         (1)
+
 /*******************************************************************************
  *
  * ECDT - Embedded Controller Boot Resources Table
@@ -1156,9 +1175,9 @@ struct acpi_srat_mem_affinity {
         u16 reserved;           /* Reserved, must be zero */
         u64 base_address;
         u64 length;
-        u32 memory_type;        /* See acpi_address_range_id */
+       u32 reserved1;
         u32 flags;
-        u64 reserved1;          /* Reserved, must be zero */
+       u64 reserved2;          /* Reserved, must be zero */
 };
 
 /* Flags */
diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
index dfea2d440488..4ea4f40bf894 100644
--- a/include/acpi/actypes.h
+++ b/include/acpi/actypes.h
@@ -110,10 +110,10 @@
  * usually used for memory allocation, efficient loop counters, and array
  * indexes. The types are similar to the size_t type in the C library and are
  * required because there is no C type that consistently represents the native
- * data width.
+ * data width. ACPI_SIZE is needed because there is no guarantee that a
+ * kernel-level C library is present.
  *
  * ACPI_SIZE        16/32/64-bit unsigned value
- * ACPI_NATIVE_UINT 16/32/64-bit unsigned value
  * ACPI_NATIVE_INT  16/32/64-bit signed value
  *
  */
@@ -147,9 +147,9 @@ typedef int INT32;
 
 /*! [End] no source code translation !*/
 
-typedef u64 acpi_native_uint;
 typedef s64 acpi_native_int;
 
+typedef u64 acpi_size;
 typedef u64 acpi_io_address;
 typedef u64 acpi_physical_address;
 
@@ -186,9 +186,9 @@ typedef int INT32;
 
 /*! [End] no source code translation !*/
 
-typedef u32 acpi_native_uint;
 typedef s32 acpi_native_int;
 
+typedef u32 acpi_size;
 typedef u32 acpi_io_address;
 typedef u32 acpi_physical_address;
 
@@ -202,10 +202,6 @@ typedef u32 acpi_physical_address;
 #error unknown ACPI_MACHINE_WIDTH
 #endif
 
-/* Variable-width type, used instead of clib size_t */
-
-typedef acpi_native_uint acpi_size;
-
 /*******************************************************************************
  *
  * OS-dependent and compiler-dependent types
@@ -219,7 +215,7 @@ typedef acpi_native_uint acpi_size;
 /* Value returned by acpi_os_get_thread_id */
 
 #ifndef acpi_thread_id
-#define acpi_thread_id                  acpi_native_uint
+#define acpi_thread_id                  acpi_size
 #endif
 
 /* Object returned from acpi_os_create_lock */
@@ -231,7 +227,7 @@ typedef acpi_native_uint acpi_size;
 /* Flags for acpi_os_acquire_lock/acpi_os_release_lock */
 
 #ifndef acpi_cpu_flags
-#define acpi_cpu_flags                  acpi_native_uint
+#define acpi_cpu_flags                  acpi_size
 #endif
 
 /* Object returned from acpi_os_create_cache */
diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h
index b42cadf07302..69f8888771ff 100644
--- a/include/acpi/acutils.h
+++ b/include/acpi/acutils.h
@@ -172,7 +172,7 @@ char *acpi_ut_strstr(char *string1, char *string2);
 
 void *acpi_ut_memcpy(void *dest, const void *src, acpi_size count);
 
-void *acpi_ut_memset(void *dest, acpi_native_uint value, acpi_size count);
+void *acpi_ut_memset(void *dest, u8 value, acpi_size count);
 
 int acpi_ut_to_upper(int c);
 
@@ -245,41 +245,45 @@ void acpi_ut_track_stack_ptr(void);
 
 void
 acpi_ut_trace(u32 line_number,
-              const char *function_name, char *module_name, u32 component_id);
+              const char *function_name,
+              const char *module_name, u32 component_id);
 
 void
 acpi_ut_trace_ptr(u32 line_number,
                   const char *function_name,
-                  char *module_name, u32 component_id, void *pointer);
+                  const char *module_name, u32 component_id, void *pointer);
 
 void
 acpi_ut_trace_u32(u32 line_number,
                   const char *function_name,
-                  char *module_name, u32 component_id, u32 integer);
+                  const char *module_name, u32 component_id, u32 integer);
 
 void
 acpi_ut_trace_str(u32 line_number,
                   const char *function_name,
-                  char *module_name, u32 component_id, char *string);
+                  const char *module_name, u32 component_id, char *string);
 
 void
 acpi_ut_exit(u32 line_number,
-             const char *function_name, char *module_name, u32 component_id);
+             const char *function_name,
+             const char *module_name, u32 component_id);
 
 void
 acpi_ut_status_exit(u32 line_number,
                     const char *function_name,
-                    char *module_name, u32 component_id, acpi_status status);
+                    const char *module_name,
+                    u32 component_id, acpi_status status);
 
 void
 acpi_ut_value_exit(u32 line_number,
                    const char *function_name,
-                   char *module_name, u32 component_id, acpi_integer value);
+                   const char *module_name,
+                   u32 component_id, acpi_integer value);
 
 void
 acpi_ut_ptr_exit(u32 line_number,
                  const char *function_name,
-                 char *module_name, u32 component_id, u8 * ptr);
+                 const char *module_name, u32 component_id, u8 *ptr);
 
 void acpi_ut_dump_buffer(u8 * buffer, u32 count, u32 display, u32 component_id);
 
@@ -297,33 +301,35 @@ void ACPI_INTERNAL_VAR_XFACE
 acpi_ut_debug_print(u32 requested_debug_level,
                     u32 line_number,
                     const char *function_name,
-                    char *module_name,
-                    u32 component_id, char *format, ...) ACPI_PRINTF_LIKE(6);
+                    const char *module_name,
+                    u32 component_id,
+                    const char *format, ...) ACPI_PRINTF_LIKE(6);
 
 void ACPI_INTERNAL_VAR_XFACE
 acpi_ut_debug_print_raw(u32 requested_debug_level,
                         u32 line_number,
                         const char *function_name,
-                        char *module_name,
+                        const char *module_name,
                         u32 component_id,
-                        char *format, ...) ACPI_PRINTF_LIKE(6);
+                        const char *format, ...) ACPI_PRINTF_LIKE(6);
 
 void ACPI_INTERNAL_VAR_XFACE
-acpi_ut_error(char *module_name,
-              u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3);
+acpi_ut_error(const char *module_name,
+              u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3);
 
 void ACPI_INTERNAL_VAR_XFACE
-acpi_ut_exception(char *module_name,
+acpi_ut_exception(const char *module_name,
                   u32 line_number,
-                  acpi_status status, char *format, ...) ACPI_PRINTF_LIKE(4);
+                  acpi_status status,
+                  const char *format, ...) ACPI_PRINTF_LIKE(4);
 
 void ACPI_INTERNAL_VAR_XFACE
-acpi_ut_warning(char *module_name,
-                u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3);
+acpi_ut_warning(const char *module_name,
+                u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3);
 
 void ACPI_INTERNAL_VAR_XFACE
-acpi_ut_info(char *module_name,
-             u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3);
+acpi_ut_info(const char *module_name,
+             u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3);
 
 /*
  * utdelete - Object deletion and reference counts
@@ -376,13 +382,14 @@ acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest);
 /*
  * utobject - internal object create/delete/cache routines
  */
-union acpi_operand_object *acpi_ut_create_internal_object_dbg(char *module_name,
+union acpi_operand_object *acpi_ut_create_internal_object_dbg(const char
+                                                              *module_name,
                                                               u32 line_number,
                                                               u32 component_id,
                                                               acpi_object_type
                                                               type);
 
-void *acpi_ut_allocate_object_desc_dbg(char *module_name,
+void *acpi_ut_allocate_object_desc_dbg(const char *module_name,
                                        u32 line_number, u32 component_id);
 
 #define acpi_ut_create_internal_object(t) acpi_ut_create_internal_object_dbg (_acpi_module_name,__LINE__,_COMPONENT,t)
@@ -476,7 +483,7 @@ u8 acpi_ut_valid_acpi_name(u32 name);
 
 acpi_name acpi_ut_repair_name(char *name);
 
-u8 acpi_ut_valid_acpi_char(char character, acpi_native_uint position);
+u8 acpi_ut_valid_acpi_char(char character, u32 position);
 
 acpi_status
 acpi_ut_strtoul64(char *string, u32 base, acpi_integer * ret_integer);
@@ -543,26 +550,29 @@ acpi_status
 acpi_ut_initialize_buffer(struct acpi_buffer *buffer,
                           acpi_size required_length);
 
-void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line);
+void *acpi_ut_allocate(acpi_size size,
+                       u32 component, const char *module, u32 line);
 
 void *acpi_ut_allocate_zeroed(acpi_size size,
-                              u32 component, char *module, u32 line);
+                              u32 component, const char *module, u32 line);
 
 #ifdef ACPI_DBG_TRACK_ALLOCATIONS
 void *acpi_ut_allocate_and_track(acpi_size size,
-                                 u32 component, char *module, u32 line);
+                                 u32 component, const char *module, u32 line);
 
 void *acpi_ut_allocate_zeroed_and_track(acpi_size size,
-                                        u32 component, char *module, u32 line);
+                                        u32 component,
+                                        const char *module, u32 line);
 
 void
-acpi_ut_free_and_track(void *address, u32 component, char *module, u32 line);
+acpi_ut_free_and_track(void *address,
+                       u32 component, const char *module, u32 line);
 
 #ifdef  ACPI_FUTURE_USAGE
 void acpi_ut_dump_allocation_info(void);
 #endif                          /* ACPI_FUTURE_USAGE */
 
-void acpi_ut_dump_allocations(u32 component, char *module);
+void acpi_ut_dump_allocations(u32 component, const char *module);
 
 acpi_status
 acpi_ut_create_list(char *list_name,
diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 06ebb6ef72aa..3795590e152a 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -255,7 +255,7 @@ extern void acpi_processor_unregister_performance(struct
 int acpi_processor_notify_smm(struct module *calling_module);
 
 /* for communication between multiple parts of the processor kernel module */
-extern struct acpi_processor *processors[NR_CPUS];
+DECLARE_PER_CPU(struct acpi_processor *, processors);
 extern struct acpi_processor_errata errata;
 
 void arch_acpi_processor_init_pdc(struct acpi_processor *pr);
diff --git a/include/acpi/reboot.h b/include/acpi/reboot.h
index 8857f57e0b78..0419184ce886 100644
--- a/include/acpi/reboot.h
+++ b/include/acpi/reboot.h
@@ -1,9 +1,11 @@
+#ifndef __ACPI_REBOOT_H
+#define __ACPI_REBOOT_H
+
+#ifdef CONFIG_ACPI
+extern void acpi_reboot(void);
+#else
+static inline void acpi_reboot(void) { }
+#endif
 
-/*
- * Dummy placeholder to make the EFI patches apply to the x86 tree.
- * Andrew/Len, please just kill this file if you encounter it.
- */
-#ifndef acpi_reboot
-# define acpi_reboot() do { } while (0)
 #endif
 
diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h
index 286e1d844f63..544c69af8168 100644
--- a/include/asm-alpha/smp.h
+++ b/include/asm-alpha/smp.h
@@ -47,12 +47,13 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS];
 extern int smp_num_cpus;
 #define cpu_possible_map        cpu_present_map
 
-int smp_call_function_on_cpu(void (*func) (void *info), void *info,int retry, int wait, cpumask_t cpu);
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
 
 #else /* CONFIG_SMP */
 
 #define hard_smp_processor_id()         0
-#define smp_call_function_on_cpu(func,info,retry,wait,cpu)    ({ 0; })
+#define smp_call_function_on_cpu(func,info,wait,cpu)    ({ 0; })
 
 #endif /* CONFIG_SMP */
 
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index 1551fc24eb43..400ec10014b4 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -75,6 +75,10 @@
 #define                 AT91_MCI_TRTYP_MULTIPLE (1 << 19)
 #define                 AT91_MCI_TRTYP_STREAM   (2 << 19)
 
+#define AT91_MCI_BLKR           0x18            /* Block Register */
+#define         AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
+#define         AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)  /* Block lenght */
+
 #define AT91_MCI_RSPR(n)        (0x20 + ((n) * 4))      /* Response Registers 0-3 */
 #define AT91_MCR_RDR            0x30            /* Receive Data Register */
 #define AT91_MCR_TDR            0x34            /* Transmit Data Register */
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index c2b13c280155..2001e81f2267 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -39,10 +39,14 @@
 #define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
 
 #define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+#define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
+#define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
+#define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
+#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI PLL Start-up Time */
 
 #define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
+#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
 #define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
 
 #define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
@@ -97,6 +101,7 @@
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [AT91CAP9 only] */
 #define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index bac83adb5050..6f14d9053ac7 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -118,7 +118,7 @@
 #define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
 
 #define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_BASE     0x00600000      /* USB High Speed Device Port */
+#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
 #define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
 
 #define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
index a641686b6c3d..ddbd4873c842 100644
--- a/include/asm-arm/arch-at91/at91cap9_matrix.h
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -106,6 +106,11 @@
 #define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
 #define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
 
+#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
+#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
+#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
+#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
+
 #define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index c8934fe34dc5..889872a3f2a9 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -6,6 +6,8 @@
  * Common definitions.
  * Based on AT91SAM9260 datasheet revision A (Preliminary).
  *
+ * Includes also definitions for AT91SAM9XE and AT91SAM9G families
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -123,5 +125,14 @@
 #define AT91SAM9XE_FLASH_BASE   0x00200000      /* Internal FLASH base address */
 #define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
 
+#define AT91SAM9G20_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9G20_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9G20_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
+#define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+
+#define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 16d2832f6c0a..622e56f81d42 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -110,6 +110,6 @@
 #define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
 
 #define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
-#define AT91SAM9RL_UDPHS_BASE   0x00600000      /* USB Device HS controller */
+#define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
 
 #endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index dc189f01c5b3..94de788da76e 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -36,6 +36,7 @@
 #include <linux/i2c.h>
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
 
  /* USB Device */
 struct at91_udc_data {
@@ -45,6 +46,9 @@ struct at91_udc_data {
 };
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
 
+ /* USB High Speed Device */
+extern void __init at91_add_device_usba(struct usba_platform_data *data);
+
  /* Compact Flash */
 struct at91_cf_data {
         u8      irq_pin;                /* I/O IRQ */
@@ -73,7 +77,7 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
 #define eth_platform_data       at91_eth_data
 #endif
 
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7145166826a2..52df794205cb 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,6 +21,7 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9G20     0x019905a0
 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
 #define ARCH_ID_AT91CAP9        0x039A03A0
 
@@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void)
 #define cpu_is_at91sam9260()    (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91SAM9G20
+#define cpu_is_at91sam9g20()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
+#else
+#define cpu_is_at91sam9g20()    (0)
+#endif
+
 #ifdef CONFIG_ARCH_AT91SAM9261
 #define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
 #else
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 2c826d8247a3..016a3a3f6633 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -18,7 +18,7 @@
 
 #if defined(CONFIG_ARCH_AT91RM9200)
 #include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_ARCH_AT91SAM9260)
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #include <asm/arch/at91sam9260.h>
 #elif defined(CONFIG_ARCH_AT91SAM9261)
 #include <asm/arch/at91sam9261.h>
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f1933b0fa43f..298d8313cdac 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -27,14 +27,29 @@
 
 #define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
 
-#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+
+#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
+#define AT91SAM9_MASTER_CLOCK   99300000
+#endif
+
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91SAM9261)
 
 #define AT91SAM9_MASTER_CLOCK   99300000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 
+#if defined(CONFIG_MACH_USB_A9263)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
 #define AT91SAM9_MASTER_CLOCK   99959500
+#endif
+
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
@@ -42,6 +57,11 @@
 #define AT91SAM9_MASTER_CLOCK   100000000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
+#elif defined(CONFIG_ARCH_AT91SAM9G20)
+
+#define AT91SAM9_MASTER_CLOCK   132096000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
 #elif defined(CONFIG_ARCH_AT91CAP9)
 
 #define AT91CAP9_MASTER_CLOCK   100000000
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index daad8ee2d194..74610c2c63d4 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -14,7 +14,6 @@
 
 #include <asm/arch/memory.h>
 
-#ifdef CONFIG_ARCH_FOOTBRIDGE
 /*   Virtual      Physical      Size
  * 0xff800000   0x40000000      1MB     X-Bus
  * 0xff000000   0x7c000000      1MB     PCI I/O space
@@ -50,31 +49,6 @@
 #define PCIMEM_SIZE             0x01000000
 #define PCIMEM_BASE             0xf0000000
 
-#elif defined(CONFIG_ARCH_CO285)
-/*
- * This is the COEBSA285 cut-down mapping
- */
-#define PCIMEM_SIZE             0x80000000
-#define PCIMEM_BASE             0x80000000
-
-#define WFLUSH_SIZE             0x01000000
-#define WFLUSH_BASE             0x7d000000
-
-#define ARMCSR_SIZE             0x00100000
-#define ARMCSR_BASE             0x7cf00000
-
-#define XBUS_SIZE               0x00020000
-#define XBUS_BASE               0x7cee0000
-
-#define PCIO_SIZE               0x00010000
-#define PCIO_BASE               0x7ced0000
-
-#else
-
-#error "Undefined footbridge architecture"
-
-#endif
-
 #define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
 #define XBUS_LED_AMBER          (1 << 0)
 #define XBUS_LED_GREEN          (1 << 1)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index cbd7ae64bcc9..9019a3bf5ab9 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
 
 #endif
 
-#if defined(CONFIG_ARCH_FOOTBRIDGE)
-
 /* Task size and page offset at 3GB */
 #define TASK_SIZE               UL(0xbf000000)
 #define PAGE_OFFSET             UL(0xc0000000)
@@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long);
  */
 #define FLUSH_BASE              0xf9000000
 
-#elif defined(CONFIG_ARCH_CO285)
-
-/* Task size and page offset at 1.5GB */
-#define TASK_SIZE               UL(0x5f000000)
-#define PAGE_OFFSET             UL(0x60000000)
-
-/*
- * Cache flushing area.
- */
-#define FLUSH_BASE              0x7e000000
-
-#else
-
-#error "Undefined footbridge architecture"
-
-#endif
-
 /*
  * Physical DRAM offset.
  */
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index 02598200997d..e487d7e8c8a6 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -7,8 +7,4 @@
  */
 
 
-#ifdef CONFIG_ARCH_FOOTBRIDGE
 #define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
-#else
-#define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
-#endif
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
index adffb6acf42a..6542ca5e8c33 100644
--- a/include/asm-arm/arch-imx/hardware.h
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -73,14 +73,6 @@
  */
 extern void imx_gpio_mode( int gpio_mode );
 
-/* get frequencies in Hz */
-extern unsigned int imx_get_system_clk(void);
-extern unsigned int imx_get_mcu_clk(void);
-extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
-extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12]         */
-extern unsigned int imx_get_perclk3(void); /* SSI                      */
-extern unsigned int imx_get_hclk(void);    /* SDRAM, CSI, Memory Stick,*/
-                                           /* I2C, DMA                 */
 #endif
 
 #define MAXIRQNUM                       62
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h
index 5b1066da4e1f..44d89c35539a 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/include/asm-arm/arch-imx/imx-dma.h
@@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name);
 
 void imx_dma_free(imx_dmach_t dma_ch);
 
-int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio);
+imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
 
 
 #endif  /* _ASM_ARCH_IMX_DMA_H */
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h
index 3a685e1780ea..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/include/asm-arm/arch-imx/imx-uart.h
@@ -4,6 +4,8 @@
 #define IMXUART_HAVE_RTSCTS (1<<0)
 
 struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        void (*exit)(struct platform_device *pdev);
         unsigned int flags;
 };
 
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
index 2e15da53ff79..d79846fbb394 100644
--- a/include/asm-arm/arch-iop13xx/dma.h
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -1,3 +1,3 @@
 #ifndef _IOP13XX_DMA_H
-#define _IOP13XX_DMA_H_
+#define _IOP13XX_DMA_H
 #endif
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h
new file mode 100644
index 000000000000..708f4ec9db1d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP32X_GPIO_H
+#define __ASM_ARCH_IOP32X_GPIO_H
+
+#include <asm/hardware/iop3xx-gpio.h>
+
+#endif
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h
new file mode 100644
index 000000000000..ddd55bba9bb9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP33X_GPIO_H
+#define __ASM_ARCH_IOP33X_GPIO_H
+
+#include <asm/hardware/iop3xx-gpio.h>
+
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h
new file mode 100644
index 000000000000..c0100cc7981c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/fsg.h
@@ -0,0 +1,50 @@
+/*
+ * include/asm-arm/arch-ixp4xx/fsg.h
+ *
+ * Freecom FSG-3 platform specific definitions
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
+ * Maintainers: http://www.nslu2-linux.org
+ *
+ * Based on coyote.h by
+ * Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#define FSG_SDA_PIN             12
+#define FSG_SCL_PIN             13
+
+/*
+ * FSG PCI IRQs
+ */
+#define FSG_PCI_MAX_DEV         3
+#define FSG_PCI_IRQ_LINES       3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define FSG_PCI_INTA_PIN        6
+#define FSG_PCI_INTB_PIN        7
+#define FSG_PCI_INTC_PIN        5
+
+/* Buttons */
+
+#define FSG_SB_GPIO             4       /* sync button */
+#define FSG_RB_GPIO             9       /* reset button */
+#define FSG_UB_GPIO             10      /* usb button */
+
+/* LEDs */
+
+#define FSG_LED_WLAN_BIT        0
+#define FSG_LED_WAN_BIT         1
+#define FSG_LED_SATA_BIT        2
+#define FSG_LED_USB_BIT         4
+#define FSG_LED_RING_BIT        5
+#define FSG_LED_SYNC_BIT        7
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 73e8dc36f6a4..fa723a627854 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -45,5 +45,6 @@
 #include "nslu2.h"
 #include "nas100d.h"
 #include "dsmg600.h"
+#include "fsg.h"
 
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index 11801605047b..674af4a84147 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -128,4 +128,11 @@
 #define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
 #define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
 
+/*
+ * Freecom FSG-3 Board IRQs
+ */
+#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
+#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
+#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
+
 #endif
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S
new file mode 100644
index 000000000000..f55fb8ad9ee4
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-kirkwood/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/kirkwood.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
+        ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S
new file mode 100644
index 000000000000..fc6a43d9355c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/entry-macro.S
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-kirkwood/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Kirkwood platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/kirkwood.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        bne     1001f
+
+        @ if no low interrupts set, check high interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        mov     \irqnr, #63
+        ands    \irqstat, \irqstat, \tmp
+
+        @ find first active interrupt source
+1001:   clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h
new file mode 100644
index 000000000000..e695719771a5
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-kirkwood/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "kirkwood.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h
new file mode 100644
index 000000000000..0ef6e95f5d5b
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-kirkwood/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "kirkwood.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
+                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h
new file mode 100644
index 000000000000..2e7b5da6335c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/irqs.h
@@ -0,0 +1,63 @@
+/*
+ * include/asm-arm/arch-kirkwood/irqs.h
+ *
+ * IRQ definitions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "kirkwood.h"   /* need GPIO_MAX */
+
+/*
+ * Low Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_HIGH_SUM   0
+#define IRQ_KIRKWOOD_BRIDGE     1
+#define IRQ_KIRKWOOD_HOST2CPU   2
+#define IRQ_KIRKWOOD_CPU2HOST   3
+#define IRQ_KIRKWOOD_XOR_00     5
+#define IRQ_KIRKWOOD_XOR_01     6
+#define IRQ_KIRKWOOD_XOR_10     7
+#define IRQ_KIRKWOOD_XOR_11     8
+#define IRQ_KIRKWOOD_PCIE       9
+#define IRQ_KIRKWOOD_GE00_SUM   11
+#define IRQ_KIRKWOOD_GE01_SUM   15
+#define IRQ_KIRKWOOD_USB        19
+#define IRQ_KIRKWOOD_SATA       21
+#define IRQ_KIRKWOOD_CRYPTO     22
+#define IRQ_KIRKWOOD_SPI        23
+#define IRQ_KIRKWOOD_I2S        24
+#define IRQ_KIRKWOOD_TS_0       26
+#define IRQ_KIRKWOOD_SDIO       28
+#define IRQ_KIRKWOOD_TWSI       29
+#define IRQ_KIRKWOOD_AVB        30
+#define IRQ_KIRKWOOD_TDMI       31
+
+/*
+ * High Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_UART_0     33
+#define IRQ_KIRKWOOD_UART_1     34
+#define IRQ_KIRKWOOD_GPIO_LOW_0_7       35
+#define IRQ_KIRKWOOD_GPIO_LOW_8_15      36
+#define IRQ_KIRKWOOD_GPIO_LOW_16_23     37
+#define IRQ_KIRKWOOD_GPIO_LOW_24_31     38
+#define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
+#define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
+#define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
+
+/*
+ * KIRKWOOD General Purpose Pins
+ */
+#define IRQ_KIRKWOOD_GPIO_START 64
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
new file mode 100644
index 000000000000..bb31b315c350
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/kirkwood.h
@@ -0,0 +1,100 @@
+/*
+ * include/asm-arm/arch-kirkwood/kirkwood.h
+ *
+ * Generic definitions for Marvell Kirkwood SoC flavors:
+ *  88F6180, 88F6192 and 88F6281.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_KIRKWOOD_H
+#define __ASM_ARCH_KIRKWOOD_H
+
+/*
+ * Marvell Kirkwood address maps.
+ *
+ * phys
+ * e0000000     PCIe Memory space
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f3000000     NAND controller address window
+ *
+ * virt         phys            size
+ * fee00000     f1000000        1M      on-chip peripheral registers
+ * fef00000     f2000000        1M      PCIe I/O space
+ */
+
+#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
+#define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
+                                                * is the minimal window size
+                                                */
+
+#define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
+#define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
+#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
+
+#define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
+#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
+#define KIRKWOOD_REGS_SIZE              SZ_1M
+
+#define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
+#define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
+
+/*
+ * MBUS bridge registers.
+ */
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   CPU_RESET             0x00000002
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0000
+#define   IRQ_MASK_LOW_OFF      0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+#define  L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
+#define   L2_WRITETHROUGH       0x00000010
+
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
+
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
+
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+
+
+#define GPIO_MAX                50
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h
new file mode 100644
index 000000000000..e5108f408ce6
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-kirkwood/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h
new file mode 100644
index 000000000000..8dde7e379855
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-kirkwood/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/kirkwood.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h
new file mode 100644
index 000000000000..82122e134e3c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/timex.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/arch-kirkwood/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define KIRKWOOD_TCLK           166666667
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h
new file mode 100644
index 000000000000..a9062b6d7680
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-kirkwood/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/arch/kirkwood.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h
new file mode 100644
index 000000000000..41852c6e77f3
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-kirkwood/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S
new file mode 100644
index 000000000000..585502e96513
--- /dev/null
+++ b/include/asm-arm/arch-loki/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-loki/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/loki.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =LOKI_REGS_PHYS_BASE
+        ldrne   \rx, =LOKI_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-loki/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S
new file mode 100644
index 000000000000..693257cdbeb8
--- /dev/null
+++ b/include/asm-arm/arch-loki/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * include/asm-arm/arch-loki/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/loki.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #IRQ_CAUSE_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_OFF]
+        mov     \irqnr, #0
+        ands    \irqstat, \irqstat, \tmp
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h
new file mode 100644
index 000000000000..f65b01c733b6
--- /dev/null
+++ b/include/asm-arm/arch-loki/hardware.h
@@ -0,0 +1,15 @@
+/*
+ * include/asm-arm/arch-loki/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "loki.h"
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h
new file mode 100644
index 000000000000..e7418a915e75
--- /dev/null
+++ b/include/asm-arm/arch-loki/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-loki/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "loki.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+                                        + LOKI_PCIE0_IO_VIRT_BASE);
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h
new file mode 100644
index 000000000000..7e4971438072
--- /dev/null
+++ b/include/asm-arm/arch-loki/irqs.h
@@ -0,0 +1,58 @@
+/*
+ * include/asm-arm/arch-loki/irqs.h
+ *
+ * IRQ definitions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "loki.h"       /* need GPIO_MAX */
+
+/*
+ * Interrupt Controller
+ */
+#define IRQ_LOKI_PCIE_A_CPU_DRBL        0
+#define IRQ_LOKI_CPU_PCIE_A_DRBL        1
+#define IRQ_LOKI_PCIE_B_CPU_DRBL        2
+#define IRQ_LOKI_CPU_PCIE_B_DRBL        3
+#define IRQ_LOKI_COM_A_ERR              6
+#define IRQ_LOKI_COM_A_IN               7
+#define IRQ_LOKI_COM_A_OUT              8
+#define IRQ_LOKI_COM_B_ERR              9
+#define IRQ_LOKI_COM_B_IN               10
+#define IRQ_LOKI_COM_B_OUT              11
+#define IRQ_LOKI_DMA_A                  12
+#define IRQ_LOKI_DMA_B                  13
+#define IRQ_LOKI_SAS_A                  14
+#define IRQ_LOKI_SAS_B                  15
+#define IRQ_LOKI_DDR                    16
+#define IRQ_LOKI_XOR                    17
+#define IRQ_LOKI_BRIDGE                 18
+#define IRQ_LOKI_PCIE_A_ERR             20
+#define IRQ_LOKI_PCIE_A_INT             21
+#define IRQ_LOKI_PCIE_B_ERR             22
+#define IRQ_LOKI_PCIE_B_INT             23
+#define IRQ_LOKI_GBE_A_INT              24
+#define IRQ_LOKI_GBE_B_INT              25
+#define IRQ_LOKI_DEV_ERR                26
+#define IRQ_LOKI_UART0                  27
+#define IRQ_LOKI_UART1                  28
+#define IRQ_LOKI_TWSI                   29
+#define IRQ_LOKI_GPIO_23_0              30
+#define IRQ_LOKI_GPIO_25_24             31
+
+/*
+ * Loki General Purpose Pins
+ */
+#define IRQ_LOKI_GPIO_START     32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
new file mode 100644
index 000000000000..5dd05ee0a4e6
--- /dev/null
+++ b/include/asm-arm/arch-loki/loki.h
@@ -0,0 +1,97 @@
+/*
+ * include/asm-arm/arch-loki/loki.h
+ *
+ * Generic definitions for Marvell Loki (88RC8480) SoC flavors
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_LOKI_H
+#define __ASM_ARCH_LOKI_H
+
+/*
+ * Marvell Loki (88RC8480) address maps.
+ *
+ * phys
+ * d0000000     on-chip peripheral registers
+ * e0000000     PCIe 0 Memory space
+ * e8000000     PCIe 1 Memory space
+ * f0000000     PCIe 0 I/O space
+ * f0100000     PCIe 1 I/O space
+ *
+ * virt         phys            size
+ * fed00000     d0000000        1M      on-chip peripheral registers
+ * fee00000     f0000000        64K     PCIe 0 I/O space
+ * fef00000     f0100000        64K     PCIe 1 I/O space
+ */
+
+#define LOKI_REGS_PHYS_BASE             0xd0000000
+#define LOKI_REGS_VIRT_BASE             0xfed00000
+#define LOKI_REGS_SIZE                  SZ_1M
+
+#define LOKI_PCIE0_IO_PHYS_BASE         0xf0000000
+#define LOKI_PCIE0_IO_VIRT_BASE         0xfee00000
+#define LOKI_PCIE0_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE0_IO_SIZE              SZ_64K
+
+#define LOKI_PCIE1_IO_PHYS_BASE         0xf0100000
+#define LOKI_PCIE1_IO_VIRT_BASE         0xfef00000
+#define LOKI_PCIE1_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE1_IO_SIZE              SZ_64K
+
+#define LOKI_PCIE0_MEM_PHYS_BASE        0xe0000000
+#define LOKI_PCIE0_MEM_SIZE             SZ_128M
+
+#define LOKI_PCIE1_MEM_PHYS_BASE        0xe8000000
+#define LOKI_PCIE1_MEM_SIZE             SZ_128M
+
+/*
+ * Register Map
+ */
+#define DEV_BUS_PHYS_BASE       (LOKI_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x10000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+
+#define BRIDGE_VIRT_BASE        (LOKI_REGS_VIRT_BASE | 0x20000)
+#define  BRIDGE_REG(x)          (BRIDGE_VIRT_BASE | (x))
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR 0x0004
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_OFF         0x0000
+#define   IRQ_MASK_OFF          0x0004
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+
+#define PCIE0_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x30000)
+
+#define PCIE1_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x40000)
+
+#define SAS0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x80000)
+
+#define SAS1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x90000)
+
+#define GE0_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xa0000)
+#define GE0_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xa0000)
+
+#define GE1_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xb0000)
+#define GE1_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xb0000)
+
+#define DDR_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xf0000)
+#define DDR_REG(x)              (DDR_VIRT_BASE | (x))
+
+
+#define GPIO_MAX                8
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h
new file mode 100644
index 000000000000..835101e49875
--- /dev/null
+++ b/include/asm-arm/arch-loki/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-loki/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h
new file mode 100644
index 000000000000..a3568ac8ec35
--- /dev/null
+++ b/include/asm-arm/arch-loki/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-loki/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/loki.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h
new file mode 100644
index 000000000000..940014f97cae
--- /dev/null
+++ b/include/asm-arm/arch-loki/timex.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/arch-loki/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define LOKI_TCLK               180000000
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h
new file mode 100644
index 000000000000..89a0cf88d3a5
--- /dev/null
+++ b/include/asm-arm/arch-loki/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-loki/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/arch/loki.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h
new file mode 100644
index 000000000000..f5be06220491
--- /dev/null
+++ b/include/asm-arm/arch-loki/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-loki/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
index 565430cfaa7e..e62a108b1857 100644
--- a/include/asm-arm/arch-msm/irqs.h
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -15,6 +15,7 @@
  */
 
 #ifndef __ASM_ARCH_MSM_IRQS_H
+#define __ASM_ARCH_MSM_IRQS_H
 
 /* MSM ARM11 Interrupt Numbers */
 /* See 80-VE113-1 A, pp219-221     */
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
index 154b23fb3599..8724487ab4c9 100644
--- a/include/asm-arm/arch-msm/timex.h
+++ b/include/asm-arm/arch-msm/timex.h
@@ -14,6 +14,7 @@
  */
 
 #ifndef __ASM_ARCH_MSM_TIMEX_H
+#define __ASM_ARCH_MSM_TIMEX_H
 
 #define CLOCK_TICK_RATE         1000000
 
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
new file mode 100644
index 000000000000..d0595bd645e5
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-mv78xx0/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/mv78xx0.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
+        ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
new file mode 100644
index 000000000000..e9a606b12669
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-mv78xx0/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell MV78xx0 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/mv78xx0.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+
+        @ if no low interrupts set, check high interrupts
+        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        moveq   \irqnr, #63
+        andeqs  \irqstat, \irqstat, \tmp
+
+        @ find first active interrupt source
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
new file mode 100644
index 000000000000..8e17926086c6
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-mv78xx0/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "mv78xx0.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
new file mode 100644
index 000000000000..415d4c98e3d1
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-mv78xx0/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "mv78xx0.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
+                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
new file mode 100644
index 000000000000..75930450cd65
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * include/asm-arm/arch-mv78xx0/irqs.h
+ *
+ * IRQ definitions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "mv78xx0.h"    /* need GPIO_MAX */
+
+/*
+ * MV78xx0 Low Interrupt Controller
+ */
+#define IRQ_MV78XX0_ERR         0
+#define IRQ_MV78XX0_SPI         1
+#define IRQ_MV78XX0_I2C_0       2
+#define IRQ_MV78XX0_I2C_1       3
+#define IRQ_MV78XX0_IDMA_0      4
+#define IRQ_MV78XX0_IDMA_1      5
+#define IRQ_MV78XX0_IDMA_2      6
+#define IRQ_MV78XX0_IDMA_3      7
+#define IRQ_MV78XX0_TIMER_0     8
+#define IRQ_MV78XX0_TIMER_1     9
+#define IRQ_MV78XX0_TIMER_2     10
+#define IRQ_MV78XX0_TIMER_3     11
+#define IRQ_MV78XX0_UART_0      12
+#define IRQ_MV78XX0_UART_1      13
+#define IRQ_MV78XX0_UART_2      14
+#define IRQ_MV78XX0_UART_3      15
+#define IRQ_MV78XX0_USB_0       16
+#define IRQ_MV78XX0_USB_1       17
+#define IRQ_MV78XX0_USB_2       18
+#define IRQ_MV78XX0_CRYPTO      19
+#define IRQ_MV78XX0_SDIO_0      20
+#define IRQ_MV78XX0_SDIO_1      21
+#define IRQ_MV78XX0_XOR_0       22
+#define IRQ_MV78XX0_XOR_1       23
+#define IRQ_MV78XX0_I2S_0       24
+#define IRQ_MV78XX0_I2S_1       25
+#define IRQ_MV78XX0_SATA        26
+#define IRQ_MV78XX0_TDMI        27
+
+/*
+ * MV78xx0 High Interrupt Controller
+ */
+#define IRQ_MV78XX0_PCIE_00     32
+#define IRQ_MV78XX0_PCIE_01     33
+#define IRQ_MV78XX0_PCIE_02     34
+#define IRQ_MV78XX0_PCIE_03     35
+#define IRQ_MV78XX0_PCIE_10     36
+#define IRQ_MV78XX0_PCIE_11     37
+#define IRQ_MV78XX0_PCIE_12     38
+#define IRQ_MV78XX0_PCIE_13     39
+#define IRQ_MV78XX0_GE00_SUM    40
+#define IRQ_MV78XX0_GE00_RX     41
+#define IRQ_MV78XX0_GE00_TX     42
+#define IRQ_MV78XX0_GE00_MISC   43
+#define IRQ_MV78XX0_GE01_SUM    44
+#define IRQ_MV78XX0_GE01_RX     45
+#define IRQ_MV78XX0_GE01_TX     46
+#define IRQ_MV78XX0_GE01_MISC   47
+#define IRQ_MV78XX0_GE10_SUM    48
+#define IRQ_MV78XX0_GE10_RX     49
+#define IRQ_MV78XX0_GE10_TX     50
+#define IRQ_MV78XX0_GE10_MISC   51
+#define IRQ_MV78XX0_GE11_SUM    52
+#define IRQ_MV78XX0_GE11_RX     53
+#define IRQ_MV78XX0_GE11_TX     54
+#define IRQ_MV78XX0_GE11_MISC   55
+#define IRQ_MV78XX0_GPIO_0_7    56
+#define IRQ_MV78XX0_GPIO_8_15   57
+#define IRQ_MV78XX0_GPIO_16_23  58
+#define IRQ_MV78XX0_GPIO_24_31  59
+#define IRQ_MV78XX0_DB_IN       60
+#define IRQ_MV78XX0_DB_OUT      61
+
+/*
+ * MV78XX0 General Purpose Pins
+ */
+#define IRQ_MV78XX0_GPIO_START  64
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
new file mode 100644
index 000000000000..721a6b185b91
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-mv78xx0/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
new file mode 100644
index 000000000000..9f5d83c73faa
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/arch-mv78xx0/mv78xx0.h
+ *
+ * Generic definitions for Marvell MV78xx0 SoC flavors:
+ *  MV781x0 and MV782x0.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_MV78XX0_H
+#define __ASM_ARCH_MV78XX0_H
+
+/*
+ * Marvell MV78xx0 address maps.
+ *
+ * phys
+ * c0000000     PCIe Memory space
+ * f0800000     PCIe #0 I/O space
+ * f0900000     PCIe #1 I/O space
+ * f0a00000     PCIe #2 I/O space
+ * f0b00000     PCIe #3 I/O space
+ * f0c00000     PCIe #4 I/O space
+ * f0d00000     PCIe #5 I/O space
+ * f0e00000     PCIe #6 I/O space
+ * f0f00000     PCIe #7 I/O space
+ * f1000000     on-chip peripheral registers
+ *
+ * virt         phys            size
+ * fe400000     f102x000        16K     core-specific peripheral registers
+ * fe700000     f0800000        1M      PCIe #0 I/O space
+ * fe800000     f0900000        1M      PCIe #1 I/O space
+ * fe900000     f0a00000        1M      PCIe #2 I/O space
+ * fea00000     f0b00000        1M      PCIe #3 I/O space
+ * feb00000     f0c00000        1M      PCIe #4 I/O space
+ * fec00000     f0d00000        1M      PCIe #5 I/O space
+ * fed00000     f0e00000        1M      PCIe #6 I/O space
+ * fee00000     f0f00000        1M      PCIe #7 I/O space
+ * fef00000     f1000000        1M      on-chip peripheral registers
+ */
+#define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
+#define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
+#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_SIZE          SZ_16K
+
+#define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_SIZE            SZ_1M
+
+#define MV78XX0_REGS_PHYS_BASE          0xf1000000
+#define MV78XX0_REGS_VIRT_BASE          0xfef00000
+#define MV78XX0_REGS_SIZE               SZ_1M
+
+#define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
+#define MV78XX0_PCIE_MEM_SIZE           0x30000000
+
+/*
+ * Core-specific peripheral registers.
+ */
+#define BRIDGE_VIRT_BASE        (MV78XX0_CORE_REGS_VIRT_BASE)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   L2_WRITETHROUGH       0x00020000
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0008
+#define   IRQ_MASK_LOW_OFF      0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
+
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
+
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
+
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
+
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
+
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
+
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+
+
+#define GPIO_MAX                32
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
new file mode 100644
index 000000000000..7eb47d376db9
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-mv78xx0/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/mv78xx0.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
new file mode 100644
index 000000000000..a854b1ccbd01
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/timex.h
@@ -0,0 +1,9 @@
+/*
+ * include/asm-arm/arch-mv78xx0/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
new file mode 100644
index 000000000000..3bfe0a293ef7
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-mv78xx0/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/arch/mv78xx0.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
new file mode 100644
index 000000000000..f2c512197579
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-mv78xx0/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx27ads.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+
+/* external interrupt multiplexer */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
+
+#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
+
+#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+
+/*
+ * MXC UART EVB board level configurations
+ */
+
+#define MXC_LL_EXTUART_PADDR    (CS4_BASE_ADDR + 0x20000)
+#define MXC_LL_EXTUART_VADDR    (CS4_BASE_ADDR_VIRT + 0x20000)
+#define MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*
+ * @name Memory Size parameters
+ */
+
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+
+/*
+ * PBC Controller parameters
+ */
+
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xEB000000
+#define PBC_REG_ADDR(offset)    (PBC_BASE_ADDRESS + (offset))
+
+/*
+ * PBC Interupt name definitions
+ */
+#define PBC_GPIO1_0  0
+#define PBC_GPIO1_1  1
+#define PBC_GPIO1_2  2
+#define PBC_GPIO1_3  3
+#define PBC_GPIO1_4  4
+#define PBC_GPIO1_5  5
+
+#define PBC_INTR_MAX_NUM 6
+#define PBC_INTR_SHARED_MAX_NUM 8
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
+/*PBC_ADDR_SH
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
+/*
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Status.
+ */
+#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Set.
+ */
+#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Clear.
+ */
+#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
+
+/* PBC Board Version Register bit definition */
+#define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
+#define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
+#define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
+#define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
+#define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
+#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
+
+/* PBC Board Control Register 2 bit definitions */
+#define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
+#define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
+#define PBC_BCTRL2_ATAFEC_EN    0X0010
+#define PBC_BCTRL2_ATAFEC_SEL   0X0020
+#define PBC_BCTRL2_ATA_EN       0X0040
+#define PBC_BCTRL2_IRDA_SD      0X0080
+#define PBC_BCTRL2_IRDA_EN      0X0100
+#define PBC_BCTRL2_CCTL10       0X0200
+#define PBC_BCTRL2_CCTL11       0X0400
+
+/* PBC Board Control Register 3 bit definitions */
+#define PBC_BCTRL3_HSH_EN       0X0020
+#define PBC_BCTRL3_FSH_MOD      0X0040
+#define PBC_BCTRL3_OTG_HS_EN    0X0080
+#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
+#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
+#define PBC_BCTRL3_USB_OTG_ON   0X0800
+#define PBC_BCTRL3_USB_FSH_ON   0X1000
+
+/* PBC Board Control Register 4 bit definitions */
+#define PBC_BCTRL4_REGEN_SEL    0X0001
+#define PBC_BCTRL4_USER_OFF     0X0002
+#define PBC_BCTRL4_VIB_EN       0X0004
+#define PBC_BCTRL4_PWRGT1_EN    0X0008
+#define PBC_BCTRL4_PWRGT2_EN    0X0010
+#define PBC_BCTRL4_STDBY_PRI    0X0020
+
+#ifndef __ASSEMBLY__
+/*
+ * Enumerations for SD cards and memory stick card. This corresponds to
+ * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
+ */
+enum mxc_card_no {
+        MXC_CARD_SD2 = 0,
+        MXC_CARD_SD3,
+        MXC_CARD_MS,
+        MXC_CARD_SD1,
+        MXC_CARD_MIN = MXC_CARD_SD2,
+        MXC_CARD_MAX = MXC_CARD_SD1,
+};
+#endif
+
+#define MXC_CPLD_VER_1_50       0x01
+
+/*
+ * PBC BSTAT Register bit definitions
+ */
+#define PBC_BSTAT_PRI_INT       0X0001
+#define PBC_BSTAT_USB_BYP       0X0002
+#define PBC_BSTAT_ATA_IOCS16    0X0004
+#define PBC_BSTAT_ATA_CBLID     0X0008
+#define PBC_BSTAT_ATA_DASP      0X0010
+#define PBC_BSTAT_PWR_RDY       0X0020
+#define PBC_BSTAT_SD3_WP        0X0100
+#define PBC_BSTAT_SD2_WP        0X0200
+#define PBC_BSTAT_SD1_WP        0X0400
+#define PBC_BSTAT_SD3_DET       0X0800
+#define PBC_BSTAT_SD2_DET       0X1000
+#define PBC_BSTAT_SD1_DET       0X2000
+#define PBC_BSTAT_MS_DET        0X4000
+#define PBC_BSTAT_SD3_DET_BIT   11
+#define PBC_BSTAT_SD2_DET_BIT   12
+#define PBC_BSTAT_SD1_DET_BIT   13
+#define PBC_BSTAT_MS_DET_BIT    14
+#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
+                                 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
+                                 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
+                                 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
+                                        0x0))))
+
+/*
+ * PBC UART Control Register bit definitions
+ */
+#define PBC_UCTRL_DCE_DCD       0X0001
+#define PBC_UCTRL_DCE_DSR       0X0002
+#define PBC_UCTRL_DCE_RI        0X0004
+#define PBC_UCTRL_DTE_DTR       0X0100
+
+/*
+ * PBC UART Status Register bit definitions
+ */
+#define PBC_USTAT_DTE_DCD       0X0001
+#define PBC_USTAT_DTE_DSR       0X0002
+#define PBC_USTAT_DTE_RI        0X0004
+#define PBC_USTAT_DCE_DTR       0X0100
+
+/*
+ * PBC Interupt mask register bit definitions
+ */
+#define PBC_INTR_SD3_R_EN_BIT   4
+#define PBC_INTR_SD2_R_EN_BIT   0
+#define PBC_INTR_SD1_R_EN_BIT   6
+#define PBC_INTR_MS_R_EN_BIT    5
+#define PBC_INTR_SD3_EN_BIT     13
+#define PBC_INTR_SD2_EN_BIT     12
+#define PBC_INTR_MS_EN_BIT      14
+#define PBC_INTR_SD1_EN_BIT     15
+
+#define PBC_INTR_SD2_R_EN       0x0001
+#define PBC_INTR_LOW_BAT        0X0002
+#define PBC_INTR_OTG_FSOVER     0X0004
+#define PBC_INTR_FSH_OVER       0X0008
+#define PBC_INTR_SD3_R_EN       0x0010
+#define PBC_INTR_MS_R_EN        0x0020
+#define PBC_INTR_SD1_R_EN       0x0040
+#define PBC_INTR_FEC_INT        0X0080
+#define PBC_INTR_ENET_INT       0X0100
+#define PBC_INTR_OTGFS_INT      0X0200
+#define PBC_INTR_XUART_INT      0X0400
+#define PBC_INTR_CCTL12         0X0800
+#define PBC_INTR_SD2_EN         0x1000
+#define PBC_INTR_SD3_EN         0x2000
+#define PBC_INTR_MS_EN          0x4000
+#define PBC_INTR_SD1_EN         0x8000
+
+
+
+/* For interrupts like xuart, enet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
+#define MXC_MAX_EXP_IO_LINES    16
+
+/*
+ * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
+ *
+ */
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
+
+/*
+ * This is System IRQ used by CS8900A for interrupt generation
+ * taken from platform.h
+ */
+#define CS8900AIRQ              EXPIO_INT_ENET_INT
+/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
+
+#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
+
+/*
+* This is used to detect if the CPLD version is for mx27 evb board rev-a
+*/
+#define PBC_CPLD_VERSION_IS_REVA() \
+        ((__raw_readw(PBC_VERSION_REG) & \
+        (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
+        == 0)
+
+/* This is used to active or inactive ata signal in CPLD .
+ *  It is dependent with hardware
+ */
+#define PBC_ATA_SIGNAL_ACTIVE() \
+        __raw_writew(           \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_CLEAR_REG)
+
+#define PBC_ATA_SIGNAL_INACTIVE() \
+        __raw_writew(  \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_SET_REG)
+
+#define MXC_BD_LED1             (1 << 5)
+#define MXC_BD_LED2             (1 << 6)
+#define MXC_BD_LED_ON(led) \
+        __raw_writew(led, PBC_BCTRL1_SET_REG)
+#define MXC_BD_LED_OFF(led) \
+        __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index 8590127760a8..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -109,4 +109,9 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31lite.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+
+/*
+ * Memory Size parameters
+ */
+
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+/*
+ * Size of MBX buffer memory
+ */
+#define MXC_MBX_MEM_SIZE        SZ_16M
+/*
+ * Size of memory available to kernel
+ */
+#define MEM_SIZE                (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm037.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
+#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm038.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
+#define __ASM_ARCH_MXC_BOARD_PCM038_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside pcm038_init().
+ *
+ * This example here is for the development board. Refer pcm970-baseboard.c
+ */
+
+extern void pcm970_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/clock.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_CLOCK_H__
+#define __ASM_ARCH_MXC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+
+struct module;
+
+struct clk {
+        struct list_head node;
+        struct module *owner;
+        const char *name;
+        int id;
+        /* Source clock this clk depends on */
+        struct clk *parent;
+        /* Secondary clock to enable/disable with this clock */
+        struct clk *secondary;
+        /* Reference count of clock enable/disable */
+        __s8 usecount;
+        /* Register bit position for clock's enable/disable control. */
+        u8 enable_shift;
+        /* Register address for clock's enable/disable control. */
+        u32 enable_reg;
+        u32 flags;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 23b4350edbd6..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,10 +11,10 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
-struct sys_timer;
-
 extern void mxc_map_io(void);
 extern void mxc_init_irq(void);
-extern struct sys_timer mxc_timer;
+extern void mxc_timer_init(const char *clk_timer);
+extern int mxc_clocks_init(unsigned long fref);
+extern int mxc_register_gpios(void);
 
 #endif
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
new file mode 100644
index 000000000000..575087f8561a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/debug-macro.S
@@ -0,0 +1,49 @@
+/* linux/include/asm-arm/arch-imx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_MACH_MX31ADS
+#include <asm/arch/board-mx31ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM037
+#include <asm/arch/board-pcm037.h>
+#endif
+#ifdef CONFIG_MACH_MX31LITE
+#include <asm/arch/board-mx31lite.h>
+#endif
+#ifdef CONFIG_MACH_MX27ADS
+#include <asm/arch/board-mx27ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM038
+#include <asm/arch/board-pcm038.h>
+#endif
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
+                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
new file mode 100644
index 000000000000..d393e15f5a6b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_GPIO_H__
+#define __ASM_ARCH_MXC_GPIO_H__
+
+#include <asm/hardware.h>
+#include <asm-generic/gpio.h>
+
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+
+#define gpio_to_irq(gpio)       (MXC_MAX_INT_LINES + (gpio))
+#define irq_to_gpio(irq)        ((irq) - MXC_MAX_INT_LINES)
+
+struct mxc_gpio_port {
+        void __iomem *base;
+        int irq;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+
+int mxc_gpio_init(struct mxc_gpio_port*, int);
+
+#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index e87ff0679d5e..37cddbaaade7 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -1,11 +1,20 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
  */
 
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
 # include <asm/arch/mx31.h>
 #endif
 
-#include <asm/arch/mxc.h>
-
-/*
- * ---------------------------------------------------------------------------
- * Board specific defines
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_MACH_MX31ADS
-# include <asm/arch/board-mx31ads.h>
+#ifdef CONFIG_ARCH_MX2
+# ifdef CONFIG_MACH_MX27
+#  include <asm/arch/mx27.h>
+# endif
 #endif
 
+#include <asm/arch/mxc.h>
+
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iim.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_IIM_H__
+#define __ASM_ARCH_MXC_IIM_H__
+
+/* Register offsets */
+#define MXC_IIMSTAT             0x0000
+#define MXC_IIMSTATM            0x0004
+#define MXC_IIMERR              0x0008
+#define MXC_IIMEMASK            0x000C
+#define MXC_IIMFCTL             0x0010
+#define MXC_IIMUA               0x0014
+#define MXC_IIMLA               0x0018
+#define MXC_IIMSDAT             0x001C
+#define MXC_IIMPREV             0x0020
+#define MXC_IIMSREV             0x0024
+#define MXC_IIMPRG_P            0x0028
+#define MXC_IIMSCS0             0x002C
+#define MXC_IIMSCS1             0x0030
+#define MXC_IIMSCS2             0x0034
+#define MXC_IIMSCS3             0x0038
+#define MXC_IIMFBAC0            0x0800
+#define MXC_IIMJAC              0x0804
+#define MXC_IIMHWV1             0x0808
+#define MXC_IIMHWV2             0x080C
+#define MXC_IIMHAB0             0x0810
+#define MXC_IIMHAB1             0x0814
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMMAC              0x0814
+#define MXC_IIMPREV_FUSE        0x0818
+#define MXC_IIMSREV_FUSE        0x081C
+#define MXC_IIMSJC_CHALL_0      0x0820
+#define MXC_IIMSJC_CHALL_7      0x083C
+#define MXC_IIMFB0UC17          0x0840
+#define MXC_IIMFB0UC255         0x0BFC
+#define MXC_IIMFBAC1            0x0C00
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMSUID             0x0C04
+#define MXC_IIMKEY0             0x0C04
+#define MXC_IIMKEY20            0x0C54
+#define MXC_IIMSJC_RESP_0       0x0C58
+#define MXC_IIMSJC_RESP_7       0x0C74
+#define MXC_IIMFB1UC30          0x0C78
+#define MXC_IIMFB1UC255         0x0FFC
+
+/* Bit definitions */
+
+#define MXC_IIMHWV1_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
+#define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
+#define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
+#define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
+#define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
+#define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
+
+#define MXC_IIMHWV2_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
+#define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
+
+#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/imx-uart.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef ASMARM_ARCH_UART_H
+#define ASMARM_ARCH_UART_H
+
+#define IMXUART_HAVE_RTSCTS (1<<0)
+
+struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        int (*exit)(struct platform_device *pdev);
+        unsigned int flags;
+};
+
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
+
+#endif
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef _MXC_GPIO_MX1_MX2_H
+#define _MXC_GPIO_MX1_MX2_H
+
+#include <linux/io.h>
+
+#define MXC_GPIO_ALLOC_MODE_NORMAL      0
+#define MXC_GPIO_ALLOC_MODE_NO_ALLOC    1
+#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC   2
+#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY  4
+#define MXC_GPIO_ALLOC_MODE_RELEASE     8
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define VA_GPIO_BASE    IO_ADDRESS(GPIO_BASE_ADDR)
+#define MXC_DDIR(x)    (0x00 + ((x) << 8))
+#define MXC_OCR1(x)    (0x04 + ((x) << 8))
+#define MXC_OCR2(x)    (0x08 + ((x) << 8))
+#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
+#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
+#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
+#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
+#define MXC_DR(x)      (0x1c + ((x) << 8))
+#define MXC_GIUS(x)    (0x20 + ((x) << 8))
+#define MXC_SSR(x)     (0x24 + ((x) << 8))
+#define MXC_ICR1(x)    (0x28 + ((x) << 8))
+#define MXC_ICR2(x)    (0x2c + ((x) << 8))
+#define MXC_IMR(x)     (0x30 + ((x) << 8))
+#define MXC_ISR(x)     (0x34 + ((x) << 8))
+#define MXC_GPR(x)     (0x38 + ((x) << 8))
+#define MXC_SWR(x)     (0x3c + ((x) << 8))
+#define MXC_PUEN(x)    (0x40 + ((x) << 8))
+
+#ifdef CONFIG_ARCH_MX1
+# define GPIO_PORT_MAX  3
+#endif
+#ifdef CONFIG_ARCH_MX2
+# define GPIO_PORT_MAX  5
+#endif
+
+#ifndef GPIO_PORT_MAX
+# error "GPIO config port count unknown!"
+#endif
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT   (1 << 8)
+#define GPIO_IN    (0 << 8)
+#define GPIO_PUEN  (1 << 9)
+
+#define GPIO_PF    (1 << 10)
+#define GPIO_AF    (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
+
+extern void mxc_gpio_mode(int gpio_mode);
+extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                        int alloc_mode, const char *label);
+
+/*-------------------------------------------------------------------------*/
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#ifdef CONFIG_ARCH_MX1
+#define PA0_AIN_SPI2_CLK     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
+#define PA0_AF_ETMTRACESYNC  (GPIO_PORTA | GPIO_AF | 0)
+#define PA1_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
+#define PA1_PF_TIN           (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_PWM0          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
+#define PA3_PF_CSI_MCLK      (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_CSI_D0        (GPIO_PORTA | GPIO_PF | 4)
+#define PA5_PF_CSI_D1        (GPIO_PORTA | GPIO_PF | 5)
+#define PA6_PF_CSI_D2        (GPIO_PORTA | GPIO_PF | 6)
+#define PA7_PF_CSI_D3        (GPIO_PORTA | GPIO_PF | 7)
+#define PA8_PF_CSI_D4        (GPIO_PORTA | GPIO_PF | 8)
+#define PA9_PF_CSI_D5        (GPIO_PORTA | GPIO_PF | 9)
+#define PA10_PF_CSI_D6       (GPIO_PORTA | GPIO_PF | 10)
+#define PA11_PF_CSI_D7       (GPIO_PORTA | GPIO_PF | 11)
+#define PA12_PF_CSI_VSYNC    (GPIO_PORTA | GPIO_PF | 12)
+#define PA13_PF_CSI_HSYNC    (GPIO_PORTA | GPIO_PF | 13)
+#define PA14_PF_CSI_PIXCLK   (GPIO_PORTA | GPIO_PF | 14)
+#define PA15_PF_I2C_SDA      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_I2C_SCL      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
+#define PA17_AIN_SPI2_SS     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
+#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
+#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
+#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
+#define PA21_PF_A0           (GPIO_PORTA | GPIO_PF | 21)
+#define PA22_PF_CS4          (GPIO_PORTA | GPIO_PF | 22)
+#define PA23_PF_CS5          (GPIO_PORTA | GPIO_PF | 23)
+#define PA24_PF_A16          (GPIO_PORTA | GPIO_PF | 24)
+#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
+#define PA25_PF_A17          (GPIO_PORTA | GPIO_PF | 25)
+#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
+#define PA26_PF_A18          (GPIO_PORTA | GPIO_PF | 26)
+#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
+#define PA27_PF_A19          (GPIO_PORTA | GPIO_PF | 27)
+#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
+#define PA28_PF_A20          (GPIO_PORTA | GPIO_PF | 28)
+#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
+#define PA29_PF_A21          (GPIO_PORTA | GPIO_PF | 29)
+#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
+#define PA30_PF_A22          (GPIO_PORTA | GPIO_PF | 30)
+#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
+#define PA31_PF_A23          (GPIO_PORTA | GPIO_PF | 31)
+#define PA31_AF_ETMTRACECLK  (GPIO_PORTA | GPIO_AF | 31)
+#define PB8_PF_SD_DAT0       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
+#define PB8_AF_MS_PIO        (GPIO_PORTB | GPIO_AF | 8)
+#define PB9_PF_SD_DAT1       (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9)
+#define PB9_AF_MS_PI1        (GPIO_PORTB | GPIO_AF | 9)
+#define PB10_PF_SD_DAT2      (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10)
+#define PB10_AF_MS_SCLKI     (GPIO_PORTB | GPIO_AF | 10)
+#define PB11_PF_SD_DAT3      (GPIO_PORTB | GPIO_PF | 11)
+#define PB11_AF_MS_SDIO      (GPIO_PORTB | GPIO_AF | 11)
+#define PB12_PF_SD_CLK       (GPIO_PORTB | GPIO_PF | 12)
+#define PB12_AF_MS_SCLK0     (GPIO_PORTB | GPIO_AF | 12)
+#define PB13_PF_SD_CMD       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
+#define PB13_AF_MS_BS        (GPIO_PORTB | GPIO_AF | 13)
+#define PB14_AF_SSI_RXFS     (GPIO_PORTB | GPIO_AF | 14)
+#define PB15_AF_SSI_RXCLK    (GPIO_PORTB | GPIO_AF | 15)
+#define PB16_AF_SSI_RXDAT    (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
+#define PB17_AF_SSI_TXDAT    (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
+#define PB18_AF_SSI_TXFS     (GPIO_PORTB | GPIO_AF | 18)
+#define PB19_AF_SSI_TXCLK    (GPIO_PORTB | GPIO_AF | 19)
+#define PB20_PF_USBD_AFE     (GPIO_PORTB | GPIO_PF | 20)
+#define PB21_PF_USBD_OE      (GPIO_PORTB | GPIO_PF | 21)
+#define PB22_PFUSBD_RCV      (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USBD_SUSPND  (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USBD_VP      (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBD_VM      (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBD_VPO     (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBD_VMO     (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_UART2_CTS    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
+#define PB29_PF_UART2_RTS    (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
+#define PB30_PF_UART2_TXD    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
+#define PB31_PF_UART2_RXD    (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
+#define PC3_PF_SSI_RXFS      (GPIO_PORTC | GPIO_PF | 3)
+#define PC4_PF_SSI_RXCLK     (GPIO_PORTC | GPIO_PF | 4)
+#define PC5_PF_SSI_RXDAT     (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
+#define PC6_PF_SSI_TXDAT     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_SSI_TXFS      (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_SSI_TXCLK     (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_UART1_CTS     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_UART1_RTS    (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
+#define PC11_PF_UART1_TXD    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_UART1_RXD    (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
+#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
+#define PC14_PF_SPI1_SCLK    (GPIO_PORTC | GPIO_PF | 14)
+#define PC15_PF_SPI1_SS      (GPIO_PORTC | GPIO_PF | 15)
+#define PC16_PF_SPI1_MISO    (GPIO_PORTC | GPIO_PF | 16)
+#define PC17_PF_SPI1_MOSI    (GPIO_PORTC | GPIO_PF | 17)
+#define PC24_BIN_UART3_RI    (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
+#define PC25_BIN_UART3_DSR   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
+#define PC26_AOUT_UART3_DTR  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
+#define PC27_BIN_UART3_DCD   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
+#define PC28_BIN_UART3_CTS   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
+#define PC29_AOUT_UART3_RTS  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
+#define PC30_BIN_UART3_TX    (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
+#define PC31_AOUT_UART3_RX   (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
+#define PD6_PF_LSCLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
+#define PD7_PF_REV           (GPIO_PORTD | GPIO_PF | 7)
+#define PD7_AF_UART2_DTR     (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
+#define PD7_AIN_SPI2_SCLK    (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
+#define PD8_PF_CLS           (GPIO_PORTD | GPIO_PF | 8)
+#define PD8_AF_UART2_DCD     (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
+#define PD8_AIN_SPI2_SS      (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
+#define PD9_PF_PS            (GPIO_PORTD | GPIO_PF | 9)
+#define PD9_AF_UART2_RI      (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
+#define PD9_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
+#define PD10_PF_SPL_SPR      (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
+#define PD10_AF_UART2_DSR    (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
+#define PD10_AIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
+#define PD11_PF_CONTRAST     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
+#define PD12_PF_ACD_OE       (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
+#define PD13_PF_LP_HSYNC     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
+#define PD14_PF_FLM_VSYNC    (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
+#define PD15_PF_LD0          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
+#define PD16_PF_LD1          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
+#define PD17_PF_LD2          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_LD3          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD19_PF_LD4          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
+#define PD20_PF_LD5          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
+#define PD21_PF_LD6          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
+#define PD22_PF_LD7          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
+#define PD23_PF_LD8          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
+#define PD24_PF_LD9          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
+#define PD25_PF_LD10         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
+#define PD26_PF_LD11         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
+#define PD27_PF_LD12         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
+#define PD28_PF_LD13         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
+#define PD29_PF_LD14         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
+#define PD30_PF_LD15         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
+#define PD31_PF_TMR2OUT      (GPIO_PORTD | GPIO_PF | 31)
+#define PD31_BIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
+#define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
+#define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
+#define PA8_PF_LD2              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
+#define PA9_PF_LD3              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
+#define PA10_PF_LD4             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
+#define PA11_PF_LD5             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
+#define PA12_PF_LD6             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
+#define PA13_PF_LD7             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
+#define PA14_PF_LD8             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
+#define PA15_PF_LD9             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_LD10            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_PF_LD11            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
+#define PA18_PF_LD12            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
+#define PA19_PF_LD13            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
+#define PA20_PF_LD14            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
+#define PA21_PF_LD15            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
+#define PA22_PF_LD16            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
+#define PA23_PF_LD17            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
+#define PA24_PF_REV             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
+#define PA25_PF_CLS             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
+#define PA26_PF_PS              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
+#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
+#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
+#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
+#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
+#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
+#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
+#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
+#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
+#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 11)
+#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
+#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
+#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
+#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 13)
+#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
+#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
+#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
+#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
+#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
+#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
+#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
+#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 19)
+#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
+#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
+#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
+#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
+#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
+#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
+#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
+#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 31)
+#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 5)
+#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 6)
+#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 16)
+#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 17)
+#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 18)
+#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 19)
+#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 20)
+#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 21)
+#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 22)
+#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 23)
+#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 24)
+#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 25)
+#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 26)
+#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 27)
+#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 28)
+#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 29)
+#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 30)
+#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 31)
+#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
+#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
+#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
+#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
+#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
+#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_IN | GPIO_PF  | 30)
+#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 31)
+#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
+#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
+#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
+#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
+#endif
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
+
+#define IRQ_GPIOA(x)  (MXC_MAX_INT_LINES + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+
+#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx3.h
@@ -0,0 +1,501 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MX31_IOMUX_H__
+#define __MACH_MX31_IOMUX_H__
+
+#include <linux/types.h>
+
+/*
+ * various IOMUX output functions
+ */
+
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+        PAD_CTL_NOLOOPBACK      = 0x0 << 9,
+        PAD_CTL_LOOPBACK        = 0x1 << 9,
+        PAD_CTL_PKE_NONE        = 0x0 << 8,
+        PAD_CTL_PKE_ENABLE      = 0x1 << 8,
+        PAD_CTL_PUE_KEEPER      = 0x0 << 7,
+        PAD_CTL_PUE_PUD         = 0x1 << 7,
+        PAD_CTL_100K_PD         = 0x0 << 5,
+        PAD_CTL_100K_PU         = 0x1 << 5,
+        PAD_CTL_47K_PU          = 0x2 << 5,
+        PAD_CTL_22K_PU          = 0x3 << 5,
+        PAD_CTL_HYS_CMOS        = 0x0 << 4,
+        PAD_CTL_HYS_SCHMITZ     = 0x1 << 4,
+        PAD_CTL_ODE_CMOS        = 0x0 << 3,
+        PAD_CTL_ODE_OpenDrain   = 0x1 << 3,
+        PAD_CTL_DRV_NORMAL      = 0x0 << 1,
+        PAD_CTL_DRV_HIGH        = 0x1 << 1,
+        PAD_CTL_DRV_MAX         = 0x2 << 1,
+        PAD_CTL_SRE_SLOW        = 0x0 << 0,
+        PAD_CTL_SRE_FAST        = 0x1 << 0
+};
+
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+        MUX_PGP_FIRI                    = 1 << 0,
+        MUX_DDR_MODE                    = 1 << 1,
+        MUX_PGP_CSPI_BB                 = 1 << 2,
+        MUX_PGP_ATA_1                   = 1 << 3,
+        MUX_PGP_ATA_2                   = 1 << 4,
+        MUX_PGP_ATA_3                   = 1 << 5,
+        MUX_PGP_ATA_4                   = 1 << 6,
+        MUX_PGP_ATA_5                   = 1 << 7,
+        MUX_PGP_ATA_6                   = 1 << 8,
+        MUX_PGP_ATA_7                   = 1 << 9,
+        MUX_PGP_ATA_8                   = 1 << 10,
+        MUX_PGP_UH2                     = 1 << 11,
+        MUX_SDCTL_CSD0_SEL              = 1 << 12,
+        MUX_SDCTL_CSD1_SEL              = 1 << 13,
+        MUX_CSPI1_UART3                 = 1 << 14,
+        MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
+        MUX_TAMPER_DETECT_EN            = 1 << 16,
+        MUX_PGP_USB_4WIRE               = 1 << 17,
+        MUX_PGB_USB_COMMON              = 1 << 18,
+        MUX_SDHC_MEMSTICK1              = 1 << 19,
+        MUX_SDHC_MEMSTICK2              = 1 << 20,
+        MUX_PGP_SPLL_BYP                = 1 << 21,
+        MUX_PGP_UPLL_BYP                = 1 << 22,
+        MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
+        MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
+        MUX_CSPI3_UART5_SEL             = 1 << 25,
+        MUX_PGP_ATA_9                   = 1 << 26,
+        MUX_PGP_USB_SUSPEND             = 1 << 27,
+        MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
+        MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
+        MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
+        MUX_CLKO_DDR_MODE               = 1 << 31,
+};
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void iomux_config_gpr(enum iomux_gp_func , bool);
+
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
+
+#define IOMUX_PADNUM_MASK       0x1ff
+#define IOMUX_GPIONUM_SHIFT     9
+#define IOMUX_GPIONUM_MASK      (0xff << IOMUX_GPIONUM_SHIFT)
+#define IOMUX_MODE_SHIFT        17
+#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
+
+#define IOMUX_PIN(gpionum, padnum) \
+        (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
+         (padnum & IOMUX_PADNUM_MASK))
+
+#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
+
+#define IOMUX_TO_GPIO(iomux_pin) \
+        ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
+#define IOMUX_TO_IRQ(iomux_pin) \
+        (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
+        MXC_GPIO_INT_BASE)
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+
+enum iomux_pins {
+        MX31_PIN_TTM_PAD        = IOMUX_PIN(0xff,   0),
+        MX31_PIN_CSPI3_SPI_RDY  = IOMUX_PIN(0xff,   1),
+        MX31_PIN_CSPI3_SCLK     = IOMUX_PIN(0xff,   2),
+        MX31_PIN_CSPI3_MISO     = IOMUX_PIN(0xff,   3),
+        MX31_PIN_CSPI3_MOSI     = IOMUX_PIN(0xff,   4),
+        MX31_PIN_CLKSS          = IOMUX_PIN(0xff,   5),
+        MX31_PIN_CE_CONTROL     = IOMUX_PIN(0xff,   6),
+        MX31_PIN_ATA_RESET_B    = IOMUX_PIN(95,     7),
+        MX31_PIN_ATA_DMACK      = IOMUX_PIN(94,     8),
+        MX31_PIN_ATA_DIOW       = IOMUX_PIN(93,     9),
+        MX31_PIN_ATA_DIOR       = IOMUX_PIN(92,    10),
+        MX31_PIN_ATA_CS1        = IOMUX_PIN(91,    11),
+        MX31_PIN_ATA_CS0        = IOMUX_PIN(90,    12),
+        MX31_PIN_SD1_DATA3      = IOMUX_PIN(63,    13),
+        MX31_PIN_SD1_DATA2      = IOMUX_PIN(62,    14),
+        MX31_PIN_SD1_DATA1      = IOMUX_PIN(61,    15),
+        MX31_PIN_SD1_DATA0      = IOMUX_PIN(60,    16),
+        MX31_PIN_SD1_CLK        = IOMUX_PIN(59,    17),
+        MX31_PIN_SD1_CMD        = IOMUX_PIN(58,    18),
+        MX31_PIN_D3_SPL         = IOMUX_PIN(0xff,  19),
+        MX31_PIN_D3_CLS         = IOMUX_PIN(0xff,  20),
+        MX31_PIN_D3_REV         = IOMUX_PIN(0xff,  21),
+        MX31_PIN_CONTRAST       = IOMUX_PIN(0xff,  22),
+        MX31_PIN_VSYNC3         = IOMUX_PIN(0xff,  23),
+        MX31_PIN_READ           = IOMUX_PIN(0xff,  24),
+        MX31_PIN_WRITE          = IOMUX_PIN(0xff,  25),
+        MX31_PIN_PAR_RS         = IOMUX_PIN(0xff,  26),
+        MX31_PIN_SER_RS         = IOMUX_PIN(89,    27),
+        MX31_PIN_LCS1           = IOMUX_PIN(88,    28),
+        MX31_PIN_LCS0           = IOMUX_PIN(87,    29),
+        MX31_PIN_SD_D_CLK       = IOMUX_PIN(86,    30),
+        MX31_PIN_SD_D_IO        = IOMUX_PIN(85,    31),
+        MX31_PIN_SD_D_I         = IOMUX_PIN(84,    32),
+        MX31_PIN_DRDY0          = IOMUX_PIN(0xff,  33),
+        MX31_PIN_FPSHIFT        = IOMUX_PIN(0xff,  34),
+        MX31_PIN_HSYNC          = IOMUX_PIN(0xff,  35),
+        MX31_PIN_VSYNC0         = IOMUX_PIN(0xff,  36),
+        MX31_PIN_LD17           = IOMUX_PIN(0xff,  37),
+        MX31_PIN_LD16           = IOMUX_PIN(0xff,  38),
+        MX31_PIN_LD15           = IOMUX_PIN(0xff,  39),
+        MX31_PIN_LD14           = IOMUX_PIN(0xff,  40),
+        MX31_PIN_LD13           = IOMUX_PIN(0xff,  41),
+        MX31_PIN_LD12           = IOMUX_PIN(0xff,  42),
+        MX31_PIN_LD11           = IOMUX_PIN(0xff,  43),
+        MX31_PIN_LD10           = IOMUX_PIN(0xff,  44),
+        MX31_PIN_LD9            = IOMUX_PIN(0xff,  45),
+        MX31_PIN_LD8            = IOMUX_PIN(0xff,  46),
+        MX31_PIN_LD7            = IOMUX_PIN(0xff,  47),
+        MX31_PIN_LD6            = IOMUX_PIN(0xff,  48),
+        MX31_PIN_LD5            = IOMUX_PIN(0xff,  49),
+        MX31_PIN_LD4            = IOMUX_PIN(0xff,  50),
+        MX31_PIN_LD3            = IOMUX_PIN(0xff,  51),
+        MX31_PIN_LD2            = IOMUX_PIN(0xff,  52),
+        MX31_PIN_LD1            = IOMUX_PIN(0xff,  53),
+        MX31_PIN_LD0            = IOMUX_PIN(0xff,  54),
+        MX31_PIN_USBH2_DATA1    = IOMUX_PIN(0xff,  55),
+        MX31_PIN_USBH2_DATA0    = IOMUX_PIN(0xff,  56),
+        MX31_PIN_USBH2_NXT      = IOMUX_PIN(0xff,  57),
+        MX31_PIN_USBH2_STP      = IOMUX_PIN(0xff,  58),
+        MX31_PIN_USBH2_DIR      = IOMUX_PIN(0xff,  59),
+        MX31_PIN_USBH2_CLK      = IOMUX_PIN(0xff,  60),
+        MX31_PIN_USBOTG_DATA7   = IOMUX_PIN(0xff,  61),
+        MX31_PIN_USBOTG_DATA6   = IOMUX_PIN(0xff,  62),
+        MX31_PIN_USBOTG_DATA5   = IOMUX_PIN(0xff,  63),
+        MX31_PIN_USBOTG_DATA4   = IOMUX_PIN(0xff,  64),
+        MX31_PIN_USBOTG_DATA3   = IOMUX_PIN(0xff,  65),
+        MX31_PIN_USBOTG_DATA2   = IOMUX_PIN(0xff,  66),
+        MX31_PIN_USBOTG_DATA1   = IOMUX_PIN(0xff,  67),
+        MX31_PIN_USBOTG_DATA0   = IOMUX_PIN(0xff,  68),
+        MX31_PIN_USBOTG_NXT     = IOMUX_PIN(0xff,  69),
+        MX31_PIN_USBOTG_STP     = IOMUX_PIN(0xff,  70),
+        MX31_PIN_USBOTG_DIR     = IOMUX_PIN(0xff,  71),
+        MX31_PIN_USBOTG_CLK     = IOMUX_PIN(0xff,  72),
+        MX31_PIN_USB_BYP        = IOMUX_PIN(31,    73),
+        MX31_PIN_USB_OC         = IOMUX_PIN(30,    74),
+        MX31_PIN_USB_PWR        = IOMUX_PIN(29,    75),
+        MX31_PIN_SJC_MOD        = IOMUX_PIN(0xff,  76),
+        MX31_PIN_DE_B           = IOMUX_PIN(0xff,  77),
+        MX31_PIN_TRSTB          = IOMUX_PIN(0xff,  78),
+        MX31_PIN_TDO            = IOMUX_PIN(0xff,  79),
+        MX31_PIN_TDI            = IOMUX_PIN(0xff,  80),
+        MX31_PIN_TMS            = IOMUX_PIN(0xff,  81),
+        MX31_PIN_TCK            = IOMUX_PIN(0xff,  82),
+        MX31_PIN_RTCK           = IOMUX_PIN(0xff,  83),
+        MX31_PIN_KEY_COL7       = IOMUX_PIN(57,    84),
+        MX31_PIN_KEY_COL6       = IOMUX_PIN(56,    85),
+        MX31_PIN_KEY_COL5       = IOMUX_PIN(55,    86),
+        MX31_PIN_KEY_COL4       = IOMUX_PIN(54,    87),
+        MX31_PIN_KEY_COL3       = IOMUX_PIN(0xff,  88),
+        MX31_PIN_KEY_COL2       = IOMUX_PIN(0xff,  89),
+        MX31_PIN_KEY_COL1       = IOMUX_PIN(0xff,  90),
+        MX31_PIN_KEY_COL0       = IOMUX_PIN(0xff,  91),
+        MX31_PIN_KEY_ROW7       = IOMUX_PIN(53,    92),
+        MX31_PIN_KEY_ROW6       = IOMUX_PIN(52,    93),
+        MX31_PIN_KEY_ROW5       = IOMUX_PIN(51,    94),
+        MX31_PIN_KEY_ROW4       = IOMUX_PIN(50,    95),
+        MX31_PIN_KEY_ROW3       = IOMUX_PIN(0xff,  96),
+        MX31_PIN_KEY_ROW2       = IOMUX_PIN(0xff,  97),
+        MX31_PIN_KEY_ROW1       = IOMUX_PIN(0xff,  98),
+        MX31_PIN_KEY_ROW0       = IOMUX_PIN(0xff,  99),
+        MX31_PIN_BATT_LINE      = IOMUX_PIN(49,   100),
+        MX31_PIN_CTS2           = IOMUX_PIN(0xff, 101),
+        MX31_PIN_RTS2           = IOMUX_PIN(0xff, 102),
+        MX31_PIN_TXD2           = IOMUX_PIN(28,   103),
+        MX31_PIN_RXD2           = IOMUX_PIN(27,   104),
+        MX31_PIN_DTR_DCE2       = IOMUX_PIN(48,   105),
+        MX31_PIN_DCD_DTE1       = IOMUX_PIN(47,   106),
+        MX31_PIN_RI_DTE1        = IOMUX_PIN(46,   107),
+        MX31_PIN_DSR_DTE1       = IOMUX_PIN(45,   108),
+        MX31_PIN_DTR_DTE1       = IOMUX_PIN(44,   109),
+        MX31_PIN_DCD_DCE1       = IOMUX_PIN(43,   110),
+        MX31_PIN_RI_DCE1        = IOMUX_PIN(42,   111),
+        MX31_PIN_DSR_DCE1       = IOMUX_PIN(41,   112),
+        MX31_PIN_DTR_DCE1       = IOMUX_PIN(40,   113),
+        MX31_PIN_CTS1           = IOMUX_PIN(39,   114),
+        MX31_PIN_RTS1           = IOMUX_PIN(38,   115),
+        MX31_PIN_TXD1           = IOMUX_PIN(37,   116),
+        MX31_PIN_RXD1           = IOMUX_PIN(36,   117),
+        MX31_PIN_CSPI2_SPI_RDY  = IOMUX_PIN(0xff, 118),
+        MX31_PIN_CSPI2_SCLK     = IOMUX_PIN(0xff, 119),
+        MX31_PIN_CSPI2_SS2      = IOMUX_PIN(0xff, 120),
+        MX31_PIN_CSPI2_SS1      = IOMUX_PIN(0xff, 121),
+        MX31_PIN_CSPI2_SS0      = IOMUX_PIN(0xff, 122),
+        MX31_PIN_CSPI2_MISO     = IOMUX_PIN(0xff, 123),
+        MX31_PIN_CSPI2_MOSI     = IOMUX_PIN(0xff, 124),
+        MX31_PIN_CSPI1_SPI_RDY  = IOMUX_PIN(0xff, 125),
+        MX31_PIN_CSPI1_SCLK     = IOMUX_PIN(0xff, 126),
+        MX31_PIN_CSPI1_SS2      = IOMUX_PIN(0xff, 127),
+        MX31_PIN_CSPI1_SS1      = IOMUX_PIN(0xff, 128),
+        MX31_PIN_CSPI1_SS0      = IOMUX_PIN(0xff, 129),
+        MX31_PIN_CSPI1_MISO     = IOMUX_PIN(0xff, 130),
+        MX31_PIN_CSPI1_MOSI     = IOMUX_PIN(0xff, 131),
+        MX31_PIN_SFS6           = IOMUX_PIN(26,   132),
+        MX31_PIN_SCK6           = IOMUX_PIN(25,   133),
+        MX31_PIN_SRXD6          = IOMUX_PIN(24,   134),
+        MX31_PIN_STXD6          = IOMUX_PIN(23,   135),
+        MX31_PIN_SFS5           = IOMUX_PIN(0xff, 136),
+        MX31_PIN_SCK5           = IOMUX_PIN(0xff, 137),
+        MX31_PIN_SRXD5          = IOMUX_PIN(22,   138),
+        MX31_PIN_STXD5          = IOMUX_PIN(21,   139),
+        MX31_PIN_SFS4           = IOMUX_PIN(0xff, 140),
+        MX31_PIN_SCK4           = IOMUX_PIN(0xff, 141),
+        MX31_PIN_SRXD4          = IOMUX_PIN(20,   142),
+        MX31_PIN_STXD4          = IOMUX_PIN(19,   143),
+        MX31_PIN_SFS3           = IOMUX_PIN(0xff, 144),
+        MX31_PIN_SCK3           = IOMUX_PIN(0xff, 145),
+        MX31_PIN_SRXD3          = IOMUX_PIN(18,   146),
+        MX31_PIN_STXD3          = IOMUX_PIN(17,   147),
+        MX31_PIN_I2C_DAT        = IOMUX_PIN(0xff, 148),
+        MX31_PIN_I2C_CLK        = IOMUX_PIN(0xff, 149),
+        MX31_PIN_CSI_PIXCLK     = IOMUX_PIN(83,   150),
+        MX31_PIN_CSI_HSYNC      = IOMUX_PIN(82,   151),
+        MX31_PIN_CSI_VSYNC      = IOMUX_PIN(81,   152),
+        MX31_PIN_CSI_MCLK       = IOMUX_PIN(80,   153),
+        MX31_PIN_CSI_D15        = IOMUX_PIN(79,   154),
+        MX31_PIN_CSI_D14        = IOMUX_PIN(78,   155),
+        MX31_PIN_CSI_D13        = IOMUX_PIN(77,   156),
+        MX31_PIN_CSI_D12        = IOMUX_PIN(76,   157),
+        MX31_PIN_CSI_D11        = IOMUX_PIN(75,   158),
+        MX31_PIN_CSI_D10        = IOMUX_PIN(74,   159),
+        MX31_PIN_CSI_D9         = IOMUX_PIN(73,   160),
+        MX31_PIN_CSI_D8         = IOMUX_PIN(72,   161),
+        MX31_PIN_CSI_D7         = IOMUX_PIN(71,   162),
+        MX31_PIN_CSI_D6         = IOMUX_PIN(70,   163),
+        MX31_PIN_CSI_D5         = IOMUX_PIN(69,   164),
+        MX31_PIN_CSI_D4         = IOMUX_PIN(68,   165),
+        MX31_PIN_M_GRANT        = IOMUX_PIN(0xff, 166),
+        MX31_PIN_M_REQUEST      = IOMUX_PIN(0xff, 167),
+        MX31_PIN_PC_POE         = IOMUX_PIN(0xff, 168),
+        MX31_PIN_PC_RW_B        = IOMUX_PIN(0xff, 169),
+        MX31_PIN_IOIS16         = IOMUX_PIN(0xff, 170),
+        MX31_PIN_PC_RST         = IOMUX_PIN(0xff, 171),
+        MX31_PIN_PC_BVD2        = IOMUX_PIN(0xff, 172),
+        MX31_PIN_PC_BVD1        = IOMUX_PIN(0xff, 173),
+        MX31_PIN_PC_VS2         = IOMUX_PIN(0xff, 174),
+        MX31_PIN_PC_VS1         = IOMUX_PIN(0xff, 175),
+        MX31_PIN_PC_PWRON       = IOMUX_PIN(0xff, 176),
+        MX31_PIN_PC_READY       = IOMUX_PIN(0xff, 177),
+        MX31_PIN_PC_WAIT_B      = IOMUX_PIN(0xff, 178),
+        MX31_PIN_PC_CD2_B       = IOMUX_PIN(0xff, 179),
+        MX31_PIN_PC_CD1_B       = IOMUX_PIN(0xff, 180),
+        MX31_PIN_D0             = IOMUX_PIN(0xff, 181),
+        MX31_PIN_D1             = IOMUX_PIN(0xff, 182),
+        MX31_PIN_D2             = IOMUX_PIN(0xff, 183),
+        MX31_PIN_D3             = IOMUX_PIN(0xff, 184),
+        MX31_PIN_D4             = IOMUX_PIN(0xff, 185),
+        MX31_PIN_D5             = IOMUX_PIN(0xff, 186),
+        MX31_PIN_D6             = IOMUX_PIN(0xff, 187),
+        MX31_PIN_D7             = IOMUX_PIN(0xff, 188),
+        MX31_PIN_D8             = IOMUX_PIN(0xff, 189),
+        MX31_PIN_D9             = IOMUX_PIN(0xff, 190),
+        MX31_PIN_D10            = IOMUX_PIN(0xff, 191),
+        MX31_PIN_D11            = IOMUX_PIN(0xff, 192),
+        MX31_PIN_D12            = IOMUX_PIN(0xff, 193),
+        MX31_PIN_D13            = IOMUX_PIN(0xff, 194),
+        MX31_PIN_D14            = IOMUX_PIN(0xff, 195),
+        MX31_PIN_D15            = IOMUX_PIN(0xff, 196),
+        MX31_PIN_NFRB           = IOMUX_PIN(16,   197),
+        MX31_PIN_NFCE_B         = IOMUX_PIN(15,   198),
+        MX31_PIN_NFWP_B         = IOMUX_PIN(14,   199),
+        MX31_PIN_NFCLE          = IOMUX_PIN(13,   200),
+        MX31_PIN_NFALE          = IOMUX_PIN(12,   201),
+        MX31_PIN_NFRE_B         = IOMUX_PIN(11,   202),
+        MX31_PIN_NFWE_B         = IOMUX_PIN(10,   203),
+        MX31_PIN_SDQS3          = IOMUX_PIN(0xff, 204),
+        MX31_PIN_SDQS2          = IOMUX_PIN(0xff, 205),
+        MX31_PIN_SDQS1          = IOMUX_PIN(0xff, 206),
+        MX31_PIN_SDQS0          = IOMUX_PIN(0xff, 207),
+        MX31_PIN_SDCLK_B        = IOMUX_PIN(0xff, 208),
+        MX31_PIN_SDCLK          = IOMUX_PIN(0xff, 209),
+        MX31_PIN_SDCKE1         = IOMUX_PIN(0xff, 210),
+        MX31_PIN_SDCKE0         = IOMUX_PIN(0xff, 211),
+        MX31_PIN_SDWE           = IOMUX_PIN(0xff, 212),
+        MX31_PIN_CAS            = IOMUX_PIN(0xff, 213),
+        MX31_PIN_RAS            = IOMUX_PIN(0xff, 214),
+        MX31_PIN_RW             = IOMUX_PIN(0xff, 215),
+        MX31_PIN_BCLK           = IOMUX_PIN(0xff, 216),
+        MX31_PIN_LBA            = IOMUX_PIN(0xff, 217),
+        MX31_PIN_ECB            = IOMUX_PIN(0xff, 218),
+        MX31_PIN_CS5            = IOMUX_PIN(0xff, 219),
+        MX31_PIN_CS4            = IOMUX_PIN(0xff, 220),
+        MX31_PIN_CS3            = IOMUX_PIN(0xff, 221),
+        MX31_PIN_CS2            = IOMUX_PIN(0xff, 222),
+        MX31_PIN_CS1            = IOMUX_PIN(0xff, 223),
+        MX31_PIN_CS0            = IOMUX_PIN(0xff, 224),
+        MX31_PIN_OE             = IOMUX_PIN(0xff, 225),
+        MX31_PIN_EB1            = IOMUX_PIN(0xff, 226),
+        MX31_PIN_EB0            = IOMUX_PIN(0xff, 227),
+        MX31_PIN_DQM3           = IOMUX_PIN(0xff, 228),
+        MX31_PIN_DQM2           = IOMUX_PIN(0xff, 229),
+        MX31_PIN_DQM1           = IOMUX_PIN(0xff, 230),
+        MX31_PIN_DQM0           = IOMUX_PIN(0xff, 231),
+        MX31_PIN_SD31           = IOMUX_PIN(0xff, 232),
+        MX31_PIN_SD30           = IOMUX_PIN(0xff, 233),
+        MX31_PIN_SD29           = IOMUX_PIN(0xff, 234),
+        MX31_PIN_SD28           = IOMUX_PIN(0xff, 235),
+        MX31_PIN_SD27           = IOMUX_PIN(0xff, 236),
+        MX31_PIN_SD26           = IOMUX_PIN(0xff, 237),
+        MX31_PIN_SD25           = IOMUX_PIN(0xff, 238),
+        MX31_PIN_SD24           = IOMUX_PIN(0xff, 239),
+        MX31_PIN_SD23           = IOMUX_PIN(0xff, 240),
+        MX31_PIN_SD22           = IOMUX_PIN(0xff, 241),
+        MX31_PIN_SD21           = IOMUX_PIN(0xff, 242),
+        MX31_PIN_SD20           = IOMUX_PIN(0xff, 243),
+        MX31_PIN_SD19           = IOMUX_PIN(0xff, 244),
+        MX31_PIN_SD18           = IOMUX_PIN(0xff, 245),
+        MX31_PIN_SD17           = IOMUX_PIN(0xff, 246),
+        MX31_PIN_SD16           = IOMUX_PIN(0xff, 247),
+        MX31_PIN_SD15           = IOMUX_PIN(0xff, 248),
+        MX31_PIN_SD14           = IOMUX_PIN(0xff, 249),
+        MX31_PIN_SD13           = IOMUX_PIN(0xff, 250),
+        MX31_PIN_SD12           = IOMUX_PIN(0xff, 251),
+        MX31_PIN_SD11           = IOMUX_PIN(0xff, 252),
+        MX31_PIN_SD10           = IOMUX_PIN(0xff, 253),
+        MX31_PIN_SD9            = IOMUX_PIN(0xff, 254),
+        MX31_PIN_SD8            = IOMUX_PIN(0xff, 255),
+        MX31_PIN_SD7            = IOMUX_PIN(0xff, 256),
+        MX31_PIN_SD6            = IOMUX_PIN(0xff, 257),
+        MX31_PIN_SD5            = IOMUX_PIN(0xff, 258),
+        MX31_PIN_SD4            = IOMUX_PIN(0xff, 259),
+        MX31_PIN_SD3            = IOMUX_PIN(0xff, 260),
+        MX31_PIN_SD2            = IOMUX_PIN(0xff, 261),
+        MX31_PIN_SD1            = IOMUX_PIN(0xff, 262),
+        MX31_PIN_SD0            = IOMUX_PIN(0xff, 263),
+        MX31_PIN_SDBA0          = IOMUX_PIN(0xff, 264),
+        MX31_PIN_SDBA1          = IOMUX_PIN(0xff, 265),
+        MX31_PIN_A25            = IOMUX_PIN(0xff, 266),
+        MX31_PIN_A24            = IOMUX_PIN(0xff, 267),
+        MX31_PIN_A23            = IOMUX_PIN(0xff, 268),
+        MX31_PIN_A22            = IOMUX_PIN(0xff, 269),
+        MX31_PIN_A21            = IOMUX_PIN(0xff, 270),
+        MX31_PIN_A20            = IOMUX_PIN(0xff, 271),
+        MX31_PIN_A19            = IOMUX_PIN(0xff, 272),
+        MX31_PIN_A18            = IOMUX_PIN(0xff, 273),
+        MX31_PIN_A17            = IOMUX_PIN(0xff, 274),
+        MX31_PIN_A16            = IOMUX_PIN(0xff, 275),
+        MX31_PIN_A14            = IOMUX_PIN(0xff, 276),
+        MX31_PIN_A15            = IOMUX_PIN(0xff, 277),
+        MX31_PIN_A13            = IOMUX_PIN(0xff, 278),
+        MX31_PIN_A12            = IOMUX_PIN(0xff, 279),
+        MX31_PIN_A11            = IOMUX_PIN(0xff, 280),
+        MX31_PIN_MA10           = IOMUX_PIN(0xff, 281),
+        MX31_PIN_A10            = IOMUX_PIN(0xff, 282),
+        MX31_PIN_A9             = IOMUX_PIN(0xff, 283),
+        MX31_PIN_A8             = IOMUX_PIN(0xff, 284),
+        MX31_PIN_A7             = IOMUX_PIN(0xff, 285),
+        MX31_PIN_A6             = IOMUX_PIN(0xff, 286),
+        MX31_PIN_A5             = IOMUX_PIN(0xff, 287),
+        MX31_PIN_A4             = IOMUX_PIN(0xff, 288),
+        MX31_PIN_A3             = IOMUX_PIN(0xff, 289),
+        MX31_PIN_A2             = IOMUX_PIN(0xff, 290),
+        MX31_PIN_A1             = IOMUX_PIN(0xff, 291),
+        MX31_PIN_A0             = IOMUX_PIN(0xff, 292),
+        MX31_PIN_VPG1           = IOMUX_PIN(0xff, 293),
+        MX31_PIN_VPG0           = IOMUX_PIN(0xff, 294),
+        MX31_PIN_DVFS1          = IOMUX_PIN(0xff, 295),
+        MX31_PIN_DVFS0          = IOMUX_PIN(0xff, 296),
+        MX31_PIN_VSTBY          = IOMUX_PIN(0xff, 297),
+        MX31_PIN_POWER_FAIL     = IOMUX_PIN(0xff, 298),
+        MX31_PIN_CKIL           = IOMUX_PIN(0xff, 299),
+        MX31_PIN_BOOT_MODE4     = IOMUX_PIN(0xff, 300),
+        MX31_PIN_BOOT_MODE3     = IOMUX_PIN(0xff, 301),
+        MX31_PIN_BOOT_MODE2     = IOMUX_PIN(0xff, 302),
+        MX31_PIN_BOOT_MODE1     = IOMUX_PIN(0xff, 303),
+        MX31_PIN_BOOT_MODE0     = IOMUX_PIN(0xff, 304),
+        MX31_PIN_CLKO           = IOMUX_PIN(0xff, 305),
+        MX31_PIN_POR_B          = IOMUX_PIN(0xff, 306),
+        MX31_PIN_RESET_IN_B     = IOMUX_PIN(0xff, 307),
+        MX31_PIN_CKIH           = IOMUX_PIN(0xff, 308),
+        MX31_PIN_SIMPD0         = IOMUX_PIN(35,   309),
+        MX31_PIN_SRX0           = IOMUX_PIN(34,   310),
+        MX31_PIN_STX0           = IOMUX_PIN(33,   311),
+        MX31_PIN_SVEN0          = IOMUX_PIN(32,   312),
+        MX31_PIN_SRST0          = IOMUX_PIN(67,   313),
+        MX31_PIN_SCLK0          = IOMUX_PIN(66,   314),
+        MX31_PIN_GPIO3_1        = IOMUX_PIN(65,   315),
+        MX31_PIN_GPIO3_0        = IOMUX_PIN(64,   316),
+        MX31_PIN_GPIO1_6        = IOMUX_PIN( 6,   317),
+        MX31_PIN_GPIO1_5        = IOMUX_PIN( 5,   318),
+        MX31_PIN_GPIO1_4        = IOMUX_PIN( 4,   319),
+        MX31_PIN_GPIO1_3        = IOMUX_PIN( 3,   320),
+        MX31_PIN_GPIO1_2        = IOMUX_PIN( 2,   321),
+        MX31_PIN_GPIO1_1        = IOMUX_PIN( 1,   322),
+        MX31_PIN_GPIO1_0        = IOMUX_PIN( 0,   323),
+        MX31_PIN_PWMO           = IOMUX_PIN( 9,   324),
+        MX31_PIN_WATCHDOG_RST   = IOMUX_PIN(0xff, 325),
+        MX31_PIN_COMPARE        = IOMUX_PIN( 8,   326),
+        MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
+};
+
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MX31_PIN_(pin name)__(function)
+ */
+#define MX31_PIN_CSPI3_MOSI__RXD3       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI3_MISO__TXD3       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins, u32);
+
+#endif
+
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
 
 #include <asm/hardware.h>
 
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
-#define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
-
-/* Number of normal interrupts */
-#define NR_IRQS         (MXC_MAX_INT_LINES + \
-                        MXC_MAX_GPIO_LINES + \
-                        MXC_MAX_VIRTUAL_INTS)
-
-/* Number of fast interrupts */
-#define NR_FIQS         MXC_MAX_INTS
-
 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX27_H__
+#define __ASM_ARCH_MXC_MX27_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/* IRAM */
+#define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
+
+/* Register offests */
+#define AIPI_BASE_ADDR          0x10000000
+#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define AIPI_SIZE               SZ_1M
+
+#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+
+#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
+#define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
+#define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
+#define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
+#define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
+#define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
+#define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
+#define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
+
+#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
+#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+/* for mx27*/
+#define OTG_BASE_ADDR           USBOTG_BASE_ADDR
+#define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
+#define EMMA_BASE_ADDR          (AIPI_BASE_ADDR + 0x26400)
+#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
+
+#define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
+#define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
+#define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
+#define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
+#define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
+
+#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+
+/* ROMP and AVIC */
+#define ROMP_BASE_ADDR          0x10041000
+
+#define AVIC_BASE_ADDR          0x10040000
+
+#define SAHB1_BASE_ADDR         0x80000000
+#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define SAHB1_SIZE              SZ_1M
+
+#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
+#define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
+
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define X_MEMC_BASE_ADDR        0xD8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define X_MEMC_SIZE             SZ_1M
+
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
+
+/* Memory regions and CS */
+#define SDRAM_BASE_ADDR         0xA0000000
+#define CSD1_BASE_ADDR          0xB0000000
+
+#define CS0_BASE_ADDR           0xC0000000
+#define CS1_BASE_ADDR           0xC8000000
+#define CS2_BASE_ADDR           0xD0000000
+#define CS3_BASE_ADDR           0xD2000000
+#define CS4_BASE_ADDR           0xD4000000
+#define CS5_BASE_ADDR           0xD6000000
+#define PCMCIA_MEM_BASE_ADDR    0xDC000000
+
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
+                AIPI_IO_ADDRESS(x) : \
+        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
+                SAHB1_IO_ADDRESS(x) : \
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
+                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
+
+/* define the address mapping macros: in physical address order */
+#define AIPI_IO_ADDRESS(x)  \
+        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
+
+#define SAHB1_IO_ADDRESS(x)  \
+        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* fixed interrput numbers */
+#define MXC_INT_CCM             63
+#define MXC_INT_IIM             62
+#define MXC_INT_LCDC            61
+#define MXC_INT_SLCDC           60
+#define MXC_INT_SAHARA          59
+#define MXC_INT_SCC_SCM         58
+#define MXC_INT_SCC_SMN         57
+#define MXC_INT_USB3            56
+#define MXC_INT_USB2            55
+#define MXC_INT_USB1            54
+#define MXC_INT_VPU             53
+#define MXC_INT_EMMAPP          52
+#define MXC_INT_EMMAPRP         51
+#define MXC_INT_FEC             50
+#define MXC_INT_UART5           49
+#define MXC_INT_UART6           48
+#define MXC_INT_DMACH15         47
+#define MXC_INT_DMACH14         46
+#define MXC_INT_DMACH13         45
+#define MXC_INT_DMACH12         44
+#define MXC_INT_DMACH11         43
+#define MXC_INT_DMACH10         42
+#define MXC_INT_DMACH9          41
+#define MXC_INT_DMACH8          40
+#define MXC_INT_DMACH7          39
+#define MXC_INT_DMACH6          38
+#define MXC_INT_DMACH5          37
+#define MXC_INT_DMACH4          36
+#define MXC_INT_DMACH3          35
+#define MXC_INT_DMACH2          34
+#define MXC_INT_DMACH1          33
+#define MXC_INT_DMACH0          32
+#define MXC_INT_CSI             31
+#define MXC_INT_ATA             30
+#define MXC_INT_NANDFC          29
+#define MXC_INT_PCMCIA          28
+#define MXC_INT_WDOG            27
+#define MXC_INT_GPT1            26
+#define MXC_INT_GPT2            25
+#define MXC_INT_GPT3            24
+#define MXC_INT_GPT             INT_GPT1
+#define MXC_INT_PWM             23
+#define MXC_INT_RTC             22
+#define MXC_INT_KPP             21
+#define MXC_INT_UART1           20
+#define MXC_INT_UART2           19
+#define MXC_INT_UART3           18
+#define MXC_INT_UART4           17
+#define MXC_INT_CSPI1           16
+#define MXC_INT_CSPI2           15
+#define MXC_INT_SSI1            14
+#define MXC_INT_SSI2            13
+#define MXC_INT_I2C             12
+#define MXC_INT_SDHC1           11
+#define MXC_INT_SDHC2           10
+#define MXC_INT_SDHC3           9
+#define MXC_INT_GPIO            8
+#define MXC_INT_SDHC            7
+#define MXC_INT_CSPI3           6
+#define MXC_INT_RTIC            5
+#define MXC_INT_GPT4            4
+#define MXC_INT_GPT5            3
+#define MXC_INT_GPT6            2
+#define MXC_INT_I2C2            1
+
+/* fixed DMA request numbers */
+#define DMA_REQ_NFC             37
+#define DMA_REQ_SDHC3           36
+#define DMA_REQ_UART6_RX        35
+#define DMA_REQ_UART6_TX        34
+#define DMA_REQ_UART5_RX        33
+#define DMA_REQ_UART5_TX        32
+#define DMA_REQ_CSI_RX          31
+#define DMA_REQ_CSI_STAT        30
+#define DMA_REQ_ATA_RCV         29
+#define DMA_REQ_ATA_TX          28
+#define DMA_REQ_UART1_TX        27
+#define DMA_REQ_UART1_RX        26
+#define DMA_REQ_UART2_TX        25
+#define DMA_REQ_UART2_RX        24
+#define DMA_REQ_UART3_TX        23
+#define DMA_REQ_UART3_RX        22
+#define DMA_REQ_UART4_TX        21
+#define DMA_REQ_UART4_RX        20
+#define DMA_REQ_CSPI1_TX        19
+#define DMA_REQ_CSPI1_RX        18
+#define DMA_REQ_CSPI2_TX        17
+#define DMA_REQ_CSPI2_RX        16
+#define DMA_REQ_SSI1_TX1        15
+#define DMA_REQ_SSI1_RX1        14
+#define DMA_REQ_SSI1_TX0        13
+#define DMA_REQ_SSI1_RX0        12
+#define DMA_REQ_SSI2_TX1        11
+#define DMA_REQ_SSI2_RX1        10
+#define DMA_REQ_SSI2_TX0        9
+#define DMA_REQ_SSI2_RX0        8
+#define DMA_REQ_SDHC1           7
+#define DMA_REQ_SDHC2           6
+#define DMA_REQ_MSHC            4
+#define DMA_REQ_EXT             3
+#define DMA_REQ_CSPI3_TX        2
+#define DMA_REQ_CSPI3_RX        1
+
+/* silicon revisions specific to i.MX27 */
+#define CHIP_REV_1_0            0x00
+#define CHIP_REV_2_0            0x01
+
+#ifndef __ASSEMBLY__
+extern int mx27_revision(void);
+#endif
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x1C
+#define GPIO_GDIR               0x00
+#define GPIO_PSR                0x24
+#define GPIO_ICR1               0x28
+#define GPIO_ICR2               0x2C
+#define GPIO_IMR                0x30
+#define GPIO_ISR                0x34
+#define GPIO_INT_LOW_LEV        0x3
+#define GPIO_INT_HIGH_LEV       0x2
+#define GPIO_INT_RISE_EDGE      0x0
+#define GPIO_INT_FALL_EDGE      0x1
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this is an i.MX27 CPU */
+#define cpu_is_mx27()           (1)
+
+/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
+#define ARCH_NR_GPIOS           (192 + 16)
+
+/* OS clock tick rate */
+#define CLOCK_TICK_RATE         13300000
+
+/* Start of RAM */
+#define PHYS_OFFSET             SDRAM_BASE_ADDR
+
+/* max interrupt lines count */
+#define NR_IRQS                 256
+
+/* count of internal interrupt sources */
+#define MXC_MAX_INT_LINES       64
+
+#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 36a1af495bb3..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
 #define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
 #define MXC_MAX_VIRTUAL_INTS    16
 
+#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
+
 /*!
  * Number of GPIO port as defined in the IC Spec
  */
@@ -347,6 +349,25 @@
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
 
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x00
+#define GPIO_GDIR               0x04
+#define GPIO_PSR                0x08
+#define GPIO_ICR1               0x0C
+#define GPIO_ICR2               0x10
+#define GPIO_IMR                0x14
+#define GPIO_ISR                0x18
+#define GPIO_INT_LOW_LEV        0x0
+#define GPIO_INT_HIGH_LEV       0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_FALL_EDGE      0x3
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this CPU supports up to 96 GPIOs */
+#define ARCH_NR_GPIOS           96
+
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
 /* this is a i.MX31 CPU */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
 /*
  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
  */
 
 #ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
 # define cpu_is_mx31() (0)
 #endif
 
-/*
- *****************************************
- * GPT  Register definitions             *
- *****************************************
- */
-#define MXC_GPT_GPTCR           IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
-#define MXC_GPT_GPTPR           IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
-#define MXC_GPT_GPTSR           IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
-#define MXC_GPT_GPTIR           IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
-#define MXC_GPT_GPTOCR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
-#define MXC_GPT_GPTOCR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
-#define MXC_GPT_GPTOCR3         IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
-#define MXC_GPT_GPTICR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
-#define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
-#define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
-
-/* GPT Control register bit definitions */
-#define GPTCR_FO3                       (1 << 31)
-#define GPTCR_FO2                       (1 << 30)
-#define GPTCR_FO1                       (1 << 29)
-
-#define GPTCR_OM3_SHIFT                 26
-#define GPTCR_OM3_MASK                  (7 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_DISCONNECTED          (0 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_TOGGLE                (1 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_CLEAR                 (2 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_SET                   (3 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_GENERATE_LOW          (7 << GPTCR_OM3_SHIFT)
-
-#define GPTCR_OM2_SHIFT                 23
-#define GPTCR_OM2_MASK                  (7 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_DISCONNECTED          (0 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_TOGGLE                (1 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_CLEAR                 (2 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_SET                   (3 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_GENERATE_LOW          (7 << GPTCR_OM2_SHIFT)
-
-#define GPTCR_OM1_SHIFT                 20
-#define GPTCR_OM1_MASK                  (7 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_DISCONNECTED          (0 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_TOGGLE                (1 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_CLEAR                 (2 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_SET                   (3 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_GENERATE_LOW          (7 << GPTCR_OM1_SHIFT)
-
-#define GPTCR_IM2_SHIFT                 18
-#define GPTCR_IM2_MASK                  (3 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_DISABLE       (0 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_RISING        (1 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_FALLING       (2 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_BOTH          (3 << GPTCR_IM2_SHIFT)
-
-#define GPTCR_IM1_SHIFT                 16
-#define GPTCR_IM1_MASK                  (3 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_DISABLE       (0 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_RISING        (1 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_FALLING       (2 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_BOTH          (3 << GPTCR_IM1_SHIFT)
-
-#define GPTCR_SWR                       (1 << 15)
-#define GPTCR_FRR                       (1 << 9)
-
-#define GPTCR_CLKSRC_SHIFT              6
-#define GPTCR_CLKSRC_MASK               (7 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_NOCLOCK            (0 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_HIGHFREQ           (2 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLKIN              (3 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLK32K             (7 << GPTCR_CLKSRC_SHIFT)
-
-#define GPTCR_STOPEN                    (1 << 5)
-#define GPTCR_DOZEN                     (1 << 4)
-#define GPTCR_WAITEN                    (1 << 3)
-#define GPTCR_DBGEN                     (1 << 2)
-
-#define GPTCR_ENMOD                     (1 << 1)
-#define GPTCR_ENABLE                    (1 << 0)
-
-#define GPTSR_OF1                       (1 << 0)
-#define GPTSR_OF2                       (1 << 1)
-#define GPTSR_OF3                       (1 << 2)
-#define GPTSR_IF1                       (1 << 3)
-#define GPTSR_IF2                       (1 << 4)
-#define GPTSR_ROV                       (1 << 5)
-
-#define GPTIR_OF1IE                     GPTSR_OF1
-#define GPTIR_OF2IE                     GPTSR_OF2
-#define GPTIR_OF3IE                     GPTSR_OF3
-#define GPTIR_IF1IE                     GPTSR_IF1
-#define GPTIR_IF2IE                     GPTSR_IF2
-#define GPTIR_ROVIE                     GPTSR_ROV
-
-/*
- *****************************************
- * AVIC Registers                        *
- *****************************************
- */
-#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
-#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
-#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
-#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
-#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
-#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
-#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
-#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
-#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
-#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
-#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
-#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
-#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
-#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
-#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
-#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
-#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
-#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
-#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
-
-#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
-#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
-#define IIM_PROD_REV_SH         3
-#define IIM_PROD_REV_LEN        5
+#ifndef CONFIG_MACH_MX27
+# define cpu_is_mx27() (0)
+#endif
 
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
+/*
+ * mxc_timer.h
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __PLAT_MXC_TIMER_H
+#define __PLAT_MXC_TIMER_H
+
+#include <linux/clk.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_ARCH_IMX
+#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
+#define TIMER_INTERRUPT         TIM1_INT
+
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_CLK_TIN            (3<<1)
+#define TCTL_CLK_32             (4<<1)
+
+#define MXC_TCTL   0x00
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_IMX */
+
+#ifdef CONFIG_ARCH_MX2
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT1
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX2 */
+
+#ifdef CONFIG_ARCH_MX3
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
+#define TCTL_CLK_IPG            (1<<6)
+#define TCTL_FRR                (1<<9)
+#define TCTL_WAITEN             (1<<3)
+
+#define MXC_TPRER  0x04
+#define MXC_TSTAT  0x08
+#define TSTAT_OF1               (1<<0)
+#define TSTAT_OF2               (1<<1)
+#define TSTAT_OF3               (1<<2)
+#define TSTAT_IF1               (1<<3)
+#define TSTAT_IF2               (1<<4)
+#define TSTAT_ROV               (1<<5)
+#define MXC_IR     0x0c
+#define MXC_TCMP   0x10
+#define MXC_TCMP2  0x14
+#define MXC_TCMP3  0x18
+#define MXC_TCR    0x1c
+#define MXC_TCN    0x24
+
+static inline void gpt_irq_disable(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX3 */
+
+#define TCTL_SWR                (1<<15)
+#define TCTL_CC                 (1<<10)
+#define TCTL_OM                 (1<<9)
+#define TCTL_CAP_RIS            (1<<6)
+#define TCTL_CAP_FAL            (2<<6)
+#define TCTL_CAP_RIS_FAL        (3<<6)
+#define TCTL_CAP_ENA            (1<<5)
+#define TCTL_TEN                (1<<0)
+
+#endif
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 0b7b34603f1c..0dca11ce21fc 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -66,13 +66,13 @@
          __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
 
 #  define REGGETIM_IDX(var, reg, field, idx)                            \
-         __REGGET(var, reg ## _ ## field((idx))) /                      \
+         __REGGET(var, reg ## _ ## field((idx))) /                      \
          __REGSHIFT(reg ## _ ## field((idx)))
 
 #else
 
 #  define __REG(x)      io_p2v(x)
-#  define __REG2(x, y)  io_p2v((x) + (y))
+#  define __REG2(x, y)  io_p2v((x) + 4 * (y))
 
 #endif
 
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
index e9c65ce3cb12..c7db9004ec31 100644
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -36,9 +36,4 @@
 
 #define TWL4030_IRQNUM                  INT_24XX_SYS_NIRQ
 
-/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
-#define IH_TWL4030_BASE                 IH_BOARD_BASE
-#define IH_TWL4030_END                  (IH_TWL4030_BASE+8)
-#define NR_IRQS                         (IH_TWL4030_END)
-
 #endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 0f6404435ea8..c5d0f32a40ac 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,12 +30,6 @@
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START             0x04000300
 
-#define MAXIRQNUM                       (IH_BOARD_BASE)
-#define MAXFIQNUM                       MAXIRQNUM
-#define MAXSWINUM                       MAXIRQNUM
-
-#define NR_IRQS                         (MAXIRQNUM + 1)
-
 extern void h3_mmc_init(void);
 extern void h3_mmc_slot_cover_handler(void *arg, int state);
 
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 56d2c98e143c..9ca03dec9d36 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,9 +36,6 @@
 #define OMAP1510P1_EMIFS_PRI_VALUE              0x00
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
 
-#define NR_FPGA_IRQS            24
-#define NR_IRQS                 (IH_BOARD_BASE + NR_FPGA_IRQS)
-
 #ifndef __ASSEMBLY__
 void fpga_write(unsigned char val, int reg);
 unsigned char fpga_read(int reg);
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index eb74420cb439..d7429cb0f726 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,10 +36,4 @@
 #define OMAP_SDRAM_DEVICE               D256M_1X16_4B
 #endif
 
-#define MAXIRQNUM               IH_BOARD_BASE
-#define MAXFIQNUM               MAXIRQNUM
-#define MAXSWINUM               MAXIRQNUM
-
-#define NR_IRQS                 (MAXIRQNUM + 1)
-
 #endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 12a5e4de9518..4c7b3514f71a 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -33,12 +33,24 @@ struct dpll_data {
         void __iomem            *mult_div1_reg;
         u32                     mult_mask;
         u32                     div1_mask;
+        u16                     last_rounded_m;
+        u8                      last_rounded_n;
+        unsigned long           last_rounded_rate;
+        unsigned int            rate_tolerance;
+        u16                     max_multiplier;
+        u8                      max_divider;
+        u32                     max_tolerance;
 #  if defined(CONFIG_ARCH_OMAP3)
+        u8                      modes;
         void __iomem            *control_reg;
         u32                     enable_mask;
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
+        void __iomem            *autoidle_reg;
+        u32                     autoidle_mask;
+        void __iomem            *idlest_reg;
+        u8                      idlest_bit;
 #  endif
 };
 
@@ -66,11 +78,14 @@ struct clk {
         void __iomem            *clksel_reg;
         u32                     clksel_mask;
         const struct clksel     *clksel;
-        const struct dpll_data  *dpll_data;
+        struct dpll_data        *dpll_data;
 #else
         __u8                    rate_offset;
         __u8                    src_offset;
 #endif
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
 };
 
 struct cpufreq_frequency_table;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 36a3b62d4d8d..8ac03071f60c 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
+/* IO bases for various OMAP processors */
+struct omap_globals {
+        void __iomem    *tap;           /* Control module ID code */
+        void __iomem    *sdrc;          /* SDRAM Controller */
+        void __iomem    *sms;           /* SDRAM Memory Scheduler */
+        void __iomem    *ctrl;          /* System Control Module */
+        void __iomem    *prm;           /* Power and Reset Management */
+        void __iomem    *cm;            /* Clock Management */
+};
+
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
 
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_memory(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
+
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 59c0686f8be7..987553e3eeb9 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -167,8 +167,7 @@
 
 #ifndef __ASSEMBLY__
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-extern void omap_ctrl_base_set(u32 base);
-extern u32 omap_ctrl_base_get(void);
+extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
@@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
 #else
-#define omap_ctrl_base_set(x)           WARN_ON(1)
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8a4cf52778b..52db09f83281 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -3,7 +3,7 @@
  *
  * OMAP cpu type detection
  *
- * Copyright (C) 2004 Nokia Corporation
+ * Copyright (C) 2004, 2008 Nokia Corporation
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
@@ -26,6 +26,12 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
+struct omap_chip_id {
+        u8 oc;
+};
+
+#define OMAP_CHIP_INIT(x)       { .oc = x }
+
 extern unsigned int system_rev;
 
 #define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
@@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP2430_REV_ES1_0      0x24300000
 #define OMAP3430_REV_ES1_0      0x34300000
 #define OMAP3430_REV_ES2_0      0x34301000
+#define OMAP3430_REV_ES2_1      0x34302000
+#define OMAP3430_REV_ES2_2      0x34303000
+
+/*
+ * omap_chip bits
+ *
+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
+ * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
+ * something that is only valid on that particular ES revision.
+ *
+ * These bits may be ORed together to indicate structures that are
+ * available on multiple chip types.
+ *
+ * To test whether a particular structure matches the current OMAP chip type,
+ * use omap_chip_is().
+ *
+ */
+#define CHIP_IS_OMAP2420       (1 << 0)
+#define CHIP_IS_OMAP2430       (1 << 1)
+#define CHIP_IS_OMAP3430       (1 << 2)
+#define CHIP_IS_OMAP3430ES1    (1 << 3)
+#define CHIP_IS_OMAP3430ES2    (1 << 4)
+
+#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+int omap_chip_is(struct omap_chip_id oci);
+
 
 /*
  * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
@@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
 #define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
 
-#endif
+void omap2_check_revision(void);
+
+#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
 
 #endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 24acf090030d..f4dcb9587869 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,108 +22,128 @@
 #define __ASM_ARCH_DMA_H
 
 /* Hardware registers for omap1 */
-#define OMAP_DMA_BASE                   (0xfffed800)
-#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
-#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
-#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
-#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
-#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
-#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
-#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
-#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
-#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
-#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
-#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
-#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
-#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
-#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
-#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
-#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
-#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
-#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
-#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
-#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
-
-/* Hardware registers for omap2 */
-#if defined(CONFIG_ARCH_OMAP3)
-#define OMAP_DMA4_BASE                  (L4_34XX_BASE + 0x56000)
-#else   /* CONFIG_ARCH_OMAP2 */
-#define OMAP_DMA4_BASE                  (L4_24XX_BASE + 0x56000)
-#endif
-
-#define OMAP_DMA4_REVISION              (OMAP_DMA4_BASE + 0x00)
-#define OMAP_DMA4_GCR_REG               (OMAP_DMA4_BASE + 0x78)
-#define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
-#define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
-#define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
-#define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)
-#define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
-#define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
-#define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
-#define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)
-#define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)
-#define OMAP_DMA4_OCP_SYSCONFIG         (OMAP_DMA4_BASE + 0x2c)
-#define OMAP_DMA4_CAPS_0                (OMAP_DMA4_BASE + 0x64)
-#define OMAP_DMA4_CAPS_2                (OMAP_DMA4_BASE + 0x6c)
-#define OMAP_DMA4_CAPS_3                (OMAP_DMA4_BASE + 0x70)
-#define OMAP_DMA4_CAPS_4                (OMAP_DMA4_BASE + 0x74)
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OMAP_LOGICAL_DMA_CH_COUNT       17
+#define OMAP1_DMA_BASE                  (0xfffed800)
+
+#define OMAP1_DMA_GCR                   0x400
+#define OMAP1_DMA_GSCR                  0x404
+#define OMAP1_DMA_GRST                  0x408
+#define OMAP1_DMA_HW_ID                 0x442
+#define OMAP1_DMA_PCH2_ID               0x444
+#define OMAP1_DMA_PCH0_ID               0x446
+#define OMAP1_DMA_PCH1_ID               0x448
+#define OMAP1_DMA_PCHG_ID               0x44a
+#define OMAP1_DMA_PCHD_ID               0x44c
+#define OMAP1_DMA_CAPS_0_U              0x44e
+#define OMAP1_DMA_CAPS_0_L              0x450
+#define OMAP1_DMA_CAPS_1_U              0x452
+#define OMAP1_DMA_CAPS_1_L              0x454
+#define OMAP1_DMA_CAPS_2                0x456
+#define OMAP1_DMA_CAPS_3                0x458
+#define OMAP1_DMA_CAPS_4                0x45a
+#define OMAP1_DMA_PCH2_SR               0x460
+#define OMAP1_DMA_PCH0_SR               0x480
+#define OMAP1_DMA_PCH1_SR               0x482
+#define OMAP1_DMA_PCHD_SR               0x4c0
+
+/* Hardware registers for omap2 and omap3 */
+#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
+#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
+
+#define OMAP_DMA4_REVISION              0x00
+#define OMAP_DMA4_GCR                   0x78
+#define OMAP_DMA4_IRQSTATUS_L0          0x08
+#define OMAP_DMA4_IRQSTATUS_L1          0x0c
+#define OMAP_DMA4_IRQSTATUS_L2          0x10
+#define OMAP_DMA4_IRQSTATUS_L3          0x14
+#define OMAP_DMA4_IRQENABLE_L0          0x18
+#define OMAP_DMA4_IRQENABLE_L1          0x1c
+#define OMAP_DMA4_IRQENABLE_L2          0x20
+#define OMAP_DMA4_IRQENABLE_L3          0x24
+#define OMAP_DMA4_SYSSTATUS             0x28
+#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
+#define OMAP_DMA4_CAPS_0                0x64
+#define OMAP_DMA4_CAPS_2                0x6c
+#define OMAP_DMA4_CAPS_3                0x70
+#define OMAP_DMA4_CAPS_4                0x74
+
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
 
 /* Common channel specific registers for omap1 */
-#define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
-#define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
-#define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
-#define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
-#define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
-#define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
-#define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
-#define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
-#define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
-#define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
-#define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
-#define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
-
-#else
-
-#define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
+#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
+#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
+#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
+#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
+#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
+#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
+#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
+#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
+#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
+#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
+#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
+#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
+#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
+#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
 
 /* Common channel specific registers for omap2 */
-#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
-#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
-#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
-#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
-#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
-#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
-#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
-#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
-#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
-#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
-#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
-#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
-
-#endif
+#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
+#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
+#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
+#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
+#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
+#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
+#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
+#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
+#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
+#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
+#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
+#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
+#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
 
 /* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
-#define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
-#define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
-#define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
+#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
+#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
+#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
+#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
+#define OMAP1_DMA_CCEN(n)               0
+#define OMAP1_DMA_CCFN(n)               0
 
 /* Channel specific registers only on omap2 */
-#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
-#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
-#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
-#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
-#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
+#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
+#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
+#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
+#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
+#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
+
+/* Dummy defines to keep multi-omap compiles happy */
+#define OMAP1_DMA_REVISION              0
+#define OMAP1_DMA_IRQSTATUS_L0          0
+#define OMAP1_DMA_IRQENABLE_L0          0
+#define OMAP1_DMA_OCP_SYSCONFIG         0
+#define OMAP_DMA4_HW_ID                 0
+#define OMAP_DMA4_CAPS_0_L              0
+#define OMAP_DMA4_CAPS_0_U              0
+#define OMAP_DMA4_CAPS_1_L              0
+#define OMAP_DMA4_CAPS_1_U              0
+#define OMAP_DMA4_GSCR                  0
+#define OMAP_DMA4_CPC(n)                0
+
+#define OMAP_DMA4_LCH_CTRL(n)           0
+#define OMAP_DMA4_COLOR_L(n)            0
+#define OMAP_DMA4_COLOR_U(n)            0
+#define OMAP_DMA4_CCR2(n)               0
+#define OMAP1_DMA_CSSA(n)               0
+#define OMAP1_DMA_CDSA(n)               0
+#define OMAP_DMA4_CSSA_L(n)             0
+#define OMAP_DMA4_CSSA_U(n)             0
+#define OMAP_DMA4_CDSA_L(n)             0
+#define OMAP_DMA4_CDSA_U(n)             0
 
 /*----------------------------------------------------------------------------*/
 
@@ -196,63 +216,98 @@
 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP24XX_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
 #define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP24XX_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP24XX_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP24XX_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP24XX_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP24XX_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP24XX_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP24XX_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP24XX_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
+#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
+#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
+#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
+#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
+#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
+#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
+#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
+#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
+#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
+#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
+#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
+#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
+#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
+#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
+#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
+#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
+#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
+#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* SDMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* SDMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* SDMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* SDMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* SDMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* SDMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* SDMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* SDMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* SDMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* SDMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* SDMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* SDMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* SDMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* SDMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* SDMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* SDMA_45 */
-
-#define OMAP24XX_DMA_UART1_TX           49      /* SDMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* SDMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* SDMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* SDMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* SDMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* SDMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* SDMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* SDMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* SDMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* SDMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* SDMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* SDMA_59 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
-#define OMAP24XX_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
+#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
+#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
+#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
+#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
+#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
+#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
+#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
+#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
+#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
+#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
+#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
 /*----------------------------------------------------------------------------*/
 
@@ -358,6 +413,11 @@ enum omap_dma_burst_mode {
         OMAP_DMA_DATA_BURST_16,
 };
 
+enum end_type {
+        OMAP_DMA_LITTLE_ENDIAN = 0,
+        OMAP_DMA_BIG_ENDIAN
+};
+
 enum omap_dma_color_mode {
         OMAP_DMA_COLOR_DIS = 0,
         OMAP_DMA_CONSTANT_FILL,
@@ -370,24 +430,34 @@ enum omap_dma_write_mode {
         OMAP_DMA_WRITE_LAST_NON_POSTED
 };
 
+enum omap_dma_channel_mode {
+        OMAP_DMA_LCH_2D = 0,
+        OMAP_DMA_LCH_G,
+        OMAP_DMA_LCH_P,
+        OMAP_DMA_LCH_PD
+};
+
 struct omap_dma_channel_params {
         int data_type;          /* data type 8,16,32 */
         int elem_count;         /* number of elements in a frame */
         int frame_count;        /* number of frames in a element */
 
         int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int src_amode;          /* constant , post increment, indexed , double indexed */
+        int src_amode;          /* constant, post increment, indexed,
+                                        double indexed */
         unsigned long src_start;        /* source address : physical */
         int src_ei;             /* source element index */
         int src_fi;             /* source frame index */
 
         int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int dst_amode;          /* constant , post increment, indexed , double indexed */
+        int dst_amode;          /* constant, post increment, indexed,
+                                        double indexed */
         unsigned long dst_start;        /* source address : physical */
         int dst_ei;             /* source element index */
         int dst_fi;             /* source frame index */
 
-        int trigger;            /* trigger attached if the channel is synchronized */
+        int trigger;            /* trigger attached if the channel is
+                                        synchronized */
         int sync_mode;          /* sycn on element, frame , block or packet */
         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 
@@ -404,8 +474,8 @@ struct omap_dma_channel_params {
 
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
-                            void (* callback)(int lch, u16 ch_status, void *data),
-                            void *data, int *dma_ch);
+                        void (*callback)(int lch, u16 ch_status, void *data),
+                        void *data, int *dma_ch);
 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 extern void omap_free_dma(int ch);
@@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                     u32 color);
 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                                     unsigned long src_start,
@@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch,
                                          enum omap_dma_burst_mode burst_mode);
 
 extern void omap_set_dma_params(int lch,
-                                struct omap_dma_channel_params * params);
+                                struct omap_dma_channel_params *params);
 
-extern void omap_dma_link_lch (int lch_head, int lch_queue);
-extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
+extern void omap_dma_link_lch(int lch_head, int lch_queue);
+extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
 
 extern int omap_set_dma_callback(int lch,
-                        void (* callback)(int lch, u16 ch_status, void *data),
+                        void (*callback)(int lch, u16 ch_status, void *data),
                         void *data);
 extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
-extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
+extern int omap_get_dma_active_status(int lch);
 extern int omap_dma_running(void);
 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
                                        int tparams);
 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                                  unsigned char write_prio);
+extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
+extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
+extern int omap_get_dma_index(int lch, int *ei, int *fi);
 
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
@@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id);
 #endif
 
 /* LCD DMA functions */
-extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
                                 void *data);
 extern void omap_free_lcd_dma(void);
 extern void omap_setup_lcd_dma(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index fefb276ed402..02b29e8437ae 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer);
 
 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 6a883e0bdbb8..f420881d2a3b 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
 #define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
 
 /* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_IH_FPGA_BASE           IH_BOARD_BASE
-#define OMAP1510_INT_FPGA_ATN           (OMAP1510_IH_FPGA_BASE + 0)
-#define OMAP1510_INT_FPGA_ACK           (OMAP1510_IH_FPGA_BASE + 1)
-#define OMAP1510_INT_FPGA2              (OMAP1510_IH_FPGA_BASE + 2)
-#define OMAP1510_INT_FPGA3              (OMAP1510_IH_FPGA_BASE + 3)
-#define OMAP1510_INT_FPGA4              (OMAP1510_IH_FPGA_BASE + 4)
-#define OMAP1510_INT_FPGA5              (OMAP1510_IH_FPGA_BASE + 5)
-#define OMAP1510_INT_FPGA6              (OMAP1510_IH_FPGA_BASE + 6)
-#define OMAP1510_INT_FPGA7              (OMAP1510_IH_FPGA_BASE + 7)
-#define OMAP1510_INT_FPGA8              (OMAP1510_IH_FPGA_BASE + 8)
-#define OMAP1510_INT_FPGA9              (OMAP1510_IH_FPGA_BASE + 9)
-#define OMAP1510_INT_FPGA10             (OMAP1510_IH_FPGA_BASE + 10)
-#define OMAP1510_INT_FPGA11             (OMAP1510_IH_FPGA_BASE + 11)
-#define OMAP1510_INT_FPGA12             (OMAP1510_IH_FPGA_BASE + 12)
-#define OMAP1510_INT_ETHER              (OMAP1510_IH_FPGA_BASE + 13)
-#define OMAP1510_INT_FPGAUART1          (OMAP1510_IH_FPGA_BASE + 14)
-#define OMAP1510_INT_FPGAUART2          (OMAP1510_IH_FPGA_BASE + 15)
-#define OMAP1510_INT_FPGA_TS            (OMAP1510_IH_FPGA_BASE + 16)
-#define OMAP1510_INT_FPGA17             (OMAP1510_IH_FPGA_BASE + 17)
-#define OMAP1510_INT_FPGA_CAM           (OMAP1510_IH_FPGA_BASE + 18)
-#define OMAP1510_INT_FPGA_RTC_A         (OMAP1510_IH_FPGA_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_B         (OMAP1510_IH_FPGA_BASE + 20)
-#define OMAP1510_INT_FPGA_CD            (OMAP1510_IH_FPGA_BASE + 21)
-#define OMAP1510_INT_FPGA22             (OMAP1510_IH_FPGA_BASE + 22)
-#define OMAP1510_INT_FPGA23             (OMAP1510_IH_FPGA_BASE + 23)
+#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
 
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 91d85b3417b7..45fdfccbd5d4 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -284,6 +284,7 @@
 #include "omap1510.h"
 #include "omap24xx.h"
 #include "omap16xx.h"
+#include "omap34xx.h"
 
 #ifndef __ASSEMBLER__
 
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 160578e1f557..0b13557fd30b 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -60,6 +60,7 @@
 #define IO_SIZE         0x40000
 #define IO_VIRT         (IO_PHYS - IO_OFFSET)
 #define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
+#define OMAP1_IO_ADDRESS(pa)    ((pa) - IO_OFFSET)
 #define io_p2v(pa)      ((pa) - IO_OFFSET)
 #define io_v2p(va)      ((va) + IO_OFFSET)
 
@@ -91,6 +92,7 @@
 
 #define IO_OFFSET       0x90000000
 #define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
 
@@ -148,6 +150,7 @@
 
 #define IO_OFFSET               0x90000000
 #define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 #define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 #define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
 
@@ -183,35 +186,12 @@
 #define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
 #define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
 
-/* 16 bit uses LDRH/STRH, base +/- offset_8 */
-typedef struct { volatile u16 offset[256]; } __regbase16;
-#define __REGV16(vaddr)         ((__regbase16 *)((vaddr)&~0xff)) \
-                                        ->offset[((vaddr)&0xff)>>1]
-#define __REG16(paddr)          __REGV16(io_p2v(paddr))
-
-/* 8/32 bit uses LDR/STR, base +/- offset_12 */
-typedef struct { volatile u8 offset[4096]; } __regbase8;
-#define __REGV8(vaddr)          ((__regbase8  *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>0]
-#define __REG8(paddr)           __REGV8(io_p2v(paddr))
-
-typedef struct { volatile u32 offset[4096]; } __regbase32;
-#define __REGV32(vaddr)         ((__regbase32 *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>2]
-#define __REG32(paddr)          __REGV32(io_p2v(paddr))
-
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
 extern void omap2_init_common_hw(void);
 
-#else
-
-#define __REG8(paddr)           io_p2v(paddr)
-#define __REG16(paddr)          io_p2v(paddr)
-#define __REG32(paddr)          io_p2v(paddr)
-
 #endif
 
 #endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 87973654e625..7464c694859b 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -285,7 +285,41 @@
 #define OMAP_MAX_GPIO_LINES     192
 #define IH_GPIO_BASE            (128 + IH2_BASE)
 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define IH_BOARD_BASE           (16 + IH_MPUIO_BASE)
+#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
+
+/* External FPGA handles interrupts on Innovator boards */
+#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef  CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS       24
+#else
+#define OMAP_FPGA_NR_IRQS       0
+#endif
+#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+
+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
+#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef  CONFIG_TWL4030_CORE
+#define TWL4030_BASE_NR_IRQS    8
+#define TWL4030_PWR_NR_IRQS     8
+#else
+#define TWL4030_BASE_NR_IRQS    0
+#define TWL4030_PWR_NR_IRQS     0
+#endif
+#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
+#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
+#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
+
+/* External TWL4030 gpio interrupts are optional */
+#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
+#ifdef  CONFIG_TWL4030_GPIO
+#define TWL4030_GPIO_NR_IRQS    18
+#else
+#define TWL4030_GPIO_NR_IRQS    0
+#endif
+#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
+
+/* Total number of interrupts depends on the enabled blocks above */
+#define NR_IRQS                 TWL4030_GPIO_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
@@ -293,14 +327,6 @@
 extern void omap_init_irq(void);
 #endif
 
-/*
- * The definition of NR_IRQS is in board-specific header file, which is
- * included via hardware.h
- */
 #include <asm/hardware.h>
 
-#ifndef NR_IRQS
-#define NR_IRQS                 IH_BOARD_BASE
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index c7a0cc1c4e93..26c78f67dc8e 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,11 @@
 #ifndef __ASM_ARCH_OMAP_MCBSP_H
 #define __ASM_ARCH_OMAP_MCBSP_H
 
+#include <linux/completion.h>
+#include <linux/spinlock.h>
+
 #include <asm/hardware.h>
+#include <asm/arch/clock.h>
 
 #define OMAP730_MCBSP1_BASE     0xfffb1000
 #define OMAP730_MCBSP2_BASE     0xfffb1800
@@ -40,6 +44,9 @@
 #define OMAP24XX_MCBSP1_BASE    0x48074000
 #define OMAP24XX_MCBSP2_BASE    0x48076000
 
+#define OMAP34XX_MCBSP1_BASE    0x48074000
+#define OMAP34XX_MCBSP2_BASE    0x49022000
+
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -74,7 +81,8 @@
 #define OMAP_MCBSP_REG_XCERG    0x3A
 #define OMAP_MCBSP_REG_XCERH    0x3C
 
-#define OMAP_MAX_MCBSP_COUNT 3
+#define OMAP_MAX_MCBSP_COUNT    3
+#define MAX_MCBSP_CLOCKS        3
 
 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
@@ -117,7 +125,8 @@
 #define OMAP_MCBSP_REG_XCERG    0x74
 #define OMAP_MCBSP_REG_XCERH    0x78
 
-#define OMAP_MAX_MCBSP_COUNT 2
+#define OMAP_MAX_MCBSP_COUNT    2
+#define MAX_MCBSP_CLOCKS        2
 
 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg {
         omap_mcbsp_word_length          word_length;
 };
 
+/* Platform specific configuration */
+struct omap_mcbsp_ops {
+        void (*request)(unsigned int);
+        void (*free)(unsigned int);
+        int (*check)(unsigned int);
+};
+
+struct omap_mcbsp_platform_data {
+        u32 virt_base;
+        u8 dma_rx_sync, dma_tx_sync;
+        u16 rx_irq, tx_irq;
+        struct omap_mcbsp_ops *ops;
+        char const *clk_name;
+};
+
+struct omap_mcbsp {
+        struct device *dev;
+        u32 io_base;
+        u8 id;
+        u8 free;
+        omap_mcbsp_word_length rx_word_length;
+        omap_mcbsp_word_length tx_word_length;
+
+        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
+        /* IRQ based TX/RX */
+        int rx_irq;
+        int tx_irq;
+
+        /* DMA stuff */
+        u8 dma_rx_sync;
+        short dma_rx_lch;
+        u8 dma_tx_sync;
+        short dma_tx_lch;
+
+        /* Completion queues */
+        struct completion tx_irq_completion;
+        struct completion rx_irq_completion;
+        struct completion tx_dma_completion;
+        struct completion rx_dma_completion;
+
+        /* Protect the field .free, while checking if the mcbsp is in use */
+        spinlock_t lock;
+        struct omap_mcbsp_platform_data *pdata;
+        struct clk *clk;
+};
+
+int omap_mcbsp_init(void);
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
new file mode 100644
index 000000000000..aa30c6d10abd
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -0,0 +1,72 @@
+/*
+ * include/asm-arm/arch-omap/omap34xx.h
+ *
+ * This file contains the processor specific definitions of the TI OMAP34XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_OMAP34XX_H
+#define __ASM_ARCH_OMAP34XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+
+#define L4_34XX_BASE            0x48000000
+#define L4_WK_34XX_BASE         0x48300000
+#define L4_WK_OMAP_BASE         L4_WK_34XX_BASE
+#define L4_PER_34XX_BASE        0x49000000
+#define L4_PER_OMAP_BASE        L4_PER_34XX_BASE
+#define L4_EMU_34XX_BASE        0x54000000
+#define L4_EMU_BASE             L4_EMU_34XX_BASE
+#define L3_34XX_BASE            0x68000000
+#define L3_OMAP_BASE            L3_34XX_BASE
+
+#define OMAP3430_32KSYNCT_BASE  0x48320000
+#define OMAP3430_CM_BASE        0x48004800
+#define OMAP3430_PRM_BASE       0x48306800
+#define OMAP343X_SMS_BASE       0x6C000000
+#define OMAP343X_SDRC_BASE      0x6D000000
+#define OMAP34XX_GPMC_BASE      0x6E000000
+#define OMAP343X_SCM_BASE       0x48002000
+#define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
+
+#define OMAP34XX_IC_BASE        0x48200000
+#define OMAP34XX_IVA_INTC_BASE  0x40000000
+#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
+#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+
+
+#if defined(CONFIG_ARCH_OMAP3430)
+
+#define OMAP2_32KSYNCT_BASE             OMAP3430_32KSYNCT_BASE
+#define OMAP2_CM_BASE                   OMAP3430_CM_BASE
+#define OMAP2_PRM_BASE                  OMAP3430_PRM_BASE
+#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
+
+#endif
+
+#define OMAP34XX_DSP_BASE       0x58000000
+#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
+#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
+#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
+#endif /* __ASM_ARCH_OMAP34XX_H */
+
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
 
+extern int __init omap_sram_init(void);
 extern void * omap_sram_push(void * start, unsigned long size);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
 /* Do not use these */
-extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long sram_reprogram_clock_sz;
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap1_sram_reprogram_clock_sz;
 
-extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                          u32 base_cs, u32 force_unlock);
-extern unsigned long sram_ddr_init_sz;
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
 
-extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-extern unsigned long sram_set_prcm_sz;
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
 
-extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type);
-extern unsigned long sram_reprogram_sdrc_sz;
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+
+
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
 #endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
index 8ded218cbea5..65a9c82d3bf7 100644
--- a/include/asm-arm/arch-omap/tc.h
+++ b/include/asm-arm/arch-omap/tc.h
@@ -75,16 +75,14 @@
 #ifndef __ASSEMBLER__
 
 /* EMIF Slow Interface Configuration Register */
-#define OMAP_EMIFS_CONFIG_REG   __REG32(EMIFS_CONFIG)
-
 #define OMAP_EMIFS_CONFIG_FR            (1 << 4)
 #define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
 #define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
 #define OMAP_EMIFS_CONFIG_BM            (1 << 1)
 #define OMAP_EMIFS_CONFIG_WP            (1 << 0)
 
-#define EMIFS_CCS(n)            __REG32(EMIFS_CS0_CONFIG + (4 * (n)))
-#define EMIFS_ACS(n)            __REG32(EMIFS_ACS0 + (4 * (n)))
+#define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
+#define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
 
 /* Almost all documentation for chip and board memory maps assumes
  * BM is clear.  Most devel boards have a switch to control booting
@@ -93,13 +91,13 @@
  */
 static inline u32 omap_cs0_phys(void)
 {
-        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
                         ?  OMAP_CS3_PHYS : 0;
 }
 
 static inline u32 omap_cs3_phys(void)
 {
-        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
                         ? 0 : OMAP_CS3_PHYS;
 }
 
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 2147d18aaeae..ddf1861e6df9 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -34,11 +34,8 @@
 /*
  * OTG and transceiver registers, for OMAPs starting with ARM926
  */
-#define OTG_REG32(offset)               __REG32(OTG_BASE + (offset))
-#define OTG_REG16(offset)               __REG16(OTG_BASE + (offset))
-
-#define OTG_REV_REG                     OTG_REG32(0x00)
-#define OTG_SYSCON_1_REG                OTG_REG32(0x04)
+#define OTG_REV                         (OTG_BASE + 0x00)
+#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
@@ -47,7 +44,7 @@
 #       define   DEV_IDLE_EN            (1 << 13)
 #       define   OTG_RESET_DONE         (1 << 2)
 #       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2_REG                OTG_REG32(0x08)
+#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
 #       define   OTG_EN                 (1 << 31)
 #       define   USBX_SYNCHRO           (1 << 30)
 #       define   OTG_MST16              (1 << 29)
@@ -65,7 +62,7 @@
 #       define   HMC_TLLSPEED           (1 << 7)
 #       define   HMC_TLLATTACH          (1 << 6)
 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL_REG                    OTG_REG32(0x0c)
+#define OTG_CTRL                        (OTG_BASE + 0x0c)
 #       define   OTG_USB2_EN            (1 << 29)
 #       define   OTG_USB2_DP            (1 << 28)
 #       define   OTG_USB2_DM            (1 << 27)
@@ -92,7 +89,7 @@
 #       define   OTG_PD_VBUS            (1 << 2)
 #       define   OTG_PU_VBUS            (1 << 1)
 #       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN_REG                  OTG_REG16(0x10)
+#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 #       define   DRIVER_SWITCH          (1 << 15)
 #       define   A_VBUS_ERR             (1 << 13)
 #       define   A_REQ_TMROUT           (1 << 12)
@@ -102,9 +99,9 @@
 #       define   B_SRP_DONE             (1 << 8)
 #       define   B_SRP_STARTED          (1 << 7)
 #       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC_REG                 OTG_REG16(0x14)
+#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
         // same bits as in IRQ_EN
-#define OTG_OUTCTRL_REG                 OTG_REG16(0x18)
+#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 #       define   OTGVPD                 (1 << 14)
 #       define   OTGVPU                 (1 << 13)
 #       define   OTGPUID                (1 << 12)
@@ -117,13 +114,13 @@
 #       define   USB0VDR                (1 << 2)
 #       define   USB0PDEN               (1 << 1)
 #       define   USB0PUEN               (1 << 0)
-#define OTG_TEST_REG                    OTG_REG16(0x20)
-#define OTG_VENDOR_CODE_REG             OTG_REG32(0xfc)
+#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
+#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 
 /*-------------------------------------------------------------------------*/
 
 /* OMAP1 */
-#define USB_TRANSCEIVER_CTRL_REG        __REG32(0xfffe1000 + 0x0064)
+#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 #       define  CONF_USB2_UNI_R         (1 << 8)
 #       define  CONF_USB1_UNI_R         (1 << 7)
 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
index 50f8c8802206..59f1bc96a23b 100644
--- a/include/asm-arm/arch-orion5x/io.h
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -14,7 +14,6 @@
 #include "orion5x.h"
 
 #define IO_SPACE_LIMIT          0xffffffff
-#define IO_SPACE_REMAP          ORION5X_PCI_SYS_IO_BASE
 
 static inline void __iomem *
 __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
@@ -53,15 +52,12 @@ static inline void __iomem *__io(unsigned long addr)
 /*****************************************************************************
  * Helpers to access Orion registers
  ****************************************************************************/
-#define orion5x_read(r)         __raw_readl(r)
-#define orion5x_write(r, val)   __raw_writel(val, r)
-
 /*
  * These are not preempt-safe.  Locks, if needed, must be taken
  * care of by the caller.
  */
-#define orion5x_setbits(r, mask)        orion5x_write((r), orion5x_read(r) | (mask))
-#define orion5x_clrbits(r, mask)        orion5x_write((r), orion5x_read(r) & ~(mask))
+#define orion5x_setbits(r, mask)        writel(readl(r) | (mask), (r))
+#define orion5x_clrbits(r, mask)        writel(readl(r) & ~(mask), (r))
 
 
 #endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
index 206ddd71e193..10257f5c5e9e 100644
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -2,7 +2,7 @@
  * include/asm-arm/arch-orion5x/orion5x.h
  *
  * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
@@ -63,9 +63,11 @@
 /*******************************************************************************
  * Supported Devices & Revisions
  ******************************************************************************/
-/* Orion-1 (88F5181) */
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
 #define MV88F5181_DEV_ID        0x5181
 #define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
 /* Orion-NAS (88F5182) */
 #define MV88F5182_DEV_ID        0x5182
 #define MV88F5182_REV_A2        2
@@ -152,6 +154,7 @@
 #define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
 #define  BRIDGE_INT_TIMER0      0x0002
 #define  BRIDGE_INT_TIMER1      0x0004
+#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 #define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
 #define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
 
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 5c13d4fafb4e..7548cedf2d76 100644
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -8,23 +8,38 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/serial_reg.h>
 #include <asm/arch/orion5x.h>
 
-#define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
-#define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
-
-#define LSR_THRE        0x20
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
 
 static void putc(const char c)
 {
-        int j = 0x1000;
-        while (--j && !(*MV_UART_LSR & LSR_THRE))
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
                 barrier();
-        *MV_UART_THR = c;
+        }
+
+        base[UART_TX << 2] = c;
 }
 
 static void flush(void)
 {
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
 }
 
 /*
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
index 52bbe3bc25e1..f82f96dd1053 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -12,4 +12,6 @@ typedef struct {
         void *priv;
 } pxa2xx_audio_ops_t;
 
+extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
+
 #endif
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e25558faa5a4..d9af6dabc899 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -192,15 +192,6 @@ extern int pxa_gpio_get_value(unsigned gpio);
 extern void pxa_gpio_set_value(unsigned gpio, int value);
 
 /*
- * Routine to enable or disable CKEN
- */
-static inline void __deprecated pxa_set_cken(int clock, int enable)
-{
-        extern void __pxa_set_cken(int clock, int enable);
-        __pxa_set_cken(clock, enable);
-}
-
-/*
  * return current memory and LCD clock frequency in units of 10kHz
  */
 extern unsigned int get_memclk_frequency_10khz(void);
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 99f4f423a8e1..0a50c3c763df 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -16,4 +16,8 @@ struct pxaficp_platform_data {
 
 extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
 
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
+void pxa2xx_transceiver_mode(struct device *dev, int mode);
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c57..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
 
 
 /*
- * USB Device Controller
- * PXA25x and PXA27x USB device controller registers are different.
- */
-#if defined(CONFIG_PXA25x)
-
-#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
-#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
-#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
-
-#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
-#define UDCCR_UDE       (1 << 0)        /* UDC enable */
-#define UDCCR_UDA       (1 << 1)        /* UDC active */
-#define UDCCR_RSM       (1 << 2)        /* Device resume */
-#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
-#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
-#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
-#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
-#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
-
-#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
-#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
-#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
-#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
-#define UDCCS0_SST      (1 << 4)        /* Sent stall */
-#define UDCCS0_FST      (1 << 5)        /* Force stall */
-#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
-#define UDCCS0_SA       (1 << 7)        /* Setup active */
-
-/* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
-
-#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
-
-/* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
-
-#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
-
-/* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
-
-#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
-
-/* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
-
-#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
-#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
-
-/* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
-
-#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
-#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
-#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
-#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
-
-#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
-#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
-#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
-#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
-#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
-#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
-#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
-#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
-#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
-#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
-#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
-#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
-#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
-#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
-#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
-#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
-#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
-#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
-#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
-#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
-#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
-#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
-#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
-#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
-
-#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
-
-#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
-#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
-#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
-#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
-#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
-#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
-#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
-#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
-
-#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
-
-#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
-#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
-#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
-#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
-#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
-#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
-#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
-#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
-
-#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
-
-#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
-#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
-#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
-#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
-#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
-#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
-#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
-#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
-
-#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
-
-#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
-#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
-#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
-#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
-#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
-#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
-#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
-#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
-
-#elif defined(CONFIG_PXA27x)
-
-#define UDCCR           __REG(0x40600000) /* UDC Control Register */
-#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
-#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
-                                           Protocol Port Support */
-#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
-                                           Support */
-#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
-                                           Enable */
-#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
-#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
-#define UDCCR_ACN_S     11
-#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
-#define UDCCR_AIN_S     8
-#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
-                                           Setting Number */
-#define UDCCR_AAISN_S   5
-#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
-                                           Configuration */
-#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
-                                           Error */
-#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
-#define UDCCR_UDA       (1 << 1)        /* UDC Active */
-#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
-
-#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
-#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
-#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
-#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
-
-#define UDC_INT_FIFOERROR  (0x2)
-#define UDC_INT_PACKETCMP  (0x1)
-
-#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
-#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
-#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
-#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
-#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
-
-#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
-#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
-#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
-#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
-#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
-#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
-#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
-
-#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
-#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
-#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
-#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
-                                           Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
-                                           Falling Edge Interrupt Enable */
-#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
-                                           Edge Interrupt Enable */
-#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
-                                           Edge Interrupt Enable */
-#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
-                                           Interrupt Enable */
-
-#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
-
-#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
-#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
-#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
-#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
-#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
-#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
-#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
-#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
-#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
-#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
-#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
-#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
-#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
-#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
-
-#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
-#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
-#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
-#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
-#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
-#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
-#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
-#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
-#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
-#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
-
-#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
-
-#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
-#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
-#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
-#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
-#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
-#define UDCCSR_FST      (1 << 5)        /* Force STALL */
-#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
-#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
-#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
-#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
-#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
-
-#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
-#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
-#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
-#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
-#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
-#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
-#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
-#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
-#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
-#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
-#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
-#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
-#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
-#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
-#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
-#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
-#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
-#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
-#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
-#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
-#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
-#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
-#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
-#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
-#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
-
-#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
-#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
-#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
-#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
-#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
-#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
-#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
-#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
-#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
-#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
-#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
-#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
-#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
-#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
-#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
-#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
-#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
-#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
-#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
-#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
-#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
-#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
-#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
-#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
-#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
-#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
-#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
-
-#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
-#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
-#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
-#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
-#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
-#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
-#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
-#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
-#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
-#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
-#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
-#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
-#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
-#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
-#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
-#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
-#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
-#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
-#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
-#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
-#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
-#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
-#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
-#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
-
-#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
-#define UDCCONR_CN_S    (25)
-#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
-#define UDCCONR_IN_S    (22)
-#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
-#define UDCCONR_AISN_S  (19)
-#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
-#define UDCCONR_EN_S    (15)
-#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
-#define UDCCONR_ET_S    (13)
-#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
-#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
-#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
-#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
-#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
-#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
-#define UDCCONR_MPS_S   (2)
-#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
-#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
-
-
-#define UDC_INT_FIFOERROR  (0x2)
-#define UDC_INT_PACKETCMP  (0x1)
-
-#define UDC_FNR_MASK     (0x7ff)
-
-#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
-#define UDC_BCR_MASK    (0x3ff)
-#endif
-
-/*
  * Fast Infrared Communication Port
  */
 
@@ -1237,120 +825,9 @@
 #endif
 
 /*
- * Power Manager
+ * Power Manager - see pxa2xx-regs.h
  */
 
-#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
-#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
-#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
-#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
-#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
-#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
-
-#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
-#define PSTR            __REG(0x40F00038)       /*Power Manager Standby Config Register */
-#define PSNR            __REG(0x40F0003C)       /*Power Manager Sense Config Register */
-#define PVCR            __REG(0x40F00040)       /*Power Manager VoltageControl Register */
-#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
-#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG2(0x40F00080, (x)<<2)
-#define PCMD0   __REG(0x40F00080 + 0 * 4)
-#define PCMD1   __REG(0x40F00080 + 1 * 4)
-#define PCMD2   __REG(0x40F00080 + 2 * 4)
-#define PCMD3   __REG(0x40F00080 + 3 * 4)
-#define PCMD4   __REG(0x40F00080 + 4 * 4)
-#define PCMD5   __REG(0x40F00080 + 5 * 4)
-#define PCMD6   __REG(0x40F00080 + 6 * 4)
-#define PCMD7   __REG(0x40F00080 + 7 * 4)
-#define PCMD8   __REG(0x40F00080 + 8 * 4)
-#define PCMD9   __REG(0x40F00080 + 9 * 4)
-#define PCMD10  __REG(0x40F00080 + 10 * 4)
-#define PCMD11  __REG(0x40F00080 + 11 * 4)
-#define PCMD12  __REG(0x40F00080 + 12 * 4)
-#define PCMD13  __REG(0x40F00080 + 13 * 4)
-#define PCMD14  __REG(0x40F00080 + 14 * 4)
-#define PCMD15  __REG(0x40F00080 + 15 * 4)
-#define PCMD16  __REG(0x40F00080 + 16 * 4)
-#define PCMD17  __REG(0x40F00080 + 17 * 4)
-#define PCMD18  __REG(0x40F00080 + 18 * 4)
-#define PCMD19  __REG(0x40F00080 + 19 * 4)
-#define PCMD20  __REG(0x40F00080 + 20 * 4)
-#define PCMD21  __REG(0x40F00080 + 21 * 4)
-#define PCMD22  __REG(0x40F00080 + 22 * 4)
-#define PCMD23  __REG(0x40F00080 + 23 * 4)
-#define PCMD24  __REG(0x40F00080 + 24 * 4)
-#define PCMD25  __REG(0x40F00080 + 25 * 4)
-#define PCMD26  __REG(0x40F00080 + 26 * 4)
-#define PCMD27  __REG(0x40F00080 + 27 * 4)
-#define PCMD28  __REG(0x40F00080 + 28 * 4)
-#define PCMD29  __REG(0x40F00080 + 29 * 4)
-#define PCMD30  __REG(0x40F00080 + 30 * 4)
-#define PCMD31  __REG(0x40F00080 + 31 * 4)
-
-#define PCMD_MBC        (1<<12)
-#define PCMD_DCE        (1<<11)
-#define PCMD_LC (1<<10)
-/* FIXME:  PCMD_SQC need be checked.   */
-#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
-                                   bit 9 should be 0 all day. */
-#define PVCR_VCSA       (0x1<<14)
-#define PVCR_CommandDelay (0xf80)
-#define PCFR_PI2C_EN    (0x1 << 6)
-
-#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
-#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
-#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
-#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
-#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
-#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
-#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
-
-#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
-
-#define PCFR_RO         (1 << 15)       /* RDH Override */
-#define PCFR_PO         (1 << 14)       /* PH Override */
-#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
-#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
-#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
-#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
-#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
-#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
-#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
-#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
-#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
-#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
-
-#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
-#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
-#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
-#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
-
-#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
-#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
-#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
-#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
-#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
-#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
-#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
-#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
-#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
-#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
-#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
-#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
-#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
-#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
-#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
-#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
-#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
-#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
-
 /*
  * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
  */
@@ -1360,52 +837,9 @@
  */
 
 /*
- * Core Clock
+ * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
  */
 
-#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
-#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
-#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
-#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
-
-#define CCCR_N_MASK     0x0380          /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define CCCR_M_MASK     0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
-#define CCCR_L_MASK     0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
-#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
-#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
-#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
-#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
-#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
-#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
-#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
-#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
-#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
-#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
-#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
-#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
-#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
-#define CKEN_USB        (11)    /* USB Unit Clock Enable */
-#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
-#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
-#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
-#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
-#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
-#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
-#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
-#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
-#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
-#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
-#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
-#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
-#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
-#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
-#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
-
-#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
-
 #ifdef CONFIG_PXA27x
 
 /* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 000000000000..840305916b6d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
+#ifndef _ASM_ARCH_PXA25X_UDC_H
+#define _ASM_ARCH_PXA25X_UDC_H
+
+#ifdef _ASM_ARCH_PXA27X_UDC_H
+#error You can't include both PXA25x and PXA27x UDC support
+#endif
+
+#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
+#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
+#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
+
+#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
+#define UDCCR_UDE       (1 << 0)        /* UDC enable */
+#define UDCCR_UDA       (1 << 1)        /* UDC active */
+#define UDCCR_RSM       (1 << 2)        /* Device resume */
+#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
+#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
+#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
+#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
+
+#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
+#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
+#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
+#define UDCCS0_SST      (1 << 4)        /* Sent stall */
+#define UDCCS0_FST      (1 << 5)        /* Force stall */
+#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
+#define UDCCS0_SA       (1 << 7)        /* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
+#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
+#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
+#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
+#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
+
+#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
+#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
+#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
+#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
+#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
+#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
+#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
+#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
+#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
+#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
+#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
+#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
+#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
+#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
+#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
+#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
+#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
+#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
+#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
+#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
+#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
+#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
+#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
+#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
+
+#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
+#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
+#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
+#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
+#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
+#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
+#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
+#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
+
+#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
+#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
+#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
+#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
+#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
+#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
+#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
+#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
+
+#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
+#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
+#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
+#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
+#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
+#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
+#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
+#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
+
+#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
+#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
+#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
+#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
+#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
+#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
+#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
+#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 000000000000..bc1cf7d0773a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,257 @@
+#ifndef _ASM_ARCH_PXA27X_UDC_H
+#define _ASM_ARCH_PXA27X_UDC_H
+
+#ifdef _ASM_ARCH_PXA25X_UDC_H
+#error You cannot include both PXA25x and PXA27x UDC support
+#endif
+
+#define UDCCR           __REG(0x40600000) /* UDC Control Register */
+#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
+#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
+                                           Protocol Port Support */
+#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
+                                           Support */
+#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
+                                           Enable */
+#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
+#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
+#define UDCCR_ACN_S     11
+#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
+#define UDCCR_AIN_S     8
+#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
+                                           Setting Number */
+#define UDCCR_AAISN_S   5
+#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
+                                           Configuration */
+#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
+                                           Error */
+#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
+#define UDCCR_UDA       (1 << 1)        /* UDC Active */
+#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
+
+#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
+#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
+
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+
+#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
+#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
+#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
+#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
+#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
+
+#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
+#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
+
+#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
+#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
+                                           Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
+                                           Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
+                                           Interrupt Enable */
+
+#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
+#define UP3OCR            __REG(0x40600024)  /* USB Port 2 Output Control register */
+
+#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
+#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
+#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
+
+#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
+#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
+#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
+#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
+#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
+#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
+#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
+#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
+#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
+
+#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+
+#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
+#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
+#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
+#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST      (1 << 5)        /* Force STALL */
+#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
+#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
+#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
+#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
+#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
+
+#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
+#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
+#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
+#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
+#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
+#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
+#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
+#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
+#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
+#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
+#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
+#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
+#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
+#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
+#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
+#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
+#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
+#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
+#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
+#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
+#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
+#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
+#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
+#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
+#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
+
+#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
+#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
+#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
+#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
+#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
+#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
+#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
+#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
+#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
+#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
+#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
+#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
+#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
+#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
+#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
+#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
+#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
+#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
+#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
+#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
+#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
+#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
+#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
+#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
+#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
+#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
+#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
+
+#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
+#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
+#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
+#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
+#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
+#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
+#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
+#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
+#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
+#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
+#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
+#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
+#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
+#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
+#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
+#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
+#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
+#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
+#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
+#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
+#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
+#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
+#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
+#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
+
+#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
+#define UDCCONR_CN_S    (25)
+#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
+#define UDCCONR_IN_S    (22)
+#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
+#define UDCCONR_AISN_S  (19)
+#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
+#define UDCCONR_EN_S    (15)
+#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
+#define UDCCONR_ET_S    (13)
+#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
+#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
+#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
+#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
+#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
+#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
+#define UDCCONR_MPS_S   (2)
+#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
+#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
+
+
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+
+#define UDC_FNR_MASK     (0x7ff)
+
+#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK    (0x3ff)
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
index b81cd63cb2eb..6ef1dd09970b 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_PXA2XX_GPIO_H
 #define __ASM_ARCH_PXA2XX_GPIO_H
 
+#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
+
 /* GPIO alternate function assignments */
 
 #define GPIO1_RST               1       /* reset */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
index 9553b54fa5bc..73e0a329cf7f 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -81,4 +81,166 @@
 
 #endif
 
+
+/*
+ * Power Manager
+ */
+
+#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
+#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
+#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
+#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
+#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
+#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
+
+#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
+#define PSTR            __REG(0x40F00038)       /* Power Manager Standby Config Register */
+#define PSNR            __REG(0x40F0003C)       /* Power Manager Sense Config Register */
+#define PVCR            __REG(0x40F00040)       /* Power Manager VoltageControl Register */
+#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
+#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
+#define PCMD(x) __REG2(0x40F00080, (x)<<2)
+#define PCMD0   __REG(0x40F00080 + 0 * 4)
+#define PCMD1   __REG(0x40F00080 + 1 * 4)
+#define PCMD2   __REG(0x40F00080 + 2 * 4)
+#define PCMD3   __REG(0x40F00080 + 3 * 4)
+#define PCMD4   __REG(0x40F00080 + 4 * 4)
+#define PCMD5   __REG(0x40F00080 + 5 * 4)
+#define PCMD6   __REG(0x40F00080 + 6 * 4)
+#define PCMD7   __REG(0x40F00080 + 7 * 4)
+#define PCMD8   __REG(0x40F00080 + 8 * 4)
+#define PCMD9   __REG(0x40F00080 + 9 * 4)
+#define PCMD10  __REG(0x40F00080 + 10 * 4)
+#define PCMD11  __REG(0x40F00080 + 11 * 4)
+#define PCMD12  __REG(0x40F00080 + 12 * 4)
+#define PCMD13  __REG(0x40F00080 + 13 * 4)
+#define PCMD14  __REG(0x40F00080 + 14 * 4)
+#define PCMD15  __REG(0x40F00080 + 15 * 4)
+#define PCMD16  __REG(0x40F00080 + 16 * 4)
+#define PCMD17  __REG(0x40F00080 + 17 * 4)
+#define PCMD18  __REG(0x40F00080 + 18 * 4)
+#define PCMD19  __REG(0x40F00080 + 19 * 4)
+#define PCMD20  __REG(0x40F00080 + 20 * 4)
+#define PCMD21  __REG(0x40F00080 + 21 * 4)
+#define PCMD22  __REG(0x40F00080 + 22 * 4)
+#define PCMD23  __REG(0x40F00080 + 23 * 4)
+#define PCMD24  __REG(0x40F00080 + 24 * 4)
+#define PCMD25  __REG(0x40F00080 + 25 * 4)
+#define PCMD26  __REG(0x40F00080 + 26 * 4)
+#define PCMD27  __REG(0x40F00080 + 27 * 4)
+#define PCMD28  __REG(0x40F00080 + 28 * 4)
+#define PCMD29  __REG(0x40F00080 + 29 * 4)
+#define PCMD30  __REG(0x40F00080 + 30 * 4)
+#define PCMD31  __REG(0x40F00080 + 31 * 4)
+
+#define PCMD_MBC        (1<<12)
+#define PCMD_DCE        (1<<11)
+#define PCMD_LC (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
+                                   bit 9 should be 0 all day. */
+#define PVCR_VCSA       (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PCFR_PI2C_EN    (0x1 << 6)
+
+#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
+#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
+#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
+#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
+#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
+#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
+
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+
+#define PCFR_RO         (1 << 15)       /* RDH Override */
+#define PCFR_PO         (1 << 14)       /* PH Override */
+#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
+#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
+#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
+#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
+#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
+#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
+#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
+#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
+#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
+#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
+#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
+#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
+
+#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
+#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
+#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
+#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
+#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
+#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
+#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
+#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
+
+/*
+ * PXA2xx specific Core clock definitions
+ */
+#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
+#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
+#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
+#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
+
+#define CCCR_N_MASK     0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
+#define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
+#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
+#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
+#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
+#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
+#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
+#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
+#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
+#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
+#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
+#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
+#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
+#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
+#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
+#define CKEN_USB        (11)    /* USB Unit Clock Enable */
+#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
+#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
+#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
+#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
+#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
+#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
+#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
+#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
+#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
+#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
+#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
+#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
+#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
+#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
+#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
+
+#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
+
 #endif
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 9aa6c2e939e8..ba7e132de1b3 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -12,6 +12,7 @@
 
 #include <asm/proc-fns.h>
 #include "hardware.h"
+#include "pxa2xx-regs.h"
 #include "pxa-regs.h"
 
 static inline void arch_idle(void)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 4881b80f0f90..de577de8d18c 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -15,7 +15,6 @@ struct platform_mmc_slot {
 
 extern struct platform_mmc_slot zylonite_mmc_slot[];
 
-extern int gpio_backlight;
 extern int gpio_eth_irq;
 
 extern int wm9713_irq;
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index b4da08d7a336..6bd2295c0e01 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port)		\
         return (unsigned sz)value;                                              \
 }
 
-static inline void __iomem *__ioaddr(unsigned int port)
+static inline void __iomem *__deprecated __ioaddr(unsigned int port)
 {
         void __iomem *ret;
         if (__PORT_PCIO(port))
@@ -232,8 +232,7 @@ DECLARE_IO(int,l,"")
         result;                                                                 \
 })
 
-#define __ioaddrc(port)         \
-        ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2))
+#define __ioaddrc(port)         __ioaddr(port)
 
 #define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
 #define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
index 7583895fd336..18e10d2c35ea 100644
--- a/include/asm-arm/arch-s3c2410/gpio.h
+++ b/include/asm-arm/arch-s3c2410/gpio.h
@@ -1,68 +1,18 @@
-/*
- * linux/include/asm-arm/arch-s3c2410/gpio.h
+/* linux/include/asm-arm/arch-s3c2410/gpio.h
  *
- * S3C2410 GPIO wrappers for arch-neutral GPIO calls
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
  *
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
+ * S3C2410 - GPIO lib support
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_S3C2410_GPIO_H
-#define __ASM_ARCH_S3C2410_GPIO_H
-
-#include <asm/irq.h>
-#include <asm/hardware.h>
-#include <asm/arch/regs-gpio.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        return;
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT);
-        return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT);
-        /* REVISIT can we write the value first, to avoid glitching? */
-        s3c2410_gpio_setpin(gpio, value);
-        return 0;
-}
-
-#define gpio_get_value(gpio)            s3c2410_gpio_getpin(gpio)
-#define gpio_set_value(gpio,value)      s3c2410_gpio_setpin(gpio, value)
-
-#include <asm-generic/gpio.h>                   /* cansleep wrappers */
-
-#ifdef CONFIG_CPU_S3C2400
-#define gpio_to_irq(gpio)               s3c2400_gpio_getirq(gpio)
-#else
-#define gpio_to_irq(gpio)               s3c2410_gpio_getirq(gpio)
-#endif
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
 
-/* FIXME implement irq_to_gpio() */
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
 
-#endif
+#include <asm-generic/gpio.h>
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index ecae9e7f5e45..37661358b42b 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #define S3C2412_CLKSRC_I2SCLK_MPLL              (1<<9)
 #define S3C2412_CLKSRC_USBCLK_HCLK              (1<<10)
 #define S3C2412_CLKSRC_CAMCLK_HCLK              (1<<11)
+#define S3C2412_CLKSRC_UREFCLK_EXTCLK   (1<<12)
+#define S3C2412_CLKSRC_EREFCLK_EXTCLK   (1<<14)
 
 #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
 
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h
index bb9d30b72952..bfb222fa4abb 100644
--- a/include/asm-arm/arch-s3c2410/regs-sdi.h
+++ b/include/asm-arm/arch-s3c2410/regs-sdi.h
@@ -28,9 +28,15 @@
 #define S3C2410_SDIDCNT               (0x30)
 #define S3C2410_SDIDSTA               (0x34)
 #define S3C2410_SDIFSTA               (0x38)
+
 #define S3C2410_SDIDATA               (0x3C)
 #define S3C2410_SDIIMSK               (0x40)
 
+#define S3C2440_SDIDATA               (0x40)
+#define S3C2440_SDIIMSK               (0x3C)
+
+#define S3C2440_SDICON_SDRESET        (1<<8)
+#define S3C2440_SDICON_MMCCLOCK       (1<<5)
 #define S3C2410_SDICON_BYTEORDER      (1<<4)
 #define S3C2410_SDICON_SDIOIRQ        (1<<3)
 #define S3C2410_SDICON_RWAITEN        (1<<2)
@@ -42,7 +48,8 @@
 #define S3C2410_SDICMDCON_LONGRSP     (1<<10)
 #define S3C2410_SDICMDCON_WAITRSP     (1<<9)
 #define S3C2410_SDICMDCON_CMDSTART    (1<<8)
-#define S3C2410_SDICMDCON_INDEX       (0xff)
+#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
+#define S3C2410_SDICMDCON_INDEX       (0x3f)
 
 #define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
 #define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
@@ -51,6 +58,9 @@
 #define S3C2410_SDICMDSTAT_XFERING    (1<<8)
 #define S3C2410_SDICMDSTAT_INDEX      (0xff)
 
+#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
+#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
+#define S3C2440_SDIDCON_DS_WORD       (2<<22)
 #define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
 #define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
 #define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
@@ -59,6 +69,7 @@
 #define S3C2410_SDIDCON_WIDEBUS       (1<<16)
 #define S3C2410_SDIDCON_DMAEN         (1<<15)
 #define S3C2410_SDIDCON_STOP          (1<<14)
+#define S3C2440_SDIDCON_DATSTART      (1<<14)
 #define S3C2410_SDIDCON_DATMODE       (3<<12)
 #define S3C2410_SDIDCON_BLKNUM        (0x7ff)
 
@@ -68,6 +79,7 @@
 #define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
 #define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
 
+#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
 #define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
 
 #define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
@@ -82,10 +94,12 @@
 #define S3C2410_SDIDSTA_TXDATAON      (1<<1)
 #define S3C2410_SDIDSTA_RXDATAON      (1<<0)
 
+#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
+#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
 #define S3C2410_SDIFSTA_TFDET          (1<<13)
 #define S3C2410_SDIFSTA_RFDET          (1<<12)
-#define S3C2410_SDIFSTA_TXHALF         (1<<11)
-#define S3C2410_SDIFSTA_TXEMPTY        (1<<10)
+#define S3C2410_SDIFSTA_TFHALF         (1<<11)
+#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
 #define S3C2410_SDIFSTA_RFLAST         (1<<9)
 #define S3C2410_SDIFSTA_RFFULL         (1<<8)
 #define S3C2410_SDIFSTA_RFHALF         (1<<7)
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
 #endif
 
 /*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+
+/*
  * Enable and disable interrupts
  */
 #if __LINUX_ARM_ARCH__ >= 6
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56eed..70b0fe724b62 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
 #endif
 
 #if defined(CONFIG_CPU_FEROCEON)
-# ifdef _CACHE
-#  define MULTI_CACHE 1
-# else
-#  define _CACHE feroceon
-# endif
+# define MULTI_CACHE 1
 #endif
 
 #if defined(CONFIG_CPU_V6)
@@ -410,6 +406,13 @@ extern void flush_dcache_page(struct page *);
 
 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 
+static inline void __flush_icache_all(void)
+{
+        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+            :
+            : "r" (0));
+}
+
 #define ARCH_HAS_FLUSH_ANON_PAGE
 static inline void flush_anon_page(struct vm_area_struct *vma,
                          struct page *page, unsigned long vmaddr)
diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h
deleted file mode 100644
index 19fab2d2b760..000000000000
--- a/include/asm-arm/dyntick.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASMARM_DYNTICK_H
-#define _ASMARM_DYNTICK_H
-
-#include <asm/mach/time.h>
-
-#endif /* _ASMARM_DYNTICK_H */
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index 684fe0645239..5e22881a630d 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -85,19 +85,6 @@
 
 #define MAX_ECARDS      9
 
-typedef enum {                          /* Cards address space          */
-        ECARD_IOC,
-        ECARD_MEMC,
-        ECARD_EASI
-} card_type_t;
-
-typedef enum {                          /* Speed for ECARD_IOC space    */
-        ECARD_SLOW       = 0,
-        ECARD_MEDIUM     = 1,
-        ECARD_FAST       = 2,
-        ECARD_SYNC       = 3
-} card_speed_t;
-
 struct ecard_id {                       /* Card ID structure            */
         unsigned short  manufacturer;
         unsigned short  product;
@@ -190,16 +177,6 @@ struct in_chunk_dir {
 };
 
 /*
- * ecard_claim: claim an expansion card entry
- */
-#define ecard_claim(ec) ((ec)->claimed = 1)
-
-/*
- * ecard_release: release an expansion card entry
- */
-#define ecard_release(ec) ((ec)->claimed = 0)
-
-/*
  * Read a chunk from an expansion card
  * cd : where to put read data
  * ec : expansion card info struct
@@ -209,18 +186,6 @@ struct in_chunk_dir {
 extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
 
 /*
- * Obtain the address of a card.  This returns the "old style" address
- * and should no longer be used.
- */
-static inline unsigned int __deprecated
-ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
-{
-        extern unsigned int __ecard_address(struct expansion_card *,
-                                            card_type_t, card_speed_t);
-        return __ecard_address(ec, type, speed);
-}
-
-/*
  * Request and release ecard resources
  */
 extern int ecard_request_resources(struct expansion_card *ec);
diff --git a/include/asm-arm/ftrace.h b/include/asm-arm/ftrace.h
new file mode 100644
index 000000000000..584ef9a8e5a5
--- /dev/null
+++ b/include/asm-arm/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_ARM_FTRACE
+#define _ASM_ARM_FTRACE
+
+#ifdef CONFIG_FTRACE
+#define MCOUNT_ADDR             ((long)(mcount))
+#define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void mcount(void);
+#endif
+
+#endif
+
+#endif /* _ASM_ARM_FTRACE */
diff --git a/include/asm-arm/hardware/iop3xx-gpio.h b/include/asm-arm/hardware/iop3xx-gpio.h
new file mode 100644
index 000000000000..0c9331f9ac24
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx-gpio.h
@@ -0,0 +1,73 @@
+/*
+ * linux/include/asm-arm/hardware/iop3xx-gpio.h
+ *
+ * IOP3xx GPIO wrappers
+ *
+ * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * Based on IXP4XX gpio.h file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
+#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
+
+#include <asm/hardware.h>
+#include <asm-generic/gpio.h>
+
+#define IOP3XX_N_GPIOS  8
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (gpio > IOP3XX_N_GPIOS)
+                return __gpio_get_value(gpio);
+
+        return gpio_line_get(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (gpio > IOP3XX_N_GPIOS) {
+                __gpio_set_value(gpio, value);
+                return;
+        }
+        gpio_line_set(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        if (gpio < IOP3XX_N_GPIOS)
+                return 0;
+        else
+                return __gpio_cansleep(gpio);
+}
+
+/*
+ * The GPIOs are not generating any interrupt
+ * Note : manuals are not clear about this
+ */
+static inline int gpio_to_irq(int gpio)
+{
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(int gpio)
+{
+        return -EINVAL;
+}
+
+#endif
+
diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h
index 98d594a973d6..f1a08a500604 100644
--- a/include/asm-arm/hw_irq.h
+++ b/include/asm-arm/hw_irq.h
@@ -6,15 +6,4 @@
 
 #include <asm/mach/irq.h>
 
-#if defined(CONFIG_NO_IDLE_HZ)
-# include <asm/dyntick.h>
-# define handle_dynamic_tick(action)                                    \
-        if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) {  \
-                write_seqlock(&xtime_lock);                             \
-                if (system_timer->dyn_tick->state & DYN_TICK_ENABLED)   \
-                        system_timer->dyn_tick->handler(irq, NULL);     \
-                write_sequnlock(&xtime_lock);                           \
-        }
-#endif
-
 #endif
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 47fe34d692da..c8986bb99ed5 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -14,8 +14,6 @@
 
 #define KEXEC_ARCH KEXEC_ARCH_ARM
 
-#define KEXEC_BOOT_PARAMS_SIZE 1536
-
 #define KEXEC_ARM_ATAGS_OFFSET  0x1000
 #define KEXEC_ARM_ZIMAGE_OFFSET 0x8000
 
diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h
index c042194d3ab5..b1a37876942d 100644
--- a/include/asm-arm/kprobes.h
+++ b/include/asm-arm/kprobes.h
@@ -59,6 +59,7 @@ struct kprobe_ctlblk {
 };
 
 void arch_remove_kprobe(struct kprobe *);
+void kretprobe_trampoline(void);
 
 int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
 int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5dc357013b79..2fd36ea0130d 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -41,30 +41,8 @@ struct sys_timer {
 #ifndef CONFIG_GENERIC_TIME
         unsigned long           (*offset)(void);
 #endif
-
-#ifdef CONFIG_NO_IDLE_HZ
-        struct dyn_tick_timer   *dyn_tick;
-#endif
-};
-
-#ifdef CONFIG_NO_IDLE_HZ
-
-#define DYN_TICK_ENABLED        (1 << 1)
-
-struct dyn_tick_timer {
-        spinlock_t      lock;
-        unsigned int    state;                  /* Current state */
-        int             (*enable)(void);        /* Enables dynamic tick */
-        int             (*disable)(void);       /* Disables dynamic tick */
-        void            (*reprogram)(unsigned long); /* Reprograms the timer */
-        int             (*handler)(int, void *);
 };
 
-void timer_dyn_reprogram(void);
-#else
-#define timer_dyn_reprogram()   do { } while (0)
-#endif
-
 extern struct sys_timer *system_timer;
 extern void timer_tick(void);
 
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 6913d02ca5d6..91b9dfdfed52 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
         unsigned int cpu = smp_processor_id();
 
+#ifdef CONFIG_SMP
+        /* check for possible thread migration */
+        if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
+                __flush_icache_all();
+#endif
         if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
                 check_context(next);
                 cpu_switch_mm(next->pgd, next);
diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h
new file mode 100644
index 000000000000..ba4e016d3ec0
--- /dev/null
+++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/plat-orion/cache-feroceon-l2.h
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern void __init feroceon_l2_init(int l2_wt_override);
diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h
index ffd3852a0dd7..ad4ce94c1998 100644
--- a/include/asm-arm/plat-orion/orion_nand.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -18,6 +18,7 @@ struct orion_nand_data {
         u8 ale;         /* address line number connected to ALE */
         u8 cle;         /* address line number connected to CLE */
         u8 width;       /* buswidth */
+        u8 chip_delay;
 };
 
 
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
index 6434ac685d21..e61b7bd97af5 100644
--- a/include/asm-arm/plat-orion/pcie.h
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -14,6 +14,7 @@
 u32 orion_pcie_dev_id(void __iomem *base);
 u32 orion_pcie_rev(void __iomem *base);
 int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_x4_mode(void __iomem *base);
 int orion_pcie_get_local_bus_nr(void __iomem *base);
 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
 void orion_pcie_setup(void __iomem *base,
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 8b0d594397b1..b5bc692f3489 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -65,6 +65,15 @@
 #define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
 #define S3C2410_TCFG1_MUX0_MASK   (15<<0)
 
+#define S3C2410_TCFG1_MUX_DIV2    (0<<0)
+#define S3C2410_TCFG1_MUX_DIV4    (1<<0)
+#define S3C2410_TCFG1_MUX_DIV8    (2<<0)
+#define S3C2410_TCFG1_MUX_DIV16   (3<<0)
+#define S3C2410_TCFG1_MUX_TCLK    (4<<0)
+#define S3C2410_TCFG1_MUX_MASK    (15<<0)
+
+#define S3C2410_TCFG1_SHIFT(x)    ((x) * 4)
+
 /* for each timer, we have an count buffer, an compare buffer and
  * an observation buffer
 */
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
index f9d6f0317bc1..badaac9d64a8 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -21,6 +21,8 @@ extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
 
+extern struct platform_device s3c_device_timer[];
+
 extern struct platform_device s3c_device_usb;
 extern struct platform_device s3c_device_lcd;
 extern struct platform_device s3c_device_wdt;
@@ -36,11 +38,6 @@ extern struct platform_device s3c_device_spi1;
 
 extern struct platform_device s3c_device_nand;
 
-extern struct platform_device s3c_device_timer0;
-extern struct platform_device s3c_device_timer1;
-extern struct platform_device s3c_device_timer2;
-extern struct platform_device s3c_device_timer3;
-
 extern struct platform_device s3c_device_usbgadget;
 
 /* s3c2440 specific devices */
diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/include/asm-arm/plat-s3c24xx/mci.h
new file mode 100644
index 000000000000..2d0852ac3b27
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/mci.h
@@ -0,0 +1,15 @@
+#ifndef _ARCH_MCI_H
+#define _ARCH_MCI_H
+
+struct s3c24xx_mci_pdata {
+        unsigned int    wprotect_invert : 1;
+        unsigned int    detect_invert : 1;   /* set => detect active high. */
+
+        unsigned int    gpio_detect;
+        unsigned int    gpio_wprotect;
+        unsigned long   ocr_avail;
+        void            (*set_power)(unsigned char power_mode,
+                                     unsigned short vdd);
+};
+
+#endif /* _ARCH_NCI_H */
diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h
deleted file mode 100644
index 1a5c9232a91e..000000000000
--- a/include/asm-arm/rtc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  linux/include/asm-arm/rtc.h
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_RTC_H
-#define ASMARM_RTC_H
-
-struct module;
-
-struct rtc_ops {
-        struct module   *owner;
-        int             (*open)(void);
-        void            (*release)(void);
-        int             (*ioctl)(unsigned int, unsigned long);
-
-        int             (*read_time)(struct rtc_time *);
-        int             (*set_time)(struct rtc_time *);
-        int             (*read_alarm)(struct rtc_wkalrm *);
-        int             (*set_alarm)(struct rtc_wkalrm *);
-        int             (*proc)(char *buf);
-};
-
-void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *);
-void rtc_update(unsigned long, unsigned long);
-int register_rtc(struct rtc_ops *);
-void unregister_rtc(struct rtc_ops *);
-
-static inline int rtc_periodic_alarm(struct rtc_time *tm)
-{
-        return  (tm->tm_year == -1) ||
-                ((unsigned)tm->tm_mon >= 12) ||
-                ((unsigned)(tm->tm_mday - 1) >= 31) ||
-                ((unsigned)tm->tm_hour > 23) ||
-                ((unsigned)tm->tm_min > 59) ||
-                ((unsigned)tm->tm_sec > 59);
-}
-
-#endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index af99636db400..7fffa2404b8e 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -101,6 +101,9 @@ extern void platform_cpu_die(unsigned int cpu);
 extern int platform_cpu_kill(unsigned int cpu);
 extern void platform_cpu_enable(unsigned int cpu);
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 /*
  * Local timer interrupt handling function (can be IPI'ed).
  */
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8c6bc1bb9d1a..909656c747ef 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -39,6 +39,7 @@
 #define TLB_V6_D_ASID   (1 << 17)
 #define TLB_V6_I_ASID   (1 << 18)
 
+#define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
 
@@ -51,6 +52,7 @@
  *        v4    - ARMv4 without write buffer
  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
+ *        fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  */
 #undef _TLB
@@ -103,6 +105,23 @@
 # define v4wbi_always_flags     (-1UL)
 #endif
 
+#define fr_tlb_flags    (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
+                         TLB_V4_I_FULL | TLB_V4_D_FULL | \
+                         TLB_V4_I_PAGE | TLB_V4_D_PAGE)
+
+#ifdef CONFIG_CPU_TLB_FEROCEON
+# define fr_possible_flags      fr_tlb_flags
+# define fr_always_flags        fr_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v4wbi
+# endif
+#else
+# define fr_possible_flags      0
+# define fr_always_flags        (-1UL)
+#endif
+
 #define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
                          TLB_V4_D_PAGE)
@@ -245,12 +264,14 @@ extern struct cpu_tlb_fns cpu_tlb;
 #define possible_tlb_flags      (v3_possible_flags | \
                                  v4_possible_flags | \
                                  v4wbi_possible_flags | \
+                                 fr_possible_flags | \
                                  v4wb_possible_flags | \
                                  v6wbi_possible_flags)
 
 #define always_tlb_flags        (v3_always_flags & \
                                  v4_always_flags & \
                                  v4wbi_always_flags & \
+                                 fr_always_flags & \
                                  v4wb_always_flags & \
                                  v6wbi_always_flags)
 
@@ -417,6 +438,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
         if (tlb_flag(TLB_DCLEAN))
                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                         : : "r" (pmd) : "cc");
+
+        if (tlb_flag(TLB_L2CLEAN_FR))
+                asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
+                        : : "r" (pmd) : "cc");
+
         if (tlb_flag(TLB_WB))
                 dsb();
 }
@@ -428,6 +454,10 @@ static inline void clean_pmd_entry(pmd_t *pmd)
         if (tlb_flag(TLB_DCLEAN))
                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                         : : "r" (pmd) : "cc");
+
+        if (tlb_flag(TLB_L2CLEAN_FR))
+                asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
+                        : : "r" (pmd) : "cc");
 }
 
 #undef tlb_flag
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index a4e2d28bfb58..a3783861cdd2 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -8,6 +8,12 @@
 
 #define GPIO_PIN_NONE   (-1)
 
+/*
+ * Clock rates for various on-board oscillators. The number of entries
+ * in this array is chip-dependent.
+ */
+extern unsigned long at32_board_osc_rates[];
+  
 /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
 void at32_add_system_devices(void);
 
@@ -36,7 +42,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
 struct atmel_lcdfb_info;
 struct platform_device *
 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-                     unsigned long fbmem_start, unsigned long fbmem_len);
+                     unsigned long fbmem_start, unsigned long fbmem_len,
+                     unsigned int pin_config);
 
 struct usba_platform_data;
 struct platform_device *
@@ -70,9 +77,14 @@ struct i2c_board_info;
 struct platform_device *at32_add_device_twi(unsigned int id,
                                             struct i2c_board_info *b,
                                             unsigned int n);
-struct platform_device *at32_add_device_mci(unsigned int id);
+
+struct mci_platform_data;
+struct platform_device *
+at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
+
 struct platform_device *at32_add_device_ac97c(unsigned int id);
 struct platform_device *at32_add_device_abdac(unsigned int id);
+struct platform_device *at32_add_device_psif(unsigned int id);
 
 struct cf_platform_data {
         int     detect_pin;
diff --git a/include/asm-avr32/arch-at32ap/init.h b/include/asm-avr32/arch-at32ap/init.h
index 5e75d850d707..bc40e3d46150 100644
--- a/include/asm-avr32/arch-at32ap/init.h
+++ b/include/asm-avr32/arch-at32ap/init.h
@@ -13,10 +13,6 @@
 void setup_platform(void);
 void setup_board(void);
 
-/* Called by setup_platform */
-void at32_clock_init(void);
-void at32_portmux_init(void);
-
 void at32_setup_serial_console(unsigned int usart_id);
 
 #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
diff --git a/include/asm-avr32/arch-at32ap/pm.h b/include/asm-avr32/arch-at32ap/pm.h
index 356e43064903..979b355b77b6 100644
--- a/include/asm-avr32/arch-at32ap/pm.h
+++ b/include/asm-avr32/arch-at32ap/pm.h
@@ -19,6 +19,7 @@
 
 #ifndef __ASSEMBLY__
 extern void cpu_enter_idle(void);
+extern void cpu_enter_standby(unsigned long sdramc_base);
 
 extern bool disable_idle_sleep;
 
@@ -43,6 +44,8 @@ static inline void cpu_idle_sleep(void)
         else
                 cpu_enter_idle();
 }
+
+void intc_set_suspend_handler(unsigned long offset);
 #endif
 
 #endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/arch-at32ap/sram.h b/include/asm-avr32/arch-at32ap/sram.h
new file mode 100644
index 000000000000..4838dae7601a
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/sram.h
@@ -0,0 +1,30 @@
+/*
+ * Simple SRAM allocator
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_AVR32_ARCH_SRAM_H
+#define __ASM_AVR32_ARCH_SRAM_H
+
+#include <linux/genalloc.h>
+
+extern struct gen_pool *sram_pool;
+
+static inline unsigned long sram_alloc(size_t len)
+{
+        if (!sram_pool)
+                return 0UL;
+
+        return gen_pool_alloc(sram_pool, len);
+}
+
+static inline void sram_free(unsigned long addr, size_t len)
+{
+        return gen_pool_free(sram_pool, addr, len);
+}
+
+#endif /* __ASM_AVR32_ARCH_SRAM_H */
diff --git a/include/asm-avr32/atmel-mci.h b/include/asm-avr32/atmel-mci.h
new file mode 100644
index 000000000000..c2ea6e1c9aa1
--- /dev/null
+++ b/include/asm-avr32/atmel-mci.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_AVR32_ATMEL_MCI_H
+#define __ASM_AVR32_ATMEL_MCI_H
+
+struct mci_platform_data {
+        int                     detect_pin;
+        int                     wp_pin;
+};
+
+#endif /* __ASM_AVR32_ATMEL_MCI_H */
diff --git a/include/asm-avr32/mmu_context.h b/include/asm-avr32/mmu_context.h
index c37c391faef6..27ff23407100 100644
--- a/include/asm-avr32/mmu_context.h
+++ b/include/asm-avr32/mmu_context.h
@@ -13,7 +13,6 @@
 #define __ASM_AVR32_MMU_CONTEXT_H
 
 #include <asm/tlbflush.h>
-#include <asm/pgalloc.h>
 #include <asm/sysreg.h>
 #include <asm-generic/mm_hooks.h>
 
diff --git a/include/asm-avr32/pci.h b/include/asm-avr32/pci.h
index 0f5f134b896a..a32a02372017 100644
--- a/include/asm-avr32/pci.h
+++ b/include/asm-avr32/pci.h
@@ -5,4 +5,6 @@
 
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
+#include <asm-generic/pci-dma-compat.h>
+
 #endif /* __ASM_AVR32_PCI_H__ */
diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h
index 51fc1f6e4b17..640821323943 100644
--- a/include/asm-avr32/pgalloc.h
+++ b/include/asm-avr32/pgalloc.h
@@ -8,65 +8,79 @@
 #ifndef __ASM_AVR32_PGALLOC_H
 #define __ASM_AVR32_PGALLOC_H
 
-#include <asm/processor.h>
-#include <linux/threads.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
+#include <linux/quicklist.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
 
-#define pmd_populate_kernel(mm, pmd, pte) \
-        set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
+#define QUICK_PGD       0       /* Preserve kernel mappings over free */
+#define QUICK_PT        1       /* Zero on free */
 
-static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+static inline void pmd_populate_kernel(struct mm_struct *mm,
+                                       pmd_t *pmd, pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
                                     pgtable_t pte)
 {
-        set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
 }
 #define pmd_pgtable(pmd) pmd_page(pmd)
 
+static inline void pgd_ctor(void *x)
+{
+        pgd_t *pgd = x;
+
+        memcpy(pgd + USER_PTRS_PER_PGD,
+                swapper_pg_dir + USER_PTRS_PER_PGD,
+                (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+}
+
 /*
  * Allocate and free page tables
  */
-static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
+        return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
 }
 
 static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 {
-        kfree(pgd);
+        quicklist_free(QUICK_PGD, NULL, pgd);
 }
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                                           unsigned long address)
 {
-        pte_t *pte;
-
-        pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
-
-        return pte;
+        return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
 }
 
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
                                          unsigned long address)
 {
-        struct page *pte;
+        struct page *page;
+        void *pg;
 
-        pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
-        if (!pte)
+        pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+        if (!pg)
                 return NULL;
-        pgtable_page_ctor(pte);
-        return pte;
+
+        page = virt_to_page(pg);
+        pgtable_page_ctor(page);
+
+        return page;
 }
 
 static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
 {
-        free_page((unsigned long)pte);
+        quicklist_free(QUICK_PT, NULL, pte);
 }
 
 static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
 {
         pgtable_page_dtor(pte);
-        __free_page(pte);
+        quicklist_free_page(QUICK_PT, NULL, pte);
 }
 
 #define __pte_free_tlb(tlb,pte)                         \
@@ -75,6 +89,10 @@ do {							\
         tlb_remove_page((tlb), pte);                    \
 } while (0)
 
-#define check_pgt_cache() do { } while(0)
+static inline void check_pgt_cache(void)
+{
+        quicklist_trim(QUICK_PGD, NULL, 25, 16);
+        quicklist_trim(QUICK_PT, NULL, 25, 16);
+}
 
 #endif /* __ASM_AVR32_PGALLOC_H */
diff --git a/include/asm-avr32/pgtable.h b/include/asm-avr32/pgtable.h
index c0e5e29417df..fecdda16f444 100644
--- a/include/asm-avr32/pgtable.h
+++ b/include/asm-avr32/pgtable.h
@@ -129,13 +129,6 @@ extern struct page *empty_zero_page;
 
 #define _PAGE_FLAGS_CACHE_MASK  (_PAGE_CACHABLE | _PAGE_BUFFER | _PAGE_WT)
 
-/* TODO: Check for saneness */
-/* User-mode page table flags (to be set in a pgd or pmd entry) */
-#define _PAGE_TABLE             (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
-                                 | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
-/* Kernel-mode page table flags */
-#define _KERNPG_TABLE           (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
-                                 | _PAGE_ACCESSED | _PAGE_DIRTY)
 /* Flags that may be modified by software */
 #define _PAGE_CHG_MASK          (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY \
                                  | _PAGE_FLAGS_CACHE_MASK)
@@ -262,10 +255,14 @@ static inline pte_t pte_mkspecial(pte_t pte)
 }
 
 #define pmd_none(x)     (!pmd_val(x))
-#define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER))      \
-                         != _KERNPG_TABLE)
+#define pmd_present(x)  (pmd_val(x))
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        set_pmd(pmdp, __pmd(0));
+}
+
+#define pmd_bad(x)      (pmd_val(x) & ~PAGE_MASK)
 
 /*
  * Permanent address of a page. We don't support highmem, so this is
@@ -303,19 +300,16 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 
 #define page_pte(page)  page_pte_prot(page, __pgprot(0))
 
-#define pmd_page_vaddr(pmd)                                     \
-        ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-#define pmd_page(pmd)   (phys_to_page(pmd_val(pmd)))
+#define pmd_page_vaddr(pmd)     pmd_val(pmd)
+#define pmd_page(pmd)           (virt_to_page(pmd_val(pmd)))
 
 /* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
-#define pgd_offset_current(address)                             \
-        ((pgd_t *)__mfsr(SYSREG_PTBR) + pgd_index(address))
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT)     \
+                                 & (PTRS_PER_PGD - 1))
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 
 /* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 
 /* Find an entry in the third-level page table.. */
 #define pte_index(address)                              \
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index 07049f6c0d41..df68631b7b27 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -88,6 +88,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_MEMDIE              6
 #define TIF_RESTORE_SIGMASK     7       /* restore signal mask in do_signal */
 #define TIF_CPU_GOING_TO_SLEEP  8       /* CPU is entering sleep 0 mode */
+#define TIF_FREEZE              29
 #define TIF_DEBUG               30      /* debugging enabled */
 #define TIF_USERSPACE           31      /* true if FS sets userspace */
 
diff --git a/include/asm-avr32/tlbflush.h b/include/asm-avr32/tlbflush.h
index 5bc7c88a5770..bf90a786f6be 100644
--- a/include/asm-avr32/tlbflush.h
+++ b/include/asm-avr32/tlbflush.h
@@ -26,7 +26,6 @@ extern void flush_tlb_mm(struct mm_struct *mm);
 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                             unsigned long end);
 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-extern void __flush_tlb_page(unsigned long asid, unsigned long page);
 
 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 4fce3db2cecc..ef87f889ef62 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -195,7 +195,6 @@ static inline int pmd_none_or_clear_bad(pmd_t *pmd)
         }
         return 0;
 }
-#endif /* CONFIG_MMU */
 
 static inline pte_t __ptep_modify_prot_start(struct mm_struct *mm,
                                              unsigned long addr,
@@ -253,6 +252,7 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm,
         __ptep_modify_prot_commit(mm, addr, ptep, pte);
 }
 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
+#endif /* CONFIG_MMU */
 
 /*
  * A facility to provide lazy MMU batching.  This allows PTE updates and
diff --git a/include/asm-generic/topology.h b/include/asm-generic/topology.h
index a6aea79bca4f..54bbf6e04ee8 100644
--- a/include/asm-generic/topology.h
+++ b/include/asm-generic/topology.h
@@ -60,7 +60,8 @@
 #ifndef node_to_cpumask_ptr
 
 #define node_to_cpumask_ptr(v, node)                                    \
-                cpumask_t _##v = node_to_cpumask(node), *v = &_##v
+                cpumask_t _##v = node_to_cpumask(node);                 \
+                const cpumask_t *v = &_##v
 
 #define node_to_cpumask_ptr_next(v, node)                               \
                           _##v = node_to_cpumask(node)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index f1992dc5c424..729f6b0a60e9 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -67,6 +67,8 @@
                 *(.rodata1)                                             \
         }                                                               \
                                                                         \
+        BUG_TABLE                                                       \
+                                                                        \
         /* PCI quirks */                                                \
         .pci_fixup        : AT(ADDR(.pci_fixup) - LOAD_OFFSET) {        \
                 VMLINUX_SYMBOL(__start_pci_fixups_early) = .;           \
@@ -84,6 +86,19 @@
                 VMLINUX_SYMBOL(__start_pci_fixups_resume) = .;          \
                 *(.pci_fixup_resume)                                    \
                 VMLINUX_SYMBOL(__end_pci_fixups_resume) = .;            \
+                VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .;    \
+                *(.pci_fixup_resume_early)                              \
+                VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .;      \
+                VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .;         \
+                *(.pci_fixup_suspend)                                   \
+                VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .;           \
+        }                                                               \
+                                                                        \
+        /* Built-in firmware blobs */                                   \
+        .builtin_fw        : AT(ADDR(.builtin_fw) - LOAD_OFFSET) {      \
+                VMLINUX_SYMBOL(__start_builtin_fw) = .;                 \
+                *(.builtin_fw)                                          \
+                VMLINUX_SYMBOL(__end_builtin_fw) = .;                   \
         }                                                               \
                                                                         \
         /* RapidIO route ops */                                         \
@@ -312,6 +327,7 @@
                 .stab.indexstr 0 : { *(.stab.indexstr) }                \
                 .comment 0 : { *(.comment) }
 
+#ifdef CONFIG_GENERIC_BUG
 #define BUG_TABLE                                                       \
         . = ALIGN(8);                                                   \
         __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) {             \
@@ -319,6 +335,9 @@
                 *(__bug_table)                                          \
                 __stop___bug_table = .;                                 \
         }
+#else
+#define BUG_TABLE
+#endif
 
 #ifdef CONFIG_PM_TRACE
 #define TRACEDATA                                                       \
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 6aff126fc07e..f88fa054d01d 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -763,6 +763,8 @@ prefetchw (const void *x)
 #define spin_lock_prefetch(x)   prefetchw(x)
 
 extern unsigned long boot_option_idle_override;
+extern unsigned long idle_halt;
+extern unsigned long idle_nomwait;
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
index ec5f355fb7e3..27731e032ee9 100644
--- a/include/asm-ia64/smp.h
+++ b/include/asm-ia64/smp.h
@@ -38,9 +38,6 @@ ia64_get_lid (void)
         return lid.f.id << 8 | lid.f.eid;
 }
 
-extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
-                                  void *info, int wait);
-
 #define hard_smp_processor_id()         ia64_get_lid()
 
 #ifdef CONFIG_SMP
@@ -124,11 +121,12 @@ extern void __init init_smp_config (void);
 extern void smp_do_timer (struct pt_regs *regs);
 
 extern void smp_send_reschedule (int cpu);
-extern void lock_ipi_calllock(void);
-extern void unlock_ipi_calllock(void);
 extern void identify_siblings (struct cpuinfo_ia64 *);
 extern int is_multithreading_enabled(void);
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 #else /* CONFIG_SMP */
 
 #define cpu_logical_id(i)               0
diff --git a/include/asm-m32r/smp.h b/include/asm-m32r/smp.h
index 078e1a51a042..c5dd66916692 100644
--- a/include/asm-m32r/smp.h
+++ b/include/asm-m32r/smp.h
@@ -89,6 +89,9 @@ static __inline__ unsigned int num_booting_cpus(void)
 extern void smp_send_timer(void);
 extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 #endif  /* not __ASSEMBLY__ */
 
 #define NO_PROC_ID (0xff)       /* No processor magic marker */
@@ -104,6 +107,7 @@ extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
 #define LOCAL_TIMER_IPI         (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
 #define INVALIDATE_CACHE_IPI    (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
 #define CPU_BOOT_IPI            (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
+#define CALL_FUNC_SINGLE_IPI    (M32R_IRQ_IPI6-M32R_IRQ_IPI0)
 
 #define IPI_SHIFT       (0)
 #define NR_IPIS         (8)
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h
index 9d8cfbb5e796..8e9ac313ca3b 100644
--- a/include/asm-mips/barrier.h
+++ b/include/asm-mips/barrier.h
@@ -92,11 +92,25 @@
 #define fast_wmb()      __sync()
 #define fast_rmb()      __sync()
 #define fast_mb()       __sync()
+#ifdef CONFIG_SGI_IP28
+#define fast_iob()                              \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "sync\n\t"                      \
+                "lw     $0,%0\n\t"              \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
+                : "memory")
+#else
 #define fast_iob()                              \
         do {                                    \
                 __sync();                       \
                 __fast_iob();                   \
         } while (0)
+#endif
 
 #ifdef CONFIG_CPU_HAS_WB
 
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 642724734eba..9a7274ba6a0b 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m), "r" (~0));
+                : "i" (bit), "m" (*m), "r" (~0));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
@@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m));
+                : "i" (bit), "m" (*m));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "ri" (bit), "m" (*m)
+                : "i" (bit), "m" (*m)
                 : "memory");
 #endif
         } else if (cpu_has_llsc) {
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index e031bdff9920..d39e143b4a3c 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -26,13 +26,6 @@
 #define  MACH_UNKNOWN           0       /* whatever...                  */
 
 /*
- * Valid machtype values for group JAZZ
- */
-#define  MACH_ACER_PICA_61      0       /* Acer PICA-61 (PICA1)         */
-#define  MACH_MIPS_MAGNUM_4000  1       /* Mips Magnum 4000 "RC4030"    */
-#define  MACH_OLIVETTI_M700     2       /* Olivetti M700-10 (-15 ??)    */
-
-/*
  * Valid machtype for group DEC
  */
 #define  MACH_DSUNKNOWN         0
@@ -48,42 +41,6 @@
 #define  MACH_DS5900            10      /* DECsystem 5900               */
 
 /*
- * Valid machtype for group SNI_RM
- */
-#define  MACH_SNI_RM200_PCI     0       /* RM200/RM300/RM400 PCI series */
-
-/*
- * Valid machtype for group SGI
- */
-#define  MACH_SGI_IP22          0       /* Indy, Indigo2, Challenge S   */
-#define  MACH_SGI_IP27          1       /* Origin 200, Origin 2000, Onyx 2 */
-#define  MACH_SGI_IP28          2       /* Indigo2 Impact               */
-#define  MACH_SGI_IP32          3       /* O2                           */
-#define  MACH_SGI_IP30          4       /* Octane, Octane2              */
-
-/*
- * Valid machtypes for group Toshiba
- */
-#define  MACH_PALLAS            0
-#define  MACH_TOPAS             1
-#define  MACH_JMR               2
-#define  MACH_TOSHIBA_JMR3927   3       /* JMR-TX3927 CPU/IO board */
-#define  MACH_TOSHIBA_RBTX4927  4
-#define  MACH_TOSHIBA_RBTX4937  5
-#define  MACH_TOSHIBA_RBTX4938  6
-
-/*
- * Valid machtype for group LASAT
- */
-#define  MACH_LASAT_100         0       /* Masquerade II/SP100/SP50/SP25 */
-#define  MACH_LASAT_200         1       /* Masquerade PRO/SP200 */
-
-/*
- * Valid machtype for group NEC EMMA2RH
- */
-#define  MACH_NEC_MARKEINS      0       /* NEC EMMA2RH Mark-eins        */
-
-/*
  * Valid machtype for group PMC-MSP
  */
 #define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 1c35cac6f35b..229a786101d9 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -66,8 +66,10 @@
 #define PRID_IMP_RM7000         0x2700
 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
 #define PRID_IMP_RM9000         0x3400
+#define PRID_IMP_LOONGSON1      0x4200
 #define PRID_IMP_R5432          0x5400
 #define PRID_IMP_R5500          0x5500
+#define PRID_IMP_LOONGSON2      0x6300
 
 #define PRID_IMP_UNKNOWN        0xff00
 
@@ -90,8 +92,6 @@
 #define PRID_IMP_24KE           0x9600
 #define PRID_IMP_74K            0x9700
 #define PRID_IMP_1004K          0x9900
-#define PRID_IMP_LOONGSON1      0x4200
-#define PRID_IMP_LOONGSON2      0x6300
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index 15fe8f881e60..56d22dc8803a 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -6,7 +6,7 @@
  *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
  *      definitions.
  *
- *      Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
+ *      Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
@@ -54,11 +54,11 @@
  */
 #define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
 #define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
-#define KN4K_MB_INT_MT          (1<<3)          /* ??? */
+#define KN4K_MB_INT_MT          (1<<3)          /* I/O ASIC cascade */
 
 /*
  * Bits for the MB control & status register.
- * Set to 0x00bf8001 on my system by the ROM.
+ * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
  */
 #define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
 #define KN4K_MB_CSR_F           (1<<1)          /* ??? */
@@ -69,7 +69,8 @@
 #define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
 #define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
 #define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
-#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* ??? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* CPU Int[4:0] mask */
 #define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_W           (1<<31)         /* ??? */
 
 #endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
deleted file mode 100644
index cc88aed23f0f..000000000000
--- a/include/asm-mips/inventory.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Miguel de Icaza
- */
-#ifndef __ASM_INVENTORY_H
-#define __ASM_INVENTORY_H
-
-#include <linux/compiler.h>
-
-typedef struct inventory_s {
-        struct inventory_s *inv_next;
-        int    inv_class;
-        int    inv_type;
-        int    inv_controller;
-        int    inv_unit;
-        int    inv_state;
-} inventory_t;
-
-extern int inventory_items;
-
-extern void add_to_inventory(int class, int type, int controller, int unit, int state);
-extern int dump_inventory_to_user(void __user *userbuf, int size);
-extern int __init init_inventory(void);
-
-#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index f18d2816cbec..501a40b9f18d 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -161,13 +161,6 @@ static inline void * isa_bus_to_virt(unsigned long address)
 #define bus_to_virt phys_to_virt
 
 /*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.  This implies the assumption that there is only
- * one of these busses.
- */
-extern unsigned long isa_slot_offset;
-
-/*
  * Change "struct page" to physical address.
  */
 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
@@ -528,16 +521,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
 }
 
 /*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char *)(isa_slot_offset))
-
-/*
  * The caches on some architectures aren't dma-coherent and have need to
  * handle this in software.  There are three types of operations that
  * can be applied to dma buffers.
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
index ea04d9262edc..caeba1e302a2 100644
--- a/include/asm-mips/lasat/lasat.h
+++ b/include/asm-mips/lasat/lasat.h
@@ -240,6 +240,8 @@ static inline void lasat_ndelay(unsigned int ns)
         __delay(ns / lasat_ndelay_divider);
 }
 
+#define IS_LASAT_200()     (current_cpu_data.cputype == CPU_R5000)
+
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
deleted file mode 100644
index 51d337e1bbd1..000000000000
--- a/include/asm-mips/mach-atlas/mc146818rtc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 1999, 2000, 2005  MIPS Technologies, Inc.
- *      All rights reserved.
- *      Authors: Carsten Langgaard <carstenl@mips.com>
- *               Maciej W. Rozycki <macro@mips.com>
- * Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org)
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef __ASM_MACH_ATLAS_MC146818RTC_H
-#define __ASM_MACH_ATLAS_MC146818RTC_H
-
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mips-boards/atlas.h>
-#include <asm/mips-boards/atlasint.h>
-
-#define ARCH_RTC_LOCATION
-
-#define RTC_PORT(x)     (ATLAS_RTC_ADR_REG + (x) * 8)
-#define RTC_IO_EXTENT   0x100
-#define RTC_IOMAPPED    0
-#define RTC_IRQ         ATLAS_INT_RTC
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
-        volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
-
-        *ireg = addr;
-        return *dreg;
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
-        volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
-
-        *ireg = addr;
-        *dreg = data;
-}
-
-#define RTC_ALWAYS_BCD  0
-
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
-
-#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
index 9e0028f60a43..c35e20918490 100644
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ b/include/asm-mips/mach-au1x00/au1100_mmc.h
@@ -38,15 +38,15 @@
 #ifndef __ASM_AU1100_MMC_H
 #define __ASM_AU1100_MMC_H
 
-
-#define NUM_AU1100_MMC_CONTROLLERS      2
-
-#if defined(CONFIG_SOC_AU1100)
-#define AU1100_SD_IRQ   AU1100_SD_INT
-#elif defined(CONFIG_SOC_AU1200)
-#define AU1100_SD_IRQ   AU1200_SD_INT
-#endif
-
+#include <linux/leds.h>
+
+struct au1xmmc_platform_data {
+        int(*cd_setup)(void *mmc_host, int on);
+        int(*card_inserted)(void *mmc_host);
+        int(*card_readonly)(void *mmc_host);
+        void(*set_power)(void *mmc_host, int state);
+        struct led_classdev *led;
+};
 
 #define SD0_BASE        0xB0600000
 #define SD1_BASE        0xB0680000
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index dae4eca2417e..892b7f168eb4 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -204,6 +204,14 @@ typedef struct	psc_i2s {
         u32     psc_i2sudf;
 } psc_i2s_t;
 
+#define PSC_I2SCFG_OFFSET       0x08
+#define PSC_I2SMASK_OFFSET      0x0C
+#define PSC_I2SPCR_OFFSET       0x10
+#define PSC_I2SSTAT_OFFSET      0x14
+#define PSC_I2SEVENT_OFFSET     0x18
+#define PSC_I2SRXTX_OFFSET      0x1C
+#define PSC_I2SUDF_OFFSET       0x20
+
 /* I2S Config Register. */
 #define PSC_I2SCFG_RT_MASK      (3 << 30)
 #define PSC_I2SCFG_RT_FIFO1     (0 << 30)
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 612ae90dbcb8..1a515b8c870f 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -146,51 +146,6 @@ typedef volatile struct
         ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
 
 /*
- * SD controller macros
- */
-
-/* Detect card. */
-#define mmc_card_inserted(_n_, _res_) \
-        do { \
-                BCSR * const bcsr = (BCSR *)0xAE000000; \
-                unsigned long mmc_wp, board_specific; \
-                if ((_n_)) { \
-                        mmc_wp = BCSR_BOARD_SD1_WP; \
-                } else { \
-                        mmc_wp = BCSR_BOARD_SD0_WP; \
-                } \
-                board_specific = au_readl((unsigned long)(&bcsr->specific)); \
-                if (!(board_specific & mmc_wp)) {/* low means card present */ \
-                        *(int *)(_res_) = 1; \
-                } else { \
-                        *(int *)(_res_) = 0; \
-                } \
-        } while (0)
-
-/*
- * Apply power to card slot(s).
- */
-#define mmc_power_on(_n_) \
-        do { \
-                BCSR * const bcsr = (BCSR *)0xAE000000; \
-                unsigned long mmc_pwr, mmc_wp, board_specific; \
-                if ((_n_)) { \
-                        mmc_pwr = BCSR_BOARD_SD1_PWR; \
-                        mmc_wp  = BCSR_BOARD_SD1_WP; \
-                } else { \
-                        mmc_pwr = BCSR_BOARD_SD0_PWR; \
-                        mmc_wp  = BCSR_BOARD_SD0_WP; \
-                } \
-                board_specific = au_readl((unsigned long)(&bcsr->specific)); \
-                if (!(board_specific & mmc_wp)) {/* low means card present */ \
-                        board_specific |= mmc_pwr; \
-                        au_writel(board_specific, (int)(&bcsr->specific)); \
-                        au_sync(); \
-                } \
-        } while (0)
-
-
-/*
  * NAND defines
  *
  * Timing values as described in databook, * ns value stripped of the
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h
index 7f3e3f9bd23a..7f3e3f9bd23a 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-malta/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-malta/irq.h
index 9b9da26683c2..9b9da26683c2 100644
--- a/include/asm-mips/mach-mips/irq.h
+++ b/include/asm-mips/mach-malta/irq.h
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h
index 0b793e7bf67e..0b793e7bf67e 100644
--- a/include/asm-mips/mach-mips/kernel-entry-init.h
+++ b/include/asm-mips/mach-malta/kernel-entry-init.h
diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h
index 0f863148f3b6..0f863148f3b6 100644
--- a/include/asm-mips/mach-mips/mach-gt64120.h
+++ b/include/asm-mips/mach-malta/mach-gt64120.h
diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h
index ea612f37f614..ea612f37f614 100644
--- a/include/asm-mips/mach-mips/mc146818rtc.h
+++ b/include/asm-mips/mach-malta/mc146818rtc.h
diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-malta/war.h
index 7c6931d5f45f..7c6931d5f45f 100644
--- a/include/asm-mips/mach-mips/war.h
+++ b/include/asm-mips/mach-malta/war.h
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h
index 29989ff10d66..93c6c04ffda3 100644
--- a/include/asm-mips/mach-jmr3927/ioremap.h
+++ b/include/asm-mips/mach-tx39xx/ioremap.h
@@ -1,13 +1,13 @@
 /*
- *      include/asm-mips/mach-jmr3927/ioremap.h
+ *      include/asm-mips/mach-tx39xx/ioremap.h
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
  *      as published by the Free Software Foundation; either version
  *      2 of the License, or (at your option) any later version.
  */
-#ifndef __ASM_MACH_JMR3927_IOREMAP_H
-#define __ASM_MACH_JMR3927_IOREMAP_H
+#ifndef __ASM_MACH_TX39XX_IOREMAP_H
+#define __ASM_MACH_TX39XX_IOREMAP_H
 
 #include <linux/types.h>
 
@@ -35,4 +35,4 @@ static inline int plat_iounmap(const volatile void __iomem *addr)
         return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
 }
 
-#endif /* __ASM_MACH_JMR3927_IOREMAP_H */
+#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h
index 11bffcd1043b..ef0b502fd8b7 100644
--- a/include/asm-mips/mach-jmr3927/mangle-port.h
+++ b/include/asm-mips/mach-tx39xx/mangle-port.h
@@ -1,7 +1,12 @@
-#ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H
-#define __ASM_MACH_JMR3927_MANGLE_PORT_H
+#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
+#define __ASM_MACH_TX39XX_MANGLE_PORT_H
 
-extern unsigned long __swizzle_addr_b(unsigned long port);
+#if defined(CONFIG_TOSHIBA_JMR3927)
+extern unsigned long (*__swizzle_addr_b)(unsigned long port);
+#define NEEDS_TXX9_SWIZZLE_ADDR_B
+#else
+#define __swizzle_addr_b(port)  (port)
+#endif
 #define __swizzle_addr_w(port)  (port)
 #define __swizzle_addr_l(port)  (port)
 #define __swizzle_addr_q(port)  (port)
@@ -15,4 +20,4 @@ extern unsigned long __swizzle_addr_b(unsigned long port);
 #define ioswabq(a, x)           le64_to_cpu(x)
 #define __mem_ioswabq(a, x)     (x)
 
-#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */
+#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-tx39xx/war.h
index 1ff55fb3fbcb..433814616359 100644
--- a/include/asm-mips/mach-jmr3927/war.h
+++ b/include/asm-mips/mach-tx39xx/war.h
@@ -5,8 +5,8 @@
  *
  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
  */
-#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H
-#define __ASM_MIPS_MACH_JMR3927_WAR_H
+#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
+#define __ASM_MIPS_MACH_TX39XX_WAR_H
 
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #define R4600_V1_HIT_CACHEOP_WAR        0
@@ -22,4 +22,4 @@
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
 
-#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */
+#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h
index 848812296052..862058d3f81b 100644
--- a/include/asm-mips/mach-vr41xx/irq.h
+++ b/include/asm-mips/mach-vr41xx/irq.h
@@ -2,9 +2,6 @@
 #define __ASM_MACH_VR41XX_IRQ_H
 
 #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
-#ifdef CONFIG_NEC_CMBVR4133
-#include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */
-#endif
 
 #include_next <irq.h>
 
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 33407bee4e73..7f0b034dd9a5 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -27,12 +27,8 @@
 /*
  * Display register base.
  */
-#ifdef CONFIG_MIPS_SEAD
-#define ASCII_DISPLAY_POS_BASE     0x1f0005c0
-#else
 #define ASCII_DISPLAY_WORD_BASE    0x1f000410
 #define ASCII_DISPLAY_POS_BASE     0x1f000418
-#endif
 
 
 /*
@@ -44,13 +40,8 @@
 /*
  * Reset register.
  */
-#ifdef CONFIG_MIPS_SEAD
-#define SOFTRES_REG       0x1e800050
-#define GORESET           0x4d
-#else
 #define SOFTRES_REG       0x1f000500
 #define GORESET           0x42
-#endif
 
 /*
  * Revision register.
diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h
index c94d12d1f868..a6605a752469 100644
--- a/include/asm-mips/namei.h
+++ b/include/asm-mips/namei.h
@@ -1,26 +1,11 @@
 #ifndef _ASM_NAMEI_H
 #define _ASM_NAMEI_H
 
-#include <linux/personality.h>
-#include <linux/stddef.h>
+/*
+ * This dummy routine maybe changed to something useful
+ * for /usr/gnemul/ emulation stuff.
+ */
 
-#define IRIX_EMUL       "/usr/gnemul/irix/"
-#define RISCOS_EMUL     "/usr/gnemul/riscos/"
-
-static inline char *__emul_prefix(void)
-{
-        switch (current->personality) {
-        case PER_IRIX32:
-        case PER_IRIXN32:
-        case PER_IRIX64:
-                return IRIX_EMUL;
-
-        case PER_RISCOS:
-                return RISCOS_EMUL;
-
-        default:
-                return NULL;
-        }
-}
+#define __emul_prefix() NULL
 
 #endif /* _ASM_NAMEI_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 301ff2f28012..d3be83436070 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -172,4 +172,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+extern int pci_probe_only;
+extern unsigned int pcibios_max_latency;
+
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
deleted file mode 100644
index 8121a9a75bfd..000000000000
--- a/include/asm-mips/prctl.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * IRIX prctl interface
- *
- * The IRIX kernel maps a page at PRDA_ADDRESS with the
- * contents of prda and fills it the bits on prda_sys.
- */
-
-#ifndef __PRCTL_H__
-#define __PRCTL_H__
-
-#define PRDA_ADDRESS 0x200000L
-#define PRDA ((struct prda *) PRDA_ADDRESS)
-
-struct prda_sys {
-        pid_t t_pid;
-        u32   t_hint;
-        u32   t_dlactseq;
-        u32   t_fpflags;
-        u32   t_prid;           /* processor type, $prid CP0 register */
-        u32   t_dlendseq;
-        u64   t_unused1[5];
-        pid_t t_rpid;
-        s32   t_resched;
-        u32   t_unused[8];
-        u32   t_cpu;            /* current/last cpu */
-
-        /* FIXME: The signal information, not supported by Linux now */
-        u32   t_flags;          /* if true, then the sigprocmask is in userspace */
-        u32   t_sigprocmask [1]; /* the sigprocmask */
-};
-
-struct prda {
-        char fill [0xe00];
-        struct prda_sys prda_sys;
-};
-
-#define t_sys           prda_sys
-
-ptrdiff_t prctl(int op, int v1, int v2);
-
-#endif
diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h
index 70009a902639..883f59bfa097 100644
--- a/include/asm-mips/setup.h
+++ b/include/asm-mips/setup.h
@@ -3,4 +3,6 @@
 
 #define COMMAND_LINE_SIZE       256
 
+extern void setup_early_printk(void);
+
 #endif /* __SETUP_H */
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 7a28989f7ee3..bee5153aca48 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -119,9 +119,6 @@ struct sigaction {
 
 struct k_sigaction {
         struct sigaction sa;
-#ifdef CONFIG_BINFMT_IRIX
-        void            (*sa_restorer)(void);
-#endif
 };
 
 /* IRIX compatible stack_t  */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 84fef1aeec0c..0ff5b523ea77 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -35,16 +35,6 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define NO_PROC_ID      (-1)
 
-struct call_data_struct {
-        void            (*func)(void *);
-        void            *info;
-        atomic_t        started;
-        atomic_t        finished;
-        int             wait;
-};
-
-extern struct call_data_struct *call_data;
-
 #define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
 #define SMP_CALL_FUNCTION       0x2
 
@@ -67,4 +57,7 @@ static inline void smp_send_reschedule(int cpu)
 
 extern asmlinkage void smp_call_function_interrupt(void);
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 #endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index e5dbde625ec2..90ff2f497c50 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -24,6 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
-extern void (*board_watchpoint_handler)(struct pt_regs *regs);
 
 #endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
deleted file mode 100644
index 193e80a17c12..000000000000
--- a/include/asm-mips/tx4927/tx4927.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2001-2006 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TX4927_TX4927_H
-#define __ASM_TX4927_TX4927_H
-
-#include <asm/txx9irq.h>
-
-#define TX4927_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
-#define TX4927_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
-
-#define TX4927_IRQ_PIC_BEG  TXX9_IRQ_BASE
-#define TX4927_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
-
-
-#define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
-#define TX4927_IRQ_USER1            (TX4927_IRQ_CP0_BEG+1)
-#define TX4927_IRQ_NEST_PIC_ON_CP0  (TX4927_IRQ_CP0_BEG+2)
-#define TX4927_IRQ_CPU_TIMER        (TX4927_IRQ_CP0_BEG+7)
-
-#define TX4927_IRQ_NEST_EXT_ON_PIC  (TX4927_IRQ_PIC_BEG+3)
-
-#endif /* __ASM_TX4927_TX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
deleted file mode 100644
index 0be77df70f2b..000000000000
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- */
-#ifndef __ASM_TX4927_TX4927_PCI_H
-#define __ASM_TX4927_TX4927_PCI_H
-
-#define TX4927_CCFG_TOE 0x00004000
-#define TX4927_CCFG_WR  0x00008000
-#define TX4927_CCFG_TINTDIS     0x01000000
-
-#define TX4927_PCIMEM      0x08000000
-#define TX4927_PCIMEM_SIZE 0x08000000
-#define TX4927_PCIIO       0x16000000
-#define TX4927_PCIIO_SIZE  0x01000000
-
-#define TX4927_SDRAMC_REG       0xff1f8000
-#define TX4927_EBUSC_REG        0xff1f9000
-#define TX4927_PCIC_REG         0xff1fd000
-#define TX4927_CCFG_REG         0xff1fe000
-#define TX4927_IRC_REG          0xff1ff600
-#define TX4927_NR_TMR   3
-#define TX4927_TMR_REG(ch)      (0xff1ff000 + (ch) * 0x100)
-#define TX4927_CE3      0x17f00000      /* 1M */
-#define TX4927_PCIRESET_ADDR    0xbc00f006
-#define TX4927_PCI_CLK_ADDR     (KSEG1 + TX4927_CE3 + 0x00040020)
-
-#define TX4927_IMSTAT_ADDR(n)   (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
-#define tx4927_imstat_ptr(n)    \
-        ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
-
-/* bits for ISTAT3/IMASK3/IMSTAT3 */
-#define TX4927_INT3B_PCID       0
-#define TX4927_INT3B_PCIC       1
-#define TX4927_INT3B_PCIB       2
-#define TX4927_INT3B_PCIA       3
-#define TX4927_INT3F_PCID       (1 << TX4927_INT3B_PCID)
-#define TX4927_INT3F_PCIC       (1 << TX4927_INT3B_PCIC)
-#define TX4927_INT3F_PCIB       (1 << TX4927_INT3B_PCIB)
-#define TX4927_INT3F_PCIA       (1 << TX4927_INT3B_PCIA)
-
-/* bits for PCI_CLK (S6) */
-#define TX4927_PCI_CLK_HOST     0x80
-#define TX4927_PCI_CLK_MASK     (0x0f << 3)
-#define TX4927_PCI_CLK_33       (0x01 << 3)
-#define TX4927_PCI_CLK_25       (0x04 << 3)
-#define TX4927_PCI_CLK_66       (0x09 << 3)
-#define TX4927_PCI_CLK_50       (0x0c << 3)
-#define TX4927_PCI_CLK_ACK      0x04
-#define TX4927_PCI_CLK_ACE      0x02
-#define TX4927_PCI_CLK_ENDIAN   0x01
-#define TX4927_NR_IRQ_LOCAL     TX4927_IRQ_PIC_BEG
-#define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
-
-#define TX4927_IR_PCIC          16
-#define TX4927_IR_PCIERR        22
-#define TX4927_IR_PCIPMA        23
-#define TX4927_IRQ_IRC_PCIC     (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
-#define TX4927_IRQ_IRC_PCIERR   (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
-#define TX4927_IRQ_IOC1         (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
-#define TX4927_IRQ_IOC_PCID     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
-#define TX4927_IRQ_IOC_PCIC     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
-#define TX4927_IRQ_IOC_PCIB     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
-#define TX4927_IRQ_IOC_PCIA     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
-
-#ifdef _LANGUAGE_ASSEMBLY
-#define _CONST64(c)     c
-#else
-#define _CONST64(c)     c##ull
-
-#include <asm/byteorder.h>
-
-#define tx4927_pcireset_ptr     \
-        ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
-#define tx4927_pci_clk_ptr      \
-        ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
-
-struct tx4927_sdramc_reg {
-        volatile unsigned long long cr[4];
-        volatile unsigned long long unused0[4];
-        volatile unsigned long long tr;
-        volatile unsigned long long unused1[2];
-        volatile unsigned long long cmd;
-};
-
-struct tx4927_ebusc_reg {
-        volatile unsigned long long cr[8];
-};
-
-struct tx4927_ccfg_reg {
-        volatile unsigned long long ccfg;
-        volatile unsigned long long crir;
-        volatile unsigned long long pcfg;
-        volatile unsigned long long tear;
-        volatile unsigned long long clkctr;
-        volatile unsigned long long unused0;
-        volatile unsigned long long garbc;
-        volatile unsigned long long unused1;
-        volatile unsigned long long unused2;
-        volatile unsigned long long ramp;
-};
-
-struct tx4927_pcic_reg {
-        volatile unsigned long pciid;
-        volatile unsigned long pcistatus;
-        volatile unsigned long pciccrev;
-        volatile unsigned long pcicfg1;
-        volatile unsigned long p2gm0plbase;             /* +10 */
-        volatile unsigned long p2gm0pubase;
-        volatile unsigned long p2gm1plbase;
-        volatile unsigned long p2gm1pubase;
-        volatile unsigned long p2gm2pbase;              /* +20 */
-        volatile unsigned long p2giopbase;
-        volatile unsigned long unused0;
-        volatile unsigned long pcisid;
-        volatile unsigned long unused1;         /* +30 */
-        volatile unsigned long pcicapptr;
-        volatile unsigned long unused2;
-        volatile unsigned long pcicfg2;
-        volatile unsigned long g2ptocnt;                /* +40 */
-        volatile unsigned long unused3[15];
-        volatile unsigned long g2pstatus;               /* +80 */
-        volatile unsigned long g2pmask;
-        volatile unsigned long pcisstatus;
-        volatile unsigned long pcimask;
-        volatile unsigned long p2gcfg;          /* +90 */
-        volatile unsigned long p2gstatus;
-        volatile unsigned long p2gmask;
-        volatile unsigned long p2gccmd;
-        volatile unsigned long unused4[24];             /* +a0 */
-        volatile unsigned long pbareqport;              /* +100 */
-        volatile unsigned long pbacfg;
-        volatile unsigned long pbastatus;
-        volatile unsigned long pbamask;
-        volatile unsigned long pbabm;           /* +110 */
-        volatile unsigned long pbacreq;
-        volatile unsigned long pbacgnt;
-        volatile unsigned long pbacstate;
-        volatile unsigned long long g2pmgbase[3];               /* +120 */
-        volatile unsigned long long g2piogbase;
-        volatile unsigned long g2pmmask[3];             /* +140 */
-        volatile unsigned long g2piomask;
-        volatile unsigned long long g2pmpbase[3];               /* +150 */
-        volatile unsigned long long g2piopbase;
-        volatile unsigned long pciccfg;         /* +170 */
-        volatile unsigned long pcicstatus;
-        volatile unsigned long pcicmask;
-        volatile unsigned long unused5;
-        volatile unsigned long long p2gmgbase[3];               /* +180 */
-        volatile unsigned long long p2giogbase;
-        volatile unsigned long g2pcfgadrs;              /* +1a0 */
-        volatile unsigned long g2pcfgdata;
-        volatile unsigned long unused6[8];
-        volatile unsigned long g2pintack;
-        volatile unsigned long g2pspc;
-        volatile unsigned long unused7[12];             /* +1d0 */
-        volatile unsigned long long pdmca;              /* +200 */
-        volatile unsigned long long pdmga;
-        volatile unsigned long long pdmpa;
-        volatile unsigned long long pdmcut;
-        volatile unsigned long long pdmcnt;             /* +220 */
-        volatile unsigned long long pdmsts;
-        volatile unsigned long long unused8[2];
-        volatile unsigned long long pdmdb[4];           /* +240 */
-        volatile unsigned long long pdmtdh;             /* +260 */
-        volatile unsigned long long pdmdms;
-};
-
-#endif /* _LANGUAGE_ASSEMBLY */
-
-/*
- * PCIC
- */
-
-/* bits for G2PSTATUS/G2PMASK */
-#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
-#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
-#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
-
-/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
-#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
-
-/* bits for PBACFG */
-#define TX4927_PCIC_PBACFG_RPBA 0x00000004
-#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
-#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
-
-/* bits for G2PMnGBASE */
-#define TX4927_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4927_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for G2PIOGBASE */
-#define TX4927_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4927_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for PCICSTATUS/PCICMASK */
-#define TX4927_PCIC_PCICSTATUS_ALL      0x000007dc
-
-/* bits for PCICCFG */
-#define TX4927_PCIC_PCICCFG_LBWC_MASK   0x0fff0000
-#define TX4927_PCIC_PCICCFG_HRST        0x00000800
-#define TX4927_PCIC_PCICCFG_SRST        0x00000400
-#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
-#define TX4927_PCIC_PCICCFG_IMSE0       0x00000100
-#define TX4927_PCIC_PCICCFG_IMSE1       0x00000080
-#define TX4927_PCIC_PCICCFG_IMSE2       0x00000040
-#define TX4927_PCIC_PCICCFG_IISE        0x00000020
-#define TX4927_PCIC_PCICCFG_ATR 0x00000010
-#define TX4927_PCIC_PCICCFG_ICAE        0x00000008
-
-/* bits for P2GMnGBASE */
-#define TX4927_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
-#define TX4927_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4927_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
-
-/* bits for P2GIOGBASE */
-#define TX4927_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
-#define TX4927_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4927_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
-
-#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
-#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4927_CCFG_PCI66       0x00800000
-#define TX4927_CCFG_PCIMIDE     0x00400000
-#define TX4927_CCFG_PCIXARB     0x00002000
-#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
-#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
-#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
-#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
-#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
-
-#define TX4937_CCFG_PCIDIVMODE_MASK     0x00001c00
-#define TX4937_CCFG_PCIDIVMODE_8        0x00000000
-#define TX4937_CCFG_PCIDIVMODE_4        0x00000400
-#define TX4937_CCFG_PCIDIVMODE_9        0x00000800
-#define TX4937_CCFG_PCIDIVMODE_4_5      0x00000c00
-#define TX4937_CCFG_PCIDIVMODE_10       0x00001000
-#define TX4937_CCFG_PCIDIVMODE_5        0x00001400
-#define TX4937_CCFG_PCIDIVMODE_11       0x00001800
-#define TX4937_CCFG_PCIDIVMODE_5_5      0x00001c00
-
-/* PCFG : Pin Configuration */
-#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
-#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
-
-/* CLKCTR : Clock Control */
-#define TX4927_CLKCTR_PCICKD    0x00400000
-#define TX4927_CLKCTR_PCIRST    0x00000040
-
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-#define tx4927_sdramcptr        ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
-#define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
-#define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
-#define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
-
-#endif /* _LANGUAGE_ASSEMBLY */
-
-#endif /* __ASM_TX4927_TX4927_PCI_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
new file mode 100644
index 000000000000..d8756660523d
--- /dev/null
+++ b/include/asm-mips/txx9/generic.h
@@ -0,0 +1,41 @@
+/*
+ * linux/include/asm-mips/txx9/generic.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_GENERIC_H
+#define __ASM_TXX9_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/ioport.h>       /* for struct resource */
+
+extern struct resource txx9_ce_res[];
+extern char txx9_pcode_str[8];
+void txx9_reg_res_init(unsigned int pcode, unsigned long base,
+                       unsigned long size);
+
+extern unsigned int txx9_master_clock;
+extern unsigned int txx9_cpu_clock;
+extern unsigned int txx9_gbus_clock;
+
+struct pci_dev;
+struct txx9_board_vec {
+        const char *system;
+        void (*prom_init)(void);
+        void (*mem_setup)(void);
+        void (*irq_setup)(void);
+        void (*time_init)(void);
+        void (*arch_init)(void);
+        void (*device_init)(void);
+#ifdef CONFIG_PCI
+        int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+#endif
+};
+extern struct txx9_board_vec *txx9_board_vec;
+extern int (*txx9_irq_dispatch)(int pending);
+void prom_init_cmdline(void);
+char *prom_getcmdline(void);
+
+#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
index a162268f17df..d6eb1b6a54eb 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -7,10 +7,10 @@
  *
  * Copyright (C) 2000-2001 Toshiba Corporation
  */
-#ifndef __ASM_TX3927_JMR3927_H
-#define __ASM_TX3927_JMR3927_H
+#ifndef __ASM_TXX9_JMR3927_H
+#define __ASM_TXX9_JMR3927_H
 
-#include <asm/jmr3927/tx3927.h>
+#include <asm/txx9/tx3927.h>
 #include <asm/addrspace.h>
 #include <asm/system.h>
 #include <asm/txx9irq.h>
@@ -174,4 +174,9 @@
  *      INT[3:0]
  */
 
-#endif /* __ASM_TX3927_JMR3927_H */
+void jmr3927_prom_init(void);
+void jmr3927_irq_setup(void);
+struct pci_dev;
+int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
new file mode 100644
index 000000000000..d89a45091e24
--- /dev/null
+++ b/include/asm-mips/txx9/pci.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_PCI_H
+#define __ASM_TXX9_PCI_H
+
+#include <linux/pci.h>
+
+extern struct pci_controller txx9_primary_pcic;
+struct pci_controller *
+txx9_alloc_pci_controller(struct pci_controller *pcic,
+                          unsigned long mem_base, unsigned long mem_size,
+                          unsigned long io_base, unsigned long io_size);
+
+int txx9_pci66_check(struct pci_controller *hose, int top_bus,
+                        int current_bus);
+extern int txx9_pci_mem_high __initdata;
+
+extern int txx9_pci_option;
+#define TXX9_PCI_OPT_PICMG      0x0002
+#define TXX9_PCI_OPT_CLK_33     0x0008
+#define TXX9_PCI_OPT_CLK_66     0x0010
+#define TXX9_PCI_OPT_CLK_MASK   \
+        (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
+#define TXX9_PCI_OPT_CLK_AUTO   TXX9_PCI_OPT_CLK_MASK
+
+enum txx9_pci_err_action {
+        TXX9_PCI_ERR_REPORT,
+        TXX9_PCI_ERR_IGNORE,
+        TXX9_PCI_ERR_PANIC,
+};
+extern enum txx9_pci_err_action txx9_pci_err_action;
+
+#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index b188a659ce02..bf194589216f 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -24,18 +24,42 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H
-#define __ASM_TX4927_TOSHIBA_RBTX4927_H
+#ifndef __ASM_TXX9_RBTX4927_H
+#define __ASM_TXX9_RBTX4927_H
 
-#include <asm/tx4927/tx4927.h>
-#ifdef CONFIG_PCI
-#include <asm/tx4927/tx4927_pci.h>
-#endif
+#include <asm/txx9/tx4927.h>
+
+#define RBTX4927_PCIMEM         0x08000000
+#define RBTX4927_PCIMEM_SIZE    0x08000000
+#define RBTX4927_PCIIO          0x16000000
+#define RBTX4927_PCIIO_SIZE     0x01000000
+
+#define rbtx4927_pcireset_addr  ((__u8 __iomem *)0xbc00f006UL)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4927_INTB_PCID      0
+#define RBTX4927_INTB_PCIC      1
+#define RBTX4927_INTB_PCIB      2
+#define RBTX4927_INTB_PCIA      3
+#define RBTX4927_INTF_PCID      (1 << RBTX4927_INTB_PCID)
+#define RBTX4927_INTF_PCIC      (1 << RBTX4927_INTB_PCIC)
+#define RBTX4927_INTF_PCIB      (1 << RBTX4927_INTB_PCIB)
+#define RBTX4927_INTF_PCIA      (1 << RBTX4927_INTB_PCIA)
+
+#define RBTX4927_NR_IRQ_IOC     8       /* IOC */
+
+#define RBTX4927_IRQ_IOC        (TXX9_IRQ_BASE + TX4927_NUM_IR)
+#define RBTX4927_IRQ_IOC_PCID   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
+#define RBTX4927_IRQ_IOC_PCIC   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
+#define RBTX4927_IRQ_IOC_PCIB   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
+#define RBTX4927_IRQ_IOC_PCIA   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
+
+#define RBTX4927_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4927_IR_INT(1))
 
 #ifdef CONFIG_PCI
-#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
+#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
 #else
-#define TBTX4927_ISA_IO_OFFSET 0
+#define RBTX4927_ISA_IO_OFFSET 0
 #endif
 
 #define RBTX4927_SW_RESET_DO         (void __iomem *)0xbc00f000UL
@@ -44,10 +68,12 @@
 #define RBTX4927_SW_RESET_ENABLE     (void __iomem *)0xbc00f002UL
 #define RBTX4927_SW_RESET_ENABLE_SET            0x01
 
+#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
+#define RBTX4927_RTL_8019_IRQ  (TXX9_IRQ_BASE + TX4927_IR_INT(3))
 
-#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
-#define RBTX4927_RTL_8019_IRQ  (TX4927_IRQ_PIC_BEG + 5)
-
-int toshiba_rbtx4927_irq_nested(int sw_irq);
+void rbtx4927_prom_init(void);
+void rbtx4927_irq_setup(void);
+struct pci_dev;
+int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 
-#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
+#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
index dfed7beb533f..2f5d5e705a41 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -1,5 +1,4 @@
 /*
- * linux/include/asm-mips/tx4938/rbtx4938.h
  * Definitions for TX4937/TX4938
  *
  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
@@ -9,12 +8,12 @@
  *
  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  */
-#ifndef __ASM_TX_BOARDS_RBTX4938_H
-#define __ASM_TX_BOARDS_RBTX4938_H
+#ifndef __ASM_TXX9_RBTX4938_H
+#define __ASM_TXX9_RBTX4938_H
 
 #include <asm/addrspace.h>
-#include <asm/tx4938/tx4938.h>
 #include <asm/txx9irq.h>
+#include <asm/txx9/tx4938.h>
 
 /* CS */
 #define RBTX4938_CE0    0x1c000000      /* 64M */
@@ -102,35 +101,12 @@
  * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
  * IRQ hardware is supported.
  */
-#define RBTX4938_NR_IRQ_LOCAL   8
-#define RBTX4938_NR_IRQ_IRC     32      /* On-Chip IRC */
 #define RBTX4938_NR_IRQ_IOC     8
 
-#define TX4938_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
-#define TX4938_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
-
-#define TX4938_IRQ_PIC_BEG  TXX9_IRQ_BASE
-#define TX4938_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
-#define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
-#define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
-#define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
-#define TX4938_IRQ_USER1            (TX4938_IRQ_CP0_BEG+1)
-#define TX4938_IRQ_CPU_TIMER        (TX4938_IRQ_CP0_BEG+7)
-
-#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG   0
-#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END   7
-
-#define TOSHIBA_RBTX4938_IRQ_IOC_BEG  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
-#define TOSHIBA_RBTX4938_IRQ_IOC_END  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
-#define RBTX4938_IRQ_LOCAL      TX4938_IRQ_CP0_BEG
-#define RBTX4938_IRQ_IRC        (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
-#define RBTX4938_IRQ_IOC        (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
+#define RBTX4938_IRQ_IRC        TXX9_IRQ_BASE
+#define RBTX4938_IRQ_IOC        (TXX9_IRQ_BASE + TX4938_NUM_IR)
 #define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
 
-#define RBTX4938_IRQ_LOCAL_SOFT0        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
-#define RBTX4938_IRQ_LOCAL_SOFT1        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
-#define RBTX4938_IRQ_LOCAL_IRC  (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
-#define RBTX4938_IRQ_LOCAL_TIMER        (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
 #define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
 #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
 #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
@@ -158,11 +134,16 @@
 
 
 /* IOC (PCI, etc) */
-#define RBTX4938_IRQ_IOCINT     (TX4938_IRQ_NEST_EXT_ON_PIC)
+#define RBTX4938_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4938_IR_INT(0))
 /* Onboard 10M Ether */
-#define RBTX4938_IRQ_ETHER      (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
+#define RBTX4938_IRQ_ETHER      (TXX9_IRQ_BASE + TX4938_IR_INT(1))
 
 #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
 #define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
 
-#endif /* __ASM_TX_BOARDS_RBTX4938_H */
+void rbtx4938_prom_init(void);
+void rbtx4938_irq_setup(void);
+struct pci_dev;
+int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
index 5d93bab51254..9375e4fc2289 100644
--- a/include/asm-mips/tx4927/smsc_fdc37m81x.h
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -1,6 +1,4 @@
 /*
- * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
- *
  * Interface for smsc fdc48m81x Super IO chip
  *
  * Author: MontaVista Software, Inc. source@mvista.com
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/txx9/spi.h
index 6a60c83e152b..ddfb2a0dc432 100644
--- a/include/asm-mips/tx4938/spi.h
+++ b/include/asm-mips/txx9/spi.h
@@ -1,5 +1,4 @@
 /*
- * linux/include/asm-mips/tx4938/spi.h
  * Definitions for TX4937/TX4938 SPI
  *
  * Copyright (C) 2000-2001 Toshiba Corporation
@@ -11,10 +10,10 @@
  *
  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  */
-#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
-#define __ASM_TX_BOARDS_TX4938_SPI_H
+#ifndef __ASM_TXX9_SPI_H
+#define __ASM_TXX9_SPI_H
 
 extern int spi_eeprom_register(int chipid);
 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
 
-#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
+#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/txx9/tx3927.h
index fb580333c102..ca414c7624e1 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -5,10 +5,10 @@
  *
  * Copyright (C) 2000 Toshiba Corporation
  */
-#ifndef __ASM_TX3927_H
-#define __ASM_TX3927_H
+#ifndef __ASM_TXX9_TX3927_H
+#define __ASM_TXX9_TX3927_H
 
-#include <asm/jmr3927/txx927.h>
+#include <asm/txx9/txx927.h>
 
 #define TX3927_SDRAMC_REG       0xfffe8000
 #define TX3927_ROMC_REG         0xfffe9000
@@ -316,4 +316,8 @@ struct tx3927_ccfg_reg {
 #define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
 #define tx3927_pioptr           ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
 
-#endif /* __ASM_TX3927_H */
+struct pci_controller;
+void __init tx3927_pcic_setup(struct pci_controller *channel,
+                              unsigned long sdram_size, int extarb);
+
+#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
new file mode 100644
index 000000000000..46d60afc038b
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927.h
@@ -0,0 +1,219 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2006 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_TX4927_H
+#define __ASM_TXX9_TX4927_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4927pcic.h>
+
+#define TX4927_SDRAMC_REG       0xff1f8000
+#define TX4927_EBUSC_REG        0xff1f9000
+#define TX4927_PCIC_REG         0xff1fd000
+#define TX4927_CCFG_REG         0xff1fe000
+#define TX4927_IRC_REG          0xff1ff600
+#define TX4927_NR_TMR   3
+#define TX4927_TMR_REG(ch)      (0xff1ff000 + (ch) * 0x100)
+
+#define TX4927_IR_INT(n)        (2 + (n))
+#define TX4927_IR_SIO(n)        (8 + (n))
+#define TX4927_IR_PCIC          16
+#define TX4927_IR_PCIERR        22
+#define TX4927_NUM_IR   32
+
+#define TX4927_IRC_INT  2       /* IP[2] in Status register */
+
+struct tx4927_sdramc_reg {
+        volatile unsigned long long cr[4];
+        volatile unsigned long long unused0[4];
+        volatile unsigned long long tr;
+        volatile unsigned long long unused1[2];
+        volatile unsigned long long cmd;
+};
+
+struct tx4927_ebusc_reg {
+        volatile unsigned long long cr[8];
+};
+
+struct tx4927_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+};
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4927_CCFG_WDRST       0x0000020000000000ULL
+#define TX4927_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4927_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4927_CCFG_TINTDIS     0x01000000
+#define TX4927_CCFG_PCI66       0x00800000
+#define TX4927_CCFG_PCIMODE     0x00400000
+#define TX4927_CCFG_DIVMODE_MASK        0x000e0000
+#define TX4927_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4927_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4927_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4927_CCFG_DIVMODE_10  (0x3 << 17)
+#define TX4927_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4927_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4927_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
+#define TX4927_CCFG_BEOW        0x00010000
+#define TX4927_CCFG_WR  0x00008000
+#define TX4927_CCFG_TOE 0x00004000
+#define TX4927_CCFG_PCIARB      0x00002000
+#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
+#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
+#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
+#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
+#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
+#define TX4927_CCFG_SYSSP_MASK  0x000000c0
+#define TX4927_CCFG_ENDIAN      0x00000004
+#define TX4927_CCFG_HALT        0x00000002
+#define TX4927_CCFG_ACEHOLD     0x00000001
+#define TX4927_CCFG_W1CBITS     (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
+
+/* PCFG : Pin Configuration */
+#define TX4927_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4927_PCFG_SYSCLKEN    0x08000000
+#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4927_PCFG_SEL2        0x00000200
+#define TX4927_PCFG_SEL1        0x00000100
+#define TX4927_PCFG_DMASEL_ALL  0x000000ff
+#define TX4927_PCFG_DMASEL0_MASK        0x00000003
+#define TX4927_PCFG_DMASEL1_MASK        0x0000000c
+#define TX4927_PCFG_DMASEL2_MASK        0x00000030
+#define TX4927_PCFG_DMASEL3_MASK        0x000000c0
+#define TX4927_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4927_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4927_PCFG_DMASEL0_ACL0        0x00000002
+#define TX4927_PCFG_DMASEL0_ACL2        0x00000003
+#define TX4927_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4927_PCFG_DMASEL1_SIO1        0x00000004
+#define TX4927_PCFG_DMASEL1_ACL1        0x00000008
+#define TX4927_PCFG_DMASEL1_ACL3        0x0000000c
+#define TX4927_PCFG_DMASEL2_DRQ2        0x00000000      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_SIO0        0x00000010      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_ACL1        0x00000000      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL2        0x00000020      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL0        0x00000030      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4927_PCFG_DMASEL3_SIO0        0x00000040
+#define TX4927_PCFG_DMASEL3_ACL3        0x00000080
+#define TX4927_PCFG_DMASEL3_ACL1        0x000000c0
+
+/* CLKCTR : Clock Control */
+#define TX4927_CLKCTR_ACLCKD    0x02000000
+#define TX4927_CLKCTR_PIOCKD    0x01000000
+#define TX4927_CLKCTR_DMACKD    0x00800000
+#define TX4927_CLKCTR_PCICKD    0x00400000
+#define TX4927_CLKCTR_TM0CKD    0x00100000
+#define TX4927_CLKCTR_TM1CKD    0x00080000
+#define TX4927_CLKCTR_TM2CKD    0x00040000
+#define TX4927_CLKCTR_SIO0CKD   0x00020000
+#define TX4927_CLKCTR_SIO1CKD   0x00010000
+#define TX4927_CLKCTR_ACLRST    0x00000200
+#define TX4927_CLKCTR_PIORST    0x00000100
+#define TX4927_CLKCTR_DMARST    0x00000080
+#define TX4927_CLKCTR_PCIRST    0x00000040
+#define TX4927_CLKCTR_TM0RST    0x00000010
+#define TX4927_CLKCTR_TM1RST    0x00000008
+#define TX4927_CLKCTR_TM2RST    0x00000004
+#define TX4927_CLKCTR_SIO0RST   0x00000002
+#define TX4927_CLKCTR_SIO1RST   0x00000001
+
+#define tx4927_sdramcptr        ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
+#define tx4927_pcicptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
+#define tx4927_ccfgptr \
+                ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
+#define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
+
+/* utilities */
+static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) & ~bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) | bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+
+/* These functions are not interrupt safe. */
+static inline void tx4927_ccfg_clear(__u64 bits)
+{
+        ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
+                       & ~(TX4927_CCFG_W1CBITS | bits),
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_set(__u64 bits)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~TX4927_CCFG_W1CBITS) | bits,
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_change(__u64 change, __u64 new)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~(TX4927_CCFG_W1CBITS | change)) |
+                       new,
+                       &tx4927_ccfgptr->ccfg);
+}
+
+int tx4927_report_pciclk(void);
+int tx4927_pciclk66_setup(void);
+void tx4927_irq_init(void);
+
+#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..d61c3d09c4a2
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -0,0 +1,199 @@
+/*
+ * include/asm-mips/txx9/tx4927pcic.h
+ * TX4927 PCI controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_TX4927PCIC_H
+#define __ASM_TXX9_TX4927PCIC_H
+
+#include <linux/pci.h>
+
+struct tx4927_pcic_reg {
+        u32 pciid;
+        u32 pcistatus;
+        u32 pciccrev;
+        u32 pcicfg1;
+        u32 p2gm0plbase;                /* +10 */
+        u32 p2gm0pubase;
+        u32 p2gm1plbase;
+        u32 p2gm1pubase;
+        u32 p2gm2pbase;         /* +20 */
+        u32 p2giopbase;
+        u32 unused0;
+        u32 pcisid;
+        u32 unused1;            /* +30 */
+        u32 pcicapptr;
+        u32 unused2;
+        u32 pcicfg2;
+        u32 g2ptocnt;           /* +40 */
+        u32 unused3[15];
+        u32 g2pstatus;          /* +80 */
+        u32 g2pmask;
+        u32 pcisstatus;
+        u32 pcimask;
+        u32 p2gcfg;             /* +90 */
+        u32 p2gstatus;
+        u32 p2gmask;
+        u32 p2gccmd;
+        u32 unused4[24];                /* +a0 */
+        u32 pbareqport;         /* +100 */
+        u32 pbacfg;
+        u32 pbastatus;
+        u32 pbamask;
+        u32 pbabm;              /* +110 */
+        u32 pbacreq;
+        u32 pbacgnt;
+        u32 pbacstate;
+        u64 g2pmgbase[3];               /* +120 */
+        u64 g2piogbase;
+        u32 g2pmmask[3];                /* +140 */
+        u32 g2piomask;
+        u64 g2pmpbase[3];               /* +150 */
+        u64 g2piopbase;
+        u32 pciccfg;            /* +170 */
+        u32 pcicstatus;
+        u32 pcicmask;
+        u32 unused5;
+        u64 p2gmgbase[3];               /* +180 */
+        u64 p2giogbase;
+        u32 g2pcfgadrs;         /* +1a0 */
+        u32 g2pcfgdata;
+        u32 unused6[8];
+        u32 g2pintack;
+        u32 g2pspc;
+        u32 unused7[12];                /* +1d0 */
+        u64 pdmca;              /* +200 */
+        u64 pdmga;
+        u64 pdmpa;
+        u64 pdmctr;
+        u64 pdmcfg;             /* +220 */
+        u64 pdmsts;
+};
+
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci_regs.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci_regs.h */
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
+#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
+
+/* bits for PBACFG */
+#define TX4927_PCIC_PBACFG_FIXPA        0x00000008
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
+
+/* bits for PBASTATUS/PBAMASK */
+#define TX4927_PCIC_PBASTATUS_ALL       0x00000001
+#define TX4927_PCIC_PBASTATUS_BM        0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4927_PCIC_G2PMnGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PMnGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for G2PIOGBASE */
+#define TX4927_PCIC_G2PIOGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PIOGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4927_PCIC_PCICSTATUS_ALL      0x000007b8
+#define TX4927_PCIC_PCICSTATUS_PME      0x00000400
+#define TX4927_PCIC_PCICSTATUS_TLB      0x00000200
+#define TX4927_PCIC_PCICSTATUS_NIB      0x00000100
+#define TX4927_PCIC_PCICSTATUS_ZIB      0x00000080
+#define TX4927_PCIC_PCICSTATUS_PERR     0x00000020
+#define TX4927_PCIC_PCICSTATUS_SERR     0x00000010
+#define TX4927_PCIC_PCICSTATUS_GBE      0x00000008
+#define TX4927_PCIC_PCICSTATUS_IWB      0x00000002
+#define TX4927_PCIC_PCICSTATUS_E2PDONE  0x00000001
+
+/* bits for PCICCFG */
+#define TX4927_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
+#define TX4927_PCIC_PCICCFG_HRST        0x00000800
+#define TX4927_PCIC_PCICCFG_SRST        0x00000400
+#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4927_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
+#define TX4927_PCIC_PCICCFG_G2PM0EN     0x00000100
+#define TX4927_PCIC_PCICCFG_G2PM1EN     0x00000080
+#define TX4927_PCIC_PCICCFG_G2PM2EN     0x00000040
+#define TX4927_PCIC_PCICCFG_G2PIOEN     0x00000020
+#define TX4927_PCIC_PCICCFG_TCAR        0x00000010
+#define TX4927_PCIC_PCICCFG_ICAEN       0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4927_PCIC_P2GMnGBASE_TMEMEN   0x0000004000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TECHG    0x0000001000000000ULL
+
+/* bits for P2GIOGBASE */
+#define TX4927_PCIC_P2GIOGBASE_TIOEN    0x0000004000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TECHG    0x0000001000000000ULL
+
+#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/* bits for PDMCFG */
+#define TX4927_PCIC_PDMCFG_RSTFIFO      0x00200000
+#define TX4927_PCIC_PDMCFG_EXFER        0x00100000
+#define TX4927_PCIC_PDMCFG_REQDLY_MASK  0x00003800
+#define TX4927_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_16    (1 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_32    (2 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_64    (3 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_128   (4 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_256   (5 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_512   (6 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
+#define TX4927_PCIC_PDMCFG_ERRIE        0x00000400
+#define TX4927_PCIC_PDMCFG_NCCMPIE      0x00000200
+#define TX4927_PCIC_PDMCFG_NTCMPIE      0x00000100
+#define TX4927_PCIC_PDMCFG_CHNEN        0x00000080
+#define TX4927_PCIC_PDMCFG_XFRACT       0x00000040
+#define TX4927_PCIC_PDMCFG_BSWAP        0x00000020
+#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
+#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
+#define TX4927_PCIC_PDMCFG_XFRDIRC      0x00000002
+#define TX4927_PCIC_PDMCFG_CHRST        0x00000001
+
+/* bits for PDMSTS */
+#define TX4927_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
+#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4927_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
+#define TX4927_PCIC_PDMSTS_FIFORP_MASK  0x00030000
+#define TX4927_PCIC_PDMSTS_ERRINT       0x00000800
+#define TX4927_PCIC_PDMSTS_DONEINT      0x00000400
+#define TX4927_PCIC_PDMSTS_CHNEN        0x00000200
+#define TX4927_PCIC_PDMSTS_XFRACT       0x00000100
+#define TX4927_PCIC_PDMSTS_ACCMP        0x00000080
+#define TX4927_PCIC_PDMSTS_NCCMP        0x00000040
+#define TX4927_PCIC_PDMSTS_NTCMP        0x00000020
+#define TX4927_PCIC_PDMSTS_CFGERR       0x00000008
+#define TX4927_PCIC_PDMSTS_PCIERR       0x00000004
+#define TX4927_PCIC_PDMSTS_CHNERR       0x00000002
+#define TX4927_PCIC_PDMSTS_DATAERR      0x00000001
+#define TX4927_PCIC_PDMSTS_ALL_CMP      0x000000e0
+#define TX4927_PCIC_PDMSTS_ALL_ERR      0x0000000f
+
+struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
+        struct pci_controller *channel);
+void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
+                              struct pci_controller *channel, int extarb);
+void tx4927_report_pcic_status(void);
+
+#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/txx9/tx4938.h
index e8807f5c61e9..12de68a4c10a 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -1,5 +1,4 @@
 /*
- * linux/include/asm-mips/tx4938/tx4938.h
  * Definitions for TX4937/TX4938
  * Copyright (C) 2000-2001 Toshiba Corporation
  *
@@ -10,17 +9,15 @@
  *
  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  */
-#ifndef __ASM_TX_BOARDS_TX4938_H
-#define __ASM_TX_BOARDS_TX4938_H
+#ifndef __ASM_TXX9_TX4938_H
+#define __ASM_TXX9_TX4938_H
+
+/* some controllers are compatible with 4927 */
+#include <asm/txx9/tx4927.h>
 
 #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
 #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
 
-#define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
-
-#define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
-#define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
-
 #define TX4938_PCIIO_0 0x10000000
 #define TX4938_PCIIO_1 0x01010000
 #define TX4938_PCIMEM_0 0x08000000
@@ -52,9 +49,6 @@
 #define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
 #define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
 
-#ifdef __ASSEMBLY__
-#define _CONST64(c)     c
-#else
 #define _CONST64(c)     c##ull
 
 #include <asm/byteorder.h>
@@ -114,68 +108,6 @@ struct tx4938_dma_reg {
         endian_def_l2(unused0, mcr);
 };
 
-struct tx4938_pcic_reg {
-        volatile unsigned long pciid;
-        volatile unsigned long pcistatus;
-        volatile unsigned long pciccrev;
-        volatile unsigned long pcicfg1;
-        volatile unsigned long p2gm0plbase;             /* +10 */
-        volatile unsigned long p2gm0pubase;
-        volatile unsigned long p2gm1plbase;
-        volatile unsigned long p2gm1pubase;
-        volatile unsigned long p2gm2pbase;              /* +20 */
-        volatile unsigned long p2giopbase;
-        volatile unsigned long unused0;
-        volatile unsigned long pcisid;
-        volatile unsigned long unused1;         /* +30 */
-        volatile unsigned long pcicapptr;
-        volatile unsigned long unused2;
-        volatile unsigned long pcicfg2;
-        volatile unsigned long g2ptocnt;                /* +40 */
-        volatile unsigned long unused3[15];
-        volatile unsigned long g2pstatus;               /* +80 */
-        volatile unsigned long g2pmask;
-        volatile unsigned long pcisstatus;
-        volatile unsigned long pcimask;
-        volatile unsigned long p2gcfg;          /* +90 */
-        volatile unsigned long p2gstatus;
-        volatile unsigned long p2gmask;
-        volatile unsigned long p2gccmd;
-        volatile unsigned long unused4[24];             /* +a0 */
-        volatile unsigned long pbareqport;              /* +100 */
-        volatile unsigned long pbacfg;
-        volatile unsigned long pbastatus;
-        volatile unsigned long pbamask;
-        volatile unsigned long pbabm;           /* +110 */
-        volatile unsigned long pbacreq;
-        volatile unsigned long pbacgnt;
-        volatile unsigned long pbacstate;
-        volatile unsigned long long g2pmgbase[3];               /* +120 */
-        volatile unsigned long long g2piogbase;
-        volatile unsigned long g2pmmask[3];             /* +140 */
-        volatile unsigned long g2piomask;
-        volatile unsigned long long g2pmpbase[3];               /* +150 */
-        volatile unsigned long long g2piopbase;
-        volatile unsigned long pciccfg;         /* +170 */
-        volatile unsigned long pcicstatus;
-        volatile unsigned long pcicmask;
-        volatile unsigned long unused5;
-        volatile unsigned long long p2gmgbase[3];               /* +180 */
-        volatile unsigned long long p2giogbase;
-        volatile unsigned long g2pcfgadrs;              /* +1a0 */
-        volatile unsigned long g2pcfgdata;
-        volatile unsigned long unused6[8];
-        volatile unsigned long g2pintack;
-        volatile unsigned long g2pspc;
-        volatile unsigned long unused7[12];             /* +1d0 */
-        volatile unsigned long long pdmca;              /* +200 */
-        volatile unsigned long long pdmga;
-        volatile unsigned long long pdmpa;
-        volatile unsigned long long pdmctr;
-        volatile unsigned long long pdmcfg;             /* +220 */
-        volatile unsigned long long pdmsts;
-};
-
 struct tx4938_aclc_reg {
         volatile unsigned long acctlen;
         volatile unsigned long acctldis;
@@ -263,18 +195,18 @@ struct tx4938_sramc_reg {
 };
 
 struct tx4938_ccfg_reg {
-        volatile unsigned long long ccfg;
-        volatile unsigned long long crir;
-        volatile unsigned long long pcfg;
-        volatile unsigned long long tear;
-        volatile unsigned long long clkctr;
-        volatile unsigned long long unused0;
-        volatile unsigned long long garbc;
-        volatile unsigned long long unused1;
-        volatile unsigned long long unused2;
-        volatile unsigned long long ramp;
-        volatile unsigned long long unused3;
-        volatile unsigned long long jmpadr;
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+        u64 unused3;
+        u64 jmpadr;
 };
 
 #undef endian_def_l2
@@ -283,8 +215,6 @@ struct tx4938_ccfg_reg {
 #undef endian_def_b2s
 #undef endian_def_b4
 
-#endif /* __ASSEMBLY__ */
-
 /*
  * NDFMC
  */
@@ -336,6 +266,8 @@ struct tx4938_ccfg_reg {
 #define TX4938_IR_ETH0  TX4938_IR_INT(4)
 #define TX4938_IR_ETH1  TX4938_IR_INT(3)
 
+#define TX4938_IRC_INT  2       /* IP[2] in Status register */
+
 /*
  * CCFG
  */
@@ -361,7 +293,7 @@ struct tx4938_ccfg_reg {
 #define TX4938_CCFG_BEOW        0x00010000
 #define TX4938_CCFG_WR  0x00008000
 #define TX4938_CCFG_TOE 0x00004000
-#define TX4938_CCFG_PCIXARB     0x00002000
+#define TX4938_CCFG_PCIARB      0x00002000
 #define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
 #define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
 #define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
@@ -437,110 +369,6 @@ struct tx4938_ccfg_reg {
 #define TX4938_CLKCTR_SIO0RST   0x00000002
 #define TX4938_CLKCTR_SIO1RST   0x00000001
 
-/* bits for G2PSTATUS/G2PMASK */
-#define TX4938_PCIC_G2PSTATUS_ALL       0x00000003
-#define TX4938_PCIC_G2PSTATUS_TTOE      0x00000002
-#define TX4938_PCIC_G2PSTATUS_RTOE      0x00000001
-
-/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
-#define TX4938_PCIC_PCISTATUS_ALL       0x0000f900
-
-/* bits for PBACFG */
-#define TX4938_PCIC_PBACFG_FIXPA        0x00000008
-#define TX4938_PCIC_PBACFG_RPBA 0x00000004
-#define TX4938_PCIC_PBACFG_PBAEN        0x00000002
-#define TX4938_PCIC_PBACFG_BMCEN        0x00000001
-
-/* bits for G2PMnGBASE */
-#define TX4938_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4938_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for G2PIOGBASE */
-#define TX4938_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4938_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for PCICSTATUS/PCICMASK */
-#define TX4938_PCIC_PCICSTATUS_ALL      0x000007b8
-#define TX4938_PCIC_PCICSTATUS_PME      0x00000400
-#define TX4938_PCIC_PCICSTATUS_TLB      0x00000200
-#define TX4938_PCIC_PCICSTATUS_NIB      0x00000100
-#define TX4938_PCIC_PCICSTATUS_ZIB      0x00000080
-#define TX4938_PCIC_PCICSTATUS_PERR     0x00000020
-#define TX4938_PCIC_PCICSTATUS_SERR     0x00000010
-#define TX4938_PCIC_PCICSTATUS_GBE      0x00000008
-#define TX4938_PCIC_PCICSTATUS_IWB      0x00000002
-#define TX4938_PCIC_PCICSTATUS_E2PDONE  0x00000001
-
-/* bits for PCICCFG */
-#define TX4938_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
-#define TX4938_PCIC_PCICCFG_HRST        0x00000800
-#define TX4938_PCIC_PCICCFG_SRST        0x00000400
-#define TX4938_PCIC_PCICCFG_IRBER       0x00000200
-#define TX4938_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
-#define TX4938_PCIC_PCICCFG_G2PM0EN     0x00000100
-#define TX4938_PCIC_PCICCFG_G2PM1EN     0x00000080
-#define TX4938_PCIC_PCICCFG_G2PM2EN     0x00000040
-#define TX4938_PCIC_PCICCFG_G2PIOEN     0x00000020
-#define TX4938_PCIC_PCICCFG_TCAR        0x00000010
-#define TX4938_PCIC_PCICCFG_ICAEN       0x00000008
-
-/* bits for P2GMnGBASE */
-#define TX4938_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
-#define TX4938_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4938_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
-
-/* bits for P2GIOGBASE */
-#define TX4938_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
-#define TX4938_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4938_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
-
-#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
-#define TX4938_PCIC_MAX_DEVNU   TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/* bits for PDMCFG */
-#define TX4938_PCIC_PDMCFG_RSTFIFO      0x00200000
-#define TX4938_PCIC_PDMCFG_EXFER        0x00100000
-#define TX4938_PCIC_PDMCFG_REQDLY_MASK  0x00003800
-#define TX4938_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_16    (1 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_32    (2 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_64    (3 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_128   (4 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_256   (5 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_512   (6 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
-#define TX4938_PCIC_PDMCFG_ERRIE        0x00000400
-#define TX4938_PCIC_PDMCFG_NCCMPIE      0x00000200
-#define TX4938_PCIC_PDMCFG_NTCMPIE      0x00000100
-#define TX4938_PCIC_PDMCFG_CHNEN        0x00000080
-#define TX4938_PCIC_PDMCFG_XFRACT       0x00000040
-#define TX4938_PCIC_PDMCFG_BSWAP        0x00000020
-#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
-#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
-#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
-#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
-#define TX4938_PCIC_PDMCFG_XFRDIRC      0x00000002
-#define TX4938_PCIC_PDMCFG_CHRST        0x00000001
-
-/* bits for PDMSTS */
-#define TX4938_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
-#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
-#define TX4938_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
-#define TX4938_PCIC_PDMSTS_FIFORP_MASK  0x00030000
-#define TX4938_PCIC_PDMSTS_ERRINT       0x00000800
-#define TX4938_PCIC_PDMSTS_DONEINT      0x00000400
-#define TX4938_PCIC_PDMSTS_CHNEN        0x00000200
-#define TX4938_PCIC_PDMSTS_XFRACT       0x00000100
-#define TX4938_PCIC_PDMSTS_ACCMP        0x00000080
-#define TX4938_PCIC_PDMSTS_NCCMP        0x00000040
-#define TX4938_PCIC_PDMSTS_NTCMP        0x00000020
-#define TX4938_PCIC_PDMSTS_CFGERR       0x00000008
-#define TX4938_PCIC_PDMSTS_PCIERR       0x00000004
-#define TX4938_PCIC_PDMSTS_CHNERR       0x00000002
-#define TX4938_PCIC_PDMSTS_DATAERR      0x00000001
-#define TX4938_PCIC_PDMSTS_ALL_CMP      0x000000e0
-#define TX4938_PCIC_PDMSTS_ALL_ERR      0x0000000f
-
 /*
  * DMA
  */
@@ -596,15 +424,15 @@ struct tx4938_ccfg_reg {
 #define TX4938_DMA_CSR_DESERR   0x00000002
 #define TX4938_DMA_CSR_SORERR   0x00000001
 
-#ifndef __ASSEMBLY__
-
 #define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 #define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 #define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
-#define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
-#define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
-#define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
+#define tx4938_pcicptr          tx4927_pcicptr
+#define tx4938_pcic1ptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr \
+                ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
 #define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
 #define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
 #define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
@@ -612,17 +440,26 @@ struct tx4938_ccfg_reg {
 #define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
 
 
-#define TX4938_REV_MAJ_MIN()    ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
-#define TX4938_REV_PCODE()      ((unsigned long)tx4938_ccfgptr->crir >> 16)
+#define TX4938_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
+
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
 
 #define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
 #define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
 
+#define TX4938_EBUSC_CR(ch)     __raw_readq(&tx4938_ebuscptr->cr[(ch)])
 #define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
 #define TX4938_EBUSC_SIZE(ch)   \
         (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
 
-
-#endif /* !__ASSEMBLY__ */
+int tx4938_report_pciclk(void);
+void tx4938_report_pci1clk(void);
+int tx4938_pciclk66_setup(void);
+struct pci_dev;
+int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+void tx4938_irq_init(void);
 
 #endif
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/txx9/txx927.h
index 25dcf2feb095..97dd7ad1a890 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/txx9/txx927.h
@@ -7,8 +7,8 @@
  *
  * Copyright (C) 2000 Toshiba Corporation
  */
-#ifndef __ASM_TXX927_H
-#define __ASM_TXX927_H
+#ifndef __ASM_TXX9_TXX927_H
+#define __ASM_TXX9_TXX927_H
 
 struct txx927_sio_reg {
         volatile unsigned long lcr;
@@ -118,4 +118,4 @@ struct txx927_sio_reg {
  * PIO
  */
 
-#endif /* __ASM_TXX927_H */
+#endif /* __ASM_TXX9_TXX927_H */
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h
deleted file mode 100644
index 42300037d593..000000000000
--- a/include/asm-mips/vr41xx/cmbvr4133.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * include/asm-mips/vr41xx/cmbvr4133.h
- *
- * Include file for NEC CMB-VR4133.
- *
- * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
- *         Jun Sun <jsun@mvista.com, or source@mvista.com> and
- *         Alex Sapkov <asapkov@ru.mvista.com>
- *
- * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __NEC_CMBVR4133_H
-#define __NEC_CMBVR4133_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define CMBVR41XX_INTA_PIN              1
-#define CMBVR41XX_INTB_PIN              1
-#define CMBVR41XX_INTC_PIN              3
-#define CMBVR41XX_INTD_PIN              1
-#define CMBVR41XX_INTE_PIN              1
-
-/*
- * Interrupt Number
- */
-#define CMBVR41XX_INTA_IRQ              GIU_IRQ(CMBVR41XX_INTA_PIN)
-#define CMBVR41XX_INTB_IRQ              GIU_IRQ(CMBVR41XX_INTB_PIN)
-#define CMBVR41XX_INTC_IRQ              GIU_IRQ(CMBVR41XX_INTC_PIN)
-#define CMBVR41XX_INTD_IRQ              GIU_IRQ(CMBVR41XX_INTD_PIN)
-#define CMBVR41XX_INTE_IRQ              GIU_IRQ(CMBVR41XX_INTE_PIN)
-
-#define I8259A_IRQ_BASE                 72
-#define I8259_IRQ(x)                    (I8259A_IRQ_BASE + (x))
-#define TIMER_IRQ                       I8259_IRQ(0)
-#define KEYBOARD_IRQ                    I8259_IRQ(1)
-#define I8259_SLAVE_IRQ                 I8259_IRQ(2)
-#define UART3_IRQ                       I8259_IRQ(3)
-#define UART1_IRQ                       I8259_IRQ(4)
-#define UART2_IRQ                       I8259_IRQ(5)
-#define FDC_IRQ                         I8259_IRQ(6)
-#define PARPORT_IRQ                     I8259_IRQ(7)
-#define RTC_IRQ                         I8259_IRQ(8)
-#define USB_IRQ                         I8259_IRQ(9)
-#define I8259_INTA_IRQ                  I8259_IRQ(10)
-#define AUDIO_IRQ                       I8259_IRQ(11)
-#define AUX_IRQ                         I8259_IRQ(12)
-#define IDE_PRIMARY_IRQ                 I8259_IRQ(14)
-#define IDE_SECONDARY_IRQ               I8259_IRQ(15)
-
-#endif /* __NEC_CMBVR4133_H */
diff --git a/include/asm-parisc/smp.h b/include/asm-parisc/smp.h
index 306f4950e32e..398cdbaf4e54 100644
--- a/include/asm-parisc/smp.h
+++ b/include/asm-parisc/smp.h
@@ -30,6 +30,9 @@ extern cpumask_t cpu_online_map;
 extern void smp_send_reschedule(int cpu);
 extern void smp_send_all_nop(void);
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 #endif /* !ASSEMBLY */
 
 /*
diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
index bca352e033c3..04ce8f8a2ee7 100644
--- a/include/asm-powerpc/Kbuild
+++ b/include/asm-powerpc/Kbuild
@@ -2,7 +2,6 @@ include include/asm-generic/Kbuild.asm
 
 header-y += auxvec.h
 header-y += ioctls.h
-header-y += mman.h
 header-y += sembuf.h
 header-y += siginfo.h
 header-y += stat.h
@@ -23,7 +22,6 @@ header-y += sigcontext.h
 header-y += statfs.h
 header-y += ps3fb.h
 
-unifdef-y += asm-compat.h
 unifdef-y += bootx.h
 unifdef-y += byteorder.h
 unifdef-y += cputable.h
diff --git a/include/asm-powerpc/asm-compat.h b/include/asm-powerpc/asm-compat.h
index c19e7367fce6..8ec2e1da68bf 100644
--- a/include/asm-powerpc/asm-compat.h
+++ b/include/asm-powerpc/asm-compat.h
@@ -15,57 +15,6 @@
 #endif
 
 
-/*
- * Feature section common macros
- *
- * Note that the entries now contain offsets between the table entry
- * and the code rather than absolute code pointers in order to be
- * useable with the vdso shared library. There is also an assumption
- * that values will be negative, that is, the fixup table has to be
- * located after the code it fixes up.
- */
-#ifdef CONFIG_PPC64
-#ifdef __powerpc64__
-/* 64 bits kernel, 64 bits code */
-#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)   \
-99:                                                     \
-        .section sect,"a";                              \
-        .align 3;                                       \
-98:                                                     \
-        .llong msk;                                     \
-        .llong val;                                     \
-        .llong label##b-98b;                            \
-        .llong 99b-98b;                                 \
-        .previous
-#else /* __powerpc64__ */
-/* 64 bits kernel, 32 bits code (ie. vdso32) */
-#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)   \
-99:                                                     \
-        .section sect,"a";                              \
-        .align 3;                                       \
-98:                                                     \
-        .llong msk;                                     \
-        .llong val;                                     \
-        .long 0xffffffff;                               \
-        .long label##b-98b;                             \
-        .long 0xffffffff;                               \
-        .long 99b-98b;                                  \
-        .previous
-#endif /* !__powerpc64__ */
-#else /* CONFIG_PPC64 */
-/* 32 bits kernel, 32 bits code */
-#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)   \
-99:                                                     \
-        .section sect,"a";                              \
-        .align 2;                                       \
-98:                                                     \
-        .long msk;                                      \
-        .long val;                                      \
-        .long label##b-98b;                             \
-        .long 99b-98b;                                  \
-        .previous
-#endif /* !CONFIG_PPC64 */
-
 #ifdef __powerpc64__
 
 /* operations for longs and pointers */
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
index 53507046a1b1..81de6eb3455d 100644
--- a/include/asm-powerpc/cache.h
+++ b/include/asm-powerpc/cache.h
@@ -8,6 +8,9 @@
 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
 #define L1_CACHE_SHIFT          4
 #define MAX_COPY_PREFETCH       1
+#elif defined(CONFIG_PPC_E500MC)
+#define L1_CACHE_SHIFT          6
+#define MAX_COPY_PREFETCH       4
 #elif defined(CONFIG_PPC32)
 #define L1_CACHE_SHIFT          5
 #define MAX_COPY_PREFETCH       4
diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h
new file mode 100644
index 000000000000..107d9b915e33
--- /dev/null
+++ b/include/asm-powerpc/code-patching.h
@@ -0,0 +1,54 @@
+#ifndef _ASM_POWERPC_CODE_PATCHING_H
+#define _ASM_POWERPC_CODE_PATCHING_H
+
+/*
+ * Copyright 2008, Michael Ellerman, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/types.h>
+
+#define PPC_NOP_INSTR           0x60000000
+#define PPC_LWSYNC_INSTR        0x7c2004ac
+
+/* Flags for create_branch:
+ * "b"   == create_branch(addr, target, 0);
+ * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
+ * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
+ * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
+ */
+#define BRANCH_SET_LINK 0x1
+#define BRANCH_ABSOLUTE 0x2
+
+unsigned int create_branch(const unsigned int *addr,
+                           unsigned long target, int flags);
+unsigned int create_cond_branch(const unsigned int *addr,
+                                unsigned long target, int flags);
+void patch_branch(unsigned int *addr, unsigned long target, int flags);
+void patch_instruction(unsigned int *addr, unsigned int instr);
+
+int instr_is_relative_branch(unsigned int instr);
+int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
+unsigned long branch_target(const unsigned int *instr);
+unsigned int translate_branch(const unsigned int *dest,
+                              const unsigned int *src);
+
+static inline unsigned long ppc_function_entry(void *func)
+{
+#ifdef CONFIG_PPC64
+        /*
+         * On PPC64 the function pointer actually points to the function's
+         * descriptor. The first entry in the descriptor is the address
+         * of the function text.
+         */
+        return ((func_descr_t *)func)->entry;
+#else
+        return (unsigned long)func;
+#endif
+}
+
+#endif /* _ASM_POWERPC_CODE_PATCHING_H */
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index ede38ffe466a..63a55337c2de 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -96,6 +96,7 @@ unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
 int cpm_muram_free(unsigned long offset);
 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
 void __iomem *cpm_muram_addr(unsigned long offset);
+unsigned long cpm_muram_offset(void __iomem *addr);
 dma_addr_t cpm_muram_dma(void __iomem *addr);
 int cpm_command(u32 command, u8 opcode);
 
diff --git a/include/asm-powerpc/cpm1.h b/include/asm-powerpc/cpm1.h
index 3df439678006..2ff798744c1d 100644
--- a/include/asm-powerpc/cpm1.h
+++ b/include/asm-powerpc/cpm1.h
@@ -42,35 +42,15 @@
 
 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-/* The dual ported RAM is multi-functional.  Some areas can be (and are
- * being) used for microcode.  There is an area that can only be used
- * as data ram for buffer descriptors, which is all we use right now.
- * Currently the first 512 and last 256 bytes are used for microcode.
- */
-#define CPM_DATAONLY_BASE       ((uint)0x0800)
-#define CPM_DATAONLY_SIZE       ((uint)0x0700)
-#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
-#endif
-
 /* Export the base address of the communication processor registers
  * and dual port ram.
  */
 extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
 
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
 #define cpm_dpalloc cpm_muram_alloc
 #define cpm_dpfree cpm_muram_free
 #define cpm_dpram_addr cpm_muram_addr
 #define cpm_dpram_phys cpm_muram_dma
-#else
-extern unsigned long cpm_dpalloc(uint size, uint align);
-extern int cpm_dpfree(unsigned long offset);
-extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
-extern void cpm_dpdump(void);
-extern void *cpm_dpram_addr(unsigned long offset);
-extern uint cpm_dpram_phys(u8 *addr);
-#endif
 
 extern void cpm_setbrg(uint brg, uint rate);
 
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
index 4c85ed9cd43f..2c7fd9cee291 100644
--- a/include/asm-powerpc/cpm2.h
+++ b/include/asm-powerpc/cpm2.h
@@ -78,24 +78,6 @@
 #define mk_cr_cmd(PG, SBC, MCN, OP) \
         ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE       ((uint)128)
-#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
-#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
-#define CPM_DATAONLY_SIZE       ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE    ((uint)0x00009000)
-#else
-#define CPM_DATAONLY_SIZE       ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE    ((uint)0x0000b000)
-#endif
-#endif
-
 /* The number of pages of host memory we allocate for CPM.  This is
  * done early in kernel initialization to get physically contiguous
  * pages.
@@ -107,17 +89,9 @@
  */
 extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
 
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
 #define cpm_dpalloc cpm_muram_alloc
 #define cpm_dpfree cpm_muram_free
 #define cpm_dpram_addr cpm_muram_addr
-#else
-extern unsigned long cpm_dpalloc(uint size, uint align);
-extern int cpm_dpfree(unsigned long offset);
-extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
-extern void cpm_dpdump(void);
-extern void *cpm_dpram_addr(unsigned long offset);
-#endif
 
 extern void cpm_setbrg(uint brg, uint rate);
 extern void cpm2_fastbrg(uint brg, uint rate, int div16);
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 1e79673b7316..2a3e9075a5a0 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_POWERPC_CPUTABLE_H
 #define __ASM_POWERPC_CPUTABLE_H
 
-#include <asm/asm-compat.h>
-
 #define PPC_FEATURE_32                  0x80000000
 #define PPC_FEATURE_64                  0x40000000
 #define PPC_FEATURE_601_INSTR           0x20000000
@@ -26,11 +24,20 @@
 #define PPC_FEATURE_PA6T                0x00000800
 #define PPC_FEATURE_HAS_DFP             0x00000400
 #define PPC_FEATURE_POWER6_EXT          0x00000200
+#define PPC_FEATURE_ARCH_2_06           0x00000100
+#define PPC_FEATURE_HAS_VSX             0x00000080
+
+#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
+                                        0x00000040
 
 #define PPC_FEATURE_TRUE_LE             0x00000002
 #define PPC_FEATURE_PPC_LE              0x00000001
 
 #ifdef __KERNEL__
+
+#include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
+
 #ifndef __ASSEMBLY__
 
 /* This structure can grow, it's real size is used by head.S code
@@ -132,7 +139,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
-#define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
+#define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
@@ -152,6 +159,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
 #define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
 #define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
+#define CPU_FTR_LWSYNC                  ASM_CONST(0x0000000008000000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -180,6 +188,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 #define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
 #define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
+#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0010000000000000)
+#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -198,6 +208,17 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 #endif
 
+/* We only set the VSX features if the kernel was compiled with VSX
+ * support
+ */
+#ifdef CONFIG_VSX
+#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
+#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
+#else
+#define CPU_FTR_VSX_COMP        0
+#define PPC_FEATURE_HAS_VSX_COMP    0
+#endif
+
 /* We only set the spe features if the kernel was compiled with spe
  * support
  */
@@ -245,8 +266,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 #define CPU_FTRS_604    (CPU_FTR_COMMON | \
-            CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
-            CPU_FTR_PPC_LE)
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
@@ -347,40 +367,50 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_UNIFIED_ID_CACHE)
-#define CPU_FTRS_E500   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
+#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
             CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
-            CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
+            CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
-#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
+#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
             CPU_FTR_MMCRA | CPU_FTR_CTRL)
-#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA)
-#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
-#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
             CPU_FTR_PURR)
-#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR)
-#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_MMCRA | CPU_FTR_SMT | \
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+            CPU_FTR_DSCR | CPU_FTR_SAO)
+#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
-#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
+#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
             CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
@@ -391,7 +421,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_POSSIBLE       \
             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
-            CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT)
+            CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
+            CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
 #else
 enum {
         CPU_FTRS_POSSIBLE =
@@ -421,7 +452,7 @@ enum {
             CPU_FTRS_E200 |
 #endif
 #ifdef CONFIG_E500
-            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
+            CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
 #endif
             0,
 };
@@ -431,7 +462,7 @@ enum {
 #define CPU_FTRS_ALWAYS         \
             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
-            CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
+            CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 #else
 enum {
         CPU_FTRS_ALWAYS =
@@ -461,7 +492,7 @@ enum {
             CPU_FTRS_E200 &
 #endif
 #ifdef CONFIG_E500
-            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
+            CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
 #endif
             CPU_FTRS_POSSIBLE,
 };
@@ -477,18 +508,5 @@ static inline int cpu_has_feature(unsigned long feature)
 
 #endif /* !__ASSEMBLY__ */
 
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION_NESTED(label) label:
-#define BEGIN_FTR_SECTION               BEGIN_FTR_SECTION_NESTED(97)
-#define END_FTR_SECTION_NESTED(msk, val, label) \
-        MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
-#define END_FTR_SECTION(msk, val)               \
-        END_FTR_SECTION_NESTED(msk, val, 97)
-
-#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
-#endif /* __ASSEMBLY__ */
-
 #endif /* __KERNEL__ */
 #endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/include/asm-powerpc/dcr-generic.h b/include/asm-powerpc/dcr-generic.h
new file mode 100644
index 000000000000..35b71599ec46
--- /dev/null
+++ b/include/asm-powerpc/dcr-generic.h
@@ -0,0 +1,49 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_DCR_GENERIC_H
+#define _ASM_POWERPC_DCR_GENERIC_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID};
+
+typedef struct {
+        enum host_type_t type;
+        union {
+                dcr_host_mmio_t mmio;
+                dcr_host_native_t native;
+        } host;
+} dcr_host_t;
+
+extern bool dcr_map_ok_generic(dcr_host_t host);
+
+extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
+                          unsigned int dcr_c);
+extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
+
+extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
+
+extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_GENERIC_H */
+
+
diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h
index 08532ff1899c..acd491dbd45a 100644
--- a/include/asm-powerpc/dcr-mmio.h
+++ b/include/asm-powerpc/dcr-mmio.h
@@ -27,20 +27,26 @@ typedef struct {
         void __iomem *token;
         unsigned int stride;
         unsigned int base;
-} dcr_host_t;
+} dcr_host_mmio_t;
 
-#define DCR_MAP_OK(host)        ((host).token != NULL)
+static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
+{
+        return host.token != NULL;
+}
 
-extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
-                          unsigned int dcr_c);
-extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c);
+extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
+                                    unsigned int dcr_n,
+                                    unsigned int dcr_c);
+extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
 
-static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
+static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
 {
         return in_be32(host.token + ((host.base + dcr_n) * host.stride));
 }
 
-static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value)
+static inline void dcr_write_mmio(dcr_host_mmio_t host,
+                                  unsigned int dcr_n,
+                                  u32 value)
 {
         out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
 }
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index f8398ce80372..72d2b72c7390 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -26,14 +26,18 @@
 
 typedef struct {
         unsigned int base;
-} dcr_host_t;
+} dcr_host_native_t;
 
-#define DCR_MAP_OK(host)        (1)
+static inline bool dcr_map_ok_native(dcr_host_native_t host)
+{
+        return 1;
+}
 
-#define dcr_map(dev, dcr_n, dcr_c)      ((dcr_host_t){ .base = (dcr_n) })
-#define dcr_unmap(host, dcr_c)          do {} while (0)
-#define dcr_read(host, dcr_n)           mfdcr(dcr_n + host.base)
-#define dcr_write(host, dcr_n, value)   mtdcr(dcr_n + host.base, value)
+#define dcr_map_native(dev, dcr_n, dcr_c) \
+        ((dcr_host_native_t){ .base = (dcr_n) })
+#define dcr_unmap_native(host, dcr_c)           do {} while (0)
+#define dcr_read_native(host, dcr_n)            mfdcr(dcr_n + host.base)
+#define dcr_write_native(host, dcr_n, value)    mtdcr(dcr_n + host.base, value)
 
 /* Device Control Registers */
 void __mtdcr(int reg, unsigned int val);
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
index 9338d50538f1..53b283050ab3 100644
--- a/include/asm-powerpc/dcr.h
+++ b/include/asm-powerpc/dcr.h
@@ -20,14 +20,50 @@
 #ifndef _ASM_POWERPC_DCR_H
 #define _ASM_POWERPC_DCR_H
 #ifdef __KERNEL__
+#ifndef __ASSEMBLY__
 #ifdef CONFIG_PPC_DCR
 
 #ifdef CONFIG_PPC_DCR_NATIVE
 #include <asm/dcr-native.h>
-#else
+#endif
+
+#ifdef CONFIG_PPC_DCR_MMIO
 #include <asm/dcr-mmio.h>
 #endif
 
+
+/* Indirection layer for providing both NATIVE and MMIO support. */
+
+#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
+
+#include <asm/dcr-generic.h>
+
+#define DCR_MAP_OK(host)        dcr_map_ok_generic(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
+
+#else
+
+#ifdef CONFIG_PPC_DCR_NATIVE
+typedef dcr_host_native_t dcr_host_t;
+#define DCR_MAP_OK(host)        dcr_map_ok_native(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
+#else
+typedef dcr_host_mmio_t dcr_host_t;
+#define DCR_MAP_OK(host)        dcr_map_ok_mmio(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
+#endif
+
+#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
+
 /*
  * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
  * base from the device-tree
@@ -41,5 +77,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
 #endif /* CONFIG_PPC_MERGE */
 
 #endif /* CONFIG_PPC_DCR */
+#endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DCR_H */
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index bbefb69bfb67..74c549780987 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -13,6 +13,7 @@
 /* need struct page definitions */
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
+#include <linux/dma-attrs.h>
 #include <asm/io.h>
 
 #define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
@@ -44,6 +45,15 @@ extern void __dma_sync_page(struct page *page, unsigned long offset,
 #endif /* ! CONFIG_NOT_COHERENT_CACHE */
 
 #ifdef CONFIG_PPC64
+
+static inline unsigned long device_to_mask(struct device *dev)
+{
+        if (dev->dma_mask && *dev->dma_mask)
+                return *dev->dma_mask;
+        /* Assume devices without mask can take 32 bit addresses */
+        return 0xfffffffful;
+}
+
 /*
  * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
  */
@@ -53,13 +63,17 @@ struct dma_mapping_ops {
         void            (*free_coherent)(struct device *dev, size_t size,
                                 void *vaddr, dma_addr_t dma_handle);
         dma_addr_t      (*map_single)(struct device *dev, void *ptr,
-                                size_t size, enum dma_data_direction direction);
+                                size_t size, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
         void            (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
-                                size_t size, enum dma_data_direction direction);
+                                size_t size, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
         int             (*map_sg)(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction);
+                                int nents, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
         void            (*unmap_sg)(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction);
+                                int nents, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
         int             (*dma_supported)(struct device *dev, u64 mask);
         int             (*set_dma_mask)(struct device *dev, u64 dma_mask);
 };
@@ -109,6 +123,77 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask)
         return 0;
 }
 
+static inline dma_addr_t dma_map_single_attrs(struct device *dev,
+                                              void *cpu_addr,
+                                              size_t size,
+                                              enum dma_data_direction direction,
+                                              struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->map_single(dev, cpu_addr, size, direction, attrs);
+}
+
+static inline void dma_unmap_single_attrs(struct device *dev,
+                                          dma_addr_t dma_addr,
+                                          size_t size,
+                                          enum dma_data_direction direction,
+                                          struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_single(dev, dma_addr, size, direction, attrs);
+}
+
+static inline dma_addr_t dma_map_page_attrs(struct device *dev,
+                                            struct page *page,
+                                            unsigned long offset, size_t size,
+                                            enum dma_data_direction direction,
+                                            struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->map_single(dev, page_address(page) + offset, size,
+                        direction, attrs);
+}
+
+static inline void dma_unmap_page_attrs(struct device *dev,
+                                        dma_addr_t dma_address,
+                                        size_t size,
+                                        enum dma_data_direction direction,
+                                        struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_single(dev, dma_address, size, direction, attrs);
+}
+
+static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
+                                   int nents, enum dma_data_direction direction,
+                                   struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->map_sg(dev, sg, nents, direction, attrs);
+}
+
+static inline void dma_unmap_sg_attrs(struct device *dev,
+                                      struct scatterlist *sg,
+                                      int nhwentries,
+                                      enum dma_data_direction direction,
+                                      struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs);
+}
+
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
                                        dma_addr_t *dma_handle, gfp_t flag)
 {
@@ -131,63 +216,43 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
                                         size_t size,
                                         enum dma_data_direction direction)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        return dma_ops->map_single(dev, cpu_addr, size, direction);
+        return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL);
 }
 
 static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
                                     size_t size,
                                     enum dma_data_direction direction)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        dma_ops->unmap_single(dev, dma_addr, size, direction);
+        dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL);
 }
 
 static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
                                       unsigned long offset, size_t size,
                                       enum dma_data_direction direction)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        return dma_ops->map_single(dev, page_address(page) + offset, size,
-                        direction);
+        return dma_map_page_attrs(dev, page, offset, size, direction, NULL);
 }
 
 static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
                                   size_t size,
                                   enum dma_data_direction direction)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        dma_ops->unmap_single(dev, dma_address, size, direction);
+        dma_unmap_page_attrs(dev, dma_address, size, direction, NULL);
 }
 
 static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
                              int nents, enum dma_data_direction direction)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        return dma_ops->map_sg(dev, sg, nents, direction);
+        return dma_map_sg_attrs(dev, sg, nents, direction, NULL);
 }
 
 static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
                                 int nhwentries,
                                 enum dma_data_direction direction)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        dma_ops->unmap_sg(dev, sg, nhwentries, direction);
+        dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL);
 }
 
-
 /*
  * Available generic sets of operations
  */
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
index 9080d85cb9d0..89664675b469 100644
--- a/include/asm-powerpc/elf.h
+++ b/include/asm-powerpc/elf.h
@@ -109,6 +109,7 @@ typedef elf_gregset_t32 compat_elf_gregset_t;
 #ifdef __powerpc64__
 # define ELF_NVRREG32   33      /* includes vscr & vrsave stuffed together */
 # define ELF_NVRREG     34      /* includes vscr & vrsave in split vectors */
+# define ELF_NVSRHALFREG 32     /* Half the vsx registers */
 # define ELF_GREG_TYPE  elf_greg_t64
 #else
 # define ELF_NEVRREG    34      /* includes acc (as 2) */
@@ -158,6 +159,7 @@ typedef __vector128 elf_vrreg_t;
 typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
 #ifdef __powerpc64__
 typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
+typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
 #endif
 
 #ifdef __KERNEL__
@@ -202,30 +204,8 @@ static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
 }
 #define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
 
-static inline int dump_task_regs(struct task_struct *tsk,
-                                 elf_gregset_t *elf_regs)
-{
-        struct pt_regs *regs = tsk->thread.regs;
-        if (regs)
-                ppc_elf_core_copy_regs(*elf_regs, regs);
-
-        return 1;
-}
-#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
-
-extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 
-#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
-
 typedef elf_vrregset_t elf_fpxregset_t;
 
-#ifdef CONFIG_ALTIVEC
-extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs);
-#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_altivec(tsk, regs)
-#define ELF_CORE_XFPREG_TYPE NT_PPC_VMX
-#endif
-
-#endif /* __KERNEL__ */
-
 /* ELF_HWCAP yields a mask that user programs can use to figure out what
    instruction set this cpu supports.  This could be done in userspace,
    but it's not easy, and we've already done it here.  */
@@ -243,8 +223,6 @@ extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs);
 } while (0)
 #endif /* __powerpc64__ */
 
-#ifdef __KERNEL__
-
 #ifdef __powerpc64__
 # define SET_PERSONALITY(ex, ibcs2)                             \
 do {                                                            \
@@ -257,7 +235,8 @@ do {								\
         else                                                    \
                 clear_thread_flag(TIF_ABI_PENDING);             \
         if (personality(current->personality) != PER_LINUX32)   \
-                set_personality(PER_LINUX);                     \
+                set_personality(PER_LINUX |                     \
+                        (current->personality & (~PER_MASK)));  \
 } while (0)
 /*
  * An executable for which elf_read_implies_exec() returns TRUE will
@@ -272,8 +251,6 @@ do {								\
 # define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
 #endif /* __powerpc64__ */
 
-#endif /* __KERNEL__ */
-
 extern int dcache_bsize;
 extern int icache_bsize;
 extern int ucache_bsize;
@@ -285,6 +262,8 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                        int executable_stack);
 #define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
 
+#endif /* __KERNEL__ */
+
 /*
  * The requirements here are:
  * - keep the final alignment of sp (sp & 0xf)
@@ -422,6 +401,8 @@ do {									\
 /* Keep this the last entry.  */
 #define R_PPC64_NUM             107
 
+#ifdef  __KERNEL__
+
 #ifdef CONFIG_SPU_BASE
 /* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
 #define NT_SPU          1
@@ -430,4 +411,6 @@ do {									\
 
 #endif /* CONFIG_SPU_BASE */
 
+#endif /* __KERNEL */
+
 #endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-powerpc/feature-fixups.h b/include/asm-powerpc/feature-fixups.h
new file mode 100644
index 000000000000..a1029967620b
--- /dev/null
+++ b/include/asm-powerpc/feature-fixups.h
@@ -0,0 +1,126 @@
+#ifndef __ASM_POWERPC_FEATURE_FIXUPS_H
+#define __ASM_POWERPC_FEATURE_FIXUPS_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Feature section common macros
+ *
+ * Note that the entries now contain offsets between the table entry
+ * and the code rather than absolute code pointers in order to be
+ * useable with the vdso shared library. There is also an assumption
+ * that values will be negative, that is, the fixup table has to be
+ * located after the code it fixes up.
+ */
+#if defined(CONFIG_PPC64) && !defined(__powerpc64__)
+/* 64 bits kernel, 32 bits code (ie. vdso32) */
+#define FTR_ENTRY_LONG          .llong
+#define FTR_ENTRY_OFFSET        .long 0xffffffff; .long
+#else
+/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */
+#define FTR_ENTRY_LONG          PPC_LONG
+#define FTR_ENTRY_OFFSET        PPC_LONG
+#endif
+
+#define START_FTR_SECTION(label)        label##1:
+
+#define FTR_SECTION_ELSE_NESTED(label)                  \
+label##2:                                               \
+        .pushsection __ftr_alt_##label,"a";             \
+        .align 2;                                       \
+label##3:
+
+#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)   \
+label##4:                                               \
+        .popsection;                                    \
+        .pushsection sect,"a";                          \
+        .align 3;                                       \
+label##5:                                               \
+        FTR_ENTRY_LONG msk;                             \
+        FTR_ENTRY_LONG val;                             \
+        FTR_ENTRY_OFFSET label##1b-label##5b;           \
+        FTR_ENTRY_OFFSET label##2b-label##5b;           \
+        FTR_ENTRY_OFFSET label##3b-label##5b;           \
+        FTR_ENTRY_OFFSET label##4b-label##5b;           \
+        .popsection;
+
+
+/* CPU feature dependent sections */
+#define BEGIN_FTR_SECTION_NESTED(label) START_FTR_SECTION(label)
+#define BEGIN_FTR_SECTION               START_FTR_SECTION(97)
+
+#define END_FTR_SECTION_NESTED(msk, val, label)                 \
+        FTR_SECTION_ELSE_NESTED(label)                          \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
+
+#define END_FTR_SECTION(msk, val)               \
+        END_FTR_SECTION_NESTED(msk, val, 97)
+
+#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
+
+/* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
+#define FTR_SECTION_ELSE        FTR_SECTION_ELSE_NESTED(97)
+#define ALT_FTR_SECTION_END_NESTED(msk, val, label)     \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
+#define ALT_FTR_SECTION_END_NESTED_IFSET(msk, label)    \
+        ALT_FTR_SECTION_END_NESTED(msk, msk, label)
+#define ALT_FTR_SECTION_END_NESTED_IFCLR(msk, label)    \
+        ALT_FTR_SECTION_END_NESTED(msk, 0, label)
+#define ALT_FTR_SECTION_END(msk, val)   \
+        ALT_FTR_SECTION_END_NESTED(msk, val, 97)
+#define ALT_FTR_SECTION_END_IFSET(msk)  \
+        ALT_FTR_SECTION_END_NESTED_IFSET(msk, 97)
+#define ALT_FTR_SECTION_END_IFCLR(msk)  \
+        ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
+
+/* Firmware feature dependent sections */
+#define BEGIN_FW_FTR_SECTION_NESTED(label)      START_FTR_SECTION(label)
+#define BEGIN_FW_FTR_SECTION                    START_FTR_SECTION(97)
+
+#define END_FW_FTR_SECTION_NESTED(msk, val, label)              \
+        FTR_SECTION_ELSE_NESTED(label)                          \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
+
+#define END_FW_FTR_SECTION(msk, val)            \
+        END_FW_FTR_SECTION_NESTED(msk, val, 97)
+
+#define END_FW_FTR_SECTION_IFSET(msk)   END_FW_FTR_SECTION((msk), (msk))
+#define END_FW_FTR_SECTION_IFCLR(msk)   END_FW_FTR_SECTION((msk), 0)
+
+/* Firmware feature sections with alternatives */
+#define FW_FTR_SECTION_ELSE_NESTED(label)       FTR_SECTION_ELSE_NESTED(label)
+#define FW_FTR_SECTION_ELSE     FTR_SECTION_ELSE_NESTED(97)
+#define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label)  \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
+#define ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, label) \
+        ALT_FW_FTR_SECTION_END_NESTED(msk, msk, label)
+#define ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, label) \
+        ALT_FW_FTR_SECTION_END_NESTED(msk, 0, label)
+#define ALT_FW_FTR_SECTION_END(msk, val)        \
+        ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97)
+#define ALT_FW_FTR_SECTION_END_IFSET(msk)       \
+        ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, 97)
+#define ALT_FW_FTR_SECTION_END_IFCLR(msk)       \
+        ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
+
+#endif /* __ASSEMBLY__ */
+
+/* LWSYNC feature sections */
+#define START_LWSYNC_SECTION(label)     label##1:
+#define MAKE_LWSYNC_SECTION_ENTRY(label, sect)          \
+label##2:                                               \
+        .pushsection sect,"a";                          \
+        .align 2;                                       \
+label##3:                                               \
+        .long label##1b-label##3b;                      \
+        .popsection;
+
+#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index 1e41bd1c8502..ef328995ba9d 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -15,6 +15,7 @@
 #ifdef __KERNEL__
 
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 /* firmware feature bitmask values */
 #define FIRMWARE_MAX_FEATURES 63
@@ -125,18 +126,6 @@ extern int fwnmi_active;
 
 extern unsigned int __start___fw_ftr_fixup, __stop___fw_ftr_fixup;
 
-#else /* __ASSEMBLY__ */
-
-#define BEGIN_FW_FTR_SECTION_NESTED(label)      label:
-#define BEGIN_FW_FTR_SECTION                    BEGIN_FW_FTR_SECTION_NESTED(97)
-#define END_FW_FTR_SECTION_NESTED(msk, val, label) \
-        MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
-#define END_FW_FTR_SECTION(msk, val)            \
-        END_FW_FTR_SECTION_NESTED(msk, val, 97)
-
-#define END_FW_FTR_SECTION_IFSET(msk)   END_FW_FTR_SECTION((msk), (msk))
-#define END_FW_FTR_SECTION_IFCLR(msk)   END_FW_FTR_SECTION((msk), 0)
-
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/include/asm-powerpc/fsl_gtm.h b/include/asm-powerpc/fsl_gtm.h
new file mode 100644
index 000000000000..8e8c9b5032d3
--- /dev/null
+++ b/include/asm-powerpc/fsl_gtm.h
@@ -0,0 +1,47 @@
+/*
+ * Freescale General-purpose Timers Module
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ *               Shlomi Gridish <gridish@freescale.com>
+ *               Jerry Huang <Chang-Ming.Huang@freescale.com>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *               Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_FSL_GTM_H
+#define __ASM_FSL_GTM_H
+
+#include <linux/types.h>
+
+struct gtm;
+
+struct gtm_timer {
+        unsigned int irq;
+
+        struct gtm *gtm;
+        bool requested;
+        u8 __iomem *gtcfr;
+        __be16 __iomem *gtmdr;
+        __be16 __iomem *gtpsr;
+        __be16 __iomem *gtcnr;
+        __be16 __iomem *gtrfr;
+        __be16 __iomem *gtevr;
+};
+
+extern struct gtm_timer *gtm_get_timer16(void);
+extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm,
+                                                  unsigned int timer);
+extern void gtm_put_timer16(struct gtm_timer *tmr);
+extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec,
+                             bool reload);
+extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec,
+                                 bool reload);
+extern void gtm_stop_timer16(struct gtm_timer *tmr);
+extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events);
+
+#endif /* __ASM_FSL_GTM_H */
diff --git a/include/asm-powerpc/ftrace.h b/include/asm-powerpc/ftrace.h
new file mode 100644
index 000000000000..de921326cca8
--- /dev/null
+++ b/include/asm-powerpc/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_POWERPC_FTRACE
+#define _ASM_POWERPC_FTRACE
+
+#ifdef CONFIG_FTRACE
+#define MCOUNT_ADDR             ((long)(_mcount))
+#define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#endif
+
+#endif
+
+#endif /* _ASM_POWERPC_FTRACE */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index ad8c9f7fd0e3..f75a5fc64d2e 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -59,6 +59,11 @@ extern void iseries_handle_interrupts(void);
                 get_paca()->hard_enabled = 0;   \
         } while(0)
 
+static inline int irqs_disabled_flags(unsigned long flags)
+{
+        return flags == 0;
+}
+
 #else
 
 #if defined(CONFIG_BOOKE)
@@ -113,6 +118,11 @@ static inline void local_irq_save_ptr(unsigned long *flags)
 #define hard_irq_enable()       local_irq_enable()
 #define hard_irq_disable()      local_irq_disable()
 
+static inline int irqs_disabled_flags(unsigned long flags)
+{
+        return (flags & MSR_EE) == 0;
+}
+
 #endif /* CONFIG_PPC64 */
 
 /*
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index 89189488e286..8b627823f5f9 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -95,33 +95,60 @@ extern resource_size_t isa_mem_base;
 #define IO_SET_SYNC_FLAG()
 #endif
 
-#define DEF_MMIO_IN(name, type, insn)                                   \
-static inline type name(const volatile type __iomem *addr)              \
+/* gcc 4.0 and older doesn't have 'Z' constraint */
+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
+#define DEF_MMIO_IN_LE(name, size, insn)                                \
+static inline u##size name(const volatile u##size __iomem *addr)        \
 {                                                                       \
-        type ret;                                                       \
-        __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync"           \
+        u##size ret;                                                    \
+        __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"    \
                 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
         return ret;                                                     \
 }
 
-#define DEF_MMIO_OUT(name, type, insn)                                  \
-static inline void name(volatile type __iomem *addr, type val)          \
+#define DEF_MMIO_OUT_LE(name, size, insn)                               \
+static inline void name(volatile u##size __iomem *addr, u##size val)    \
 {                                                                       \
-        __asm__ __volatile__("sync;" insn                               \
+        __asm__ __volatile__("sync;"#insn" %1,0,%2"                     \
                 : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
         IO_SET_SYNC_FLAG();                                             \
 }
+#else /* newer gcc */
+#define DEF_MMIO_IN_LE(name, size, insn)                                \
+static inline u##size name(const volatile u##size __iomem *addr)        \
+{                                                                       \
+        u##size ret;                                                    \
+        __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
+                : "=r" (ret) : "Z" (*addr) : "memory");                 \
+        return ret;                                                     \
+}
+
+#define DEF_MMIO_OUT_LE(name, size, insn)                               \
+static inline void name(volatile u##size __iomem *addr, u##size val)    \
+{                                                                       \
+        __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
+                : "=Z" (*addr) : "r" (val) : "memory");                 \
+        IO_SET_SYNC_FLAG();                                             \
+}
+#endif
 
+#define DEF_MMIO_IN_BE(name, size, insn)                                \
+static inline u##size name(const volatile u##size __iomem *addr)        \
+{                                                                       \
+        u##size ret;                                                    \
+        __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
+                : "=r" (ret) : "m" (*addr) : "memory");                 \
+        return ret;                                                     \
+}
 
-#define DEF_MMIO_IN_BE(name, size, insn) \
-        DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2")
-#define DEF_MMIO_IN_LE(name, size, insn) \
-        DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1")
+#define DEF_MMIO_OUT_BE(name, size, insn)                               \
+static inline void name(volatile u##size __iomem *addr, u##size val)    \
+{                                                                       \
+        __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
+                : "=m" (*addr) : "r" (val) : "memory");                 \
+        IO_SET_SYNC_FLAG();                                             \
+}
 
-#define DEF_MMIO_OUT_BE(name, size, insn) \
-        DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0")
-#define DEF_MMIO_OUT_LE(name, size, insn) \
-        DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2")
 
 DEF_MMIO_IN_BE(in_8,     8, lbz);
 DEF_MMIO_IN_BE(in_be16, 16, lhz);
@@ -745,7 +772,7 @@ static inline void * bus_to_virt(unsigned long address)
 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 
 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
-#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 
 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 
diff --git a/include/asm-powerpc/ioctl.h b/include/asm-powerpc/ioctl.h
index 8eb99848c402..57d68304218b 100644
--- a/include/asm-powerpc/ioctl.h
+++ b/include/asm-powerpc/ioctl.h
@@ -1,69 +1,13 @@
 #ifndef _ASM_POWERPC_IOCTL_H
 #define _ASM_POWERPC_IOCTL_H
 
-
-/*
- * this was copied from the alpha as it's a bit cleaner there.
- *                         -- Cort
- */
-
-#define _IOC_NRBITS     8
-#define _IOC_TYPEBITS   8
 #define _IOC_SIZEBITS   13
 #define _IOC_DIRBITS    3
 
-#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
-
-#define _IOC_NRSHIFT    0
-#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
-#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
-#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
-
-/*
- * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
- * And this turns out useful to catch old ioctl numbers in header
- * files for us.
- */
 #define _IOC_NONE       1U
 #define _IOC_READ       2U
 #define _IOC_WRITE      4U
 
-#define _IOC(dir,type,nr,size) \
-        (((dir)  << _IOC_DIRSHIFT) | \
-         ((type) << _IOC_TYPESHIFT) | \
-         ((nr)   << _IOC_NRSHIFT) | \
-         ((size) << _IOC_SIZESHIFT))
-
-/* provoke compile error for invalid uses of size argument */
-extern unsigned int __invalid_size_argument_for_IOC;
-#define _IOC_TYPECHECK(t) \
-        ((sizeof(t) == sizeof(t[1]) && \
-          sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
-          sizeof(t) : __invalid_size_argument_for_IOC)
-
-/* used to create numbers */
-#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
-#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
-#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
-#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
-#define _IOR_BAD(type,nr,size)  _IOC(_IOC_READ,(type),(nr),sizeof(size))
-#define _IOW_BAD(type,nr,size)  _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
-#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
-
-/* used to decode them.. */
-#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
-#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
-
-/* various drivers, such as the pcmcia stuff, need these... */
-#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+#include <asm-generic/ioctl.h>
 
 #endif  /* _ASM_POWERPC_IOCTL_H */
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 852e15f51a1e..51ecfef8d843 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -79,11 +79,13 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
 extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
                                             int nid);
 
-extern int iommu_map_sg(struct device *dev, struct scatterlist *sglist,
-                        int nelems, unsigned long mask,
-                        enum dma_data_direction direction);
+extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
+                        struct scatterlist *sglist, int nelems,
+                        unsigned long mask, enum dma_data_direction direction,
+                        struct dma_attrs *attrs);
 extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
-                           int nelems, enum dma_data_direction direction);
+                           int nelems, enum dma_data_direction direction,
+                           struct dma_attrs *attrs);
 
 extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
                                   size_t size, dma_addr_t *dma_handle,
@@ -92,9 +94,11 @@ extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
                                 void *vaddr, dma_addr_t dma_handle);
 extern dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl,
                                    void *vaddr, size_t size, unsigned long mask,
-                                   enum dma_data_direction direction);
+                                   enum dma_data_direction direction,
+                                   struct dma_attrs *attrs);
 extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
-                               size_t size, enum dma_data_direction direction);
+                               size_t size, enum dma_data_direction direction,
+                               struct dma_attrs *attrs);
 
 extern void iommu_init_early_pSeries(void);
 extern void iommu_init_early_iSeries(void);
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 5089deb8fec3..1ef8e304e0ea 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -619,6 +619,19 @@ struct pt_regs;
 
 #define __ARCH_HAS_DO_SOFTIRQ
 
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+/*
+ * Per-cpu stacks for handling critical, debug and machine check
+ * level interrupts.
+ */
+extern struct thread_info *critirq_ctx[NR_CPUS];
+extern struct thread_info *dbgirq_ctx[NR_CPUS];
+extern struct thread_info *mcheckirq_ctx[NR_CPUS];
+extern void exc_lvl_ctx_init(void);
+#else
+#define exc_lvl_ctx_init()
+#endif
+
 #ifdef CONFIG_IRQSTACKS
 /*
  * Per-cpu stacks for handling hard and soft interrupts.
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
index 701857bc8e24..acdcdc66f1b6 100644
--- a/include/asm-powerpc/kexec.h
+++ b/include/asm-powerpc/kexec.h
@@ -34,6 +34,8 @@
 #ifndef __ASSEMBLY__
 #include <linux/cpumask.h>
 
+typedef void (*crash_shutdown_t)(void);
+
 #ifdef CONFIG_KEXEC
 
 #ifdef __powerpc64__
@@ -123,7 +125,6 @@ struct pt_regs;
 extern void default_machine_kexec(struct kimage *image);
 extern int default_machine_kexec_prepare(struct kimage *image);
 extern void default_machine_crash_shutdown(struct pt_regs *regs);
-typedef void (*crash_shutdown_t)(void);
 extern int crash_shutdown_register(crash_shutdown_t handler);
 extern int crash_shutdown_unregister(crash_shutdown_t handler);
 
@@ -143,6 +144,16 @@ static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
 
 static inline void reserve_crashkernel(void) { ; }
 
+static inline int crash_shutdown_register(crash_shutdown_t handler)
+{
+        return 0;
+}
+
+static inline int crash_shutdown_unregister(crash_shutdown_t handler)
+{
+        return 0;
+}
+
 #endif /* CONFIG_KEXEC */
 #endif /* ! __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 54ed64df95b8..989922621e35 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -262,6 +262,7 @@ struct machdep_calls {
 #endif
 };
 
+extern void e500_idle(void);
 extern void power4_idle(void);
 extern void power4_cpu_offline_powersave(void);
 extern void ppc6xx_idle(void);
diff --git a/include/asm-powerpc/mman.h b/include/asm-powerpc/mman.h
index 24cf664a8295..9209f755763e 100644
--- a/include/asm-powerpc/mman.h
+++ b/include/asm-powerpc/mman.h
@@ -10,6 +10,8 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#define PROT_SAO        0x10            /* Strong Access Ordering */
+
 #define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */
 #define MAP_NORESERVE   0x40            /* don't reserve swap pages */
 #define MAP_LOCKED      0x80
@@ -24,4 +26,38 @@
 #define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
 #define MAP_NONBLOCK    0x10000         /* do not block on IO */
 
+#ifdef __KERNEL__
+#ifdef CONFIG_PPC64
+
+#include <asm/cputable.h>
+#include <linux/mm.h>
+
+/*
+ * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits()
+ * here.  How important is the optimization?
+ */
+static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot)
+{
+        return (prot & PROT_SAO) ? VM_SAO : 0;
+}
+#define arch_calc_vm_prot_bits(prot) arch_calc_vm_prot_bits(prot)
+
+static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)
+{
+        return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : 0;
+}
+#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)
+
+static inline int arch_validate_prot(unsigned long prot)
+{
+        if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))
+                return 0;
+        if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO))
+                return 0;
+        return 1;
+}
+#define arch_validate_prot(prot) arch_validate_prot(prot)
+
+#endif /* CONFIG_PPC64 */
+#endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_MMAN_H */
diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h
index 6e21ca618ec3..16b1a1e77e64 100644
--- a/include/asm-powerpc/mmu-hash32.h
+++ b/include/asm-powerpc/mmu-hash32.h
@@ -28,24 +28,18 @@
 #define BPP_RW  0x02            /* Read/write */
 
 #ifndef __ASSEMBLY__
+/* Contort a phys_addr_t into the right format/bits for a BAT */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
+                                ((x & 0x0000000e00000000ULL) >> 24) | \
+                                ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x) (x)
+#endif
+
 struct ppc_bat {
-        struct {
-                unsigned long bepi:15;  /* Effective page index (virtual address) */
-                unsigned long :4;       /* Unused */
-                unsigned long bl:11;    /* Block size mask */
-                unsigned long vs:1;     /* Supervisor valid */
-                unsigned long vp:1;     /* User valid */
-        } batu;                 /* Upper register */
-        struct {
-                unsigned long brpn:15;  /* Real page index (physical address) */
-                unsigned long :10;      /* Unused */
-                unsigned long w:1;      /* Write-thru cache */
-                unsigned long i:1;      /* Cache inhibit */
-                unsigned long m:1;      /* Memory coherence */
-                unsigned long g:1;      /* Guarded (MBZ in IBAT) */
-                unsigned long :1;       /* Unused */
-                unsigned long pp:2;     /* Page access protections */
-        } batl;                 /* Lower register */
+        u32 batu;
+        u32 batl;
 };
 #endif /* !__ASSEMBLY__ */
 
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 39c5c5f62bf5..d1dc16afb118 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -182,6 +182,7 @@ extern int mmu_io_psize;
 extern int mmu_kernel_ssize;
 extern int mmu_highuser_ssize;
 extern u16 mmu_slb_size;
+extern unsigned long tce_alloc_start, tce_alloc_end;
 
 /*
  * If the processor supports 64k normal pages but not 64k cache
diff --git a/include/asm-powerpc/mpc6xx.h b/include/asm-powerpc/mpc6xx.h
new file mode 100644
index 000000000000..effc2291beb2
--- /dev/null
+++ b/include/asm-powerpc/mpc6xx.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_POWERPC_MPC6xx_H
+#define __ASM_POWERPC_MPC6xx_H
+
+void mpc6xx_enter_standby(void);
+
+#endif
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index a4d0f876b427..fe566a348a86 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -353,6 +353,8 @@ struct mpic
 #define MPIC_ENABLE_MCK                 0x00000200
 /* Disable bias among target selection, spread interrupts evenly */
 #define MPIC_NO_BIAS                    0x00000400
+/* Ignore NIRQS as reported by FRR */
+#define MPIC_BROKEN_FRR_NIRQS           0x00000800
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK                0xf0000000
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
index 6526e139a463..3c123990ca2e 100644
--- a/include/asm-powerpc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -21,8 +21,6 @@ extern struct of_device *of_device_alloc(struct device_node *np,
                                          const char *bus_id,
                                          struct device *parent);
 
-extern ssize_t of_device_get_modalias(struct of_device *ofdev,
-                                        char *str, ssize_t len);
 extern int of_device_uevent(struct device *dev,
                             struct kobj_uevent_env *env);
 
diff --git a/include/asm-powerpc/pSeries_reconfig.h b/include/asm-powerpc/pSeries_reconfig.h
index ea6cfb8efb84..e482e5352e69 100644
--- a/include/asm-powerpc/pSeries_reconfig.h
+++ b/include/asm-powerpc/pSeries_reconfig.h
@@ -9,8 +9,10 @@
  * added or removed on pSeries systems.
  */
 
-#define PSERIES_RECONFIG_ADD    0x0001
-#define PSERIES_RECONFIG_REMOVE 0x0002
+#define PSERIES_RECONFIG_ADD            0x0001
+#define PSERIES_RECONFIG_REMOVE         0x0002
+#define PSERIES_DRCONF_MEM_ADD          0x0003
+#define PSERIES_DRCONF_MEM_REMOVE       0x0004
 
 #ifdef CONFIG_PPC_PSERIES
 extern int pSeries_reconfig_notifier_register(struct notifier_block *);
diff --git a/include/asm-powerpc/page_64.h b/include/asm-powerpc/page_64.h
index 25af4fc8daf4..02fd80710e9d 100644
--- a/include/asm-powerpc/page_64.h
+++ b/include/asm-powerpc/page_64.h
@@ -126,16 +126,22 @@ extern unsigned int get_slice_psize(struct mm_struct *mm,
 
 extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
 extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
+extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
+                                  unsigned long len, unsigned int psize);
+
 #define slice_mm_new_context(mm)        ((mm)->context.id == 0)
 
 #endif /* __ASSEMBLY__ */
 #else
 #define slice_init()
+#define get_slice_psize(mm, addr)       ((mm)->context.user_psize)
 #define slice_set_user_psize(mm, psize)         \
 do {                                            \
         (mm)->context.user_psize = (psize);     \
         (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
 } while (0)
+#define slice_set_range_psize(mm, start, len, psize)    \
+        slice_set_user_psize((mm), (psize))
 #define slice_mm_new_context(mm)        1
 #endif /* CONFIG_PPC_MM_SLICES */
 
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index b95d033ae6e6..ae2ea803a0f2 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -92,12 +92,15 @@ struct pci_controller {
          *   anything but the PHB.  Only allow talking to the PHB if this is
          *   set.
          *  BIG_ENDIAN - cfg_addr is a big endian register
+         *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
+         *   the PLB4.  Effectively disable MRM commands by setting this.
          */
 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
+#define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
         u32 indirect_type;
 #endif  /* !CONFIG_PPC64 */
         /* Currently, we limit ourselves to 1 IO range and 3 mem
diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h
index 818e2abc81e2..fd2090dc1dce 100644
--- a/include/asm-powerpc/pgtable-4k.h
+++ b/include/asm-powerpc/pgtable-4k.h
@@ -41,6 +41,7 @@
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
 /* PTE bits */
+#define _PAGE_HASHPTE   0x0400 /* software: pte has an associated HPTE */
 #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
 #define _PAGE_GROUP_IX  0x7000 /* software: HPTE index within group */
 #define _PAGE_F_SECOND  _PAGE_SECONDARY
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index 1cbd6b377eea..c5007712473f 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -75,6 +75,20 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
 #define _PAGE_COMBO     0x10000000 /* this is a combo 4k page */
 #define _PAGE_4K_PFN    0x20000000 /* PFN is for a single 4k page */
 
+/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
+ * we set that to be the whole sub-bits mask. The C code will only
+ * test this, so a multi-bit mask will work. For combo pages, this
+ * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
+ * all the sub bits. For real 64k pages, we now have the assembly set
+ * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
+ * that mask. This is fine as long as the HIDX bits are never set on
+ * a PTE that isn't hashed, which is the case today.
+ *
+ * A little nit is for the huge page C code, which does the hashing
+ * in C, we need to provide which bit to use.
+ */
+#define _PAGE_HASHPTE   _PAGE_HPTE_SUB
+
 /* Note the full page bits must be in the same location as for normal
  * 4k pages as the same asssembly will be used to insert 64K pages
  * wether the kernel has CONFIG_PPC_64K_PAGES or not
@@ -83,8 +97,7 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
 #define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */
 
 /* PTE flags to conserve for HPTE identification */
-#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
-                         _PAGE_COMBO)
+#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
 
 /* Shift to put page number into pte.
  *
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index c08e714d0c42..73015f0139de 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -182,6 +182,9 @@ extern int icache_44x_need_flush;
 #define _PMD_SIZE_16M   0x0e0
 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 
+/* Until my rework is finished, 40x still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES      1
+
 #elif defined(CONFIG_44x)
 /*
  * Definitions for PPC440
@@ -253,17 +256,17 @@ extern int icache_44x_need_flush;
  */
 
 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
-#define _PAGE_RW        0x00000002              /* S: Write permission */
+#define _PAGE_RW        0x00000002              /* S: Write permission */
 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
+#define _PAGE_HWEXEC    0x00000004              /* H: Execute permission */
 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
-#define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
-#define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
-#define _PAGE_USER      0x00000040              /* S: User page */
-#define _PAGE_ENDIAN    0x00000080              /* H: E bit */
-#define _PAGE_GUARDED   0x00000100              /* H: G bit */
-#define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
-#define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
-#define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
+#define _PAGE_DIRTY     0x00000010              /* S: Page dirty */
+#define _PAGE_USER      0x00000040              /* S: User page */
+#define _PAGE_ENDIAN    0x00000080              /* H: E bit */
+#define _PAGE_GUARDED   0x00000100              /* H: G bit */
+#define _PAGE_COHERENT  0x00000200              /* H: M bit */
+#define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 
 /* TODO: Add large page lowmem mapping support */
 #define _PMD_PRESENT    0
@@ -273,6 +276,7 @@ extern int icache_44x_need_flush;
 /* ERPN in a PTE never gets cleared, ignore it */
 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 
+
 #elif defined(CONFIG_FSL_BOOKE)
 /*
    MMU Assist Register 3:
@@ -315,6 +319,9 @@ extern int icache_44x_need_flush;
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD        (~PAGE_MASK)
 
+/* Until my rework is finished, FSL BookE still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES      1
+
 #elif defined(CONFIG_8xx)
 /* Definitions for 8xx embedded chips. */
 #define _PAGE_PRESENT   0x0001  /* Page is valid */
@@ -345,6 +352,9 @@ extern int icache_44x_need_flush;
 
 #define _PTE_NONE_MASK _PAGE_ACCESSED
 
+/* Until my rework is finished, 8xx still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES      1
+
 #else /* CONFIG_6xx */
 /* Definitions for 60x, 740/750, etc. */
 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
@@ -365,6 +375,10 @@ extern int icache_44x_need_flush;
 #define _PMD_PRESENT    0
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD        (~PAGE_MASK)
+
+/* Hash table based platforms need atomic updates of the linux PTE */
+#define PTE_ATOMIC_UPDATES      1
+
 #endif
 
 /*
@@ -557,9 +571,11 @@ extern void add_hash_page(unsigned context, unsigned long va,
  * low PTE word since we expect ALL flag bits to be there
  */
 #ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p, unsigned long clr,
+static inline unsigned long pte_update(pte_t *p,
+                                       unsigned long clr,
                                        unsigned long set)
 {
+#ifdef PTE_ATOMIC_UPDATES
         unsigned long old, tmp;
 
         __asm__ __volatile__("\
@@ -572,16 +588,26 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr,
         : "=&r" (old), "=&r" (tmp), "=m" (*p)
         : "r" (p), "r" (clr), "r" (set), "m" (*p)
         : "cc" );
+#else /* PTE_ATOMIC_UPDATES */
+        unsigned long old = pte_val(*p);
+        *p = __pte((old & ~clr) | set);
+#endif /* !PTE_ATOMIC_UPDATES */
+
 #ifdef CONFIG_44x
         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
                 icache_44x_need_flush = 1;
 #endif
         return old;
 }
-#else
-static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
-                                       unsigned long set)
+#else /* CONFIG_PTE_64BIT */
+/* TODO: Change that to only modify the low word and move set_pte_at()
+ * out of line
+ */
+static inline unsigned long long pte_update(pte_t *p,
+                                            unsigned long clr,
+                                            unsigned long set)
 {
+#ifdef PTE_ATOMIC_UPDATES
         unsigned long long old;
         unsigned long tmp;
 
@@ -596,13 +622,18 @@ static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
         : "=&r" (old), "=&r" (tmp), "=m" (*p)
         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
         : "cc" );
+#else /* PTE_ATOMIC_UPDATES */
+        unsigned long long old = pte_val(*p);
+        *p = __pte((old & ~(unsigned long long)clr) | set);
+#endif /* !PTE_ATOMIC_UPDATES */
+
 #ifdef CONFIG_44x
         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
                 icache_44x_need_flush = 1;
 #endif
         return old;
 }
-#endif
+#endif /* CONFIG_PTE_64BIT */
 
 /*
  * set_pte stores a linux PTE into the linux page table.
@@ -620,8 +651,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 }
 
 /*
- * 2.6 calles this without flushing the TLB entry, this is wrong
- * for our hash-based implementation, we fix that up here
+ * 2.6 calls this without flushing the TLB entry; this is wrong
+ * for our hash-based implementation, we fix that up here.
  */
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
@@ -652,6 +683,12 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 {
         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 }
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
 
 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
@@ -665,7 +702,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 ({                                                                         \
         int __changed = !pte_same(*(__ptep), __entry);                     \
         if (__changed) {                                                   \
-                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
                 flush_tlb_page_nohash(__vma, __address);                   \
         }                                                                  \
         __changed;                                                         \
diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h
index 7686569a0bef..ab98a9c80b28 100644
--- a/include/asm-powerpc/pgtable-ppc64.h
+++ b/include/asm-powerpc/pgtable-ppc64.h
@@ -91,9 +91,11 @@
 #define _PAGE_DIRTY     0x0080 /* C: page changed */
 #define _PAGE_ACCESSED  0x0100 /* R: page referenced */
 #define _PAGE_RW        0x0200 /* software: user write access allowed */
-#define _PAGE_HASHPTE   0x0400 /* software: pte has an associated HPTE */
 #define _PAGE_BUSY      0x0800 /* software: PTE & hash are busy */
 
+/* Strong Access Ordering */
+#define _PAGE_SAO       (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
+
 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
 
 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY)
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index 2dbd4e7884fa..0966899d974b 100644
--- a/include/asm-powerpc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -6,6 +6,7 @@
 
 #include <linux/stringify.h>
 #include <asm/asm-compat.h>
+#include <asm/processor.h>
 
 #ifndef __ASSEMBLY__
 #error __FILE__ should only be used in assembler files
@@ -73,6 +74,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
                                 REST_10GPRS(22, base)
 #endif
 
+/*
+ * Define what the VSX XX1 form instructions will look like, then add
+ * the 128 bit load store instructions based on that.
+ */
+#define VSX_XX1(xs, ra, rb)     (((xs) & 0x1f) << 21 | ((ra) << 16) |  \
+                                 ((rb) << 11) | (((xs) >> 5)))
+
+#define STXVD2X(xs, ra, rb)     .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
+#define LXVD2X(xs, ra, rb)      .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
 
 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
@@ -83,13 +93,13 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
 
-#define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
+#define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
-#define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
+#define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
@@ -109,6 +119,33 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 
+/* Save the lower 32 VSRs in the thread VSR region */
+#define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,b,base)
+#define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
+#define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
+#define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
+#define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
+#define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
+#define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
+#define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
+#define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
+#define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
+#define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
+#define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
+/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
+#define SAVE_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,b,base)
+#define SAVE_2VSRSU(n,b,base)   SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
+#define SAVE_4VSRSU(n,b,base)   SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
+#define SAVE_8VSRSU(n,b,base)   SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
+#define SAVE_16VSRSU(n,b,base)  SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
+#define SAVE_32VSRSU(n,b,base)  SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
+#define REST_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
+#define REST_2VSRSU(n,b,base)   REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
+#define REST_4VSRSU(n,b,base)   REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
+#define REST_8VSRSU(n,b,base)   REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
+#define REST_16VSRSU(n,b,base)  REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
+#define REST_32VSRSU(n,b,base)  REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
+
 #define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
 #define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
 #define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
@@ -356,6 +393,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define toreal(rd)
 #define fromreal(rd)
 
+/*
+ * We use addis to ensure compatibility with the "classic" ppc versions of
+ * these macros, which use rs = 0 to get the tophys offset in rd, rather than
+ * converting the address in r0, and so this version has to do that too
+ * (i.e. set register rd to 0 when rs == 0).
+ */
 #define tophys(rd,rs)                           \
         addis   rd,rs,0
 
@@ -533,6 +576,73 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define vr30    30
 #define vr31    31
 
+/* VSX Registers (VSRs) */
+
+#define vsr0    0
+#define vsr1    1
+#define vsr2    2
+#define vsr3    3
+#define vsr4    4
+#define vsr5    5
+#define vsr6    6
+#define vsr7    7
+#define vsr8    8
+#define vsr9    9
+#define vsr10   10
+#define vsr11   11
+#define vsr12   12
+#define vsr13   13
+#define vsr14   14
+#define vsr15   15
+#define vsr16   16
+#define vsr17   17
+#define vsr18   18
+#define vsr19   19
+#define vsr20   20
+#define vsr21   21
+#define vsr22   22
+#define vsr23   23
+#define vsr24   24
+#define vsr25   25
+#define vsr26   26
+#define vsr27   27
+#define vsr28   28
+#define vsr29   29
+#define vsr30   30
+#define vsr31   31
+#define vsr32   32
+#define vsr33   33
+#define vsr34   34
+#define vsr35   35
+#define vsr36   36
+#define vsr37   37
+#define vsr38   38
+#define vsr39   39
+#define vsr40   40
+#define vsr41   41
+#define vsr42   42
+#define vsr43   43
+#define vsr44   44
+#define vsr45   45
+#define vsr46   46
+#define vsr47   47
+#define vsr48   48
+#define vsr49   49
+#define vsr50   50
+#define vsr51   51
+#define vsr52   52
+#define vsr53   53
+#define vsr54   54
+#define vsr55   55
+#define vsr56   56
+#define vsr57   57
+#define vsr58   58
+#define vsr59   59
+#define vsr60   60
+#define vsr61   61
+#define vsr62   62
+#define vsr63   63
+
 /* SPE Registers (EVPRs) */
 
 #define evr0    0
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index cf83f2d7e2a5..101ed87f7d84 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -12,6 +12,12 @@
 
 #include <asm/reg.h>
 
+#ifdef CONFIG_VSX
+#define TS_FPRWIDTH 2
+#else
+#define TS_FPRWIDTH 1
+#endif
+
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
 #include <asm/ptrace.h>
@@ -78,9 +84,14 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 /* Lazy FPU handling on uni-processor */
 extern struct task_struct *last_task_used_math;
 extern struct task_struct *last_task_used_altivec;
+extern struct task_struct *last_task_used_vsx;
 extern struct task_struct *last_task_used_spe;
 
 #ifdef CONFIG_PPC32
+
+#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
+#error User TASK_SIZE overlaps with KERNEL_START address
+#endif
 #define TASK_SIZE       (CONFIG_TASK_SIZE)
 
 /* This decides where the kernel will search for a free chunk of vm
@@ -136,6 +147,10 @@ typedef struct {
         unsigned long seg;
 } mm_segment_t;
 
+#define TS_FPROFFSET 0
+#define TS_VSRLOWOFFSET 1
+#define TS_FPR(i) fpr[i][TS_FPROFFSET]
+
 struct thread_struct {
         unsigned long   ksp;            /* Kernel stack pointer */
         unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
@@ -152,8 +167,9 @@ struct thread_struct {
         unsigned long   dbcr0;          /* debug control register values */
         unsigned long   dbcr1;
 #endif
-        double          fpr[32];        /* Complete floating point set */
-        struct {                        /* fpr ... fpscr must be contiguous */
+        /* FP and VSX 0-31 register set */
+        double          fpr[32][TS_FPRWIDTH];
+        struct {
 
                 unsigned int pad;
                 unsigned int val;       /* Floating point status */
@@ -173,6 +189,10 @@ struct thread_struct {
         unsigned long   vrsave;
         int             used_vr;        /* set if process has used altivec */
 #endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_VSX
+        /* VSR status */
+        int             used_vsr;       /* set if process has used altivec */
+#endif /* CONFIG_VSX */
 #ifdef CONFIG_SPE
         unsigned long   evr[32];        /* upper 32-bits of SPE regs */
         u64             acc;            /* Accumulator */
@@ -202,7 +222,7 @@ struct thread_struct {
         .ksp_limit = INIT_SP_LIMIT, \
         .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
         .fs = KERNEL_DS, \
-        .fpr = {0}, \
+        .fpr = {{0}}, \
         .fpscr = { .val = 0, }, \
         .fpexc_mode = 0, \
 }
@@ -214,6 +234,8 @@ struct thread_struct {
 #define thread_saved_pc(tsk)    \
         ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 
+#define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.regs)
+
 unsigned long get_wchan(struct task_struct *p);
 
 #define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index 78b7b0d494c0..eb3bd2e1c7f6 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -212,8 +212,16 @@ extern u64 of_translate_dma_address(struct device_node *dev,
  */
 extern const u32 *of_get_address(struct device_node *dev, int index,
                            u64 *size, unsigned int *flags);
+#ifdef CONFIG_PCI
 extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
                                u64 *size, unsigned int *flags);
+#else
+static inline const u32 *of_get_pci_address(struct device_node *dev,
+                int bar_no, u64 *size, unsigned int *flags)
+{
+        return NULL;
+}
+#endif /* CONFIG_PCI */
 
 /* Get an address as a resource. Note that if your address is
  * a PIO address, the conversion will fail if the physical address
@@ -223,8 +231,16 @@ extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
  */
 extern int of_address_to_resource(struct device_node *dev, int index,
                                   struct resource *r);
+#ifdef CONFIG_PCI
 extern int of_pci_address_to_resource(struct device_node *dev, int bar,
                                       struct resource *r);
+#else
+static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
+                struct resource *r)
+{
+        return -ENOSYS;
+}
+#endif /* CONFIG_PCI */
 
 /* Parse the ibm,dma-window property of an OF node into the busno, phys and
  * size parameters.
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 39023dde1cc4..3d6e31024e56 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -119,6 +119,7 @@ extern int ptrace_put_reg(struct task_struct *task, int regno,
 #ifndef __powerpc64__
 #define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) != 0)
 #define IS_MCHECK_EXC(regs)     (((regs)->trap & 4) != 0)
+#define IS_DEBUG_EXC(regs)      (((regs)->trap & 8) != 0)
 #endif /* ! __powerpc64__ */
 #define TRAP(regs)              ((regs)->trap & ~0xF)
 #ifdef __powerpc64__
@@ -223,6 +224,14 @@ extern void user_disable_single_step(struct task_struct *);
 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
 #endif
 
+/*
+ * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
+ */
+#define PT_VSR0 150     /* each VSR reg occupies 2 slots in 64-bit */
+#define PT_VSR31 (PT_VSR0 + 2*31)
+#ifdef __KERNEL__
+#define PT_VSR0_32 300  /* each VSR reg occupies 4 slots in 32-bit */
+#endif
 #endif /* __powerpc64__ */
 
 /*
@@ -245,6 +254,10 @@ extern void user_disable_single_step(struct task_struct *);
 #define PTRACE_GETEVRREGS       20
 #define PTRACE_SETEVRREGS       21
 
+/* Get the first 32 128bit VSX registers */
+#define PTRACE_GETVSRREGS       27
+#define PTRACE_SETVSRREGS       28
+
 /*
  * Get or set a debug register. The first 16 are DABR registers and the
  * second 16 are IABR registers.
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index c3be6e2e1490..edee15d269ea 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -16,6 +16,8 @@
 #define _ASM_POWERPC_QE_H
 #ifdef __KERNEL__
 
+#include <linux/spinlock.h>
+#include <asm/cpm.h>
 #include <asm/immap_qe.h>
 
 #define QE_NUM_OF_SNUM  28
@@ -74,10 +76,38 @@ enum qe_clock {
         QE_CLK_DUMMY
 };
 
+static inline bool qe_clock_is_brg(enum qe_clock clk)
+{
+        return clk >= QE_BRG1 && clk <= QE_BRG16;
+}
+
+extern spinlock_t cmxgcr_lock;
+
 /* Export QE common operations */
-extern void qe_reset(void);
+extern void __init qe_reset(void);
+
+/* QE PIO */
+#define QE_PIO_PINS 32
+
+struct qe_pio_regs {
+        __be32  cpodr;          /* Open drain register */
+        __be32  cpdata;         /* Data register */
+        __be32  cpdir1;         /* Direction register */
+        __be32  cpdir2;         /* Direction register */
+        __be32  cppar1;         /* Pin assignment register */
+        __be32  cppar2;         /* Pin assignment register */
+#ifdef CONFIG_PPC_85xx
+        u8      pad[8];
+#endif
+};
+
 extern int par_io_init(struct device_node *np);
 extern int par_io_of_config(struct device_node *np);
+#define QE_PIO_DIR_IN   2
+#define QE_PIO_DIR_OUT  1
+extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
+                                int dir, int open_drain, int assignment,
+                                int has_irq);
 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
                              int assignment, int has_irq);
 extern int par_io_data_set(u8 port, u8 pin, u8 val);
@@ -89,20 +119,13 @@ unsigned int qe_get_brg_clk(void);
 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
-unsigned long qe_muram_alloc(int size, int align);
-int qe_muram_free(unsigned long offset);
-unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
-void qe_muram_dump(void);
-
-static inline void __iomem *qe_muram_addr(unsigned long offset)
-{
-        return (void __iomem *)&qe_immr->muram[offset];
-}
-
-static inline unsigned long qe_muram_offset(void __iomem *addr)
-{
-        return addr - (void __iomem *)qe_immr->muram;
-}
+/* we actually use cpm_muram implementation, define this for convenience */
+#define qe_muram_init cpm_muram_init
+#define qe_muram_alloc cpm_muram_alloc
+#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
+#define qe_muram_free cpm_muram_free
+#define qe_muram_addr cpm_muram_addr
+#define qe_muram_offset cpm_muram_offset
 
 /* Structure that defines QE firmware binary files.
  *
@@ -156,6 +179,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware);
 /* Obtain information on the uploaded firmware */
 struct qe_firmware_info *qe_get_firmware_info(void);
 
+/* QE USB */
+int qe_usb_clock_set(enum qe_clock clk, int rate);
+
 /* Buffer descriptors */
 struct qe_bd {
         __be16 status;
@@ -166,20 +192,6 @@ struct qe_bd {
 #define BD_STATUS_MASK  0xffff0000
 #define BD_LENGTH_MASK  0x0000ffff
 
-#define BD_SC_EMPTY     0x8000  /* Receive is empty */
-#define BD_SC_READY     0x8000  /* Transmit is ready */
-#define BD_SC_WRAP      0x2000  /* Last buffer descriptor */
-#define BD_SC_INTRPT    0x1000  /* Interrupt on change */
-#define BD_SC_LAST      0x0800  /* Last buffer in frame */
-#define BD_SC_CM        0x0200  /* Continous mode */
-#define BD_SC_ID        0x0100  /* Rec'd too many idles */
-#define BD_SC_P         0x0100  /* xmt preamble */
-#define BD_SC_BR        0x0020  /* Break received */
-#define BD_SC_FR        0x0010  /* Framing error */
-#define BD_SC_PR        0x0008  /* Parity error */
-#define BD_SC_OV        0x0002  /* Overrun */
-#define BD_SC_CD        0x0001  /* ?? */
-
 /* Alignment */
 #define QE_INTR_TABLE_ALIGN     16      /* ??? */
 #define QE_ALIGNMENT_OF_BD      8
@@ -254,6 +266,16 @@ enum comm_dir {
 #define QE_CMXGCR_MII_ENET_MNG          0x00007000
 #define QE_CMXGCR_MII_ENET_MNG_SHIFT    12
 #define QE_CMXGCR_USBCS                 0x0000000f
+#define QE_CMXGCR_USBCS_CLK3            0x1
+#define QE_CMXGCR_USBCS_CLK5            0x2
+#define QE_CMXGCR_USBCS_CLK7            0x3
+#define QE_CMXGCR_USBCS_CLK9            0x4
+#define QE_CMXGCR_USBCS_CLK13           0x5
+#define QE_CMXGCR_USBCS_CLK17           0x6
+#define QE_CMXGCR_USBCS_CLK19           0x7
+#define QE_CMXGCR_USBCS_CLK21           0x8
+#define QE_CMXGCR_USBCS_BRG9            0x9
+#define QE_CMXGCR_USBCS_BRG10           0xa
 
 /* QE CECR Commands.
 */
@@ -283,7 +305,7 @@ enum comm_dir {
 #define QE_HPAC_START_TX                0x0000060b
 #define QE_HPAC_START_RX                0x0000070b
 #define QE_USB_STOP_TX                  0x0000000a
-#define QE_USB_RESTART_TX               0x0000000b
+#define QE_USB_RESTART_TX               0x0000000c
 #define QE_QMC_STOP_TX                  0x0000000c
 #define QE_QMC_STOP_RX                  0x0000000d
 #define QE_SS7_SU_FIL_RESET             0x0000000e
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index edc0cfd7f6e2..bbccadfee0d6 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -30,6 +30,7 @@
 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
 #define MSR_HV_LG       60              /* Hypervisor state */
 #define MSR_VEC_LG      25              /* Enable AltiVec */
+#define MSR_VSX_LG      23              /* Enable VSX */
 #define MSR_POW_LG      18              /* Enable Power Management */
 #define MSR_WE_LG       18              /* Wait State Enable */
 #define MSR_TGPR_LG     17              /* TLB Update registers in use */
@@ -71,6 +72,7 @@
 #endif
 
 #define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
+#define MSR_VSX         __MASK(MSR_VSX_LG)      /* Enable VSX */
 #define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
 #define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
 #define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
@@ -240,7 +242,7 @@
 #define HID0_DAPUEN     (1<<8)          /* Debug APU enable */
 #define HID0_SGE        (1<<7)          /* Store Gathering Enable */
 #define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
-#define HID0_DFCA       (1<<6)          /* Data Cache Flush Assist */
+#define HID0_DCFA       (1<<6)          /* Data Cache Flush Assist */
 #define HID0_LRSTK      (1<<4)          /* Link register stack - 745x */
 #define HID0_BTIC       (1<<5)          /* Branch Target Instr Cache Enable */
 #define HID0_ABE        (1<<3)          /* Address Broadcast Enable */
@@ -732,6 +734,8 @@
                                 "       .llong %1\n"                    \
                                 "       .llong 97b-98b\n"               \
                                 "       .llong 99b-98b\n"               \
+                                "       .llong 0\n"                     \
+                                "       .llong 0\n"                     \
                                 ".previous"                             \
                         : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
 #else
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index cf54a3f31753..be980f4ee495 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -61,6 +61,8 @@
 #define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
 #define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
 #define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
+#define SPRN_L1CFG0     0x203   /* L1 Cache Configure Register 0 */
+#define SPRN_L1CFG1     0x204   /* L1 Cache Configure Register 1 */
 #define SPRN_ATB        0x20E   /* Alternate Time Base */
 #define SPRN_ATBL       0x20E   /* Alternate Time Base Lower */
 #define SPRN_ATBU       0x20F   /* Alternate Time Base Upper */
@@ -78,6 +80,7 @@
 #define SPRN_DSRR1      0x23F   /* Debug Save and Restore Register 1 */
 #define SPRN_SPRG8      0x25C   /* Special Purpose Register General 8 */
 #define SPRN_SPRG9      0x25D   /* Special Purpose Register General 9 */
+#define SPRN_L1CSR2     0x25E   /* L1 Cache Control and Status Register 2 */
 #define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
 #define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
 #define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
@@ -108,6 +111,8 @@
 #define SPRN_L1CSR1     0x3F3   /* L1 Cache Control and Status Register 1 */
 #define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 #define SPRN_BUCSR      0x3F5   /* Branch Unit Control and Status */
+#define SPRN_L2CSR0     0x3F9   /* L2 Data Cache Control and Status Register 0 */
+#define SPRN_L2CSR1     0x3FA   /* L2 Data Cache Control and Status Register 1 */
 #define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 #define SPRN_SVR        0x3FF   /* System Version Register */
@@ -210,6 +215,7 @@
 #ifdef CONFIG_BOOKE
 #define DBSR_IC         0x08000000      /* Instruction Completion */
 #define DBSR_BT         0x04000000      /* Branch Taken */
+#define DBSR_IRPT       0x02000000      /* Exception Debug Event */
 #define DBSR_TIE        0x01000000      /* Trap Instruction Event */
 #define DBSR_IAC1       0x00800000      /* Instr Address Compare 1 Event */
 #define DBSR_IAC2       0x00400000      /* Instr Address Compare 2 Event */
@@ -219,10 +225,14 @@
 #define DBSR_DAC1W      0x00040000      /* Data Addr Compare 1 Write Event */
 #define DBSR_DAC2R      0x00020000      /* Data Addr Compare 2 Read Event */
 #define DBSR_DAC2W      0x00010000      /* Data Addr Compare 2 Write Event */
+#define DBSR_RET        0x00008000      /* Return Debug Event */
+#define DBSR_CIRPT      0x00000040      /* Critical Interrupt Taken Event */
+#define DBSR_CRET       0x00000020      /* Critical Return Debug Event */
 #endif
 #ifdef CONFIG_40x
 #define DBSR_IC         0x80000000      /* Instruction Completion */
 #define DBSR_BT         0x40000000      /* Branch taken */
+#define DBSR_IRPT       0x20000000      /* Exception Debug Event */
 #define DBSR_TIE        0x10000000      /* Trap Instruction debug Event */
 #define DBSR_IAC1       0x04000000      /* Instruction Address Compare 1 Event */
 #define DBSR_IAC2       0x02000000      /* Instruction Address Compare 2 Event */
@@ -253,6 +263,7 @@
 #define ESR_BO          0x00020000      /* Byte Ordering */
 
 /* Bit definitions related to the DBCR0. */
+#if defined(CONFIG_40x)
 #define DBCR0_EDM       0x80000000      /* External Debug Mode */
 #define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
 #define DBCR0_RST       0x30000000      /* all the bits in the RST field */
@@ -261,20 +272,69 @@
 #define DBCR0_RST_CORE  0x10000000      /* Core Reset */
 #define DBCR0_RST_NONE  0x00000000      /* No Reset */
 #define DBCR0_IC        0x08000000      /* Instruction Completion */
+#define DBCR0_ICMP      DBCR0_IC
 #define DBCR0_BT        0x04000000      /* Branch Taken */
+#define DBCR0_BRT       DBCR0_BT
 #define DBCR0_EDE       0x02000000      /* Exception Debug Event */
+#define DBCR0_IRPT      DBCR0_EDE
 #define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
 #define DBCR0_IA1       0x00800000      /* Instr Addr compare 1 enable */
+#define DBCR0_IAC1      DBCR0_IA1
 #define DBCR0_IA2       0x00400000      /* Instr Addr compare 2 enable */
+#define DBCR0_IAC2      DBCR0_IA2
 #define DBCR0_IA12      0x00200000      /* Instr Addr 1-2 range enable */
 #define DBCR0_IA12X     0x00100000      /* Instr Addr 1-2 range eXclusive */
 #define DBCR0_IA3       0x00080000      /* Instr Addr compare 3 enable */
+#define DBCR0_IAC3      DBCR0_IA3
 #define DBCR0_IA4       0x00040000      /* Instr Addr compare 4 enable */
+#define DBCR0_IAC4      DBCR0_IA4
 #define DBCR0_IA34      0x00020000      /* Instr Addr 3-4 range Enable */
 #define DBCR0_IA34X     0x00010000      /* Instr Addr 3-4 range eXclusive */
 #define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
 #define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
 #define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
+#elif defined(CONFIG_BOOKE)
+#define DBCR0_EDM       0x80000000      /* External Debug Mode */
+#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
+#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
+/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
+#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
+#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
+#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
+#define DBCR0_RST_NONE  0x00000000      /* No Reset */
+#define DBCR0_ICMP      0x08000000      /* Instruction Completion */
+#define DBCR0_IC        DBCR0_ICMP
+#define DBCR0_BRT       0x04000000      /* Branch Taken */
+#define DBCR0_BT        DBCR0_BRT
+#define DBCR0_IRPT      0x02000000      /* Exception Debug Event */
+#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
+#define DBCR0_TIE       DBCR0_TDE
+#define DBCR0_IAC1      0x00800000      /* Instr Addr compare 1 enable */
+#define DBCR0_IAC2      0x00400000      /* Instr Addr compare 2 enable */
+#define DBCR0_IAC3      0x00200000      /* Instr Addr compare 3 enable */
+#define DBCR0_IAC4      0x00100000      /* Instr Addr compare 4 enable */
+#define DBCR0_DAC1R     0x00080000      /* DAC 1 Read enable */
+#define DBCR0_DAC1W     0x00040000      /* DAC 1 Write enable */
+#define DBCR0_DAC2R     0x00020000      /* DAC 2 Read enable */
+#define DBCR0_DAC2W     0x00010000      /* DAC 2 Write enable */
+#define DBCR0_RET       0x00008000      /* Return Debug Event */
+#define DBCR0_CIRPT     0x00000040      /* Critical Interrupt Taken Event */
+#define DBCR0_CRET      0x00000020      /* Critical Return Debug Event */
+#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_IAC12M    0x00800000      /* Instr Addr 1-2 range enable */
+#define DBCR1_IAC12MX   0x00C00000      /* Instr Addr 1-2 range eXclusive */
+#define DBCR1_IAC12AT   0x00010000      /* Instr Addr 1-2 range Toggle */
+#define DBCR1_IAC34M    0x00000080      /* Instr Addr 3-4 range enable */
+#define DBCR1_IAC34MX   0x000000C0      /* Instr Addr 3-4 range eXclusive */
+#define DBCR1_IAC34AT   0x00000001      /* Instr Addr 3-4 range Toggle */
+
+/* Bit definitions related to the DBCR2. */
+#define DBCR2_DAC12M    0x00800000      /* DAC 1-2 range enable */
+#define DBCR2_DAC12MX   0x00C00000      /* DAC 1-2 range eXclusive */
+#define DBCR2_DAC12A    0x00200000      /* DAC 1-2 Asynchronous */
+#endif
 
 /* Bit definitions related to the TCR. */
 #define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
@@ -336,6 +396,20 @@
 #define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
 #define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
 
+/* Bit definitions for L2CSR0. */
+#define L2CSR0_L2E      0x80000000      /* L2 Cache Enable */
+#define L2CSR0_L2PE     0x40000000      /* L2 Cache Parity/ECC Enable */
+#define L2CSR0_L2WP     0x1c000000      /* L2 I/D Way Partioning */
+#define L2CSR0_L2CM     0x03000000      /* L2 Cache Coherency Mode */
+#define L2CSR0_L2FI     0x00200000      /* L2 Cache Flash Invalidate */
+#define L2CSR0_L2IO     0x00100000      /* L2 Cache Instruction Only */
+#define L2CSR0_L2DO     0x00010000      /* L2 Cache Data Only */
+#define L2CSR0_L2REP    0x00003000      /* L2 Line Replacement Algo */
+#define L2CSR0_L2FL     0x00000800      /* L2 Cache Flush */
+#define L2CSR0_L2LFC    0x00000400      /* L2 Cache Lock Flash Clear */
+#define L2CSR0_L2LOA    0x00000080      /* L2 Cache Lock Overflow Allocate */
+#define L2CSR0_L2LO     0x00000020      /* L2 Cache Lock Overflow */
+
 /* Bit definitions for SGR. */
 #define SGR_NORMAL      0               /* Speculative fetching allowed. */
 #define SGR_GUARDED     1               /* Speculative fetching disallowed. */
diff --git a/include/asm-powerpc/sigcontext.h b/include/asm-powerpc/sigcontext.h
index 165d630e1cf3..9c1f24fd5d11 100644
--- a/include/asm-powerpc/sigcontext.h
+++ b/include/asm-powerpc/sigcontext.h
@@ -43,9 +43,44 @@ struct sigcontext {
  * it must be copied via a vector register to/from storage) or as a word.
  * The entry with index 33 contains the vrsave as the first word (offset 0)
  * within the quadword.
+ *
+ * Part of the VSX data is stored here also by extending vmx_restore
+ * by an additional 32 double words.  Architecturally the layout of
+ * the VSR registers and how they overlap on top of the legacy FPR and
+ * VR registers is shown below:
+ *
+ *                    VSR doubleword 0               VSR doubleword 1
+ *           ----------------------------------------------------------------
+ *   VSR[0]  |             FPR[0]            |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[1]  |             FPR[1]            |                              |
+ *           ----------------------------------------------------------------
+ *           |              ...              |                              |
+ *           |              ...              |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[30] |             FPR[30]           |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[31] |             FPR[31]           |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[32] |                             VR[0]                            |
+ *           ----------------------------------------------------------------
+ *   VSR[33] |                             VR[1]                            |
+ *           ----------------------------------------------------------------
+ *           |                              ...                             |
+ *           |                              ...                             |
+ *           ----------------------------------------------------------------
+ *   VSR[62] |                             VR[30]                           |
+ *           ----------------------------------------------------------------
+ *   VSR[63] |                             VR[31]                           |
+ *           ----------------------------------------------------------------
+ *
+ * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
+ * is stored at the start of vmx_reserve.  vmx_reserve is extended for
+ * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
+ * registers and vscr/vrsave.
  */
         elf_vrreg_t     __user *v_regs;
-        long            vmx_reserve[ELF_NVRREG+ELF_NVRREG+1];
+        long            vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
 #endif
 };
 
diff --git a/include/asm-powerpc/smp.h b/include/asm-powerpc/smp.h
index 505f35bacaa9..416d4c288cea 100644
--- a/include/asm-powerpc/smp.h
+++ b/include/asm-powerpc/smp.h
@@ -37,6 +37,8 @@ extern void cpu_die(void);
 extern void smp_send_debugger_break(int cpu);
 extern void smp_message_recv(int);
 
+DECLARE_PER_CPU(unsigned int, pvr);
+
 #ifdef CONFIG_HOTPLUG_CPU
 extern void fixup_irqs(cpumask_t map);
 int generic_cpu_disable(void);
@@ -67,10 +69,7 @@ DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
  * in /proc/interrupts will be wrong!!! --Troy */
 #define PPC_MSG_CALL_FUNCTION   0
 #define PPC_MSG_RESCHEDULE      1
-/* This is unused now */
-#if 0
-#define PPC_MSG_MIGRATE_TASK    2
-#endif
+#define PPC_MSG_CALL_FUNC_SINGLE        2
 #define PPC_MSG_DEBUGGER_BREAK  3
 
 void smp_init_iSeries(void);
@@ -117,6 +116,9 @@ extern void smp_generic_take_timebase(void);
 
 extern struct smp_ops_t *smp_ops;
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index 9aea8e9f0bd1..54a47ea2c3aa 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -13,6 +13,8 @@
 #define MAX_PHYSADDR_BITS       44
 #define MAX_PHYSMEM_BITS        44
 
+#endif /* CONFIG_SPARSEMEM */
+
 #ifdef CONFIG_MEMORY_HOTPLUG
 extern void create_section_mapping(unsigned long start, unsigned long end);
 extern int remove_section_mapping(unsigned long start, unsigned long end);
@@ -26,7 +28,5 @@ static inline int hot_add_scn_to_nid(unsigned long scn_addr)
 #endif /* CONFIG_NUMA */
 #endif /* CONFIG_MEMORY_HOTPLUG */
 
-#endif /* CONFIG_SPARSEMEM */
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/include/asm-powerpc/spinlock.h b/include/asm-powerpc/spinlock.h
index 258c93993190..f56a843f4705 100644
--- a/include/asm-powerpc/spinlock.h
+++ b/include/asm-powerpc/spinlock.h
@@ -54,7 +54,7 @@
  * This returns the old value in the lock, so we succeeded
  * in getting the lock if the return value is 0.
  */
-static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock)
+static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
 {
         unsigned long tmp, token;
 
@@ -73,7 +73,7 @@ static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock)
         return tmp;
 }
 
-static int __inline__ __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
 {
         CLEAR_IO_SYNC;
         return __spin_trylock(lock) == 0;
@@ -104,7 +104,7 @@ extern void __rw_yield(raw_rwlock_t *lock);
 #define SHARED_PROCESSOR        0
 #endif
 
-static void __inline__ __raw_spin_lock(raw_spinlock_t *lock)
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
 {
         CLEAR_IO_SYNC;
         while (1) {
@@ -119,7 +119,8 @@ static void __inline__ __raw_spin_lock(raw_spinlock_t *lock)
         }
 }
 
-static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+static inline
+void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
 {
         unsigned long flags_dis;
 
@@ -139,7 +140,7 @@ static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long
         }
 }
 
-static __inline__ void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
         SYNC_IO;
         __asm__ __volatile__("# __raw_spin_unlock\n\t"
@@ -180,7 +181,7 @@ extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
  * This returns the old value in the lock + 1,
  * so we got a read lock if the return value is > 0.
  */
-static long __inline__ __read_trylock(raw_rwlock_t *rw)
+static inline long __read_trylock(raw_rwlock_t *rw)
 {
         long tmp;
 
@@ -204,7 +205,7 @@ static long __inline__ __read_trylock(raw_rwlock_t *rw)
  * This returns the old value in the lock,
  * so we got the write lock if the return value is 0.
  */
-static __inline__ long __write_trylock(raw_rwlock_t *rw)
+static inline long __write_trylock(raw_rwlock_t *rw)
 {
         long tmp, token;
 
@@ -224,7 +225,7 @@ static __inline__ long __write_trylock(raw_rwlock_t *rw)
         return tmp;
 }
 
-static void __inline__ __raw_read_lock(raw_rwlock_t *rw)
+static inline void __raw_read_lock(raw_rwlock_t *rw)
 {
         while (1) {
                 if (likely(__read_trylock(rw) > 0))
@@ -238,7 +239,7 @@ static void __inline__ __raw_read_lock(raw_rwlock_t *rw)
         }
 }
 
-static void __inline__ __raw_write_lock(raw_rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
         while (1) {
                 if (likely(__write_trylock(rw) == 0))
@@ -252,17 +253,17 @@ static void __inline__ __raw_write_lock(raw_rwlock_t *rw)
         }
 }
 
-static int __inline__ __raw_read_trylock(raw_rwlock_t *rw)
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
 {
         return __read_trylock(rw) > 0;
 }
 
-static int __inline__ __raw_write_trylock(raw_rwlock_t *rw)
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
         return __write_trylock(rw) == 0;
 }
 
-static void __inline__ __raw_read_unlock(raw_rwlock_t *rw)
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
         long tmp;
 
@@ -279,7 +280,7 @@ static void __inline__ __raw_read_unlock(raw_rwlock_t *rw)
         : "cr0", "memory");
 }
 
-static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
 {
         __asm__ __volatile__("# write_unlock\n\t"
                                 LWSYNC_ON_SMP: : :"memory");
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 99348c1f4cab..8b2eb044270a 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -191,6 +191,7 @@ struct cbe_spu_info {
         struct list_head spus;
         int n_spus;
         int nr_active;
+        atomic_t busy_spus;
         atomic_t reserved_spus;
 };
 
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
index 2cda3c38a9fa..45963e80f557 100644
--- a/include/asm-powerpc/synch.h
+++ b/include/asm-powerpc/synch.h
@@ -3,34 +3,42 @@
 #ifdef __KERNEL__
 
 #include <linux/stringify.h>
+#include <asm/feature-fixups.h>
 
-#ifdef __powerpc64__
-#define __SUBARCH_HAS_LWSYNC
-#endif
+#ifndef __ASSEMBLY__
+extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
+extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
+                             void *fixup_end);
+
+static inline void eieio(void)
+{
+        __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void isync(void)
+{
+        __asm__ __volatile__ ("isync" : : : "memory");
+}
+#endif /* __ASSEMBLY__ */
 
-#ifdef __SUBARCH_HAS_LWSYNC
+#if defined(__powerpc64__)
 #    define LWSYNC      lwsync
+#elif defined(CONFIG_E500)
+#    define LWSYNC                                      \
+        START_LWSYNC_SECTION(96);                       \
+        sync;                                           \
+        MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
 #else
 #    define LWSYNC      sync
 #endif
 
 #ifdef CONFIG_SMP
 #define ISYNC_ON_SMP    "\n\tisync\n"
-#define LWSYNC_ON_SMP   __stringify(LWSYNC) "\n"
+#define LWSYNC_ON_SMP   stringify_in_c(LWSYNC) "\n"
 #else
 #define ISYNC_ON_SMP
 #define LWSYNC_ON_SMP
 #endif
 
-static inline void eieio(void)
-{
-        __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-static inline void isync(void)
-{
-        __asm__ __volatile__ ("isync" : : : "memory");
-}
-
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_SYNCH_H */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 5235f875b932..e6e25e2364eb 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -30,8 +30,8 @@
  *
  * For wmb(), we use sync since wmb is used in drivers to order
  * stores to system memory with respect to writes to the device.
- * However, smp_wmb() can be a lighter-weight eieio barrier on
- * SMP since it is only used to order updates to system memory.
+ * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier
+ * on SMP since it is only used to order updates to system memory.
  */
 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
@@ -43,9 +43,16 @@
 #ifdef __KERNEL__
 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
 #ifdef CONFIG_SMP
+
+#ifdef __SUBARCH_HAS_LWSYNC
+#    define SMPWMB      lwsync
+#else
+#    define SMPWMB      eieio
+#endif
+
 #define smp_mb()        mb()
 #define smp_rmb()       rmb()
-#define smp_wmb()       eieio()
+#define smp_wmb()       __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory")
 #define smp_read_barrier_depends()      read_barrier_depends()
 #else
 #define smp_mb()        barrier()
@@ -132,6 +139,8 @@ extern void enable_kernel_altivec(void);
 extern void giveup_altivec(struct task_struct *);
 extern void load_up_altivec(struct task_struct *);
 extern int emulate_altivec(struct pt_regs *);
+extern void __giveup_vsx(struct task_struct *);
+extern void giveup_vsx(struct task_struct *);
 extern void enable_kernel_spe(void);
 extern void giveup_spe(struct task_struct *);
 extern void load_up_spe(struct task_struct *);
@@ -155,6 +164,14 @@ static inline void flush_altivec_to_thread(struct task_struct *t)
 }
 #endif
 
+#ifdef CONFIG_VSX
+extern void flush_vsx_to_thread(struct task_struct *);
+#else
+static inline void flush_vsx_to_thread(struct task_struct *t)
+{
+}
+#endif
+
 #ifdef CONFIG_SPE
 extern void flush_spe_to_thread(struct task_struct *);
 #else
@@ -190,6 +207,7 @@ extern struct task_struct *_switch(struct thread_struct *prev,
 
 extern unsigned int rtas_data;
 extern int mem_init_done;       /* set on boot once kmalloc can be called */
+extern int init_bootmem_done;   /* set on !NUMA once bootmem is available */
 extern unsigned long memory_limit;
 extern unsigned long klimit;
 
@@ -518,54 +536,6 @@ extern void reloc_got2(unsigned long);
 
 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 
-static inline void create_instruction(unsigned long addr, unsigned int instr)
-{
-        unsigned int *p;
-        p  = (unsigned int *)addr;
-        *p = instr;
-        asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
-}
-
-/* Flags for create_branch:
- * "b"   == create_branch(addr, target, 0);
- * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
- * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
- * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
- */
-#define BRANCH_SET_LINK 0x1
-#define BRANCH_ABSOLUTE 0x2
-
-static inline void create_branch(unsigned long addr,
-                unsigned long target, int flags)
-{
-        unsigned int instruction;
-
-        if (! (flags & BRANCH_ABSOLUTE))
-                target = target - addr;
-
-        /* Mask out the flags and target, so they don't step on each other. */
-        instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
-
-        create_instruction(addr, instruction);
-}
-
-static inline void create_function_call(unsigned long addr, void * func)
-{
-        unsigned long func_addr;
-
-#ifdef CONFIG_PPC64
-        /*
-         * On PPC64 the function pointer actually points to the function's
-         * descriptor. The first entry in the descriptor is the address
-         * of the function text.
-         */
-        func_addr = *(unsigned long *)func;
-#else
-        func_addr = (unsigned long)func;
-#endif
-        create_branch(addr, func_addr, BRANCH_SET_LINK);
-}
-
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 extern void account_system_vtime(struct task_struct *);
 #endif
diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h
index d030f5ce39ad..b705c2a7651a 100644
--- a/include/asm-powerpc/thread_info.h
+++ b/include/asm-powerpc/thread_info.h
@@ -116,7 +116,6 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_SECCOMP             10      /* secure computing */
 #define TIF_RESTOREALL          11      /* Restore all regs (implies NOERROR) */
 #define TIF_NOERROR             12      /* Force successful syscall return */
-#define TIF_RESTORE_SIGMASK     13      /* Restore signal mask in do_signal */
 #define TIF_FREEZE              14      /* Freezing for suspend */
 #define TIF_RUNLATCH            15      /* Is the runlatch enabled? */
 #define TIF_ABI_PENDING         16      /* 32/64 bit switch needed */
@@ -134,21 +133,33 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_RESTOREALL         (1<<TIF_RESTOREALL)
 #define _TIF_NOERROR            (1<<TIF_NOERROR)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
 #define _TIF_RUNLATCH           (1<<TIF_RUNLATCH)
 #define _TIF_ABI_PENDING        (1<<TIF_ABI_PENDING)
 #define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
 
-#define _TIF_USER_WORK_MASK     ( _TIF_SIGPENDING | \
-                                 _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK)
+#define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
 #define _TIF_PERSYSCALL_MASK    (_TIF_RESTOREALL|_TIF_NOERROR)
 
 /* Bits in local_flags */
 /* Don't move TLF_NAPPING without adjusting the code in entry_32.S */
 #define TLF_NAPPING             0       /* idle thread enabled NAP mode */
+#define TLF_SLEEPING            1       /* suspend code enabled SLEEP mode */
+#define TLF_RESTORE_SIGMASK     2       /* Restore signal mask in do_signal */
 
 #define _TLF_NAPPING            (1 << TLF_NAPPING)
+#define _TLF_SLEEPING           (1 << TLF_SLEEPING)
+#define _TLF_RESTORE_SIGMASK    (1 << TLF_RESTORE_SIGMASK)
+
+#ifndef __ASSEMBLY__
+#define HAVE_SET_RESTORE_SIGMASK        1
+static inline void set_restore_sigmask(void)
+{
+        struct thread_info *ti = current_thread_info();
+        ti->local_flags |= _TLF_RESTORE_SIGMASK;
+        set_bit(TIF_SIGPENDING, &ti->flags);
+}
+#endif  /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index ce5de6e0e690..febd581ec9b0 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -33,6 +33,7 @@ extern unsigned      tb_to_us;
 
 struct rtc_time;
 extern void to_tm(int tim, struct rtc_time * tm);
+extern void GregorianDay(struct rtc_time *tm);
 extern time_t last_rtc_update;
 
 extern void generic_calibrate_decr(void);
diff --git a/include/asm-powerpc/timex.h b/include/asm-powerpc/timex.h
index 92dedde761d1..c55e14f7ef44 100644
--- a/include/asm-powerpc/timex.h
+++ b/include/asm-powerpc/timex.h
@@ -38,6 +38,8 @@ static inline cycles_t get_cycles(void)
                 "       .long 0\n"
                 "       .long 97b-98b\n"
                 "       .long 99b-98b\n"
+                "       .long 0\n"
+                "       .long 0\n"
                 ".previous"
                 : "=r" (ret) : "i" (CPU_FTR_601));
         return ret;
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
index 88320a05f0a8..5eb8e599e5cc 100644
--- a/include/asm-powerpc/xmon.h
+++ b/include/asm-powerpc/xmon.h
@@ -12,13 +12,22 @@
 
 #ifdef __KERNEL__
 
+#include <linux/irqreturn.h>
+
 #ifdef CONFIG_XMON
 extern void xmon_setup(void);
 extern void xmon_register_spus(struct list_head *list);
+struct pt_regs;
+extern int xmon(struct pt_regs *excp);
+extern irqreturn_t xmon_irq(int, void *);
 #else
 static inline void xmon_setup(void) { };
 static inline void xmon_register_spus(struct list_head *list) { };
 #endif
 
+#if defined(CONFIG_XMON) && defined(CONFIG_SMP)
+extern int cpus_are_in_xmon(void);
+#endif
+
 #endif /* __KERNEL __ */
 #endif /* __ASM_POWERPC_XMON_H */
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h
deleted file mode 100644
index 4b0e15206006..000000000000
--- a/include/asm-ppc/8xx_immap.h
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * MPC8xx Internal Memory Map
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * The I/O on the MPC860 is comprised of blocks of special registers
- * and the dual port ram for the Communication Processor Module.
- * Within this space are functional units such as the SIU, memory
- * controller, system timers, and other control functions.  It is
- * a combination that I found difficult to separate into logical
- * functional files.....but anyone else is welcome to try.  -- Dan
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_8XX__
-#define __IMMAP_8XX__
-
-/* System configuration registers.
-*/
-typedef struct sys_conf {
-        uint    sc_siumcr;
-        uint    sc_sypcr;
-        uint    sc_swt;
-        char    res1[2];
-        ushort  sc_swsr;
-        uint    sc_sipend;
-        uint    sc_simask;
-        uint    sc_siel;
-        uint    sc_sivec;
-        uint    sc_tesr;
-        char    res2[0xc];
-        uint    sc_sdcr;
-        char    res3[0x4c];
-} sysconf8xx_t;
-
-/* PCMCIA configuration registers.
-*/
-typedef struct pcmcia_conf {
-        uint    pcmc_pbr0;
-        uint    pcmc_por0;
-        uint    pcmc_pbr1;
-        uint    pcmc_por1;
-        uint    pcmc_pbr2;
-        uint    pcmc_por2;
-        uint    pcmc_pbr3;
-        uint    pcmc_por3;
-        uint    pcmc_pbr4;
-        uint    pcmc_por4;
-        uint    pcmc_pbr5;
-        uint    pcmc_por5;
-        uint    pcmc_pbr6;
-        uint    pcmc_por6;
-        uint    pcmc_pbr7;
-        uint    pcmc_por7;
-        char    res1[0x20];
-        uint    pcmc_pgcra;
-        uint    pcmc_pgcrb;
-        uint    pcmc_pscr;
-        char    res2[4];
-        uint    pcmc_pipr;
-        char    res3[4];
-        uint    pcmc_per;
-        char    res4[4];
-} pcmconf8xx_t;
-
-/* Memory controller registers.
-*/
-typedef struct  mem_ctlr {
-        uint    memc_br0;
-        uint    memc_or0;
-        uint    memc_br1;
-        uint    memc_or1;
-        uint    memc_br2;
-        uint    memc_or2;
-        uint    memc_br3;
-        uint    memc_or3;
-        uint    memc_br4;
-        uint    memc_or4;
-        uint    memc_br5;
-        uint    memc_or5;
-        uint    memc_br6;
-        uint    memc_or6;
-        uint    memc_br7;
-        uint    memc_or7;
-        char    res1[0x24];
-        uint    memc_mar;
-        uint    memc_mcr;
-        char    res2[4];
-        uint    memc_mamr;
-        uint    memc_mbmr;
-        ushort  memc_mstat;
-        ushort  memc_mptpr;
-        uint    memc_mdr;
-        char    res3[0x80];
-} memctl8xx_t;
-
-/*-----------------------------------------------------------------------
- * BR - Memory Controler: Base Register                                 16-9
- */
-#define BR_BA_MSK       0xffff8000      /* Base Address Mask                    */
-#define BR_AT_MSK       0x00007000      /* Address Type Mask                    */
-#define BR_PS_MSK       0x00000c00      /* Port Size Mask                       */
-#define BR_PS_32        0x00000000      /* 32 bit port size                     */
-#define BR_PS_16        0x00000800      /* 16 bit port size                     */
-#define BR_PS_8         0x00000400      /*  8 bit port size                     */
-#define BR_PARE         0x00000200      /* Parity Enable                        */
-#define BR_WP           0x00000100      /* Write Protect                        */
-#define BR_MS_MSK       0x000000c0      /* Machine Select Mask                  */
-#define BR_MS_GPCM      0x00000000      /* G.P.C.M. Machine Select              */
-#define BR_MS_UPMA      0x00000080      /* U.P.M.A Machine Select               */
-#define BR_MS_UPMB      0x000000c0      /* U.P.M.B Machine Select               */
-#define BR_V            0x00000001      /* Bank Valid                           */
-
-/*-----------------------------------------------------------------------
- * OR - Memory Controler: Option Register                               16-11
- */
-#define OR_AM_MSK       0xffff8000      /* Address Mask Mask                    */
-#define OR_ATM_MSK      0x00007000      /* Address Type Mask Mask               */
-#define OR_CSNT_SAM     0x00000800      /* Chip Select Negation Time/ Start     */
-                                        /* Address Multiplex                    */
-#define OR_ACS_MSK      0x00000600      /* Address to Chip Select Setup mask    */
-#define OR_ACS_DIV1     0x00000000      /* CS is output at the same time        */
-#define OR_ACS_DIV4     0x00000400      /* CS is output 1/4 a clock later       */
-#define OR_ACS_DIV2     0x00000600      /* CS is output 1/2 a clock later       */
-#define OR_G5LA         0x00000400      /* Output #GPL5 on #GPL_A5              */
-#define OR_G5LS         0x00000200      /* Drive #GPL high on falling edge of...*/
-#define OR_BI           0x00000100      /* Burst inhibit                        */
-#define OR_SCY_MSK      0x000000f0      /* Cycle Length in Clocks               */
-#define OR_SCY_0_CLK    0x00000000      /* 0 clock cycles wait states           */
-#define OR_SCY_1_CLK    0x00000010      /* 1 clock cycles wait states           */
-#define OR_SCY_2_CLK    0x00000020      /* 2 clock cycles wait states           */
-#define OR_SCY_3_CLK    0x00000030      /* 3 clock cycles wait states           */
-#define OR_SCY_4_CLK    0x00000040      /* 4 clock cycles wait states           */
-#define OR_SCY_5_CLK    0x00000050      /* 5 clock cycles wait states           */
-#define OR_SCY_6_CLK    0x00000060      /* 6 clock cycles wait states           */
-#define OR_SCY_7_CLK    0x00000070      /* 7 clock cycles wait states           */
-#define OR_SCY_8_CLK    0x00000080      /* 8 clock cycles wait states           */
-#define OR_SCY_9_CLK    0x00000090      /* 9 clock cycles wait states           */
-#define OR_SCY_10_CLK   0x000000a0      /* 10 clock cycles wait states          */
-#define OR_SCY_11_CLK   0x000000b0      /* 11 clock cycles wait states          */
-#define OR_SCY_12_CLK   0x000000c0      /* 12 clock cycles wait states          */
-#define OR_SCY_13_CLK   0x000000d0      /* 13 clock cycles wait states          */
-#define OR_SCY_14_CLK   0x000000e0      /* 14 clock cycles wait states          */
-#define OR_SCY_15_CLK   0x000000f0      /* 15 clock cycles wait states          */
-#define OR_SETA         0x00000008      /* External Transfer Acknowledge        */
-#define OR_TRLX         0x00000004      /* Timing Relaxed                       */
-#define OR_EHTR         0x00000002      /* Extended Hold Time on Read           */
-
-/* System Integration Timers.
-*/
-typedef struct  sys_int_timers {
-        ushort  sit_tbscr;
-        char    res0[0x02];
-        uint    sit_tbreff0;
-        uint    sit_tbreff1;
-        char    res1[0x14];
-        ushort  sit_rtcsc;
-        char    res2[0x02];
-        uint    sit_rtc;
-        uint    sit_rtsec;
-        uint    sit_rtcal;
-        char    res3[0x10];
-        ushort  sit_piscr;
-        char    res4[2];
-        uint    sit_pitc;
-        uint    sit_pitr;
-        char    res5[0x34];
-} sit8xx_t;
-
-#define TBSCR_TBIRQ_MASK        ((ushort)0xff00)
-#define TBSCR_REFA              ((ushort)0x0080)
-#define TBSCR_REFB              ((ushort)0x0040)
-#define TBSCR_REFAE             ((ushort)0x0008)
-#define TBSCR_REFBE             ((ushort)0x0004)
-#define TBSCR_TBF               ((ushort)0x0002)
-#define TBSCR_TBE               ((ushort)0x0001)
-
-#define RTCSC_RTCIRQ_MASK       ((ushort)0xff00)
-#define RTCSC_SEC               ((ushort)0x0080)
-#define RTCSC_ALR               ((ushort)0x0040)
-#define RTCSC_38K               ((ushort)0x0010)
-#define RTCSC_SIE               ((ushort)0x0008)
-#define RTCSC_ALE               ((ushort)0x0004)
-#define RTCSC_RTF               ((ushort)0x0002)
-#define RTCSC_RTE               ((ushort)0x0001)
-
-#define PISCR_PIRQ_MASK         ((ushort)0xff00)
-#define PISCR_PS                ((ushort)0x0080)
-#define PISCR_PIE               ((ushort)0x0004)
-#define PISCR_PTF               ((ushort)0x0002)
-#define PISCR_PTE               ((ushort)0x0001)
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-        uint    car_sccr;
-        uint    car_plprcr;
-        uint    car_rsr;
-        char    res[0x74];        /* Reserved area                  */
-} car8xx_t;
-
-/* System Integration Timers keys.
-*/
-typedef struct sitk {
-        uint    sitk_tbscrk;
-        uint    sitk_tbreff0k;
-        uint    sitk_tbreff1k;
-        uint    sitk_tbk;
-        char    res1[0x10];
-        uint    sitk_rtcsck;
-        uint    sitk_rtck;
-        uint    sitk_rtseck;
-        uint    sitk_rtcalk;
-        char    res2[0x10];
-        uint    sitk_piscrk;
-        uint    sitk_pitck;
-        char    res3[0x38];
-} sitk8xx_t;
-
-/* Clocks and reset keys.
-*/
-typedef struct cark {
-        uint    cark_sccrk;
-        uint    cark_plprcrk;
-        uint    cark_rsrk;
-        char    res[0x474];
-} cark8xx_t;
-
-/* The key to unlock registers maintained by keep-alive power.
-*/
-#define KAPWR_KEY       ((unsigned int)0x55ccaa33)
-
-/* Video interface.  MPC823 Only.
-*/
-typedef struct vid823 {
-        ushort  vid_vccr;
-        ushort  res1;
-        u_char  vid_vsr;
-        u_char  res2;
-        u_char  vid_vcmr;
-        u_char  res3;
-        uint    vid_vbcb;
-        uint    res4;
-        uint    vid_vfcr0;
-        uint    vid_vfaa0;
-        uint    vid_vfba0;
-        uint    vid_vfcr1;
-        uint    vid_vfaa1;
-        uint    vid_vfba1;
-        u_char  res5[0x18];
-} vid823_t;
-
-/* LCD interface.  823 Only.
-*/
-typedef struct lcd {
-        uint    lcd_lccr;
-        uint    lcd_lchcr;
-        uint    lcd_lcvcr;
-        char    res1[4];
-        uint    lcd_lcfaa;
-        uint    lcd_lcfba;
-        char    lcd_lcsr;
-        char    res2[0x7];
-} lcd823_t;
-
-/* I2C
-*/
-typedef struct i2c {
-        u_char  i2c_i2mod;
-        char    res1[3];
-        u_char  i2c_i2add;
-        char    res2[3];
-        u_char  i2c_i2brg;
-        char    res3[3];
-        u_char  i2c_i2com;
-        char    res4[3];
-        u_char  i2c_i2cer;
-        char    res5[3];
-        u_char  i2c_i2cmr;
-        char    res6[0x8b];
-} i2c8xx_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-        char    res1[4];
-        uint    sdma_sdar;
-        u_char  sdma_sdsr;
-        char    res3[3];
-        u_char  sdma_sdmr;
-        char    res4[3];
-        u_char  sdma_idsr1;
-        char    res5[3];
-        u_char  sdma_idmr1;
-        char    res6[3];
-        u_char  sdma_idsr2;
-        char    res7[3];
-        u_char  sdma_idmr2;
-        char    res8[0x13];
-} sdma8xx_t;
-
-/* Communication Processor Module Interrupt Controller.
-*/
-typedef struct cpm_ic {
-        ushort  cpic_civr;
-        char    res[0xe];
-        uint    cpic_cicr;
-        uint    cpic_cipr;
-        uint    cpic_cimr;
-        uint    cpic_cisr;
-} cpic8xx_t;
-
-/* Input/Output Port control/status registers.
-*/
-typedef struct io_port {
-        ushort  iop_padir;
-        ushort  iop_papar;
-        ushort  iop_paodr;
-        ushort  iop_padat;
-        char    res1[8];
-        ushort  iop_pcdir;
-        ushort  iop_pcpar;
-        ushort  iop_pcso;
-        ushort  iop_pcdat;
-        ushort  iop_pcint;
-        char    res2[6];
-        ushort  iop_pddir;
-        ushort  iop_pdpar;
-        char    res3[2];
-        ushort  iop_pddat;
-        uint    utmode;
-        char    res4[4];
-} iop8xx_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-        ushort  cpmt_tgcr;
-        char    res1[0xe];
-        ushort  cpmt_tmr1;
-        ushort  cpmt_tmr2;
-        ushort  cpmt_trr1;
-        ushort  cpmt_trr2;
-        ushort  cpmt_tcr1;
-        ushort  cpmt_tcr2;
-        ushort  cpmt_tcn1;
-        ushort  cpmt_tcn2;
-        ushort  cpmt_tmr3;
-        ushort  cpmt_tmr4;
-        ushort  cpmt_trr3;
-        ushort  cpmt_trr4;
-        ushort  cpmt_tcr3;
-        ushort  cpmt_tcr4;
-        ushort  cpmt_tcn3;
-        ushort  cpmt_tcn4;
-        ushort  cpmt_ter1;
-        ushort  cpmt_ter2;
-        ushort  cpmt_ter3;
-        ushort  cpmt_ter4;
-        char    res2[8];
-} cpmtimer8xx_t;
-
-/* Finally, the Communication Processor stuff.....
-*/
-typedef struct scc {            /* Serial communication channels */
-        uint    scc_gsmrl;
-        uint    scc_gsmrh;
-        ushort  scc_psmr;
-        char    res1[2];
-        ushort  scc_todr;
-        ushort  scc_dsr;
-        ushort  scc_scce;
-        char    res2[2];
-        ushort  scc_sccm;
-        char    res3;
-        u_char  scc_sccs;
-        char    res4[8];
-} scc_t;
-
-typedef struct smc {            /* Serial management channels */
-        char    res1[2];
-        ushort  smc_smcmr;
-        char    res2[2];
-        u_char  smc_smce;
-        char    res3[3];
-        u_char  smc_smcm;
-        char    res4[5];
-} smc_t;
-
-/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
- * it fits within the address space.
- */
-
-typedef struct fec {
-        uint    fec_addr_low;           /* lower 32 bits of station address     */
-        ushort  fec_addr_high;          /* upper 16 bits of station address     */
-        ushort  res1;                   /* reserved                             */
-        uint    fec_hash_table_high;    /* upper 32-bits of hash table          */
-        uint    fec_hash_table_low;     /* lower 32-bits of hash table          */
-        uint    fec_r_des_start;        /* beginning of Rx descriptor ring      */
-        uint    fec_x_des_start;        /* beginning of Tx descriptor ring      */
-        uint    fec_r_buff_size;        /* Rx buffer size                       */
-        uint    res2[9];                /* reserved                             */
-        uint    fec_ecntrl;             /* ethernet control register            */
-        uint    fec_ievent;             /* interrupt event register             */
-        uint    fec_imask;              /* interrupt mask register              */
-        uint    fec_ivec;               /* interrupt level and vector status    */
-        uint    fec_r_des_active;       /* Rx ring updated flag                 */
-        uint    fec_x_des_active;       /* Tx ring updated flag                 */
-        uint    res3[10];               /* reserved                             */
-        uint    fec_mii_data;           /* MII data register                    */
-        uint    fec_mii_speed;          /* MII speed control register           */
-        uint    res4[17];               /* reserved                             */
-        uint    fec_r_bound;            /* end of RAM (read-only)               */
-        uint    fec_r_fstart;           /* Rx FIFO start address                */
-        uint    res5[6];                /* reserved                             */
-        uint    fec_x_fstart;           /* Tx FIFO start address                */
-        uint    res6[17];               /* reserved                             */
-        uint    fec_fun_code;           /* fec SDMA function code               */
-        uint    res7[3];                /* reserved                             */
-        uint    fec_r_cntrl;            /* Rx control register                  */
-        uint    fec_r_hash;             /* Rx hash register                     */
-        uint    res8[14];               /* reserved                             */
-        uint    fec_x_cntrl;            /* Tx control register                  */
-        uint    res9[0x1e];             /* reserved                             */
-} fec_t;
-
-/* The FEC and LCD color map share the same address space....
- * I guess we will never see an 823T :-).
- */
-union fec_lcd {
-        fec_t   fl_un_fec;
-        u_char  fl_un_cmap[0x200];
-};
-
-typedef struct comm_proc {
-        /* General control and status registers.
-        */
-        ushort  cp_cpcr;
-        u_char  res1[2];
-        ushort  cp_rccr;
-        u_char  res2;
-        u_char  cp_rmds;
-        u_char  res3[4];
-        ushort  cp_cpmcr1;
-        ushort  cp_cpmcr2;
-        ushort  cp_cpmcr3;
-        ushort  cp_cpmcr4;
-        u_char  res4[2];
-        ushort  cp_rter;
-        u_char  res5[2];
-        ushort  cp_rtmr;
-        u_char  res6[0x14];
-
-        /* Baud rate generators.
-        */
-        uint    cp_brgc1;
-        uint    cp_brgc2;
-        uint    cp_brgc3;
-        uint    cp_brgc4;
-
-        /* Serial Communication Channels.
-        */
-        scc_t   cp_scc[4];
-
-        /* Serial Management Channels.
-        */
-        smc_t   cp_smc[2];
-
-        /* Serial Peripheral Interface.
-        */
-        ushort  cp_spmode;
-        u_char  res7[4];
-        u_char  cp_spie;
-        u_char  res8[3];
-        u_char  cp_spim;
-        u_char  res9[2];
-        u_char  cp_spcom;
-        u_char  res10[2];
-
-        /* Parallel Interface Port.
-        */
-        u_char  res11[2];
-        ushort  cp_pipc;
-        u_char  res12[2];
-        ushort  cp_ptpr;
-        uint    cp_pbdir;
-        uint    cp_pbpar;
-        u_char  res13[2];
-        ushort  cp_pbodr;
-        uint    cp_pbdat;
-
-        /* Port E - MPC87x/88x only.
-         */
-        uint    cp_pedir;
-        uint    cp_pepar;
-        uint    cp_peso;
-        uint    cp_peodr;
-        uint    cp_pedat;
-
-        /* Communications Processor Timing Register -
-           Contains RMII Timing for the FECs on MPC87x/88x only.
-        */
-        uint    cp_cptr;
-
-        /* Serial Interface and Time Slot Assignment.
-        */
-        uint    cp_simode;
-        u_char  cp_sigmr;
-        u_char  res15;
-        u_char  cp_sistr;
-        u_char  cp_sicmr;
-        u_char  res16[4];
-        uint    cp_sicr;
-        uint    cp_sirp;
-        u_char  res17[0xc];
-
-        /* 256 bytes of MPC823 video controller RAM array.
-        */
-        u_char  cp_vcram[0x100];
-        u_char  cp_siram[0x200];
-
-        /* The fast ethernet controller is not really part of the CPM,
-         * but it resides in the address space.
-         * The LCD color map is also here.
-         */
-        union   fec_lcd fl_un;
-#define cp_fec          fl_un.fl_un_fec
-#define lcd_cmap        fl_un.fl_un_cmap
-        char    res18[0xE00];
-
-        /* The DUET family has a second FEC here */
-        fec_t   cp_fec2;
-#define cp_fec1 cp_fec  /* consistency macro */
-
-        /* Dual Ported RAM follows.
-         * There are many different formats for this memory area
-         * depending upon the devices used and options chosen.
-         * Some processors don't have all of it populated.
-         */
-        u_char  cp_dpmem[0x1C00];       /* BD / Data / ucode */
-        u_char  cp_dparam[0x400];       /* Parameter RAM */
-} cpm8xx_t;
-
-/* Internal memory map.
-*/
-typedef struct immap {
-        sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
-        pcmconf8xx_t    im_pcmcia;      /* PCMCIA Configuration */
-        memctl8xx_t     im_memctl;      /* Memory Controller */
-        sit8xx_t        im_sit;         /* System integration timers */
-        car8xx_t        im_clkrst;      /* Clocks and reset */
-        sitk8xx_t       im_sitk;        /* Sys int timer keys */
-        cark8xx_t       im_clkrstk;     /* Clocks and reset keys */
-        vid823_t        im_vid;         /* Video (823 only) */
-        lcd823_t        im_lcd;         /* LCD (823 only) */
-        i2c8xx_t        im_i2c;         /* I2C control/status */
-        sdma8xx_t       im_sdma;        /* SDMA control/status */
-        cpic8xx_t       im_cpic;        /* CPM Interrupt Controller */
-        iop8xx_t        im_ioport;      /* IO Port control/status */
-        cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
-        cpm8xx_t        im_cpm;         /* Communication processor */
-} immap_t;
-
-#endif /* __IMMAP_8XX__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h
deleted file mode 100644
index 1fe0b87859b0..000000000000
--- a/include/asm-ppc/amigayle.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/amigayle.h>
diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h
deleted file mode 100644
index 3f65f63f508f..000000000000
--- a/include/asm-ppc/amipcmcia.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/amipcmcia.h>
diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h
deleted file mode 100644
index f6ed77aee328..000000000000
--- a/include/asm-ppc/bootinfo.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Non-machine dependent bootinfo structure.  Basic idea
- * borrowed from the m68k.
- *
- * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
- */
-
-#ifdef __KERNEL__
-#ifndef _PPC_BOOTINFO_H
-#define _PPC_BOOTINFO_H
-
-#include <asm/page.h>
-
-struct bi_record {
-        unsigned long tag;              /* tag ID */
-        unsigned long size;             /* size of record (in bytes) */
-        unsigned long data[0];          /* data */
-};
-
-#define BI_FIRST                0x1010  /* first record - marker */
-#define BI_LAST                 0x1011  /* last record - marker */
-#define BI_CMD_LINE             0x1012
-#define BI_BOOTLOADER_ID        0x1013
-#define BI_INITRD               0x1014
-#define BI_SYSMAP               0x1015
-#define BI_MACHTYPE             0x1016
-#define BI_MEMSIZE              0x1017
-#define BI_BOARD_INFO           0x1018
-
-extern struct bi_record *find_bootinfo(void);
-extern void bootinfo_init(struct bi_record *rec);
-extern void bootinfo_append(unsigned long tag, unsigned long size, void * data);
-extern void parse_bootinfo(struct bi_record *rec);
-extern unsigned long boot_mem_size;
-
-static inline struct bi_record *
-bootinfo_addr(unsigned long offset)
-{
-
-        return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
-                                          (1 << 20));
-}
-
-
-#endif /* _PPC_BOOTINFO_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h
deleted file mode 100644
index b0c51b45d7a2..000000000000
--- a/include/asm-ppc/bootx.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file describes the structure passed from the BootX application
- * (for MacOS) when it is used to boot Linux.
- *
- * Written by Benjamin Herrenschmidt.
- */
-
-
-#ifndef __ASM_BOOTX_H__
-#define __ASM_BOOTX_H__
-
-#ifdef macintosh
-#include <Types.h>
-#include "linux_type_defs.h"
-#endif
-
-#ifdef macintosh
-/* All this requires PowerPC alignment */
-#pragma options align=power
-#endif
-
-/* On kernel entry:
- *
- * r3 = 0x426f6f58    ('BooX')
- * r4 = pointer to boot_infos
- * r5 = NULL
- *
- * Data and instruction translation disabled, interrupts
- * disabled, kernel loaded at physical 0x00000000 on PCI
- * machines (will be different on NuBus).
- */
-
-#define BOOT_INFO_VERSION               5
-#define BOOT_INFO_COMPATIBLE_VERSION    1
-
-/* Bit in the architecture flag mask. More to be defined in
-   future versions. Note that either BOOT_ARCH_PCI or
-   BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
-   set additionally when BOOT_ARCH_NUBUS is set.
- */
-#define BOOT_ARCH_PCI                   0x00000001UL
-#define BOOT_ARCH_NUBUS                 0x00000002UL
-#define BOOT_ARCH_NUBUS_PDM             0x00000010UL
-#define BOOT_ARCH_NUBUS_PERFORMA        0x00000020UL
-#define BOOT_ARCH_NUBUS_POWERBOOK       0x00000040UL
-
-/*  Maximum number of ranges in phys memory map */
-#define MAX_MEM_MAP_SIZE                                26
-
-/* This is the format of an element in the physical memory map. Note that
-   the map is optional and current BootX will only build it for pre-PCI
-   machines */
-typedef struct boot_info_map_entry
-{
-    __u32       physAddr;                /* Physical starting address */
-    __u32       size;                    /* Size in bytes */
-} boot_info_map_entry_t;
-
-
-/* Here are the boot informations that are passed to the bootstrap
- * Note that the kernel arguments and the device tree are appended
- * at the end of this structure. */
-typedef struct boot_infos
-{
-    /* Version of this structure */
-    __u32       version;
-    /* backward compatible down to version: */
-    __u32       compatible_version;
-
-    /* NEW (vers. 2) this holds the current _logical_ base addr of
-       the frame buffer (for use by early boot message) */
-    __u8*       logicalDisplayBase;
-
-    /* NEW (vers. 4) Apple's machine identification */
-    __u32       machineID;
-
-    /* NEW (vers. 4) Detected hw architecture */
-    __u32       architecture;
-
-    /* The device tree (internal addresses relative to the beginning of the tree,
-     * device tree offset relative to the beginning of this structure).
-     * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
-     * field is 0.
-     */
-    __u32       deviceTreeOffset;        /* Device tree offset */
-    __u32       deviceTreeSize;          /* Size of the device tree */
-
-    /* Some infos about the current MacOS display */
-    __u32       dispDeviceRect[4];       /* left,top,right,bottom */
-    __u32       dispDeviceDepth;         /* (8, 16 or 32) */
-    __u8*       dispDeviceBase;          /* base address (physical) */
-    __u32       dispDeviceRowBytes;      /* rowbytes (in bytes) */
-    __u32       dispDeviceColorsOffset;  /* Colormap (8 bits only) or 0 (*) */
-    /* Optional offset in the registry to the current
-     * MacOS display. (Can be 0 when not detected) */
-     __u32      dispDeviceRegEntryOffset;
-
-    /* Optional pointer to boot ramdisk (offset from this structure) */
-    __u32       ramDisk;
-    __u32       ramDiskSize;             /* size of ramdisk image */
-
-    /* Kernel command line arguments (offset from this structure) */
-    __u32       kernelParamsOffset;
-
-    /* ALL BELOW NEW (vers. 4) */
-
-    /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
-       (non-PCI) only. On PCI, memory is contiguous and it's size is in the
-       device-tree. */
-    boot_info_map_entry_t
-                physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
-    __u32       physMemoryMapSize;               /* How many entries in map */
-
-
-    /* The framebuffer size (optional, currently 0) */
-    __u32       frameBufferSize;         /* Represents a max size, can be 0. */
-
-    /* NEW (vers. 5) */
-
-    /* Total params size (args + colormap + device tree + ramdisk) */
-    __u32       totalParamsSize;
-
-} boot_infos_t;
-
-/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented
- * by 3 short words containing a 16 bits (unsigned) color component.
- * Later versions may contain the gamma table for direct-color devices here.
- */
-#define BOOTX_COLORTABLE_SIZE    (256UL*3UL*2UL)
-
-#ifdef macintosh
-#pragma options align=reset
-#endif
-
-#endif
diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h
deleted file mode 100644
index ed3630251b3b..000000000000
--- a/include/asm-ppc/btext.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Definitions for using the procedures in btext.c.
- *
- * Benjamin Herrenschmidt <benh@kernel.crashing.org>
- */
-#ifndef __PPC_BTEXT_H
-#define __PPC_BTEXT_H
-#ifdef __KERNEL__
-
-#include <asm/bootx.h>
-
-extern void btext_clearscreen(void);
-extern void btext_flushscreen(void);
-
-extern unsigned long disp_BAT[2];
-
-extern boot_infos_t disp_bi;
-extern int boot_text_mapped;
-
-extern void btext_init(boot_infos_t *bi);
-extern void btext_welcome(void);
-extern void btext_prepare_BAT(void);
-extern void btext_setup_display(int width, int height, int depth, int pitch,
-                                unsigned long address);
-extern void map_boot_text(void);
-extern void btext_update_display(unsigned long phys, int width, int height,
-                                 int depth, int pitch);
-
-extern void btext_drawchar(char c);
-extern void btext_drawstring(const char *str);
-extern void btext_drawhex(unsigned long v);
-
-#endif /* __KERNEL__ */
-#endif /* __PPC_BTEXT_H */
diff --git a/include/asm-ppc/cpm1.h b/include/asm-ppc/cpm1.h
deleted file mode 100644
index 03035acd85c6..000000000000
--- a/include/asm-ppc/cpm1.h
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * MPC8xx Communication Processor Module.
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels.  Some CPM control and status is available
- * throught the MPC8xx internal memory map.  See immap.h for details.
- * This file only contains what I need for the moment, not the total
- * CPM capabilities.  I (or someone else) will add definitions as they
- * are needed.  -- Dan
- *
- * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
- * bytes of the DP RAM and relocates the I2C parameter area to the
- * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
- * or other use.
- */
-#ifndef __CPM1__
-#define __CPM1__
-
-#include <asm/8xx_immap.h>
-#include <asm/ptrace.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST      ((ushort)0x8000)
-#define CPM_CR_OPCODE   ((ushort)0x0f00)
-#define CPM_CR_CHAN     ((ushort)0x00f0)
-#define CPM_CR_FLG      ((ushort)0x0001)
-
-/* Some commands (there are more...later)
-*/
-#define CPM_CR_INIT_TRX         ((ushort)0x0000)
-#define CPM_CR_INIT_RX          ((ushort)0x0001)
-#define CPM_CR_INIT_TX          ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
-#define CPM_CR_STOP_TX          ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
-#define CPM_CR_RESTART_TX       ((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD      ((ushort)0x0007)
-#define CPM_CR_SET_GADDR        ((ushort)0x0008)
-#define CPM_CR_SET_TIMER        CPM_CR_SET_GADDR
-
-/* Channel numbers.
-*/
-#define CPM_CR_CH_SCC1          ((ushort)0x0000)
-#define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
-#define CPM_CR_CH_SCC2          ((ushort)0x0004)
-#define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
-#define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
-#define CPM_CR_CH_SCC3          ((ushort)0x0008)
-#define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
-#define CPM_CR_CH_SCC4          ((ushort)0x000c)
-#define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
-
-#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
-
-/* The dual ported RAM is multi-functional.  Some areas can be (and are
- * being) used for microcode.  There is an area that can only be used
- * as data ram for buffer descriptors, which is all we use right now.
- * Currently the first 512 and last 256 bytes are used for microcode.
- */
-#define CPM_DATAONLY_BASE       ((uint)0x0800)
-#define CPM_DATAONLY_SIZE       ((uint)0x0700)
-#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
-extern unsigned long cpm_dpalloc(uint size, uint align);
-extern int cpm_dpfree(unsigned long offset);
-extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
-extern void cpm_dpdump(void);
-extern void *cpm_dpram_addr(unsigned long offset);
-extern uint cpm_dpram_phys(u8 *addr);
-extern void cpm_setbrg(uint brg, uint rate);
-
-extern void cpm_load_patch(volatile immap_t *immr);
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-        ushort  cbd_sc;         /* Status and Control */
-        ushort  cbd_datlen;     /* Data length in buffer */
-        uint    cbd_bufaddr;    /* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
-#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
-#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
-#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
-#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
-#define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
-#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
-#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
-#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
-#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
-#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
-#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
-#define BD_SC_NAK       ((ushort)0x0004)        /* NAK - did not respond */
-#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
-#define BD_SC_UN        ((ushort)0x0002)        /* Underrun */
-#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
-#define BD_SC_CL        ((ushort)0x0001)        /* Collision */
-
-/* Parameter RAM offsets.
-*/
-#define PROFF_SCC1      ((uint)0x0000)
-#define PROFF_IIC       ((uint)0x0080)
-#define PROFF_SCC2      ((uint)0x0100)
-#define PROFF_SPI       ((uint)0x0180)
-#define PROFF_SCC3      ((uint)0x0200)
-#define PROFF_SMC1      ((uint)0x0280)
-#define PROFF_SCC4      ((uint)0x0300)
-#define PROFF_SMC2      ((uint)0x0380)
-
-/* Define enough so I can at least use the serial port as a UART.
- * The MBX uses SMC1 as the host serial port.
- */
-typedef struct smc_uart {
-        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
-        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
-        u_char  smc_rfcr;       /* Rx function code */
-        u_char  smc_tfcr;       /* Tx function code */
-        ushort  smc_mrblr;      /* Max receive buffer length */
-        uint    smc_rstate;     /* Internal */
-        uint    smc_idp;        /* Internal */
-        ushort  smc_rbptr;      /* Internal */
-        ushort  smc_ibc;        /* Internal */
-        uint    smc_rxtmp;      /* Internal */
-        uint    smc_tstate;     /* Internal */
-        uint    smc_tdp;        /* Internal */
-        ushort  smc_tbptr;      /* Internal */
-        ushort  smc_tbc;        /* Internal */
-        uint    smc_txtmp;      /* Internal */
-        ushort  smc_maxidl;     /* Maximum idle characters */
-        ushort  smc_tmpidl;     /* Temporary idle counter */
-        ushort  smc_brklen;     /* Last received break length */
-        ushort  smc_brkec;      /* rcv'd break condition counter */
-        ushort  smc_brkcr;      /* xmt break count register */
-        ushort  smc_rmask;      /* Temporary bit mask */
-        char    res1[8];        /* Reserved */
-        ushort  smc_rpbase;     /* Relocation pointer */
-} smc_uart_t;
-
-/* Function code bits.
-*/
-#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
-
-/* SMC uart mode register.
-*/
-#define SMCMR_REN       ((ushort)0x0001)
-#define SMCMR_TEN       ((ushort)0x0002)
-#define SMCMR_DM        ((ushort)0x000c)
-#define SMCMR_SM_GCI    ((ushort)0x0000)
-#define SMCMR_SM_UART   ((ushort)0x0020)
-#define SMCMR_SM_TRANS  ((ushort)0x0030)
-#define SMCMR_SM_MASK   ((ushort)0x0030)
-#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
-#define SMCMR_REVD      SMCMR_PM_EVEN
-#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
-#define SMCMR_BS        SMCMR_PEN
-#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
-#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
-#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC2 as Centronics parallel printer.  It is half duplex, in that
- * it can only receive or transmit.  The parameter ram values for
- * each direction are either unique or properly overlap, so we can
- * include them in one structure.
- */
-typedef struct smc_centronics {
-        ushort  scent_rbase;
-        ushort  scent_tbase;
-        u_char  scent_cfcr;
-        u_char  scent_smask;
-        ushort  scent_mrblr;
-        uint    scent_rstate;
-        uint    scent_r_ptr;
-        ushort  scent_rbptr;
-        ushort  scent_r_cnt;
-        uint    scent_rtemp;
-        uint    scent_tstate;
-        uint    scent_t_ptr;
-        ushort  scent_tbptr;
-        ushort  scent_t_cnt;
-        uint    scent_ttemp;
-        ushort  scent_max_sl;
-        ushort  scent_sl_cnt;
-        ushort  scent_character1;
-        ushort  scent_character2;
-        ushort  scent_character3;
-        ushort  scent_character4;
-        ushort  scent_character5;
-        ushort  scent_character6;
-        ushort  scent_character7;
-        ushort  scent_character8;
-        ushort  scent_rccm;
-        ushort  scent_rccr;
-} smc_cent_t;
-
-/* Centronics Status Mask Register.
-*/
-#define SMC_CENT_F      ((u_char)0x08)
-#define SMC_CENT_PE     ((u_char)0x04)
-#define SMC_CENT_S      ((u_char)0x02)
-
-/* SMC Event and Mask register.
-*/
-#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
-#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
-#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
-#define SMCM_BSY        ((unsigned char)0x04)
-#define SMCM_TX         ((unsigned char)0x02)
-#define SMCM_RX         ((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST             ((uint)0x00020000)
-#define CPM_BRG_EN              ((uint)0x00010000)
-#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
-#define CPM_BRG_ATB             ((uint)0x00002000)
-#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
-#define CPM_BRG_DIV16           ((uint)0x00000001)
-
-/* SI Clock Route Register
-*/
-#define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
-#define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
-#define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
-#define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
-#define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
-#define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
-#define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
-#define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP           ((uint)0x00040000)
-#define SCC_GSMRH_GDE           ((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
-#define SCC_GSMRH_REVD          ((uint)0x00002000)
-#define SCC_GSMRH_TRX           ((uint)0x00001000)
-#define SCC_GSMRH_TTX           ((uint)0x00000800)
-#define SCC_GSMRH_CDP           ((uint)0x00000400)
-#define SCC_GSMRH_CTSP          ((uint)0x00000200)
-#define SCC_GSMRH_CDS           ((uint)0x00000100)
-#define SCC_GSMRH_CTSS          ((uint)0x00000080)
-#define SCC_GSMRH_TFL           ((uint)0x00000040)
-#define SCC_GSMRH_RFW           ((uint)0x00000020)
-#define SCC_GSMRH_TXSY          ((uint)0x00000010)
-#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
-#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
-#define SCC_GSMRH_RTSM          ((uint)0x00000002)
-#define SCC_GSMRH_RSYN          ((uint)0x00000001)
-
-#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
-#define SCC_GSMRL_TCI           ((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
-#define SCC_GSMRL_RINV          ((uint)0x02000000)
-#define SCC_GSMRL_TINV          ((uint)0x01000000)
-#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
-#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
-#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
-#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
-#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
-#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
-#define SCC_GSMRL_TEND          ((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
-#define SCC_GSMRL_ENR           ((uint)0x00000020)
-#define SCC_GSMRL_ENT           ((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
-#define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
-#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
-
-#define SCC_TODR_TOD            ((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define SCCM_TXE        ((unsigned char)0x10)
-#define SCCM_BSY        ((unsigned char)0x04)
-#define SCCM_TX         ((unsigned char)0x02)
-#define SCCM_RX         ((unsigned char)0x01)
-
-typedef struct scc_param {
-        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
-        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
-        u_char  scc_rfcr;       /* Rx function code */
-        u_char  scc_tfcr;       /* Tx function code */
-        ushort  scc_mrblr;      /* Max receive buffer length */
-        uint    scc_rstate;     /* Internal */
-        uint    scc_idp;        /* Internal */
-        ushort  scc_rbptr;      /* Internal */
-        ushort  scc_ibc;        /* Internal */
-        uint    scc_rxtmp;      /* Internal */
-        uint    scc_tstate;     /* Internal */
-        uint    scc_tdp;        /* Internal */
-        ushort  scc_tbptr;      /* Internal */
-        ushort  scc_tbc;        /* Internal */
-        uint    scc_txtmp;      /* Internal */
-        uint    scc_rcrc;       /* Internal */
-        uint    scc_tcrc;       /* Internal */
-} sccp_t;
-
-/* Function code bits.
-*/
-#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
-
-/* CPM Ethernet through SCCx.
- */
-typedef struct scc_enet {
-        sccp_t  sen_genscc;
-        uint    sen_cpres;      /* Preset CRC */
-        uint    sen_cmask;      /* Constant mask for CRC */
-        uint    sen_crcec;      /* CRC Error counter */
-        uint    sen_alec;       /* alignment error counter */
-        uint    sen_disfc;      /* discard frame counter */
-        ushort  sen_pads;       /* Tx short frame pad character */
-        ushort  sen_retlim;     /* Retry limit threshold */
-        ushort  sen_retcnt;     /* Retry limit counter */
-        ushort  sen_maxflr;     /* maximum frame length register */
-        ushort  sen_minflr;     /* minimum frame length register */
-        ushort  sen_maxd1;      /* maximum DMA1 length */
-        ushort  sen_maxd2;      /* maximum DMA2 length */
-        ushort  sen_maxd;       /* Rx max DMA */
-        ushort  sen_dmacnt;     /* Rx DMA counter */
-        ushort  sen_maxb;       /* Max BD byte count */
-        ushort  sen_gaddr1;     /* Group address filter */
-        ushort  sen_gaddr2;
-        ushort  sen_gaddr3;
-        ushort  sen_gaddr4;
-        uint    sen_tbuf0data0; /* Save area 0 - current frame */
-        uint    sen_tbuf0data1; /* Save area 1 - current frame */
-        uint    sen_tbuf0rba;   /* Internal */
-        uint    sen_tbuf0crc;   /* Internal */
-        ushort  sen_tbuf0bcnt;  /* Internal */
-        ushort  sen_paddrh;     /* physical address (MSB) */
-        ushort  sen_paddrm;
-        ushort  sen_paddrl;     /* physical address (LSB) */
-        ushort  sen_pper;       /* persistence */
-        ushort  sen_rfbdptr;    /* Rx first BD pointer */
-        ushort  sen_tfbdptr;    /* Tx first BD pointer */
-        ushort  sen_tlbdptr;    /* Tx last BD pointer */
-        uint    sen_tbuf1data0; /* Save area 0 - current frame */
-        uint    sen_tbuf1data1; /* Save area 1 - current frame */
-        uint    sen_tbuf1rba;   /* Internal */
-        uint    sen_tbuf1crc;   /* Internal */
-        ushort  sen_tbuf1bcnt;  /* Internal */
-        ushort  sen_txlen;      /* Tx Frame length counter */
-        ushort  sen_iaddr1;     /* Individual address filter */
-        ushort  sen_iaddr2;
-        ushort  sen_iaddr3;
-        ushort  sen_iaddr4;
-        ushort  sen_boffcnt;    /* Backoff counter */
-
-        /* NOTE: Some versions of the manual have the following items
-         * incorrectly documented.  Below is the proper order.
-         */
-        ushort  sen_taddrh;     /* temp address (MSB) */
-        ushort  sen_taddrm;
-        ushort  sen_taddrl;     /* temp address (LSB) */
-} scc_enet_t;
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
-#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
-#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
-#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
-#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
-#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
-
-/* SCC Mode Register (PMSR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
-#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
-#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
-#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
-#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
-#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
-#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
-#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
-#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
-#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
-#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
-#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
-#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
-*/
-#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
-#define BD_ENET_RX_WRAP         ((ushort)0x2000)
-#define BD_ENET_RX_INTR         ((ushort)0x1000)
-#define BD_ENET_RX_LAST         ((ushort)0x0800)
-#define BD_ENET_RX_FIRST        ((ushort)0x0400)
-#define BD_ENET_RX_MISS         ((ushort)0x0100)
-#define BD_ENET_RX_LG           ((ushort)0x0020)
-#define BD_ENET_RX_NO           ((ushort)0x0010)
-#define BD_ENET_RX_SH           ((ushort)0x0008)
-#define BD_ENET_RX_CR           ((ushort)0x0004)
-#define BD_ENET_RX_OV           ((ushort)0x0002)
-#define BD_ENET_RX_CL           ((ushort)0x0001)
-#define BD_ENET_RX_BC           ((ushort)0x0080)        /* DA is Broadcast */
-#define BD_ENET_RX_MC           ((ushort)0x0040)        /* DA is Multicast */
-#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
-*/
-#define BD_ENET_TX_READY        ((ushort)0x8000)
-#define BD_ENET_TX_PAD          ((ushort)0x4000)
-#define BD_ENET_TX_WRAP         ((ushort)0x2000)
-#define BD_ENET_TX_INTR         ((ushort)0x1000)
-#define BD_ENET_TX_LAST         ((ushort)0x0800)
-#define BD_ENET_TX_TC           ((ushort)0x0400)
-#define BD_ENET_TX_DEF          ((ushort)0x0200)
-#define BD_ENET_TX_HB           ((ushort)0x0100)
-#define BD_ENET_TX_LC           ((ushort)0x0080)
-#define BD_ENET_TX_RL           ((ushort)0x0040)
-#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
-#define BD_ENET_TX_UN           ((ushort)0x0002)
-#define BD_ENET_TX_CSL          ((ushort)0x0001)
-#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-        sccp_t  scc_genscc;
-        char    res1[8];        /* Reserved */
-        ushort  scc_maxidl;     /* Maximum idle chars */
-        ushort  scc_idlc;       /* temp idle counter */
-        ushort  scc_brkcr;      /* Break count register */
-        ushort  scc_parec;      /* receive parity error counter */
-        ushort  scc_frmec;      /* receive framing error counter */
-        ushort  scc_nosec;      /* receive noise counter */
-        ushort  scc_brkec;      /* receive break condition counter */
-        ushort  scc_brkln;      /* last received break length */
-        ushort  scc_uaddr1;     /* UART address character 1 */
-        ushort  scc_uaddr2;     /* UART address character 2 */
-        ushort  scc_rtemp;      /* Temp storage */
-        ushort  scc_toseq;      /* Transmit out of sequence char */
-        ushort  scc_char1;      /* control character 1 */
-        ushort  scc_char2;      /* control character 2 */
-        ushort  scc_char3;      /* control character 3 */
-        ushort  scc_char4;      /* control character 4 */
-        ushort  scc_char5;      /* control character 5 */
-        ushort  scc_char6;      /* control character 6 */
-        ushort  scc_char7;      /* control character 7 */
-        ushort  scc_char8;      /* control character 8 */
-        ushort  scc_rccm;       /* receive control character mask */
-        ushort  scc_rccr;       /* receive control character register */
-        ushort  scc_rlbc;       /* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR           ((ushort)0x1000)
-#define UART_SCCM_GLT           ((ushort)0x0800)
-#define UART_SCCM_AB            ((ushort)0x0200)
-#define UART_SCCM_IDL           ((ushort)0x0100)
-#define UART_SCCM_GRA           ((ushort)0x0080)
-#define UART_SCCM_BRKE          ((ushort)0x0040)
-#define UART_SCCM_BRKS          ((ushort)0x0020)
-#define UART_SCCM_CCR           ((ushort)0x0008)
-#define UART_SCCM_BSY           ((ushort)0x0004)
-#define UART_SCCM_TX            ((ushort)0x0002)
-#define UART_SCCM_RX            ((ushort)0x0001)
-
-/* The SCC PMSR when used as a UART.
-*/
-#define SCU_PSMR_FLC            ((ushort)0x8000)
-#define SCU_PSMR_SL             ((ushort)0x4000)
-#define SCU_PSMR_CL             ((ushort)0x3000)
-#define SCU_PSMR_UM             ((ushort)0x0c00)
-#define SCU_PSMR_FRZ            ((ushort)0x0200)
-#define SCU_PSMR_RZS            ((ushort)0x0100)
-#define SCU_PSMR_SYN            ((ushort)0x0080)
-#define SCU_PSMR_DRT            ((ushort)0x0040)
-#define SCU_PSMR_PEN            ((ushort)0x0010)
-#define SCU_PSMR_RPM            ((ushort)0x000c)
-#define SCU_PSMR_REVP           ((ushort)0x0008)
-#define SCU_PSMR_TPM            ((ushort)0x0003)
-#define SCU_PSMR_TEVP           ((ushort)0x0002)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-        sccp_t  st_genscc;
-        uint    st_cpres;       /* Preset CRC */
-        uint    st_cmask;       /* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST          ((ushort)0x0800)
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
-        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
-        u_char  iic_rfcr;       /* Rx function code */
-        u_char  iic_tfcr;       /* Tx function code */
-        ushort  iic_mrblr;      /* Max receive buffer length */
-        uint    iic_rstate;     /* Internal */
-        uint    iic_rdp;        /* Internal */
-        ushort  iic_rbptr;      /* Internal */
-        ushort  iic_rbc;        /* Internal */
-        uint    iic_rxtmp;      /* Internal */
-        uint    iic_tstate;     /* Internal */
-        uint    iic_tdp;        /* Internal */
-        ushort  iic_tbptr;      /* Internal */
-        ushort  iic_tbc;        /* Internal */
-        uint    iic_txtmp;      /* Internal */
-        char    res1[4];        /* Reserved */
-        ushort  iic_rpbase;     /* Relocation pointer */
-        char    res2[2];        /* Reserved */
-} iic_t;
-
-#define BD_IIC_START            ((ushort)0x0400)
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
-        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
-        u_char  spi_rfcr;       /* Rx function code */
-        u_char  spi_tfcr;       /* Tx function code */
-        ushort  spi_mrblr;      /* Max receive buffer length */
-        uint    spi_rstate;     /* Internal */
-        uint    spi_rdp;        /* Internal */
-        ushort  spi_rbptr;      /* Internal */
-        ushort  spi_rbc;        /* Internal */
-        uint    spi_rxtmp;      /* Internal */
-        uint    spi_tstate;     /* Internal */
-        uint    spi_tdp;        /* Internal */
-        ushort  spi_tbptr;      /* Internal */
-        ushort  spi_tbc;        /* Internal */
-        uint    spi_txtmp;      /* Internal */
-        uint    spi_res;
-        ushort  spi_rpbase;     /* Relocation pointer */
-        ushort  spi_res2;
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
-#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
-#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
-#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
-#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
-#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
-#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
-#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
-#define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
-#define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
-#define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
-#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
-
-/* SPIE fields */
-#define SPIE_MME        0x20
-#define SPIE_TXE        0x10
-#define SPIE_BSY        0x04
-#define SPIE_TXB        0x02
-#define SPIE_RXB        0x01
-
-/*
- * RISC Controller Configuration Register definitons
- */
-#define RCCR_TIME       0x8000                  /* RISC Timer Enable */
-#define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
-#define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
-
-/* RISC Timer Parameter RAM offset */
-#define PROFF_RTMR      ((uint)0x01B0)
-
-typedef struct risc_timer_pram {
-        unsigned short  tm_base;        /* RISC Timer Table Base Address */
-        unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
-        unsigned short  r_tmr;          /* RISC Timer Mode Register */
-        unsigned short  r_tmv;          /* RISC Timer Valid Register */
-        unsigned long   tm_cmd;         /* RISC Timer Command Register */
-        unsigned long   tm_cnt;         /* RISC Timer Internal Count */
-} rt_pram_t;
-
-/* Bits in RISC Timer Command Register */
-#define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
-#define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
-#define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
-#define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
-#define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
-
-/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
- * channels or devices.  All of these are presented to the PPC core
- * as a single interrupt.  The CPM interrupt handler dispatches its
- * own handlers, in a similar fashion to the PPC core handler.  We
- * use the table as defined in the manuals (i.e. no special high
- * priority and SCC1 == SCCa, etc...).
- */
-#define CPMVEC_NR               32
-#define CPMVEC_PIO_PC15         ((ushort)0x1f)
-#define CPMVEC_SCC1             ((ushort)0x1e)
-#define CPMVEC_SCC2             ((ushort)0x1d)
-#define CPMVEC_SCC3             ((ushort)0x1c)
-#define CPMVEC_SCC4             ((ushort)0x1b)
-#define CPMVEC_PIO_PC14         ((ushort)0x1a)
-#define CPMVEC_TIMER1           ((ushort)0x19)
-#define CPMVEC_PIO_PC13         ((ushort)0x18)
-#define CPMVEC_PIO_PC12         ((ushort)0x17)
-#define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
-#define CPMVEC_IDMA1            ((ushort)0x15)
-#define CPMVEC_IDMA2            ((ushort)0x14)
-#define CPMVEC_TIMER2           ((ushort)0x12)
-#define CPMVEC_RISCTIMER        ((ushort)0x11)
-#define CPMVEC_I2C              ((ushort)0x10)
-#define CPMVEC_PIO_PC11         ((ushort)0x0f)
-#define CPMVEC_PIO_PC10         ((ushort)0x0e)
-#define CPMVEC_TIMER3           ((ushort)0x0c)
-#define CPMVEC_PIO_PC9          ((ushort)0x0b)
-#define CPMVEC_PIO_PC8          ((ushort)0x0a)
-#define CPMVEC_PIO_PC7          ((ushort)0x09)
-#define CPMVEC_TIMER4           ((ushort)0x07)
-#define CPMVEC_PIO_PC6          ((ushort)0x06)
-#define CPMVEC_SPI              ((ushort)0x05)
-#define CPMVEC_SMC1             ((ushort)0x04)
-#define CPMVEC_SMC2             ((ushort)0x03)
-#define CPMVEC_PIO_PC5          ((ushort)0x02)
-#define CPMVEC_PIO_PC4          ((ushort)0x01)
-#define CPMVEC_ERROR            ((ushort)0x00)
-
-/* CPM interrupt configuration vector.
-*/
-#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
-#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
-#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
-#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
-#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
-#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
-#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
-#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
-
-extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
-extern void cpm_free_handler(int vec);
-
-#endif /* __CPM1__ */
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
deleted file mode 100644
index 4c538228e42f..000000000000
--- a/include/asm-ppc/cpm2.h
+++ /dev/null
@@ -1,1248 +0,0 @@
-/*
- * Communication Processor Module v2.
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the CPM2 internal
- * memory map.  See immap_cpm2.h for details.
- */
-#ifdef __KERNEL__
-#ifndef __CPM2__
-#define __CPM2__
-
-#include <asm/immap_cpm2.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST      ((uint)0x80000000)
-#define CPM_CR_PAGE     ((uint)0x7c000000)
-#define CPM_CR_SBLOCK   ((uint)0x03e00000)
-#define CPM_CR_FLG      ((uint)0x00010000)
-#define CPM_CR_MCN      ((uint)0x00003fc0)
-#define CPM_CR_OPCODE   ((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK      (0x04)
-#define CPM_CR_SCC2_SBLOCK      (0x05)
-#define CPM_CR_SCC3_SBLOCK      (0x06)
-#define CPM_CR_SCC4_SBLOCK      (0x07)
-#define CPM_CR_SMC1_SBLOCK      (0x08)
-#define CPM_CR_SMC2_SBLOCK      (0x09)
-#define CPM_CR_SPI_SBLOCK       (0x0a)
-#define CPM_CR_I2C_SBLOCK       (0x0b)
-#define CPM_CR_TIMER_SBLOCK     (0x0f)
-#define CPM_CR_RAND_SBLOCK      (0x0e)
-#define CPM_CR_FCC1_SBLOCK      (0x10)
-#define CPM_CR_FCC2_SBLOCK      (0x11)
-#define CPM_CR_FCC3_SBLOCK      (0x12)
-#define CPM_CR_IDMA1_SBLOCK     (0x14)
-#define CPM_CR_IDMA2_SBLOCK     (0x15)
-#define CPM_CR_IDMA3_SBLOCK     (0x16)
-#define CPM_CR_IDMA4_SBLOCK     (0x17)
-#define CPM_CR_MCC1_SBLOCK      (0x1c)
-
-#define CPM_CR_FCC_SBLOCK(x)    (x + 0x10)
-
-#define CPM_CR_SCC1_PAGE        (0x00)
-#define CPM_CR_SCC2_PAGE        (0x01)
-#define CPM_CR_SCC3_PAGE        (0x02)
-#define CPM_CR_SCC4_PAGE        (0x03)
-#define CPM_CR_SMC1_PAGE        (0x07)
-#define CPM_CR_SMC2_PAGE        (0x08)
-#define CPM_CR_SPI_PAGE         (0x09)
-#define CPM_CR_I2C_PAGE         (0x0a)
-#define CPM_CR_TIMER_PAGE       (0x0a)
-#define CPM_CR_RAND_PAGE        (0x0a)
-#define CPM_CR_FCC1_PAGE        (0x04)
-#define CPM_CR_FCC2_PAGE        (0x05)
-#define CPM_CR_FCC3_PAGE        (0x06)
-#define CPM_CR_IDMA1_PAGE       (0x07)
-#define CPM_CR_IDMA2_PAGE       (0x08)
-#define CPM_CR_IDMA3_PAGE       (0x09)
-#define CPM_CR_IDMA4_PAGE       (0x0a)
-#define CPM_CR_MCC1_PAGE        (0x07)
-#define CPM_CR_MCC2_PAGE        (0x08)
-
-#define CPM_CR_FCC_PAGE(x)      (x + 0x04)
-
-/* Some opcodes (there are more...later)
-*/
-#define CPM_CR_INIT_TRX         ((ushort)0x0000)
-#define CPM_CR_INIT_RX          ((ushort)0x0001)
-#define CPM_CR_INIT_TX          ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
-#define CPM_CR_STOP_TX          ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
-#define CPM_CR_RESTART_TX       ((ushort)0x0006)
-#define CPM_CR_SET_GADDR        ((ushort)0x0008)
-#define CPM_CR_START_IDMA       ((ushort)0x0009)
-#define CPM_CR_STOP_IDMA        ((ushort)0x000b)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-        ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE       ((uint)128)
-#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
-#if defined(CONFIG_8272)
-#define CPM_DATAONLY_SIZE       ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE    ((uint)0x00009000)
-#else
-#define CPM_DATAONLY_SIZE       ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE    ((uint)0x0000b000)
-#endif
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES      2
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern          cpm_cpm2_t      *cpmp;   /* Pointer to comm processor */
-
-extern unsigned long cpm_dpalloc(uint size, uint align);
-extern int cpm_dpfree(unsigned long offset);
-extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
-extern void cpm_dpdump(void);
-extern void *cpm_dpram_addr(unsigned long offset);
-extern void cpm_setbrg(uint brg, uint rate);
-extern void cpm2_fastbrg(uint brg, uint rate, int div16);
-extern void cpm2_reset(void);
-
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-        ushort  cbd_sc;         /* Status and Control */
-        ushort  cbd_datlen;     /* Data length in buffer */
-        uint    cbd_bufaddr;    /* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
-#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
-#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
-#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
-#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
-#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
-#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
-#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
-#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
-#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
-#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
-#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
-#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
-
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
-#define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
-#define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
-#define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
-#define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
-
-/* Parameter RAM offsets from the base.
-*/
-#define PROFF_SCC1              ((uint)0x8000)
-#define PROFF_SCC2              ((uint)0x8100)
-#define PROFF_SCC3              ((uint)0x8200)
-#define PROFF_SCC4              ((uint)0x8300)
-#define PROFF_FCC1              ((uint)0x8400)
-#define PROFF_FCC2              ((uint)0x8500)
-#define PROFF_FCC3              ((uint)0x8600)
-#define PROFF_MCC1              ((uint)0x8700)
-#define PROFF_SMC1_BASE         ((uint)0x87fc)
-#define PROFF_IDMA1_BASE        ((uint)0x87fe)
-#define PROFF_MCC2              ((uint)0x8800)
-#define PROFF_SMC2_BASE         ((uint)0x88fc)
-#define PROFF_IDMA2_BASE        ((uint)0x88fe)
-#define PROFF_SPI_BASE          ((uint)0x89fc)
-#define PROFF_IDMA3_BASE        ((uint)0x89fe)
-#define PROFF_TIMERS            ((uint)0x8ae0)
-#define PROFF_REVNUM            ((uint)0x8af0)
-#define PROFF_RAND              ((uint)0x8af8)
-#define PROFF_I2C_BASE          ((uint)0x8afc)
-#define PROFF_IDMA4_BASE        ((uint)0x8afe)
-
-#define PROFF_SCC_SIZE          ((uint)0x100)
-#define PROFF_FCC_SIZE          ((uint)0x100)
-#define PROFF_SMC_SIZE          ((uint)64)
-
-/* The SMCs are relocated to any of the first eight DPRAM pages.
- * We will fix these at the first locations of DPRAM, until we
- * get some microcode patches :-).
- * The parameter ram space for the SMCs is fifty-some bytes, and
- * they are required to start on a 64 byte boundary.
- */
-#define PROFF_SMC1      (0)
-#define PROFF_SMC2      (64)
-
-
-/* Define enough so I can at least use the serial port as a UART.
- */
-typedef struct smc_uart {
-        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
-        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
-        u_char  smc_rfcr;       /* Rx function code */
-        u_char  smc_tfcr;       /* Tx function code */
-        ushort  smc_mrblr;      /* Max receive buffer length */
-        uint    smc_rstate;     /* Internal */
-        uint    smc_idp;        /* Internal */
-        ushort  smc_rbptr;      /* Internal */
-        ushort  smc_ibc;        /* Internal */
-        uint    smc_rxtmp;      /* Internal */
-        uint    smc_tstate;     /* Internal */
-        uint    smc_tdp;        /* Internal */
-        ushort  smc_tbptr;      /* Internal */
-        ushort  smc_tbc;        /* Internal */
-        uint    smc_txtmp;      /* Internal */
-        ushort  smc_maxidl;     /* Maximum idle characters */
-        ushort  smc_tmpidl;     /* Temporary idle counter */
-        ushort  smc_brklen;     /* Last received break length */
-        ushort  smc_brkec;      /* rcv'd break condition counter */
-        ushort  smc_brkcr;      /* xmt break count register */
-        ushort  smc_rmask;      /* Temporary bit mask */
-        uint    smc_stmp;       /* SDMA Temp */
-} smc_uart_t;
-
-/* SMC uart mode register (Internal memory map).
-*/
-#define SMCMR_REN       ((ushort)0x0001)
-#define SMCMR_TEN       ((ushort)0x0002)
-#define SMCMR_DM        ((ushort)0x000c)
-#define SMCMR_SM_GCI    ((ushort)0x0000)
-#define SMCMR_SM_UART   ((ushort)0x0020)
-#define SMCMR_SM_TRANS  ((ushort)0x0030)
-#define SMCMR_SM_MASK   ((ushort)0x0030)
-#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
-#define SMCMR_REVD      SMCMR_PM_EVEN
-#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
-#define SMCMR_BS        SMCMR_PEN
-#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
-#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
-#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC Event and Mask register.
-*/
-#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
-#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
-#define SMCM_TXE        ((unsigned char)0x10)
-#define SMCM_BSY        ((unsigned char)0x04)
-#define SMCM_TX         ((unsigned char)0x02)
-#define SMCM_RX         ((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST             ((uint)0x00020000)
-#define CPM_BRG_EN              ((uint)0x00010000)
-#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9     ((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15    ((uint)0x00008000)
-#define CPM_BRG_ATB             ((uint)0x00002000)
-#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
-#define CPM_BRG_DIV16           ((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP           ((uint)0x00040000)
-#define SCC_GSMRH_GDE           ((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
-#define SCC_GSMRH_REVD          ((uint)0x00002000)
-#define SCC_GSMRH_TRX           ((uint)0x00001000)
-#define SCC_GSMRH_TTX           ((uint)0x00000800)
-#define SCC_GSMRH_CDP           ((uint)0x00000400)
-#define SCC_GSMRH_CTSP          ((uint)0x00000200)
-#define SCC_GSMRH_CDS           ((uint)0x00000100)
-#define SCC_GSMRH_CTSS          ((uint)0x00000080)
-#define SCC_GSMRH_TFL           ((uint)0x00000040)
-#define SCC_GSMRH_RFW           ((uint)0x00000020)
-#define SCC_GSMRH_TXSY          ((uint)0x00000010)
-#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
-#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
-#define SCC_GSMRH_RTSM          ((uint)0x00000002)
-#define SCC_GSMRH_RSYN          ((uint)0x00000001)
-
-#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
-#define SCC_GSMRL_TCI           ((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
-#define SCC_GSMRL_RINV          ((uint)0x02000000)
-#define SCC_GSMRL_TINV          ((uint)0x01000000)
-#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
-#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
-#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
-#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
-#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
-#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
-#define SCC_GSMRL_TEND          ((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
-#define SCC_GSMRL_ENR           ((uint)0x00000020)
-#define SCC_GSMRL_ENT           ((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
-
-#define SCC_TODR_TOD            ((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define SCCM_TXE        ((unsigned char)0x10)
-#define SCCM_BSY        ((unsigned char)0x04)
-#define SCCM_TX         ((unsigned char)0x02)
-#define SCCM_RX         ((unsigned char)0x01)
-
-typedef struct scc_param {
-        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
-        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
-        u_char  scc_rfcr;       /* Rx function code */
-        u_char  scc_tfcr;       /* Tx function code */
-        ushort  scc_mrblr;      /* Max receive buffer length */
-        uint    scc_rstate;     /* Internal */
-        uint    scc_idp;        /* Internal */
-        ushort  scc_rbptr;      /* Internal */
-        ushort  scc_ibc;        /* Internal */
-        uint    scc_rxtmp;      /* Internal */
-        uint    scc_tstate;     /* Internal */
-        uint    scc_tdp;        /* Internal */
-        ushort  scc_tbptr;      /* Internal */
-        ushort  scc_tbc;        /* Internal */
-        uint    scc_txtmp;      /* Internal */
-        uint    scc_rcrc;       /* Internal */
-        uint    scc_tcrc;       /* Internal */
-} sccp_t;
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-        sccp_t  sen_genscc;
-        uint    sen_cpres;      /* Preset CRC */
-        uint    sen_cmask;      /* Constant mask for CRC */
-        uint    sen_crcec;      /* CRC Error counter */
-        uint    sen_alec;       /* alignment error counter */
-        uint    sen_disfc;      /* discard frame counter */
-        ushort  sen_pads;       /* Tx short frame pad character */
-        ushort  sen_retlim;     /* Retry limit threshold */
-        ushort  sen_retcnt;     /* Retry limit counter */
-        ushort  sen_maxflr;     /* maximum frame length register */
-        ushort  sen_minflr;     /* minimum frame length register */
-        ushort  sen_maxd1;      /* maximum DMA1 length */
-        ushort  sen_maxd2;      /* maximum DMA2 length */
-        ushort  sen_maxd;       /* Rx max DMA */
-        ushort  sen_dmacnt;     /* Rx DMA counter */
-        ushort  sen_maxb;       /* Max BD byte count */
-        ushort  sen_gaddr1;     /* Group address filter */
-        ushort  sen_gaddr2;
-        ushort  sen_gaddr3;
-        ushort  sen_gaddr4;
-        uint    sen_tbuf0data0; /* Save area 0 - current frame */
-        uint    sen_tbuf0data1; /* Save area 1 - current frame */
-        uint    sen_tbuf0rba;   /* Internal */
-        uint    sen_tbuf0crc;   /* Internal */
-        ushort  sen_tbuf0bcnt;  /* Internal */
-        ushort  sen_paddrh;     /* physical address (MSB) */
-        ushort  sen_paddrm;
-        ushort  sen_paddrl;     /* physical address (LSB) */
-        ushort  sen_pper;       /* persistence */
-        ushort  sen_rfbdptr;    /* Rx first BD pointer */
-        ushort  sen_tfbdptr;    /* Tx first BD pointer */
-        ushort  sen_tlbdptr;    /* Tx last BD pointer */
-        uint    sen_tbuf1data0; /* Save area 0 - current frame */
-        uint    sen_tbuf1data1; /* Save area 1 - current frame */
-        uint    sen_tbuf1rba;   /* Internal */
-        uint    sen_tbuf1crc;   /* Internal */
-        ushort  sen_tbuf1bcnt;  /* Internal */
-        ushort  sen_txlen;      /* Tx Frame length counter */
-        ushort  sen_iaddr1;     /* Individual address filter */
-        ushort  sen_iaddr2;
-        ushort  sen_iaddr3;
-        ushort  sen_iaddr4;
-        ushort  sen_boffcnt;    /* Backoff counter */
-
-        /* NOTE: Some versions of the manual have the following items
-         * incorrectly documented.  Below is the proper order.
-         */
-        ushort  sen_taddrh;     /* temp address (MSB) */
-        ushort  sen_taddrm;
-        ushort  sen_taddrl;     /* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
-#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
-#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
-#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
-#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
-#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
-#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
-#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
-#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
-#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
-#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
-#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
-#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
-#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
-#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
-#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
-#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
-#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
-#define BD_ENET_RX_WRAP         ((ushort)0x2000)
-#define BD_ENET_RX_INTR         ((ushort)0x1000)
-#define BD_ENET_RX_LAST         ((ushort)0x0800)
-#define BD_ENET_RX_FIRST        ((ushort)0x0400)
-#define BD_ENET_RX_MISS         ((ushort)0x0100)
-#define BD_ENET_RX_BC           ((ushort)0x0080)        /* FCC Only */
-#define BD_ENET_RX_MC           ((ushort)0x0040)        /* FCC Only */
-#define BD_ENET_RX_LG           ((ushort)0x0020)
-#define BD_ENET_RX_NO           ((ushort)0x0010)
-#define BD_ENET_RX_SH           ((ushort)0x0008)
-#define BD_ENET_RX_CR           ((ushort)0x0004)
-#define BD_ENET_RX_OV           ((ushort)0x0002)
-#define BD_ENET_RX_CL           ((ushort)0x0001)
-#define BD_ENET_RX_STATS        ((ushort)0x01ff)        /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY        ((ushort)0x8000)
-#define BD_ENET_TX_PAD          ((ushort)0x4000)
-#define BD_ENET_TX_WRAP         ((ushort)0x2000)
-#define BD_ENET_TX_INTR         ((ushort)0x1000)
-#define BD_ENET_TX_LAST         ((ushort)0x0800)
-#define BD_ENET_TX_TC           ((ushort)0x0400)
-#define BD_ENET_TX_DEF          ((ushort)0x0200)
-#define BD_ENET_TX_HB           ((ushort)0x0100)
-#define BD_ENET_TX_LC           ((ushort)0x0080)
-#define BD_ENET_TX_RL           ((ushort)0x0040)
-#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
-#define BD_ENET_TX_UN           ((ushort)0x0002)
-#define BD_ENET_TX_CSL          ((ushort)0x0001)
-#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-        sccp_t  scc_genscc;
-        uint    scc_res1;       /* Reserved */
-        uint    scc_res2;       /* Reserved */
-        ushort  scc_maxidl;     /* Maximum idle chars */
-        ushort  scc_idlc;       /* temp idle counter */
-        ushort  scc_brkcr;      /* Break count register */
-        ushort  scc_parec;      /* receive parity error counter */
-        ushort  scc_frmec;      /* receive framing error counter */
-        ushort  scc_nosec;      /* receive noise counter */
-        ushort  scc_brkec;      /* receive break condition counter */
-        ushort  scc_brkln;      /* last received break length */
-        ushort  scc_uaddr1;     /* UART address character 1 */
-        ushort  scc_uaddr2;     /* UART address character 2 */
-        ushort  scc_rtemp;      /* Temp storage */
-        ushort  scc_toseq;      /* Transmit out of sequence char */
-        ushort  scc_char1;      /* control character 1 */
-        ushort  scc_char2;      /* control character 2 */
-        ushort  scc_char3;      /* control character 3 */
-        ushort  scc_char4;      /* control character 4 */
-        ushort  scc_char5;      /* control character 5 */
-        ushort  scc_char6;      /* control character 6 */
-        ushort  scc_char7;      /* control character 7 */
-        ushort  scc_char8;      /* control character 8 */
-        ushort  scc_rccm;       /* receive control character mask */
-        ushort  scc_rccr;       /* receive control character register */
-        ushort  scc_rlbc;       /* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR           ((ushort)0x1000)
-#define UART_SCCM_GLT           ((ushort)0x0800)
-#define UART_SCCM_AB            ((ushort)0x0200)
-#define UART_SCCM_IDL           ((ushort)0x0100)
-#define UART_SCCM_GRA           ((ushort)0x0080)
-#define UART_SCCM_BRKE          ((ushort)0x0040)
-#define UART_SCCM_BRKS          ((ushort)0x0020)
-#define UART_SCCM_CCR           ((ushort)0x0008)
-#define UART_SCCM_BSY           ((ushort)0x0004)
-#define UART_SCCM_TX            ((ushort)0x0002)
-#define UART_SCCM_RX            ((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC            ((ushort)0x8000)
-#define SCU_PSMR_SL             ((ushort)0x4000)
-#define SCU_PSMR_CL             ((ushort)0x3000)
-#define SCU_PSMR_UM             ((ushort)0x0c00)
-#define SCU_PSMR_FRZ            ((ushort)0x0200)
-#define SCU_PSMR_RZS            ((ushort)0x0100)
-#define SCU_PSMR_SYN            ((ushort)0x0080)
-#define SCU_PSMR_DRT            ((ushort)0x0040)
-#define SCU_PSMR_PEN            ((ushort)0x0010)
-#define SCU_PSMR_RPM            ((ushort)0x000c)
-#define SCU_PSMR_REVP           ((ushort)0x0008)
-#define SCU_PSMR_TPM            ((ushort)0x0003)
-#define SCU_PSMR_TEVP           ((ushort)0x0002)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-        sccp_t  st_genscc;
-        uint    st_cpres;       /* Preset CRC */
-        uint    st_cmask;       /* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST          ((ushort)0x0800)
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM      ((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE        ((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE        ((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE       ((uint)0xc0000000)
-#define FCC_GFMR_TCI            ((uint)0x20000000)
-#define FCC_GFMR_TRX            ((uint)0x10000000)
-#define FCC_GFMR_TTX            ((uint)0x08000000)
-#define FCC_GFMR_TTX            ((uint)0x08000000)
-#define FCC_GFMR_CDP            ((uint)0x04000000)
-#define FCC_GFMR_CTSP           ((uint)0x02000000)
-#define FCC_GFMR_CDS            ((uint)0x01000000)
-#define FCC_GFMR_CTSS           ((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE      ((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO      ((uint)0x00004000)
-#define FCC_GFMR_SYNL_8         ((uint)0x00008000)
-#define FCC_GFMR_SYNL_16        ((uint)0x0000c000)
-#define FCC_GFMR_RTSM           ((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ       ((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI      ((uint)0x00000800)
-#define FCC_GFMR_REVD           ((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ       ((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI      ((uint)0x00000100)
-#define FCC_GFMR_TCRC_16        ((uint)0x00000000)
-#define FCC_GFMR_TCRC_32        ((uint)0x00000080)
-#define FCC_GFMR_ENR            ((uint)0x00000020)
-#define FCC_GFMR_ENT            ((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET      ((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM       ((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC      ((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-        ushort  fcc_riptr;      /* Rx Internal temp pointer */
-        ushort  fcc_tiptr;      /* Tx Internal temp pointer */
-        ushort  fcc_res1;
-        ushort  fcc_mrblr;      /* Max receive buffer length, mod 32 bytes */
-        uint    fcc_rstate;     /* Upper byte is Func code, must be set */
-        uint    fcc_rbase;      /* Receive BD base */
-        ushort  fcc_rbdstat;    /* RxBD status */
-        ushort  fcc_rbdlen;     /* RxBD down counter */
-        uint    fcc_rdptr;      /* RxBD internal data pointer */
-        uint    fcc_tstate;     /* Upper byte is Func code, must be set */
-        uint    fcc_tbase;      /* Transmit BD base */
-        ushort  fcc_tbdstat;    /* TxBD status */
-        ushort  fcc_tbdlen;     /* TxBD down counter */
-        uint    fcc_tdptr;      /* TxBD internal data pointer */
-        uint    fcc_rbptr;      /* Rx BD Internal buf pointer */
-        uint    fcc_tbptr;      /* Tx BD Internal buf pointer */
-        uint    fcc_rcrc;       /* Rx temp CRC */
-        uint    fcc_res2;
-        uint    fcc_tcrc;       /* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-        fccp_t  fen_genfcc;
-        uint    fen_statbuf;    /* Internal status buffer */
-        uint    fen_camptr;     /* CAM address */
-        uint    fen_cmask;      /* Constant mask for CRC */
-        uint    fen_cpres;      /* Preset CRC */
-        uint    fen_crcec;      /* CRC Error counter */
-        uint    fen_alec;       /* alignment error counter */
-        uint    fen_disfc;      /* discard frame counter */
-        ushort  fen_retlim;     /* Retry limit */
-        ushort  fen_retcnt;     /* Retry counter */
-        ushort  fen_pper;       /* Persistence */
-        ushort  fen_boffcnt;    /* backoff counter */
-        uint    fen_gaddrh;     /* Group address filter, high 32-bits */
-        uint    fen_gaddrl;     /* Group address filter, low 32-bits */
-        ushort  fen_tfcstat;    /* out of sequence TxBD */
-        ushort  fen_tfclen;
-        uint    fen_tfcptr;
-        ushort  fen_mflr;       /* Maximum frame length (1518) */
-        ushort  fen_paddrh;     /* MAC address */
-        ushort  fen_paddrm;
-        ushort  fen_paddrl;
-        ushort  fen_ibdcount;   /* Internal BD counter */
-        ushort  fen_ibdstart;   /* Internal BD start pointer */
-        ushort  fen_ibdend;     /* Internal BD end pointer */
-        ushort  fen_txlen;      /* Internal Tx frame length counter */
-        uint    fen_ibdbase[8]; /* Internal use */
-        uint    fen_iaddrh;     /* Individual address filter */
-        uint    fen_iaddrl;
-        ushort  fen_minflr;     /* Minimum frame length (64) */
-        ushort  fen_taddrh;     /* Filter transfer MAC address */
-        ushort  fen_taddrm;
-        ushort  fen_taddrl;
-        ushort  fen_padptr;     /* Pointer to pad byte buffer */
-        ushort  fen_cftype;     /* control frame type */
-        ushort  fen_cfrange;    /* control frame range */
-        ushort  fen_maxb;       /* maximum BD count */
-        ushort  fen_maxd1;      /* Max DMA1 length (1520) */
-        ushort  fen_maxd2;      /* Max DMA2 length (1520) */
-        ushort  fen_maxd;       /* internal max DMA count */
-        ushort  fen_dmacnt;     /* internal DMA counter */
-        uint    fen_octc;       /* Total octect counter */
-        uint    fen_colc;       /* Total collision counter */
-        uint    fen_broc;       /* Total broadcast packet counter */
-        uint    fen_mulc;       /* Total multicast packet count */
-        uint    fen_uspc;       /* Total packets < 64 bytes */
-        uint    fen_frgc;       /* Total packets < 64 bytes with errors */
-        uint    fen_ospc;       /* Total packets > 1518 */
-        uint    fen_jbrc;       /* Total packets > 1518 with errors */
-        uint    fen_p64c;       /* Total packets == 64 bytes */
-        uint    fen_p65c;       /* Total packets 64 < bytes <= 127 */
-        uint    fen_p128c;      /* Total packets 127 < bytes <= 255 */
-        uint    fen_p256c;      /* Total packets 256 < bytes <= 511 */
-        uint    fen_p512c;      /* Total packets 512 < bytes <= 1023 */
-        uint    fen_p1024c;     /* Total packets 1024 < bytes <= 1518 */
-        uint    fen_cambuf;     /* Internal CAM buffer poiner */
-        ushort  fen_rfthr;      /* Received frames threshold */
-        ushort  fen_rfcnt;      /* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA    ((ushort)0x0080)        /* Graceful stop complete */
-#define FCC_ENET_RXC    ((ushort)0x0040)        /* Control Frame Received */
-#define FCC_ENET_TXC    ((ushort)0x0020)        /* Out of seq. Tx sent */
-#define FCC_ENET_TXE    ((ushort)0x0010)        /* Transmit Error */
-#define FCC_ENET_RXF    ((ushort)0x0008)        /* Full frame received */
-#define FCC_ENET_BSY    ((ushort)0x0004)        /* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB    ((ushort)0x0002)        /* A buffer was transmitted */
-#define FCC_ENET_RXB    ((ushort)0x0001)        /* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC    ((uint)0x80000000)      /* Enable heartbeat */
-#define FCC_PSMR_FC     ((uint)0x40000000)      /* Force Collision */
-#define FCC_PSMR_SBT    ((uint)0x20000000)      /* Stop backoff timer */
-#define FCC_PSMR_LPB    ((uint)0x10000000)      /* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW    ((uint)0x08000000)      /* Late collision select */
-#define FCC_PSMR_FDE    ((uint)0x04000000)      /* Full Duplex Enable */
-#define FCC_PSMR_MON    ((uint)0x02000000)      /* RMON Enable */
-#define FCC_PSMR_PRO    ((uint)0x00400000)      /* Promiscuous Enable */
-#define FCC_PSMR_FCE    ((uint)0x00200000)      /* Flow Control Enable */
-#define FCC_PSMR_RSH    ((uint)0x00100000)      /* Receive Short Frames */
-#define FCC_PSMR_CAM    ((uint)0x00000400)      /* CAM enable */
-#define FCC_PSMR_BRO    ((uint)0x00000200)      /* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC  ((uint)0x00000080)      /* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
-        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
-        u_char  iic_rfcr;       /* Rx function code */
-        u_char  iic_tfcr;       /* Tx function code */
-        ushort  iic_mrblr;      /* Max receive buffer length */
-        uint    iic_rstate;     /* Internal */
-        uint    iic_rdp;        /* Internal */
-        ushort  iic_rbptr;      /* Internal */
-        ushort  iic_rbc;        /* Internal */
-        uint    iic_rxtmp;      /* Internal */
-        uint    iic_tstate;     /* Internal */
-        uint    iic_tdp;        /* Internal */
-        ushort  iic_tbptr;      /* Internal */
-        ushort  iic_tbc;        /* Internal */
-        uint    iic_txtmp;      /* Internal */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
-        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
-        u_char  spi_rfcr;       /* Rx function code */
-        u_char  spi_tfcr;       /* Tx function code */
-        ushort  spi_mrblr;      /* Max receive buffer length */
-        uint    spi_rstate;     /* Internal */
-        uint    spi_rdp;        /* Internal */
-        ushort  spi_rbptr;      /* Internal */
-        ushort  spi_rbc;        /* Internal */
-        uint    spi_rxtmp;      /* Internal */
-        uint    spi_tstate;     /* Internal */
-        uint    spi_tdp;        /* Internal */
-        ushort  spi_tbptr;      /* Internal */
-        ushort  spi_tbc;        /* Internal */
-        uint    spi_txtmp;      /* Internal */
-        uint    spi_res;        /* Tx temp. */
-        uint    spi_res1[4];    /* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
-#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
-#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
-#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
-#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
-#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
-#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
-#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
-#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
-
-#define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)    ((x) &0xF)
-
-#define SPI_EB          ((u_char)0x10)          /* big endian byte order */
-
-#define BD_IIC_START            ((ushort)0x0400)
-
-/* IDMA parameter RAM
-*/
-typedef struct idma {
-        ushort ibase;           /* IDMA buffer descriptor table base address */
-        ushort dcm;             /* DMA channel mode */
-        ushort ibdptr;          /* IDMA current buffer descriptor pointer */
-        ushort dpr_buf;         /* IDMA transfer buffer base address */
-        ushort buf_inv;         /* internal buffer inventory */
-        ushort ss_max;          /* steady-state maximum transfer size */
-        ushort dpr_in_ptr;      /* write pointer inside the internal buffer */
-        ushort sts;             /* source transfer size */
-        ushort dpr_out_ptr;     /* read pointer inside the internal buffer */
-        ushort seob;            /* source end of burst */
-        ushort deob;            /* destination end of burst */
-        ushort dts;             /* destination transfer size */
-        ushort ret_add;         /* return address when working in ERM=1 mode */
-        ushort res0;            /* reserved */
-        uint   bd_cnt;          /* internal byte count */
-        uint   s_ptr;           /* source internal data pointer */
-        uint   d_ptr;           /* destination internal data pointer */
-        uint   istate;          /* internal state */
-        u_char res1[20];        /* pad to 64-byte length */
-} idma_t;
-
-/* DMA channel mode bit fields
-*/
-#define IDMA_DCM_FB             ((ushort)0x8000) /* fly-by mode */
-#define IDMA_DCM_LP             ((ushort)0x4000) /* low priority */
-#define IDMA_DCM_TC2            ((ushort)0x0400) /* value driven on TC[2] */
-#define IDMA_DCM_DMA_WRAP_MASK  ((ushort)0x01c0) /* mask for DMA wrap */
-#define IDMA_DCM_DMA_WRAP_64    ((ushort)0x0000) /* 64-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_128   ((ushort)0x0040) /* 128-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_256   ((ushort)0x0080) /* 256-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_512   ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_1024  ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_2048  ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
-#define IDMA_DCM_SINC           ((ushort)0x0020) /* source inc addr */
-#define IDMA_DCM_DINC           ((ushort)0x0010) /* destination inc addr */
-#define IDMA_DCM_ERM            ((ushort)0x0008) /* external request mode */
-#define IDMA_DCM_DT             ((ushort)0x0004) /* DONE treatment */
-#define IDMA_DCM_SD_MASK        ((ushort)0x0003) /* mask for SD bit field */
-#define IDMA_DCM_SD_MEM2MEM     ((ushort)0x0000) /* memory-to-memory xfer */
-#define IDMA_DCM_SD_PER2MEM     ((ushort)0x0002) /* peripheral-to-memory xfer */
-#define IDMA_DCM_SD_MEM2PER     ((ushort)0x0001) /* memory-to-peripheral xfer */
-
-/* IDMA Buffer Descriptors
-*/
-typedef struct idma_bd {
-        uint flags;
-        uint len;       /* data length */
-        uint src;       /* source data buffer pointer */
-        uint dst;       /* destination data buffer pointer */
-} idma_bd_t;
-
-/* IDMA buffer descriptor flag bit fields
-*/
-#define IDMA_BD_V       ((uint)0x80000000)      /* valid */
-#define IDMA_BD_W       ((uint)0x20000000)      /* wrap */
-#define IDMA_BD_I       ((uint)0x10000000)      /* interrupt */
-#define IDMA_BD_L       ((uint)0x08000000)      /* last */
-#define IDMA_BD_CM      ((uint)0x02000000)      /* continuous mode */
-#define IDMA_BD_SDN     ((uint)0x00400000)      /* source done */
-#define IDMA_BD_DDN     ((uint)0x00200000)      /* destination done */
-#define IDMA_BD_DGBL    ((uint)0x00100000)      /* destination global */
-#define IDMA_BD_DBO_LE  ((uint)0x00040000)      /* little-end dest byte order */
-#define IDMA_BD_DBO_BE  ((uint)0x00080000)      /* big-end dest byte order */
-#define IDMA_BD_DDTB    ((uint)0x00010000)      /* destination data bus */
-#define IDMA_BD_SGBL    ((uint)0x00002000)      /* source global */
-#define IDMA_BD_SBO_LE  ((uint)0x00000800)      /* little-end src byte order */
-#define IDMA_BD_SBO_BE  ((uint)0x00001000)      /* big-end src byte order */
-#define IDMA_BD_SDTB    ((uint)0x00000200)      /* source data bus */
-
-/* per-channel IDMA registers
-*/
-typedef struct im_idma {
-        u_char idsr;                    /* IDMAn event status register */
-        u_char res0[3];
-        u_char idmr;                    /* IDMAn event mask register */
-        u_char res1[3];
-} im_idma_t;
-
-/* IDMA event register bit fields
-*/
-#define IDMA_EVENT_SC   ((unsigned char)0x08)   /* stop completed */
-#define IDMA_EVENT_OB   ((unsigned char)0x04)   /* out of buffers */
-#define IDMA_EVENT_EDN  ((unsigned char)0x02)   /* external DONE asserted */
-#define IDMA_EVENT_BC   ((unsigned char)0x01)   /* buffer descriptor complete */
-
-/* RISC Controller Configuration Register (RCCR) bit fields
-*/
-#define RCCR_TIME       ((uint)0x80000000) /* timer enable */
-#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
-#define RCCR_DR0M       ((uint)0x00800000) /* IDMA0 request mode */
-#define RCCR_DR1M       ((uint)0x00400000) /* IDMA1 request mode */
-#define RCCR_DR2M       ((uint)0x00000080) /* IDMA2 request mode */
-#define RCCR_DR3M       ((uint)0x00000040) /* IDMA3 request mode */
-#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
-#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
-#define RCCR_DR0QP_MED  ((uint)0x00100000) /* IDMA0 has medium req priority */
-#define RCCR_DR0QP_LOW  ((uint)0x00200000) /* IDMA0 has low req priority */
-#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
-#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
-#define RCCR_DR1QP_MED  ((uint)0x00010000) /* IDMA1 has medium req priority */
-#define RCCR_DR1QP_LOW  ((uint)0x00020000) /* IDMA1 has low req priority */
-#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
-#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
-#define RCCR_DR2QP_MED  ((uint)0x00000010) /* IDMA2 has medium req priority */
-#define RCCR_DR2QP_LOW  ((uint)0x00000020) /* IDMA2 has low req priority */
-#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
-#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
-#define RCCR_DR3QP_MED  ((uint)0x00000001) /* IDMA3 has medium req priority */
-#define RCCR_DR3QP_LOW  ((uint)0x00000002) /* IDMA3 has low req priority */
-#define RCCR_EIE        ((uint)0x00080000) /* external interrupt enable */
-#define RCCR_SCD        ((uint)0x00040000) /* scheduler configuration */
-#define RCCR_ERAM_MASK  ((uint)0x0000e000) /* mask for enable RAM microcode */
-#define RCCR_ERAM_0KB   ((uint)0x00000000) /* use 0KB of dpram for microcode */
-#define RCCR_ERAM_2KB   ((uint)0x00002000) /* use 2KB of dpram for microcode */
-#define RCCR_ERAM_4KB   ((uint)0x00004000) /* use 4KB of dpram for microcode */
-#define RCCR_ERAM_6KB   ((uint)0x00006000) /* use 6KB of dpram for microcode */
-#define RCCR_ERAM_8KB   ((uint)0x00008000) /* use 8KB of dpram for microcode */
-#define RCCR_ERAM_10KB  ((uint)0x0000a000) /* use 10KB of dpram for microcode */
-#define RCCR_ERAM_12KB  ((uint)0x0000c000) /* use 12KB of dpram for microcode */
-#define RCCR_EDM0       ((uint)0x00000800) /* DREQ0 edge detect mode */
-#define RCCR_EDM1       ((uint)0x00000400) /* DREQ1 edge detect mode */
-#define RCCR_EDM2       ((uint)0x00000200) /* DREQ2 edge detect mode */
-#define RCCR_EDM3       ((uint)0x00000100) /* DREQ3 edge detect mode */
-#define RCCR_DEM01      ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
-#define RCCR_DEM23      ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
-
-/*-----------------------------------------------------------------------
- * CMXFCR - CMX FCC Clock Route Register
- */
-#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
-#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
-#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
-#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
-#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
-#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
-#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
-#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
-#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
-
-#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
-#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
-#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
-#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
-#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
-#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
-#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
-#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
-#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
-#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
-#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
-#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
-#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
-#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
-#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
-#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
-#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
-#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
-#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
-#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
-#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
-#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
-#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
-#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
-#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
-#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
-#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
-#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
-#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
-#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
-#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
-#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
-#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
-#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
-#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
-#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
-
-#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
-#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
-#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
-#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
-#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
-#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
-#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
-#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
-
-/*-----------------------------------------------------------------------
- * CMXSCR - CMX SCC Clock Route Register
- */
-#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
-#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
-#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
-#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
-#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
-#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
-#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
-#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
-#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
-#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
-#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
-#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
-#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
-#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
-#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
-#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
-
-#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
-#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
-#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
-#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
-#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
-#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
-#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
-#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
-#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
-#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
-#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
-#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
-#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
-#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
-#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
-#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
-#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
-#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
-#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
-#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
-#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
-#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
-#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
-#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
-#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
-#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
-#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
-#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
-#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
-#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
-#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
-#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
-#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
-#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
-#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
-#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
-#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
-#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
-#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
-#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
-#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
-#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
-#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
-
-#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
-#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
-#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
-#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
-#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
-#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
-#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
-#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
-#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
-#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
-#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
-#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
-#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
-#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
-#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration Register                            4-31
- */
-#define SIUMCR_BBD      0x80000000      /* Bus Busy Disable             */
-#define SIUMCR_ESE      0x40000000      /* External Snoop Enable        */
-#define SIUMCR_PBSE     0x20000000      /* Parity Byte Select Enable    */
-#define SIUMCR_CDIS     0x10000000      /* Core Disable                 */
-#define SIUMCR_DPPC00   0x00000000      /* Data Parity Pins Configuration*/
-#define SIUMCR_DPPC01   0x04000000      /* - " -                        */
-#define SIUMCR_DPPC10   0x08000000      /* - " -                        */
-#define SIUMCR_DPPC11   0x0c000000      /* - " -                        */
-#define SIUMCR_L2CPC00  0x00000000      /* L2 Cache Pins Configuration  */
-#define SIUMCR_L2CPC01  0x01000000      /* - " -                        */
-#define SIUMCR_L2CPC10  0x02000000      /* - " -                        */
-#define SIUMCR_L2CPC11  0x03000000      /* - " -                        */
-#define SIUMCR_LBPC00   0x00000000      /* Local Bus Pins Configuration */
-#define SIUMCR_LBPC01   0x00400000      /* - " -                        */
-#define SIUMCR_LBPC10   0x00800000      /* - " -                        */
-#define SIUMCR_LBPC11   0x00c00000      /* - " -                        */
-#define SIUMCR_APPC00   0x00000000      /* Address Parity Pins Configuration*/
-#define SIUMCR_APPC01   0x00100000      /* - " -                        */
-#define SIUMCR_APPC10   0x00200000      /* - " -                        */
-#define SIUMCR_APPC11   0x00300000      /* - " -                        */
-#define SIUMCR_CS10PC00 0x00000000      /* CS10 Pin Configuration       */
-#define SIUMCR_CS10PC01 0x00040000      /* - " -                        */
-#define SIUMCR_CS10PC10 0x00080000      /* - " -                        */
-#define SIUMCR_CS10PC11 0x000c0000      /* - " -                        */
-#define SIUMCR_BCTLC00  0x00000000      /* Buffer Control Configuration */
-#define SIUMCR_BCTLC01  0x00010000      /* - " -                        */
-#define SIUMCR_BCTLC10  0x00020000      /* - " -                        */
-#define SIUMCR_BCTLC11  0x00030000      /* - " -                        */
-#define SIUMCR_MMR00    0x00000000      /* Mask Masters Requests        */
-#define SIUMCR_MMR01    0x00004000      /* - " -                        */
-#define SIUMCR_MMR10    0x00008000      /* - " -                        */
-#define SIUMCR_MMR11    0x0000c000      /* - " -                        */
-#define SIUMCR_LPBSE    0x00002000      /* LocalBus Parity Byte Select Enable*/
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control Register                                  9-8
-*/
-#define SCCR_PCI_MODE   0x00000100      /* PCI Mode     */
-#define SCCR_PCI_MODCK  0x00000080      /* Value of PCI_MODCK pin       */
-#define SCCR_PCIDF_MSK  0x00000078      /* PCI division factor  */
-#define SCCR_PCIDF_SHIFT 3
-
-#ifndef CPM_IMMR_OFFSET
-#define CPM_IMMR_OFFSET 0x101a8
-#endif
-
-#define FCC_PSMR_RMII   ((uint)0x00020000)      /* Use RMII interface */
-
-/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
- * in order to use clock-computing stuff below for the FCC x
- */
-
-/* Automatically generates register configurations */
-#define PC_CLK(x)       ((uint)(1<<(x-1)))      /* FCC CLK I/O ports */
-
-#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27))     /* FCC1 Receive Clock Source */
-#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24))     /* FCC1 Transmit Clock Source */
-#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19))     /* FCC2 Receive Clock Source */
-#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))     /* FCC2 Transmit Clock Source */
-#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11))     /* FCC3 Receive Clock Source */
-#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))      /* FCC3 Transmit Clock Source */
-
-#define PC_F1RXCLK      PC_CLK(F1_RXCLK)
-#define PC_F1TXCLK      PC_CLK(F1_TXCLK)
-#define CMX1_CLK_ROUTE  (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
-#define CMX1_CLK_MASK   ((uint)0xff000000)
-
-#define PC_F2RXCLK      PC_CLK(F2_RXCLK)
-#define PC_F2TXCLK      PC_CLK(F2_TXCLK)
-#define CMX2_CLK_ROUTE  (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
-#define CMX2_CLK_MASK   ((uint)0x00ff0000)
-
-#define PC_F3RXCLK      PC_CLK(F3_RXCLK)
-#define PC_F3TXCLK      PC_CLK(F3_TXCLK)
-#define CMX3_CLK_ROUTE  (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
-#define CMX3_CLK_MASK   ((uint)0x0000ff00)
-
-#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
-#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
-
-#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
-
-/* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PA1_COL         0x00000001U
-#define PA1_CRS         0x00000002U
-#define PA1_TXER        0x00000004U
-#define PA1_TXEN        0x00000008U
-#define PA1_RXDV        0x00000010U
-#define PA1_RXER        0x00000020U
-#define PA1_TXDAT       0x00003c00U
-#define PA1_RXDAT       0x0003c000U
-#define PA1_PSORA0      (PA1_RXDAT | PA1_TXDAT)
-#define PA1_PSORA1      (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
-                PA1_RXDV | PA1_RXER)
-#define PA1_DIRA0       (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
-#define PA1_DIRA1       (PA1_TXDAT | PA1_TXEN | PA1_TXER)
-
-
-/* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB2_TXER        0x00000001U
-#define PB2_RXDV        0x00000002U
-#define PB2_TXEN        0x00000004U
-#define PB2_RXER        0x00000008U
-#define PB2_COL         0x00000010U
-#define PB2_CRS         0x00000020U
-#define PB2_TXDAT       0x000003c0U
-#define PB2_RXDAT       0x00003c00U
-#define PB2_PSORB0      (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
-                PB2_RXER | PB2_RXDV | PB2_TXER)
-#define PB2_PSORB1      (PB2_TXEN)
-#define PB2_DIRB0       (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
-#define PB2_DIRB1       (PB2_TXDAT | PB2_TXEN | PB2_TXER)
-
-
-/* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB3_RXDV        0x00004000U
-#define PB3_RXER        0x00008000U
-#define PB3_TXER        0x00010000U
-#define PB3_TXEN        0x00020000U
-#define PB3_COL         0x00040000U
-#define PB3_CRS         0x00080000U
-#define PB3_TXDAT       0x0f000000U
-#define PC3_TXDAT       0x00000010U
-#define PB3_RXDAT       0x00f00000U
-#define PB3_PSORB0      (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
-                PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
-#define PB3_PSORB1      0
-#define PB3_DIRB0       (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
-#define PB3_DIRB1       (PB3_TXDAT | PB3_TXEN | PB3_TXER)
-#define PC3_DIRC1       (PC3_TXDAT)
-
-/* Handy macro to specify mem for FCCs*/
-#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
-#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
-#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
-#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
-
-/* Clocks and GRG's */
-
-enum cpm_clk_dir {
-        CPM_CLK_RX,
-        CPM_CLK_TX,
-        CPM_CLK_RTX
-};
-
-enum cpm_clk_target {
-        CPM_CLK_SCC1,
-        CPM_CLK_SCC2,
-        CPM_CLK_SCC3,
-        CPM_CLK_SCC4,
-        CPM_CLK_FCC1,
-        CPM_CLK_FCC2,
-        CPM_CLK_FCC3
-};
-
-enum cpm_clk {
-        CPM_CLK_NONE = 0,
-        CPM_BRG1,       /* Baud Rate Generator  1 */
-        CPM_BRG2,       /* Baud Rate Generator  2 */
-        CPM_BRG3,       /* Baud Rate Generator  3 */
-        CPM_BRG4,       /* Baud Rate Generator  4 */
-        CPM_BRG5,       /* Baud Rate Generator  5 */
-        CPM_BRG6,       /* Baud Rate Generator  6 */
-        CPM_BRG7,       /* Baud Rate Generator  7 */
-        CPM_BRG8,       /* Baud Rate Generator  8 */
-        CPM_CLK1,       /* Clock  1 */
-        CPM_CLK2,       /* Clock  2 */
-        CPM_CLK3,       /* Clock  3 */
-        CPM_CLK4,       /* Clock  4 */
-        CPM_CLK5,       /* Clock  5 */
-        CPM_CLK6,       /* Clock  6 */
-        CPM_CLK7,       /* Clock  7 */
-        CPM_CLK8,       /* Clock  8 */
-        CPM_CLK9,       /* Clock  9 */
-        CPM_CLK10,      /* Clock 10 */
-        CPM_CLK11,      /* Clock 11 */
-        CPM_CLK12,      /* Clock 12 */
-        CPM_CLK13,      /* Clock 13 */
-        CPM_CLK14,      /* Clock 14 */
-        CPM_CLK15,      /* Clock 15 */
-        CPM_CLK16,      /* Clock 16 */
-        CPM_CLK17,      /* Clock 17 */
-        CPM_CLK18,      /* Clock 18 */
-        CPM_CLK19,      /* Clock 19 */
-        CPM_CLK20,      /* Clock 20 */
-        CPM_CLK_DUMMY
-};
-
-extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
-
-#endif /* __CPM2__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h
deleted file mode 100644
index badde6845af2..000000000000
--- a/include/asm-ppc/delay.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_DELAY_H
-#define _PPC_DELAY_H
-
-#include <asm/param.h>
-
-/*
- * Copyright 1996, Paul Mackerras.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-extern unsigned long loops_per_jiffy;
-
-extern void __delay(unsigned int loops);
-
-/*
- * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
- * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32.
- *
- * The mulhwu instruction gives us loops = (a * b) / 2^32.
- * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
- * because this lets us support a wide range of HZ and
- * loops_per_jiffy values without either a or b overflowing 2^32.
- * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
- * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280
- * (which corresponds to ~3800 bogomips at HZ = 100).
- *  -- paulus
- */
-#define __MAX_UDELAY    (226050910UL/HZ)        /* maximum udelay argument */
-#define __MAX_NDELAY    (4294967295UL/HZ)       /* maximum ndelay argument */
-
-extern __inline__ void __udelay(unsigned int x)
-{
-        unsigned int loops;
-
-        __asm__("mulhwu %0,%1,%2" : "=r" (loops) :
-                "r" (x), "r" (loops_per_jiffy * 226));
-        __delay(loops);
-}
-
-extern __inline__ void __ndelay(unsigned int x)
-{
-        unsigned int loops;
-
-        __asm__("mulhwu %0,%1,%2" : "=r" (loops) :
-                "r" (x), "r" (loops_per_jiffy * 5));
-        __delay(loops);
-}
-
-extern void __bad_udelay(void);         /* deliberately undefined */
-extern void __bad_ndelay(void);         /* deliberately undefined */
-
-#define udelay(n) (__builtin_constant_p(n)? \
-        ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \
-        __udelay((n) * (19 * HZ)))
-
-#define ndelay(n) (__builtin_constant_p(n)? \
-        ((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \
-        __ndelay((n) * HZ))
-
-#endif /* defined(_PPC_DELAY_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/device.h b/include/asm-ppc/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-ppc/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h
deleted file mode 100644
index 7d9b3f430d92..000000000000
--- a/include/asm-ppc/floppy.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Architecture specific parts of the Floppy driver
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_FLOPPY_H
-#define __ASM_PPC_FLOPPY_H
-
-#define fd_inb(port)            inb_p(port)
-#define fd_outb(value,port)     outb_p(value,port)
-
-#define fd_disable_dma()        fd_ops->_disable_dma(FLOPPY_DMA)
-#define fd_free_dma()           fd_ops->_free_dma(FLOPPY_DMA)
-#define fd_get_dma_residue()    fd_ops->_get_dma_residue(FLOPPY_DMA)
-#define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io)
-#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
-#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
-#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
-
-static int fd_request_dma(void);
-
-struct fd_dma_ops {
-        void (*_disable_dma)(unsigned int dmanr);
-        void (*_free_dma)(unsigned int dmanr);
-        int (*_get_dma_residue)(unsigned int dummy);
-        int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
-};
-
-static int virtual_dma_count;
-static int virtual_dma_residue;
-static char *virtual_dma_addr;
-static int virtual_dma_mode;
-static int doing_vdma;
-static struct fd_dma_ops *fd_ops;
-
-static irqreturn_t floppy_hardint(int irq, void *dev_id)
-{
-        unsigned char st;
-        int lcount;
-        char *lptr;
-
-        if (!doing_vdma)
-                return floppy_interrupt(irq, dev_id);
-
-
-        st = 1;
-        for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
-             lcount; lcount--, lptr++) {
-                st=inb(virtual_dma_port+4) & 0xa0 ;
-                if (st != 0xa0)
-                        break;
-                if (virtual_dma_mode)
-                        outb_p(*lptr, virtual_dma_port+5);
-                else
-                        *lptr = inb_p(virtual_dma_port+5);
-        }
-        virtual_dma_count = lcount;
-        virtual_dma_addr = lptr;
-        st = inb(virtual_dma_port+4);
-
-        if (st == 0x20)
-                return IRQ_HANDLED;
-        if (!(st & 0x20)) {
-                virtual_dma_residue += virtual_dma_count;
-                virtual_dma_count=0;
-                doing_vdma = 0;
-                floppy_interrupt(irq, dev_id);
-                return IRQ_HANDLED;
-        }
-        return IRQ_HANDLED;
-}
-
-static void vdma_disable_dma(unsigned int dummy)
-{
-        doing_vdma = 0;
-        virtual_dma_residue += virtual_dma_count;
-        virtual_dma_count=0;
-}
-
-static void vdma_nop(unsigned int dummy)
-{
-}
-
-
-static int vdma_get_dma_residue(unsigned int dummy)
-{
-        return virtual_dma_count + virtual_dma_residue;
-}
-
-
-static int fd_request_irq(void)
-{
-        if (can_use_virtual_dma)
-                return request_irq(FLOPPY_IRQ, floppy_hardint,
-                                   IRQF_DISABLED, "floppy", NULL);
-        else
-                return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                                   IRQF_DISABLED, "floppy", NULL);
-}
-
-static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-        doing_vdma = 1;
-        virtual_dma_port = io;
-        virtual_dma_mode = (mode  == DMA_MODE_WRITE);
-        virtual_dma_addr = addr;
-        virtual_dma_count = size;
-        virtual_dma_residue = 0;
-        return 0;
-}
-
-static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-        /* actual, physical DMA */
-        doing_vdma = 0;
-        clear_dma_ff(FLOPPY_DMA);
-        set_dma_mode(FLOPPY_DMA,mode);
-        set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr));
-        set_dma_count(FLOPPY_DMA,size);
-        enable_dma(FLOPPY_DMA);
-        return 0;
-}
-
-static struct fd_dma_ops real_dma_ops =
-{
-        ._disable_dma = disable_dma,
-        ._free_dma = free_dma,
-        ._get_dma_residue = get_dma_residue,
-        ._dma_setup = hard_dma_setup
-};
-
-static struct fd_dma_ops virt_dma_ops =
-{
-        ._disable_dma = vdma_disable_dma,
-        ._free_dma = vdma_nop,
-        ._get_dma_residue = vdma_get_dma_residue,
-        ._dma_setup = vdma_dma_setup
-};
-
-static int fd_request_dma()
-{
-        if (can_use_virtual_dma & 1) {
-                fd_ops = &virt_dma_ops;
-                return 0;
-        }
-        else {
-                fd_ops = &real_dma_ops;
-                return request_dma(FLOPPY_DMA, "floppy");
-        }
-}
-
-static int FDC1 = 0x3f0;
-static int FDC2 = -1;
-
-/*
- * Again, the CMOS information not available
- */
-#define FLOPPY0_TYPE 6
-#define FLOPPY1_TYPE 0
-
-#define N_FDC 2                 /* Don't change this! */
-#define N_DRIVE 8
-
-/*
- * The PowerPC has no problems with floppy DMA crossing 64k borders.
- */
-#define CROSS_64KB(a,s) (0)
-
-#endif /* __ASM_PPC_FLOPPY_H */
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/fs_pd.h b/include/asm-ppc/fs_pd.h
deleted file mode 100644
index 8691327653af..000000000000
--- a/include/asm-ppc/fs_pd.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Platform information definitions.
- *
- * 2006 (c) MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef FS_PD_H
-#define FS_PD_H
-
-static inline int uart_baudrate(void)
-{
-        int baud;
-        bd_t *bd = (bd_t *) __res;
-
-        if (bd->bi_baudrate)
-                baud = bd->bi_baudrate;
-        else
-                baud = -1;
-        return baud;
-}
-
-static inline int uart_clock(void)
-{
-        return (((bd_t *) __res)->bi_intfreq);
-}
-
-#define cpm2_map(member)        (&cpm2_immr->member)
-#define cpm2_map_size(member, size)     (&cpm2_immr->member)
-#define cpm2_unmap(addr)        do {} while(0)
-
-#endif
diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h
deleted file mode 100644
index 341ae55b99fb..000000000000
--- a/include/asm-ppc/gg2.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- *  include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is based on the following documentation:
- *
- *      The VAS96011/12 Chipset, Data Book, Edition 1.0
- *      VLSI Technology, Inc.
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifndef _ASMPPC_GG2_H
-#define _ASMPPC_GG2_H
-
-    /*
-     *  Memory Map (CHRP mode)
-     */
-
-#define GG2_PCI_MEM_BASE        0xc0000000      /* Peripheral memory space */
-#define GG2_ISA_MEM_BASE        0xf7000000      /* Peripheral memory alias */
-#define GG2_ISA_IO_BASE         0xf8000000      /* Peripheral I/O space */
-#define GG2_PCI_CONFIG_BASE     0xfec00000      /* PCI configuration space */
-#define GG2_INT_ACK_SPECIAL     0xfec80000      /* Interrupt acknowledge and */
-                                                /* special PCI cycles */
-#define GG2_ROM_BASE0           0xff000000      /* ROM bank 0 */
-#define GG2_ROM_BASE1           0xff800000      /* ROM bank 1 */
-
-
-    /*
-     *  GG2 specific PCI Registers
-     */
-
-extern void __iomem *gg2_pci_config_base;       /* kernel virtual address */
-
-#define GG2_PCI_BUSNO           0x40    /* Bus number */
-#define GG2_PCI_SUBBUSNO        0x41    /* Subordinate bus number */
-#define GG2_PCI_DISCCTR         0x42    /* Disconnect counter */
-#define GG2_PCI_PPC_CTRL        0x50    /* PowerPC interface control register */
-#define GG2_PCI_ADDR_MAP        0x5c    /* Address map */
-#define GG2_PCI_PCI_CTRL        0x60    /* PCI interface control register */
-#define GG2_PCI_ROM_CTRL        0x70    /* ROM interface control register */
-#define GG2_PCI_ROM_TIME        0x74    /* ROM timing */
-#define GG2_PCI_CC_CTRL         0x80    /* Cache controller control register */
-#define GG2_PCI_DRAM_BANK0      0x90    /* Control register for DRAM bank #0 */
-#define GG2_PCI_DRAM_BANK1      0x94    /* Control register for DRAM bank #1 */
-#define GG2_PCI_DRAM_BANK2      0x98    /* Control register for DRAM bank #2 */
-#define GG2_PCI_DRAM_BANK3      0x9c    /* Control register for DRAM bank #3 */
-#define GG2_PCI_DRAM_BANK4      0xa0    /* Control register for DRAM bank #4 */
-#define GG2_PCI_DRAM_BANK5      0xa4    /* Control register for DRAM bank #5 */
-#define GG2_PCI_DRAM_TIME0      0xb0    /* Timing parameters set #0 */
-#define GG2_PCI_DRAM_TIME1      0xb4    /* Timing parameters set #1 */
-#define GG2_PCI_DRAM_CTRL       0xc0    /* DRAM control */
-#define GG2_PCI_ERR_CTRL        0xd0    /* Error control register */
-#define GG2_PCI_ERR_STATUS      0xd4    /* Error status register */
-                                        /* Cleared when read */
-
-#endif /* _ASMPPC_GG2_H */
diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h
deleted file mode 100644
index 9e63b3cfffca..000000000000
--- a/include/asm-ppc/gt64260.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * include/asm-ppc/gt64260.h
- *
- * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_GT64260_H
-#define __ASMPPC_GT64260_H
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/gt64260_defs.h>
-
-
-extern u32     gt64260_base;
-extern u32     gt64260_irq_base;     /* We handle the next 96 IRQs from here */
-extern u32     gt64260_revision;
-extern u8      gt64260_pci_exclude_bridge;
-
-#ifndef TRUE
-#define TRUE    1
-#endif
-
-#ifndef FALSE
-#define FALSE   0
-#endif
-
-/* IRQs defined by the 64260 */
-#define GT64260_IRQ_MPSC0               40
-#define GT64260_IRQ_MPSC1               42
-#define GT64260_IRQ_SDMA                36
-
-/*
- * Define a default physical memory map to be set up on the bridge.
- * Also define a struct to pass that info from board-specific routines to
- * GT64260 generic set up routines.  By passing this info in, the board
- * support developer can modify it at will.
- */
-
-/*
- * This is the default memory map:
- *                      CPU                     PCI
- *                      ---                     ---
- * PCI 0 I/O:   0xfa000000-0xfaffffff   0x00000000-0x00ffffff
- * PCI 1 I/O:   0xfb000000-0xfbffffff   0x01000000-0x01ffffff
- * PCI 0 MEM:   0x80000000-0x8fffffff   0x80000000-0x8fffffff
- * PCI 1 MEM:   0x90000000-0x9fffffff   0x90000000-0x9fffffff
- */
-
-/* Default physical memory map for the GT64260 bridge */
-
-/*
- * PCI Bus 0 Definitions
- */
-#define GT64260_PCI_0_IO_SIZE           0x01000000U
-#define GT64260_PCI_0_MEM_SIZE          0x10000000U
-
-/* Processor Physical addresses */
-#define GT64260_PCI_0_IO_START_PROC     0xfa000000U
-#define GT64260_PCI_0_IO_END_PROC       (GT64260_PCI_0_IO_START_PROC + \
-                                         GT64260_PCI_0_IO_SIZE - 1)
-
-/* PCI 0 addresses */
-#define GT64260_PCI_0_IO_START          0x00000000U
-#define GT64260_PCI_0_IO_END            (GT64260_PCI_0_IO_START + \
-                                         GT64260_PCI_0_IO_SIZE - 1)
-
-/* Processor Physical addresses */
-#define GT64260_PCI_0_MEM_START_PROC    0x80000000U
-#define GT64260_PCI_0_MEM_END_PROC      (GT64260_PCI_0_MEM_START_PROC + \
-                                         GT64260_PCI_0_MEM_SIZE - 1)
-
-/* PCI 0 addresses */
-#define GT64260_PCI_0_MEM_START         0x80000000U
-#define GT64260_PCI_0_MEM_END           (GT64260_PCI_0_MEM_START + \
-                                         GT64260_PCI_0_MEM_SIZE - 1)
-
-/*
- * PCI Bus 1 Definitions
- */
-#define GT64260_PCI_1_IO_SIZE           0x01000000U
-#define GT64260_PCI_1_MEM_SIZE          0x10000000U
-
-/* PCI 1 addresses */
-#define GT64260_PCI_1_IO_START          0x01000000U
-#define GT64260_PCI_1_IO_END            (GT64260_PCI_1_IO_START + \
-                                         GT64260_PCI_1_IO_SIZE - 1)
-
-/* Processor Physical addresses */
-#define GT64260_PCI_1_IO_START_PROC     0xfb000000U
-#define GT64260_PCI_1_IO_END_PROC       (GT64260_PCI_1_IO_START_PROC + \
-                                         GT64260_PCI_1_IO_SIZE - 1)
-
-/* PCI 1 addresses */
-#define GT64260_PCI_1_MEM_START         0x90000000U
-#define GT64260_PCI_1_MEM_END           (GT64260_PCI_1_MEM_START + \
-                                         GT64260_PCI_1_MEM_SIZE - 1)
-
-/* Processor Physical addresses */
-#define GT64260_PCI_1_MEM_START_PROC    0x90000000U
-#define GT64260_PCI_1_MEM_END_PROC      (GT64260_PCI_1_MEM_START_PROC + \
-                                         GT64260_PCI_1_MEM_SIZE - 1)
-
-/* Define struct to pass mem-map info into gt64260_common.c code */
-typedef struct {
-        struct pci_controller   *hose_a;
-        struct pci_controller   *hose_b;
-
-        u32     mem_size;
-
-        u32     pci_0_io_start_proc;
-        u32     pci_0_io_start_pci;
-        u32     pci_0_io_size;
-        u32     pci_0_io_swap;
-
-        u32     pci_0_mem_start_proc;
-        u32     pci_0_mem_start_pci_hi;
-        u32     pci_0_mem_start_pci_lo;
-        u32     pci_0_mem_size;
-        u32     pci_0_mem_swap;
-
-        u32     pci_1_io_start_proc;
-        u32     pci_1_io_start_pci;
-        u32     pci_1_io_size;
-        u32     pci_1_io_swap;
-
-        u32     pci_1_mem_start_proc;
-        u32     pci_1_mem_start_pci_hi;
-        u32     pci_1_mem_start_pci_lo;
-        u32     pci_1_mem_size;
-        u32     pci_1_mem_swap;
-} gt64260_bridge_info_t;
-
-#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) {                           \
-        (ip)->mem_size = (ms);                                          \
-                                                                        \
-        (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC;        \
-        (ip)->pci_0_io_start_pci  = GT64260_PCI_0_IO_START;             \
-        (ip)->pci_0_io_size       = GT64260_PCI_0_IO_SIZE;              \
-        (ip)->pci_0_io_swap       = GT64260_CPU_PCI_SWAP_NONE;          \
-                                                                        \
-        (ip)->pci_0_mem_start_proc   = GT64260_PCI_0_MEM_START_PROC;    \
-        (ip)->pci_0_mem_start_pci_hi = 0x00000000;                      \
-        (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START;         \
-        (ip)->pci_0_mem_size         = GT64260_PCI_0_MEM_SIZE;          \
-        (ip)->pci_0_mem_swap         = GT64260_CPU_PCI_SWAP_NONE;       \
-                                                                        \
-        (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC;        \
-        (ip)->pci_1_io_start_pci  = GT64260_PCI_1_IO_START;             \
-        (ip)->pci_1_io_size       = GT64260_PCI_1_IO_SIZE;              \
-        (ip)->pci_1_io_swap       = GT64260_CPU_PCI_SWAP_NONE;          \
-                                                                        \
-        (ip)->pci_1_mem_start_proc   = GT64260_PCI_1_MEM_START_PROC;    \
-        (ip)->pci_1_mem_start_pci_hi = 0x00000000;                      \
-        (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START;         \
-        (ip)->pci_1_mem_size         = GT64260_PCI_1_MEM_SIZE;          \
-        (ip)->pci_1_mem_swap         = GT64260_CPU_PCI_SWAP_NONE;       \
-}
-
-/*
- *****************************************************************************
- *
- *      I/O macros to access the 64260's registers
- *
- *****************************************************************************
- */
-
-extern inline uint32_t gt_read(uint32_t offs){
-        return (in_le32((volatile uint *)(gt64260_base + offs)));
-}
-extern inline void gt_write(uint32_t offs, uint32_t d){
-        out_le32((volatile uint *)(gt64260_base + offs), d);
-}
-
-#if 0 /* paranoid SMP version */
-extern inline void gt_modify(u32 offs, u32 data, u32 mask) \
-{
-        uint32_t reg;
-        spin_lock(&gt64260_lock);
-        reg = gt_read(offs) & (~mask); /* zero any bits we care about*/
-        reg |= data & mask; /* set bits from the data */
-        gt_write(offs, reg);
-        spin_unlock(&gt64260_lock);
-}
-#else
-extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask)
-{
-        uint32_t reg;
-        reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/
-        reg |= (data) & (mask); /* set bits from the data */
-        gt_write(offs, reg);
-}
-#endif
-#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
-
-#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
-
-
-/*
- *****************************************************************************
- *
- *      Function Prototypes
- *
- *****************************************************************************
- */
-
-int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
-        int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)));
-int gt64260_bridge_init(gt64260_bridge_info_t *info);
-int gt64260_cpu_scs_set_window(u32 window,
-                               u32 base_addr,
-                               u32 size);
-int gt64260_cpu_cs_set_window(u32 window,
-                              u32 base_addr,
-                              u32 size);
-int gt64260_cpu_boot_set_window(u32 base_addr,
-                                u32 size);
-int gt64260_cpu_set_pci_io_window(u32 pci_bus,
-                                  u32 cpu_base_addr,
-                                  u32 pci_base_addr,
-                                  u32 size,
-                                  u32 swap);
-int gt64260_cpu_set_pci_mem_window(u32 pci_bus,
-                                   u32 window,
-                                   u32 cpu_base_addr,
-                                   u32 pci_base_addr_hi,
-                                   u32 pci_base_addr_lo,
-                                   u32 size,
-                                   u32 swap_64bit);
-int gt64260_cpu_prot_set_window(u32 window,
-                                u32 base_addr,
-                                u32 size,
-                                u32 access_bits);
-int gt64260_cpu_snoop_set_window(u32 window,
-                                 u32 base_addr,
-                                 u32 size,
-                                 u32  snoop_type);
-void gt64260_cpu_disable_all_windows(void);
-int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits);
-int gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
-                                     u32 window,
-                                     u32 pci_base_addr,
-                                     u32 cpu_base_addr,
-                                     u32 size);
-int gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
-                                    u32 window,
-                                    u32 pci_base_addr,
-                                    u32 cpu_base_addr,
-                                    u32 size);
-int gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
-                                      u32 pci_base_addr,
-                                      u32 cpu_base_addr,
-                                      u32 size);
-int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
-                                         u32 window,
-                                         u32 pci_base_addr,
-                                         u32 other_bus_base_addr,
-                                         u32 size);
-int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
-                                        u32 pci_base_addr,
-                                        u32 other_bus_base_addr,
-                                        u32 size);
-int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
-                                         u32 window,
-                                         u32 pci_base_addr_hi,
-                                         u32 pci_base_addr_lo,
-                                         u32 cpu_base_addr,
-                                         u32 size);
-int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
-                                        u32 window,
-                                        u32 pci_base_addr_hi,
-                                        u32 pci_base_addr_lo,
-                                        u32 cpu_base_addr,
-                                        u32 size);
-int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
-                                          u32 pci_base_addr_hi,
-                                          u32 pci_base_addr_lo,
-                                          u32 cpu_base_addr,
-                                          u32 size);
-int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
-                                             u32 window,
-                                             u32 pci_base_addr_hi,
-                                             u32 pci_base_addr_lo,
-                                             u32 other_bus_base_addr,
-                                             u32 size);
-int gt64260_pci_acc_cntl_set_window(u32 pci_bus,
-                                    u32 window,
-                                    u32 base_addr_hi,
-                                    u32 base_addr_lo,
-                                    u32 size,
-                                    u32 features);
-int gt64260_pci_snoop_set_window(u32 pci_bus,
-                                 u32 window,
-                                 u32 base_addr_hi,
-                                 u32 base_addr_lo,
-                                 u32 size,
-                                 u32 snoop_type);
-int gt64260_set_base(u32 new_base);
-int gt64260_get_base(u32 *base);
-int gt64260_pci_exclude_device(u8 bus, u8 devfn);
-
-void gt64260_init_irq(void);
-int gt64260_get_irq(void);
-
-void gt64260_mpsc_progress(char *s, unsigned short hex);
-
-#endif /* __ASMPPC_GT64260_H */
diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h
deleted file mode 100644
index 6ffd01a5373e..000000000000
--- a/include/asm-ppc/gt64260_defs.h
+++ /dev/null
@@ -1,1010 +0,0 @@
-/*
- * include/asm-ppc/gt64260_defs.h
- *
- * Register definitions for the Marvell/Galileo GT64260 host bridge.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_GT64260_DEFS_H
-#define __ASMPPC_GT64260_DEFS_H
-
-/*
- * Define a macro to represent the supported version of the 64260.
- */
-#define GT64260                 0x01
-#define GT64260A                0x10
-
-/*
- *****************************************************************************
- *
- *      CPU Interface Registers
- *
- *****************************************************************************
- */
-
-/* CPU physical address of 64260's registers */
-#define GT64260_INTERNAL_SPACE_DECODE                   0x0068
-#define GT64260_INTERNAL_SPACE_SIZE                     0x10000
-#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR             0x14000000
-
-/* CPU Memory Controller Window Registers (4 windows) */
-#define GT64260_CPU_SCS_DECODE_WINDOWS                  4
-
-#define GT64260_CPU_SCS_DECODE_0_BOT                    0x0008
-#define GT64260_CPU_SCS_DECODE_0_TOP                    0x0010
-#define GT64260_CPU_SCS_DECODE_1_BOT                    0x0208
-#define GT64260_CPU_SCS_DECODE_1_TOP                    0x0210
-#define GT64260_CPU_SCS_DECODE_2_BOT                    0x0018
-#define GT64260_CPU_SCS_DECODE_2_TOP                    0x0020
-#define GT64260_CPU_SCS_DECODE_3_BOT                    0x0218
-#define GT64260_CPU_SCS_DECODE_3_TOP                    0x0220
-
-/* CPU Device Controller Window Registers (4 windows) */
-#define GT64260_CPU_CS_DECODE_WINDOWS                   4
-
-#define GT64260_CPU_CS_DECODE_0_BOT                     0x0028
-#define GT64260_CPU_CS_DECODE_0_TOP                     0x0030
-#define GT64260_CPU_CS_DECODE_1_BOT                     0x0228
-#define GT64260_CPU_CS_DECODE_1_TOP                     0x0230
-#define GT64260_CPU_CS_DECODE_2_BOT                     0x0248
-#define GT64260_CPU_CS_DECODE_2_TOP                     0x0250
-#define GT64260_CPU_CS_DECODE_3_BOT                     0x0038
-#define GT64260_CPU_CS_DECODE_3_TOP                     0x0040
-
-#define GT64260_CPU_BOOT_CS_DECODE_0_BOT                0x0238
-#define GT64260_CPU_BOOT_CS_DECODE_0_TOP                0x0240
-
-/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
-#define GT64260_PCI_BUSES                               2
-#define GT64260_PCI_IO_WINDOWS_PER_BUS                  1
-#define GT64260_PCI_MEM_WINDOWS_PER_BUS                 4
-
-#define GT64260_CPU_PCI_SWAP_BYTE                       0x00000000
-#define GT64260_CPU_PCI_SWAP_NONE                       0x01000000
-#define GT64260_CPU_PCI_SWAP_BYTE_WORD                  0x02000000
-#define GT64260_CPU_PCI_SWAP_WORD                       0x03000000
-#define GT64260_CPU_PCI_SWAP_MASK                       0x07000000
-
-#define GT64260_CPU_PCI_MEM_REQ64                       (1<<27)
-
-#define GT64260_CPU_PCI_0_IO_DECODE_BOT                 0x0048
-#define GT64260_CPU_PCI_0_IO_DECODE_TOP                 0x0050
-#define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT              0x0058
-#define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP              0x0060
-#define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT              0x0080
-#define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP              0x0088
-#define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT              0x0258
-#define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP              0x0260
-#define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT              0x0280
-#define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP              0x0288
-
-#define GT64260_CPU_PCI_0_IO_REMAP                      0x00f0
-#define GT64260_CPU_PCI_0_MEM_0_REMAP_LO                0x00f8
-#define GT64260_CPU_PCI_0_MEM_0_REMAP_HI                0x0320
-#define GT64260_CPU_PCI_0_MEM_1_REMAP_LO                0x0100
-#define GT64260_CPU_PCI_0_MEM_1_REMAP_HI                0x0328
-#define GT64260_CPU_PCI_0_MEM_2_REMAP_LO                0x02f8
-#define GT64260_CPU_PCI_0_MEM_2_REMAP_HI                0x0330
-#define GT64260_CPU_PCI_0_MEM_3_REMAP_LO                0x0300
-#define GT64260_CPU_PCI_0_MEM_3_REMAP_HI                0x0338
-
-#define GT64260_CPU_PCI_1_IO_DECODE_BOT                 0x0090
-#define GT64260_CPU_PCI_1_IO_DECODE_TOP                 0x0098
-#define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT              0x00a0
-#define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP              0x00a8
-#define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT              0x00b0
-#define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP              0x00b8
-#define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT              0x02a0
-#define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP              0x02a8
-#define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT              0x02b0
-#define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP              0x02b8
-
-#define GT64260_CPU_PCI_1_IO_REMAP                      0x0108
-#define GT64260_CPU_PCI_1_MEM_0_REMAP_LO                0x0110
-#define GT64260_CPU_PCI_1_MEM_0_REMAP_HI                0x0340
-#define GT64260_CPU_PCI_1_MEM_1_REMAP_LO                0x0118
-#define GT64260_CPU_PCI_1_MEM_1_REMAP_HI                0x0348
-#define GT64260_CPU_PCI_1_MEM_2_REMAP_LO                0x0310
-#define GT64260_CPU_PCI_1_MEM_2_REMAP_HI                0x0350
-#define GT64260_CPU_PCI_1_MEM_3_REMAP_LO                0x0318
-#define GT64260_CPU_PCI_1_MEM_3_REMAP_HI                0x0358
-
-/* CPU Control Registers */
-#define GT64260_CPU_CONFIG                              0x0000
-#define GT64260_CPU_MODE                                0x0120
-#define GT64260_CPU_MASTER_CNTL                         0x0160
-#define GT64260_CPU_XBAR_CNTL_LO                        0x0150
-#define GT64260_CPU_XBAR_CNTL_HI                        0x0158
-#define GT64260_CPU_XBAR_TO                             0x0168
-#define GT64260_CPU_RR_XBAR_CNTL_LO                     0x0170
-#define GT64260_CPU_RR_XBAR_CNTL_HI                     0x0178
-
-/* CPU Sync Barrier Registers */
-#define GT64260_CPU_SYNC_BARRIER_PCI_0                  0x00c0
-#define GT64260_CPU_SYNC_BARRIER_PCI_1                  0x00c8
-
-/* CPU Access Protection Registers */
-#define GT64260_CPU_PROT_WINDOWS                        8
-
-#define GT64260_CPU_PROT_ACCPROTECT                     (1<<16)
-#define GT64260_CPU_PROT_WRPROTECT                      (1<<17)
-#define GT64260_CPU_PROT_CACHEPROTECT                   (1<<18)
-
-#define GT64260_CPU_PROT_BASE_0                         0x0180
-#define GT64260_CPU_PROT_TOP_0                          0x0188
-#define GT64260_CPU_PROT_BASE_1                         0x0190
-#define GT64260_CPU_PROT_TOP_1                          0x0198
-#define GT64260_CPU_PROT_BASE_2                         0x01a0
-#define GT64260_CPU_PROT_TOP_2                          0x01a8
-#define GT64260_CPU_PROT_BASE_3                         0x01b0
-#define GT64260_CPU_PROT_TOP_3                          0x01b8
-#define GT64260_CPU_PROT_BASE_4                         0x01c0
-#define GT64260_CPU_PROT_TOP_4                          0x01c8
-#define GT64260_CPU_PROT_BASE_5                         0x01d0
-#define GT64260_CPU_PROT_TOP_5                          0x01d8
-#define GT64260_CPU_PROT_BASE_6                         0x01e0
-#define GT64260_CPU_PROT_TOP_6                          0x01e8
-#define GT64260_CPU_PROT_BASE_7                         0x01f0
-#define GT64260_CPU_PROT_TOP_7                          0x01f8
-
-/* CPU Snoop Control Registers */
-#define GT64260_CPU_SNOOP_WINDOWS                       4
-
-#define GT64260_CPU_SNOOP_NONE                          0x00000000
-#define GT64260_CPU_SNOOP_WT                            0x00010000
-#define GT64260_CPU_SNOOP_WB                            0x00020000
-#define GT64260_CPU_SNOOP_MASK                          0x00030000
-#define GT64260_CPU_SNOOP_ALL_BITS                      GT64260_CPU_SNOOP_MASK
-
-#define GT64260_CPU_SNOOP_BASE_0                        0x0380
-#define GT64260_CPU_SNOOP_TOP_0                         0x0388
-#define GT64260_CPU_SNOOP_BASE_1                        0x0390
-#define GT64260_CPU_SNOOP_TOP_1                         0x0398
-#define GT64260_CPU_SNOOP_BASE_2                        0x03a0
-#define GT64260_CPU_SNOOP_TOP_2                         0x03a8
-#define GT64260_CPU_SNOOP_BASE_3                        0x03b0
-#define GT64260_CPU_SNOOP_TOP_3                         0x03b8
-
-/* CPU Error Report Registers */
-#define GT64260_CPU_ERR_ADDR_LO                         0x0070
-#define GT64260_CPU_ERR_ADDR_HI                         0x0078
-#define GT64260_CPU_ERR_DATA_LO                         0x0128
-#define GT64260_CPU_ERR_DATA_HI                         0x0130
-#define GT64260_CPU_ERR_PARITY                          0x0138
-#define GT64260_CPU_ERR_CAUSE                           0x0140
-#define GT64260_CPU_ERR_MASK                            0x0148
-
-
-/*
- *****************************************************************************
- *
- *      SDRAM Cotnroller Registers
- *
- *****************************************************************************
- */
-
-/* SDRAM Config Registers */
-#define GT64260_SDRAM_CONFIG                            0x0448
-#define GT64260_SDRAM_OPERATION_MODE                    0x0474
-#define GT64260_SDRAM_ADDR_CNTL                         0x047c
-#define GT64260_SDRAM_TIMING_PARAMS                     0x04b4
-#define GT64260_SDRAM_UMA_CNTL                          0x04a4
-#define GT64260_SDRAM_XBAR_CNTL_LO                      0x04a8
-#define GT64260_SDRAM_XBAR_CNTL_HI                      0x04ac
-#define GT64260_SDRAM_XBAR_CNTL_TO                      0x04b0
-
-/* SDRAM Banks Parameters Registers */
-#define GT64260_SDRAM_BANK_PARAMS_0                     0x044c
-#define GT64260_SDRAM_BANK_PARAMS_1                     0x0450
-#define GT64260_SDRAM_BANK_PARAMS_2                     0x0454
-#define GT64260_SDRAM_BANK_PARAMS_3                     0x0458
-
-/* SDRAM Error Report Registers */
-#define GT64260_SDRAM_ERR_DATA_LO                       0x0484
-#define GT64260_SDRAM_ERR_DATA_HI                       0x0480
-#define GT64260_SDRAM_ERR_ADDR                          0x0490
-#define GT64260_SDRAM_ERR_ECC_RCVD                      0x0488
-#define GT64260_SDRAM_ERR_ECC_CALC                      0x048c
-#define GT64260_SDRAM_ERR_ECC_CNTL                      0x0494
-#define GT64260_SDRAM_ERR_ECC_ERR_CNT                   0x0498
-
-
-/*
- *****************************************************************************
- *
- *      Device/BOOT Cotnroller Registers
- *
- *****************************************************************************
- */
-
-/* Device Control Registers */
-#define GT64260_DEV_BANK_PARAMS_0                       0x045c
-#define GT64260_DEV_BANK_PARAMS_1                       0x0460
-#define GT64260_DEV_BANK_PARAMS_2                       0x0464
-#define GT64260_DEV_BANK_PARAMS_3                       0x0468
-#define GT64260_DEV_BOOT_PARAMS                         0x046c
-#define GT64260_DEV_IF_CNTL                             0x04c0
-#define GT64260_DEV_IF_XBAR_CNTL_LO                     0x04c8
-#define GT64260_DEV_IF_XBAR_CNTL_HI                     0x04cc
-#define GT64260_DEV_IF_XBAR_CNTL_TO                     0x04c4
-
-/* Device Interrupt Registers */
-#define GT64260_DEV_INTR_CAUSE                          0x04d0
-#define GT64260_DEV_INTR_MASK                           0x04d4
-#define GT64260_DEV_INTR_ERR_ADDR                       0x04d8
-
-
-/*
- *****************************************************************************
- *
- *      PCI Bridge Interface Registers
- *
- *****************************************************************************
- */
-
-/* PCI Configuration Access Registers */
-#define GT64260_PCI_0_CONFIG_ADDR                       0x0cf8
-#define GT64260_PCI_0_CONFIG_DATA                       0x0cfc
-#define GT64260_PCI_0_IACK                              0x0c34
-
-#define GT64260_PCI_1_CONFIG_ADDR                       0x0c78
-#define GT64260_PCI_1_CONFIG_DATA                       0x0c7c
-#define GT64260_PCI_1_IACK                              0x0cb4
-
-/* PCI Control Registers */
-#define GT64260_PCI_0_CMD                               0x0c00
-#define GT64260_PCI_0_MODE                              0x0d00
-#define GT64260_PCI_0_TO_RETRY                          0x0c04
-#define GT64260_PCI_0_RD_BUF_DISCARD_TIMER              0x0d04
-#define GT64260_PCI_0_MSI_TRIGGER_TIMER                 0x0c38
-#define GT64260_PCI_0_ARBITER_CNTL                      0x1d00
-#define GT64260_PCI_0_XBAR_CNTL_LO                      0x1d08
-#define GT64260_PCI_0_XBAR_CNTL_HI                      0x1d0c
-#define GT64260_PCI_0_XBAR_CNTL_TO                      0x1d04
-#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO              0x1d18
-#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI              0x1d1c
-#define GT64260_PCI_0_SYNC_BARRIER                      0x1d10
-#define GT64260_PCI_0_P2P_CONFIG                        0x1d14
-#define GT64260_PCI_0_P2P_SWAP_CNTL                     0x1d54
-
-#define GT64260_PCI_1_CMD                               0x0c80
-#define GT64260_PCI_1_MODE                              0x0d80
-#define GT64260_PCI_1_TO_RETRY                          0x0c84
-#define GT64260_PCI_1_RD_BUF_DISCARD_TIMER              0x0d84
-#define GT64260_PCI_1_MSI_TRIGGER_TIMER                 0x0cb8
-#define GT64260_PCI_1_ARBITER_CNTL                      0x1d80
-#define GT64260_PCI_1_XBAR_CNTL_LO                      0x1d88
-#define GT64260_PCI_1_XBAR_CNTL_HI                      0x1d8c
-#define GT64260_PCI_1_XBAR_CNTL_TO                      0x1d84
-#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO              0x1d98
-#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI              0x1d9c
-#define GT64260_PCI_1_SYNC_BARRIER                      0x1d90
-#define GT64260_PCI_1_P2P_CONFIG                        0x1d94
-#define GT64260_PCI_1_P2P_SWAP_CNTL                     0x1dd4
-
-/* PCI Access Control Regions Registers */
-#define GT64260_PCI_ACC_CNTL_WINDOWS                    8
-
-#define GT64260_PCI_ACC_CNTL_PREFETCHEN                 (1<<12)
-#define GT64260_PCI_ACC_CNTL_DREADEN                    (1<<13)
-#define GT64260_PCI_ACC_CNTL_RDPREFETCH                 (1<<16)
-#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH             (1<<17)
-#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH              (1<<18)
-#define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS             0x00000000
-#define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS             0x00100000
-#define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS            0x00200000
-#define GT64260_PCI_ACC_CNTL_MBURST_MASK                0x00300000
-#define GT64260_PCI_ACC_CNTL_SWAP_BYTE                  0x00000000
-#define GT64260_PCI_ACC_CNTL_SWAP_NONE                  0x01000000
-#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD             0x02000000
-#define GT64260_PCI_ACC_CNTL_SWAP_WORD                  0x03000000
-#define GT64260_PCI_ACC_CNTL_SWAP_MASK                  0x03000000
-#define GT64260_PCI_ACC_CNTL_ACCPROT                    (1<<28)
-#define GT64260_PCI_ACC_CNTL_WRPROT                     (1<<29)
-
-#define GT64260_PCI_ACC_CNTL_ALL_BITS   (GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
-                                         GT64260_PCI_ACC_CNTL_DREADEN |       \
-                                         GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
-                                         GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
-                                         GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
-                                         GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
-                                         GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
-                                         GT64260_PCI_ACC_CNTL_ACCPROT|        \
-                                         GT64260_PCI_ACC_CNTL_WRPROT)
-
-#define GT64260_PCI_0_ACC_CNTL_0_BASE_LO                0x1e00
-#define GT64260_PCI_0_ACC_CNTL_0_BASE_HI                0x1e04
-#define GT64260_PCI_0_ACC_CNTL_0_TOP                    0x1e08
-#define GT64260_PCI_0_ACC_CNTL_1_BASE_LO                0x1e10
-#define GT64260_PCI_0_ACC_CNTL_1_BASE_HI                0x1e14
-#define GT64260_PCI_0_ACC_CNTL_1_TOP                    0x1e18
-#define GT64260_PCI_0_ACC_CNTL_2_BASE_LO                0x1e20
-#define GT64260_PCI_0_ACC_CNTL_2_BASE_HI                0x1e24
-#define GT64260_PCI_0_ACC_CNTL_2_TOP                    0x1e28
-#define GT64260_PCI_0_ACC_CNTL_3_BASE_LO                0x1e30
-#define GT64260_PCI_0_ACC_CNTL_3_BASE_HI                0x1e34
-#define GT64260_PCI_0_ACC_CNTL_3_TOP                    0x1e38
-#define GT64260_PCI_0_ACC_CNTL_4_BASE_LO                0x1e40
-#define GT64260_PCI_0_ACC_CNTL_4_BASE_HI                0x1e44
-#define GT64260_PCI_0_ACC_CNTL_4_TOP                    0x1e48
-#define GT64260_PCI_0_ACC_CNTL_5_BASE_LO                0x1e50
-#define GT64260_PCI_0_ACC_CNTL_5_BASE_HI                0x1e54
-#define GT64260_PCI_0_ACC_CNTL_5_TOP                    0x1e58
-#define GT64260_PCI_0_ACC_CNTL_6_BASE_LO                0x1e60
-#define GT64260_PCI_0_ACC_CNTL_6_BASE_HI                0x1e64
-#define GT64260_PCI_0_ACC_CNTL_6_TOP                    0x1e68
-#define GT64260_PCI_0_ACC_CNTL_7_BASE_LO                0x1e70
-#define GT64260_PCI_0_ACC_CNTL_7_BASE_HI                0x1e74
-#define GT64260_PCI_0_ACC_CNTL_7_TOP                    0x1e78
-
-#define GT64260_PCI_1_ACC_CNTL_0_BASE_LO                0x1e80
-#define GT64260_PCI_1_ACC_CNTL_0_BASE_HI                0x1e84
-#define GT64260_PCI_1_ACC_CNTL_0_TOP                    0x1e88
-#define GT64260_PCI_1_ACC_CNTL_1_BASE_LO                0x1e90
-#define GT64260_PCI_1_ACC_CNTL_1_BASE_HI                0x1e94
-#define GT64260_PCI_1_ACC_CNTL_1_TOP                    0x1e98
-#define GT64260_PCI_1_ACC_CNTL_2_BASE_LO                0x1ea0
-#define GT64260_PCI_1_ACC_CNTL_2_BASE_HI                0x1ea4
-#define GT64260_PCI_1_ACC_CNTL_2_TOP                    0x1ea8
-#define GT64260_PCI_1_ACC_CNTL_3_BASE_LO                0x1eb0
-#define GT64260_PCI_1_ACC_CNTL_3_BASE_HI                0x1eb4
-#define GT64260_PCI_1_ACC_CNTL_3_TOP                    0x1eb8
-#define GT64260_PCI_1_ACC_CNTL_4_BASE_LO                0x1ec0
-#define GT64260_PCI_1_ACC_CNTL_4_BASE_HI                0x1ec4
-#define GT64260_PCI_1_ACC_CNTL_4_TOP                    0x1ec8
-#define GT64260_PCI_1_ACC_CNTL_5_BASE_LO                0x1ed0
-#define GT64260_PCI_1_ACC_CNTL_5_BASE_HI                0x1ed4
-#define GT64260_PCI_1_ACC_CNTL_5_TOP                    0x1ed8
-#define GT64260_PCI_1_ACC_CNTL_6_BASE_LO                0x1ee0
-#define GT64260_PCI_1_ACC_CNTL_6_BASE_HI                0x1ee4
-#define GT64260_PCI_1_ACC_CNTL_6_TOP                    0x1ee8
-#define GT64260_PCI_1_ACC_CNTL_7_BASE_LO                0x1ef0
-#define GT64260_PCI_1_ACC_CNTL_7_BASE_HI                0x1ef4
-#define GT64260_PCI_1_ACC_CNTL_7_TOP                    0x1ef8
-
-/* PCI Snoop Control Registers */
-#define GT64260_PCI_SNOOP_WINDOWS                       4
-
-#define GT64260_PCI_SNOOP_NONE                          0x00000000
-#define GT64260_PCI_SNOOP_WT                            0x00001000
-#define GT64260_PCI_SNOOP_WB                            0x00002000
-
-#define GT64260_PCI_0_SNOOP_0_BASE_LO                   0x1f00
-#define GT64260_PCI_0_SNOOP_0_BASE_HI                   0x1f04
-#define GT64260_PCI_0_SNOOP_0_TOP                       0x1f08
-#define GT64260_PCI_0_SNOOP_1_BASE_LO                   0x1f10
-#define GT64260_PCI_0_SNOOP_1_BASE_HI                   0x1f14
-#define GT64260_PCI_0_SNOOP_1_TOP                       0x1f18
-#define GT64260_PCI_0_SNOOP_2_BASE_LO                   0x1f20
-#define GT64260_PCI_0_SNOOP_2_BASE_HI                   0x1f24
-#define GT64260_PCI_0_SNOOP_2_TOP                       0x1f28
-#define GT64260_PCI_0_SNOOP_3_BASE_LO                   0x1f30
-#define GT64260_PCI_0_SNOOP_3_BASE_HI                   0x1f34
-#define GT64260_PCI_0_SNOOP_3_TOP                       0x1f38
-
-#define GT64260_PCI_1_SNOOP_0_BASE_LO                   0x1f80
-#define GT64260_PCI_1_SNOOP_0_BASE_HI                   0x1f84
-#define GT64260_PCI_1_SNOOP_0_TOP                       0x1f88
-#define GT64260_PCI_1_SNOOP_1_BASE_LO                   0x1f90
-#define GT64260_PCI_1_SNOOP_1_BASE_HI                   0x1f94
-#define GT64260_PCI_1_SNOOP_1_TOP                       0x1f98
-#define GT64260_PCI_1_SNOOP_2_BASE_LO                   0x1fa0
-#define GT64260_PCI_1_SNOOP_2_BASE_HI                   0x1fa4
-#define GT64260_PCI_1_SNOOP_2_TOP                       0x1fa8
-#define GT64260_PCI_1_SNOOP_3_BASE_LO                   0x1fb0
-#define GT64260_PCI_1_SNOOP_3_BASE_HI                   0x1fb4
-#define GT64260_PCI_1_SNOOP_3_TOP                       0x1fb8
-
-/* PCI Error Report Registers */
-#define GT64260_PCI_0_ERR_SERR_MASK                     0x0c28
-#define GT64260_PCI_0_ERR_ADDR_LO                       0x1d40
-#define GT64260_PCI_0_ERR_ADDR_HI                       0x1d44
-#define GT64260_PCI_0_ERR_DATA_LO                       0x1d48
-#define GT64260_PCI_0_ERR_DATA_HI                       0x1d4c
-#define GT64260_PCI_0_ERR_CMD                           0x1d50
-#define GT64260_PCI_0_ERR_CAUSE                         0x1d58
-#define GT64260_PCI_0_ERR_MASK                          0x1d5c
-
-#define GT64260_PCI_1_ERR_SERR_MASK                     0x0ca8
-#define GT64260_PCI_1_ERR_ADDR_LO                       0x1dc0
-#define GT64260_PCI_1_ERR_ADDR_HI                       0x1dc4
-#define GT64260_PCI_1_ERR_DATA_LO                       0x1dc8
-#define GT64260_PCI_1_ERR_DATA_HI                       0x1dcc
-#define GT64260_PCI_1_ERR_CMD                           0x1dd0
-#define GT64260_PCI_1_ERR_CAUSE                         0x1dd8
-#define GT64260_PCI_1_ERR_MASK                          0x1ddc
-
-/* PCI Slave Address Decoding Registers */
-#define GT64260_PCI_SCS_WINDOWS                         4
-#define GT64260_PCI_CS_WINDOWS                          4
-#define GT64260_PCI_BOOT_WINDOWS                        1
-#define GT64260_PCI_P2P_MEM_WINDOWS                     2
-#define GT64260_PCI_P2P_IO_WINDOWS                      1
-#define GT64260_PCI_DAC_SCS_WINDOWS                     4
-#define GT64260_PCI_DAC_CS_WINDOWS                      4
-#define GT64260_PCI_DAC_BOOT_WINDOWS                    1
-#define GT64260_PCI_DAC_P2P_MEM_WINDOWS                 2
-
-#define GT64260_PCI_0_SLAVE_SCS_0_SIZE                  0x0c08
-#define GT64260_PCI_0_SLAVE_SCS_1_SIZE                  0x0d08
-#define GT64260_PCI_0_SLAVE_SCS_2_SIZE                  0x0c0c
-#define GT64260_PCI_0_SLAVE_SCS_3_SIZE                  0x0d0c
-#define GT64260_PCI_0_SLAVE_CS_0_SIZE                   0x0c10
-#define GT64260_PCI_0_SLAVE_CS_1_SIZE                   0x0d10
-#define GT64260_PCI_0_SLAVE_CS_2_SIZE                   0x0d18
-#define GT64260_PCI_0_SLAVE_CS_3_SIZE                   0x0c14
-#define GT64260_PCI_0_SLAVE_BOOT_SIZE                   0x0d14
-#define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE              0x0d1c
-#define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE              0x0d20
-#define GT64260_PCI_0_SLAVE_P2P_IO_SIZE                 0x0d24
-#define GT64260_PCI_0_SLAVE_CPU_SIZE                    0x0d28
-
-#define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE              0x0e00
-#define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE              0x0e04
-#define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE              0x0e08
-#define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE              0x0e0c
-#define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE               0x0e10
-#define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE               0x0e14
-#define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE               0x0e18
-#define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE               0x0e1c
-#define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE               0x0e20
-#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE          0x0e24
-#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE          0x0e28
-#define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE                0x0e2c
-
-#define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE                0x0d2c
-
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0         (1<<0)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1         (1<<1)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2         (1<<2)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3         (1<<3)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0          (1<<4)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1          (1<<5)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2          (1<<6)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3          (1<<7)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT          (1<<8)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM       (1<<9)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO        (1<<10)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0     (1<<11)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1     (1<<12)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO        (1<<13)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU           (1<<14)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0     (1<<15)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1     (1<<16)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2     (1<<17)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3     (1<<18)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0      (1<<19)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1      (1<<20)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2      (1<<21)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3      (1<<22)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT      (1<<23)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25)
-#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU       (1<<26)
-
-#define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES             0x0c3c
-#define GT64260_PCI_0_SLAVE_SCS_0_REMAP                 0x0c48
-#define GT64260_PCI_0_SLAVE_SCS_1_REMAP                 0x0d48
-#define GT64260_PCI_0_SLAVE_SCS_2_REMAP                 0x0c4c
-#define GT64260_PCI_0_SLAVE_SCS_3_REMAP                 0x0d4c
-#define GT64260_PCI_0_SLAVE_CS_0_REMAP                  0x0c50
-#define GT64260_PCI_0_SLAVE_CS_1_REMAP                  0x0d50
-#define GT64260_PCI_0_SLAVE_CS_2_REMAP                  0x0d58
-#define GT64260_PCI_0_SLAVE_CS_3_REMAP                  0x0c54
-#define GT64260_PCI_0_SLAVE_BOOT_REMAP                  0x0d54
-#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO          0x0d5c
-#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI          0x0d60
-#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO          0x0d64
-#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI          0x0d68
-#define GT64260_PCI_0_SLAVE_P2P_IO_REMAP                0x0d6c
-#define GT64260_PCI_0_SLAVE_CPU_REMAP                   0x0d70
-
-#define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP             0x0f00
-#define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP             0x0f04
-#define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP             0x0f08
-#define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP             0x0f0c
-#define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP              0x0f10
-#define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP              0x0f14
-#define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP              0x0f18
-#define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP              0x0f1c
-#define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP              0x0f20
-#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO      0x0f24
-#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI      0x0f28
-#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO      0x0f2c
-#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI      0x0f30
-#define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP               0x0f34
-
-#define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP               0x0f38
-#define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL             0x0d3c
-
-#define GT64260_PCI_1_SLAVE_SCS_0_SIZE                  0x0c88
-#define GT64260_PCI_1_SLAVE_SCS_1_SIZE                  0x0d88
-#define GT64260_PCI_1_SLAVE_SCS_2_SIZE                  0x0c8c
-#define GT64260_PCI_1_SLAVE_SCS_3_SIZE                  0x0d8c
-#define GT64260_PCI_1_SLAVE_CS_0_SIZE                   0x0c90
-#define GT64260_PCI_1_SLAVE_CS_1_SIZE                   0x0d90
-#define GT64260_PCI_1_SLAVE_CS_2_SIZE                   0x0d98
-#define GT64260_PCI_1_SLAVE_CS_3_SIZE                   0x0c94
-#define GT64260_PCI_1_SLAVE_BOOT_SIZE                   0x0d94
-#define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE              0x0d9c
-#define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE              0x0da0
-#define GT64260_PCI_1_SLAVE_P2P_IO_SIZE                 0x0da4
-#define GT64260_PCI_1_SLAVE_CPU_SIZE                    0x0da8
-
-#define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE              0x0e80
-#define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE              0x0e84
-#define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE              0x0e88
-#define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE              0x0e8c
-#define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE               0x0e90
-#define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE               0x0e94
-#define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE               0x0e98
-#define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE               0x0e9c
-#define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE               0x0ea0
-#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE          0x0ea4
-#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE          0x0ea8
-#define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE                0x0eac
-
-#define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE                0x0dac
-
-#define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES             0x0cbc
-#define GT64260_PCI_1_SLAVE_SCS_0_REMAP                 0x0cc8
-#define GT64260_PCI_1_SLAVE_SCS_1_REMAP                 0x0dc8
-#define GT64260_PCI_1_SLAVE_SCS_2_REMAP                 0x0ccc
-#define GT64260_PCI_1_SLAVE_SCS_3_REMAP                 0x0dcc
-#define GT64260_PCI_1_SLAVE_CS_0_REMAP                  0x0cd0
-#define GT64260_PCI_1_SLAVE_CS_1_REMAP                  0x0dd0
-#define GT64260_PCI_1_SLAVE_CS_2_REMAP                  0x0dd8
-#define GT64260_PCI_1_SLAVE_CS_3_REMAP                  0x0cd4
-#define GT64260_PCI_1_SLAVE_BOOT_REMAP                  0x0dd4
-#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO          0x0ddc
-#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI          0x0de0
-#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO          0x0de4
-#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI          0x0de8
-#define GT64260_PCI_1_SLAVE_P2P_IO_REMAP                0x0dec
-#define GT64260_PCI_1_SLAVE_CPU_REMAP                   0x0df0
-
-#define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP             0x0f80
-#define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP             0x0f84
-#define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP             0x0f88
-#define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP             0x0f8c
-#define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP              0x0f90
-#define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP              0x0f94
-#define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP              0x0f98
-#define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP              0x0f9c
-#define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP              0x0fa0
-#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO      0x0fa4
-#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI      0x0fa8
-#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO      0x0fac
-#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI      0x0fb0
-#define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP               0x0fb4
-
-#define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP               0x0fb8
-#define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL             0x0dbc
-
-
-/*
- *****************************************************************************
- *
- *      I2O Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-
-/*
- *****************************************************************************
- *
- *      DMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-/*
- *****************************************************************************
- *
- *      Timer/Counter Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-/*
- *****************************************************************************
- *
- *      Communications Controller (Enet, Serial, etc.) Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_ENET_0_CNTL_LO                          0xf200
-#define GT64260_ENET_0_CNTL_HI                          0xf204
-#define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI               0xf208
-#define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI               0xf20c
-#define GT64260_ENET_0_RX_DESC_ADDR_HI                  0xf210
-#define GT64260_ENET_0_TX_DESC_ADDR_HI                  0xf214
-#define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI             0xf218
-#define GT64260_ENET_1_CNTL_LO                          0xf220
-#define GT64260_ENET_1_CNTL_HI                          0xf224
-#define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI               0xf228
-#define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI               0xf22c
-#define GT64260_ENET_1_RX_DESC_ADDR_HI                  0xf230
-#define GT64260_ENET_1_TX_DESC_ADDR_HI                  0xf234
-#define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI             0xf238
-#define GT64260_ENET_2_CNTL_LO                          0xf240
-#define GT64260_ENET_2_CNTL_HI                          0xf244
-#define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI               0xf248
-#define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI               0xf24c
-#define GT64260_ENET_2_RX_DESC_ADDR_HI                  0xf250
-#define GT64260_ENET_2_TX_DESC_ADDR_HI                  0xf254
-#define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI             0xf258
-
-#define GT64260_MPSC_0_CNTL_LO                          0xf280
-#define GT64260_MPSC_0_CNTL_HI                          0xf284
-#define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI               0xf288
-#define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI               0xf28c
-#define GT64260_MPSC_0_RX_DESC_ADDR_HI                  0xf290
-#define GT64260_MPSC_0_TX_DESC_ADDR_HI                  0xf294
-#define GT64260_MPSC_1_CNTL_LO                          0xf2c0
-#define GT64260_MPSC_1_CNTL_HI                          0xf2c4
-#define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI               0xf2c8
-#define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI               0xf2cc
-#define GT64260_MPSC_1_RX_DESC_ADDR_HI                  0xf2d0
-#define GT64260_MPSC_1_TX_DESC_ADDR_HI                  0xf2d4
-
-#define GT64260_SER_INIT_PCI_ADDR_HI                    0xf320
-#define GT64260_SER_INIT_LAST_DATA                      0xf324
-#define GT64260_SER_INIT_CONTROL                        0xf328
-#define GT64260_SER_INIT_STATUS                         0xf32c
-
-#define GT64260_COMM_ARBITER_CNTL                       0xf300
-#define GT64260_COMM_CONFIG                             0xb40c
-#define GT64260_COMM_XBAR_TO                            0xf304
-#define GT64260_COMM_INTR_CAUSE                         0xf310
-#define GT64260_COMM_INTR_MASK                          0xf314
-#define GT64260_COMM_ERR_ADDR                           0xf318
-
-
-/*
- *****************************************************************************
- *
- *      Fast Ethernet Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_ENET_PHY_ADDR                           0x2000
-#define GT64260_ENET_ESMIR                              0x2010
-
-#define GT64260_ENET_E0PCR                              0x2400
-#define GT64260_ENET_E0PCXR                             0x2408
-#define GT64260_ENET_E0PCMR                             0x2410
-#define GT64260_ENET_E0PSR                              0x2418
-#define GT64260_ENET_E0SPR                              0x2420
-#define GT64260_ENET_E0HTPR                             0x2428
-#define GT64260_ENET_E0FCSAL                            0x2430
-#define GT64260_ENET_E0FCSAH                            0x2438
-#define GT64260_ENET_E0SDCR                             0x2440
-#define GT64260_ENET_E0SDCMR                            0x2448
-#define GT64260_ENET_E0ICR                              0x2450
-#define GT64260_ENET_E0IMR                              0x2458
-#define GT64260_ENET_E0FRDP0                            0x2480
-#define GT64260_ENET_E0FRDP1                            0x2484
-#define GT64260_ENET_E0FRDP2                            0x2488
-#define GT64260_ENET_E0FRDP3                            0x248c
-#define GT64260_ENET_E0CRDP0                            0x24a0
-#define GT64260_ENET_E0CRDP1                            0x24a4
-#define GT64260_ENET_E0CRDP2                            0x24a8
-#define GT64260_ENET_E0CRDP3                            0x24ac
-#define GT64260_ENET_E0CTDP0                            0x24e0
-#define GT64260_ENET_E0CTDP1                            0x24e4
-#define GT64260_ENET_0_DSCP2P0L                         0x2460
-#define GT64260_ENET_0_DSCP2P0H                         0x2464
-#define GT64260_ENET_0_DSCP2P1L                         0x2468
-#define GT64260_ENET_0_DSCP2P1H                         0x246c
-#define GT64260_ENET_0_VPT2P                            0x2470
-#define GT64260_ENET_0_MIB_CTRS                         0x2500
-
-#define GT64260_ENET_E1PCR                              0x2800
-#define GT64260_ENET_E1PCXR                             0x2808
-#define GT64260_ENET_E1PCMR                             0x2810
-#define GT64260_ENET_E1PSR                              0x2818
-#define GT64260_ENET_E1SPR                              0x2820
-#define GT64260_ENET_E1HTPR                             0x2828
-#define GT64260_ENET_E1FCSAL                            0x2830
-#define GT64260_ENET_E1FCSAH                            0x2838
-#define GT64260_ENET_E1SDCR                             0x2840
-#define GT64260_ENET_E1SDCMR                            0x2848
-#define GT64260_ENET_E1ICR                              0x2850
-#define GT64260_ENET_E1IMR                              0x2858
-#define GT64260_ENET_E1FRDP0                            0x2880
-#define GT64260_ENET_E1FRDP1                            0x2884
-#define GT64260_ENET_E1FRDP2                            0x2888
-#define GT64260_ENET_E1FRDP3                            0x288c
-#define GT64260_ENET_E1CRDP0                            0x28a0
-#define GT64260_ENET_E1CRDP1                            0x28a4
-#define GT64260_ENET_E1CRDP2                            0x28a8
-#define GT64260_ENET_E1CRDP3                            0x28ac
-#define GT64260_ENET_E1CTDP0                            0x28e0
-#define GT64260_ENET_E1CTDP1                            0x28e4
-#define GT64260_ENET_1_DSCP2P0L                         0x2860
-#define GT64260_ENET_1_DSCP2P0H                         0x2864
-#define GT64260_ENET_1_DSCP2P1L                         0x2868
-#define GT64260_ENET_1_DSCP2P1H                         0x286c
-#define GT64260_ENET_1_VPT2P                            0x2870
-#define GT64260_ENET_1_MIB_CTRS                         0x2900
-
-#define GT64260_ENET_E2PCR                              0x2c00
-#define GT64260_ENET_E2PCXR                             0x2c08
-#define GT64260_ENET_E2PCMR                             0x2c10
-#define GT64260_ENET_E2PSR                              0x2c18
-#define GT64260_ENET_E2SPR                              0x2c20
-#define GT64260_ENET_E2HTPR                             0x2c28
-#define GT64260_ENET_E2FCSAL                            0x2c30
-#define GT64260_ENET_E2FCSAH                            0x2c38
-#define GT64260_ENET_E2SDCR                             0x2c40
-#define GT64260_ENET_E2SDCMR                            0x2c48
-#define GT64260_ENET_E2ICR                              0x2c50
-#define GT64260_ENET_E2IMR                              0x2c58
-#define GT64260_ENET_E2FRDP0                            0x2c80
-#define GT64260_ENET_E2FRDP1                            0x2c84
-#define GT64260_ENET_E2FRDP2                            0x2c88
-#define GT64260_ENET_E2FRDP3                            0x2c8c
-#define GT64260_ENET_E2CRDP0                            0x2ca0
-#define GT64260_ENET_E2CRDP1                            0x2ca4
-#define GT64260_ENET_E2CRDP2                            0x2ca8
-#define GT64260_ENET_E2CRDP3                            0x2cac
-#define GT64260_ENET_E2CTDP0                            0x2ce0
-#define GT64260_ENET_E2CTDP1                            0x2ce4
-#define GT64260_ENET_2_DSCP2P0L                         0x2c60
-#define GT64260_ENET_2_DSCP2P0H                         0x2c64
-#define GT64260_ENET_2_DSCP2P1L                         0x2c68
-#define GT64260_ENET_2_DSCP2P1H                         0x2c6c
-#define GT64260_ENET_2_VPT2P                            0x2c70
-#define GT64260_ENET_2_MIB_CTRS                         0x2d00
-
-
-/*
- *****************************************************************************
- *
- *      Multi-Protocol Serial Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* Signal Routing */
-#define GT64260_MPSC_MRR                                0xb400
-#define GT64260_MPSC_RCRR                               0xb404
-#define GT64260_MPSC_TCRR                               0xb408
-
-/* Main Configuratino Registers */
-#define GT64260_MPSC_0_MMCRL                            0x8000
-#define GT64260_MPSC_0_MMCRH                            0x8004
-#define GT64260_MPSC_0_MPCR                             0x8008
-#define GT64260_MPSC_0_CHR_1                            0x800c
-#define GT64260_MPSC_0_CHR_2                            0x8010
-#define GT64260_MPSC_0_CHR_3                            0x8014
-#define GT64260_MPSC_0_CHR_4                            0x8018
-#define GT64260_MPSC_0_CHR_5                            0x801c
-#define GT64260_MPSC_0_CHR_6                            0x8020
-#define GT64260_MPSC_0_CHR_7                            0x8024
-#define GT64260_MPSC_0_CHR_8                            0x8028
-#define GT64260_MPSC_0_CHR_9                            0x802c
-#define GT64260_MPSC_0_CHR_10                           0x8030
-#define GT64260_MPSC_0_CHR_11                           0x8034
-
-#define GT64260_MPSC_1_MMCRL                            0x9000
-#define GT64260_MPSC_1_MMCRH                            0x9004
-#define GT64260_MPSC_1_MPCR                             0x9008
-#define GT64260_MPSC_1_CHR_1                            0x900c
-#define GT64260_MPSC_1_CHR_2                            0x9010
-#define GT64260_MPSC_1_CHR_3                            0x9014
-#define GT64260_MPSC_1_CHR_4                            0x9018
-#define GT64260_MPSC_1_CHR_5                            0x901c
-#define GT64260_MPSC_1_CHR_6                            0x9020
-#define GT64260_MPSC_1_CHR_7                            0x9024
-#define GT64260_MPSC_1_CHR_8                            0x9028
-#define GT64260_MPSC_1_CHR_9                            0x902c
-#define GT64260_MPSC_1_CHR_10                           0x9030
-#define GT64260_MPSC_1_CHR_11                           0x9034
-
-#define GT64260_MPSC_0_INTR_CAUSE                       0xb804
-#define GT64260_MPSC_0_INTR_MASK                        0xb884
-#define GT64260_MPSC_1_INTR_CAUSE                       0xb80c
-#define GT64260_MPSC_1_INTR_MASK                        0xb88c
-
-#define GT64260_MPSC_UART_CR_TEV                        (1<<1)
-#define GT64260_MPSC_UART_CR_TA                         (1<<7)
-#define GT64260_MPSC_UART_CR_TTCS                       (1<<9)
-#define GT64260_MPSC_UART_CR_REV                        (1<<17)
-#define GT64260_MPSC_UART_CR_RA                         (1<<23)
-#define GT64260_MPSC_UART_CR_CRD                        (1<<25)
-#define GT64260_MPSC_UART_CR_EH                         (1<<31)
-
-#define GT64260_MPSC_UART_ESR_CTS                       (1<<0)
-#define GT64260_MPSC_UART_ESR_CD                        (1<<1)
-#define GT64260_MPSC_UART_ESR_TIDLE                     (1<<3)
-#define GT64260_MPSC_UART_ESR_RHS                       (1<<5)
-#define GT64260_MPSC_UART_ESR_RLS                       (1<<7)
-#define GT64260_MPSC_UART_ESR_RLIDL                     (1<<11)
-
-
-/*
- *****************************************************************************
- *
- *      Serial DMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_SDMA_0_SDC                              0x4000
-#define GT64260_SDMA_0_SDCM                             0x4008
-#define GT64260_SDMA_0_RX_DESC                          0x4800
-#define GT64260_SDMA_0_RX_BUF_PTR                       0x4808
-#define GT64260_SDMA_0_SCRDP                            0x4810
-#define GT64260_SDMA_0_TX_DESC                          0x4c00
-#define GT64260_SDMA_0_SCTDP                            0x4c10
-#define GT64260_SDMA_0_SFTDP                            0x4c14
-
-#define GT64260_SDMA_1_SDC                              0x6000
-#define GT64260_SDMA_1_SDCM                             0x6008
-#define GT64260_SDMA_1_RX_DESC                          0x6800
-#define GT64260_SDMA_1_RX_BUF_PTR                       0x6808
-#define GT64260_SDMA_1_SCRDP                            0x6810
-#define GT64260_SDMA_1_TX_DESC                          0x6c00
-#define GT64260_SDMA_1_SCTDP                            0x6c10
-#define GT64260_SDMA_1_SFTDP                            0x6c14
-
-#define GT64260_SDMA_INTR_CAUSE                         0xb800
-#define GT64260_SDMA_INTR_MASK                          0xb880
-
-#define GT64260_SDMA_DESC_CMDSTAT_PE                    (1<<0)
-#define GT64260_SDMA_DESC_CMDSTAT_CDL                   (1<<1)
-#define GT64260_SDMA_DESC_CMDSTAT_FR                    (1<<3)
-#define GT64260_SDMA_DESC_CMDSTAT_OR                    (1<<6)
-#define GT64260_SDMA_DESC_CMDSTAT_BR                    (1<<9)
-#define GT64260_SDMA_DESC_CMDSTAT_MI                    (1<<10)
-#define GT64260_SDMA_DESC_CMDSTAT_A                     (1<<11)
-#define GT64260_SDMA_DESC_CMDSTAT_AM                    (1<<12)
-#define GT64260_SDMA_DESC_CMDSTAT_CT                    (1<<13)
-#define GT64260_SDMA_DESC_CMDSTAT_C                     (1<<14)
-#define GT64260_SDMA_DESC_CMDSTAT_ES                    (1<<15)
-#define GT64260_SDMA_DESC_CMDSTAT_L                     (1<<16)
-#define GT64260_SDMA_DESC_CMDSTAT_F                     (1<<17)
-#define GT64260_SDMA_DESC_CMDSTAT_P                     (1<<18)
-#define GT64260_SDMA_DESC_CMDSTAT_EI                    (1<<23)
-#define GT64260_SDMA_DESC_CMDSTAT_O                     (1<<31)
-
-#define GT64260_SDMA_SDC_RFT                            (1<<0)
-#define GT64260_SDMA_SDC_SFM                            (1<<1)
-#define GT64260_SDMA_SDC_BLMR                           (1<<6)
-#define GT64260_SDMA_SDC_BLMT                           (1<<7)
-#define GT64260_SDMA_SDC_POVR                           (1<<8)
-#define GT64260_SDMA_SDC_RIFB                           (1<<9)
-
-#define GT64260_SDMA_SDCM_ERD                           (1<<7)
-#define GT64260_SDMA_SDCM_AR                            (1<<15)
-#define GT64260_SDMA_SDCM_STD                           (1<<16)
-#define GT64260_SDMA_SDCM_TXD                           (1<<23)
-#define GT64260_SDMA_SDCM_AT                            (1<<31)
-
-#define GT64260_SDMA_0_CAUSE_RXBUF                      (1<<0)
-#define GT64260_SDMA_0_CAUSE_RXERR                      (1<<1)
-#define GT64260_SDMA_0_CAUSE_TXBUF                      (1<<2)
-#define GT64260_SDMA_0_CAUSE_TXEND                      (1<<3)
-#define GT64260_SDMA_1_CAUSE_RXBUF                      (1<<8)
-#define GT64260_SDMA_1_CAUSE_RXERR                      (1<<9)
-#define GT64260_SDMA_1_CAUSE_TXBUF                      (1<<10)
-#define GT64260_SDMA_1_CAUSE_TXEND                      (1<<11)
-
-
-/*
- *****************************************************************************
- *
- *      Baud Rate Generator Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_BRG_0_BCR                               0xb200
-#define GT64260_BRG_0_BTR                               0xb204
-#define GT64260_BRG_1_BCR                               0xb208
-#define GT64260_BRG_1_BTR                               0xb20c
-#define GT64260_BRG_2_BCR                               0xb210
-#define GT64260_BRG_2_BTR                               0xb214
-
-#define GT64260_BRG_INTR_CAUSE                          0xb834
-#define GT64260_BRG_INTR_MASK                           0xb8b4
-
-
-/*
- *****************************************************************************
- *
- *      Watchdog Timer Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_WDT_WDC                                 0xb410
-#define GT64260_WDT_WDV                                 0xb414
-
-
-/*
- *****************************************************************************
- *
- *       General Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_GPP_IO_CNTL                             0xf100
-#define GT64260_GPP_LEVEL_CNTL                          0xf110
-#define GT64260_GPP_VALUE                               0xf104
-#define GT64260_GPP_INTR_CAUSE                          0xf108
-#define GT64260_GPP_INTR_MASK                           0xf10c
-
-
-/*
- *****************************************************************************
- *
- *      Multi-Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_MPP_CNTL_0                              0xf000
-#define GT64260_MPP_CNTL_1                              0xf004
-#define GT64260_MPP_CNTL_2                              0xf008
-#define GT64260_MPP_CNTL_3                              0xf00c
-#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX              0xf010
-
-
-/*
- *****************************************************************************
- *
- *      I2C Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-/*
- *****************************************************************************
- *
- *      Interrupt Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_IC_MAIN_CAUSE_LO                        0x0c18
-#define GT64260_IC_MAIN_CAUSE_HI                        0x0c68
-#define GT64260_IC_CPU_INTR_MASK_LO                     0x0c1c
-#define GT64260_IC_CPU_INTR_MASK_HI                     0x0c6c
-#define GT64260_IC_CPU_SELECT_CAUSE                     0x0c70
-#define GT64260_IC_PCI_0_INTR_MASK_LO                   0x0c24
-#define GT64260_IC_PCI_0_INTR_MASK_HI                   0x0c64
-#define GT64260_IC_PCI_0_SELECT_CAUSE                   0x0c74
-#define GT64260_IC_PCI_1_INTR_MASK_LO                   0x0ca4
-#define GT64260_IC_PCI_1_INTR_MASK_HI                   0x0ce4
-#define GT64260_IC_PCI_1_SELECT_CAUSE                   0x0cf4
-#define GT64260_IC_CPU_INT_0_MASK                       0x0e60
-#define GT64260_IC_CPU_INT_1_MASK                       0x0e64
-#define GT64260_IC_CPU_INT_2_MASK                       0x0e68
-#define GT64260_IC_CPU_INT_3_MASK                       0x0e6c
-
-
-#endif /* __ASMPPC_GT64260_DEFS_H */
diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h
deleted file mode 100644
index 7acd7fc126ec..000000000000
--- a/include/asm-ppc/harrier.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Definitions for Motorola MCG Harrier North Bridge & Memory controller
- *
- * Author: Dale Farnsworth
- *         dale.farnsworth@mvista.com
- *
- * Modified by: Randy Vinson
- *         rvinson@mvista.com
- *
- * Copyright 2001-2002 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASMPPC_HARRIER_H
-#define __ASMPPC_HARRIER_H
-
-#include <linux/types.h>
-#include <asm/pci-bridge.h>
-
-struct pci_controller;
-int harrier_init(struct pci_controller *hose,
-                 uint ppc_reg_base,
-                 ulong processor_pci_mem_start,
-                 ulong processor_pci_mem_end,
-                 ulong processor_pci_io_start,
-                 ulong processor_pci_io_end,
-                 ulong processor_mpic_base);
-
-unsigned long harrier_get_mem_size(uint smc_base);
-
-int harrier_mpic_init(unsigned int pci_mem_offset);
-
-void harrier_setup_nonmonarch(uint ppc_reg_base,
-                              uint in0_size);
-void harrier_release_eready(uint ppc_reg_base);
-
-void harrier_wait_eready(uint ppc_reg_base);
-
-#endif /* __ASMPPC_HARRIER_H */
diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h
deleted file mode 100644
index f347007d22af..000000000000
--- a/include/asm-ppc/hawk.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-ppc/hawk.h
- *
- * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * Modified by Randy Vinson (rvinson@mvista.com)
- *
- * 2001,2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASMPPC_HAWK_H
-#define __ASMPPC_HAWK_H
-
-#include <asm/pci-bridge.h>
-#include <asm/hawk_defs.h>
-
-extern int hawk_init(struct pci_controller *hose,
-              unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
-              unsigned long processor_pci_mem_end,
-              unsigned long processor_pci_io_start,
-              unsigned long processor_pci_io_end,
-              unsigned long processor_mpic_base);
-extern unsigned long hawk_get_mem_size(unsigned int smc_base);
-extern int hawk_mpic_init(unsigned int pci_mem_offset);
-
-#endif  /* __ASMPPC_HAWK_H */
diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h
deleted file mode 100644
index 6d1d2baf648c..000000000000
--- a/include/asm-ppc/hawk_defs.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * include/asm-ppc/hawk_defs.h
- *
- * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * Modified by Randy Vinson (rvinson@mvista.com)
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASMPPC_HAWK_DEFS_H
-#define __ASMPPC_HAWK_DEFS_H
-
-#include <asm/pci-bridge.h>
-
-/*
- * The Falcon/Raven and HAWK have 4 sets of registers:
- *   1) PPC Registers which define the mappings from PPC bus to PCI bus,
- *      etc.
- *   2) PCI Registers which define the mappings from PCI bus to PPC bus and the
- *      MPIC base address.
- *   3) MPIC registers
- *   4) System Memory Controller (SMC) registers.
- */
-
-#define HAWK_PCI_CONFIG_ADDR_OFF        0x00000cf8
-#define HAWK_PCI_CONFIG_DATA_OFF        0x00000cfc
-
-#define HAWK_MPIC_SIZE                  0x00040000U
-#define HAWK_SMC_SIZE                   0x00001000U
-
-/*
- * Define PPC register offsets.
- */
-#define HAWK_PPC_XSADD0_OFF                     0x40
-#define HAWK_PPC_XSOFF0_OFF                     0x44
-#define HAWK_PPC_XSADD1_OFF                     0x48
-#define HAWK_PPC_XSOFF1_OFF                     0x4c
-#define HAWK_PPC_XSADD2_OFF                     0x50
-#define HAWK_PPC_XSOFF2_OFF                     0x54
-#define HAWK_PPC_XSADD3_OFF                     0x58
-#define HAWK_PPC_XSOFF3_OFF                     0x5c
-
-/*
- * Define PCI register offsets.
- */
-#define HAWK_PCI_PSADD0_OFF                     0x80
-#define HAWK_PCI_PSOFF0_OFF                     0x84
-#define HAWK_PCI_PSADD1_OFF                     0x88
-#define HAWK_PCI_PSOFF1_OFF                     0x8c
-#define HAWK_PCI_PSADD2_OFF                     0x90
-#define HAWK_PCI_PSOFF2_OFF                     0x94
-#define HAWK_PCI_PSADD3_OFF                     0x98
-#define HAWK_PCI_PSOFF3_OFF                     0x9c
-
-/*
- * Define the System Memory Controller (SMC) register offsets.
- */
-#define HAWK_SMC_RAM_A_SIZE_REG_OFF             0x10
-#define HAWK_SMC_RAM_B_SIZE_REG_OFF             0x11
-#define HAWK_SMC_RAM_C_SIZE_REG_OFF             0x12
-#define HAWK_SMC_RAM_D_SIZE_REG_OFF             0x13
-#define HAWK_SMC_RAM_E_SIZE_REG_OFF             0xc0    /* HAWK Only */
-#define HAWK_SMC_RAM_F_SIZE_REG_OFF             0xc1    /* HAWK Only */
-#define HAWK_SMC_RAM_G_SIZE_REG_OFF             0xc2    /* HAWK Only */
-#define HAWK_SMC_RAM_H_SIZE_REG_OFF             0xc3    /* HAWK Only */
-
-#define FALCON_SMC_REG_COUNT                    4
-#define HAWK_SMC_REG_COUNT                      8
-#endif                          /* __ASMPPC_HAWK_DEFS_H */
diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h
deleted file mode 100644
index f7b21ee302b4..000000000000
--- a/include/asm-ppc/highmem.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * PowerPC version, stolen from the i386 version.
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- *                    Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terrabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <asm/kmap_types.h>
-#include <asm/tlbflush.h>
-#include <asm/page.h>
-
-/* undef for production */
-#define HIGHMEM_DEBUG 1
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define PKMAP_BASE      CONFIG_HIGHMEM_START
-#define LAST_PKMAP      (1 << PTE_SHIFT)
-#define LAST_PKMAP_MASK (LAST_PKMAP-1)
-#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-#define KMAP_FIX_BEGIN  (PKMAP_BASE + 0x00400000UL)
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-static inline void *kmap(struct page *page)
-{
-        might_sleep();
-        if (!PageHighMem(page))
-                return page_address(page);
-        return kmap_high(page);
-}
-
-static inline void kunmap(struct page *page)
-{
-        BUG_ON(in_interrupt());
-        if (!PageHighMem(page))
-                return;
-        kunmap_high(page);
-}
-
-/*
- * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
- * gives a more generic (and caching) interface. But kmap_atomic can
- * be used in IRQ contexts, so in some (very limited) cases we need
- * it.
- */
-static inline void *kmap_atomic(struct page *page, enum km_type type)
-{
-        unsigned int idx;
-        unsigned long vaddr;
-
-        /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
-        pagefault_disable();
-        if (!PageHighMem(page))
-                return page_address(page);
-
-        idx = type + KM_TYPE_NR*smp_processor_id();
-        vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
-#ifdef HIGHMEM_DEBUG
-        BUG_ON(!pte_none(*(kmap_pte+idx)));
-#endif
-        set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
-        flush_tlb_page(NULL, vaddr);
-
-        return (void*) vaddr;
-}
-
-static inline void kunmap_atomic(void *kvaddr, enum km_type type)
-{
-#ifdef HIGHMEM_DEBUG
-        unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
-        unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
-
-        if (vaddr < KMAP_FIX_BEGIN) { // FIXME
-                pagefault_enable();
-                return;
-        }
-
-        BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
-
-        /*
-         * force other mappings to Oops if they'll try to access
-         * this pte without first remap it
-         */
-        pte_clear(&init_mm, vaddr, kmap_pte+idx);
-        flush_tlb_page(NULL, vaddr);
-#endif
-        pagefault_enable();
-}
-
-static inline struct page *kmap_atomic_to_page(void *ptr)
-{
-        unsigned long idx, vaddr = (unsigned long) ptr;
-
-        if (vaddr < KMAP_FIX_BEGIN)
-                return virt_to_page(ptr);
-
-        idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
-        return pte_page(kmap_pte[idx]);
-}
-
-#define flush_cache_kmaps()     flush_cache_all()
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h
deleted file mode 100644
index 1ad4eed07fbe..000000000000
--- a/include/asm-ppc/hydra.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- *  include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is based on the following documentation:
- *
- *      Macintosh Technology in the Common Hardware Reference Platform
- *      Apple Computer, Inc.
- *
- *      © Copyright 1995 Apple Computer, Inc. All rights reserved.
- *
- *  It's available online from http://chrp.apple.com/MacTech.pdf.
- *  You can obtain paper copies of this book from computer bookstores or by
- *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
- *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifndef _ASMPPC_HYDRA_H
-#define _ASMPPC_HYDRA_H
-
-#ifdef __KERNEL__
-
-struct Hydra {
-    /* DBDMA Controller Register Space */
-    char Pad1[0x30];
-    u_int CachePD;
-    u_int IDs;
-    u_int Feature_Control;
-    char Pad2[0x7fc4];
-    /* DBDMA Channel Register Space */
-    char SCSI_DMA[0x100];
-    char Pad3[0x300];
-    char SCCA_Tx_DMA[0x100];
-    char SCCA_Rx_DMA[0x100];
-    char SCCB_Tx_DMA[0x100];
-    char SCCB_Rx_DMA[0x100];
-    char Pad4[0x7800];
-    /* Device Register Space */
-    char SCSI[0x1000];
-    char ADB[0x1000];
-    char SCC_Legacy[0x1000];
-    char SCC[0x1000];
-    char Pad9[0x2000];
-    char VIA[0x2000];
-    char Pad10[0x28000];
-    char OpenPIC[0x40000];
-};
-
-extern volatile struct Hydra __iomem *Hydra;
-
-
-    /*
-     *  Feature Control Register
-     */
-
-#define HYDRA_FC_SCC_CELL_EN    0x00000001      /* Enable SCC Clock */
-#define HYDRA_FC_SCSI_CELL_EN   0x00000002      /* Enable SCSI Clock */
-#define HYDRA_FC_SCCA_ENABLE    0x00000004      /* Enable SCC A Lines */
-#define HYDRA_FC_SCCB_ENABLE    0x00000008      /* Enable SCC B Lines */
-#define HYDRA_FC_ARB_BYPASS     0x00000010      /* Bypass Internal Arbiter */
-#define HYDRA_FC_RESET_SCC      0x00000020      /* Reset SCC */
-#define HYDRA_FC_MPIC_ENABLE    0x00000040      /* Enable OpenPIC */
-#define HYDRA_FC_SLOW_SCC_PCLK  0x00000080      /* 1=15.6672, 0=25 MHz */
-#define HYDRA_FC_MPIC_IS_MASTER 0x00000100      /* OpenPIC Master Mode */
-
-
-    /*
-     *  OpenPIC Interrupt Sources
-     */
-
-#define HYDRA_INT_SIO           0
-#define HYDRA_INT_SCSI_DMA      1
-#define HYDRA_INT_SCCA_TX_DMA   2
-#define HYDRA_INT_SCCA_RX_DMA   3
-#define HYDRA_INT_SCCB_TX_DMA   4
-#define HYDRA_INT_SCCB_RX_DMA   5
-#define HYDRA_INT_SCSI          6
-#define HYDRA_INT_SCCA          7
-#define HYDRA_INT_SCCB          8
-#define HYDRA_INT_VIA           9
-#define HYDRA_INT_ADB           10
-#define HYDRA_INT_ADB_NMI       11
-#define HYDRA_INT_EXT1          12      /* PCI IRQW */
-#define HYDRA_INT_EXT2          13      /* PCI IRQX */
-#define HYDRA_INT_EXT3          14      /* PCI IRQY */
-#define HYDRA_INT_EXT4          15      /* PCI IRQZ */
-#define HYDRA_INT_EXT5          16      /* IDE Primay/Secondary */
-#define HYDRA_INT_EXT6          17      /* IDE Secondary */
-#define HYDRA_INT_EXT7          18      /* Power Off Request */
-#define HYDRA_INT_SPARE         19
-
-extern int hydra_init(void);
-extern void macio_adb_init(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASMPPC_HYDRA_H */
diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h
deleted file mode 100644
index c9c5d539cfdb..000000000000
--- a/include/asm-ppc/ibm403.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/*
- * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM403_H__
-#define __ASM_IBM403_H__
-
-
-#if defined(CONFIG_403GCX)
-
-#define DCRN_BE_BASE            0x090
-#define DCRN_DMA0_BASE          0x0C0
-#define DCRN_DMA1_BASE          0x0C8
-#define DCRN_DMA2_BASE          0x0D0
-#define DCRN_DMA3_BASE          0x0D8
-#define DCRNCAP_DMA_CC          1       /* have DMA chained count capability */
-#define DCRN_DMASR_BASE         0x0E0
-
-#define DCRN_EXIER_BASE         0x042
-#define DCRN_EXISR_BASE         0x040
-#define DCRN_IOCR_BASE          0x0A0
-
-
-/* ------------------------------------------------------------------------- */
-#endif
-
-
-
-#ifdef DCRN_BE_BASE
-#define DCRN_BEAR       (DCRN_BE_BASE + 0x0)    /* Bus Error Address Register */
-#define DCRN_BESR       (DCRN_BE_BASE + 0x1)    /* Bus Error Syndrome Register*/
-#endif
-/* DCRN_BESR */
-#define BESR_DSES       0x80000000      /* Data-Side Error Status */
-#define BESR_DMES       0x40000000      /* DMA Error Status */
-#define BESR_RWS        0x20000000      /* Read/Write Status */
-#define BESR_ETMASK     0x1C000000      /* Error Type */
-#define ET_PROT 0
-#define ET_PARITY       1
-#define ET_NCFG 2
-#define ET_BUSERR       4
-#define ET_BUSTO        6
-
-#ifdef DCRN_CHCR_BASE
-#define DCRN_CHCR0      (DCRN_CHCR_BASE + 0x0)  /* Chip Control Register 1 */
-#define DCRN_CHCR1      (DCRN_CHCR_BASE + 0x1)  /* Chip Control Register 2 */
-#endif
-#define CHR1_CETE       0x00800000               /* CPU external timer enable */
-#define CHR1_PCIPW      0x00008000 /* PCI Int enable/Peripheral Write enable */
-
-#ifdef DCRN_CHPSR_BASE
-#define DCRN_CHPSR      (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
-#endif
-
-#ifdef DCRN_CIC_BASE
-#define DCRN_CICCR      (DCRN_CIC_BASE + 0x0)   /* CIC Control Register */
-#define DCRN_DMAS1      (DCRN_CIC_BASE + 0x1)   /* DMA Select1 Register */
-#define DCRN_DMAS2      (DCRN_CIC_BASE + 0x2)   /* DMA Select2 Register */
-#define DCRN_CICVCR     (DCRN_CIC_BASE + 0x3)   /* CIC Video COntro Register */
-#define DCRN_CICSEL3    (DCRN_CIC_BASE + 0x5)   /* CIC Select 3 Register */
-#define DCRN_SGPO       (DCRN_CIC_BASE + 0x6)   /* CIC GPIO Output Register */
-#define DCRN_SGPOD      (DCRN_CIC_BASE + 0x7)   /* CIC GPIO OD Register */
-#define DCRN_SGPTC      (DCRN_CIC_BASE + 0x8)   /* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI       (DCRN_CIC_BASE + 0x9)   /* CIC GPIO Input Reg */
-#endif
-
-#ifdef DCRN_CPMFR_BASE
-#define DCRN_CPMFR      (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
-#endif
-
-#ifndef CPM_AUD
-#define CPM_AUD         0x00000000
-#endif
-#ifndef CPM_BRG
-#define CPM_BRG         0x00000000
-#endif
-#ifndef CPM_CBS
-#define CPM_CBS         0x00000000
-#endif
-#ifndef CPM_CPU
-#define CPM_CPU         0x00000000
-#endif
-#ifndef CPM_DCP
-#define CPM_DCP         0x00000000
-#endif
-#ifndef CPM_DCRX
-#define CPM_DCRX        0x00000000
-#endif
-#ifndef CPM_DENC
-#define CPM_DENC        0x00000000
-#endif
-#ifndef CPM_DMA
-#define CPM_DMA         0x00000000
-#endif
-#ifndef CPM_DSCR
-#define CPM_DSCR        0x00000000
-#endif
-#ifndef CPM_EBC
-#define CPM_EBC         0x00000000
-#endif
-#ifndef CPM_EBIU
-#define CPM_EBIU        0x00000000
-#endif
-#ifndef CPM_EMAC_MM
-#define CPM_EMAC_MM     0x00000000
-#endif
-#ifndef CPM_EMAC_RM
-#define CPM_EMAC_RM     0x00000000
-#endif
-#ifndef CPM_EMAC_TM
-#define CPM_EMAC_TM     0x00000000
-#endif
-#ifndef CPM_GPIO0
-#define CPM_GPIO0       0x00000000
-#endif
-#ifndef CPM_GPT
-#define CPM_GPT         0x00000000
-#endif
-#ifndef CPM_I1284
-#define CPM_I1284       0x00000000
-#endif
-#ifndef CPM_IIC0
-#define CPM_IIC0        0x00000000
-#endif
-#ifndef CPM_IIC1
-#define CPM_IIC1        0x00000000
-#endif
-#ifndef CPM_MSI
-#define CPM_MSI         0x00000000
-#endif
-#ifndef CPM_PCI
-#define CPM_PCI         0x00000000
-#endif
-#ifndef CPM_PLB
-#define CPM_PLB         0x00000000
-#endif
-#ifndef CPM_SC0
-#define CPM_SC0         0x00000000
-#endif
-#ifndef CPM_SC1
-#define CPM_SC1         0x00000000
-#endif
-#ifndef CPM_SDRAM0
-#define CPM_SDRAM0      0x00000000
-#endif
-#ifndef CPM_SDRAM1
-#define CPM_SDRAM1      0x00000000
-#endif
-#ifndef CPM_TMRCLK
-#define CPM_TMRCLK      0x00000000
-#endif
-#ifndef CPM_UART0
-#define CPM_UART0       0x00000000
-#endif
-#ifndef CPM_UART1
-#define CPM_UART1       0x00000000
-#endif
-#ifndef CPM_UART2
-#define CPM_UART2       0x00000000
-#endif
-#ifndef CPM_UIC
-#define CPM_UIC         0x00000000
-#endif
-#ifndef CPM_VID2
-#define CPM_VID2        0x00000000
-#endif
-#ifndef CPM_XPT27
-#define CPM_XPT27       0x00000000
-#endif
-#ifndef CPM_XPT54
-#define CPM_XPT54       0x00000000
-#endif
-
-#ifdef DCRN_CPMSR_BASE
-#define DCRN_CPMSR      (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
-#define DCRN_CPMER      (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
-#endif
-
-#ifdef DCRN_DCP0_BASE
-#define DCRN_DCP0_CFGADDR       (DCRN_DCP0_BASE + 0x0)  /* Decompression Controller Address */
-#define DCRN_DCP0_CFGDATA       (DCRN_DCP0_BASE + 0x1)  /* Decompression Controller Data */
-#endif
-
-#ifdef DCRN_DCRX_BASE
-#define DCRN_DCRXICR    (DCRN_DCRX_BASE + 0x0)  /* Internal Control Register */
-#define DCRN_DCRXISR    (DCRN_DCRX_BASE + 0x1)  /* Internal Status Register */
-#define DCRN_DCRXECR    (DCRN_DCRX_BASE + 0x2)  /* External Control Register */
-#define DCRN_DCRXESR    (DCRN_DCRX_BASE + 0x3)  /* External Status Register */
-#define DCRN_DCRXTAR    (DCRN_DCRX_BASE + 0x4)  /* Target Address Register */
-#define DCRN_DCRXTDR    (DCRN_DCRX_BASE + 0x5)  /* Target Data Register */
-#define DCRN_DCRXIGR    (DCRN_DCRX_BASE + 0x6)  /* Interrupt Generation Register */
-#define DCRN_DCRXBCR    (DCRN_DCRX_BASE + 0x7)  /* Line Buffer Control Register */
-#endif
-
-#ifdef DCRN_DMA0_BASE
-#define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)  /* DMA Channel Control Register 0 */
-#define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count Register 0 */
-#define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x2)  /* DMA Destination Address Register 0 */
-#define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)  /* DMA Source Address Register 0 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC0     (DCRN_DMA0_BASE + 0x4)  /* DMA Chained Count Register 0 */
-#endif
-
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG0       (DCRN_DMA0_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 0 */
-#endif
-#endif
-
-#ifdef DCRN_DMA1_BASE
-#define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)  /* DMA Channel Control Register 1 */
-#define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count Register 1 */
-#define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x2)  /* DMA Destination Address Register 1 */
-#define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Source Address Register 1 */
-
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC1     (DCRN_DMA1_BASE + 0x4)  /* DMA Chained Count Register 1 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG1       (DCRN_DMA1_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 1 */
-#endif
-#endif
-
-#ifdef DCRN_DMA2_BASE
-#define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control Register 2 */
-#define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count Register 2 */
-#define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x2)  /* DMA Destination Address Register 2 */
-#define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Source Address Register 2 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC2     (DCRN_DMA2_BASE + 0x4)  /* DMA Chained Count Register 2 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG2       (DCRN_DMA2_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 2 */
-#endif
-#endif
-
-#ifdef DCRN_DMA3_BASE
-#define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control Register 3 */
-#define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count Register 3 */
-#define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x2)  /* DMA Destination Address Register 3 */
-#define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Source Address Register 3 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC3     (DCRN_DMA3_BASE + 0x4)  /* DMA Chained Count Register 3 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG3       (DCRN_DMA3_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 3 */
-#endif
-#endif
-
-#ifdef DCRN_DMASR_BASE
-#define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
-/* don't know if these two registers always exist if scatter/gather exists */
-#define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
-#define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
-#endif
-#endif
-
-#ifdef DCRN_EBC_BASE
-#define DCRN_EBCCFGADR  (DCRN_EBC_BASE + 0x0)   /* Peripheral Controller Address */
-#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1)   /* Peripheral Controller Data */
-#endif
-
-#ifdef DCRN_EXIER_BASE
-#define DCRN_EXIER      (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
-#endif
-
-#ifdef DCRN_EBIMC_BASE
-#define DCRN_BRCRH0     (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
-#define DCRN_BRCRH1     (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
-#define DCRN_BRCRH2     (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
-#define DCRN_BRCRH3     (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
-#define DCRN_BRCRH4     (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
-#define DCRN_BRCRH5     (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
-#define DCRN_BRCRH6     (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
-#define DCRN_BRCRH7     (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
-#define DCRN_BRCR0      (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */
-#define DCRN_BRCR1      (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */
-#define DCRN_BRCR2      (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */
-#define DCRN_BRCR3      (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */
-#define DCRN_BRCR4      (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */
-#define DCRN_BRCR5      (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */
-#define DCRN_BRCR6      (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */
-#define DCRN_BRCR7      (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */
-#define DCRN_BEAR0      (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */
-#define DCRN_BESR0      (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */
-#define DCRN_BIUCR      (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */
-#endif
-
-#ifdef DCRN_EXISR_BASE
-#define DCRN_EXISR      (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
-#endif
-#define EXIER_CIE       0x80000000      /* Critical Interrupt Enable */
-#define EXIER_SRIE      0x08000000      /* Serial Port Rx Int. Enable */
-#define EXIER_STIE      0x04000000      /* Serial Port Tx Int. Enable */
-#define EXIER_JRIE      0x02000000      /* JTAG Serial Port Rx Int. Enable */
-#define EXIER_JTIE      0x01000000      /* JTAG Serial Port Tx Int. Enable */
-#define EXIER_D0IE      0x00800000      /* DMA Channel 0 Interrupt Enable */
-#define EXIER_D1IE      0x00400000      /* DMA Channel 1 Interrupt Enable */
-#define EXIER_D2IE      0x00200000      /* DMA Channel 2 Interrupt Enable */
-#define EXIER_D3IE      0x00100000      /* DMA Channel 3 Interrupt Enable */
-#define EXIER_E0IE      0x00000010      /* External Interrupt 0 Enable */
-#define EXIER_E1IE      0x00000008      /* External Interrupt 1 Enable */
-#define EXIER_E2IE      0x00000004      /* External Interrupt 2 Enable */
-#define EXIER_E3IE      0x00000002      /* External Interrupt 3 Enable */
-#define EXIER_E4IE      0x00000001      /* External Interrupt 4 Enable */
-
-#ifdef DCRN_IOCR_BASE
-#define DCRN_IOCR       (DCRN_IOCR_BASE + 0x0)  /* Input/Output Configuration Register */
-#endif
-#define IOCR_E0TE       0x80000000
-#define IOCR_E0LP       0x40000000
-#define IOCR_E1TE       0x20000000
-#define IOCR_E1LP       0x10000000
-#define IOCR_E2TE       0x08000000
-#define IOCR_E2LP       0x04000000
-#define IOCR_E3TE       0x02000000
-#define IOCR_E3LP       0x01000000
-#define IOCR_E4TE       0x00800000
-#define IOCR_E4LP       0x00400000
-#define IOCR_EDT        0x00080000
-#define IOCR_SOR        0x00040000
-#define IOCR_EDO        0x00008000
-#define IOCR_2XC        0x00004000
-#define IOCR_ATC        0x00002000
-#define IOCR_SPD        0x00001000
-#define IOCR_BEM        0x00000800
-#define IOCR_PTD        0x00000400
-#define IOCR_ARE        0x00000080
-#define IOCR_DRC        0x00000020
-#define IOCR_RDM(x)     (((x) & 0x3) << 3)
-#define IOCR_TCS        0x00000004
-#define IOCR_SCS        0x00000002
-#define IOCR_SPC        0x00000001
-
-#ifdef DCRN_MAL_BASE
-#define DCRN_MALCR              (DCRN_MAL_BASE + 0x0) /* MAL Configuration */
-#define DCRN_MALDBR             (DCRN_MAL_BASE + 0x3) /* Debug Register */
-#define DCRN_MALESR             (DCRN_MAL_BASE + 0x1) /* Error Status */
-#define DCRN_MALIER             (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */
-#define DCRN_MALTXCARR          (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */
-#define DCRN_MALTXCASR          (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */
-#define DCRN_MALTXDEIR          (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */
-#define DCRN_MALTXEOBISR        (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status  */
-#define DCRN_MALRXCARR          (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */
-#define DCRN_MALRXCASR          (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */
-#define DCRN_MALRXDEIR          (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */
-#define DCRN_MALRXEOBISR        (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status  */
-#define DCRN_MALRXCTP0R         (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP0R         (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R         (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0           (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */
-#endif
-/* DCRN_MALCR */
-#define MALCR_MMSR              0x80000000/* MAL Software reset */
-#define MALCR_PLBP_1            0x00400000 /* MAL reqest priority: */
-#define MALCR_PLBP_2            0x00800000 /* lowsest is 00 */
-#define MALCR_PLBP_3            0x00C00000 /* highest */
-#define MALCR_GA                0x00200000 /* Guarded Active Bit */
-#define MALCR_OA                0x00100000 /* Ordered Active Bit */
-#define MALCR_PLBLE             0x00080000 /* PLB Lock Error Bit */
-#define MALCR_PLBLT_1           0x00040000 /* PLB Latency Timer */
-#define MALCR_PLBLT_2           0x00020000
-#define MALCR_PLBLT_3           0x00010000
-#define MALCR_PLBLT_4           0x00008000
-#define MALCR_PLBLT_DEFAULT     0x00078000 /* JSP: Is this a valid default?? */
-#define MALCR_PLBB              0x00004000 /* PLB Burst Deactivation Bit */
-#define MALCR_OPBBL             0x00000080 /* OPB Lock Bit */
-#define MALCR_EOPIE             0x00000004 /* End Of Packet Interrupt Enable */
-#define MALCR_LEA               0x00000002 /* Locked Error Active */
-#define MALCR_MSD               0x00000001 /* MAL Scroll Descriptor Bit */
-/* DCRN_MALESR */
-#define MALESR_EVB              0x80000000 /* Error Valid Bit */
-#define MALESR_CIDRX            0x40000000 /* Channel ID Receive */
-#define MALESR_DE               0x00100000 /* Descriptor Error */
-#define MALESR_OEN              0x00080000 /* OPB Non-Fullword Error */
-#define MALESR_OTE              0x00040000 /* OPB Timeout Error */
-#define MALESR_OSE              0x00020000 /* OPB Slave Error */
-#define MALESR_PEIN             0x00010000 /* PLB Bus Error Indication */
-#define MALESR_DEI              0x00000010 /* Descriptor Error Interrupt */
-#define MALESR_ONEI             0x00000008 /* OPB Non-Fullword Error Interrupt */
-#define MALESR_OTEI             0x00000004 /* OPB Timeout Error Interrupt */
-#define MALESR_OSEI             0x00000002 /* OPB Slace Error Interrupt */
-#define MALESR_PBEI             0x00000001 /* PLB Bus Error Interrupt */
-/* DCRN_MALIER */
-#define MALIER_DE               0x00000010 /* Descriptor Error Interrupt Enable */
-#define MALIER_NE               0x00000008 /* OPB Non-word Transfer Int Enable */
-#define MALIER_TE               0x00000004 /* OPB Time Out Error Interrupt Enable  */
-#define MALIER_OPBE             0x00000002 /* OPB Slave Error Interrupt Enable */
-#define MALIER_PLBE             0x00000001 /* PLB Error Interrupt Enable */
-/* DCRN_MALTXEOBISR */
-#define MALOBISR_CH0            0x80000000 /* EOB channel 1 bit */
-#define MALOBISR_CH2            0x40000000 /* EOB channel 2 bit */
-
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0)  /* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1)  /* OCM Instr Side Control */
-#define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2)  /* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3)  /* OCM Data Side Control */
-#endif
-
-#ifdef DCRN_PLB0_BASE
-#define DCRN_PLB0_BESR  (DCRN_PLB0_BASE + 0x0)
-#define DCRN_PLB0_BEAR  (DCRN_PLB0_BASE + 0x2)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB0_ACR   (DCRN_PLB0_BASE + 0x3)
-#endif
-
-#ifdef DCRN_PLB1_BASE
-#define DCRN_PLB1_BESR  (DCRN_PLB1_BASE + 0x0)
-#define DCRN_PLB1_BEAR  (DCRN_PLB1_BASE + 0x1)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB1_ACR   (DCRN_PLB1_BASE + 0x2)
-#endif
-
-#ifdef DCRN_PLLMR_BASE
-#define DCRN_PLLMR      (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
-#endif
-
-#ifdef DCRN_POB0_BASE
-#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
-#define DCRN_POB0_BEAR  (DCRN_POB0_BASE + 0x2)
-#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
-#endif
-
-#ifdef DCRN_SCCR_BASE
-#define DCRN_SCCR       (DCRN_SCCR_BASE + 0x0)
-#endif
-
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */
-#define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */
-#endif
-
-#ifdef DCRN_UIC0_BASE
-#define DCRN_UIC0_SR    (DCRN_UIC0_BASE + 0x0)
-#define DCRN_UIC0_ER    (DCRN_UIC0_BASE + 0x2)
-#define DCRN_UIC0_CR    (DCRN_UIC0_BASE + 0x3)
-#define DCRN_UIC0_PR    (DCRN_UIC0_BASE + 0x4)
-#define DCRN_UIC0_TR    (DCRN_UIC0_BASE + 0x5)
-#define DCRN_UIC0_MSR   (DCRN_UIC0_BASE + 0x6)
-#define DCRN_UIC0_VR    (DCRN_UIC0_BASE + 0x7)
-#define DCRN_UIC0_VCR   (DCRN_UIC0_BASE + 0x8)
-#endif
-
-#ifdef DCRN_UIC1_BASE
-#define DCRN_UIC1_SR    (DCRN_UIC1_BASE + 0x0)
-#define DCRN_UIC1_SRS   (DCRN_UIC1_BASE + 0x1)
-#define DCRN_UIC1_ER    (DCRN_UIC1_BASE + 0x2)
-#define DCRN_UIC1_CR    (DCRN_UIC1_BASE + 0x3)
-#define DCRN_UIC1_PR    (DCRN_UIC1_BASE + 0x4)
-#define DCRN_UIC1_TR    (DCRN_UIC1_BASE + 0x5)
-#define DCRN_UIC1_MSR   (DCRN_UIC1_BASE + 0x6)
-#define DCRN_UIC1_VR    (DCRN_UIC1_BASE + 0x7)
-#define DCRN_UIC1_VCR   (DCRN_UIC1_BASE + 0x8)
-#endif
-
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
-#define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
-#endif
-
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
-#define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
-#endif
-
-#endif /* __ASM_IBM403_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h
deleted file mode 100644
index 4e5be9e2c153..000000000000
--- a/include/asm-ppc/ibm405.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405_H__
-#define __ASM_IBM405_H__
-
-#ifdef DCRN_BE_BASE
-#define DCRN_BEAR       (DCRN_BE_BASE + 0x0)    /* Bus Error Address Register */
-#define DCRN_BESR       (DCRN_BE_BASE + 0x1)    /* Bus Error Syndrome Register */
-#endif
-/* DCRN_BESR */
-#define BESR_DSES       0x80000000      /* Data-Side Error Status */
-#define BESR_DMES       0x40000000      /* DMA Error Status */
-#define BESR_RWS        0x20000000      /* Read/Write Status */
-#define BESR_ETMASK     0x1C000000      /* Error Type */
-#define ET_PROT 0
-#define ET_PARITY       1
-#define ET_NCFG 2
-#define ET_BUSERR       4
-#define ET_BUSTO        6
-
-/* Clock and power management shifts for emacs */
-#define IBM_CPM_EMMII   0       /* Shift value for MII */
-#define IBM_CPM_EMRX    1       /* Shift value for recv */
-#define IBM_CPM_EMTX    2       /* Shift value for MAC */
-
-#ifdef DCRN_CHCR_BASE
-#define DCRN_CHCR0      (DCRN_CHCR_BASE + 0x0)  /* Chip Control Register 1 */
-#define DCRN_CHCR1      (DCRN_CHCR_BASE + 0x1)  /* Chip Control Register 2 */
-#endif
-#define CHR1_PCIPW      0x00008000      /* PCI Int enable/Peripheral Write enable */
-
-#ifdef DCRN_CHPSR_BASE
-#define DCRN_CHPSR      (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
-#endif
-
-#ifdef DCRN_CPMFR_BASE
-#define DCRN_CPMFR      (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
-#endif
-
-#ifdef DCRN_CPMSR_BASE
-#define DCRN_CPMSR      (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
-#define DCRN_CPMER      (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
-#endif
-
-#ifdef DCRN_DCP0_BASE
-/* Decompression Controller Address */
-#define DCRN_DCP0_CFGADDR       (DCRN_DCP0_BASE + 0x0)
-/* Decompression Controller Data */
-#define DCRN_DCP0_CFGDATA       (DCRN_DCP0_BASE + 0x1)
-#else
-#define DCRN_DCP0_CFGADDR       0x0
-#define DCRN_DCP0_CFGDATA       0x0
-#endif
-
-#ifdef DCRN_DMA0_BASE
-/* DMA Channel Control Register 0 */
-#define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)
-#define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count Register 0 */
-/* DMA Destination Address Register 0 */
-#define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x2)
-/* DMA Source Address Register 0 */
-#define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)
-#ifdef DCRNCAP_DMA_CC
-/* DMA Chained Count Register 0 */
-#define DCRN_DMACC0     (DCRN_DMA0_BASE + 0x4)
-#endif
-#ifdef DCRNCAP_DMA_SG
-/* DMA Scatter/Gather Descriptor Addr 0 */
-#define DCRN_ASG0       (DCRN_DMA0_BASE + 0x4)
-#endif
-#endif
-
-#ifdef DCRN_DMA1_BASE
-/* DMA Channel Control Register 1 */
-#define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)
-#define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count Register 1 */
-/* DMA Destination Address Register 1 */
-#define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x2)
-/* DMA Source Address Register 1 */
-#define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Source Address Register 1 */
-#ifdef DCRNCAP_DMA_CC
-/* DMA Chained Count Register 1 */
-#define DCRN_DMACC1     (DCRN_DMA1_BASE + 0x4)
-#endif
-#ifdef DCRNCAP_DMA_SG
-/* DMA Scatter/Gather Descriptor Addr 1 */
-#define DCRN_ASG1       (DCRN_DMA1_BASE + 0x4)
-#endif
-#endif
-
-#ifdef DCRN_DMA2_BASE
-#define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control Register 2 */
-#define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count Register 2 */
-#define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x2)  /* DMA Destination Address Register 2 */
-#define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Source Address Register 2 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC2     (DCRN_DMA2_BASE + 0x4)  /* DMA Chained Count Register 2 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG2       (DCRN_DMA2_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 2 */
-#endif
-#endif
-
-#ifdef DCRN_DMA3_BASE
-#define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control Register 3 */
-#define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count Register 3 */
-#define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x2)  /* DMA Destination Address Register 3 */
-#define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Source Address Register 3 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC3     (DCRN_DMA3_BASE + 0x4)  /* DMA Chained Count Register 3 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG3       (DCRN_DMA3_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 3 */
-#endif
-#endif
-
-#ifdef DCRN_DMASR_BASE
-#define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
-/* don't know if these two registers always exist if scatter/gather exists */
-#define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
-#define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
-#endif
-#endif
-
-#ifdef DCRN_EBC_BASE
-#define DCRN_EBCCFGADR  (DCRN_EBC_BASE + 0x0)   /* Peripheral Controller Address */
-#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1)   /* Peripheral Controller Data */
-#endif
-
-#ifdef DCRN_EXIER_BASE
-#define DCRN_EXIER      (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
-#endif
-
-#ifdef DCRN_EXISR_BASE
-#define DCRN_EXISR      (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
-#endif
-
-#define EXIER_CIE       0x80000000      /* Critical Interrupt Enable */
-#define EXIER_SRIE      0x08000000      /* Serial Port Rx Int. Enable */
-#define EXIER_STIE      0x04000000      /* Serial Port Tx Int. Enable */
-#define EXIER_JRIE      0x02000000      /* JTAG Serial Port Rx Int. Enable */
-#define EXIER_JTIE      0x01000000      /* JTAG Serial Port Tx Int. Enable */
-#define EXIER_D0IE      0x00800000      /* DMA Channel 0 Interrupt Enable */
-#define EXIER_D1IE      0x00400000      /* DMA Channel 1 Interrupt Enable */
-#define EXIER_D2IE      0x00200000      /* DMA Channel 2 Interrupt Enable */
-#define EXIER_D3IE      0x00100000      /* DMA Channel 3 Interrupt Enable */
-#define EXIER_E0IE      0x00000010      /* External Interrupt 0 Enable */
-#define EXIER_E1IE      0x00000008      /* External Interrupt 1 Enable */
-#define EXIER_E2IE      0x00000004      /* External Interrupt 2 Enable */
-#define EXIER_E3IE      0x00000002      /* External Interrupt 3 Enable */
-#define EXIER_E4IE      0x00000001      /* External Interrupt 4 Enable */
-
-#ifdef DCRN_IOCR_BASE
-#define DCRN_IOCR       (DCRN_IOCR_BASE + 0x0)  /* Input/Output Configuration Register */
-#endif
-#define IOCR_E0TE       0x80000000
-#define IOCR_E0LP       0x40000000
-#define IOCR_E1TE       0x20000000
-#define IOCR_E1LP       0x10000000
-#define IOCR_E2TE       0x08000000
-#define IOCR_E2LP       0x04000000
-#define IOCR_E3TE       0x02000000
-#define IOCR_E3LP       0x01000000
-#define IOCR_E4TE       0x00800000
-#define IOCR_E4LP       0x00400000
-#define IOCR_EDT        0x00080000
-#define IOCR_SOR        0x00040000
-#define IOCR_EDO        0x00008000
-#define IOCR_2XC        0x00004000
-#define IOCR_ATC        0x00002000
-#define IOCR_SPD        0x00001000
-#define IOCR_BEM        0x00000800
-#define IOCR_PTD        0x00000400
-#define IOCR_ARE        0x00000080
-#define IOCR_DRC        0x00000020
-#define IOCR_RDM(x)     (((x) & 0x3) << 3)
-#define IOCR_TCS        0x00000004
-#define IOCR_SCS        0x00000002
-#define IOCR_SPC        0x00000001
-
-#define DCRN_MALCR(base)        (base + 0x0)    /* MAL Configuration */
-#define DCRN_MALDBR(base)       ((base) + 0x3)  /* Debug Register */
-#define DCRN_MALESR(base)       ((base) + 0x1)  /* Error Status */
-#define DCRN_MALIER(base)       ((base) + 0x2)  /* Interrupt Enable */
-#define DCRN_MALTXCARR(base)    ((base) + 0x5)  /* TX Channed Active Reset Register */
-#define DCRN_MALTXCASR(base)    ((base) + 0x4)  /* TX Channel Active Set Register */
-#define DCRN_MALTXDEIR(base)    ((base) + 0x7)  /* Tx Descriptor Error Interrupt */
-#define DCRN_MALTXEOBISR(base)  ((base) + 0x6)  /* Tx End of Buffer Interrupt Status */
-#define DCRN_MALRXCARR(base)    ((base) + 0x11) /* RX Channed Active Reset Register */
-#define DCRN_MALRXCASR(base)    ((base) + 0x10) /* RX Channel Active Set Register */
-#define DCRN_MALRXDEIR(base)    ((base) + 0x13) /* Rx Descriptor Error Interrupt */
-#define DCRN_MALRXEOBISR(base)  ((base) + 0x12) /* Rx End of Buffer Interrupt Status */
-#define DCRN_MALRXCTP0R(base)   ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALRXCTP1R(base)   ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */
-#define DCRN_MALTXCTP0R(base)   ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R(base)   ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALTXCTP2R(base)   ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */
-#define DCRN_MALTXCTP3R(base)   ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */
-#define DCRN_MALRCBS0(base)     ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */
-#define DCRN_MALRCBS1(base)     ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */
-
- /* DCRN_MALCR */
-#define MALCR_MMSR              0x80000000      /* MAL Software reset */
-#define MALCR_PLBP_1            0x00400000      /* MAL reqest priority: */
-#define MALCR_PLBP_2            0x00800000      /* lowsest is 00 */
-#define MALCR_PLBP_3            0x00C00000      /* highest */
-#define MALCR_GA                0x00200000      /* Guarded Active Bit */
-#define MALCR_OA                0x00100000      /* Ordered Active Bit */
-#define MALCR_PLBLE             0x00080000      /* PLB Lock Error Bit */
-#define MALCR_PLBLT_1           0x00040000      /* PLB Latency Timer */
-#define MALCR_PLBLT_2           0x00020000
-#define MALCR_PLBLT_3           0x00010000
-#define MALCR_PLBLT_4           0x00008000
-#define MALCR_PLBLT_DEFAULT     0x00078000      /* JSP: Is this a valid default?? */
-#define MALCR_PLBB              0x00004000      /* PLB Burst Deactivation Bit */
-#define MALCR_OPBBL             0x00000080      /* OPB Lock Bit */
-#define MALCR_EOPIE             0x00000004      /* End Of Packet Interrupt Enable */
-#define MALCR_LEA               0x00000002      /* Locked Error Active */
-#define MALCR_MSD               0x00000001      /* MAL Scroll Descriptor Bit */
-/* DCRN_MALESR */
-#define MALESR_EVB              0x80000000      /* Error Valid Bit */
-#define MALESR_CIDRX            0x40000000      /* Channel ID Receive */
-#define MALESR_DE               0x00100000      /* Descriptor Error */
-#define MALESR_OEN              0x00080000      /* OPB Non-Fullword Error */
-#define MALESR_OTE              0x00040000      /* OPB Timeout Error */
-#define MALESR_OSE              0x00020000      /* OPB Slave Error */
-#define MALESR_PEIN             0x00010000      /* PLB Bus Error Indication */
-#define MALESR_DEI              0x00000010      /* Descriptor Error Interrupt */
-#define MALESR_ONEI             0x00000008      /* OPB Non-Fullword Error Interrupt */
-#define MALESR_OTEI             0x00000004      /* OPB Timeout Error Interrupt */
-#define MALESR_OSEI             0x00000002      /* OPB Slace Error Interrupt */
-#define MALESR_PBEI             0x00000001      /* PLB Bus Error Interrupt */
-/* DCRN_MALIER */
-#define MALIER_DE               0x00000010      /* Descriptor Error Interrupt Enable */
-#define MALIER_NE               0x00000008      /* OPB Non-word Transfer Int Enable */
-#define MALIER_TE               0x00000004      /* OPB Time Out Error Interrupt Enable */
-#define MALIER_OPBE             0x00000002      /* OPB Slave Error Interrupt Enable */
-#define MALIER_PLBE             0x00000001      /* PLB Error Interrupt Enable */
-/* DCRN_MALTXEOBISR */
-#define MALOBISR_CH0            0x80000000      /* EOB channel 1 bit */
-#define MALOBISR_CH2            0x40000000      /* EOB channel 2 bit */
-
-#ifdef DCRN_PLB0_BASE
-#define DCRN_PLB0_BESR  (DCRN_PLB0_BASE + 0x0)
-#define DCRN_PLB0_BEAR  (DCRN_PLB0_BASE + 0x2)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB0_ACR   (DCRN_PLB0_BASE + 0x3)
-#endif
-
-#ifdef DCRN_PLB1_BASE
-#define DCRN_PLB1_BESR  (DCRN_PLB1_BASE + 0x0)
-#define DCRN_PLB1_BEAR  (DCRN_PLB1_BASE + 0x1)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB1_ACR   (DCRN_PLB1_BASE + 0x2)
-#endif
-
-#ifdef DCRN_PLLMR_BASE
-#define DCRN_PLLMR      (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
-#endif
-
-#ifdef DCRN_POB0_BASE
-#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
-#define DCRN_POB0_BEAR  (DCRN_POB0_BASE + 0x2)
-#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
-#endif
-
-#define DCRN_UIC_SR(base)       (base + 0x0)
-#define DCRN_UIC_ER(base)       (base + 0x2)
-#define DCRN_UIC_CR(base)       (base + 0x3)
-#define DCRN_UIC_PR(base)       (base + 0x4)
-#define DCRN_UIC_TR(base)       (base + 0x5)
-#define DCRN_UIC_MSR(base)      (base + 0x6)
-#define DCRN_UIC_VR(base)       (base + 0x7)
-#define DCRN_UIC_VCR(base)      (base + 0x8)
-
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0)        /* Memory Controller Address */
-#define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1)        /* Memory Controller Data */
-#endif
-
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0)  /* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1)  /* OCM Instr Side Control */
-#define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2)  /* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3)  /* OCM Data Side Control */
-#endif
-
-#endif                          /* __ASM_IBM405_H__ */
-#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
deleted file mode 100644
index 7818b54b6e37..000000000000
--- a/include/asm-ppc/ibm44x.h
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- * include/asm-ppc/ibm44x.h
- *
- * PPC44x definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM44x_H__
-#define __ASM_IBM44x_H__
-
-
-#ifndef NR_BOARD_IRQS
-#define NR_BOARD_IRQS 0
-#endif
-
-#define _IO_BASE        isa_io_base
-#define _ISA_MEM_BASE   isa_mem_base
-#define PCI_DRAM_OFFSET pci_dram_offset
-
-/* TLB entry offset/size used for pinning kernel lowmem */
-#define PPC44x_PIN_SHIFT        28
-#define PPC_PIN_SIZE            (1 << PPC44x_PIN_SHIFT)
-
-/* Lowest TLB slot consumed by the default pinned TLBs */
-#define PPC44x_LOW_SLOT         63
-
-/*
- * Least significant 32-bits and extended real page number (ERPN) of
- * UART0 physical address location for early serial text debug
- */
-#if defined(CONFIG_440SP)
-#define UART0_PHYS_ERPN         1
-#define UART0_PHYS_IO_BASE      0xf0000200
-#elif defined(CONFIG_440SPE)
-#define UART0_PHYS_ERPN         4
-#define UART0_PHYS_IO_BASE      0xf0000200
-#elif defined(CONFIG_440EP)
-#define UART0_PHYS_IO_BASE      0xe0000000
-#else
-#define UART0_PHYS_ERPN         1
-#define UART0_PHYS_IO_BASE      0x40000200
-#endif
-
-/*
- * XXX This 36-bit trap stuff will move somewhere in syslib/
- * when we rework/abstract the PPC44x PCI-X handling -mdp
- */
-
-/*
- * Standard 4GB "page" definitions
- */
-#if defined(CONFIG_440SP)
-#define PPC44x_IO_PAGE          0x0000000100000000ULL
-#define PPC44x_PCICFG_PAGE      0x0000000900000000ULL
-#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
-#define PPC44x_PCIMEM_PAGE      0x0000000a00000000ULL
-#elif defined(CONFIG_440SPE)
-#define PPC44x_IO_PAGE          0x0000000400000000ULL
-#define PPC44x_PCICFG_PAGE      0x0000000c00000000ULL
-#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
-#define PPC44x_PCIMEM_PAGE      0x0000000d00000000ULL
-#elif defined(CONFIG_440EP)
-#define PPC44x_IO_PAGE          0x0000000000000000ULL
-#define PPC44x_PCICFG_PAGE      0x0000000000000000ULL
-#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
-#define PPC44x_PCIMEM_PAGE      0x0000000000000000ULL
-#else
-#define PPC44x_IO_PAGE          0x0000000100000000ULL
-#define PPC44x_PCICFG_PAGE      0x0000000200000000ULL
-#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
-#define PPC44x_PCIMEM_PAGE      0x0000000300000000ULL
-#endif
-
-/*
- * 36-bit trap ranges
- */
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define PPC44x_IO_LO            0xf0000000UL
-#define PPC44x_IO_HI            0xf0000fffUL
-#define PPC44x_PCI0CFG_LO       0x0ec00000UL
-#define PPC44x_PCI0CFG_HI       0x0ec00007UL
-#define PPC44x_PCI1CFG_LO       0x1ec00000UL
-#define PPC44x_PCI1CFG_HI       0x1ec00007UL
-#define PPC44x_PCI2CFG_LO       0x2ec00000UL
-#define PPC44x_PCI2CFG_HI       0x2ec00007UL
-#define PPC44x_PCIMEM_LO        0x80000000UL
-#define PPC44x_PCIMEM_HI        0xdfffffffUL
-#elif defined(CONFIG_440EP)
-#define PPC44x_IO_LO            0xef500000UL
-#define PPC44x_IO_HI            0xefffffffUL
-#define PPC44x_PCI0CFG_LO       0xeec00000UL
-#define PPC44x_PCI0CFG_HI       0xeecfffffUL
-#define PPC44x_PCIMEM_LO        0xa0000000UL
-#define PPC44x_PCIMEM_HI        0xdfffffffUL
-#else
-#define PPC44x_IO_LO            0x40000000UL
-#define PPC44x_IO_HI            0x40000fffUL
-#define PPC44x_PCI0CFG_LO       0x0ec00000UL
-#define PPC44x_PCI0CFG_HI       0x0ec00007UL
-#define PPC44x_PCIMEM_LO        0x80002000UL
-#define PPC44x_PCIMEM_HI        0xffffffffUL
-#endif
-
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-#ifndef __ASSEMBLY__
-
-/*
- * DCRN definitions
- */
-
-
-/* CPRs (440GX and 440SP/440SPe) */
-#define DCRN_CPR_CONFIG_ADDR    0xc
-#define DCRN_CPR_CONFIG_DATA    0xd
-
-#define DCRN_CPR_CLKUPD         0x0020
-#define DCRN_CPR_PLLC           0x0040
-#define DCRN_CPR_PLLD           0x0060
-#define DCRN_CPR_PRIMAD         0x0080
-#define DCRN_CPR_PRIMBD         0x00a0
-#define DCRN_CPR_OPBD           0x00c0
-#define DCRN_CPR_PERD           0x00e0
-#define DCRN_CPR_MALD           0x0100
-
-/* CPRs read/write helper macros */
-#define CPR_READ(offset) ({\
-        mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
-        mfdcr(DCRN_CPR_CONFIG_DATA);})
-#define CPR_WRITE(offset, data) ({\
-        mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
-        mtdcr(DCRN_CPR_CONFIG_DATA, data);})
-
-/* SDRs (440GX and 440SP/440SPe) */
-#define DCRN_SDR_CONFIG_ADDR    0xe
-#define DCRN_SDR_CONFIG_DATA    0xf
-#define DCRN_SDR_PFC0           0x4100
-#define DCRN_SDR_PFC1           0x4101
-#define DCRN_SDR_PFC1_EPS       0x1c00000
-#define DCRN_SDR_PFC1_EPS_SHIFT 22
-#define DCRN_SDR_PFC1_RMII      0x02000000
-#define DCRN_SDR_MFR            0x4300
-#define DCRN_SDR_MFR_TAH0       0x80000000      /* TAHOE0 Enable */
-#define DCRN_SDR_MFR_TAH1       0x40000000      /* TAHOE1 Enable */
-#define DCRN_SDR_MFR_PCM        0x10000000      /* PPC440GP irq compat mode */
-#define DCRN_SDR_MFR_ECS        0x08000000      /* EMAC int clk */
-#define DCRN_SDR_MFR_T0TXFL     0x00080000
-#define DCRN_SDR_MFR_T0TXFH     0x00040000
-#define DCRN_SDR_MFR_T1TXFL     0x00020000
-#define DCRN_SDR_MFR_T1TXFH     0x00010000
-#define DCRN_SDR_MFR_E0TXFL     0x00008000
-#define DCRN_SDR_MFR_E0TXFH     0x00004000
-#define DCRN_SDR_MFR_E0RXFL     0x00002000
-#define DCRN_SDR_MFR_E0RXFH     0x00001000
-#define DCRN_SDR_MFR_E1TXFL     0x00000800
-#define DCRN_SDR_MFR_E1TXFH     0x00000400
-#define DCRN_SDR_MFR_E1RXFL     0x00000200
-#define DCRN_SDR_MFR_E1RXFH     0x00000100
-#define DCRN_SDR_MFR_E2TXFL     0x00000080
-#define DCRN_SDR_MFR_E2TXFH     0x00000040
-#define DCRN_SDR_MFR_E2RXFL     0x00000020
-#define DCRN_SDR_MFR_E2RXFH     0x00000010
-#define DCRN_SDR_MFR_E3TXFL     0x00000008
-#define DCRN_SDR_MFR_E3TXFH     0x00000004
-#define DCRN_SDR_MFR_E3RXFL     0x00000002
-#define DCRN_SDR_MFR_E3RXFH     0x00000001
-#define DCRN_SDR_UART0          0x0120
-#define DCRN_SDR_UART1          0x0121
-
-#ifdef CONFIG_440EP
-#define DCRN_SDR_UART2          0x0122
-#define DCRN_SDR_UART3          0x0123
-#define DCRN_SDR_CUST0          0x4000
-#endif
-
-/* SDR read/write helper macros */
-#define SDR_READ(offset) ({\
-        mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
-        mfdcr(DCRN_SDR_CONFIG_DATA);})
-#define SDR_WRITE(offset, data) ({\
-        mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
-        mtdcr(DCRN_SDR_CONFIG_DATA,data);})
-
-/* DMA (excluding 440SP/440SPe) */
-#define DCRN_DMA0_BASE          0x100
-#define DCRN_DMA1_BASE          0x108
-#define DCRN_DMA2_BASE          0x110
-#define DCRN_DMA3_BASE          0x118
-#define DCRN_DMASR_BASE         0x120
-#define DCRNCAP_DMA_SG          1       /* have DMA scatter/gather capability */
-#define DCRN_MAL_BASE           0x180
-
-#ifdef CONFIG_440EP
-#define DCRN_DMA2P40_BASE       0x300
-#define DCRN_DMA2P41_BASE       0x308
-#define DCRN_DMA2P42_BASE       0x310
-#define DCRN_DMA2P43_BASE       0x318
-#define DCRN_DMA2P4SR_BASE      0x320
-#endif
-
-/* UIC */
-#define DCRN_UIC0_BASE  0xc0
-#define DCRN_UIC1_BASE  0xd0
-#define UIC0            DCRN_UIC0_BASE
-#define UIC1            DCRN_UIC1_BASE
-
-#ifdef CONFIG_440SPE
-#define DCRN_UIC2_BASE  0xe0
-#define DCRN_UIC3_BASE  0xf0
-#define UIC2            DCRN_UIC2_BASE
-#define UIC3            DCRN_UIC3_BASE
-#else
-#define DCRN_UIC2_BASE  0x210
-#define DCRN_UICB_BASE  0x200
-#define UIC2            DCRN_UIC2_BASE
-#define UICB            DCRN_UICB_BASE
-#endif
-
-#define DCRN_UIC_SR(base)       (base + 0x0)
-#define DCRN_UIC_ER(base)       (base + 0x2)
-#define DCRN_UIC_CR(base)       (base + 0x3)
-#define DCRN_UIC_PR(base)       (base + 0x4)
-#define DCRN_UIC_TR(base)       (base + 0x5)
-#define DCRN_UIC_MSR(base)      (base + 0x6)
-#define DCRN_UIC_VR(base)       (base + 0x7)
-#define DCRN_UIC_VCR(base)      (base + 0x8)
-
-#define UIC0_UIC1NC             0x00000002
-
-#ifdef CONFIG_440SPE
-#define UIC0_UIC1NC      0x00000002
-#define UIC0_UIC2NC      0x00200000
-#define UIC0_UIC3NC      0x00008000
-#endif
-
-#define UICB_UIC0NC             0x40000000
-#define UICB_UIC1NC             0x10000000
-#define UICB_UIC2NC             0x04000000
-
-/* 440 MAL DCRs */
-#define DCRN_MALCR(base)                (base + 0x0)    /* Configuration */
-#define DCRN_MALESR(base)               (base + 0x1)    /* Error Status */
-#define DCRN_MALIER(base)               (base + 0x2)    /* Interrupt Enable */
-#define DCRN_MALTXCASR(base)            (base + 0x4)    /* Tx Channel Active Set */
-#define DCRN_MALTXCARR(base)            (base + 0x5)    /* Tx Channel Active Reset */
-#define DCRN_MALTXEOBISR(base)          (base + 0x6)    /* Tx End of Buffer Interrupt Status */
-#define DCRN_MALTXDEIR(base)            (base + 0x7)    /* Tx Descriptor Error Interrupt */
-#define DCRN_MALRXCASR(base)            (base + 0x10)   /* Rx Channel Active Set */
-#define DCRN_MALRXCARR(base)            (base + 0x11)   /* Rx Channel Active Reset */
-#define DCRN_MALRXEOBISR(base)          (base + 0x12)   /* Rx End of Buffer Interrupt Status */
-#define DCRN_MALRXDEIR(base)            (base + 0x13)   /* Rx Descriptor Error Interrupt */
-#define DCRN_MALTXCTP0R(base)           (base + 0x20)   /* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R(base)           (base + 0x21)   /* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALTXCTP2R(base)           (base + 0x22)   /* Channel Tx 2 Channel Table Pointer */
-#define DCRN_MALTXCTP3R(base)           (base + 0x23)   /* Channel Tx 3 Channel Table Pointer */
-#define DCRN_MALRXCTP0R(base)           (base + 0x40)   /* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALRXCTP1R(base)           (base + 0x41)   /* Channel Rx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0(base)             (base + 0x60)   /* Channel Rx 0 Channel Buffer Size */
-#define DCRN_MALRCBS1(base)             (base + 0x61)   /* Channel Rx 1 Channel Buffer Size */
-
-/* Compatibility DCRN's */
-#define DCRN_MALRXCTP2R(base)   ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
-#define DCRN_MALRXCTP3R(base)   ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
-#define DCRN_MALTXCTP4R(base)   ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
-#define DCRN_MALTXCTP5R(base)   ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
-#define DCRN_MALTXCTP6R(base)   ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
-#define DCRN_MALTXCTP7R(base)   ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
-#define DCRN_MALRCBS2(base)     ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
-#define DCRN_MALRCBS3(base)     ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
-
-#define MALCR_MMSR              0x80000000      /* MAL Software reset */
-#define MALCR_PLBP_1            0x00400000      /* MAL reqest priority: */
-#define MALCR_PLBP_2            0x00800000      /* lowsest is 00 */
-#define MALCR_PLBP_3            0x00C00000      /* highest */
-#define MALCR_GA                0x00200000      /* Guarded Active Bit */
-#define MALCR_OA                0x00100000      /* Ordered Active Bit */
-#define MALCR_PLBLE             0x00080000      /* PLB Lock Error Bit */
-#define MALCR_PLBLT_1           0x00040000      /* PLB Latency Timer */
-#define MALCR_PLBLT_2           0x00020000
-#define MALCR_PLBLT_3           0x00010000
-#define MALCR_PLBLT_4           0x00008000
-#ifdef CONFIG_440GP
-#define MALCR_PLBLT_DEFAULT     0x00330000      /* PLB Latency Timer default */
-#else
-#define MALCR_PLBLT_DEFAULT     0x00ff0000      /* PLB Latency Timer default */
-#endif
-#define MALCR_PLBB              0x00004000      /* PLB Burst Deactivation Bit */
-#define MALCR_OPBBL             0x00000080      /* OPB Lock Bit */
-#define MALCR_EOPIE             0x00000004      /* End Of Packet Interrupt Enable */
-#define MALCR_LEA               0x00000002      /* Locked Error Active */
-#define MALCR_MSD               0x00000001      /* MAL Scroll Descriptor Bit */
-/* DCRN_MALESR */
-#define MALESR_EVB              0x80000000      /* Error Valid Bit */
-#define MALESR_CIDRX            0x40000000      /* Channel ID Receive */
-#define MALESR_DE               0x00100000      /* Descriptor Error */
-#define MALESR_OEN              0x00080000      /* OPB Non-Fullword Error */
-#define MALESR_OTE              0x00040000      /* OPB Timeout Error */
-#define MALESR_OSE              0x00020000      /* OPB Slave Error */
-#define MALESR_PEIN             0x00010000      /* PLB Bus Error Indication */
-#define MALESR_DEI              0x00000010      /* Descriptor Error Interrupt */
-#define MALESR_ONEI             0x00000008      /* OPB Non-Fullword Error Interrupt */
-#define MALESR_OTEI             0x00000004      /* OPB Timeout Error Interrupt */
-#define MALESR_OSEI             0x00000002      /* OPB Slace Error Interrupt */
-#define MALESR_PBEI             0x00000001      /* PLB Bus Error Interrupt */
-/* DCRN_MALIER */
-#define MALIER_DE               0x00000010      /* Descriptor Error Interrupt Enable */
-#define MALIER_NE               0x00000008      /* OPB Non-word Transfer Int Enable */
-#define MALIER_TE               0x00000004      /* OPB Time Out Error Interrupt Enable */
-#define MALIER_OPBE             0x00000002      /* OPB Slave Error Interrupt Enable */
-#define MALIER_PLBE             0x00000001      /* PLB Error Interrupt Enable */
-/* DCRN_MALTXEOBISR */
-#define MALOBISR_CH0            0x80000000      /* EOB channel 1 bit */
-#define MALOBISR_CH2            0x40000000      /* EOB channel 2 bit */
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-/* 440SP/440SPe PLB Arbiter DCRs */
-#define DCRN_PLB_REVID         0x080            /* PLB Revision ID */
-#define DCRN_PLB_CCR           0x088            /* PLB Crossbar Control */
-
-#define DCRN_PLB0_ACR          0x081            /* PLB Arbiter Control */
-#define DCRN_PLB0_BESRL        0x082            /* PLB Error Status */
-#define DCRN_PLB0_BESRH        0x083            /* PLB Error Status */
-#define DCRN_PLB0_BEARL        0x084            /* PLB Error Address Low */
-#define DCRN_PLB0_BEARH        0x085            /* PLB Error Address High */
-
-#define DCRN_PLB1_ACR           0x089           /* PLB Arbiter Control */
-#define DCRN_PLB1_BESRL         0x08a           /* PLB Error Status */
-#define DCRN_PLB1_BESRH         0x08b           /* PLB Error Status */
-#define DCRN_PLB1_BEARL         0x08c           /* PLB Error Address Low */
-#define DCRN_PLB1_BEARH         0x08d           /* PLB Error Address High */
-#else
-/* 440GP/GX PLB Arbiter DCRs */
-#define DCRN_PLB0_REVID         0x082           /* PLB Arbiter Revision ID */
-#define DCRN_PLB0_ACR           0x083           /* PLB Arbiter Control */
-#define DCRN_PLB0_BESR          0x084           /* PLB Error Status */
-#define DCRN_PLB0_BEARL         0x086           /* PLB Error Address Low */
-#define DCRN_PLB0_BEAR          DCRN_PLB0_BEARL /* 40x compatibility */
-#define DCRN_PLB0_BEARH         0x087           /* PLB Error Address High */
-#endif
-
-/* 440GP/GX PLB to OPB bridge DCRs */
-#define DCRN_POB0_BESR0         0x090
-#define DCRN_POB0_BESR1         0x094
-#define DCRN_POB0_BEARL         0x092
-#define DCRN_POB0_BEARH         0x093
-
-/* 440GP/GX OPB to PLB bridge DCRs */
-#define DCRN_OPB0_BSTAT         0x0a9
-#define DCRN_OPB0_BEARL         0x0aa
-#define DCRN_OPB0_BEARH         0x0ab
-
-/* 440GP Clock, PM, chip control */
-#define DCRN_CPC0_SR            0x0b0
-#define DCRN_CPC0_ER            0x0b1
-#define DCRN_CPC0_FR            0x0b2
-#define DCRN_CPC0_SYS0          0x0e0
-#define DCRN_CPC0_SYS1          0x0e1
-#define DCRN_CPC0_CUST0         0x0e2
-#define DCRN_CPC0_CUST1         0x0e3
-#define DCRN_CPC0_STRP0         0x0e4
-#define DCRN_CPC0_STRP1         0x0e5
-#define DCRN_CPC0_STRP2         0x0e6
-#define DCRN_CPC0_STRP3         0x0e7
-#define DCRN_CPC0_GPIO          0x0e8
-#define DCRN_CPC0_PLB           0x0e9
-#define DCRN_CPC0_CR1           0x0ea
-#define DCRN_CPC0_CR0           0x0eb
-#define DCRN_CPC0_MIRQ0         0x0ec
-#define DCRN_CPC0_MIRQ1         0x0ed
-#define DCRN_CPC0_JTAGID        0x0ef
-
-/* 440GP DMA controller DCRs */
-#define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)  /* DMA Channel Control 0 */
-#define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count 0 */
-#define DCRN_DMASAH0    (DCRN_DMA0_BASE + 0x2)  /* DMA Src Addr High 0 */
-#define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)  /* DMA Src Addr Low 0 */
-#define DCRN_DMADAH0    (DCRN_DMA0_BASE + 0x4)  /* DMA Dest Addr High 0 */
-#define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x5)  /* DMA Dest Addr Low 0 */
-#define DCRN_ASGH0      (DCRN_DMA0_BASE + 0x6)  /* DMA SG Desc Addr High 0 */
-#define DCRN_ASG0       (DCRN_DMA0_BASE + 0x7)  /* DMA SG Desc Addr Low 0 */
-
-#define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)  /* DMA Channel Control 1 */
-#define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count 1 */
-#define DCRN_DMASAH1    (DCRN_DMA1_BASE + 0x2)  /* DMA Src Addr High 1 */
-#define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Src Addr Low 1 */
-#define DCRN_DMADAH1    (DCRN_DMA1_BASE + 0x4)  /* DMA Dest Addr High 1 */
-#define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x5)  /* DMA Dest Addr Low 1 */
-#define DCRN_ASGH1      (DCRN_DMA1_BASE + 0x6)  /* DMA SG Desc Addr High 1 */
-#define DCRN_ASG1       (DCRN_DMA1_BASE + 0x7)  /* DMA SG Desc Addr Low 1 */
-
-#define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control 2 */
-#define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count 2 */
-#define DCRN_DMASAH2    (DCRN_DMA2_BASE + 0x2)  /* DMA Src Addr High 2 */
-#define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Src Addr Low 2 */
-#define DCRN_DMADAH2    (DCRN_DMA2_BASE + 0x4)  /* DMA Dest Addr High 2 */
-#define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x5)  /* DMA Dest Addr Low 2 */
-#define DCRN_ASGH2      (DCRN_DMA2_BASE + 0x6)  /* DMA SG Desc Addr High 2 */
-#define DCRN_ASG2       (DCRN_DMA2_BASE + 0x7)  /* DMA SG Desc Addr Low 2 */
-
-#define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control 3 */
-#define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count 3 */
-#define DCRN_DMASAH3    (DCRN_DMA3_BASE + 0x2)  /* DMA Src Addr High 3 */
-#define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Src Addr Low 3 */
-#define DCRN_DMADAH3    (DCRN_DMA3_BASE + 0x4)  /* DMA Dest Addr High 3 */
-#define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x5)  /* DMA Dest Addr Low 3 */
-#define DCRN_ASGH3      (DCRN_DMA3_BASE + 0x6)  /* DMA SG Desc Addr High 3 */
-#define DCRN_ASG3       (DCRN_DMA3_BASE + 0x7)  /* DMA SG Desc Addr Low 3 */
-
-#define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
-#define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
-#define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
-#define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
-
-/* 440GP/440GX SDRAM controller DCRs */
-#define DCRN_SDRAM0_CFGADDR             0x010
-#define DCRN_SDRAM0_CFGDATA             0x011
-
-#define SDRAM0_B0CR     0x40
-#define SDRAM0_B1CR     0x44
-#define SDRAM0_B2CR     0x48
-#define SDRAM0_B3CR     0x4c
-
-#define SDRAM_CONFIG_BANK_ENABLE        0x00000001
-#define SDRAM_CONFIG_SIZE_MASK          0x000e0000
-#define SDRAM_CONFIG_BANK_SIZE(reg)     ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
-#define SDRAM_CONFIG_SIZE_8M            0x00000001
-#define SDRAM_CONFIG_SIZE_16M           0x00000002
-#define SDRAM_CONFIG_SIZE_32M           0x00000003
-#define SDRAM_CONFIG_SIZE_64M           0x00000004
-#define SDRAM_CONFIG_SIZE_128M          0x00000005
-#define SDRAM_CONFIG_SIZE_256M          0x00000006
-#define SDRAM_CONFIG_SIZE_512M          0x00000007
-#define PPC44x_MEM_SIZE_8M              0x00800000
-#define PPC44x_MEM_SIZE_16M             0x01000000
-#define PPC44x_MEM_SIZE_32M             0x02000000
-#define PPC44x_MEM_SIZE_64M             0x04000000
-#define PPC44x_MEM_SIZE_128M            0x08000000
-#define PPC44x_MEM_SIZE_256M            0x10000000
-#define PPC44x_MEM_SIZE_512M            0x20000000
-#define PPC44x_MEM_SIZE_1G              0x40000000
-#define PPC44x_MEM_SIZE_2G              0x80000000
-
-/* 440SP/440SPe memory controller DCRs */
-#define DCRN_MQ0_BS0BAS                 0x40
-#if defined(CONFIG_440SP)
-#define MQ0_NUM_BANKS                   2
-#elif defined(CONFIG_440SPE)
-#define MQ0_NUM_BANKS                   4
-#endif
-
-#define MQ0_CONFIG_SIZE_MASK            0x0000fff0
-#define MQ0_CONFIG_SIZE_8M              0x0000ffc0
-#define MQ0_CONFIG_SIZE_16M             0x0000ff80
-#define MQ0_CONFIG_SIZE_32M             0x0000ff00
-#define MQ0_CONFIG_SIZE_64M             0x0000fe00
-#define MQ0_CONFIG_SIZE_128M            0x0000fc00
-#define MQ0_CONFIG_SIZE_256M            0x0000f800
-#define MQ0_CONFIG_SIZE_512M            0x0000f000
-#define MQ0_CONFIG_SIZE_1G              0x0000e000
-#define MQ0_CONFIG_SIZE_2G              0x0000c000
-#define MQ0_CONFIG_SIZE_4G              0x00008000
-
-/* Internal SRAM Controller 440GX/440SP/440SPe */
-#define DCRN_SRAM0_BASE         0x000
-
-#define DCRN_SRAM0_SB0CR        (DCRN_SRAM0_BASE + 0x020)
-#define DCRN_SRAM0_SB1CR        (DCRN_SRAM0_BASE + 0x021)
-#define DCRN_SRAM0_SB2CR        (DCRN_SRAM0_BASE + 0x022)
-#define DCRN_SRAM0_SB3CR        (DCRN_SRAM0_BASE + 0x023)
-#define  SRAM_SBCR_BAS0         0x80000000
-#define  SRAM_SBCR_BAS1         0x80010000
-#define  SRAM_SBCR_BAS2         0x80020000
-#define  SRAM_SBCR_BAS3         0x80030000
-#define  SRAM_SBCR_BU_MASK      0x00000180
-#define  SRAM_SBCR_BS_64KB      0x00000800
-#define  SRAM_SBCR_BU_RO        0x00000080
-#define  SRAM_SBCR_BU_RW        0x00000180
-#define DCRN_SRAM0_BEAR         (DCRN_SRAM0_BASE + 0x024)
-#define DCRN_SRAM0_BESR0        (DCRN_SRAM0_BASE + 0x025)
-#define DCRN_SRAM0_BESR1        (DCRN_SRAM0_BASE + 0x026)
-#define DCRN_SRAM0_PMEG         (DCRN_SRAM0_BASE + 0x027)
-#define DCRN_SRAM0_CID          (DCRN_SRAM0_BASE + 0x028)
-#define DCRN_SRAM0_REVID        (DCRN_SRAM0_BASE + 0x029)
-#define DCRN_SRAM0_DPC          (DCRN_SRAM0_BASE + 0x02a)
-#define  SRAM_DPC_ENABLE        0x80000000
-
-/* L2 Cache Controller 440GX/440SP/440SPe */
-#define DCRN_L2C0_CFG           0x030
-#define  L2C_CFG_L2M            0x80000000
-#define  L2C_CFG_ICU            0x40000000
-#define  L2C_CFG_DCU            0x20000000
-#define  L2C_CFG_DCW_MASK       0x1e000000
-#define  L2C_CFG_TPC            0x01000000
-#define  L2C_CFG_CPC            0x00800000
-#define  L2C_CFG_FRAN           0x00200000
-#define  L2C_CFG_SS_MASK        0x00180000
-#define  L2C_CFG_SS_256         0x00000000
-#define  L2C_CFG_CPIM           0x00040000
-#define  L2C_CFG_TPIM           0x00020000
-#define  L2C_CFG_LIM            0x00010000
-#define  L2C_CFG_PMUX_MASK      0x00007000
-#define  L2C_CFG_PMUX_SNP       0x00000000
-#define  L2C_CFG_PMUX_IF        0x00001000
-#define  L2C_CFG_PMUX_DF        0x00002000
-#define  L2C_CFG_PMUX_DS        0x00003000
-#define  L2C_CFG_PMIM           0x00000800
-#define  L2C_CFG_TPEI           0x00000400
-#define  L2C_CFG_CPEI           0x00000200
-#define  L2C_CFG_NAM            0x00000100
-#define  L2C_CFG_SMCM           0x00000080
-#define  L2C_CFG_NBRM           0x00000040
-#define DCRN_L2C0_CMD           0x031
-#define  L2C_CMD_CLR            0x80000000
-#define  L2C_CMD_DIAG           0x40000000
-#define  L2C_CMD_INV            0x20000000
-#define  L2C_CMD_CCP            0x10000000
-#define  L2C_CMD_CTE            0x08000000
-#define  L2C_CMD_STRC           0x04000000
-#define  L2C_CMD_STPC           0x02000000
-#define  L2C_CMD_RPMC           0x01000000
-#define  L2C_CMD_HCC            0x00800000
-#define DCRN_L2C0_ADDR          0x032
-#define DCRN_L2C0_DATA          0x033
-#define DCRN_L2C0_SR            0x034
-#define  L2C_SR_CC              0x80000000
-#define  L2C_SR_CPE             0x40000000
-#define  L2C_SR_TPE             0x20000000
-#define  L2C_SR_LRU             0x10000000
-#define  L2C_SR_PCS             0x08000000
-#define DCRN_L2C0_REVID         0x035
-#define DCRN_L2C0_SNP0          0x036
-#define DCRN_L2C0_SNP1          0x037
-#define  L2C_SNP_BA_MASK        0xffff0000
-#define  L2C_SNP_SSR_MASK       0x0000f000
-#define  L2C_SNP_SSR_32G        0x0000f000
-#define  L2C_SNP_ESR            0x00000800
-
-/*
- * PCI-X definitions
- */
-#define PCIX0_CFGA              0x0ec00000UL
-#define PCIX1_CFGA              0x1ec00000UL
-#define PCIX2_CFGA              0x2ec00000UL
-#define PCIX0_CFGD              0x0ec00004UL
-#define PCIX1_CFGD              0x1ec00004UL
-#define PCIX2_CFGD              0x2ec00004UL
-
-#define PCIX0_IO_BASE           0x0000000908000000ULL
-#define PCIX1_IO_BASE           0x0000000908000000ULL
-#define PCIX2_IO_BASE           0x0000000908000000ULL
-#define PCIX_IO_SIZE            0x00010000
-
-#ifdef CONFIG_440SP
-#define PCIX0_REG_BASE          0x000000090ec80000ULL
-#else
-#define PCIX0_REG_BASE          0x000000020ec80000ULL
-#endif
-#define PCIX_REG_OFFSET         0x10000000
-#define PCIX_REG_SIZE           0x200
-
-#define PCIX0_VENDID            0x000
-#define PCIX0_DEVID             0x002
-#define PCIX0_COMMAND           0x004
-#define PCIX0_STATUS            0x006
-#define PCIX0_REVID             0x008
-#define PCIX0_CLS               0x009
-#define PCIX0_CACHELS           0x00c
-#define PCIX0_LATTIM            0x00d
-#define PCIX0_HDTYPE            0x00e
-#define PCIX0_BIST              0x00f
-#define PCIX0_BAR0L             0x010
-#define PCIX0_BAR0H             0x014
-#define PCIX0_BAR1              0x018
-#define PCIX0_BAR2L             0x01c
-#define PCIX0_BAR2H             0x020
-#define PCIX0_BAR3              0x024
-#define PCIX0_CISPTR            0x028
-#define PCIX0_SBSYSVID          0x02c
-#define PCIX0_SBSYSID           0x02e
-#define PCIX0_EROMBA            0x030
-#define PCIX0_CAP               0x034
-#define PCIX0_RES0              0x035
-#define PCIX0_RES1              0x036
-#define PCIX0_RES2              0x038
-#define PCIX0_INTLN             0x03c
-#define PCIX0_INTPN             0x03d
-#define PCIX0_MINGNT            0x03e
-#define PCIX0_MAXLTNCY          0x03f
-#define PCIX0_BRDGOPT1          0x040
-#define PCIX0_BRDGOPT2          0x044
-#define PCIX0_ERREN             0x050
-#define PCIX0_ERRSTS            0x054
-#define PCIX0_PLBBESR           0x058
-#define PCIX0_PLBBEARL          0x05c
-#define PCIX0_PLBBEARH          0x060
-#define PCIX0_POM0LAL           0x068
-#define PCIX0_POM0LAH           0x06c
-#define PCIX0_POM0SA            0x070
-#define PCIX0_POM0PCIAL         0x074
-#define PCIX0_POM0PCIAH         0x078
-#define PCIX0_POM1LAL           0x07c
-#define PCIX0_POM1LAH           0x080
-#define PCIX0_POM1SA            0x084
-#define PCIX0_POM1PCIAL         0x088
-#define PCIX0_POM1PCIAH         0x08c
-#define PCIX0_POM2SA            0x090
-#define PCIX0_PIM0SAL           0x098
-#define PCIX0_PIM0SA            PCIX0_PIM0SAL
-#define PCIX0_PIM0LAL           0x09c
-#define PCIX0_PIM0LAH           0x0a0
-#define PCIX0_PIM1SA            0x0a4
-#define PCIX0_PIM1LAL           0x0a8
-#define PCIX0_PIM1LAH           0x0ac
-#define PCIX0_PIM2SAL           0x0b0
-#define PCIX0_PIM2SA            PCIX0_PIM2SAL
-#define PCIX0_PIM2LAL           0x0b4
-#define PCIX0_PIM2LAH           0x0b8
-#define PCIX0_OMCAPID           0x0c0
-#define PCIX0_OMNIPTR           0x0c1
-#define PCIX0_OMMC              0x0c2
-#define PCIX0_OMMA              0x0c4
-#define PCIX0_OMMUA             0x0c8
-#define PCIX0_OMMDATA           0x0cc
-#define PCIX0_OMMEOI            0x0ce
-#define PCIX0_PMCAPID           0x0d0
-#define PCIX0_PMNIPTR           0x0d1
-#define PCIX0_PMC               0x0d2
-#define PCIX0_PMCSR             0x0d4
-#define PCIX0_PMCSRBSE          0x0d6
-#define PCIX0_PMDATA            0x0d7
-#define PCIX0_PMSCRR            0x0d8
-#define PCIX0_CAPID             0x0dc
-#define PCIX0_NIPTR             0x0dd
-#define PCIX0_CMD               0x0de
-#define PCIX0_STS               0x0e0
-#define PCIX0_IDR               0x0e4
-#define PCIX0_CID               0x0e8
-#define PCIX0_RID               0x0ec
-#define PCIX0_PIM0SAH           0x0f8
-#define PCIX0_PIM2SAH           0x0fc
-#define PCIX0_MSGIL             0x100
-#define PCIX0_MSGIH             0x104
-#define PCIX0_MSGOL             0x108
-#define PCIX0_MSGOH             0x10c
-#define PCIX0_IM                0x1f8
-
-#define IIC_OWN                 0x55
-#define IIC_CLOCK               50
-
-#undef NR_UICS
-#if defined(CONFIG_440GX)
-#define NR_UICS 3
-#elif defined(CONFIG_440SPE)
-#define NR_UICS 4
-#else
-#define NR_UICS 2
-#endif
-
-#include <asm/ibm4xx.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_IBM44x_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
deleted file mode 100644
index ed6891af05d3..000000000000
--- a/include/asm-ppc/ibm4xx.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- *
- *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *
- *    Module name: ibm4xx.h
- *
- *    Description:
- *      A generic include file which pulls in appropriate include files
- *      for specific board types based on configuration settings.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM4XX_H__
-#define __ASM_IBM4XX_H__
-
-#include <asm/types.h>
-#include <asm/dcr.h>
-
-#ifdef CONFIG_40x
-
-#if defined(CONFIG_BUBINGA)
-#include <platforms/4xx/bubinga.h>
-#endif
-
-#if defined(CONFIG_CPCI405)
-#include <platforms/4xx/cpci405.h>
-#endif
-
-#if defined(CONFIG_EP405)
-#include <platforms/4xx/ep405.h>
-#endif
-
-#if defined(CONFIG_REDWOOD_5)
-#include <platforms/4xx/redwood5.h>
-#endif
-
-#if defined(CONFIG_REDWOOD_6)
-#include <platforms/4xx/redwood6.h>
-#endif
-
-#if defined(CONFIG_SYCAMORE)
-#include <platforms/4xx/sycamore.h>
-#endif
-
-#if defined(CONFIG_WALNUT)
-#include <platforms/4xx/walnut.h>
-#endif
-
-#if defined(CONFIG_XILINX_VIRTEX)
-#include <platforms/4xx/virtex.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_40x
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern bd_t __res;
-#endif
-
-void ppc4xx_setup_arch(void);
-void ppc4xx_map_io(void);
-void ppc4xx_init_IRQ(void);
-void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
-                 unsigned long r6, unsigned long r7);
-#endif
-
-#ifndef PPC4xx_MACHINE_NAME
-#define PPC4xx_MACHINE_NAME     "Unidentified 4xx class"
-#endif
-
-
-/* IO_BASE is for PCI I/O.
- * ISA not supported, just here to resolve copilation.
- */
-
-#ifndef _IO_BASE
-#define _IO_BASE        0xe8000000      /* The PCI address window */
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#endif
-
-#elif defined(CONFIG_44x)
-
-#if defined(CONFIG_BAMBOO)
-#include <platforms/4xx/bamboo.h>
-#endif
-
-#if defined(CONFIG_EBONY)
-#include <platforms/4xx/ebony.h>
-#endif
-
-#if defined(CONFIG_LUAN)
-#include <platforms/4xx/luan.h>
-#endif
-
-#if defined(CONFIG_YUCCA)
-#include <platforms/4xx/yucca.h>
-#endif
-
-#if defined(CONFIG_OCOTEA)
-#include <platforms/4xx/ocotea.h>
-#endif
-
-#if defined(CONFIG_TAISHAN)
-#include <platforms/4xx/taishan.h>
-#endif
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_40x
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern bd_t __res;
-#endif
-#endif
-#endif /* CONFIG_40x */
-
-#endif /* __ASM_IBM4XX_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
deleted file mode 100644
index ddce616f765a..000000000000
--- a/include/asm-ppc/ibm_ocp.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * ibm_ocp.h
- *
- *      (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *          Mipsys - France
- *
- *          Derived from work (c) Armin Kuster akuster@pacbell.net
- *
- *          Additional support and port to 2.6 LDM/sysfs by
- *          Matt Porter <mporter@kernel.crashing.org>
- *          Copyright 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#ifdef __KERNEL__
-#ifndef __IBM_OCP_H__
-#define __IBM_OCP_H__
-
-#include <asm/types.h>
-
-/*
- * IBM 4xx OCP system information
- */
-struct ocp_sys_info_data {
-        int     opb_bus_freq;   /* OPB Bus Frequency (Hz) */
-        int     ebc_bus_freq;   /* EBC Bus Frequency (Hz) */
-};
-
-extern struct ocp_sys_info_data ocp_sys_info;
-
-/*
- * EMAC additional data and sysfs support
- *
- * Note about mdio_idx: When you have a zmii, it's usually
- * not necessary, it covers the case of the 405EP which has
- * the MDIO lines on EMAC0 only
- *
- * Note about phy_map: Per EMAC map of PHY ids which should
- * be probed by emac_probe. Different EMACs can have
- * overlapping maps.
- *
- * Note, this map uses inverse logic for bits:
- *  0 - id should be probed
- *  1 - id should be ignored
- *
- * Default value of 0x00000000 - will result in usual
- * auto-detection logic.
- *
- */
-
-struct ocp_func_emac_data {
-        int     rgmii_idx;      /* RGMII device index or -1 */
-        int     rgmii_mux;      /* RGMII input of this EMAC */
-        int     zmii_idx;       /* ZMII device index or -1 */
-        int     zmii_mux;       /* ZMII input of this EMAC */
-        int     mal_idx;        /* MAL device index */
-        int     mal_rx_chan;    /* MAL rx channel number */
-        int     mal_tx_chan;    /* MAL tx channel number */
-        int     wol_irq;        /* WOL interrupt */
-        int     mdio_idx;       /* EMAC idx of MDIO master or -1 */
-        int     tah_idx;        /* TAH device index or -1 */
-        int     phy_mode;       /* PHY type or configurable mode */
-        u8      mac_addr[6];    /* EMAC mac address */
-        u32     phy_map;        /* EMAC phy map */
-        u32     phy_feat_exc;   /* Excluded PHY features */
-};
-
-/* Sysfs support */
-#define OCP_SYSFS_EMAC_DATA()                                           \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx)     \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux)     \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx)      \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux)      \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx)       \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan)   \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan)   \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq)       \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx)      \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx)       \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode)      \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map)   \
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
-                                                                        \
-void ocp_show_emac_data(struct device *dev)                             \
-{                                                                       \
-        device_create_file(dev, &dev_attr_emac_rgmii_idx);              \
-        device_create_file(dev, &dev_attr_emac_rgmii_mux);              \
-        device_create_file(dev, &dev_attr_emac_zmii_idx);               \
-        device_create_file(dev, &dev_attr_emac_zmii_mux);               \
-        device_create_file(dev, &dev_attr_emac_mal_idx);                \
-        device_create_file(dev, &dev_attr_emac_mal_rx_chan);            \
-        device_create_file(dev, &dev_attr_emac_mal_tx_chan);            \
-        device_create_file(dev, &dev_attr_emac_wol_irq);                \
-        device_create_file(dev, &dev_attr_emac_mdio_idx);               \
-        device_create_file(dev, &dev_attr_emac_tah_idx);                \
-        device_create_file(dev, &dev_attr_emac_phy_mode);               \
-        device_create_file(dev, &dev_attr_emac_phy_map);                \
-        device_create_file(dev, &dev_attr_emac_phy_feat_exc);           \
-}
-
-/*
- * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
- */
-#define PHY_MODE_NA     0
-#define PHY_MODE_MII    1
-#define PHY_MODE_RMII   2
-#define PHY_MODE_SMII   3
-#define PHY_MODE_RGMII  4
-#define PHY_MODE_TBI    5
-#define PHY_MODE_GMII   6
-#define PHY_MODE_RTBI   7
-#define PHY_MODE_SGMII  8
-
-#ifdef CONFIG_40x
-/*
- * Helper function to copy MAC addresses from the bd_t to OCP EMAC
- * additions.
- *
- * The range of EMAC indices (inclusive) to be copied are the arguments.
- */
-static inline void ibm_ocp_set_emac(int start, int end)
-{
-        int i;
-        struct ocp_def *def;
-
-        /* Copy MAC addresses to EMAC additions */
-        for (i=start; i<=end; i++) {
-                def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
-                if (i == 0)
-                        memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-                               __res.bi_enetaddr, 6);
-#if defined(CONFIG_405EP) || defined(CONFIG_44x)
-                else if (i == 1)
-                        memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-                               __res.bi_enet1addr, 6);
-#endif
-#if defined(CONFIG_440GX)
-                else if (i == 2)
-                        memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-                               __res.bi_enet2addr, 6);
-                else if (i == 3)
-                        memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-                               __res.bi_enet3addr, 6);
-#endif
-        }
-}
-#endif
-
-/*
- * MAL additional data and sysfs support
- */
-struct ocp_func_mal_data {
-        int     num_tx_chans;   /* Number of TX channels */
-        int     num_rx_chans;   /* Number of RX channels */
-        int     txeob_irq;      /* TX End Of Buffer IRQ  */
-        int     rxeob_irq;      /* RX End Of Buffer IRQ  */
-        int     txde_irq;       /* TX Descriptor Error IRQ */
-        int     rxde_irq;       /* RX Descriptor Error IRQ */
-        int     serr_irq;       /* MAL System Error IRQ    */
-        int     dcr_base;       /* MALx_CFG DCR number   */
-};
-
-#define OCP_SYSFS_MAL_DATA()                                            \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans)    \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans)    \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq)       \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq)       \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq)        \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq)        \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq)        \
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base)        \
-                                                                        \
-void ocp_show_mal_data(struct device *dev)                              \
-{                                                                       \
-        device_create_file(dev, &dev_attr_mal_num_tx_chans);            \
-        device_create_file(dev, &dev_attr_mal_num_rx_chans);            \
-        device_create_file(dev, &dev_attr_mal_txeob_irq);               \
-        device_create_file(dev, &dev_attr_mal_rxeob_irq);               \
-        device_create_file(dev, &dev_attr_mal_txde_irq);                \
-        device_create_file(dev, &dev_attr_mal_rxde_irq);                \
-        device_create_file(dev, &dev_attr_mal_serr_irq);                \
-        device_create_file(dev, &dev_attr_mal_dcr_base);                \
-}
-
-/*
- * IIC additional data and sysfs support
- */
-struct ocp_func_iic_data {
-        int     fast_mode;      /* IIC fast mode enabled */
-};
-
-#define OCP_SYSFS_IIC_DATA()                                            \
-OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode)       \
-                                                                        \
-void ocp_show_iic_data(struct device *dev)                              \
-{                                                                       \
-        device_create_file(dev, &dev_attr_iic_fast_mode);               \
-}
-#endif /* __IBM_OCP_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h
deleted file mode 100644
index a81ab6144358..000000000000
--- a/include/asm-ppc/ibm_ocp_pci.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM_OCP_PCI_H__
-#define __ASM_IBM_OCP_PCI_H__
-
-/* PCI 32 */
-
-struct pmm_regs {
-        u32 la;
-        u32 ma;
-        u32 pcila;
-        u32 pciha;
-};
-
-typedef struct pcil0_regs {
-        struct pmm_regs pmm[3];
-        u32 ptm1ms;
-        u32 ptm1la;
-        u32 ptm2ms;
-        u32 ptm2la;
-} pci0_t;
-
-#endif                          /* __ASM_IBM_OCP_PCI_H__ */
-#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h
deleted file mode 100644
index 3c23d9cb47a6..000000000000
--- a/include/asm-ppc/immap_cpm2.h
+++ /dev/null
@@ -1,648 +0,0 @@
-/*
- * CPM2 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * The Internal Memory Map for devices with CPM2 on them.  This
- * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
- * 8560). 
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_CPM2__
-#define __IMMAP_CPM2__
-
-/* System configuration registers.
-*/
-typedef struct sys_82xx_conf {
-        u32     sc_siumcr;
-        u32     sc_sypcr;
-        u8      res1[6];
-        u16     sc_swsr;
-        u8      res2[20];
-        u32     sc_bcr;
-        u8      sc_ppc_acr;
-        u8      res3[3];
-        u32     sc_ppc_alrh;
-        u32     sc_ppc_alrl;
-        u8      sc_lcl_acr;
-        u8      res4[3];
-        u32     sc_lcl_alrh;
-        u32     sc_lcl_alrl;
-        u32     sc_tescr1;
-        u32     sc_tescr2;
-        u32     sc_ltescr1;
-        u32     sc_ltescr2;
-        u32     sc_pdtea;
-        u8      sc_pdtem;
-        u8      res5[3];
-        u32     sc_ldtea;
-        u8      sc_ldtem;
-        u8      res6[163];
-} sysconf_82xx_cpm2_t;
-
-typedef struct sys_85xx_conf {
-        u32     sc_cear;
-        u16     sc_ceer;
-        u16     sc_cemr;
-        u8      res1[70];
-        u32     sc_smaer;
-        u8      res2[4];
-        u32     sc_smevr;
-        u32     sc_smctr;
-        u32     sc_lmaer;
-        u8      res3[4];
-        u32     sc_lmevr;
-        u32     sc_lmctr;
-        u8      res4[144];
-} sysconf_85xx_cpm2_t;
-
-typedef union sys_conf {
-        sysconf_82xx_cpm2_t     siu_82xx;
-        sysconf_85xx_cpm2_t     siu_85xx;
-} sysconf_cpm2_t;
-
-
-
-/* Memory controller registers.
-*/
-typedef struct  mem_ctlr {
-        u32     memc_br0;
-        u32     memc_or0;
-        u32     memc_br1;
-        u32     memc_or1;
-        u32     memc_br2;
-        u32     memc_or2;
-        u32     memc_br3;
-        u32     memc_or3;
-        u32     memc_br4;
-        u32     memc_or4;
-        u32     memc_br5;
-        u32     memc_or5;
-        u32     memc_br6;
-        u32     memc_or6;
-        u32     memc_br7;
-        u32     memc_or7;
-        u32     memc_br8;
-        u32     memc_or8;
-        u32     memc_br9;
-        u32     memc_or9;
-        u32     memc_br10;
-        u32     memc_or10;
-        u32     memc_br11;
-        u32     memc_or11;
-        u8      res1[8];
-        u32     memc_mar;
-        u8      res2[4];
-        u32     memc_mamr;
-        u32     memc_mbmr;
-        u32     memc_mcmr;
-        u8      res3[8];
-        u16     memc_mptpr;
-        u8      res4[2];
-        u32     memc_mdr;
-        u8      res5[4];
-        u32     memc_psdmr;
-        u32     memc_lsdmr;
-        u8      memc_purt;
-        u8      res6[3];
-        u8      memc_psrt;
-        u8      res7[3];
-        u8      memc_lurt;
-        u8      res8[3];
-        u8      memc_lsrt;
-        u8      res9[3];
-        u32     memc_immr;
-        u32     memc_pcibr0;
-        u32     memc_pcibr1;
-        u8      res10[16];
-        u32     memc_pcimsk0;
-        u32     memc_pcimsk1;
-        u8      res11[52];
-} memctl_cpm2_t;
-
-/* System Integration Timers.
-*/
-typedef struct  sys_int_timers {
-        u8      res1[32];
-        u16     sit_tmcntsc;
-        u8      res2[2];
-        u32     sit_tmcnt;
-        u8      res3[4];
-        u32     sit_tmcntal;
-        u8      res4[16];
-        u16     sit_piscr;
-        u8      res5[2];
-        u32     sit_pitc;
-        u32     sit_pitr;
-        u8      res6[94];
-        u8      res7[390];
-} sit_cpm2_t;
-
-#define PISCR_PIRQ_MASK         ((u16)0xff00)
-#define PISCR_PS                ((u16)0x0080)
-#define PISCR_PIE               ((u16)0x0004)
-#define PISCR_PTF               ((u16)0x0002)
-#define PISCR_PTE               ((u16)0x0001)
-
-/* PCI Controller.
-*/
-typedef struct pci_ctlr {
-        u32     pci_omisr;
-        u32     pci_omimr;
-        u8      res1[8];
-        u32     pci_ifqpr;
-        u32     pci_ofqpr;
-        u8      res2[8];
-        u32     pci_imr0;
-        u32     pci_imr1;
-        u32     pci_omr0;
-        u32     pci_omr1;
-        u32     pci_odr;
-        u8      res3[4];
-        u32     pci_idr;
-        u8      res4[20];
-        u32     pci_imisr;
-        u32     pci_imimr;
-        u8      res5[24];
-        u32     pci_ifhpr;
-        u8      res6[4];
-        u32     pci_iftpr;
-        u8      res7[4];
-        u32     pci_iphpr;
-        u8      res8[4];
-        u32     pci_iptpr;
-        u8      res9[4];
-        u32     pci_ofhpr;
-        u8      res10[4];
-        u32     pci_oftpr;
-        u8      res11[4];
-        u32     pci_ophpr;
-        u8      res12[4];
-        u32     pci_optpr;
-        u8      res13[8];
-        u32     pci_mucr;
-        u8      res14[8];
-        u32     pci_qbar;
-        u8      res15[12];
-        u32     pci_dmamr0;
-        u32     pci_dmasr0;
-        u32     pci_dmacdar0;
-        u8      res16[4];
-        u32     pci_dmasar0;
-        u8      res17[4];
-        u32     pci_dmadar0;
-        u8      res18[4];
-        u32     pci_dmabcr0;
-        u32     pci_dmandar0;
-        u8      res19[86];
-        u32     pci_dmamr1;
-        u32     pci_dmasr1;
-        u32     pci_dmacdar1;
-        u8      res20[4];
-        u32     pci_dmasar1;
-        u8      res21[4];
-        u32     pci_dmadar1;
-        u8      res22[4];
-        u32     pci_dmabcr1;
-        u32     pci_dmandar1;
-        u8      res23[88];
-        u32     pci_dmamr2;
-        u32     pci_dmasr2;
-        u32     pci_dmacdar2;
-        u8      res24[4];
-        u32     pci_dmasar2;
-        u8      res25[4];
-        u32     pci_dmadar2;
-        u8      res26[4];
-        u32     pci_dmabcr2;
-        u32     pci_dmandar2;
-        u8      res27[88];
-        u32     pci_dmamr3;
-        u32     pci_dmasr3;
-        u32     pci_dmacdar3;
-        u8      res28[4];
-        u32     pci_dmasar3;
-        u8      res29[4];
-        u32     pci_dmadar3;
-        u8      res30[4];
-        u32     pci_dmabcr3;
-        u32     pci_dmandar3;
-        u8      res31[344];
-        u32     pci_potar0;
-        u8      res32[4];
-        u32     pci_pobar0;
-        u8      res33[4];
-        u32     pci_pocmr0;
-        u8      res34[4];
-        u32     pci_potar1;
-        u8      res35[4];
-        u32     pci_pobar1;
-        u8      res36[4];
-        u32     pci_pocmr1;
-        u8      res37[4];
-        u32     pci_potar2;
-        u8      res38[4];
-        u32     pci_pobar2;
-        u8      res39[4];
-        u32     pci_pocmr2;
-        u8      res40[50];
-        u32     pci_ptcr;
-        u32     pci_gpcr;
-        u32     pci_gcr;
-        u32     pci_esr;
-        u32     pci_emr;
-        u32     pci_ecr;
-        u32     pci_eacr;
-        u8      res41[4];
-        u32     pci_edcr;
-        u8      res42[4];
-        u32     pci_eccr;
-        u8      res43[44];
-        u32     pci_pitar1;
-        u8      res44[4];
-        u32     pci_pibar1;
-        u8      res45[4];
-        u32     pci_picmr1;
-        u8      res46[4];
-        u32     pci_pitar0;
-        u8      res47[4];
-        u32     pci_pibar0;
-        u8      res48[4];
-        u32     pci_picmr0;
-        u8      res49[4];
-        u32     pci_cfg_addr;
-        u32     pci_cfg_data;
-        u32     pci_int_ack;
-        u8      res50[756];
-} pci_cpm2_t;
-
-/* Interrupt Controller.
-*/
-typedef struct interrupt_controller {
-        u16     ic_sicr;
-        u8      res1[2];
-        u32     ic_sivec;
-        u32     ic_sipnrh;
-        u32     ic_sipnrl;
-        u32     ic_siprr;
-        u32     ic_scprrh;
-        u32     ic_scprrl;
-        u32     ic_simrh;
-        u32     ic_simrl;
-        u32     ic_siexr;
-        u8      res2[88];
-} intctl_cpm2_t;
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-        u32     car_sccr;
-        u8      res1[4];
-        u32     car_scmr;
-        u8      res2[4];
-        u32     car_rsr;
-        u32     car_rmr;
-        u8      res[104];
-} car_cpm2_t;
-
-/* Input/Output Port control/status registers.
- * Names consistent with processor manual, although they are different
- * from the original 8xx names.......
- */
-typedef struct io_port {
-        u32     iop_pdira;
-        u32     iop_ppara;
-        u32     iop_psora;
-        u32     iop_podra;
-        u32     iop_pdata;
-        u8      res1[12];
-        u32     iop_pdirb;
-        u32     iop_pparb;
-        u32     iop_psorb;
-        u32     iop_podrb;
-        u32     iop_pdatb;
-        u8      res2[12];
-        u32     iop_pdirc;
-        u32     iop_pparc;
-        u32     iop_psorc;
-        u32     iop_podrc;
-        u32     iop_pdatc;
-        u8      res3[12];
-        u32     iop_pdird;
-        u32     iop_ppard;
-        u32     iop_psord;
-        u32     iop_podrd;
-        u32     iop_pdatd;
-        u8      res4[12];
-} iop_cpm2_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-        u8      cpmt_tgcr1;
-        u8      res1[3];
-        u8      cpmt_tgcr2;
-        u8      res2[11];
-        u16     cpmt_tmr1;
-        u16     cpmt_tmr2;
-        u16     cpmt_trr1;
-        u16     cpmt_trr2;
-        u16     cpmt_tcr1;
-        u16     cpmt_tcr2;
-        u16     cpmt_tcn1;
-        u16     cpmt_tcn2;
-        u16     cpmt_tmr3;
-        u16     cpmt_tmr4;
-        u16     cpmt_trr3;
-        u16     cpmt_trr4;
-        u16     cpmt_tcr3;
-        u16     cpmt_tcr4;
-        u16     cpmt_tcn3;
-        u16     cpmt_tcn4;
-        u16     cpmt_ter1;
-        u16     cpmt_ter2;
-        u16     cpmt_ter3;
-        u16     cpmt_ter4;
-        u8      res3[584];
-} cpmtimer_cpm2_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-        u8      res0[24];
-        u8      sdma_sdsr;
-        u8      res1[3];
-        u8      sdma_sdmr;
-        u8      res2[3];
-        u8      sdma_idsr1;
-        u8      res3[3];
-        u8      sdma_idmr1;
-        u8      res4[3];
-        u8      sdma_idsr2;
-        u8      res5[3];
-        u8      sdma_idmr2;
-        u8      res6[3];
-        u8      sdma_idsr3;
-        u8      res7[3];
-        u8      sdma_idmr3;
-        u8      res8[3];
-        u8      sdma_idsr4;
-        u8      res9[3];
-        u8      sdma_idmr4;
-        u8      res10[707];
-} sdma_cpm2_t;
-
-/* Fast controllers
-*/
-typedef struct fcc {
-        u32     fcc_gfmr;
-        u32     fcc_fpsmr;
-        u16     fcc_ftodr;
-        u8      res1[2];
-        u16     fcc_fdsr;
-        u8      res2[2];
-        u16     fcc_fcce;
-        u8      res3[2];
-        u16     fcc_fccm;
-        u8      res4[2];
-        u8      fcc_fccs;
-        u8      res5[3];
-        u8      fcc_ftirr_phy[4];
-} fcc_t;
-
-/* Fast controllers continued
- */
-typedef struct fcc_c {
-        u32     fcc_firper;
-        u32     fcc_firer;
-        u32     fcc_firsr_hi;
-        u32     fcc_firsr_lo;
-        u8      fcc_gfemr;
-        u8      res1[15];
-} fcc_c_t;
-
-/* TC Layer
- */
-typedef struct tclayer {
-        u16     tc_tcmode;
-        u16     tc_cdsmr;
-        u16     tc_tcer;
-        u16     tc_rcc;
-        u16     tc_tcmr;
-        u16     tc_fcc;
-        u16     tc_ccc;
-        u16     tc_icc;
-        u16     tc_tcc;
-        u16     tc_ecc;
-        u8      res1[12];
-} tclayer_t;
-
-
-/* I2C
-*/
-typedef struct i2c {
-        u8      i2c_i2mod;
-        u8      res1[3];
-        u8      i2c_i2add;
-        u8      res2[3];
-        u8      i2c_i2brg;
-        u8      res3[3];
-        u8      i2c_i2com;
-        u8      res4[3];
-        u8      i2c_i2cer;
-        u8      res5[3];
-        u8      i2c_i2cmr;
-        u8      res6[331];
-} i2c_cpm2_t;
-
-typedef struct scc {            /* Serial communication channels */
-        u32     scc_gsmrl;
-        u32     scc_gsmrh;
-        u16     scc_psmr;
-        u8      res1[2];
-        u16     scc_todr;
-        u16     scc_dsr;
-        u16     scc_scce;
-        u8      res2[2];
-        u16     scc_sccm;
-        u8      res3;
-        u8      scc_sccs;
-        u8      res4[8];
-} scc_t;
-
-typedef struct smc {            /* Serial management channels */
-        u8      res1[2];
-        u16     smc_smcmr;
-        u8      res2[2];
-        u8      smc_smce;
-        u8      res3[3];
-        u8      smc_smcm;
-        u8      res4[5];
-} smc_t;
-
-/* Serial Peripheral Interface.
-*/
-typedef struct spi_ctrl {
-        u16     spi_spmode;
-        u8      res1[4];
-        u8      spi_spie;
-        u8      res2[3];
-        u8      spi_spim;
-        u8      res3[2];
-        u8      spi_spcom;
-        u8      res4[82];
-} spictl_cpm2_t;
-
-/* CPM Mux.
-*/
-typedef struct cpmux {
-        u8      cmx_si1cr;
-        u8      res1;
-        u8      cmx_si2cr;
-        u8      res2;
-        u32     cmx_fcr;
-        u32     cmx_scr;
-        u8      cmx_smr;
-        u8      res3;
-        u16     cmx_uar;
-        u8      res4[16];
-} cpmux_t;
-
-/* SIRAM control
-*/
-typedef struct siram {
-        u16     si_amr;
-        u16     si_bmr;
-        u16     si_cmr;
-        u16     si_dmr;
-        u8      si_gmr;
-        u8      res1;
-        u8      si_cmdr;
-        u8      res2;
-        u8      si_str;
-        u8      res3;
-        u16     si_rsr;
-} siramctl_t;
-
-typedef struct mcc {
-        u16     mcc_mcce;
-        u8      res1[2];
-        u16     mcc_mccm;
-        u8      res2[2];
-        u8      mcc_mccf;
-        u8      res3[7];
-} mcc_t;
-
-typedef struct comm_proc {
-        u32     cp_cpcr;
-        u32     cp_rccr;
-        u8      res1[14];
-        u16     cp_rter;
-        u8      res2[2];
-        u16     cp_rtmr;
-        u16     cp_rtscr;
-        u8      res3[2];
-        u32     cp_rtsr;
-        u8      res4[12];
-} cpm_cpm2_t;
-
-/* USB Controller.
-*/
-typedef struct usb_ctlr {
-        u8      usb_usmod;
-        u8      usb_usadr;
-        u8      usb_uscom;
-        u8      res1[1];
-        u16     usb_usep1;
-        u16     usb_usep2;
-        u16     usb_usep3;
-        u16     usb_usep4;
-        u8      res2[4];
-        u16     usb_usber;
-        u8      res3[2];
-        u16     usb_usbmr;
-        u8      usb_usbs;
-        u8      res4[7];
-} usb_cpm2_t;
-
-/* ...and the whole thing wrapped up....
-*/
-
-typedef struct immap {
-        /* Some references are into the unique and known dpram spaces,
-         * others are from the generic base.
-         */
-#define im_dprambase    im_dpram1
-        u8              im_dpram1[16*1024];
-        u8              res1[16*1024];
-        u8              im_dpram2[4*1024];
-        u8              res2[8*1024];
-        u8              im_dpram3[4*1024];
-        u8              res3[16*1024];
-
-        sysconf_cpm2_t  im_siu_conf;    /* SIU Configuration */
-        memctl_cpm2_t   im_memctl;      /* Memory Controller */
-        sit_cpm2_t      im_sit;         /* System Integration Timers */
-        pci_cpm2_t      im_pci;         /* PCI Controller */
-        intctl_cpm2_t   im_intctl;      /* Interrupt Controller */
-        car_cpm2_t      im_clkrst;      /* Clocks and reset */
-        iop_cpm2_t      im_ioport;      /* IO Port control/status */
-        cpmtimer_cpm2_t im_cpmtimer;    /* CPM timers */
-        sdma_cpm2_t     im_sdma;        /* SDMA control/status */
-
-        fcc_t           im_fcc[3];      /* Three FCCs */
-        u8              res4z[32];
-        fcc_c_t         im_fcc_c[3];    /* Continued FCCs */
-
-        u8              res4[32];
-
-        tclayer_t       im_tclayer[8];  /* Eight TCLayers */
-        u16             tc_tcgsr;
-        u16             tc_tcger;
-        
-        /* First set of baud rate generators.
-        */
-        u8              res[236];
-        u32             im_brgc5;
-        u32             im_brgc6;
-        u32             im_brgc7;
-        u32             im_brgc8;
-
-        u8              res5[608];
-
-        i2c_cpm2_t      im_i2c;         /* I2C control/status */
-        cpm_cpm2_t      im_cpm;         /* Communication processor */
-
-        /* Second set of baud rate generators.
-        */
-        u32             im_brgc1;
-        u32             im_brgc2;
-        u32             im_brgc3;
-        u32             im_brgc4;
-
-        scc_t           im_scc[4];      /* Four SCCs */
-        smc_t           im_smc[2];      /* Couple of SMCs */
-        spictl_cpm2_t   im_spi;         /* A SPI */
-        cpmux_t         im_cpmux;       /* CPM clock route mux */
-        siramctl_t      im_siramctl1;   /* First SI RAM Control */
-        mcc_t           im_mcc1;        /* First MCC */
-        siramctl_t      im_siramctl2;   /* Second SI RAM Control */
-        mcc_t           im_mcc2;        /* Second MCC */
-        usb_cpm2_t      im_usb;         /* USB Controller */
-
-        u8              res6[1153];
-
-        u16             im_si1txram[256];
-        u8              res7[512];
-        u16             im_si1rxram[256];
-        u8              res8[512];
-        u16             im_si2txram[256];
-        u8              res9[512];
-        u16             im_si2rxram[256];
-        u8              res10[512];
-        u8              res11[4096];
-} cpm2_map_t;
-
-extern cpm2_map_t       *cpm2_immr;
-
-#endif /* __IMMAP_CPM2__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
deleted file mode 100644
index a0d409a5d80f..000000000000
--- a/include/asm-ppc/io.h
+++ /dev/null
@@ -1,502 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_IO_H
-#define _PPC_IO_H
-
-#include <linux/string.h>
-#include <linux/types.h>
-
-#include <asm/page.h>
-#include <asm/byteorder.h>
-#include <asm/synch.h>
-#include <asm/mmu.h>
-
-#define SIO_CONFIG_RA   0x398
-#define SIO_CONFIG_RD   0x399
-
-#define SLOW_DOWN_IO
-
-#define PMAC_ISA_MEM_BASE       0
-#define PMAC_PCI_DRAM_OFFSET    0
-#define CHRP_ISA_IO_BASE        0xf8000000
-#define CHRP_ISA_MEM_BASE       0xf7000000
-#define CHRP_PCI_DRAM_OFFSET    0
-#define PREP_ISA_IO_BASE        0x80000000
-#define PREP_ISA_MEM_BASE       0xc0000000
-#define PREP_PCI_DRAM_OFFSET    0x80000000
-
-#if defined(CONFIG_4xx)
-#include <asm/ibm4xx.h>
-#elif defined(CONFIG_8xx)
-#include <asm/mpc8xx.h>
-#elif defined(CONFIG_8260)
-#include <asm/mpc8260.h>
-#elif !defined(CONFIG_PCI)
-#define _IO_BASE        0
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#else /* Everyone else */
-#define _IO_BASE        isa_io_base
-#define _ISA_MEM_BASE   isa_mem_base
-#define PCI_DRAM_OFFSET pci_dram_offset
-#endif /* Platform-dependent I/O */
-
-#define ___IO_BASE ((void __iomem *)_IO_BASE)
-extern unsigned long isa_io_base;
-extern unsigned long isa_mem_base;
-extern unsigned long pci_dram_offset;
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- *
- * Read operations have additional twi & isync to make sure the read
- * is actually performed (i.e. the data has come back) before we start
- * executing any following instructions.
- */
-extern inline int in_8(const volatile unsigned char __iomem *addr)
-{
-        int ret;
-
-        __asm__ __volatile__(
-                "sync; lbz%U1%X1 %0,%1;\n"
-                "twi 0,%0,0;\n"
-                "isync" : "=r" (ret) : "m" (*addr));
-        return ret;
-}
-
-extern inline void out_8(volatile unsigned char __iomem *addr, int val)
-{
-        __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-extern inline int in_le16(const volatile unsigned short __iomem *addr)
-{
-        int ret;
-
-        __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
-                             "twi 0,%0,0;\n"
-                             "isync" : "=r" (ret) :
-                              "r" (addr), "m" (*addr));
-        return ret;
-}
-
-extern inline int in_be16(const volatile unsigned short __iomem *addr)
-{
-        int ret;
-
-        __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
-                             "twi 0,%0,0;\n"
-                             "isync" : "=r" (ret) : "m" (*addr));
-        return ret;
-}
-
-extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
-                              "r" (val), "r" (addr));
-}
-
-extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-
-extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
-{
-        unsigned ret;
-
-        __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
-                             "twi 0,%0,0;\n"
-                             "isync" : "=r" (ret) :
-                             "r" (addr), "m" (*addr));
-        return ret;
-}
-
-extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
-{
-        unsigned ret;
-
-        __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
-                             "twi 0,%0,0;\n"
-                             "isync" : "=r" (ret) : "m" (*addr));
-        return ret;
-}
-
-extern inline void out_le32(volatile unsigned __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
-                             "r" (val), "r" (addr));
-}
-
-extern inline void out_be32(volatile unsigned __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-#if defined (CONFIG_8260_PCI9)
-#define readb(addr) in_8((volatile u8 *)(addr))
-#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
-#else
-static inline __u8 readb(const volatile void __iomem *addr)
-{
-        return in_8(addr);
-}
-static inline void writeb(__u8 b, volatile void __iomem *addr)
-{
-        out_8(addr, b);
-}
-#endif
-
-#if defined (CONFIG_8260_PCI9)
-/* Use macros if PCI9 workaround enabled */
-#define readw(addr) in_le16((volatile u16 *)(addr))
-#define readl(addr) in_le32((volatile u32 *)(addr))
-#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
-#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
-#else
-static inline __u16 readw(const volatile void __iomem *addr)
-{
-        return in_le16(addr);
-}
-static inline __u32 readl(const volatile void __iomem *addr)
-{
-        return in_le32(addr);
-}
-static inline void writew(__u16 b, volatile void __iomem *addr)
-{
-        out_le16(addr, b);
-}
-static inline void writel(__u32 b, volatile void __iomem *addr)
-{
-        out_le32(addr, b);
-}
-#endif /* CONFIG_8260_PCI9 */
-
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-
-static inline __u8 __raw_readb(const volatile void __iomem *addr)
-{
-        return *(__force volatile __u8 *)(addr);
-}
-static inline __u16 __raw_readw(const volatile void __iomem *addr)
-{
-        return *(__force volatile __u16 *)(addr);
-}
-static inline __u32 __raw_readl(const volatile void __iomem *addr)
-{
-        return *(__force volatile __u32 *)(addr);
-}
-static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
-{
-        *(__force volatile __u8 *)(addr) = b;
-}
-static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
-{
-        *(__force volatile __u16 *)(addr) = b;
-}
-static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
-{
-        *(__force volatile __u32 *)(addr) = b;
-}
-
-#define mmiowb()
-
-/*
- * The insw/outsw/insl/outsl macros don't do byte-swapping.
- * They are only used in practice for transferring buffers which
- * are arrays of bytes, and byte-swapping is not appropriate in
- * that case.  - paulus
- */
-#define insb(port, buf, ns)     _insb((port)+___IO_BASE, (buf), (ns))
-#define outsb(port, buf, ns)    _outsb((port)+___IO_BASE, (buf), (ns))
-#define insw(port, buf, ns)     _insw_ns((port)+___IO_BASE, (buf), (ns))
-#define outsw(port, buf, ns)    _outsw_ns((port)+___IO_BASE, (buf), (ns))
-#define insl(port, buf, nl)     _insl_ns((port)+___IO_BASE, (buf), (nl))
-#define outsl(port, buf, nl)    _outsl_ns((port)+___IO_BASE, (buf), (nl))
-
-#define readsb(a, b, n)         _insb((a), (b), (n))
-#define readsw(a, b, n)         _insw_ns((a), (b), (n))
-#define readsl(a, b, n)         _insl_ns((a), (b), (n))
-#define writesb(a, b, n)        _outsb((a),(b),(n))
-#define writesw(a, b, n)        _outsw_ns((a),(b),(n))
-#define writesl(a, b, n)        _outsl_ns((a),(b),(n))
-
-
-/*
- * On powermacs and 8xx we will get a machine check exception 
- * if we try to read data from a non-existent I/O port. Because
- * the machine check is an asynchronous exception, it isn't
- * well-defined which instruction SRR0 will point to when the
- * exception occurs.
- * With the sequence below (twi; isync; nop), we have found that
- * the machine check occurs on one of the three instructions on
- * all PPC implementations tested so far.  The twi and isync are
- * needed on the 601 (in fact twi; sync works too), the isync and
- * nop are needed on 604[e|r], and any of twi, sync or isync will
- * work on 603[e], 750, 74xx.
- * The twi creates an explicit data dependency on the returned
- * value which seems to be needed to make the 601 wait for the
- * load to finish.
- */
-
-#define __do_in_asm(name, op)                           \
-extern __inline__ unsigned int name(unsigned int port)  \
-{                                                       \
-        unsigned int x;                                 \
-        __asm__ __volatile__(                           \
-                "sync\n"                                \
-                "0:"    op "    %0,0,%1\n"              \
-                "1:     twi     0,%0,0\n"               \
-                "2:     isync\n"                        \
-                "3:     nop\n"                          \
-                "4:\n"                                  \
-                ".section .fixup,\"ax\"\n"              \
-                "5:     li      %0,-1\n"                \
-                "       b       4b\n"                   \
-                ".previous\n"                           \
-                ".section __ex_table,\"a\"\n"           \
-                "       .align  2\n"                    \
-                "       .long   0b,5b\n"                \
-                "       .long   1b,5b\n"                \
-                "       .long   2b,5b\n"                \
-                "       .long   3b,5b\n"                \
-                ".previous"                             \
-                : "=&r" (x)                             \
-                : "r" (port + ___IO_BASE));             \
-        return x;                                       \
-}
-
-#define __do_out_asm(name, op)                          \
-extern __inline__ void name(unsigned int val, unsigned int port) \
-{                                                       \
-        __asm__ __volatile__(                           \
-                "sync\n"                                \
-                "0:" op " %0,0,%1\n"                    \
-                "1:     sync\n"                         \
-                "2:\n"                                  \
-                ".section __ex_table,\"a\"\n"           \
-                "       .align  2\n"                    \
-                "       .long   0b,2b\n"                \
-                "       .long   1b,2b\n"                \
-                ".previous"                             \
-                : : "r" (val), "r" (port + ___IO_BASE));        \
-}
-
-__do_out_asm(outb, "stbx")
-#if defined (CONFIG_8260_PCI9)
-/* in asm cannot be defined if PCI9 workaround is used */
-#define inb(port)               in_8((port)+___IO_BASE)
-#define inw(port)               in_le16((port)+___IO_BASE)
-#define inl(port)               in_le32((port)+___IO_BASE)
-__do_out_asm(outw, "sthbrx")
-__do_out_asm(outl, "stwbrx")
-#else
-__do_in_asm(inb, "lbzx")
-__do_in_asm(inw, "lhbrx")
-__do_in_asm(inl, "lwbrx")
-__do_out_asm(outw, "sthbrx")
-__do_out_asm(outl, "stwbrx")
-
-#endif
-
-#define inb_p(port)             inb((port))
-#define outb_p(val, port)       outb((val), (port))
-#define inw_p(port)             inw((port))
-#define outw_p(val, port)       outw((val), (port))
-#define inl_p(port)             inl((port))
-#define outl_p(val, port)       outl((val), (port))
-
-extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
-extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
-extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
-extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
-extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
-extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
-
-
-#define IO_SPACE_LIMIT ~0
-
-#if defined (CONFIG_8260_PCI9)
-#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
-#else
-static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
-        memset((void __force *)addr, val, count);
-}
-static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
-{
-        memcpy(dst, (void __force *) src, count);
-}
-static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
-        memcpy((void __force *) dst, src, count);
-}
-#endif
-
-/*
- * Map in an area of physical address space, for accessing
- * I/O devices etc.
- */
-extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
-                       unsigned long flags);
-extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
-#ifdef CONFIG_44x
-extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
-#endif
-#define ioremap_nocache(addr, size)     ioremap((addr), (size))
-extern void iounmap(volatile void __iomem *addr);
-extern unsigned long iopa(unsigned long addr);
-extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
-                             unsigned int size, int flags);
-
-/*
- * The PCI bus is inherently Little-Endian.  The PowerPC is being
- * run Big-Endian.  Thus all values which cross the [PCI] barrier
- * must be endian-adjusted.  Also, the local DRAM has a different
- * address from the PCI point of view, thus buffer addresses also
- * have to be modified [mapped] appropriately.
- */
-extern inline unsigned long virt_to_bus(volatile void * address)
-{
-        if (address == (void *)0)
-                return 0;
-        return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
-}
-
-extern inline void * bus_to_virt(unsigned long address)
-{
-        if (address == 0)
-                return NULL;
-        return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
-}
-
-/*
- * Change virtual addresses to physical addresses and vv, for
- * addresses in the area where the kernel has the RAM mapped.
- */
-extern inline unsigned long virt_to_phys(volatile void * address)
-{
-        return (unsigned long) address - KERNELBASE;
-}
-
-extern inline void * phys_to_virt(unsigned long address)
-{
-        return (void *) (address + KERNELBASE);
-}
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
-#define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
-
-/* Enforce in-order execution of data I/O.
- * No distinction between read/write on PPC; use eieio for all three.
- */
-#define iobarrier_rw() eieio()
-#define iobarrier_r()  eieio()
-#define iobarrier_w()  eieio()
-
-/*
- * Here comes the ppc implementation of the IOMAP 
- * interfaces.
- */
-static inline unsigned int ioread8(void __iomem *addr)
-{
-        return readb(addr);
-}
-
-static inline unsigned int ioread16(void __iomem *addr)
-{
-        return readw(addr);
-}
-
-static inline unsigned int ioread32(void __iomem *addr)
-{
-        return readl(addr);
-}
-
-static inline void iowrite8(u8 val, void __iomem *addr)
-{
-        writeb(val, addr);
-}
-
-static inline void iowrite16(u16 val, void __iomem *addr)
-{
-        writew(val, addr);
-}
-
-static inline void iowrite32(u32 val, void __iomem *addr)
-{
-        writel(val, addr);
-}
-
-static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
-{
-        _insb(addr, dst, count);
-}
-
-static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
-{
-        _insw_ns(addr, dst, count);
-}
-
-static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
-{
-        _insl_ns(addr, dst, count);
-}
-
-static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
-{
-        _outsb(addr, src, count);
-}
-
-static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
-{
-        _outsw_ns(addr, src, count);
-}
-
-static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
-{
-        _outsl_ns(addr, src, count);
-}
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-#endif /* _PPC_IO_H */
-
-#ifdef CONFIG_8260_PCI9
-#include <asm/mpc8260_pci9.h>
-#endif
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
-
-#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
-#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
-
-#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
-#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/irq_regs.h b/include/asm-ppc/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-ppc/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-ppc/kdebug.h b/include/asm-ppc/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-ppc/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h
deleted file mode 100644
index b617dac82969..000000000000
--- a/include/asm-ppc/kgdb.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * kgdb.h: Defines and declarations for serial line source level
- *         remote debugging of the Linux kernel using gdb.
- *
- * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifdef __KERNEL__
-#ifndef _PPC_KGDB_H
-#define _PPC_KGDB_H
-
-#ifndef __ASSEMBLY__
-
-/* Things specific to the gen550 backend. */
-struct uart_port;
-
-extern void gen550_progress(char *, unsigned short);
-extern void gen550_kgdb_map_scc(void);
-extern void gen550_init(int, struct uart_port *);
-
-/* Things specific to the pmac backend. */
-extern void zs_kgdb_hook(int tty_num);
-
-/* To init the kgdb engine. (called by serial hook)*/
-extern void set_debug_traps(void);
-
-/* To enter the debugger explicitly. */
-extern void breakpoint(void);
-
-/* For taking exceptions
- * these are defined in traps.c
- */
-extern int (*debugger)(struct pt_regs *regs);
-extern int (*debugger_bpt)(struct pt_regs *regs);
-extern int (*debugger_sstep)(struct pt_regs *regs);
-extern int (*debugger_iabr_match)(struct pt_regs *regs);
-extern int (*debugger_dabr_match)(struct pt_regs *regs);
-extern void (*debugger_fault_handler)(struct pt_regs *regs);
-
-/* What we bring to the party */
-int kgdb_bpt(struct pt_regs *regs);
-int kgdb_sstep(struct pt_regs *regs);
-void kgdb(struct pt_regs *regs);
-int kgdb_iabr_match(struct pt_regs *regs);
-int kgdb_dabr_match(struct pt_regs *regs);
-
-/*
- * external low-level support routines (ie macserial.c)
- */
-extern void kgdb_interruptible(int); /* control interrupts from serial */
-extern void putDebugChar(char);   /* write a single character      */
-extern char getDebugChar(void);   /* read and return a single char */
-
-#endif /* !(__ASSEMBLY__) */
-#endif /* !(_PPC_KGDB_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
deleted file mode 100644
index bf9e05dd54b5..000000000000
--- a/include/asm-ppc/m8260_pci.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * include/asm-ppc/m8260_pci.h
- *
- * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __M8260_PCI_H
-#define __M8260_PCI_H
-
-#include <linux/pci_ids.h>
-
-/*
- * Define the vendor/device ID for the MPC8265.
- */
-#define PCI_DEVICE_ID_MPC8265   ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
-#define PCI_DEVICE_ID_MPC8272   ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
-
-#define M8265_PCIBR0    0x101ac
-#define M8265_PCIBR1    0x101b0
-#define M8265_PCIMSK0   0x101c4
-#define M8265_PCIMSK1   0x101c8
-
-/* Bit definitions for PCIBR registers */
-
-#define PCIBR_ENABLE        0x00000001
-
-/* Bit definitions for PCIMSK registers */
-
-#define PCIMSK_32KiB         0xFFFF8000  /* Size of window, smallest */
-#define PCIMSK_64KiB         0xFFFF0000
-#define PCIMSK_128KiB        0xFFFE0000
-#define PCIMSK_256KiB        0xFFFC0000
-#define PCIMSK_512KiB        0xFFF80000
-#define PCIMSK_1MiB          0xFFF00000
-#define PCIMSK_2MiB          0xFFE00000
-#define PCIMSK_4MiB          0xFFC00000
-#define PCIMSK_8MiB          0xFF800000
-#define PCIMSK_16MiB         0xFF000000
-#define PCIMSK_32MiB         0xFE000000
-#define PCIMSK_64MiB         0xFC000000
-#define PCIMSK_128MiB        0xF8000000
-#define PCIMSK_256MiB        0xF0000000
-#define PCIMSK_512MiB        0xE0000000
-#define PCIMSK_1GiB          0xC0000000  /* Size of window, largest */
-
-
-#define M826X_SCCR_PCI_MODE_EN 0x100
-
-
-/*
- * Outbound ATU registers (3 sets). These registers control how 60x bus (local) 
- * addresses are translated to PCI addresses when the MPC826x is a PCI bus 
- * master (initiator).
- */
-
-#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
-#define POTAR_REG1          0x10818
-#define POTAR_REG2          0x10830
-
-#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
-#define POBAR_REG1          0x10820
-#define POBAR_REG2          0x10838
-
-#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
-#define POCMR_REG1          0x10828
-#define POCMR_REG2          0x10840
-
-/* Bit definitions for POMCR registers */
-
-#define POCMR_MASK_4KiB      0x000FFFFF
-#define POCMR_MASK_8KiB      0x000FFFFE
-#define POCMR_MASK_16KiB     0x000FFFFC
-#define POCMR_MASK_32KiB     0x000FFFF8
-#define POCMR_MASK_64KiB     0x000FFFF0
-#define POCMR_MASK_128KiB    0x000FFFE0
-#define POCMR_MASK_256KiB    0x000FFFC0
-#define POCMR_MASK_512KiB    0x000FFF80
-#define POCMR_MASK_1MiB      0x000FFF00
-#define POCMR_MASK_2MiB      0x000FFE00
-#define POCMR_MASK_4MiB      0x000FFC00
-#define POCMR_MASK_8MiB      0x000FF800
-#define POCMR_MASK_16MiB     0x000FF000
-#define POCMR_MASK_32MiB     0x000FE000
-#define POCMR_MASK_64MiB     0x000FC000
-#define POCMR_MASK_128MiB    0x000F8000
-#define POCMR_MASK_256MiB    0x000F0000
-#define POCMR_MASK_512MiB    0x000E0000
-#define POCMR_MASK_1GiB      0x000C0000
-
-#define POCMR_ENABLE        0x80000000
-#define POCMR_PCI_IO        0x40000000
-#define POCMR_PREFETCH_EN   0x20000000
-
-/* Soft PCI reset */
-
-#define PCI_GCR_REG         0x10880
-
-/* Bit definitions for PCI_GCR registers */
-
-#define PCIGCR_PCI_BUS_EN   0x1
-
-#define PCI_EMR_REG         0x10888
-/*
- * Inbound ATU registers (2 sets). These registers control how PCI addresses 
- * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
- */
-
-#define PITAR_REG1          0x108D0
-#define PIBAR_REG1          0x108D8
-#define PICMR_REG1          0x108E0
-#define PITAR_REG0          0x108E8
-#define PIBAR_REG0          0x108F0
-#define PICMR_REG0          0x108F8
-
-/* Bit definitions for PCI Inbound Comparison Mask registers */
-
-#define PICMR_MASK_4KiB       0x000FFFFF
-#define PICMR_MASK_8KiB       0x000FFFFE
-#define PICMR_MASK_16KiB      0x000FFFFC
-#define PICMR_MASK_32KiB      0x000FFFF8
-#define PICMR_MASK_64KiB      0x000FFFF0
-#define PICMR_MASK_128KiB     0x000FFFE0
-#define PICMR_MASK_256KiB     0x000FFFC0
-#define PICMR_MASK_512KiB     0x000FFF80
-#define PICMR_MASK_1MiB       0x000FFF00
-#define PICMR_MASK_2MiB       0x000FFE00
-#define PICMR_MASK_4MiB       0x000FFC00
-#define PICMR_MASK_8MiB       0x000FF800
-#define PICMR_MASK_16MiB      0x000FF000
-#define PICMR_MASK_32MiB      0x000FE000
-#define PICMR_MASK_64MiB      0x000FC000
-#define PICMR_MASK_128MiB     0x000F8000
-#define PICMR_MASK_256MiB     0x000F0000
-#define PICMR_MASK_512MiB     0x000E0000
-#define PICMR_MASK_1GiB       0x000C0000
-
-#define PICMR_ENABLE         0x80000000
-#define PICMR_NO_SNOOP_EN    0x40000000
-#define PICMR_PREFETCH_EN    0x20000000
-
-/* PCI error Registers */
-
-#define PCI_ERROR_STATUS_REG            0x10884
-#define PCI_ERROR_MASK_REG              0x10888
-#define PCI_ERROR_CONTROL_REG           0x1088C
-#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
-#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
-#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
-
-/* PCI error Register bit defines */
-
-#define PCI_ERROR_PCI_ADDR_PAR                  0x00000001
-#define PCI_ERROR_PCI_DATA_PAR_WR               0x00000002
-#define PCI_ERROR_PCI_DATA_PAR_RD               0x00000004
-#define PCI_ERROR_PCI_NO_RSP                    0x00000008
-#define PCI_ERROR_PCI_TAR_ABT                   0x00000010
-#define PCI_ERROR_PCI_SERR                      0x00000020
-#define PCI_ERROR_PCI_PERR_RD                   0x00000040
-#define PCI_ERROR_PCI_PERR_WR                   0x00000080
-#define PCI_ERROR_I2O_OFQO                      0x00000100
-#define PCI_ERROR_I2O_IPQO                      0x00000200
-#define PCI_ERROR_IRA                           0x00000400
-#define PCI_ERROR_NMI                           0x00000800
-#define PCI_ERROR_I2O_DBMC                      0x00001000
-
-/*
- * Register pair used to generate configuration cycles on the PCI bus
- * and access the MPC826x's own PCI configuration registers.
- */
-
-#define PCI_CFG_ADDR_REG     0x10900
-#define PCI_CFG_DATA_REG     0x10904
-
-/* Bus parking decides where the bus control sits when idle */
-/* If modifying memory controllers for PCI park on the core */
-
-#define PPC_ACR_BUS_PARK_CORE 0x6
-#define PPC_ACR_BUS_PARK_PCI  0x3
-
-#endif /* __M8260_PCI_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
deleted file mode 100644
index a20b499b0186..000000000000
--- a/include/asm-ppc/machdep.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_MACHDEP_H
-#define _PPC_MACHDEP_H
-
-#include <linux/init.h>
-#include <linux/kexec.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-struct pt_regs;
-struct pci_bus; 
-struct pci_dev;
-struct seq_file;
-struct file;
-
-/*
- * This is for compatibility with ARCH=powerpc.
- */
-#define machine_is(x)   __MACHINE_IS_##x
-#define __MACHINE_IS_powermac   0
-#define __MACHINE_IS_chrp       0
-#ifdef CONFIG_PPC_PREP
-#define __MACHINE_IS_prep       1
-#else
-#define __MACHINE_IS_prep       0
-#endif
-
-/* We export this macro for external modules like Alsa to know if
- * ppc_md.feature_call is implemented or not
- */
-#define CONFIG_PPC_HAS_FEATURE_CALLS
-
-struct machdep_calls {
-        void            (*setup_arch)(void);
-        /* Optional, may be NULL. */
-        int             (*show_cpuinfo)(struct seq_file *m);
-        int             (*show_percpuinfo)(struct seq_file *m, int i);
-        /* Optional, may be NULL. */
-        unsigned int    (*irq_canonicalize)(unsigned int irq);
-        void            (*init_IRQ)(void);
-        int             (*get_irq)(void);
-        
-        /* A general init function, called by ppc_init in init/main.c.
-           May be NULL. DEPRECATED ! */
-        void            (*init)(void);
-        /* For compatibility with merged platforms */
-        void            (*init_early)(void);
-
-        void            (*restart)(char *cmd);
-        void            (*power_off)(void);
-        void            (*halt)(void);
-
-        void            (*idle_loop)(void);
-        void            (*power_save)(void);
-
-        long            (*time_init)(void); /* Optional, may be NULL */
-        int             (*set_rtc_time)(unsigned long nowtime);
-        unsigned long   (*get_rtc_time)(void);
-        unsigned char   (*rtc_read_val)(int addr);
-        void            (*rtc_write_val)(int addr, unsigned char val);
-        void            (*calibrate_decr)(void);
-
-        void            (*heartbeat)(void);
-        unsigned long   heartbeat_reset;
-        unsigned long   heartbeat_count;
-
-        unsigned long   (*find_end_of_memory)(void);
-        void            (*setup_io_mappings)(void);
-
-        void            (*early_serial_map)(void);
-        void            (*progress)(char *, unsigned short);
-        void            (*kgdb_map_scc)(void);
-
-        unsigned char   (*nvram_read_val)(int addr);
-        void            (*nvram_write_val)(int addr, unsigned char val);
-        void            (*nvram_sync)(void);
-
-        /*
-         * optional PCI "hooks"
-         */
-
-        /* Called after scanning the bus, before allocating resources */
-        void (*pcibios_fixup)(void);
-
-        /* Called after PPC generic resource fixup to perform
-           machine specific fixups */
-        void (*pcibios_fixup_resources)(struct pci_dev *);
-
-        /* Called for each PCI bus in the system when it's probed */
-        void (*pcibios_fixup_bus)(struct pci_bus *);
-
-        /* Called when pci_enable_device() is called (initial=0) or
-         * when a device with no assigned resource is found (initial=1).
-         * Returns 0 to allow assignment/enabling of the device. */
-        int  (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
-
-        /* For interrupt routing */
-        unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
-        int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
-
-        /* Called in indirect_* to avoid touching devices */
-        int (*pci_exclude_device)(unsigned char, unsigned char);
-
-        /* Called at then very end of pcibios_init() */
-        void (*pcibios_after_init)(void);
-
-        /* Get access protection for /dev/mem */
-        pgprot_t        (*phys_mem_access_prot)(struct file *file,
-                                                unsigned long pfn,
-                                                unsigned long size,
-                                                pgprot_t vma_prot);
-
-        /* Motherboard/chipset features. This is a kind of general purpose
-         * hook used to control some machine specific features (like reset
-         * lines, chip power control, etc...).
-         */
-        long (*feature_call)(unsigned int feature, ...);
-
-#ifdef CONFIG_SMP
-        /* functions for dealing with other cpus */
-        struct smp_ops_t *smp_ops;
-#endif /* CONFIG_SMP */
-
-#ifdef CONFIG_KEXEC
-        /* Called to shutdown machine specific hardware not already controlled
-         * by other drivers.
-         * XXX Should we move this one out of kexec scope?
-         */
-        void (*machine_shutdown)(void);
-
-        /* Called to do the minimal shutdown needed to run a kexec'd kernel
-         * to run successfully.
-         * XXX Should we move this one out of kexec scope?
-         */
-        void (*machine_crash_shutdown)(void);
-
-        /* Called to do what every setup is needed on image and the
-         * reboot code buffer. Returns 0 on success.
-         * Provide your own (maybe dummy) implementation if your platform
-         * claims to support kexec.
-         */
-        int (*machine_kexec_prepare)(struct kimage *image);
-
-        /* Called to handle any machine specific cleanup on image */
-        void (*machine_kexec_cleanup)(struct kimage *image);
-
-        /* Called to perform the _real_ kexec.
-         * Do NOT allocate memory or fail here. We are past the point of
-         * no return.
-         */
-        void (*machine_kexec)(struct kimage *image);
-#endif /* CONFIG_KEXEC */
-};
-
-extern struct machdep_calls ppc_md;
-extern char cmd_line[COMMAND_LINE_SIZE];
-
-extern void setup_pci_ptrs(void);
-
-#ifdef CONFIG_SMP
-struct smp_ops_t {
-        void  (*message_pass)(int target, int msg);
-        int   (*probe)(void);
-        void  (*kick_cpu)(int nr);
-        void  (*setup_cpu)(int nr);
-        void  (*space_timers)(int nr);
-        void  (*take_timebase)(void);
-        void  (*give_timebase)(void);
-};
-
-/* Poor default implementations */
-extern void __devinit smp_generic_give_timebase(void);
-extern void __devinit smp_generic_take_timebase(void);
-#endif /* CONFIG_SMP */
-
-#endif /* _PPC_MACHDEP_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h
deleted file mode 100644
index 9a9b6b42b4b4..000000000000
--- a/include/asm-ppc/md.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * md.h: High speed xor_block operation for RAID4/5
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MD_H
-#define __ASM_MD_H
-
-/* #define HAVE_ARCH_XORBLOCK */
-
-#define MD_XORBLOCK_ALIGNMENT   sizeof(long)
-
-#endif /* __ASM_MD_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h
deleted file mode 100644
index 6a0ed6fc2d56..000000000000
--- a/include/asm-ppc/mk48t59.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Registers for the mk48t59 real-time-clock
- */
-
-#ifndef _PPC_MK48T59_H
-#define _PPC_MK48T59_H
-
-/* RTC Offsets */
-
-#define MK48T59_RTC_SECONDS             0x1FF9
-#define MK48T59_RTC_MINUTES             0x1FFA
-#define MK48T59_RTC_HOURS               0x1FFB
-#define MK48T59_RTC_DAY_OF_WEEK         0x1FFC
-#define MK48T59_RTC_DAY_OF_MONTH        0x1FFD
-#define MK48T59_RTC_MONTH               0x1FFE
-#define MK48T59_RTC_YEAR                0x1FFF
-
-#define MK48T59_RTC_CONTROLA            0x1FF8
-#define MK48T59_RTC_CA_WRITE            0x80
-#define MK48T59_RTC_CA_READ             0x40
-#define MK48T59_RTC_CA_CALIB_SIGN       0x20
-#define MK48T59_RTC_CA_CALIB_MASK       0x1f
-
-#define MK48T59_RTC_CONTROLB            0x1FF9
-#define MK48T59_RTC_CB_STOP             0x80
-
-#endif /* _PPC_MK48T59_H */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
deleted file mode 100644
index d76ef098ed37..000000000000
--- a/include/asm-ppc/mmu.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
- * PowerPC memory management structures
- */
-
-#ifdef __KERNEL__
-#ifndef _PPC_MMU_H_
-#define _PPC_MMU_H_
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Define physical address type.  Machines using split size
- * virtual/physical addressing like 32-bit virtual / 36-bit
- * physical need a larger than native word size type. -Matt
- */
-#ifndef CONFIG_PHYS_64BIT
-#define PHYS_FMT        "%.8lx"
-#else
-extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
-#define PHYS_FMT        "%16Lx"
-#endif
-
-typedef struct {
-        unsigned long id;
-        unsigned long vdso_base;
-} mm_context_t;
-
-/* Hardware Page Table Entry */
-typedef struct _PTE {
-        unsigned long v:1;      /* Entry is valid */
-        unsigned long vsid:24;  /* Virtual segment identifier */
-        unsigned long h:1;      /* Hash algorithm indicator */
-        unsigned long api:6;    /* Abbreviated page index */
-        unsigned long rpn:20;   /* Real (physical) page number */
-        unsigned long    :3;    /* Unused */
-        unsigned long r:1;      /* Referenced */
-        unsigned long c:1;      /* Changed */
-        unsigned long w:1;      /* Write-thru cache mode */
-        unsigned long i:1;      /* Cache inhibited */
-        unsigned long m:1;      /* Memory coherence */
-        unsigned long g:1;      /* Guarded */
-        unsigned long  :1;      /* Unused */
-        unsigned long pp:2;     /* Page protection */
-} PTE;
-
-/* Values for PP (assumes Ks=0, Kp=1) */
-#define PP_RWXX 0       /* Supervisor read/write, User none */
-#define PP_RWRX 1       /* Supervisor read/write, User read */
-#define PP_RWRW 2       /* Supervisor read/write, User read/write */
-#define PP_RXRX 3       /* Supervisor read,       User read */
-
-/* Segment Register */
-typedef struct _SEGREG {
-        unsigned long t:1;      /* Normal or I/O  type */
-        unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
-        unsigned long kp:1;     /* User 'key' (normally 1) */
-        unsigned long n:1;      /* No-execute */
-        unsigned long :4;       /* Unused */
-        unsigned long vsid:24;  /* Virtual Segment Identifier */
-} SEGREG;
-
-/* Block Address Translation (BAT) Registers */
-typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
-        unsigned long bepi:15;  /* Effective page index (virtual address) */
-        unsigned long :8;       /* unused */
-        unsigned long w:1;
-        unsigned long i:1;      /* Cache inhibit */
-        unsigned long m:1;      /* Memory coherence */
-        unsigned long ks:1;     /* Supervisor key (normally 0) */
-        unsigned long kp:1;     /* User key (normally 1) */
-        unsigned long pp:2;     /* Page access protections */
-} P601_BATU;
-
-typedef struct _BATU {          /* Upper part of BAT (all except 601) */
-        unsigned long bepi:15;  /* Effective page index (virtual address) */
-        unsigned long :4;       /* Unused */
-        unsigned long bl:11;    /* Block size mask */
-        unsigned long vs:1;     /* Supervisor valid */
-        unsigned long vp:1;     /* User valid */
-} BATU;
-
-typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
-        unsigned long brpn:15;  /* Real page index (physical address) */
-        unsigned long :10;      /* Unused */
-        unsigned long v:1;      /* Valid bit */
-        unsigned long bl:6;     /* Block size mask */
-} P601_BATL;
-
-typedef struct _BATL {          /* Lower part of BAT (all except 601) */
-        unsigned long brpn:15;  /* Real page index (physical address) */
-        unsigned long :10;      /* Unused */
-        unsigned long w:1;      /* Write-thru cache */
-        unsigned long i:1;      /* Cache inhibit */
-        unsigned long m:1;      /* Memory coherence */
-        unsigned long g:1;      /* Guarded (MBZ in IBAT) */
-        unsigned long :1;       /* Unused */
-        unsigned long pp:2;     /* Page access protections */
-} BATL;
-
-typedef struct _BAT {
-        BATU batu;              /* Upper register */
-        BATL batl;              /* Lower register */
-} BAT;
-
-typedef struct _P601_BAT {
-        P601_BATU batu;         /* Upper register */
-        P601_BATL batl;         /* Lower register */
-} P601_BAT;
-
-#endif /* __ASSEMBLY__ */
-
-/* Block size masks */
-#define BL_128K 0x000
-#define BL_256K 0x001
-#define BL_512K 0x003
-#define BL_1M   0x007
-#define BL_2M   0x00F
-#define BL_4M   0x01F
-#define BL_8M   0x03F
-#define BL_16M  0x07F
-#define BL_32M  0x0FF
-#define BL_64M  0x1FF
-#define BL_128M 0x3FF
-#define BL_256M 0x7FF
-
-/* BAT Access Protection */
-#define BPP_XX  0x00            /* No access */
-#define BPP_RX  0x01            /* Read only */
-#define BPP_RW  0x02            /* Read/write */
-
-/* Control/status registers for the MPC8xx.
- * A write operation to these registers causes serialized access.
- * During software tablewalk, the registers used perform mask/shift-add
- * operations when written/read.  A TLB entry is created when the Mx_RPN
- * is written, and the contents of several registers are used to
- * create the entry.
- */
-#define SPRN_MI_CTR     784     /* Instruction TLB control register */
-#define MI_GPM          0x80000000      /* Set domain manager mode */
-#define MI_PPM          0x40000000      /* Set subpage protection */
-#define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
-#define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
-#define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
-#define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
-#define MI_RESETVAL     0x00000000      /* Value of register at reset */
-
-/* These are the Ks and Kp from the PowerPC books.  For proper operation,
- * Ks = 0, Kp = 1.
- */
-#define SPRN_MI_AP      786
-#define MI_Ks           0x80000000      /* Should not be set */
-#define MI_Kp           0x40000000      /* Should always be set */
-
-/* The effective page number register.  When read, contains the information
- * about the last instruction TLB miss.  When MI_RPN is written, bits in
- * this register are used to create the TLB entry.
- */
-#define SPRN_MI_EPN     787
-#define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
-#define MI_EVALID       0x00000200      /* Entry is valid */
-#define MI_ASIDMASK     0x0000000f      /* ASID match value */
-                                        /* Reset value is undefined */
-
-/* A "level 1" or "segment" or whatever you want to call it register.
- * For the instruction TLB, it contains bits that get loaded into the
- * TLB entry when the MI_RPN is written.
- */
-#define SPRN_MI_TWC     789
-#define MI_APG          0x000001e0      /* Access protection group (0) */
-#define MI_GUARDED      0x00000010      /* Guarded storage */
-#define MI_PSMASK       0x0000000c      /* Mask of page size bits */
-#define MI_PS8MEG       0x0000000c      /* 8M page size */
-#define MI_PS512K       0x00000004      /* 512K page size */
-#define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
-#define MI_SVALID       0x00000001      /* Segment entry is valid */
-                                        /* Reset value is undefined */
-
-/* Real page number.  Defined by the pte.  Writing this register
- * causes a TLB entry to be created for the instruction TLB, using
- * additional information from the MI_EPN, and MI_TWC registers.
- */
-#define SPRN_MI_RPN     790
-
-/* Define an RPN value for mapping kernel memory to large virtual
- * pages for boot initialization.  This has real page number of 0,
- * large page size, shared page, cache enabled, and valid.
- * Also mark all subpages valid and write access.
- */
-#define MI_BOOTINIT     0x000001fd
-
-#define SPRN_MD_CTR     792     /* Data TLB control register */
-#define MD_GPM          0x80000000      /* Set domain manager mode */
-#define MD_PPM          0x40000000      /* Set subpage protection */
-#define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
-#define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
-#define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
-#define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
-#define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
-#define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
-#define MD_RESETVAL     0x04000000      /* Value of register at reset */
-
-#define SPRN_M_CASID    793     /* Address space ID (context) to match */
-#define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
-
-
-/* These are the Ks and Kp from the PowerPC books.  For proper operation,
- * Ks = 0, Kp = 1.
- */
-#define SPRN_MD_AP      794
-#define MD_Ks           0x80000000      /* Should not be set */
-#define MD_Kp           0x40000000      /* Should always be set */
-
-/* The effective page number register.  When read, contains the information
- * about the last instruction TLB miss.  When MD_RPN is written, bits in
- * this register are used to create the TLB entry.
- */
-#define SPRN_MD_EPN     795
-#define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
-#define MD_EVALID       0x00000200      /* Entry is valid */
-#define MD_ASIDMASK     0x0000000f      /* ASID match value */
-                                        /* Reset value is undefined */
-
-/* The pointer to the base address of the first level page table.
- * During a software tablewalk, reading this register provides the address
- * of the entry associated with MD_EPN.
- */
-#define SPRN_M_TWB      796
-#define M_L1TB          0xfffff000      /* Level 1 table base address */
-#define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
-                                        /* Reset value is undefined */
-
-/* A "level 1" or "segment" or whatever you want to call it register.
- * For the data TLB, it contains bits that get loaded into the TLB entry
- * when the MD_RPN is written.  It is also provides the hardware assist
- * for finding the PTE address during software tablewalk.
- */
-#define SPRN_MD_TWC     797
-#define MD_L2TB         0xfffff000      /* Level 2 table base address */
-#define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
-#define MD_APG          0x000001e0      /* Access protection group (0) */
-#define MD_GUARDED      0x00000010      /* Guarded storage */
-#define MD_PSMASK       0x0000000c      /* Mask of page size bits */
-#define MD_PS8MEG       0x0000000c      /* 8M page size */
-#define MD_PS512K       0x00000004      /* 512K page size */
-#define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
-#define MD_WT           0x00000002      /* Use writethrough page attribute */
-#define MD_SVALID       0x00000001      /* Segment entry is valid */
-                                        /* Reset value is undefined */
-
-
-/* Real page number.  Defined by the pte.  Writing this register
- * causes a TLB entry to be created for the data TLB, using
- * additional information from the MD_EPN, and MD_TWC registers.
- */
-#define SPRN_MD_RPN     798
-
-/* This is a temporary storage register that could be used to save
- * a processor working register during a tablewalk.
- */
-#define SPRN_M_TW       799
-
-/*
- * At present, all PowerPC 400-class processors share a similar TLB
- * architecture. The instruction and data sides share a unified,
- * 64-entry, fully-associative TLB which is maintained totally under
- * software control. In addition, the instruction side has a
- * hardware-managed, 4-entry, fully- associative TLB which serves as a
- * first level to the shared TLB. These two TLBs are known as the UTLB
- * and ITLB, respectively.
- */
-
-#define        PPC4XX_TLB_SIZE 64
-
-/*
- * TLB entries are defined by a "high" tag portion and a "low" data
- * portion.  On all architectures, the data portion is 32-bits.
- *
- * TLB entries are managed entirely under software control by reading,
- * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
- * instructions.
- */
-
-#define TLB_LO          1
-#define TLB_HI          0
-
-#define TLB_DATA        TLB_LO
-#define TLB_TAG         TLB_HI
-
-/* Tag portion */
-
-#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
-#define TLB_PAGESZ_MASK 0x00000380
-#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
-#define   PAGESZ_1K             0
-#define   PAGESZ_4K             1
-#define   PAGESZ_16K            2
-#define   PAGESZ_64K            3
-#define   PAGESZ_256K           4
-#define   PAGESZ_1M             5
-#define   PAGESZ_4M             6
-#define   PAGESZ_16M            7
-#define TLB_VALID       0x00000040      /* Entry is valid */
-
-/* Data portion */
-
-#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
-#define TLB_PERM_MASK   0x00000300
-#define TLB_EX          0x00000200      /* Instruction execution allowed */
-#define TLB_WR          0x00000100      /* Writes permitted */
-#define TLB_ZSEL_MASK   0x000000F0
-#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
-#define TLB_ATTR_MASK   0x0000000F
-#define TLB_W           0x00000008      /* Caching is write-through */
-#define TLB_I           0x00000004      /* Caching is inhibited */
-#define TLB_M           0x00000002      /* Memory is coherent */
-#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
-
-/*
- * PPC440 support
- */
-#define PPC44x_MMUCR_TID        0x000000ff
-#define PPC44x_MMUCR_STS        0x00010000
-
-#define PPC44x_TLB_PAGEID       0
-#define PPC44x_TLB_XLAT         1
-#define PPC44x_TLB_ATTRIB       2
-
-/* Page identification fields */
-#define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
-#define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
-#define PPC44x_TLB_TS           0x00000100      /* Translation address space */
-#define PPC44x_TLB_1K           0x00000000      /* Page sizes */
-#define PPC44x_TLB_4K           0x00000010
-#define PPC44x_TLB_16K          0x00000020
-#define PPC44x_TLB_64K          0x00000030
-#define PPC44x_TLB_256K         0x00000040
-#define PPC44x_TLB_1M           0x00000050
-#define PPC44x_TLB_16M          0x00000070
-#define PPC44x_TLB_256M         0x00000090
-
-/* Translation fields */
-#define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
-#define PPC44x_TLB_ERPN_MASK    0x0000000f
-
-/* Storage attribute and access control fields */
-#define PPC44x_TLB_ATTR_MASK    0x0000ff80
-#define PPC44x_TLB_U0           0x00008000      /* User 0 */
-#define PPC44x_TLB_U1           0x00004000      /* User 1 */
-#define PPC44x_TLB_U2           0x00002000      /* User 2 */
-#define PPC44x_TLB_U3           0x00001000      /* User 3 */
-#define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
-#define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
-#define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
-#define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
-#define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
-
-#define PPC44x_TLB_PERM_MASK    0x0000003f
-#define PPC44x_TLB_UX           0x00000020      /* User execution */
-#define PPC44x_TLB_UW           0x00000010      /* User write */
-#define PPC44x_TLB_UR           0x00000008      /* User read */
-#define PPC44x_TLB_SX           0x00000004      /* Super execution */
-#define PPC44x_TLB_SW           0x00000002      /* Super write */
-#define PPC44x_TLB_SR           0x00000001      /* Super read */
-
-/* Book-E defined page sizes */
-#define BOOKE_PAGESZ_1K         0
-#define BOOKE_PAGESZ_4K         1
-#define BOOKE_PAGESZ_16K        2
-#define BOOKE_PAGESZ_64K        3
-#define BOOKE_PAGESZ_256K       4
-#define BOOKE_PAGESZ_1M         5
-#define BOOKE_PAGESZ_4M         6
-#define BOOKE_PAGESZ_16M        7
-#define BOOKE_PAGESZ_64M        8
-#define BOOKE_PAGESZ_256M       9
-#define BOOKE_PAGESZ_1GB        10
-#define BOOKE_PAGESZ_4GB        11
-#define BOOKE_PAGESZ_16GB       12
-#define BOOKE_PAGESZ_64GB       13
-#define BOOKE_PAGESZ_256GB      14
-#define BOOKE_PAGESZ_1TB        15
-
-#ifndef CONFIG_SERIAL_TEXT_DEBUG
-#define PPC44x_EARLY_TLBS       1
-#else
-#define PPC44x_EARLY_TLBS       2
-#endif
-
-/*
- * Freescale Book-E MMU support
- */
-
-#define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
-#define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
-#define MAS0_NV(x)      ((x) & 0x00000FFF)
-
-#define MAS1_VALID      0x80000000
-#define MAS1_IPROT      0x40000000
-#define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
-#define MAS1_TS         0x00001000
-#define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
-
-#define MAS2_EPN        0xFFFFF000
-#define MAS2_X0         0x00000040
-#define MAS2_X1         0x00000020
-#define MAS2_W          0x00000010
-#define MAS2_I          0x00000008
-#define MAS2_M          0x00000004
-#define MAS2_G          0x00000002
-#define MAS2_E          0x00000001
-
-#define MAS3_RPN        0xFFFFF000
-#define MAS3_U0         0x00000200
-#define MAS3_U1         0x00000100
-#define MAS3_U2         0x00000080
-#define MAS3_U3         0x00000040
-#define MAS3_UX         0x00000020
-#define MAS3_SX         0x00000010
-#define MAS3_UW         0x00000008
-#define MAS3_SW         0x00000004
-#define MAS3_UR         0x00000002
-#define MAS3_SR         0x00000001
-
-#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
-#define MAS4_TIDDSEL    0x000F0000
-#define MAS4_TSIZED(x)  MAS1_TSIZE(x)
-#define MAS4_X0D        0x00000040
-#define MAS4_X1D        0x00000020
-#define MAS4_WD         0x00000010
-#define MAS4_ID         0x00000008
-#define MAS4_MD         0x00000004
-#define MAS4_GD         0x00000002
-#define MAS4_ED         0x00000001
-
-#define MAS6_SPID0      0x3FFF0000
-#define MAS6_SPID1      0x00007FFE
-#define MAS6_SAS        0x00000001
-#define MAS6_SPID       MAS6_SPID0
-
-#define MAS7_RPN        0xFFFFFFFF
-
-#endif /* _PPC_MMU_H_ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
deleted file mode 100644
index 9f097e25b169..000000000000
--- a/include/asm-ppc/mmu_context.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifdef __KERNEL__
-#ifndef __PPC_MMU_CONTEXT_H
-#define __PPC_MMU_CONTEXT_H
-
-#include <linux/bitops.h>
-
-#include <asm/atomic.h>
-#include <asm/mmu.h>
-#include <asm/cputable.h>
-#include <asm-generic/mm_hooks.h>
-
-/*
- * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
- * (virtual segment identifiers) for each context.  Although the
- * hardware supports 24-bit VSIDs, and thus >1 million contexts,
- * we only use 32,768 of them.  That is ample, since there can be
- * at most around 30,000 tasks in the system anyway, and it means
- * that we can use a bitmap to indicate which contexts are in use.
- * Using a bitmap means that we entirely avoid all of the problems
- * that we used to have when the context number overflowed,
- * particularly on SMP systems.
- *  -- paulus.
- */
-
-/*
- * This function defines the mapping from contexts to VSIDs (virtual
- * segment IDs).  We use a skew on both the context and the high 4 bits
- * of the 32-bit virtual address (the "effective segment ID") in order
- * to spread out the entries in the MMU hash table.  Note, if this
- * function is changed then arch/ppc/mm/hashtable.S will have to be
- * changed to correspond.
- */
-#define CTX_TO_VSID(ctx, va)    (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
-                                 & 0xffffff)
-
-/*
-   The MPC8xx has only 16 contexts.  We rotate through them on each
-   task switch.  A better way would be to keep track of tasks that
-   own contexts, and implement an LRU usage.  That way very active
-   tasks don't always have to pay the TLB reload overhead.  The
-   kernel pages are mapped shared, so the kernel can run on behalf
-   of any task that makes a kernel entry.  Shared does not mean they
-   are not protected, just that the ASID comparison is not performed.
-        -- Dan
-
-   The IBM4xx has 256 contexts, so we can just rotate through these
-   as a way of "switching" contexts.  If the TID of the TLB is zero,
-   the PID/TID comparison is disabled, so we can use a TID of zero
-   to represent all kernel pages as shared among all contexts.
-        -- Dan
- */
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#ifdef CONFIG_8xx
-#define NO_CONTEXT              16
-#define LAST_CONTEXT            15
-#define FIRST_CONTEXT           0
-
-#elif defined(CONFIG_4xx)
-#define NO_CONTEXT              256
-#define LAST_CONTEXT            255
-#define FIRST_CONTEXT           1
-
-#else
-
-/* PPC 6xx, 7xx CPUs */
-#define NO_CONTEXT              ((unsigned long) -1)
-#define LAST_CONTEXT            32767
-#define FIRST_CONTEXT           1
-#endif
-
-/*
- * Set the current MMU context.
- * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
- * loading up the segment registers for the user part of the address space.
- *
- * Since the PGD is immediately available, it is much faster to simply
- * pass this along as a second parameter, which is required for 8xx and
- * can be used for debugging on all processors (if you happen to have
- * an Abatron).
- */
-extern void set_context(unsigned long contextid, pgd_t *pgd);
-
-/*
- * Bitmap of contexts in use.
- * The size of this bitmap is LAST_CONTEXT + 1 bits.
- */
-extern unsigned long context_map[];
-
-/*
- * This caches the next context number that we expect to be free.
- * Its use is an optimization only, we can't rely on this context
- * number to be free, but it usually will be.
- */
-extern unsigned long next_mmu_context;
-
-/*
- * If we don't have sufficient contexts to give one to every task
- * that could be in the system, we need to be able to steal contexts.
- * These variables support that.
- */
-#if LAST_CONTEXT < 30000
-#define FEW_CONTEXTS    1
-extern atomic_t nr_free_contexts;
-extern struct mm_struct *context_mm[LAST_CONTEXT+1];
-extern void steal_context(void);
-#endif
-
-/*
- * Get a new mmu context for the address space described by `mm'.
- */
-static inline void get_mmu_context(struct mm_struct *mm)
-{
-        unsigned long ctx;
-
-        if (mm->context.id != NO_CONTEXT)
-                return;
-#ifdef FEW_CONTEXTS
-        while (atomic_dec_if_positive(&nr_free_contexts) < 0)
-                steal_context();
-#endif
-        ctx = next_mmu_context;
-        while (test_and_set_bit(ctx, context_map)) {
-                ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
-                if (ctx > LAST_CONTEXT)
-                        ctx = 0;
-        }
-        next_mmu_context = (ctx + 1) & LAST_CONTEXT;
-        mm->context.id = ctx;
-#ifdef FEW_CONTEXTS
-        context_mm[ctx] = mm;
-#endif
-}
-
-/*
- * Set up the context for a new address space.
- */
-static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
-{
-        mm->context.id = NO_CONTEXT;
-        mm->context.vdso_base = 0;
-        return 0;
-}
-
-/*
- * We're finished using the context for an address space.
- */
-static inline void destroy_context(struct mm_struct *mm)
-{
-        preempt_disable();
-        if (mm->context.id != NO_CONTEXT) {
-                clear_bit(mm->context.id, context_map);
-                mm->context.id = NO_CONTEXT;
-#ifdef FEW_CONTEXTS
-                atomic_inc(&nr_free_contexts);
-#endif
-        }
-        preempt_enable();
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-                             struct task_struct *tsk)
-{
-#ifdef CONFIG_ALTIVEC
-        if (cpu_has_feature(CPU_FTR_ALTIVEC))
-        asm volatile ("dssall;\n"
-#ifndef CONFIG_POWER4
-         "sync;\n" /* G4 needs a sync here, G5 apparently not */
-#endif
-         : : );
-#endif /* CONFIG_ALTIVEC */
-
-        tsk->thread.pgdir = next->pgd;
-
-        /* No need to flush userspace segments if the mm doesnt change */
-        if (prev == next)
-                return;
-
-        /* Setup new userspace context */
-        get_mmu_context(next);
-        set_context(next->context.id, next->pgd);
-}
-
-#define deactivate_mm(tsk,mm)   do { } while (0)
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-#define activate_mm(active_mm, mm)   switch_mm(active_mm, mm, current)
-
-extern void mmu_context_init(void);
-
-#endif /* __PPC_MMU_CONTEXT_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
deleted file mode 100644
index b30a6a3b5bd2..000000000000
--- a/include/asm-ppc/mpc10x.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
- * ctlr/EPIC/etc.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PPC_KERNEL_MPC10X_H
-#define __PPC_KERNEL_MPC10X_H
-
-#include <linux/pci_ids.h>
-#include <asm/pci-bridge.h>
-
-/*
- * The values here don't completely map everything but should work in most
- * cases.
- *
- * MAP A (PReP Map)
- *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
- *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
- *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
- *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
- *
- * MAP B (CHRP Map)
- *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
- *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
- *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
- *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
- */
-
-/*
- * Define the vendor/device IDs for the various bridges--should be added to
- * <linux/pci_ids.h>
- */
-#define MPC10X_BRIDGE_106       ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
-                                  PCI_VENDOR_ID_MOTOROLA)
-#define MPC10X_BRIDGE_8240      ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
-#define MPC10X_BRIDGE_107       ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
-#define MPC10X_BRIDGE_8245      ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
-
-/* Define the type of map to use */
-#define MPC10X_MEM_MAP_A                1
-#define MPC10X_MEM_MAP_B                2
-
-/* Map A (PReP Map) Defines */
-#define MPC10X_MAPA_CNFG_ADDR           0x80000cf8
-#define MPC10X_MAPA_CNFG_DATA           0x80000cfc
-
-#define MPC10X_MAPA_ISA_IO_BASE         0x80000000
-#define MPC10X_MAPA_ISA_MEM_BASE        0xc0000000
-#define MPC10X_MAPA_DRAM_OFFSET         0x80000000
-
-#define MPC10X_MAPA_PCI_INTACK_ADDR     0xbffffff0
-#define MPC10X_MAPA_PCI_IO_START        0x00000000
-#define MPC10X_MAPA_PCI_IO_END         (0x00800000 - 1)
-#define MPC10X_MAPA_PCI_MEM_START       0x00000000
-#define MPC10X_MAPA_PCI_MEM_END        (0x20000000 - 1)
-
-#define MPC10X_MAPA_PCI_MEM_OFFSET      (MPC10X_MAPA_ISA_MEM_BASE -     \
-                                         MPC10X_MAPA_PCI_MEM_START)
-
-/* Map B (CHRP Map) Defines */
-#define MPC10X_MAPB_CNFG_ADDR           0xfec00000
-#define MPC10X_MAPB_CNFG_DATA           0xfee00000
-
-#define MPC10X_MAPB_ISA_IO_BASE         0xfe000000
-#define MPC10X_MAPB_ISA_MEM_BASE        0x80000000
-#define MPC10X_MAPB_DRAM_OFFSET         0x00000000
-
-#define MPC10X_MAPB_PCI_INTACK_ADDR     0xfef00000
-#define MPC10X_MAPB_PCI_IO_START        0x00000000
-#define MPC10X_MAPB_PCI_IO_END         (0x00c00000 - 1)
-#define MPC10X_MAPB_PCI_MEM_START       0x80000000
-#define MPC10X_MAPB_PCI_MEM_END        (0xc0000000 - 1)
-
-#define MPC10X_MAPB_PCI_MEM_OFFSET      (MPC10X_MAPB_ISA_MEM_BASE -     \
-                                         MPC10X_MAPB_PCI_MEM_START)
-
-/* Set hose members to values appropriate for the mem map used */
-#define MPC10X_SETUP_HOSE(hose, map) {                                  \
-        (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET;      \
-        (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START;        \
-        (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END;            \
-        (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START;      \
-        (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END;          \
-        (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE;   \
-}
-
-
-/* Miscellaneous Configuration register offsets */
-#define MPC10X_CFG_PIR_REG              0x09
-#define MPC10X_CFG_PIR_HOST_BRIDGE      0x00
-#define MPC10X_CFG_PIR_AGENT            0x01
-
-#define MPC10X_CFG_EUMBBAR              0x78
-
-#define MPC10X_CFG_PICR1_REG            0xa8
-#define MPC10X_CFG_PICR1_ADDR_MAP_MASK  0x00010000
-#define MPC10X_CFG_PICR1_ADDR_MAP_A     0x00010000
-#define MPC10X_CFG_PICR1_ADDR_MAP_B     0x00000000
-#define MPC10X_CFG_PICR1_SPEC_PCI_RD    0x00000004
-#define MPC10X_CFG_PICR1_ST_GATH_EN     0x00000040
-
-#define MPC10X_CFG_PICR2_REG            0xac
-#define MPC10X_CFG_PICR2_COPYBACK_OPT   0x00000001
-
-#define MPC10X_CFG_MAPB_OPTIONS_REG     0xe0
-#define MPC10X_CFG_MAPB_OPTIONS_CFAE    0x80    /* CPU_FD_ALIAS_EN */
-#define MPC10X_CFG_MAPB_OPTIONS_PFAE    0x40    /* PCI_FD_ALIAS_EN */
-#define MPC10X_CFG_MAPB_OPTIONS_DR      0x20    /* DLL_RESET */
-#define MPC10X_CFG_MAPB_OPTIONS_PCICH   0x08    /* PCI_COMPATIBILITY_HOLE */
-#define MPC10X_CFG_MAPB_OPTIONS_PROCCH  0x04    /* PROC_COMPATIBILITY_HOLE */
-
-/* Define offsets for the memory controller registers in the config space */
-#define MPC10X_MCTLR_MEM_START_1        0x80    /* Banks 0-3 */
-#define MPC10X_MCTLR_MEM_START_2        0x84    /* Banks 4-7 */
-#define MPC10X_MCTLR_EXT_MEM_START_1    0x88    /* Banks 0-3 */
-#define MPC10X_MCTLR_EXT_MEM_START_2    0x8c    /* Banks 4-7 */
-
-#define MPC10X_MCTLR_MEM_END_1          0x90    /* Banks 0-3 */
-#define MPC10X_MCTLR_MEM_END_2          0x94    /* Banks 4-7 */
-#define MPC10X_MCTLR_EXT_MEM_END_1      0x98    /* Banks 0-3 */
-#define MPC10X_MCTLR_EXT_MEM_END_2      0x9c    /* Banks 4-7 */
-
-#define MPC10X_MCTLR_MEM_BANK_ENABLES   0xa0
-
-/* Define some offset in the EUMB */
-#define MPC10X_EUMB_SIZE                0x00100000 /* Total EUMB size (1MB) */
-
-#define MPC10X_EUMB_MU_OFFSET           0x00000000 /* Msg Unit reg offset */
-#define MPC10X_EUMB_MU_SIZE             0x00001000 /* Msg Unit reg size */
-#define MPC10X_EUMB_DMA_OFFSET          0x00001000 /* DMA Unit reg offset */
-#define MPC10X_EUMB_DMA_SIZE            0x00001000 /* DMA Unit reg size  */
-#define MPC10X_EUMB_ATU_OFFSET          0x00002000 /* Addr xlate reg offset */
-#define MPC10X_EUMB_ATU_SIZE            0x00001000 /* Addr xlate reg size  */
-#define MPC10X_EUMB_I2C_OFFSET          0x00003000 /* I2C Unit reg offset */
-#define MPC10X_EUMB_I2C_SIZE            0x00001000 /* I2C Unit reg size  */
-#define MPC10X_EUMB_DUART_OFFSET        0x00004000 /* DUART Unit reg offset (8245) */
-#define MPC10X_EUMB_DUART_SIZE          0x00001000 /* DUART Unit reg size (8245) */
-#define MPC10X_EUMB_EPIC_OFFSET         0x00040000 /* EPIC offset in EUMB */
-#define MPC10X_EUMB_EPIC_SIZE           0x00030000 /* EPIC size */
-#define MPC10X_EUMB_PM_OFFSET           0x000fe000 /* Performance Monitor reg offset (8245) */
-#define MPC10X_EUMB_PM_SIZE             0x00001000 /* Performance Monitor reg size (8245) */
-#define MPC10X_EUMB_WP_OFFSET           0x000ff000 /* Data path diagnostic, watchpoint reg offset */
-#define MPC10X_EUMB_WP_SIZE             0x00001000 /* Data path diagnostic, watchpoint reg size */
-
-/*
- * Define some recommended places to put the EUMB regs.
- * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
- */
-extern unsigned long                    ioremap_base;
-#define MPC10X_MAPA_EUMB_BASE           (ioremap_base - MPC10X_EUMB_SIZE)
-#define MPC10X_MAPB_EUMB_BASE           MPC10X_MAPA_EUMB_BASE
-
-enum ppc_sys_devices {
-        MPC10X_IIC1,
-        MPC10X_DMA0,
-        MPC10X_DMA1,
-        MPC10X_UART0,
-        MPC10X_UART1,
-        NUM_PPC_SYS_DEVS,
-};
-
-int mpc10x_bridge_init(struct pci_controller *hose,
-                       uint current_map,
-                       uint new_map,
-                       uint phys_eumb_base);
-unsigned long mpc10x_get_mem_size(uint mem_map);
-int mpc10x_enable_store_gathering(struct pci_controller *hose);
-int mpc10x_disable_store_gathering(struct pci_controller *hose);
-
-/* For MPC107 boards that use the built-in openpic */
-void mpc10x_set_openpic(void);
-
-#endif  /* __PPC_KERNEL_MPC10X_H */
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
deleted file mode 100644
index d9d21aa68ba3..000000000000
--- a/include/asm-ppc/mpc52xx.h
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * include/asm-ppc/mpc52xx.h
- * 
- * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
- * May need to be cleaned as the port goes on ...
- *
- *
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> 
- * for the 2.4 kernel.
- *
- * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ASM_MPC52xx_H__
-#define __ASM_MPC52xx_H__
-
-#ifndef __ASSEMBLY__
-#include <asm/ppcboot.h>
-#include <asm/types.h>
-
-struct pt_regs;
-#endif /* __ASSEMBLY__ */
-
-
-/* ======================================================================== */
-/* PPC Sys devices definition                                               */
-/* ======================================================================== */
-
-enum ppc_sys_devices {
-        MPC52xx_MSCAN1,
-        MPC52xx_MSCAN2,
-        MPC52xx_SPI,
-        MPC52xx_USB,
-        MPC52xx_BDLC,
-        MPC52xx_PSC1,
-        MPC52xx_PSC2,
-        MPC52xx_PSC3,
-        MPC52xx_PSC4,
-        MPC52xx_PSC5,
-        MPC52xx_PSC6,
-        MPC52xx_FEC,
-        MPC52xx_ATA,
-        MPC52xx_I2C1,
-        MPC52xx_I2C2,
-        NUM_PPC_SYS_DEVS,
-};
-
-
-/* ======================================================================== */
-/* Main registers/struct addresses                                          */
-/* ======================================================================== */
-
-/* MBAR position */
-#define MPC52xx_MBAR            0xf0000000      /* Phys address */
-#define MPC52xx_MBAR_VIRT       0xf0000000      /* Virt address */
-#define MPC52xx_MBAR_SIZE       0x00010000
-
-#define MPC52xx_PA(x)           ((phys_addr_t)(MPC52xx_MBAR + (x)))
-#define MPC52xx_VA(x)           ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
-
-/* Registers zone offset/size  */
-#define MPC52xx_MMAP_CTL_OFFSET         0x0000
-#define MPC52xx_MMAP_CTL_SIZE           0x068
-#define MPC52xx_SDRAM_OFFSET            0x0100
-#define MPC52xx_SDRAM_SIZE              0x010
-#define MPC52xx_CDM_OFFSET              0x0200
-#define MPC52xx_CDM_SIZE                0x038
-#define MPC52xx_INTR_OFFSET             0x0500
-#define MPC52xx_INTR_SIZE               0x04c
-#define MPC52xx_GPTx_OFFSET(x)          (0x0600 + ((x)<<4))
-#define MPC52xx_GPT_SIZE                0x010
-#define MPC52xx_RTC_OFFSET              0x0800
-#define MPC52xx_RTC_SIZE                0x024
-#define MPC52xx_GPIO_OFFSET             0x0b00
-#define MPC52xx_GPIO_SIZE               0x040
-#define MPC52xx_GPIO_WKUP_OFFSET        0x0c00
-#define MPC52xx_GPIO_WKUP_SIZE          0x028
-#define MPC52xx_PCI_OFFSET              0x0d00
-#define MPC52xx_PCI_SIZE                0x100
-#define MPC52xx_SDMA_OFFSET             0x1200
-#define MPC52xx_SDMA_SIZE               0x100
-#define MPC52xx_XLB_OFFSET              0x1f00
-#define MPC52xx_XLB_SIZE                0x100
-#define MPC52xx_PSCx_OFFSET(x)          (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
-#define MPC52xx_PSC_SIZE                0x0a0
-
-/* SRAM used for SDMA */
-#define MPC52xx_SRAM_OFFSET             0x8000
-#define MPC52xx_SRAM_SIZE               0x4000
-
-
-/* ======================================================================== */
-/* IRQ mapping                                                              */
-/* ======================================================================== */
-/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
- * this
- */
-
-#define MPC52xx_CRIT_IRQ_NUM    4
-#define MPC52xx_MAIN_IRQ_NUM    17
-#define MPC52xx_SDMA_IRQ_NUM    17
-#define MPC52xx_PERP_IRQ_NUM    23
-
-#define MPC52xx_CRIT_IRQ_BASE   1
-#define MPC52xx_MAIN_IRQ_BASE   (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
-#define MPC52xx_SDMA_IRQ_BASE   (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
-#define MPC52xx_PERP_IRQ_BASE   (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
-
-#define MPC52xx_IRQ0                    (MPC52xx_CRIT_IRQ_BASE + 0)
-#define MPC52xx_SLICE_TIMER_0_IRQ       (MPC52xx_CRIT_IRQ_BASE + 1)
-#define MPC52xx_HI_INT_IRQ              (MPC52xx_CRIT_IRQ_BASE + 2)
-#define MPC52xx_CCS_IRQ                 (MPC52xx_CRIT_IRQ_BASE + 3)
-
-#define MPC52xx_IRQ1                    (MPC52xx_MAIN_IRQ_BASE + 1)
-#define MPC52xx_IRQ2                    (MPC52xx_MAIN_IRQ_BASE + 2)
-#define MPC52xx_IRQ3                    (MPC52xx_MAIN_IRQ_BASE + 3)
-
-#define MPC52xx_SDMA_IRQ                (MPC52xx_PERP_IRQ_BASE + 0)
-#define MPC52xx_PSC1_IRQ                (MPC52xx_PERP_IRQ_BASE + 1)
-#define MPC52xx_PSC2_IRQ                (MPC52xx_PERP_IRQ_BASE + 2)
-#define MPC52xx_PSC3_IRQ                (MPC52xx_PERP_IRQ_BASE + 3)
-#define MPC52xx_PSC6_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
-#define MPC52xx_IRDA_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
-#define MPC52xx_FEC_IRQ                 (MPC52xx_PERP_IRQ_BASE + 5)
-#define MPC52xx_USB_IRQ                 (MPC52xx_PERP_IRQ_BASE + 6)
-#define MPC52xx_ATA_IRQ                 (MPC52xx_PERP_IRQ_BASE + 7)
-#define MPC52xx_PCI_CNTRL_IRQ           (MPC52xx_PERP_IRQ_BASE + 8)
-#define MPC52xx_PCI_SCIRX_IRQ           (MPC52xx_PERP_IRQ_BASE + 9)
-#define MPC52xx_PCI_SCITX_IRQ           (MPC52xx_PERP_IRQ_BASE + 10)
-#define MPC52xx_PSC4_IRQ                (MPC52xx_PERP_IRQ_BASE + 11)
-#define MPC52xx_PSC5_IRQ                (MPC52xx_PERP_IRQ_BASE + 12)
-#define MPC52xx_SPI_MODF_IRQ            (MPC52xx_PERP_IRQ_BASE + 13)
-#define MPC52xx_SPI_SPIF_IRQ            (MPC52xx_PERP_IRQ_BASE + 14)
-#define MPC52xx_I2C1_IRQ                (MPC52xx_PERP_IRQ_BASE + 15)
-#define MPC52xx_I2C2_IRQ                (MPC52xx_PERP_IRQ_BASE + 16)
-#define MPC52xx_MSCAN1_IRQ              (MPC52xx_PERP_IRQ_BASE + 17)
-#define MPC52xx_MSCAN2_IRQ              (MPC52xx_PERP_IRQ_BASE + 18)
-#define MPC52xx_IR_RX_IRQ               (MPC52xx_PERP_IRQ_BASE + 19)
-#define MPC52xx_IR_TX_IRQ               (MPC52xx_PERP_IRQ_BASE + 20)
-#define MPC52xx_XLB_ARB_IRQ             (MPC52xx_PERP_IRQ_BASE + 21)
-#define MPC52xx_BDLC_IRQ                (MPC52xx_PERP_IRQ_BASE + 22)
-
-
-
-/* ======================================================================== */
-/* Structures mapping of some unit register set                             */
-/* ======================================================================== */
-
-#ifndef __ASSEMBLY__
-
-/* Memory Mapping Control */
-struct mpc52xx_mmap_ctl {
-        u32     mbar;           /* MMAP_CTRL + 0x00 */
-
-        u32     cs0_start;      /* MMAP_CTRL + 0x04 */
-        u32     cs0_stop;       /* MMAP_CTRL + 0x08 */
-        u32     cs1_start;      /* MMAP_CTRL + 0x0c */
-        u32     cs1_stop;       /* MMAP_CTRL + 0x10 */
-        u32     cs2_start;      /* MMAP_CTRL + 0x14 */
-        u32     cs2_stop;       /* MMAP_CTRL + 0x18 */
-        u32     cs3_start;      /* MMAP_CTRL + 0x1c */
-        u32     cs3_stop;       /* MMAP_CTRL + 0x20 */
-        u32     cs4_start;      /* MMAP_CTRL + 0x24 */
-        u32     cs4_stop;       /* MMAP_CTRL + 0x28 */
-        u32     cs5_start;      /* MMAP_CTRL + 0x2c */
-        u32     cs5_stop;       /* MMAP_CTRL + 0x30 */
-
-        u32     sdram0;         /* MMAP_CTRL + 0x34 */
-        u32     sdram1;         /* MMAP_CTRL + 0X38 */
-
-        u32     reserved[4];    /* MMAP_CTRL + 0x3c .. 0x48 */
-
-        u32     boot_start;     /* MMAP_CTRL + 0x4c */
-        u32     boot_stop;      /* MMAP_CTRL + 0x50 */
-
-        u32     ipbi_ws_ctrl;   /* MMAP_CTRL + 0x54 */
-
-        u32     cs6_start;      /* MMAP_CTRL + 0x58 */
-        u32     cs6_stop;       /* MMAP_CTRL + 0x5c */
-        u32     cs7_start;      /* MMAP_CTRL + 0x60 */
-        u32     cs7_stop;       /* MMAP_CTRL + 0x64 */
-};
-
-/* SDRAM control */
-struct mpc52xx_sdram {
-        u32     mode;           /* SDRAM + 0x00 */
-        u32     ctrl;           /* SDRAM + 0x04 */
-        u32     config1;        /* SDRAM + 0x08 */
-        u32     config2;        /* SDRAM + 0x0c */
-};
-
-/* Interrupt controller */
-struct mpc52xx_intr {
-        u32     per_mask;       /* INTR + 0x00 */
-        u32     per_pri1;       /* INTR + 0x04 */
-        u32     per_pri2;       /* INTR + 0x08 */
-        u32     per_pri3;       /* INTR + 0x0c */
-        u32     ctrl;           /* INTR + 0x10 */
-        u32     main_mask;      /* INTR + 0x14 */
-        u32     main_pri1;      /* INTR + 0x18 */
-        u32     main_pri2;      /* INTR + 0x1c */
-        u32     reserved1;      /* INTR + 0x20 */
-        u32     enc_status;     /* INTR + 0x24 */
-        u32     crit_status;    /* INTR + 0x28 */
-        u32     main_status;    /* INTR + 0x2c */
-        u32     per_status;     /* INTR + 0x30 */
-        u32     reserved2;      /* INTR + 0x34 */
-        u32     per_error;      /* INTR + 0x38 */
-};
-
-/* SDMA */
-struct mpc52xx_sdma {
-        u32     taskBar;        /* SDMA + 0x00 */
-        u32     currentPointer; /* SDMA + 0x04 */
-        u32     endPointer;     /* SDMA + 0x08 */
-        u32     variablePointer;/* SDMA + 0x0c */
-
-        u8      IntVect1;       /* SDMA + 0x10 */
-        u8      IntVect2;       /* SDMA + 0x11 */
-        u16     PtdCntrl;       /* SDMA + 0x12 */
-
-        u32     IntPend;        /* SDMA + 0x14 */
-        u32     IntMask;        /* SDMA + 0x18 */
-
-        u16     tcr[16];        /* SDMA + 0x1c .. 0x3a */
-
-        u8      ipr[32];        /* SDMA + 0x3c .. 0x5b */
-
-        u32     cReqSelect;     /* SDMA + 0x5c */
-        u32     task_size0;     /* SDMA + 0x60 */
-        u32     task_size1;     /* SDMA + 0x64 */
-        u32     MDEDebug;       /* SDMA + 0x68 */
-        u32     ADSDebug;       /* SDMA + 0x6c */
-        u32     Value1;         /* SDMA + 0x70 */
-        u32     Value2;         /* SDMA + 0x74 */
-        u32     Control;        /* SDMA + 0x78 */
-        u32     Status;         /* SDMA + 0x7c */
-        u32     PTDDebug;       /* SDMA + 0x80 */
-};
-
-/* GPT */
-struct mpc52xx_gpt {
-        u32     mode;           /* GPTx + 0x00 */
-        u32     count;          /* GPTx + 0x04 */
-        u32     pwm;            /* GPTx + 0x08 */
-        u32     status;         /* GPTx + 0X0c */
-};
-
-/* RTC */
-struct mpc52xx_rtc {
-        u32     time_set;       /* RTC + 0x00 */
-        u32     date_set;       /* RTC + 0x04 */
-        u32     stopwatch;      /* RTC + 0x08 */
-        u32     int_enable;     /* RTC + 0x0c */
-        u32     time;           /* RTC + 0x10 */
-        u32     date;           /* RTC + 0x14 */
-        u32     stopwatch_intr; /* RTC + 0x18 */
-        u32     bus_error;      /* RTC + 0x1c */
-        u32     dividers;       /* RTC + 0x20 */
-};
-
-/* GPIO */
-struct mpc52xx_gpio {
-        u32     port_config;    /* GPIO + 0x00 */
-        u32     simple_gpioe;   /* GPIO + 0x04 */
-        u32     simple_ode;     /* GPIO + 0x08 */
-        u32     simple_ddr;     /* GPIO + 0x0c */
-        u32     simple_dvo;     /* GPIO + 0x10 */
-        u32     simple_ival;    /* GPIO + 0x14 */
-        u8      outo_gpioe;     /* GPIO + 0x18 */
-        u8      reserved1[3];   /* GPIO + 0x19 */
-        u8      outo_dvo;       /* GPIO + 0x1c */
-        u8      reserved2[3];   /* GPIO + 0x1d */
-        u8      sint_gpioe;     /* GPIO + 0x20 */
-        u8      reserved3[3];   /* GPIO + 0x21 */
-        u8      sint_ode;       /* GPIO + 0x24 */
-        u8      reserved4[3];   /* GPIO + 0x25 */
-        u8      sint_ddr;       /* GPIO + 0x28 */
-        u8      reserved5[3];   /* GPIO + 0x29 */
-        u8      sint_dvo;       /* GPIO + 0x2c */
-        u8      reserved6[3];   /* GPIO + 0x2d */
-        u8      sint_inten;     /* GPIO + 0x30 */
-        u8      reserved7[3];   /* GPIO + 0x31 */
-        u16     sint_itype;     /* GPIO + 0x34 */
-        u16     reserved8;      /* GPIO + 0x36 */
-        u8      gpio_control;   /* GPIO + 0x38 */
-        u8      reserved9[3];   /* GPIO + 0x39 */
-        u8      sint_istat;     /* GPIO + 0x3c */
-        u8      sint_ival;      /* GPIO + 0x3d */
-        u8      bus_errs;       /* GPIO + 0x3e */
-        u8      reserved10;     /* GPIO + 0x3f */
-};
-
-#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
-#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
-#define MPC52xx_GPIO_PCI_DIS                    (1<<15)
-
-/* GPIO with WakeUp*/
-struct mpc52xx_gpio_wkup {
-        u8      wkup_gpioe;     /* GPIO_WKUP + 0x00 */
-        u8      reserved1[3];   /* GPIO_WKUP + 0x03 */
-        u8      wkup_ode;       /* GPIO_WKUP + 0x04 */
-        u8      reserved2[3];   /* GPIO_WKUP + 0x05 */
-        u8      wkup_ddr;       /* GPIO_WKUP + 0x08 */
-        u8      reserved3[3];   /* GPIO_WKUP + 0x09 */
-        u8      wkup_dvo;       /* GPIO_WKUP + 0x0C */
-        u8      reserved4[3];   /* GPIO_WKUP + 0x0D */
-        u8      wkup_inten;     /* GPIO_WKUP + 0x10 */
-        u8      reserved5[3];   /* GPIO_WKUP + 0x11 */
-        u8      wkup_iinten;    /* GPIO_WKUP + 0x14 */
-        u8      reserved6[3];   /* GPIO_WKUP + 0x15 */
-        u16     wkup_itype;     /* GPIO_WKUP + 0x18 */
-        u8      reserved7[2];   /* GPIO_WKUP + 0x1A */
-        u8      wkup_maste;     /* GPIO_WKUP + 0x1C */
-        u8      reserved8[3];   /* GPIO_WKUP + 0x1D */
-        u8      wkup_ival;      /* GPIO_WKUP + 0x20 */
-        u8      reserved9[3];   /* GPIO_WKUP + 0x21 */
-        u8      wkup_istat;     /* GPIO_WKUP + 0x24 */
-        u8      reserved10[3];  /* GPIO_WKUP + 0x25 */
-};
-
-/* XLB Bus control */
-struct mpc52xx_xlb {
-        u8      reserved[0x40];
-        u32     config;                 /* XLB + 0x40 */
-        u32     version;                /* XLB + 0x44 */
-        u32     status;                 /* XLB + 0x48 */
-        u32     int_enable;             /* XLB + 0x4c */
-        u32     addr_capture;           /* XLB + 0x50 */
-        u32     bus_sig_capture;        /* XLB + 0x54 */
-        u32     addr_timeout;           /* XLB + 0x58 */
-        u32     data_timeout;           /* XLB + 0x5c */
-        u32     bus_act_timeout;        /* XLB + 0x60 */
-        u32     master_pri_enable;      /* XLB + 0x64 */
-        u32     master_priority;        /* XLB + 0x68 */
-        u32     base_address;           /* XLB + 0x6c */
-        u32     snoop_window;           /* XLB + 0x70 */
-};
-
-#define MPC52xx_XLB_CFG_PLDIS           (1 << 31)
-#define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
-
-/* Clock Distribution control */
-struct mpc52xx_cdm {
-        u32     jtag_id;                /* CDM + 0x00  reg0 read only */
-        u32     rstcfg;                 /* CDM + 0x04  reg1 read only */
-        u32     breadcrumb;             /* CDM + 0x08  reg2 */
-
-        u8      mem_clk_sel;            /* CDM + 0x0c  reg3 byte0 */
-        u8      xlb_clk_sel;            /* CDM + 0x0d  reg3 byte1 read only */
-        u8      ipb_clk_sel;            /* CDM + 0x0e  reg3 byte2 */
-        u8      pci_clk_sel;            /* CDM + 0x0f  reg3 byte3 */
-
-        u8      ext_48mhz_en;           /* CDM + 0x10  reg4 byte0 */
-        u8      fd_enable;              /* CDM + 0x11  reg4 byte1 */
-        u16     fd_counters;            /* CDM + 0x12  reg4 byte2,3 */
-
-        u32     clk_enables;            /* CDM + 0x14  reg5 */
-
-        u8      osc_disable;            /* CDM + 0x18  reg6 byte0 */
-        u8      reserved0[3];           /* CDM + 0x19  reg6 byte1,2,3 */
-
-        u8      ccs_sleep_enable;       /* CDM + 0x1c  reg7 byte0 */
-        u8      osc_sleep_enable;       /* CDM + 0x1d  reg7 byte1 */
-        u8      reserved1;              /* CDM + 0x1e  reg7 byte2 */
-        u8      ccs_qreq_test;          /* CDM + 0x1f  reg7 byte3 */
-
-        u8      soft_reset;             /* CDM + 0x20  u8 byte0 */
-        u8      no_ckstp;               /* CDM + 0x21  u8 byte0 */
-        u8      reserved2[2];           /* CDM + 0x22  u8 byte1,2,3 */
-
-        u8      pll_lock;               /* CDM + 0x24  reg9 byte0 */
-        u8      pll_looselock;          /* CDM + 0x25  reg9 byte1 */
-        u8      pll_sm_lockwin;         /* CDM + 0x26  reg9 byte2 */
-        u8      reserved3;              /* CDM + 0x27  reg9 byte3 */
-
-        u16     reserved4;              /* CDM + 0x28  reg10 byte0,1 */
-        u16     mclken_div_psc1;        /* CDM + 0x2a  reg10 byte2,3 */
-
-        u16     reserved5;              /* CDM + 0x2c  reg11 byte0,1 */
-        u16     mclken_div_psc2;        /* CDM + 0x2e  reg11 byte2,3 */
-
-        u16     reserved6;              /* CDM + 0x30  reg12 byte0,1 */
-        u16     mclken_div_psc3;        /* CDM + 0x32  reg12 byte2,3 */
-
-        u16     reserved7;              /* CDM + 0x34  reg13 byte0,1 */
-        u16     mclken_div_psc6;        /* CDM + 0x36  reg13 byte2,3 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-
-/* ========================================================================= */
-/* Prototypes for MPC52xx syslib                                             */
-/* ========================================================================= */
-
-#ifndef __ASSEMBLY__
-
-extern void mpc52xx_init_irq(void);
-extern int mpc52xx_get_irq(void);
-
-extern unsigned long mpc52xx_find_end_of_memory(void);
-extern void mpc52xx_set_bat(void);
-extern void mpc52xx_map_io(void);
-extern void mpc52xx_restart(char *cmd);
-extern void mpc52xx_halt(void);
-extern void mpc52xx_power_off(void);
-extern void mpc52xx_progress(char *s, unsigned short hex);
-extern void mpc52xx_calibrate_decr(void);
-
-extern void mpc52xx_find_bridges(void);
-
-extern void mpc52xx_setup_cpu(void);
-
-
-
-        /* Matching of PSC function */
-struct mpc52xx_psc_func {
-        int id;
-        char *func;
-};
-
-extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
-extern struct  mpc52xx_psc_func mpc52xx_psc_functions[];
-        /* This array is to be defined in platform file */
-
-#endif /* __ASSEMBLY__ */
-
-
-/* ========================================================================= */
-/* Platform configuration                                                    */
-/* ========================================================================= */
-
-/* The U-Boot platform information struct */
-extern bd_t __res;
-
-/* Platform options */
-#if defined(CONFIG_LITE5200)
-#include <platforms/lite5200.h>
-#endif
-
-
-#endif /* __ASM_MPC52xx_H__ */
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h
deleted file mode 100644
index 39fcd02cd4e8..000000000000
--- a/include/asm-ppc/mpc52xx_psc.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * include/asm-ppc/mpc52xx_psc.h
- * 
- * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
- * PSCs. Theses are shared between multiple drivers since a PSC can be
- * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
- *
- *
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Based/Extracted from some header of the 2.4 originally written by 
- * Dale Farnsworth <dfarnsworth@mvista.com> 
- *
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ASM_MPC52xx_PSC_H__
-#define __ASM_MPC52xx_PSC_H__
-
-#include <asm/types.h>
-
-/* Max number of PSCs */
-#define MPC52xx_PSC_MAXNUM      6
-
-/* Programmable Serial Controller (PSC) status register bits */
-#define MPC52xx_PSC_SR_UNEX_RX  0x0001
-#define MPC52xx_PSC_SR_DATA_VAL 0x0002
-#define MPC52xx_PSC_SR_DATA_OVR 0x0004
-#define MPC52xx_PSC_SR_CMDSEND  0x0008
-#define MPC52xx_PSC_SR_CDE      0x0080
-#define MPC52xx_PSC_SR_RXRDY    0x0100
-#define MPC52xx_PSC_SR_RXFULL   0x0200
-#define MPC52xx_PSC_SR_TXRDY    0x0400
-#define MPC52xx_PSC_SR_TXEMP    0x0800
-#define MPC52xx_PSC_SR_OE       0x1000
-#define MPC52xx_PSC_SR_PE       0x2000
-#define MPC52xx_PSC_SR_FE       0x4000
-#define MPC52xx_PSC_SR_RB       0x8000
-
-/* PSC Command values */
-#define MPC52xx_PSC_RX_ENABLE           0x0001
-#define MPC52xx_PSC_RX_DISABLE          0x0002
-#define MPC52xx_PSC_TX_ENABLE           0x0004
-#define MPC52xx_PSC_TX_DISABLE          0x0008
-#define MPC52xx_PSC_SEL_MODE_REG_1      0x0010
-#define MPC52xx_PSC_RST_RX              0x0020
-#define MPC52xx_PSC_RST_TX              0x0030
-#define MPC52xx_PSC_RST_ERR_STAT        0x0040
-#define MPC52xx_PSC_RST_BRK_CHG_INT     0x0050
-#define MPC52xx_PSC_START_BRK           0x0060
-#define MPC52xx_PSC_STOP_BRK            0x0070
-
-/* PSC TxRx FIFO status bits */
-#define MPC52xx_PSC_RXTX_FIFO_ERR       0x0040
-#define MPC52xx_PSC_RXTX_FIFO_UF        0x0020
-#define MPC52xx_PSC_RXTX_FIFO_OF        0x0010
-#define MPC52xx_PSC_RXTX_FIFO_FR        0x0008
-#define MPC52xx_PSC_RXTX_FIFO_FULL      0x0004
-#define MPC52xx_PSC_RXTX_FIFO_ALARM     0x0002
-#define MPC52xx_PSC_RXTX_FIFO_EMPTY     0x0001
-
-/* PSC interrupt mask bits */
-#define MPC52xx_PSC_IMR_TXRDY           0x0100
-#define MPC52xx_PSC_IMR_RXRDY           0x0200
-#define MPC52xx_PSC_IMR_DB              0x0400
-#define MPC52xx_PSC_IMR_IPC             0x8000
-
-/* PSC input port change bit */
-#define MPC52xx_PSC_CTS                 0x01
-#define MPC52xx_PSC_DCD                 0x02
-#define MPC52xx_PSC_D_CTS               0x10
-#define MPC52xx_PSC_D_DCD               0x20
-
-/* PSC mode fields */
-#define MPC52xx_PSC_MODE_5_BITS                 0x00
-#define MPC52xx_PSC_MODE_6_BITS                 0x01
-#define MPC52xx_PSC_MODE_7_BITS                 0x02
-#define MPC52xx_PSC_MODE_8_BITS                 0x03
-#define MPC52xx_PSC_MODE_BITS_MASK              0x03
-#define MPC52xx_PSC_MODE_PAREVEN                0x00
-#define MPC52xx_PSC_MODE_PARODD                 0x04
-#define MPC52xx_PSC_MODE_PARFORCE               0x08
-#define MPC52xx_PSC_MODE_PARNONE                0x10
-#define MPC52xx_PSC_MODE_ERR                    0x20
-#define MPC52xx_PSC_MODE_FFULL                  0x40
-#define MPC52xx_PSC_MODE_RXRTS                  0x80
-
-#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS        0x00
-#define MPC52xx_PSC_MODE_ONE_STOP               0x07
-#define MPC52xx_PSC_MODE_TWO_STOP               0x0f
-
-#define MPC52xx_PSC_RFNUM_MASK  0x01ff
-
-
-/* Structure of the hardware registers */
-struct mpc52xx_psc {
-        u8              mode;           /* PSC + 0x00 */
-        u8              reserved0[3];
-        union {                         /* PSC + 0x04 */
-                u16     status;
-                u16     clock_select;
-        } sr_csr;
-#define mpc52xx_psc_status      sr_csr.status
-#define mpc52xx_psc_clock_select sr_csr.clock_select
-        u16             reserved1;
-        u8              command;        /* PSC + 0x08 */
-        u8              reserved2[3];
-        union {                         /* PSC + 0x0c */
-                u8      buffer_8;
-                u16     buffer_16;
-                u32     buffer_32;
-        } buffer;
-#define mpc52xx_psc_buffer_8    buffer.buffer_8
-#define mpc52xx_psc_buffer_16   buffer.buffer_16
-#define mpc52xx_psc_buffer_32   buffer.buffer_32
-        union {                         /* PSC + 0x10 */
-                u8      ipcr;
-                u8      acr;
-        } ipcr_acr;
-#define mpc52xx_psc_ipcr        ipcr_acr.ipcr
-#define mpc52xx_psc_acr         ipcr_acr.acr
-        u8              reserved3[3];
-        union {                         /* PSC + 0x14 */
-                u16     isr;
-                u16     imr;
-        } isr_imr;
-#define mpc52xx_psc_isr         isr_imr.isr
-#define mpc52xx_psc_imr         isr_imr.imr
-        u16             reserved4;
-        u8              ctur;           /* PSC + 0x18 */
-        u8              reserved5[3];
-        u8              ctlr;           /* PSC + 0x1c */
-        u8              reserved6[3];
-        u32             ccr;            /* PSC + 0x20 */
-        u32             ac97_slots;     /* PSC + 0x24 */
-        u32             ac97_cmd;       /* PSC + 0x28 */
-        u32             ac97_data;      /* PSC + 0x2c */
-        u8              ivr;            /* PSC + 0x30 */
-        u8              reserved8[3];
-        u8              ip;             /* PSC + 0x34 */
-        u8              reserved9[3];
-        u8              op1;            /* PSC + 0x38 */
-        u8              reserved10[3];
-        u8              op0;            /* PSC + 0x3c */
-        u8              reserved11[3];
-        u32             sicr;           /* PSC + 0x40 */
-        u8              ircr1;          /* PSC + 0x44 */
-        u8              reserved13[3];
-        u8              ircr2;          /* PSC + 0x44 */
-        u8              reserved14[3];
-        u8              irsdr;          /* PSC + 0x4c */
-        u8              reserved15[3];
-        u8              irmdr;          /* PSC + 0x50 */
-        u8              reserved16[3];
-        u8              irfdr;          /* PSC + 0x54 */
-        u8              reserved17[3];
-};
-
-struct mpc52xx_psc_fifo {
-        u16             rfnum;          /* PSC + 0x58 */
-        u16             reserved18;
-        u16             tfnum;          /* PSC + 0x5c */
-        u16             reserved19;
-        u32             rfdata;         /* PSC + 0x60 */
-        u16             rfstat;         /* PSC + 0x64 */
-        u16             reserved20;
-        u8              rfcntl;         /* PSC + 0x68 */
-        u8              reserved21[5];
-        u16             rfalarm;        /* PSC + 0x6e */
-        u16             reserved22;
-        u16             rfrptr;         /* PSC + 0x72 */
-        u16             reserved23;
-        u16             rfwptr;         /* PSC + 0x76 */
-        u16             reserved24;
-        u16             rflrfptr;       /* PSC + 0x7a */
-        u16             reserved25;
-        u16             rflwfptr;       /* PSC + 0x7e */
-        u32             tfdata;         /* PSC + 0x80 */
-        u16             tfstat;         /* PSC + 0x84 */
-        u16             reserved26;
-        u8              tfcntl;         /* PSC + 0x88 */
-        u8              reserved27[5];
-        u16             tfalarm;        /* PSC + 0x8e */
-        u16             reserved28;
-        u16             tfrptr;         /* PSC + 0x92 */
-        u16             reserved29;
-        u16             tfwptr;         /* PSC + 0x96 */
-        u16             reserved30;
-        u16             tflrfptr;       /* PSC + 0x9a */
-        u16             reserved31;
-        u16             tflwfptr;       /* PSC + 0x9e */
-};
-
-
-#endif  /* __ASM_MPC52xx_PSC_H__ */
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
deleted file mode 100644
index 402ba15c2e80..000000000000
--- a/include/asm-ppc/mpc8260.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8260 configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_MPC8260_H__
-#define __ASM_PPC_MPC8260_H__
-
-
-#ifdef CONFIG_8260
-
-#ifdef CONFIG_EST8260
-#include <platforms/est8260.h>
-#endif
-
-#ifdef CONFIG_SBC82xx
-#include <platforms/sbc82xx.h>
-#endif
-
-#ifdef CONFIG_SBS8260
-#include <platforms/sbs8260.h>
-#endif
-
-#ifdef CONFIG_RPX8260
-#include <platforms/rpx8260.h>
-#endif
-
-#ifdef CONFIG_WILLOW
-#include <platforms/willow.h>
-#endif
-
-#ifdef CONFIG_TQM8260
-#include <platforms/tqm8260.h>
-#endif
-
-#ifdef CONFIG_PCI_8260
-#include <syslib/m82xx_pci.h>
-#endif
-
-/* Make sure the memory translation stuff is there if PCI not used.
- */
-#ifndef _IO_BASE
-#define _IO_BASE        0
-#endif
-
-#ifndef _ISA_MEM_BASE
-#define _ISA_MEM_BASE   0
-#endif
-
-#ifndef PCI_DRAM_OFFSET
-#define PCI_DRAM_OFFSET 0
-#endif
-
-/* Map 256MB I/O region
- */
-#ifndef IO_PHYS_ADDR
-#define IO_PHYS_ADDR    0xe0000000
-#endif
-#ifndef IO_VIRT_ADDR
-#define IO_VIRT_ADDR    IO_PHYS_ADDR
-#endif
-
-enum ppc_sys_devices {
-        MPC82xx_CPM_FCC1,
-        MPC82xx_CPM_FCC2,
-        MPC82xx_CPM_FCC3,
-        MPC82xx_CPM_I2C,
-        MPC82xx_CPM_SCC1,
-        MPC82xx_CPM_SCC2,
-        MPC82xx_CPM_SCC3,
-        MPC82xx_CPM_SCC4,
-        MPC82xx_CPM_SPI,
-        MPC82xx_CPM_MCC1,
-        MPC82xx_CPM_MCC2,
-        MPC82xx_CPM_SMC1,
-        MPC82xx_CPM_SMC2,
-        MPC82xx_CPM_USB,
-        MPC82xx_SEC1,
-        MPC82xx_MDIO_BB,
-        NUM_PPC_SYS_DEVS,
-};
-
-#ifndef __ASSEMBLY__
-/* The "residual" data board information structure the boot loader
- * hands to us.
- */
-extern unsigned char __res[];
-#endif
-
-#ifndef BOARD_CHIP_NAME
-#define BOARD_CHIP_NAME ""
-#endif
-
-#endif /* CONFIG_8260 */
-#endif /* !__ASM_PPC_MPC8260_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h
deleted file mode 100644
index 9f7176881c56..000000000000
--- a/include/asm-ppc/mpc8260_pci9.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* include/asm-ppc/mpc8260_pci9.h
- *
- * Undefine the PCI read* and in* macros so we can define them as functions
- * that implement the workaround for the MPC8260 device erratum PCI 9.
- *
- * This header file should only be included at the end of include/asm-ppc/io.h
- * and never included directly anywhere else.
- *
- * Author:  andy_lowe@mvista.com
- *
- * 2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _PPC_IO_H
-#error "Do not include mpc8260_pci9.h directly."
-#endif
-
-#ifdef __KERNEL__
-#ifndef __CONFIG_8260_PCI9_DEFS
-#define __CONFIG_8260_PCI9_DEFS
-
-#undef readb
-#undef readw
-#undef readl
-#undef insb
-#undef insw
-#undef insl
-#undef inb
-#undef inw
-#undef inl
-#undef memcpy_fromio
-
-extern int readb(volatile unsigned char *addr);
-extern int readw(volatile unsigned short *addr);
-extern unsigned readl(volatile unsigned *addr);
-extern void insb(unsigned port, void *buf, int ns);
-extern void insw(unsigned port, void *buf, int ns);
-extern void insl(unsigned port, void *buf, int nl);
-extern int inb(unsigned port);
-extern int inw(unsigned port);
-extern unsigned inl(unsigned port);
-extern void *memcpy_fromio(void *dest, unsigned long src, size_t count);
-
-#endif /* !__CONFIG_8260_PCI9_DEFS */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
deleted file mode 100644
index b9e3060b0278..000000000000
--- a/include/asm-ppc/mpc8xx.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* This is the single file included by all MPC8xx build options.
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8xx configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifdef __KERNEL__
-#ifndef __CONFIG_8xx_DEFS
-#define __CONFIG_8xx_DEFS
-
-
-#ifdef CONFIG_8xx
-
-#ifdef CONFIG_MBX
-#include <platforms/mbx.h>
-#endif
-
-#ifdef CONFIG_FADS
-#include <platforms/fads.h>
-#endif
-
-#ifdef CONFIG_RPXLITE
-#include <platforms/rpxlite.h>
-#endif
-
-#ifdef CONFIG_BSEIP
-#include <platforms/bseip.h>
-#endif
-
-#ifdef CONFIG_RPXCLASSIC
-#include <platforms/rpxclassic.h>
-#endif
-
-#if defined(CONFIG_TQM8xxL)
-#include <platforms/tqm8xx.h>
-#endif
-
-#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
-#include <platforms/ivms8.h>
-#endif
-
-#if defined(CONFIG_HERMES_PRO)
-#include <platforms/hermes.h>
-#endif
-
-#if defined(CONFIG_IP860)
-#include <platforms/ip860.h>
-#endif
-
-#if defined(CONFIG_LWMON)
-#include <platforms/lwmon.h>
-#endif
-
-#if defined(CONFIG_PCU_E)
-#include <platforms/pcu_e.h>
-#endif
-
-#if defined(CONFIG_CCM)
-#include <platforms/ccm.h>
-#endif
-
-#if defined(CONFIG_LANTEC)
-#include <platforms/lantec.h>
-#endif
-
-/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
- * use the same memory map.
- */
-#if 0
-#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
-#define _IO_BASE PCI_ISA_IO_ADDR
-#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR
-#define PCI_DRAM_OFFSET 0x80000000
-#else
-#define _IO_BASE        0
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#endif
-#else
-#if !defined(_IO_BASE)  /* defined in board specific header */
-#define _IO_BASE        0
-#endif
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#endif
-
-#ifndef __ASSEMBLY__
-/* The "residual" data board information structure the boot loader
- * hands to us.
- */
-extern unsigned char __res[];
-
-struct pt_regs;
-
-enum ppc_sys_devices {
-        MPC8xx_CPM_FEC1,
-        MPC8xx_CPM_FEC2,
-        MPC8xx_CPM_I2C,
-        MPC8xx_CPM_SCC1,
-        MPC8xx_CPM_SCC2,
-        MPC8xx_CPM_SCC3,
-        MPC8xx_CPM_SCC4,
-        MPC8xx_CPM_SPI,
-        MPC8xx_CPM_MCC1,
-        MPC8xx_CPM_MCC2,
-        MPC8xx_CPM_SMC1,
-        MPC8xx_CPM_SMC2,
-        MPC8xx_CPM_USB,
-        MPC8xx_MDIO_FEC,
-        NUM_PPC_SYS_DEVS,
-};
-
-#define PPC_PIN_SIZE    (24 * 1024 * 1024)      /* 24Mbytes of data pinned */
-
-#ifndef BOARD_CHIP_NAME
-#define BOARD_CHIP_NAME ""
-#endif
-
-#endif /* !__ASSEMBLY__ */
-#endif /* CONFIG_8xx */
-#endif /* __CONFIG_8xx_DEFS */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
deleted file mode 100644
index 2963d6aa3ea5..000000000000
--- a/include/asm-ppc/mv64x60.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * include/asm-ppc/mv64x60.h
- *
- * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_MV64x60_H
-#define __ASMPPC_MV64x60_H
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/mv64x60_defs.h>
-
-struct platform_device;
-
-extern u8       mv64x60_pci_exclude_bridge;
-
-extern spinlock_t mv64x60_lock;
-
-/* 32-bit Window table entry defines */
-#define MV64x60_CPU2MEM_0_WIN                   0
-#define MV64x60_CPU2MEM_1_WIN                   1
-#define MV64x60_CPU2MEM_2_WIN                   2
-#define MV64x60_CPU2MEM_3_WIN                   3
-#define MV64x60_CPU2DEV_0_WIN                   4
-#define MV64x60_CPU2DEV_1_WIN                   5
-#define MV64x60_CPU2DEV_2_WIN                   6
-#define MV64x60_CPU2DEV_3_WIN                   7
-#define MV64x60_CPU2BOOT_WIN                    8
-#define MV64x60_CPU2PCI0_IO_WIN                 9
-#define MV64x60_CPU2PCI0_MEM_0_WIN              10
-#define MV64x60_CPU2PCI0_MEM_1_WIN              11
-#define MV64x60_CPU2PCI0_MEM_2_WIN              12
-#define MV64x60_CPU2PCI0_MEM_3_WIN              13
-#define MV64x60_CPU2PCI1_IO_WIN                 14
-#define MV64x60_CPU2PCI1_MEM_0_WIN              15
-#define MV64x60_CPU2PCI1_MEM_1_WIN              16
-#define MV64x60_CPU2PCI1_MEM_2_WIN              17
-#define MV64x60_CPU2PCI1_MEM_3_WIN              18
-#define MV64x60_CPU2SRAM_WIN                    19
-#define MV64x60_CPU2PCI0_IO_REMAP_WIN           20
-#define MV64x60_CPU2PCI1_IO_REMAP_WIN           21
-#define MV64x60_CPU_PROT_0_WIN                  22
-#define MV64x60_CPU_PROT_1_WIN                  23
-#define MV64x60_CPU_PROT_2_WIN                  24
-#define MV64x60_CPU_PROT_3_WIN                  25
-#define MV64x60_CPU_SNOOP_0_WIN                 26
-#define MV64x60_CPU_SNOOP_1_WIN                 27
-#define MV64x60_CPU_SNOOP_2_WIN                 28
-#define MV64x60_CPU_SNOOP_3_WIN                 29
-#define MV64x60_PCI02MEM_REMAP_0_WIN            30
-#define MV64x60_PCI02MEM_REMAP_1_WIN            31
-#define MV64x60_PCI02MEM_REMAP_2_WIN            32
-#define MV64x60_PCI02MEM_REMAP_3_WIN            33
-#define MV64x60_PCI12MEM_REMAP_0_WIN            34
-#define MV64x60_PCI12MEM_REMAP_1_WIN            35
-#define MV64x60_PCI12MEM_REMAP_2_WIN            36
-#define MV64x60_PCI12MEM_REMAP_3_WIN            37
-#define MV64x60_ENET2MEM_0_WIN                  38
-#define MV64x60_ENET2MEM_1_WIN                  39
-#define MV64x60_ENET2MEM_2_WIN                  40
-#define MV64x60_ENET2MEM_3_WIN                  41
-#define MV64x60_ENET2MEM_4_WIN                  42
-#define MV64x60_ENET2MEM_5_WIN                  43
-#define MV64x60_MPSC2MEM_0_WIN                  44
-#define MV64x60_MPSC2MEM_1_WIN                  45
-#define MV64x60_MPSC2MEM_2_WIN                  46
-#define MV64x60_MPSC2MEM_3_WIN                  47
-#define MV64x60_IDMA2MEM_0_WIN                  48
-#define MV64x60_IDMA2MEM_1_WIN                  49
-#define MV64x60_IDMA2MEM_2_WIN                  50
-#define MV64x60_IDMA2MEM_3_WIN                  51
-#define MV64x60_IDMA2MEM_4_WIN                  52
-#define MV64x60_IDMA2MEM_5_WIN                  53
-#define MV64x60_IDMA2MEM_6_WIN                  54
-#define MV64x60_IDMA2MEM_7_WIN                  55
-
-#define MV64x60_32BIT_WIN_COUNT                 56
-
-/* 64-bit Window table entry defines */
-#define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN        0
-#define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN        1
-#define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN        2
-#define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN        3
-#define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN        4
-#define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN        5
-#define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN        6
-#define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN        7
-#define MV64x60_PCI02MEM_ACC_CNTL_0_WIN         8
-#define MV64x60_PCI02MEM_ACC_CNTL_1_WIN         9
-#define MV64x60_PCI02MEM_ACC_CNTL_2_WIN         10
-#define MV64x60_PCI02MEM_ACC_CNTL_3_WIN         11
-#define MV64x60_PCI12MEM_ACC_CNTL_0_WIN         12
-#define MV64x60_PCI12MEM_ACC_CNTL_1_WIN         13
-#define MV64x60_PCI12MEM_ACC_CNTL_2_WIN         14
-#define MV64x60_PCI12MEM_ACC_CNTL_3_WIN         15
-#define MV64x60_PCI02MEM_SNOOP_0_WIN            16
-#define MV64x60_PCI02MEM_SNOOP_1_WIN            17
-#define MV64x60_PCI02MEM_SNOOP_2_WIN            18
-#define MV64x60_PCI02MEM_SNOOP_3_WIN            19
-#define MV64x60_PCI12MEM_SNOOP_0_WIN            20
-#define MV64x60_PCI12MEM_SNOOP_1_WIN            21
-#define MV64x60_PCI12MEM_SNOOP_2_WIN            22
-#define MV64x60_PCI12MEM_SNOOP_3_WIN            23
-
-#define MV64x60_64BIT_WIN_COUNT                 24
-
-/*
- * Define a structure that's used to pass in config information to the
- * core routines.
- */
-struct mv64x60_pci_window {
-        u32     cpu_base;
-        u32     pci_base_hi;
-        u32     pci_base_lo;
-        u32     size;
-        u32     swap;
-};
-
-struct mv64x60_pci_info {
-        u8      enable_bus;     /* allow access to this PCI bus? */
-
-        struct mv64x60_pci_window       pci_io;
-        struct mv64x60_pci_window       pci_mem[3];
-
-        u32     acc_cntl_options[MV64x60_CPU2MEM_WINDOWS];
-        u32     snoop_options[MV64x60_CPU2MEM_WINDOWS];
-        u16     pci_cmd_bits;
-        u16     latency_timer;
-};
-
-struct mv64x60_setup_info {
-        u32     phys_reg_base;
-        u32     window_preserve_mask_32_hi;
-        u32     window_preserve_mask_32_lo;
-        u32     window_preserve_mask_64;
-
-        u32     cpu_prot_options[MV64x60_CPU2MEM_WINDOWS];
-        u32     cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS];
-        u32     enet_options[MV64x60_CPU2MEM_WINDOWS];
-        u32     mpsc_options[MV64x60_CPU2MEM_WINDOWS];
-        u32     idma_options[MV64x60_CPU2MEM_WINDOWS];
-
-        struct mv64x60_pci_info pci_0;
-        struct mv64x60_pci_info pci_1;
-};
-
-/* Define what the top bits in the extra member of a window entry means. */
-#define MV64x60_EXTRA_INVALID           0x00000000
-#define MV64x60_EXTRA_CPUWIN_ENAB       0x10000000
-#define MV64x60_EXTRA_CPUPROT_ENAB      0x20000000
-#define MV64x60_EXTRA_ENET_ENAB         0x30000000
-#define MV64x60_EXTRA_MPSC_ENAB         0x40000000
-#define MV64x60_EXTRA_IDMA_ENAB         0x50000000
-#define MV64x60_EXTRA_PCIACC_ENAB       0x60000000
-
-#define MV64x60_EXTRA_MASK              0xf0000000
-
-/*
- * Define the 'handle' struct that will be passed between the 64x60 core
- * code and the platform-specific code that will use it.  The handle
- * will contain pointers to chip-specific routines & information.
- */
-struct mv64x60_32bit_window {
-        u32     base_reg;
-        u32     size_reg;
-        u8      base_bits;
-        u8      size_bits;
-        u32     (*get_from_field)(u32 val, u32 num_bits);
-        u32     (*map_to_field)(u32 val, u32 num_bits);
-        u32     extra;
-};
-
-struct mv64x60_64bit_window {
-        u32     base_hi_reg;
-        u32     base_lo_reg;
-        u32     size_reg;
-        u8      base_lo_bits;
-        u8      size_bits;
-        u32     (*get_from_field)(u32 val, u32 num_bits);
-        u32     (*map_to_field)(u32 val, u32 num_bits);
-        u32     extra;
-};
-
-typedef struct mv64x60_handle   mv64x60_handle_t;
-struct mv64x60_chip_info {
-        u32     (*translate_size)(u32 base, u32 size, u32 num_bits);
-        u32     (*untranslate_size)(u32 base, u32 size, u32 num_bits);
-        void    (*set_pci2mem_window)(struct pci_controller *hose, u32 bus,
-                        u32 window, u32 base);
-        void    (*set_pci2regs_window)(struct mv64x60_handle *bh,
-                        struct pci_controller *hose, u32 bus, u32 base);
-        u32     (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window);
-        void    (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window);
-        void    (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window);
-        void    (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
-        void    (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
-        void    (*disable_all_windows)(mv64x60_handle_t *bh,
-                        struct mv64x60_setup_info *si);
-        void    (*config_io2mem_windows)(mv64x60_handle_t *bh,
-                        struct mv64x60_setup_info *si,
-                        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-        void    (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base);
-        void    (*chip_specific_init)(mv64x60_handle_t *bh,
-                        struct mv64x60_setup_info *si);
-
-        struct mv64x60_32bit_window     *window_tab_32bit;
-        struct mv64x60_64bit_window     *window_tab_64bit;
-};
-
-struct mv64x60_handle {
-        u32             type;           /* type of bridge */
-        u32             rev;            /* revision of bridge */
-        void            __iomem *v_base;/* virtual base addr of bridge regs */
-        phys_addr_t     p_base;         /* physical base addr of bridge regs */
-
-        u32             pci_mode_a;     /* pci 0 mode: conventional pci, pci-x*/
-        u32             pci_mode_b;     /* pci 1 mode: conventional pci, pci-x*/
-
-        u32             io_base_a;      /* vaddr of pci 0's I/O space */
-        u32             io_base_b;      /* vaddr of pci 1's I/O space */
-
-        struct pci_controller   *hose_a;
-        struct pci_controller   *hose_b;
-
-        struct mv64x60_chip_info *ci;   /* chip/bridge-specific info */
-};
-
-
-/* Define I/O routines for accessing registers on the 64x60 bridge. */
-extern inline void
-mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) {
-        ulong   flags;
-
-        spin_lock_irqsave(&mv64x60_lock, flags);
-        out_le32(bh->v_base + offset, val);
-        spin_unlock_irqrestore(&mv64x60_lock, flags);
-}
-
-extern inline u32
-mv64x60_read(struct mv64x60_handle *bh, u32 offset) {
-        ulong   flags;
-        u32     reg;
-
-        spin_lock_irqsave(&mv64x60_lock, flags);
-        reg = in_le32(bh->v_base + offset);
-        spin_unlock_irqrestore(&mv64x60_lock, flags);
-        return reg;
-}
-
-extern inline void
-mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
-{
-        u32     reg;
-        ulong   flags;
-
-        spin_lock_irqsave(&mv64x60_lock, flags);
-        reg = in_le32(bh->v_base + offs) & (~mask);
-        reg |= data & mask;
-        out_le32(bh->v_base + offs, reg);
-        spin_unlock_irqrestore(&mv64x60_lock, flags);
-}
-
-#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
-#define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
-
-#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
-#define MV64XXX_DEV_NAME        "mv64xxx"
-
-struct mv64xxx_pdata {
-        u32     hs_reg_valid;
-};
-#endif
-
-/* Externally visible function prototypes */
-int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
-u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
-void mv64x60_early_init(struct mv64x60_handle *bh,
-        struct mv64x60_setup_info *si);
-void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
-        u32 cfg_data, struct pci_controller **hose);
-int mv64x60_get_type(struct mv64x60_handle *bh);
-int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
-void __iomem *mv64x60_get_bridge_vbase(void);
-u32 mv64x60_get_bridge_type(void);
-u32 mv64x60_get_bridge_rev(void);
-void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
-        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
-        struct mv64x60_setup_info *si,
-        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
-        struct mv64x60_pci_info *pi, u32 bus);
-void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
-        struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus,
-        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-void mv64x60_config_resources(struct pci_controller *hose,
-        struct mv64x60_pci_info *pi, u32 io_base);
-void mv64x60_config_pci_params(struct pci_controller *hose,
-        struct mv64x60_pci_info *pi);
-void mv64x60_pd_fixup(struct mv64x60_handle *bh,
-        struct platform_device *pd_devs[], u32 entries);
-void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
-        u32 *base, u32 *size);
-void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base,
-        u32 size, u32 other_bits);
-void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
-        u32 *base_hi, u32 *base_lo, u32 *size);
-void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
-        u32 base_hi, u32 base_lo, u32 size, u32 other_bits);
-void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus);
-int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
-
-
-void gt64260_init_irq(void);
-int gt64260_get_irq(void);
-void mv64360_init_irq(void);
-int mv64360_get_irq(void);
-
-u32 mv64x60_mask(u32 val, u32 num_bits);
-u32 mv64x60_shift_left(u32 val, u32 num_bits);
-u32 mv64x60_shift_right(u32 val, u32 num_bits);
-u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
-        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-
-void mv64x60_progress_init(u32 base);
-void mv64x60_mpsc_progress(char *s, unsigned short hex);
-
-extern struct mv64x60_32bit_window
-        gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT];
-extern struct mv64x60_64bit_window
-        gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT];
-extern struct mv64x60_32bit_window
-        mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT];
-extern struct mv64x60_64bit_window
-        mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT];
-
-#endif /* __ASMPPC_MV64x60_H */
diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h
deleted file mode 100644
index 5b0704a3e6ea..000000000000
--- a/include/asm-ppc/mv64x60_defs.h
+++ /dev/null
@@ -1,976 +0,0 @@
-/*
- * include/asm-ppc/mv64x60_defs.h
- *
- * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
- * host bridges.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_MV64x60_DEFS_H
-#define __ASMPPC_MV64x60_DEFS_H
-
-/*
- * Define the Marvell bridges that are supported
- */
-#define MV64x60_TYPE_INVALID                    0
-#define MV64x60_TYPE_GT64260A                   1
-#define MV64x60_TYPE_GT64260B                   2
-#define MV64x60_TYPE_MV64360                    3
-#define MV64x60_TYPE_MV64361                    4
-#define MV64x60_TYPE_MV64362                    5
-#define MV64x60_TYPE_MV64460                    6
-
-
-/* Revisions of each supported chip */
-#define GT64260_REV_A                           0x10
-#define GT64260_REV_B                           0x20
-#define MV64360                                 0x01
-#define MV64460                                 0x01
-
-/* Minimum window size supported by 64260 is 1MB */
-#define GT64260_WINDOW_SIZE_MIN                 0x00100000
-#define MV64360_WINDOW_SIZE_MIN                 0x00010000
-
-#define MV64x60_TCLK_FREQ_MAX                   133333333U
-
-/* IRQ's for embedded controllers */
-#define MV64x60_IRQ_DEV                         1
-#define MV64x60_IRQ_CPU_ERR                     3
-#define MV64x60_IRQ_TIMER_0_1                   8
-#define MV64x60_IRQ_TIMER_2_3                   9
-#define MV64x60_IRQ_TIMER_4_5                   10
-#define MV64x60_IRQ_TIMER_6_7                   11
-#define MV64x60_IRQ_P1_GPP_0_7                  24
-#define MV64x60_IRQ_P1_GPP_8_15                 25
-#define MV64x60_IRQ_P1_GPP_16_23                26
-#define MV64x60_IRQ_P1_GPP_24_31                27
-#define MV64x60_IRQ_DOORBELL                    28
-#define MV64x60_IRQ_ETH_0                       32
-#define MV64x60_IRQ_ETH_1                       33
-#define MV64x60_IRQ_ETH_2                       34
-#define MV64x60_IRQ_SDMA_0                      36
-#define MV64x60_IRQ_I2C                         37
-#define MV64x60_IRQ_BRG                         39
-#define MV64x60_IRQ_MPSC_0                      40
-#define MV64x60_IRQ_MPSC_1                      42
-#define MV64x60_IRQ_COMM                        43
-#define MV64x60_IRQ_P0_GPP_0_7                  56
-#define MV64x60_IRQ_P0_GPP_8_15                 57
-#define MV64x60_IRQ_P0_GPP_16_23                58
-#define MV64x60_IRQ_P0_GPP_24_31                59
-
-#define MV64360_IRQ_PCI0                        12
-#define MV64360_IRQ_SRAM_PAR_ERR                13
-#define MV64360_IRQ_PCI1                        16
-#define MV64360_IRQ_SDMA_1                      38
-
-#define MV64x60_IRQ_GPP0                        64
-#define MV64x60_IRQ_GPP1                        65
-#define MV64x60_IRQ_GPP2                        66
-#define MV64x60_IRQ_GPP3                        67
-#define MV64x60_IRQ_GPP4                        68
-#define MV64x60_IRQ_GPP5                        69
-#define MV64x60_IRQ_GPP6                        70
-#define MV64x60_IRQ_GPP7                        71
-#define MV64x60_IRQ_GPP8                        72
-#define MV64x60_IRQ_GPP9                        73
-#define MV64x60_IRQ_GPP10                       74
-#define MV64x60_IRQ_GPP11                       75
-#define MV64x60_IRQ_GPP12                       76
-#define MV64x60_IRQ_GPP13                       77
-#define MV64x60_IRQ_GPP14                       78
-#define MV64x60_IRQ_GPP15                       79
-#define MV64x60_IRQ_GPP16                       80
-#define MV64x60_IRQ_GPP17                       81
-#define MV64x60_IRQ_GPP18                       82
-#define MV64x60_IRQ_GPP19                       83
-#define MV64x60_IRQ_GPP20                       84
-#define MV64x60_IRQ_GPP21                       85
-#define MV64x60_IRQ_GPP22                       86
-#define MV64x60_IRQ_GPP23                       87
-#define MV64x60_IRQ_GPP24                       88
-#define MV64x60_IRQ_GPP25                       89
-#define MV64x60_IRQ_GPP26                       90
-#define MV64x60_IRQ_GPP27                       91
-#define MV64x60_IRQ_GPP28                       92
-#define MV64x60_IRQ_GPP29                       93
-#define MV64x60_IRQ_GPP30                       94
-#define MV64x60_IRQ_GPP31                       95
-
-/* Offsets for register blocks */
-#define GT64260_ENET_PHY_ADDR                   0x2000
-#define GT64260_ENET_ESMIR                      0x2010
-#define GT64260_ENET_0_OFFSET                   0x2400
-#define GT64260_ENET_1_OFFSET                   0x2800
-#define GT64260_ENET_2_OFFSET                   0x2c00
-#define MV64x60_SDMA_0_OFFSET                   0x4000
-#define MV64x60_SDMA_1_OFFSET                   0x6000
-#define MV64x60_MPSC_0_OFFSET                   0x8000
-#define MV64x60_MPSC_1_OFFSET                   0x9000
-#define MV64x60_MPSC_ROUTING_OFFSET             0xb400
-#define MV64x60_SDMA_INTR_OFFSET                0xb800
-#define MV64x60_BRG_0_OFFSET                    0xb200
-#define MV64x60_BRG_1_OFFSET                    0xb208
-
-/*
- *****************************************************************************
- *
- *      CPU Interface Registers
- *
- *****************************************************************************
- */
-
-/* CPU physical address of bridge's registers */
-#define MV64x60_INTERNAL_SPACE_DECODE           0x0068
-#define MV64x60_INTERNAL_SPACE_SIZE             0x10000
-#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR     0x14000000
-
-#define MV64360_CPU_BAR_ENABLE                  0x0278
-
-/* CPU Memory Controller Window Registers (4 windows) */
-#define MV64x60_CPU2MEM_WINDOWS                 4
-
-#define MV64x60_CPU2MEM_0_BASE                  0x0008
-#define MV64x60_CPU2MEM_0_SIZE                  0x0010
-#define MV64x60_CPU2MEM_1_BASE                  0x0208
-#define MV64x60_CPU2MEM_1_SIZE                  0x0210
-#define MV64x60_CPU2MEM_2_BASE                  0x0018
-#define MV64x60_CPU2MEM_2_SIZE                  0x0020
-#define MV64x60_CPU2MEM_3_BASE                  0x0218
-#define MV64x60_CPU2MEM_3_SIZE                  0x0220
-
-/* CPU Device Controller Window Registers (4 windows) */
-#define MV64x60_CPU2DEV_WINDOWS                 4
-
-#define MV64x60_CPU2DEV_0_BASE                  0x0028
-#define MV64x60_CPU2DEV_0_SIZE                  0x0030
-#define MV64x60_CPU2DEV_1_BASE                  0x0228
-#define MV64x60_CPU2DEV_1_SIZE                  0x0230
-#define MV64x60_CPU2DEV_2_BASE                  0x0248
-#define MV64x60_CPU2DEV_2_SIZE                  0x0250
-#define MV64x60_CPU2DEV_3_BASE                  0x0038
-#define MV64x60_CPU2DEV_3_SIZE                  0x0040
-
-#define MV64x60_CPU2BOOT_0_BASE                 0x0238
-#define MV64x60_CPU2BOOT_0_SIZE                 0x0240
-
-#define MV64360_CPU2SRAM_BASE                   0x0268
-
-/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
-#define MV64x60_PCI_BUSES                       2
-#define MV64x60_PCI_IO_WINDOWS_PER_BUS          1
-#define MV64x60_PCI_MEM_WINDOWS_PER_BUS         4
-
-#define MV64x60_CPU2PCI_SWAP_BYTE               0x00000000
-#define MV64x60_CPU2PCI_SWAP_NONE               0x01000000
-#define MV64x60_CPU2PCI_SWAP_BYTE_WORD          0x02000000
-#define MV64x60_CPU2PCI_SWAP_WORD               0x03000000
-
-#define MV64x60_CPU2PCI_MEM_REQ64               (1<<27)
-
-#define MV64x60_CPU2PCI0_IO_BASE                0x0048
-#define MV64x60_CPU2PCI0_IO_SIZE                0x0050
-#define MV64x60_CPU2PCI0_MEM_0_BASE             0x0058
-#define MV64x60_CPU2PCI0_MEM_0_SIZE             0x0060
-#define MV64x60_CPU2PCI0_MEM_1_BASE             0x0080
-#define MV64x60_CPU2PCI0_MEM_1_SIZE             0x0088
-#define MV64x60_CPU2PCI0_MEM_2_BASE             0x0258
-#define MV64x60_CPU2PCI0_MEM_2_SIZE             0x0260
-#define MV64x60_CPU2PCI0_MEM_3_BASE             0x0280
-#define MV64x60_CPU2PCI0_MEM_3_SIZE             0x0288
-
-#define MV64x60_CPU2PCI0_IO_REMAP               0x00f0
-#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO         0x00f8
-#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI         0x0320
-#define MV64x60_CPU2PCI0_MEM_1_REMAP_LO         0x0100
-#define MV64x60_CPU2PCI0_MEM_1_REMAP_HI         0x0328
-#define MV64x60_CPU2PCI0_MEM_2_REMAP_LO         0x02f8
-#define MV64x60_CPU2PCI0_MEM_2_REMAP_HI         0x0330
-#define MV64x60_CPU2PCI0_MEM_3_REMAP_LO         0x0300
-#define MV64x60_CPU2PCI0_MEM_3_REMAP_HI         0x0338
-
-#define MV64x60_CPU2PCI1_IO_BASE                0x0090
-#define MV64x60_CPU2PCI1_IO_SIZE                0x0098
-#define MV64x60_CPU2PCI1_MEM_0_BASE             0x00a0
-#define MV64x60_CPU2PCI1_MEM_0_SIZE             0x00a8
-#define MV64x60_CPU2PCI1_MEM_1_BASE             0x00b0
-#define MV64x60_CPU2PCI1_MEM_1_SIZE             0x00b8
-#define MV64x60_CPU2PCI1_MEM_2_BASE             0x02a0
-#define MV64x60_CPU2PCI1_MEM_2_SIZE             0x02a8
-#define MV64x60_CPU2PCI1_MEM_3_BASE             0x02b0
-#define MV64x60_CPU2PCI1_MEM_3_SIZE             0x02b8
-
-#define MV64x60_CPU2PCI1_IO_REMAP               0x0108
-#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO         0x0110
-#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI         0x0340
-#define MV64x60_CPU2PCI1_MEM_1_REMAP_LO         0x0118
-#define MV64x60_CPU2PCI1_MEM_1_REMAP_HI         0x0348
-#define MV64x60_CPU2PCI1_MEM_2_REMAP_LO         0x0310
-#define MV64x60_CPU2PCI1_MEM_2_REMAP_HI         0x0350
-#define MV64x60_CPU2PCI1_MEM_3_REMAP_LO         0x0318
-#define MV64x60_CPU2PCI1_MEM_3_REMAP_HI         0x0358
-
-/* CPU Control Registers */
-#define MV64x60_CPU_CONFIG                      0x0000
-#define MV64x60_CPU_MODE                        0x0120
-#define MV64x60_CPU_MASTER_CNTL                 0x0160
-#define MV64x60_CPU_XBAR_CNTL_LO                0x0150
-#define MV64x60_CPU_XBAR_CNTL_HI                0x0158
-#define MV64x60_CPU_XBAR_TO                     0x0168
-
-#define GT64260_CPU_RR_XBAR_CNTL_LO             0x0170
-#define GT64260_CPU_RR_XBAR_CNTL_HI             0x0178
-
-#define MV64360_CPU_PADS_CALIBRATION            0x03b4
-#define MV64360_CPU_RESET_SAMPLE_LO             0x03c4
-#define MV64360_CPU_RESET_SAMPLE_HI             0x03d4
-
-/* SMP Register Map */
-#define MV64360_WHO_AM_I                        0x0200
-#define MV64360_CPU0_DOORBELL                   0x0214
-#define MV64360_CPU0_DOORBELL_CLR               0x021c
-#define MV64360_CPU0_DOORBELL_MASK              0x0234
-#define MV64360_CPU1_DOORBELL                   0x0224
-#define MV64360_CPU1_DOORBELL_CLR               0x022c
-#define MV64360_CPU1_DOORBELL_MASK              0x023c
-#define MV64360_CPUx_DOORBELL(x)                (0x0214 + ((x)*0x10))
-#define MV64360_CPUx_DOORBELL_CLR(x)            (0x021c + ((x)*0x10))
-#define MV64360_CPUx_DOORBELL_MASK(x)           (0x0234 + ((x)*0x08))
-#define MV64360_SEMAPHORE_0                     0x0244
-#define MV64360_SEMAPHORE_1                     0x024c
-#define MV64360_SEMAPHORE_2                     0x0254
-#define MV64360_SEMAPHORE_3                     0x025c
-#define MV64360_SEMAPHORE_4                     0x0264
-#define MV64360_SEMAPHORE_5                     0x026c
-#define MV64360_SEMAPHORE_6                     0x0274
-#define MV64360_SEMAPHORE_7                     0x027c
-
-/* CPU Sync Barrier Registers */
-#define GT64260_CPU_SYNC_BARRIER_PCI0           0x00c0
-#define GT64260_CPU_SYNC_BARRIER_PCI1           0x00c8
-
-#define MV64360_CPU0_SYNC_BARRIER_TRIG          0x00c0
-#define MV64360_CPU0_SYNC_BARRIER_VIRT          0x00c8
-#define MV64360_CPU1_SYNC_BARRIER_TRIG          0x00d0
-#define MV64360_CPU1_SYNC_BARRIER_VIRT          0x00d8
-
-/* CPU Deadlock and Ordering registers (Rev B part only) */
-#define GT64260_CPU_DEADLOCK_ORDERING                   0x02d0
-#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH            0x02d8
-#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE     0x02e0
-
-/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
-#define MV64x260_CPU_PROT_WINDOWS               4
-
-#define GT64260_CPU_PROT_ACCPROTECT             (1<<16)
-#define GT64260_CPU_PROT_WRPROTECT              (1<<17)
-#define GT64260_CPU_PROT_CACHEPROTECT           (1<<18)
-
-#define MV64360_CPU_PROT_ACCPROTECT             (1<<20)
-#define MV64360_CPU_PROT_WRPROTECT              (1<<21)
-#define MV64360_CPU_PROT_CACHEPROTECT           (1<<22)
-#define MV64360_CPU_PROT_WIN_ENABLE             (1<<31)
-
-#define MV64x60_CPU_PROT_BASE_0                 0x0180
-#define MV64x60_CPU_PROT_SIZE_0                 0x0188
-#define MV64x60_CPU_PROT_BASE_1                 0x0190
-#define MV64x60_CPU_PROT_SIZE_1                 0x0198
-#define MV64x60_CPU_PROT_BASE_2                 0x01a0
-#define MV64x60_CPU_PROT_SIZE_2                 0x01a8
-#define MV64x60_CPU_PROT_BASE_3                 0x01b0
-#define MV64x60_CPU_PROT_SIZE_3                 0x01b8
-
-#define GT64260_CPU_PROT_BASE_4                 0x01c0
-#define GT64260_CPU_PROT_SIZE_4                 0x01c8
-#define GT64260_CPU_PROT_BASE_5                 0x01d0
-#define GT64260_CPU_PROT_SIZE_5                 0x01d8
-#define GT64260_CPU_PROT_BASE_6                 0x01e0
-#define GT64260_CPU_PROT_SIZE_6                 0x01e8
-#define GT64260_CPU_PROT_BASE_7                 0x01f0
-#define GT64260_CPU_PROT_SIZE_7                 0x01f8
-
-/* CPU Snoop Control Registers (64260 only) */
-#define GT64260_CPU_SNOOP_WINDOWS               4
-
-#define GT64260_CPU_SNOOP_NONE                  0x00000000
-#define GT64260_CPU_SNOOP_WT                    0x00010000
-#define GT64260_CPU_SNOOP_WB                    0x00020000
-#define GT64260_CPU_SNOOP_MASK                  0x00030000
-#define GT64260_CPU_SNOOP_ALL_BITS              GT64260_CPU_SNOOP_MASK
-
-#define GT64260_CPU_SNOOP_BASE_0                0x0380
-#define GT64260_CPU_SNOOP_SIZE_0                0x0388
-#define GT64260_CPU_SNOOP_BASE_1                0x0390
-#define GT64260_CPU_SNOOP_SIZE_1                0x0398
-#define GT64260_CPU_SNOOP_BASE_2                0x03a0
-#define GT64260_CPU_SNOOP_SIZE_2                0x03a8
-#define GT64260_CPU_SNOOP_BASE_3                0x03b0
-#define GT64260_CPU_SNOOP_SIZE_3                0x03b8
-
-/* CPU Snoop Control Registers (64360 only) */
-#define MV64360_CPU_SNOOP_WINDOWS               4
-#define MV64360_CPU_SNOOP_NONE                  0x00000000
-#define MV64360_CPU_SNOOP_WT                    0x00010000
-#define MV64360_CPU_SNOOP_WB                    0x00020000
-#define MV64360_CPU_SNOOP_MASK                  0x00030000
-#define MV64360_CPU_SNOOP_ALL_BITS              MV64360_CPU_SNOOP_MASK
-
-
-/* CPU Error Report Registers */
-#define MV64x60_CPU_ERR_ADDR_LO                 0x0070
-#define MV64x60_CPU_ERR_ADDR_HI                 0x0078
-#define MV64x60_CPU_ERR_DATA_LO                 0x0128
-#define MV64x60_CPU_ERR_DATA_HI                 0x0130
-#define MV64x60_CPU_ERR_PARITY                  0x0138
-#define MV64x60_CPU_ERR_CAUSE                   0x0140
-#define MV64x60_CPU_ERR_MASK                    0x0148
-
-/*
- *****************************************************************************
- *
- *      SRAM Controller Registers
- *
- *****************************************************************************
- */
-
-#define MV64360_SRAM_CONFIG                     0x0380
-#define MV64360_SRAM_TEST_MODE                  0x03f4
-#define MV64360_SRAM_ERR_CAUSE                  0x0388
-#define MV64360_SRAM_ERR_ADDR_LO                0x0390
-#define MV64360_SRAM_ERR_ADDR_HI                0x03f8
-#define MV64360_SRAM_ERR_DATA_LO                0x0398
-#define MV64360_SRAM_ERR_DATA_HI                0x03a0
-#define MV64360_SRAM_ERR_PARITY                 0x03a8
-
-#define MV64360_SRAM_SIZE                       0x00040000 /* 2Mb/256KB SRAM */
-
-/*
- *****************************************************************************
- *
- *      SDRAM/MEM Controller Registers
- *
- *****************************************************************************
- */
-
-/* SDRAM Config Registers (64260) */
-#define GT64260_SDRAM_CONFIG                    0x0448
-
-/* SDRAM Error Report Registers (64260) */
-#define GT64260_SDRAM_ERR_DATA_LO               0x0484
-#define GT64260_SDRAM_ERR_DATA_HI               0x0480
-#define GT64260_SDRAM_ERR_ADDR                  0x0490
-#define GT64260_SDRAM_ERR_ECC_RCVD              0x0488
-#define GT64260_SDRAM_ERR_ECC_CALC              0x048c
-#define GT64260_SDRAM_ERR_ECC_CNTL              0x0494
-#define GT64260_SDRAM_ERR_ECC_ERR_CNT           0x0498
-
-/* SDRAM Config Registers (64360) */
-#define MV64360_SDRAM_CONFIG                    0x1400
-
-/* SDRAM Control Registers */
-#define MV64360_D_UNIT_CONTROL_LOW              0x1404
-#define MV64360_D_UNIT_CONTROL_HIGH             0x1424
-#define MV64460_D_UNIT_MMASK                    0x14b0
-
-/* SDRAM Error Report Registers (64360) */
-#define MV64360_SDRAM_ERR_DATA_LO               0x1444
-#define MV64360_SDRAM_ERR_DATA_HI               0x1440
-#define MV64360_SDRAM_ERR_ADDR                  0x1450
-#define MV64360_SDRAM_ERR_ECC_RCVD              0x1448
-#define MV64360_SDRAM_ERR_ECC_CALC              0x144c
-#define MV64360_SDRAM_ERR_ECC_CNTL              0x1454
-#define MV64360_SDRAM_ERR_ECC_ERR_CNT           0x1458
-
-/*
- *****************************************************************************
- *
- *      Device/BOOT Controller Registers
- *
- *****************************************************************************
- */
-
-/* Device Control Registers */
-#define MV64x60_DEV_BANK_PARAMS_0               0x045c
-#define MV64x60_DEV_BANK_PARAMS_1               0x0460
-#define MV64x60_DEV_BANK_PARAMS_2               0x0464
-#define MV64x60_DEV_BANK_PARAMS_3               0x0468
-#define MV64x60_DEV_BOOT_PARAMS                 0x046c
-#define MV64x60_DEV_IF_CNTL                     0x04c0
-#define MV64x60_DEV_IF_XBAR_CNTL_LO             0x04c8
-#define MV64x60_DEV_IF_XBAR_CNTL_HI             0x04cc
-#define MV64x60_DEV_IF_XBAR_CNTL_TO             0x04c4
-
-/* Device Interrupt Registers */
-#define MV64x60_DEV_INTR_CAUSE                  0x04d0
-#define MV64x60_DEV_INTR_MASK                   0x04d4
-#define MV64x60_DEV_INTR_ERR_ADDR               0x04d8
-
-#define MV64360_DEV_INTR_ERR_DATA               0x04dc
-#define MV64360_DEV_INTR_ERR_PAR                0x04e0
-
-/*
- *****************************************************************************
- *
- *      PCI Bridge Interface Registers
- *
- *****************************************************************************
- */
-
-/* PCI Configuration Access Registers */
-#define MV64x60_PCI0_CONFIG_ADDR                0x0cf8
-#define MV64x60_PCI0_CONFIG_DATA                0x0cfc
-#define MV64x60_PCI0_IACK                       0x0c34
-
-#define MV64x60_PCI1_CONFIG_ADDR                0x0c78
-#define MV64x60_PCI1_CONFIG_DATA                0x0c7c
-#define MV64x60_PCI1_IACK                       0x0cb4
-
-/* PCI Control Registers */
-#define MV64x60_PCI0_CMD                        0x0c00
-#define MV64x60_PCI0_MODE                       0x0d00
-#define MV64x60_PCI0_TO_RETRY                   0x0c04
-#define MV64x60_PCI0_RD_BUF_DISCARD_TIMER       0x0d04
-#define MV64x60_PCI0_MSI_TRIGGER_TIMER          0x0c38
-#define MV64x60_PCI0_ARBITER_CNTL               0x1d00
-#define MV64x60_PCI0_XBAR_CNTL_LO               0x1d08
-#define MV64x60_PCI0_XBAR_CNTL_HI               0x1d0c
-#define MV64x60_PCI0_XBAR_CNTL_TO               0x1d04
-#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO       0x1d18
-#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI       0x1d1c
-#define MV64x60_PCI0_SYNC_BARRIER               0x1d10
-#define MV64x60_PCI0_P2P_CONFIG                 0x1d14
-#define MV64x60_PCI0_INTR_MASK
-
-#define GT64260_PCI0_P2P_SWAP_CNTL              0x1d54
-
-#define MV64x60_PCI1_CMD                        0x0c80
-#define MV64x60_PCI1_MODE                       0x0d80
-#define MV64x60_PCI1_TO_RETRY                   0x0c84
-#define MV64x60_PCI1_RD_BUF_DISCARD_TIMER       0x0d84
-#define MV64x60_PCI1_MSI_TRIGGER_TIMER          0x0cb8
-#define MV64x60_PCI1_ARBITER_CNTL               0x1d80
-#define MV64x60_PCI1_XBAR_CNTL_LO               0x1d88
-#define MV64x60_PCI1_XBAR_CNTL_HI               0x1d8c
-#define MV64x60_PCI1_XBAR_CNTL_TO               0x1d84
-#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO       0x1d98
-#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI       0x1d9c
-#define MV64x60_PCI1_SYNC_BARRIER               0x1d90
-#define MV64x60_PCI1_P2P_CONFIG                 0x1d94
-
-#define GT64260_PCI1_P2P_SWAP_CNTL              0x1dd4
-
-/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
-#define MV64x60_PCIMODE_CONVENTIONAL            0
-#define MV64x60_PCIMODE_PCIX_66                 (1 << 4)
-#define MV64x60_PCIMODE_PCIX_100                (2 << 4)
-#define MV64x60_PCIMODE_PCIX_133                (3 << 4)
-#define MV64x60_PCIMODE_MASK                    (0x3 << 4)
-
-/* PCI Access Control Regions Registers */
-#define GT64260_PCI_ACC_CNTL_PREFETCHEN         (1<<12)
-#define GT64260_PCI_ACC_CNTL_DREADEN            (1<<13)
-#define GT64260_PCI_ACC_CNTL_RDPREFETCH         (1<<16)
-#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH     (1<<17)
-#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH      (1<<18)
-#define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES    0x00000000
-#define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES    0x00100000
-#define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES   0x00200000
-#define GT64260_PCI_ACC_CNTL_MBURST_MASK        0x00300000
-#define GT64260_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
-#define GT64260_PCI_ACC_CNTL_SWAP_NONE          0x01000000
-#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x02000000
-#define GT64260_PCI_ACC_CNTL_SWAP_WORD          0x03000000
-#define GT64260_PCI_ACC_CNTL_SWAP_MASK          0x03000000
-#define GT64260_PCI_ACC_CNTL_ACCPROT            (1<<28)
-#define GT64260_PCI_ACC_CNTL_WRPROT             (1<<29)
-
-#define GT64260_PCI_ACC_CNTL_ALL_BITS   (GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
-                                         GT64260_PCI_ACC_CNTL_DREADEN |       \
-                                         GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
-                                         GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
-                                         GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
-                                         GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
-                                         GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
-                                         GT64260_PCI_ACC_CNTL_ACCPROT|        \
-                                         GT64260_PCI_ACC_CNTL_WRPROT)
-
-#define MV64360_PCI_ACC_CNTL_ENABLE             (1<<0)
-#define MV64360_PCI_ACC_CNTL_REQ64              (1<<1)
-#define MV64360_PCI_ACC_CNTL_SNOOP_NONE         0x00000000
-#define MV64360_PCI_ACC_CNTL_SNOOP_WT           0x00000004
-#define MV64360_PCI_ACC_CNTL_SNOOP_WB           0x00000008
-#define MV64360_PCI_ACC_CNTL_SNOOP_MASK         0x0000000c
-#define MV64360_PCI_ACC_CNTL_ACCPROT            (1<<4)
-#define MV64360_PCI_ACC_CNTL_WRPROT             (1<<5)
-#define MV64360_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
-#define MV64360_PCI_ACC_CNTL_SWAP_NONE          0x00000040
-#define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x00000080
-#define MV64360_PCI_ACC_CNTL_SWAP_WORD          0x000000c0
-#define MV64360_PCI_ACC_CNTL_SWAP_MASK          0x000000c0
-#define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES    0x00000000
-#define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES    0x00000100
-#define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES   0x00000200
-#define MV64360_PCI_ACC_CNTL_MBURST_MASK        0x00000300
-#define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES    0x00000000
-#define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES    0x00000400
-#define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES   0x00000800
-#define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES   0x00000c00
-#define MV64360_PCI_ACC_CNTL_RDSIZE_MASK        0x00000c00
-
-#define MV64360_PCI_ACC_CNTL_ALL_BITS   (MV64360_PCI_ACC_CNTL_ENABLE |      \
-                                         MV64360_PCI_ACC_CNTL_REQ64 |       \
-                                         MV64360_PCI_ACC_CNTL_SNOOP_MASK |  \
-                                         MV64360_PCI_ACC_CNTL_ACCPROT |     \
-                                         MV64360_PCI_ACC_CNTL_WRPROT |      \
-                                         MV64360_PCI_ACC_CNTL_SWAP_MASK |   \
-                                         MV64360_PCI_ACC_CNTL_MBURST_MASK | \
-                                         MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
-
-#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO         0x1e00
-#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI         0x1e04
-#define MV64x60_PCI0_ACC_CNTL_0_SIZE            0x1e08
-#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO         0x1e10
-#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI         0x1e14
-#define MV64x60_PCI0_ACC_CNTL_1_SIZE            0x1e18
-#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO         0x1e20
-#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI         0x1e24
-#define MV64x60_PCI0_ACC_CNTL_2_SIZE            0x1e28
-#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO         0x1e30
-#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI         0x1e34
-#define MV64x60_PCI0_ACC_CNTL_3_SIZE            0x1e38
-#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO         0x1e40
-#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI         0x1e44
-#define MV64x60_PCI0_ACC_CNTL_4_SIZE            0x1e48
-#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO         0x1e50
-#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI         0x1e54
-#define MV64x60_PCI0_ACC_CNTL_5_SIZE            0x1e58
-
-#define GT64260_PCI0_ACC_CNTL_6_BASE_LO         0x1e60
-#define GT64260_PCI0_ACC_CNTL_6_BASE_HI         0x1e64
-#define GT64260_PCI0_ACC_CNTL_6_SIZE            0x1e68
-#define GT64260_PCI0_ACC_CNTL_7_BASE_LO         0x1e70
-#define GT64260_PCI0_ACC_CNTL_7_BASE_HI         0x1e74
-#define GT64260_PCI0_ACC_CNTL_7_SIZE            0x1e78
-
-#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO         0x1e80
-#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI         0x1e84
-#define MV64x60_PCI1_ACC_CNTL_0_SIZE            0x1e88
-#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO         0x1e90
-#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI         0x1e94
-#define MV64x60_PCI1_ACC_CNTL_1_SIZE            0x1e98
-#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO         0x1ea0
-#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI         0x1ea4
-#define MV64x60_PCI1_ACC_CNTL_2_SIZE            0x1ea8
-#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO         0x1eb0
-#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI         0x1eb4
-#define MV64x60_PCI1_ACC_CNTL_3_SIZE            0x1eb8
-#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO         0x1ec0
-#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI         0x1ec4
-#define MV64x60_PCI1_ACC_CNTL_4_SIZE            0x1ec8
-#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO         0x1ed0
-#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI         0x1ed4
-#define MV64x60_PCI1_ACC_CNTL_5_SIZE            0x1ed8
-
-#define GT64260_PCI1_ACC_CNTL_6_BASE_LO         0x1ee0
-#define GT64260_PCI1_ACC_CNTL_6_BASE_HI         0x1ee4
-#define GT64260_PCI1_ACC_CNTL_6_SIZE            0x1ee8
-#define GT64260_PCI1_ACC_CNTL_7_BASE_LO         0x1ef0
-#define GT64260_PCI1_ACC_CNTL_7_BASE_HI         0x1ef4
-#define GT64260_PCI1_ACC_CNTL_7_SIZE            0x1ef8
-
-/* PCI Snoop Control Registers (64260 only) */
-#define GT64260_PCI_SNOOP_NONE                  0x00000000
-#define GT64260_PCI_SNOOP_WT                    0x00001000
-#define GT64260_PCI_SNOOP_WB                    0x00002000
-
-#define GT64260_PCI0_SNOOP_0_BASE_LO            0x1f00
-#define GT64260_PCI0_SNOOP_0_BASE_HI            0x1f04
-#define GT64260_PCI0_SNOOP_0_SIZE               0x1f08
-#define GT64260_PCI0_SNOOP_1_BASE_LO            0x1f10
-#define GT64260_PCI0_SNOOP_1_BASE_HI            0x1f14
-#define GT64260_PCI0_SNOOP_1_SIZE               0x1f18
-#define GT64260_PCI0_SNOOP_2_BASE_LO            0x1f20
-#define GT64260_PCI0_SNOOP_2_BASE_HI            0x1f24
-#define GT64260_PCI0_SNOOP_2_SIZE               0x1f28
-#define GT64260_PCI0_SNOOP_3_BASE_LO            0x1f30
-#define GT64260_PCI0_SNOOP_3_BASE_HI            0x1f34
-#define GT64260_PCI0_SNOOP_3_SIZE               0x1f38
-
-#define GT64260_PCI1_SNOOP_0_BASE_LO            0x1f80
-#define GT64260_PCI1_SNOOP_0_BASE_HI            0x1f84
-#define GT64260_PCI1_SNOOP_0_SIZE               0x1f88
-#define GT64260_PCI1_SNOOP_1_BASE_LO            0x1f90
-#define GT64260_PCI1_SNOOP_1_BASE_HI            0x1f94
-#define GT64260_PCI1_SNOOP_1_SIZE               0x1f98
-#define GT64260_PCI1_SNOOP_2_BASE_LO            0x1fa0
-#define GT64260_PCI1_SNOOP_2_BASE_HI            0x1fa4
-#define GT64260_PCI1_SNOOP_2_SIZE               0x1fa8
-#define GT64260_PCI1_SNOOP_3_BASE_LO            0x1fb0
-#define GT64260_PCI1_SNOOP_3_BASE_HI            0x1fb4
-#define GT64260_PCI1_SNOOP_3_SIZE               0x1fb8
-
-/* PCI Error Report Registers */
-#define MV64x60_PCI0_ERR_SERR_MASK              0x0c28
-#define MV64x60_PCI0_ERR_ADDR_LO                0x1d40
-#define MV64x60_PCI0_ERR_ADDR_HI                0x1d44
-#define MV64x60_PCI0_ERR_DATA_LO                0x1d48
-#define MV64x60_PCI0_ERR_DATA_HI                0x1d4c
-#define MV64x60_PCI0_ERR_CMD                    0x1d50
-#define MV64x60_PCI0_ERR_CAUSE                  0x1d58
-#define MV64x60_PCI0_ERR_MASK                   0x1d5c
-
-#define MV64x60_PCI1_ERR_SERR_MASK              0x0ca8
-#define MV64x60_PCI1_ERR_ADDR_LO                0x1dc0
-#define MV64x60_PCI1_ERR_ADDR_HI                0x1dc4
-#define MV64x60_PCI1_ERR_DATA_LO                0x1dc8
-#define MV64x60_PCI1_ERR_DATA_HI                0x1dcc
-#define MV64x60_PCI1_ERR_CMD                    0x1dd0
-#define MV64x60_PCI1_ERR_CAUSE                  0x1dd8
-#define MV64x60_PCI1_ERR_MASK                   0x1ddc
-
-/* PCI Slave Address Decoding Registers */
-#define MV64x60_PCI0_MEM_0_SIZE                 0x0c08
-#define MV64x60_PCI0_MEM_1_SIZE                 0x0d08
-#define MV64x60_PCI0_MEM_2_SIZE                 0x0c0c
-#define MV64x60_PCI0_MEM_3_SIZE                 0x0d0c
-#define MV64x60_PCI1_MEM_0_SIZE                 0x0c88
-#define MV64x60_PCI1_MEM_1_SIZE                 0x0d88
-#define MV64x60_PCI1_MEM_2_SIZE                 0x0c8c
-#define MV64x60_PCI1_MEM_3_SIZE                 0x0d8c
-
-#define MV64x60_PCI0_BAR_ENABLE                 0x0c3c
-#define MV64x60_PCI1_BAR_ENABLE                 0x0cbc
-
-#define MV64x60_PCI0_PCI_DECODE_CNTL            0x0d3c
-#define MV64x60_PCI1_PCI_DECODE_CNTL            0x0dbc
-
-#define MV64x60_PCI0_SLAVE_MEM_0_REMAP          0x0c48
-#define MV64x60_PCI0_SLAVE_MEM_1_REMAP          0x0d48
-#define MV64x60_PCI0_SLAVE_MEM_2_REMAP          0x0c4c
-#define MV64x60_PCI0_SLAVE_MEM_3_REMAP          0x0d4c
-#define MV64x60_PCI0_SLAVE_DEV_0_REMAP          0x0c50
-#define MV64x60_PCI0_SLAVE_DEV_1_REMAP          0x0d50
-#define MV64x60_PCI0_SLAVE_DEV_2_REMAP          0x0d58
-#define MV64x60_PCI0_SLAVE_DEV_3_REMAP          0x0c54
-#define MV64x60_PCI0_SLAVE_BOOT_REMAP           0x0d54
-#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO   0x0d5c
-#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI   0x0d60
-#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO   0x0d64
-#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI   0x0d68
-#define MV64x60_PCI0_SLAVE_P2P_IO_REMAP         0x0d6c
-#define MV64x60_PCI0_SLAVE_CPU_REMAP            0x0d70
-
-#define MV64x60_PCI1_SLAVE_MEM_0_REMAP          0x0cc8
-#define MV64x60_PCI1_SLAVE_MEM_1_REMAP          0x0dc8
-#define MV64x60_PCI1_SLAVE_MEM_2_REMAP          0x0ccc
-#define MV64x60_PCI1_SLAVE_MEM_3_REMAP          0x0dcc
-#define MV64x60_PCI1_SLAVE_DEV_0_REMAP          0x0cd0
-#define MV64x60_PCI1_SLAVE_DEV_1_REMAP          0x0dd0
-#define MV64x60_PCI1_SLAVE_DEV_2_REMAP          0x0dd8
-#define MV64x60_PCI1_SLAVE_DEV_3_REMAP          0x0cd4
-#define MV64x60_PCI1_SLAVE_BOOT_REMAP           0x0dd4
-#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO   0x0ddc
-#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI   0x0de0
-#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO   0x0de4
-#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI   0x0de8
-#define MV64x60_PCI1_SLAVE_P2P_IO_REMAP         0x0dec
-#define MV64x60_PCI1_SLAVE_CPU_REMAP            0x0df0
-
-#define MV64360_PCICFG_CPCI_HOTSWAP             0x68
-
-/*
- *****************************************************************************
- *
- *      ENET Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* ENET Controller Window Registers (6 windows) */
-#define MV64360_ENET2MEM_WINDOWS                6
-
-#define MV64360_ENET2MEM_0_BASE                 0x2200
-#define MV64360_ENET2MEM_0_SIZE                 0x2204
-#define MV64360_ENET2MEM_1_BASE                 0x2208
-#define MV64360_ENET2MEM_1_SIZE                 0x220c
-#define MV64360_ENET2MEM_2_BASE                 0x2210
-#define MV64360_ENET2MEM_2_SIZE                 0x2214
-#define MV64360_ENET2MEM_3_BASE                 0x2218
-#define MV64360_ENET2MEM_3_SIZE                 0x221c
-#define MV64360_ENET2MEM_4_BASE                 0x2220
-#define MV64360_ENET2MEM_4_SIZE                 0x2224
-#define MV64360_ENET2MEM_5_BASE                 0x2228
-#define MV64360_ENET2MEM_5_SIZE                 0x222c
-
-#define MV64360_ENET2MEM_SNOOP_NONE             0x00000000
-#define MV64360_ENET2MEM_SNOOP_WT               0x00001000
-#define MV64360_ENET2MEM_SNOOP_WB               0x00002000
-
-#define MV64360_ENET2MEM_BAR_ENABLE             0x2290
-
-#define MV64360_ENET2MEM_ACC_PROT_0             0x2294
-#define MV64360_ENET2MEM_ACC_PROT_1             0x2298
-#define MV64360_ENET2MEM_ACC_PROT_2             0x229c
-
-/*
- *****************************************************************************
- *
- *      MPSC Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* MPSC Controller Window Registers (4 windows) */
-#define MV64360_MPSC2MEM_WINDOWS                4
-
-#define MV64360_MPSC2MEM_0_BASE                 0xf200
-#define MV64360_MPSC2MEM_0_SIZE                 0xf204
-#define MV64360_MPSC2MEM_1_BASE                 0xf208
-#define MV64360_MPSC2MEM_1_SIZE                 0xf20c
-#define MV64360_MPSC2MEM_2_BASE                 0xf210
-#define MV64360_MPSC2MEM_2_SIZE                 0xf214
-#define MV64360_MPSC2MEM_3_BASE                 0xf218
-#define MV64360_MPSC2MEM_3_SIZE                 0xf21c
-
-#define MV64360_MPSC_0_REMAP                    0xf240
-#define MV64360_MPSC_1_REMAP                    0xf244
-
-#define MV64360_MPSC2MEM_SNOOP_NONE             0x00000000
-#define MV64360_MPSC2MEM_SNOOP_WT               0x00001000
-#define MV64360_MPSC2MEM_SNOOP_WB               0x00002000
-
-#define MV64360_MPSC2MEM_BAR_ENABLE             0xf250
-
-#define MV64360_MPSC2MEM_ACC_PROT_0             0xf254
-#define MV64360_MPSC2MEM_ACC_PROT_1             0xf258
-
-#define MV64360_MPSC2REGS_BASE                  0xf25c
-
-/*
- *****************************************************************************
- *
- *      Timer/Counter Interface Registers
- *
- *****************************************************************************
- */
-
-#define MV64x60_TIMR_CNTR_0                     0x0850
-#define MV64x60_TIMR_CNTR_1                     0x0854
-#define MV64x60_TIMR_CNTR_2                     0x0858
-#define MV64x60_TIMR_CNTR_3                     0x085c
-#define MV64x60_TIMR_CNTR_0_3_CNTL              0x0864
-#define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE        0x0868
-#define MV64x60_TIMR_CNTR_0_3_INTR_MASK         0x086c
-
-#define GT64260_TIMR_CNTR_4                     0x0950
-#define GT64260_TIMR_CNTR_5                     0x0954
-#define GT64260_TIMR_CNTR_6                     0x0958
-#define GT64260_TIMR_CNTR_7                     0x095c
-#define GT64260_TIMR_CNTR_4_7_CNTL              0x0964
-#define GT64260_TIMR_CNTR_4_7_INTR_CAUSE        0x0968
-#define GT64260_TIMR_CNTR_4_7_INTR_MASK         0x096c
-
-/*
- *****************************************************************************
- *
- *      Communications Controller
- *
- *****************************************************************************
- */
-
-#define GT64260_SER_INIT_PCI_ADDR_HI            0xf320
-#define GT64260_SER_INIT_LAST_DATA              0xf324
-#define GT64260_SER_INIT_CONTROL                0xf328
-#define GT64260_SER_INIT_STATUS                 0xf32c
-
-#define MV64x60_COMM_ARBITER_CNTL               0xf300
-#define MV64x60_COMM_CONFIG                     0xb40c
-#define MV64x60_COMM_XBAR_TO                    0xf304
-#define MV64x60_COMM_INTR_CAUSE                 0xf310
-#define MV64x60_COMM_INTR_MASK                  0xf314
-#define MV64x60_COMM_ERR_ADDR                   0xf318
-
-#define MV64360_COMM_ARBITER_CNTL               0xf300
-
-/*
- *****************************************************************************
- *
- *      IDMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* IDMA Controller Window Registers (8 windows) */
-#define MV64360_IDMA2MEM_WINDOWS                8
-
-#define MV64360_IDMA2MEM_0_BASE                 0x0a00
-#define MV64360_IDMA2MEM_0_SIZE                 0x0a04
-#define MV64360_IDMA2MEM_1_BASE                 0x0a08
-#define MV64360_IDMA2MEM_1_SIZE                 0x0a0c
-#define MV64360_IDMA2MEM_2_BASE                 0x0a10
-#define MV64360_IDMA2MEM_2_SIZE                 0x0a14
-#define MV64360_IDMA2MEM_3_BASE                 0x0a18
-#define MV64360_IDMA2MEM_3_SIZE                 0x0a1c
-#define MV64360_IDMA2MEM_4_BASE                 0x0a20
-#define MV64360_IDMA2MEM_4_SIZE                 0x0a24
-#define MV64360_IDMA2MEM_5_BASE                 0x0a28
-#define MV64360_IDMA2MEM_5_SIZE                 0x0a2c
-#define MV64360_IDMA2MEM_6_BASE                 0x0a30
-#define MV64360_IDMA2MEM_6_SIZE                 0x0a34
-#define MV64360_IDMA2MEM_7_BASE                 0x0a38
-#define MV64360_IDMA2MEM_7_SIZE                 0x0a3c
-
-#define MV64360_IDMA2MEM_SNOOP_NONE             0x00000000
-#define MV64360_IDMA2MEM_SNOOP_WT               0x00001000
-#define MV64360_IDMA2MEM_SNOOP_WB               0x00002000
-
-#define MV64360_IDMA2MEM_BAR_ENABLE             0x0a80
-
-#define MV64360_IDMA2MEM_ACC_PROT_0             0x0a70
-#define MV64360_IDMA2MEM_ACC_PROT_1             0x0a74
-#define MV64360_IDMA2MEM_ACC_PROT_2             0x0a78
-#define MV64360_IDMA2MEM_ACC_PROT_3             0x0a7c
-
-#define MV64x60_IDMA_0_OFFSET                   0x0800
-#define MV64x60_IDMA_1_OFFSET                   0x0804
-#define MV64x60_IDMA_2_OFFSET                   0x0808
-#define MV64x60_IDMA_3_OFFSET                   0x080c
-#define MV64x60_IDMA_4_OFFSET                   0x0900
-#define MV64x60_IDMA_5_OFFSET                   0x0904
-#define MV64x60_IDMA_6_OFFSET                   0x0908
-#define MV64x60_IDMA_7_OFFSET                   0x090c
-
-#define MV64x60_IDMA_BYTE_COUNT                 (0x0800 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_SRC_ADDR                   (0x0810 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_DST_ADDR                   (0x0820 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_NEXT_DESC                  (0x0830 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_CUR_DESC                   (0x0870 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_SRC_PCI_ADDR_HI            (0x0890 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_DST_PCI_ADDR_HI            (0x08a0 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI      (0x08b0 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_CONTROL_LO                 (0x0840 - MV64x60_IDMA_0_OFFSET)
-#define MV64x60_IDMA_CONTROL_HI                 (0x0880 - MV64x60_IDMA_0_OFFSET)
-
-#define MV64x60_IDMA_0_3_ARBITER_CNTL           0x0860
-#define MV64x60_IDMA_4_7_ARBITER_CNTL           0x0960
-
-#define MV64x60_IDMA_0_3_XBAR_TO                0x08d0
-#define MV64x60_IDMA_4_7_XBAR_TO                0x09d0
-
-#define MV64x60_IDMA_0_3_INTR_CAUSE             0x08c0
-#define MV64x60_IDMA_0_3_INTR_MASK              0x08c4
-#define MV64x60_IDMA_0_3_ERROR_ADDR             0x08c8
-#define MV64x60_IDMA_0_3_ERROR_SELECT           0x08cc
-#define MV64x60_IDMA_4_7_INTR_CAUSE             0x09c0
-#define MV64x60_IDMA_4_7_INTR_MASK              0x09c4
-#define MV64x60_IDMA_4_7_ERROR_ADDR             0x09c8
-#define MV64x60_IDMA_4_7_ERROR_SELECT           0x09cc
-
-/*
- *****************************************************************************
- *
- *      Watchdog Timer Interface Registers
- *
- *****************************************************************************
- */
-
-#define MV64x60_WDT_WDC                         0xb410
-#define MV64x60_WDT_WDV                         0xb414
-
-
-/*
- *****************************************************************************
- *
- *       General Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define MV64x60_GPP_IO_CNTL                     0xf100
-#define MV64x60_GPP_LEVEL_CNTL                  0xf110
-#define MV64x60_GPP_VALUE                       0xf104
-#define MV64x60_GPP_INTR_CAUSE                  0xf108
-#define MV64x60_GPP_INTR_MASK                   0xf10c
-#define MV64x60_GPP_VALUE_SET                   0xf118
-#define MV64x60_GPP_VALUE_CLR                   0xf11c
-
-
-/*
- *****************************************************************************
- *
- *      Multi-Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define MV64x60_MPP_CNTL_0                      0xf000
-#define MV64x60_MPP_CNTL_1                      0xf004
-#define MV64x60_MPP_CNTL_2                      0xf008
-#define MV64x60_MPP_CNTL_3                      0xf00c
-#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX      0xf010
-
-#define MV64x60_ETH_BAR_GAP                     0x8
-#define MV64x60_ETH_SIZE_REG_GAP                0x8
-#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP     0x4
-#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP        0x4
-
-#define MV64x60_EBAR_ATTR_DRAM_CS0              0x00000E00
-#define MV64x60_EBAR_ATTR_DRAM_CS1              0x00000D00
-#define MV64x60_EBAR_ATTR_DRAM_CS2              0x00000B00
-#define MV64x60_EBAR_ATTR_DRAM_CS3              0x00000700
-
-#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0       0x00000000
-#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1       0x00000100
-#define MV64x60_EBAR_ATTR_CBS_SRAM              0x00000000
-#define MV64x60_EBAR_ATTR_CBS_CPU_BUS           0x00000800
-
-
-/*
- *****************************************************************************
- *
- *      Interrupt Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define GT64260_IC_OFFSET                       0x0c18
-
-#define GT64260_IC_MAIN_CAUSE_LO                0x0c18
-#define GT64260_IC_MAIN_CAUSE_HI                0x0c68
-#define GT64260_IC_CPU_INTR_MASK_LO             0x0c1c
-#define GT64260_IC_CPU_INTR_MASK_HI             0x0c6c
-#define GT64260_IC_CPU_SELECT_CAUSE             0x0c70
-#define GT64260_IC_PCI0_INTR_MASK_LO            0x0c24
-#define GT64260_IC_PCI0_INTR_MASK_HI            0x0c64
-#define GT64260_IC_PCI0_SELECT_CAUSE            0x0c74
-#define GT64260_IC_PCI1_INTR_MASK_LO            0x0ca4
-#define GT64260_IC_PCI1_INTR_MASK_HI            0x0ce4
-#define GT64260_IC_PCI1_SELECT_CAUSE            0x0cf4
-#define GT64260_IC_CPU_INT_0_MASK               0x0e60
-#define GT64260_IC_CPU_INT_1_MASK               0x0e64
-#define GT64260_IC_CPU_INT_2_MASK               0x0e68
-#define GT64260_IC_CPU_INT_3_MASK               0x0e6c
-
-#define MV64360_IC_OFFSET                       0x0000
-
-#define MV64360_IC_MAIN_CAUSE_LO                0x0004
-#define MV64360_IC_MAIN_CAUSE_HI                0x000c
-#define MV64360_IC_CPU0_INTR_MASK_LO            0x0014
-#define MV64360_IC_CPU0_INTR_MASK_HI            0x001c
-#define MV64360_IC_CPU0_SELECT_CAUSE            0x0024
-#define MV64360_IC_CPU1_INTR_MASK_LO            0x0034
-#define MV64360_IC_CPU1_INTR_MASK_HI            0x003c
-#define MV64360_IC_CPU1_SELECT_CAUSE            0x0044
-#define MV64360_IC_INT0_MASK_LO                 0x0054
-#define MV64360_IC_INT0_MASK_HI                 0x005c
-#define MV64360_IC_INT0_SELECT_CAUSE            0x0064
-#define MV64360_IC_INT1_MASK_LO                 0x0074
-#define MV64360_IC_INT1_MASK_HI                 0x007c
-#define MV64360_IC_INT1_SELECT_CAUSE            0x0084
-
-#endif /* __ASMPPC_MV64x60_DEFS_H */
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
deleted file mode 100644
index 3909a2eec286..000000000000
--- a/include/asm-ppc/ocp.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * ocp.h
- *
- *      (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *          Mipsys - France
- *
- *          Derived from work (c) Armin Kuster akuster@pacbell.net
- *
- *          Additional support and port to 2.6 LDM/sysfs by
- *          Matt Porter <mporter@kernel.crashing.org>
- *          Copyright 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- *  TODO: - Add get/put interface & fixup locking to provide same API for
- *          2.4 and 2.5
- *        - Rework PM callbacks
- */
-
-#ifdef __KERNEL__
-#ifndef __OCP_H__
-#define __OCP_H__
-
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/device.h>
-#include <linux/rwsem.h>
-
-#include <asm/mmu.h>
-#include <asm/ocp_ids.h>
-
-#ifdef CONFIG_PPC_OCP
-
-#define OCP_MAX_IRQS    7
-#define MAX_EMACS       4
-#define OCP_IRQ_NA      -1      /* used when ocp device does not have an irq */
-#define OCP_IRQ_MUL     -2      /* used for ocp devices with multiply irqs */
-#define OCP_NULL_TYPE   -1      /* used to mark end of list */
-#define OCP_CPM_NA      0       /* No Clock or Power Management avaliable */
-#define OCP_PADDR_NA    0       /* No MMIO registers */
-
-#define OCP_ANY_ID      (~0)
-#define OCP_ANY_INDEX   -1
-
-extern struct list_head         ocp_devices;
-extern struct rw_semaphore      ocp_devices_sem;
-
-struct ocp_device_id {
-        unsigned int    vendor, function;       /* Vendor and function ID or OCP_ANY_ID */
-        unsigned long   driver_data;            /* Data private to the driver */
-};
-
-
-/*
- * Static definition of an OCP device.
- *
- * @vendor:    Vendor code. It is _STRONGLY_ discouraged to use
- *             the vendor code as a way to match a unique device,
- *             though I kept that possibility open, you should
- *             really define different function codes for different
- *             device types
- * @function:  This is the function code for this device.
- * @index:     This index is used for mapping the Nth function of a
- *             given core. This is typically used for cross-driver
- *             matching, like looking for a given MAL or ZMII from
- *             an EMAC or for getting to the proper set of DCRs.
- *             Indices are no longer magically calculated based on
- *             structure ordering, they have to be actually coded
- *             into the ocp_def to avoid any possible confusion
- *             I _STRONGLY_ (again ? wow !) encourage anybody relying
- *             on index mapping to encode the "target" index in an
- *             associated structure pointed to by "additions", see
- *             how it's done for the EMAC driver.
- * @paddr:     Device physical address (may not mean anything...)
- * @irq:       Interrupt line for this device (TODO: think about making
- *             an array with this)
- * @pm:        Currently, contains the bitmask in CPMFR DCR for the device
- * @additions: Optionally points to a function specific structure
- *             providing additional informations for a given device
- *             instance. It's currently used by the EMAC driver for MAL
- *             channel & ZMII port mapping among others.
- * @show:      Optionally points to a function specific structure
- *             providing a sysfs show routine for additions fields.
- */
-struct ocp_def {
-        unsigned int    vendor;
-        unsigned int    function;
-        int             index;
-        phys_addr_t     paddr;
-        int             irq;
-        unsigned long   pm;
-        void            *additions;
-        void            (*show)(struct device *);
-};
-
-
-/* Struct for a given device instance */
-struct ocp_device {
-        struct list_head        link;
-        char                    name[80];       /* device name */
-        struct ocp_def          *def;           /* device definition */
-        void                    *drvdata;       /* driver data for this device */
-        struct ocp_driver       *driver;
-        u32                     current_state;  /* Current operating state. In ACPI-speak,
-                                                   this is D0-D3, D0 being fully functional,
-                                                   and D3 being off. */
-        struct                  device dev;
-};
-
-struct ocp_driver {
-        struct list_head node;
-        char *name;
-        const struct ocp_device_id *id_table;   /* NULL if wants all devices */
-        int  (*probe)  (struct ocp_device *dev);        /* New device inserted */
-        void (*remove) (struct ocp_device *dev);        /* Device removed (NULL if not a hot-plug capable driver) */
-        int  (*suspend) (struct ocp_device *dev, pm_message_t state);   /* Device suspended */
-        int  (*resume) (struct ocp_device *dev);                        /* Device woken up */
-        struct device_driver driver;
-};
-
-#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
-#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
-
-/* Similar to the helpers above, these manipulate per-ocp_dev
- * driver-specific data.  Currently stored as ocp_dev::ocpdev,
- * a void pointer, but it is not present on older kernels.
- */
-static inline void *
-ocp_get_drvdata(struct ocp_device *pdev)
-{
-        return pdev->drvdata;
-}
-
-static inline void
-ocp_set_drvdata(struct ocp_device *pdev, void *data)
-{
-        pdev->drvdata = data;
-}
-
-#if defined (CONFIG_PM)
-/*
- * This is right for the IBM 405 and 440 but will need to be
- * generalized if the OCP stuff gets used on other processors.
- */
-static inline void
-ocp_force_power_off(struct ocp_device *odev)
-{
-        mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
-}
-
-static inline void
-ocp_force_power_on(struct ocp_device *odev)
-{
-        mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
-}
-#else
-#define ocp_force_power_off(x)  (void)(x)
-#define ocp_force_power_on(x)   (void)(x)
-#endif
-
-/* Register/Unregister an OCP driver */
-extern int ocp_register_driver(struct ocp_driver *drv);
-extern void ocp_unregister_driver(struct ocp_driver *drv);
-
-/* Build list of devices */
-extern int ocp_early_init(void) __init;
-
-/* Find a device by index */
-extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
-
-/* Get a def by index */
-extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Add a device by index */
-extern int ocp_add_one_device(struct ocp_def *def);
-
-/* Remove a device by index */
-extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Iterate over devices and execute a routine */
-extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
-
-/* Sysfs support */
-#define OCP_SYSFS_ADDTL(type, format, name, field)                      \
-static ssize_t                                                          \
-show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf)                     \
-{                                                                       \
-        struct ocp_device *odev = to_ocp_dev(dev);                      \
-        type *add = odev->def->additions;                               \
-                                                                        \
-        return sprintf(buf, format, add->field);                        \
-}                                                                       \
-static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
-
-#ifdef CONFIG_IBM_OCP
-#include <asm/ibm_ocp.h>
-#endif
-
-#endif                          /* CONFIG_PPC_OCP */
-#endif                          /* __OCP_H__ */
-#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
deleted file mode 100644
index 8ae4b311a37c..000000000000
--- a/include/asm-ppc/ocp_ids.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * ocp_ids.h
- *
- * OCP device ids based on the ideas from PCI
- *
- * The numbers below are almost completely arbitrary, and in fact
- * strings might work better.  -- paulus
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/*
- * Vender  device
- * [xxxx]  [xxxx]
- *
- *  Keep in order, please
- */
-
-/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
-
-#define OCP_VENDOR_INVALID      0x0000
-#define OCP_VENDOR_ARM          0x0004
-#define OCP_VENDOR_FREESCALE    0x1057
-#define OCP_VENDOR_IBM          0x1014
-#define OCP_VENDOR_MOTOROLA     OCP_VENDOR_FREESCALE
-#define OCP_VENDOR_XILINX       0x10ee
-#define OCP_VENDOR_UNKNOWN      0xFFFF
-
-/* device identification */
-
-/* define type */
-#define OCP_FUNC_INVALID        0x0000
-
-/* system 0x0001 - 0x001F */
-
-/* Timers 0x0020 - 0x002F */
-
-/* Serial 0x0030 - 0x006F*/
-#define OCP_FUNC_16550          0x0031
-#define OCP_FUNC_IIC            0x0032
-#define OCP_FUNC_USB            0x0033
-#define OCP_FUNC_PSC_UART       0x0034
-
-/* Memory devices 0x0090 - 0x009F */
-#define OCP_FUNC_MAL            0x0090
-#define OCP_FUNC_DMA            0x0091
-
-/* Display 0x00A0 - 0x00AF */
-
-/* Sound 0x00B0 - 0x00BF */
-
-/* Mass Storage 0x00C0 - 0xxCF */
-#define OCP_FUNC_IDE            0x00C0
-
-/* Misc 0x00D0 - 0x00DF*/
-#define OCP_FUNC_GPIO           0x00D0
-#define OCP_FUNC_ZMII           0x00D1
-#define OCP_FUNC_PERFMON        0x00D2  /* Performance Monitor */
-#define OCP_FUNC_RGMII          0x00D3
-#define OCP_FUNC_TAH            0x00D4
-#define OCP_FUNC_SEC2           0x00D5  /* Crypto/Security 2.0 */
-
-/* Network 0x0200 - 0x02FF */
-#define OCP_FUNC_EMAC           0x0200
-#define OCP_FUNC_GFAR           0x0201  /* TSEC & FEC */
-
-/* Bridge devices 0xE00 - 0xEFF */
-#define OCP_FUNC_OPB            0x0E00
-
-#define OCP_FUNC_UNKNOWN        0xFFFF
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
deleted file mode 100644
index 778d5726212c..000000000000
--- a/include/asm-ppc/open_pic.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *  include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- *
- */
-
-#ifndef _PPC_KERNEL_OPEN_PIC_H
-#define _PPC_KERNEL_OPEN_PIC_H
-
-#include <linux/irq.h>
-
-#define OPENPIC_SIZE    0x40000
-
-/*
- *  Non-offset'ed vector numbers
- */
-
-#define OPENPIC_VEC_TIMER       110     /* and up */
-#define OPENPIC_VEC_IPI         118     /* and up */
-#define OPENPIC_VEC_SPURIOUS    255
-
-/* Priorities */
-#define OPENPIC_PRIORITY_IPI_BASE       10
-#define OPENPIC_PRIORITY_DEFAULT        4
-#define OPENPIC_PRIORITY_NMI            9
-
-/* OpenPIC IRQ controller structure */
-extern struct hw_interrupt_type open_pic;
-
-/* OpenPIC IPI controller structure */
-#ifdef CONFIG_SMP
-extern struct hw_interrupt_type open_pic_ipi;
-#endif /* CONFIG_SMP */
-
-extern u_int OpenPIC_NumInitSenses;
-extern u_char *OpenPIC_InitSenses;
-extern void __iomem * OpenPIC_Addr;
-extern int epic_serial_mode;
-
-/* Exported functions */
-extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
-extern void openpic_init(int linux_irq_offset);
-extern void openpic_init_nmi_irq(u_int irq);
-extern void openpic_set_irq_priority(u_int irq, u_int pri);
-extern void openpic_hookup_cascade(u_int irq, char *name,
-                                   int (*cascade_fn)(void));
-extern u_int openpic_irq(void);
-extern void openpic_eoi(void);
-extern void openpic_request_IPIs(void);
-extern void do_openpic_setup_cpu(void);
-extern int openpic_get_irq(void);
-extern void openpic_reset_processor_phys(u_int cpumask);
-extern void openpic_setup_ISU(int isu_num, unsigned long addr);
-extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
-extern void smp_openpic_message_pass(int target, int msg);
-extern void openpic_set_k2_cascade(int irq);
-extern void openpic_set_priority(u_int pri);
-extern u_int openpic_get_priority(void);
-
-extern inline int openpic_to_irq(int irq)
-{
-        /* IRQ 0 usually means 'disabled'.. don't mess with it
-         * exceptions to this (sandpoint maybe?)
-         * shouldn't use openpic_to_irq
-         */
-        if (irq != 0){
-                return irq += NUM_8259_INTERRUPTS;
-        } else {
-                return 0;
-        }
-}
-/* Support for second openpic on G5 macs */
-
-// FIXME: To be replaced by sane cascaded controller management */
-
-#define PMAC_OPENPIC2_OFFSET    128
-
-#define OPENPIC2_VEC_TIMER      110     /* and up */
-#define OPENPIC2_VEC_IPI        118     /* and up */
-#define OPENPIC2_VEC_SPURIOUS   127
-
-
-extern void* OpenPIC2_Addr;
-
-/* Exported functions */
-extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
-extern void openpic2_init(int linux_irq_offset);
-extern void openpic2_init_nmi_irq(u_int irq);
-extern u_int openpic2_irq(void);
-extern void openpic2_eoi(void);
-extern int openpic2_get_irq(void);
-extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
-#endif /* _PPC_KERNEL_OPEN_PIC_H */
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
deleted file mode 100644
index 37e4756b6b2d..000000000000
--- a/include/asm-ppc/page.h
+++ /dev/null
@@ -1,140 +0,0 @@
-#ifndef _PPC_PAGE_H
-#define _PPC_PAGE_H
-
-#include <asm/asm-compat.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT      12
-#define PAGE_SIZE       (ASM_CONST(1) << PAGE_SHIFT)
-
-/*
- * Subtle: this is an int (not an unsigned long) and so it
- * gets extended to 64 bits the way want (i.e. with 1s).  -- paulus
- */
-#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
-
-#ifdef __KERNEL__
-
-/* This must match what is in arch/ppc/Makefile */
-#define PAGE_OFFSET     CONFIG_KERNEL_START
-#define KERNELBASE      PAGE_OFFSET
-#define is_kernel_addr(x)       ((x) >= PAGE_OFFSET)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
- * physical addressing.  For now this just the IBM PPC440.
- */
-#ifdef CONFIG_PTE_64BIT
-typedef unsigned long long pte_basic_t;
-#define PTE_SHIFT       (PAGE_SHIFT - 3)        /* 512 ptes per page */
-#define PTE_FMT         "%16Lx"
-#else
-typedef unsigned long pte_basic_t;
-#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
-#define PTE_FMT         "%.8lx"
-#endif
-
-/* align addr on a size boundary - adjust address up/down if needed */
-#define _ALIGN_UP(addr,size)    (((addr)+((size)-1))&(~((size)-1)))
-#define _ALIGN_DOWN(addr,size)  ((addr)&(~((size)-1)))
-
-/* align addr on a size boundary - adjust address up if needed */
-#define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
-
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr)        _ALIGN(addr, PAGE_SIZE)
-
-
-#undef STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { pte_basic_t pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-
-#define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((x).pmd)
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-#else
-/*
- * .. while these make it easier on the compiler
- */
-typedef pte_basic_t pte_t;
-typedef unsigned long pmd_t;
-typedef unsigned long pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x)      (x)
-#define pmd_val(x)      (x)
-#define pgd_val(x)      (x)
-#define pgprot_val(x)   (x)
-
-#define __pte(x)        (x)
-#define __pmd(x)        (x)
-#define __pgd(x)        (x)
-#define __pgprot(x)     (x)
-
-#endif
-
-struct page;
-extern void clear_pages(void *page, int order);
-static inline void clear_page(void *page) { clear_pages(page, 0); }
-extern void copy_page(void *to, void *from);
-extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
-extern void copy_user_page(void *to, void *from, unsigned long vaddr,
-                           struct page *pg);
-
-#define PPC_MEMSTART    0
-#define PPC_MEMOFFSET   PAGE_OFFSET
-
-#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET)
-#define ___va(paddr) ((paddr)+PPC_MEMOFFSET)
-
-extern int page_is_ram(unsigned long pfn);
-
-#define __pa(x) ___pa((unsigned long)(x))
-#define __va(x) ((void *)(___va((unsigned long)(x))))
-
-#define ARCH_PFN_OFFSET         0
-#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define page_to_virt(page)      __va(page_to_pfn(page) << PAGE_SHIFT)
-
-#define pfn_valid(pfn)          ((pfn) < max_mapnr)
-#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int lz;
-
-        size = (size-1) >> PAGE_SHIFT;
-        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
-        return 32 - lz;
-}
-
-typedef struct page *pgtable_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
-                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
-#define __HAVE_ARCH_GATE_AREA           1
-
-#include <asm-generic/memory_model.h>
-#endif /* __KERNEL__ */
-#endif /* _PPC_PAGE_H */
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h
deleted file mode 100644
index 81a2d0fdaf00..000000000000
--- a/include/asm-ppc/pc_serial.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-ppc/pc_serial.h
- *
- * This is basically a copy of include/asm-i386/serial.h.
- * It is used on platforms which have an ISA bus and thus are likely
- * to have PC-style serial ports at the legacy I/O port addresses.
- * It also includes the definitions for the fourport, accent, boca
- * and hub6 multiport serial cards, although I have never heard of
- * anyone using any of those on a PPC platform.  -- paulus
- */
-
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD ( 1843200 / 16 )
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define RS_TABLE_SIZE  64
-#else
-#define RS_TABLE_SIZE  4
-#endif
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-
-#define SERIAL_PORT_DFNS                        \
-        /* UART CLK   PORT IRQ     FLAGS        */                      \
-        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
-        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
-        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
-        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
deleted file mode 100644
index 4d35b844bc58..000000000000
--- a/include/asm-ppc/pci-bridge.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_PCI_BRIDGE_H
-#define _ASM_PCI_BRIDGE_H
-
-#include <linux/ioport.h>
-#include <linux/pci.h>
-
-struct device_node;
-struct pci_controller;
-
-/*
- * pci_io_base returns the memory address at which you can access
- * the I/O space for PCI bus number `bus' (or NULL on error).
- */
-extern void __iomem *pci_bus_io_base(unsigned int bus);
-extern unsigned long pci_bus_io_base_phys(unsigned int bus);
-extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
-
-/* Allocate a new PCI host bridge structure */
-extern struct pci_controller* pcibios_alloc_controller(void);
-
-/* Helper function for setting up resources */
-extern void pci_init_resource(struct resource *res, resource_size_t start,
-                              resource_size_t end, int flags, char *name);
-
-/* Get the PCI host controller for a bus */
-extern struct pci_controller* pci_bus_to_hose(int bus);
-
-/* Get the PCI host controller for an OF device */
-extern struct pci_controller*
-pci_find_hose_for_OF_device(struct device_node* node);
-
-/* Fill up host controller resources from the OF node */
-extern void
-pci_process_bridge_OF_ranges(struct pci_controller *hose,
-                           struct device_node *dev, int primary);
-
-/*
- * Structure of a PCI controller (host bridge)
- */
-struct pci_controller {
-        int index;                      /* PCI domain number */
-        struct pci_controller *next;
-        struct pci_bus *bus;
-        void *arch_data;
-        struct device *parent;
-
-        int first_busno;
-        int last_busno;
-        int bus_offset;
-
-        void __iomem *io_base_virt;
-        resource_size_t io_base_phys;
-
-        /* Some machines (PReP) have a non 1:1 mapping of
-         * the PCI memory space in the CPU bus space
-         */
-        resource_size_t pci_mem_offset;
-
-        struct pci_ops *ops;
-        volatile unsigned int __iomem *cfg_addr;
-        volatile void __iomem *cfg_data;
-        /*
-         * If set, indirect method will set the cfg_type bit as
-         * needed to generate type 1 configuration transactions.
-         */
-        int set_cfg_type;
-
-        /* Currently, we limit ourselves to 1 IO range and 3 mem
-         * ranges since the common pci_bus structure can't handle more
-         */
-        struct resource io_resource;
-        struct resource mem_resources[3];
-        int mem_resource_count;
-
-        /* Host bridge I/O and Memory space
-         * Used for BAR placement algorithms
-         */
-        struct resource io_space;
-        struct resource mem_space;
-};
-
-static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
-{
-        return bus->sysdata;
-}
-
-/* These are used for config access before all the PCI probing
-   has been done. */
-int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
-                           int where, u8 *val);
-int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
-                           int where, u16 *val);
-int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
-                            int where, u32 *val);
-int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
-                            int where, u8 val);
-int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
-                            int where, u16 val);
-int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
-                             int where, u32 val);
-
-extern void setup_indirect_pci_nomap(struct pci_controller* hose,
-                               void __iomem *cfg_addr, void __iomem *cfg_data);
-extern void setup_indirect_pci(struct pci_controller* hose,
-                               u32 cfg_addr, u32 cfg_data);
-extern void setup_grackle(struct pci_controller *hose);
-
-extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
-
-/*
- *   The following code swizzles for exactly one bridge.  The routine
- *   common_swizzle below handles multiple bridges.  But there are a
- *   some boards that don't follow the PCI spec's suggestion so we
- *   break this piece out separately.
- */
-static inline unsigned char bridge_swizzle(unsigned char pin,
-                unsigned char idsel)
-{
-        return (((pin-1) + idsel) % 4) + 1;
-}
-
-/*
- * The following macro is used to lookup irqs in a standard table
- * format for those PPC systems that do not already have PCI
- * interrupts properly routed.
- */
-/* FIXME - double check this */
-#define PCI_IRQ_TABLE_LOOKUP                                                \
-({ long _ctl_ = -1;                                                         \
-   if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
-     _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];                       \
-   _ctl_; })
-
-/*
- * Scan the buses below a given PCI host bridge and assign suitable
- * resources to all devices found.
- */
-extern int pciauto_bus_scan(struct pci_controller *, int);
-
-#ifdef CONFIG_PCI
-extern unsigned long pci_address_to_pio(phys_addr_t address);
-#else
-static inline unsigned long pci_address_to_pio(phys_addr_t address)
-{
-        return (unsigned long)-1;
-}
-#endif
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
deleted file mode 100644
index d2442cd72a59..000000000000
--- a/include/asm-ppc/pci.h
+++ /dev/null
@@ -1,156 +0,0 @@
-#ifndef __PPC_PCI_H
-#define __PPC_PCI_H
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <asm/scatterlist.h>
-#include <asm/io.h>
-#include <asm/pci-bridge.h>
-#include <asm-generic/pci-dma-compat.h>
-
-struct pci_dev;
-
-/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
-#define IOBASE_BRIDGE_NUMBER    0
-#define IOBASE_MEMORY           1
-#define IOBASE_IO               2
-#define IOBASE_ISA_IO           3
-#define IOBASE_ISA_MEM          4
-
-/*
- * Set this to 1 if you want the kernel to re-assign all PCI
- * bus numbers
- */
-extern int pci_assign_all_buses;
-
-#define pcibios_assign_all_busses()     (pci_assign_all_buses)
-#define pcibios_scan_all_fns(a, b)      0
-
-#define PCIBIOS_MIN_IO          0x1000
-#define PCIBIOS_MIN_MEM         0x10000000
-
-extern inline void pcibios_set_master(struct pci_dev *dev)
-{
-        /* No special bus mastering setup handling */
-}
-
-extern inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-        /* We don't do dynamic PCI IRQ allocation */
-}
-
-extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res);
-
-/*
- * The PCI bus bridge can translate addresses issued by the processor(s)
- * into a different address on the PCI bus.  On 32-bit cpus, we assume
- * this mapping is 1-1, but on 64-bit systems it often isn't.
- *
- * Obsolete ! Drivers should now use pci_resource_to_bus
- */
-extern unsigned long phys_to_bus(unsigned long pa);
-extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr);
-extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
-
-/* The PCI address space does equal the physical memory
- * address space.  The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS     (1)
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/*
- * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu()
- * and so on are not, so...
- */
-
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
-        dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
-        __u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME)                  \
-        ((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
-        (((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME)                    \
-        ((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
-        (((PTR)->LEN_NAME) = (VAL))
-
-#else /* coherent */
-
-/* pci_unmap_{page,single} is a nop so... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
-#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
-#define pci_unmap_len(PTR, LEN_NAME)            (0)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
-
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-                                        enum pci_dma_burst_strategy *strat,
-                                        unsigned long *strategy_parameter)
-{
-        *strat = PCI_DMA_BURST_INFINITY;
-        *strategy_parameter = ~0UL;
-}
-#endif
-
-/* Return the index of the PCI controller for device PDEV. */
-#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
-
-/* Set the name of the bus as it appears in /proc/bus/pci */
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
-        return 0;
-}
-
-/* Map a range of PCI memory or I/O space for a device into user space */
-int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
-                        enum pci_mmap_state mmap_state, int write_combine);
-
-/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
-#define HAVE_PCI_MMAP   1
-
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-        struct resource *root = NULL;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &ioport_resource;
-        if (res->flags & IORESOURCE_MEM)
-                root = &iomem_resource;
-
-        return root;
-}
-
-struct file;
-extern pgprot_t pci_phys_mem_access_prot(struct file *file,
-                                         unsigned long pfn,
-                                         unsigned long size,
-                                         pgprot_t prot);
-
-#define HAVE_ARCH_PCI_RESOURCE_TO_USER
-extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
-                                 const struct resource *rsrc,
-                                 resource_size_t *start, resource_size_t *end);
-
-
-#endif  /* __KERNEL__ */
-
-#endif /* __PPC_PCI_H */
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h
deleted file mode 100644
index fd4d1d74cfb1..000000000000
--- a/include/asm-ppc/pgalloc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_PGALLOC_H
-#define _PPC_PGALLOC_H
-
-#include <linux/threads.h>
-
-extern void __bad_pte(pmd_t *pmd);
-
-extern pgd_t *pgd_alloc(struct mm_struct *mm);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-
-/*
- * We don't have any real pmd's, and this code never triggers because
- * the pgd will always be present..
- */
-#define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); })
-#define pmd_free(mm, x)                 do { } while (0)
-#define __pmd_free_tlb(tlb,x)           do { } while (0)
-#define pgd_populate(mm, pmd, pte)      BUG()
-
-#ifndef CONFIG_BOOKE
-#define pmd_populate_kernel(mm, pmd, pte)       \
-                (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
-#define pmd_populate(mm, pmd, pte)      \
-                (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#else
-#define pmd_populate_kernel(mm, pmd, pte)       \
-                (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
-#define pmd_populate(mm, pmd, pte)      \
-                (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#endif
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
-extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
-extern void pte_free(struct mm_struct *mm, pgtable_t pte);
-
-#define __pte_free_tlb(tlb, pte)        pte_free((tlb)->mm, (pte))
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif /* _PPC_PGALLOC_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
deleted file mode 100644
index 55f9d38e3bf8..000000000000
--- a/include/asm-ppc/pgtable.h
+++ /dev/null
@@ -1,771 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_PGTABLE_H
-#define _PPC_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <linux/threads.h>
-#include <asm/processor.h>              /* For TASK_SIZE */
-#include <asm/mmu.h>
-#include <asm/page.h>
-#include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
-struct mm_struct;
-
-extern unsigned long va_to_phys(unsigned long address);
-extern pte_t *va_to_pte(unsigned long address);
-extern unsigned long ioremap_bot, ioremap_base;
-#endif /* __ASSEMBLY__ */
-
-/*
- * The PowerPC MMU uses a hash table containing PTEs, together with
- * a set of 16 segment registers (on 32-bit implementations), to define
- * the virtual to physical address mapping.
- *
- * We use the hash table as an extended TLB, i.e. a cache of currently
- * active mappings.  We maintain a two-level page table tree, much
- * like that used by the i386, for the sake of the Linux memory
- * management code.  Low-level assembler code in hashtable.S
- * (procedure hash_page) is responsible for extracting ptes from the
- * tree and putting them into the hash table when necessary, and
- * updating the accessed and modified bits in the page table tree.
- */
-
-/*
- * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
- * We also use the two level tables, but we can put the real bits in them
- * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
- * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
- * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
- * based upon user/super access.  The TLB does not have accessed nor write
- * protect.  We assume that if the TLB get loaded with an entry it is
- * accessed, and overload the changed bit for write protect.  We use
- * two bits in the software pte that are supposed to be set to zero in
- * the TLB entry (24 and 25) for these indicators.  Although the level 1
- * descriptor contains the guarded and writethrough/copyback bits, we can
- * set these at the page level since they get copied from the Mx_TWC
- * register when the TLB entry is loaded.  We will use bit 27 for guard, since
- * that is where it exists in the MD_TWC, and bit 26 for writethrough.
- * These will get masked from the level 2 descriptor at TLB load time, and
- * copied to the MD_TWC before it gets loaded.
- * Large page sizes added.  We currently support two sizes, 4K and 8M.
- * This also allows a TLB hander optimization because we can directly
- * load the PMD into MD_TWC.  The 8M pages are only used for kernel
- * mapping of well known areas.  The PMD (PGD) entries contain control
- * flags in addition to the address, so care must be taken that the
- * software no longer assumes these are only pointers.
- */
-
-/*
- * At present, all PowerPC 400-class processors share a similar TLB
- * architecture. The instruction and data sides share a unified,
- * 64-entry, fully-associative TLB which is maintained totally under
- * software control. In addition, the instruction side has a
- * hardware-managed, 4-entry, fully-associative TLB which serves as a
- * first level to the shared TLB. These two TLBs are known as the UTLB
- * and ITLB, respectively (see "mmu.h" for definitions).
- */
-
-/*
- * The normal case is that PTEs are 32-bits and we have a 1-page
- * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
- *
- * For any >32-bit physical address platform, we can use the following
- * two level page table layout where the pgdir is 8KB and the MS 13 bits
- * are an index to the second level table.  The combined pgdir/pmd first
- * level has 2048 entries and the second level has 512 64-bit PTE entries.
- * -Matt
- */
-/* PMD_SHIFT determines the size of the area mapped by the PTE pages */
-#define PMD_SHIFT       (PAGE_SHIFT + PTE_SHIFT)
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a top-level page table entry can map */
-#define PGDIR_SHIFT     PMD_SHIFT
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK      (~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: our page-table tree is two-level, so
- * we don't really have any PMD directory.
- */
-#define PTRS_PER_PTE    (1 << PTE_SHIFT)
-#define PTRS_PER_PMD    1
-#define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
-
-#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS      0
-
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 64MB value just means that there will be a 64MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- *
- * We no longer map larger than phys RAM with the BATs so we don't have
- * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
- * about clashes between our early calls to ioremap() that start growing down
- * from ioremap_base being run into the VM area allocations (growing upwards
- * from VMALLOC_START).  For this reason we have ioremap_bot to check when
- * we actually run into our mappings setup in the early boot with the VM
- * system.  This really does become a problem for machines with good amounts
- * of RAM.  -- Cort
- */
-#define VMALLOC_OFFSET (0x1000000) /* 16M */
-#ifdef PPC_PIN_SIZE
-#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
-#else
-#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
-#endif
-#define VMALLOC_END     ioremap_bot
-
-/*
- * Bits in a linux-style PTE.  These match the bits in the
- * (hardware-defined) PowerPC PTE as closely as possible.
- */
-
-#if defined(CONFIG_40x)
-
-/* There are several potential gotchas here.  The 40x hardware TLBLO
-   field looks like this:
-
-   0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-   RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
-
-   Where possible we make the Linux PTE bits match up with this
-
-   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
-     support down to 1k pages), this is done in the TLBMiss exception
-     handler.
-   - We use only zones 0 (for kernel pages) and 1 (for user pages)
-     of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
-     miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
-     zone.
-   - PRESENT *must* be in the bottom two bits because swap cache
-     entries use the top 30 bits.  Because 40x doesn't support SMP
-     anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
-     is cleared in the TLB miss handler before the TLB entry is loaded.
-   - All other bits of the PTE are loaded into TLBLO without
-     modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
-     software PTE bits.  We actually use use bits 21, 24, 25, and
-     30 respectively for the software bits: ACCESSED, DIRTY, RW, and
-     PRESENT.
-*/
-
-/* Definitions for 40x embedded chips. */
-#define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
-#define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
-#define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
-#define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
-#define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
-#define _PAGE_USER      0x010   /* matches one of the zone permission bits */
-#define _PAGE_RW        0x040   /* software: Writes permitted */
-#define _PAGE_DIRTY     0x080   /* software: dirty page */
-#define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
-#define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
-#define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
-
-#define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
-#define _PMD_BAD        0x802
-#define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
-#define _PMD_SIZE_4M    0x0c0
-#define _PMD_SIZE_16M   0x0e0
-#define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
-
-#elif defined(CONFIG_44x)
-/*
- * Definitions for PPC440
- *
- * Because of the 3 word TLB entries to support 36-bit addressing,
- * the attribute are difficult to map in such a fashion that they
- * are easily loaded during exception processing.  I decided to
- * organize the entry so the ERPN is the only portion in the
- * upper word of the PTE and the attribute bits below are packed
- * in as sensibly as they can be in the area below a 4KB page size
- * oriented RPN.  This at least makes it easy to load the RPN and
- * ERPN fields in the TLB. -Matt
- *
- * Note that these bits preclude future use of a page size
- * less than 4KB.
- *
- *
- * PPC 440 core has following TLB attribute fields;
- *
- *   TLB1:
- *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- *   RPN.................................  -  -  -  -  -  - ERPN.......
- *
- *   TLB2:
- *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
- *
- * There are some constrains and options, to decide mapping software bits
- * into TLB entry.
- *
- *   - PRESENT *must* be in the bottom three bits because swap cache
- *     entries use the top 29 bits for TLB2.
- *
- *   - FILE *must* be in the bottom three bits because swap cache
- *     entries use the top 29 bits for TLB2.
- *
- *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
- *     doesn't support SMP. So we can use this as software bit, like
- *     DIRTY.
- *
- * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
- * for memory protection related functions (see PTE structure in
- * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
- * above bits.  Note that the bit values are CPU specific, not architecture
- * specific.
- *
- * The kernel PTE entry holds an arch-dependent swp_entry structure under
- * certain situations. In other words, in such situations some portion of
- * the PTE bits are used as a swp_entry. In the PPC implementation, the
- * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
- * hold protection values. That means the three protection bits are
- * reserved for both PTE and SWAP entry at the most significant three
- * LSBs.
- *
- * There are three protection bits available for SWAP entry:
- *      _PAGE_PRESENT
- *      _PAGE_FILE
- *      _PAGE_HASHPTE (if HW has)
- *
- * So those three bits have to be inside of 0-2nd LSB of PTE.
- *
- */
-
-#define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
-#define _PAGE_RW        0x00000002              /* S: Write permission */
-#define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
-#define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
-#define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
-#define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
-#define _PAGE_USER      0x00000040              /* S: User page */
-#define _PAGE_ENDIAN    0x00000080              /* H: E bit */
-#define _PAGE_GUARDED   0x00000100              /* H: G bit */
-#define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
-#define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
-#define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
-
-/* TODO: Add large page lowmem mapping support */
-#define _PMD_PRESENT    0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD        (~PAGE_MASK)
-
-/* ERPN in a PTE never gets cleared, ignore it */
-#define _PTE_NONE_MASK  0xffffffff00000000ULL
-
-#elif defined(CONFIG_8xx)
-/* Definitions for 8xx embedded chips. */
-#define _PAGE_PRESENT   0x0001  /* Page is valid */
-#define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
-#define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
-#define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
-
-/* These five software bits must be masked out when the entry is loaded
- * into the TLB.
- */
-#define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
-#define _PAGE_GUARDED   0x0010  /* software: guarded access */
-#define _PAGE_DIRTY     0x0020  /* software: page changed */
-#define _PAGE_RW        0x0040  /* software: user write access allowed */
-#define _PAGE_ACCESSED  0x0080  /* software: page referenced */
-
-/* Setting any bits in the nibble with the follow two controls will
- * require a TLB exception handler change.  It is assumed unused bits
- * are always zero.
- */
-#define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
-#define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
-
-#define _PMD_PRESENT    0x0001
-#define _PMD_BAD        0x0ff0
-#define _PMD_PAGE_MASK  0x000c
-#define _PMD_PAGE_8M    0x000c
-
-#define _PTE_NONE_MASK _PAGE_ACCESSED
-
-#else /* CONFIG_6xx */
-/* Definitions for 60x, 740/750, etc. */
-#define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
-#define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
-#define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
-#define _PAGE_USER      0x004   /* usermode access allowed */
-#define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
-#define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
-#define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
-#define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
-#define _PAGE_DIRTY     0x080   /* C: page changed */
-#define _PAGE_ACCESSED  0x100   /* R: page referenced */
-#define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
-#define _PAGE_RW        0x400   /* software: user write access allowed */
-
-#define _PTE_NONE_MASK  _PAGE_HASHPTE
-
-#define _PMD_PRESENT    0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD        (~PAGE_MASK)
-#endif
-
-/*
- * Some bits are only used on some cpu families...
- */
-#ifndef _PAGE_HASHPTE
-#define _PAGE_HASHPTE   0
-#endif
-#ifndef _PTE_NONE_MASK
-#define _PTE_NONE_MASK 0
-#endif
-#ifndef _PAGE_SHARED
-#define _PAGE_SHARED    0
-#endif
-#ifndef _PAGE_HWWRITE
-#define _PAGE_HWWRITE   0
-#endif
-#ifndef _PAGE_HWEXEC
-#define _PAGE_HWEXEC    0
-#endif
-#ifndef _PAGE_EXEC
-#define _PAGE_EXEC      0
-#endif
-#ifndef _PMD_PRESENT_MASK
-#define _PMD_PRESENT_MASK       _PMD_PRESENT
-#endif
-#ifndef _PMD_SIZE
-#define _PMD_SIZE       0
-#define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
-#endif
-
-#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-/*
- * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
- * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
- * to have it in the Linux PTE, and in fact the bit could be reused for
- * another purpose.  -- paulus.
- */
-
-#ifdef CONFIG_44x
-#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
-#else
-#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
-#endif
-#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
-#define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
-
-#ifdef CONFIG_PPC_STD_MMU
-/* On standard PPC MMU, no user access implies kernel read/write access,
- * so to write-protect kernel memory we must turn on user access */
-#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
-#else
-#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
-#endif
-
-#define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
-
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
-/* We want the debuggers to be able to set breakpoints anywhere, so
- * don't write protect the kernel text */
-#define _PAGE_RAM_TEXT  _PAGE_RAM
-#else
-#define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
-#endif
-
-#define PAGE_NONE       __pgprot(_PAGE_BASE)
-#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
-#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
-#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-
-#define PAGE_KERNEL             __pgprot(_PAGE_RAM)
-#define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
-
-/*
- * The PowerPC can only do execute protection on a segment (256MB) basis,
- * not on a page basis.  So we consider execute permission the same as read.
- * Also, write permissions imply read permissions.
- * This is the closest we can get..
- */
-#define __P000  PAGE_NONE
-#define __P001  PAGE_READONLY_X
-#define __P010  PAGE_COPY
-#define __P011  PAGE_COPY_X
-#define __P100  PAGE_READONLY
-#define __P101  PAGE_READONLY_X
-#define __P110  PAGE_COPY
-#define __P111  PAGE_COPY_X
-
-#define __S000  PAGE_NONE
-#define __S001  PAGE_READONLY_X
-#define __S010  PAGE_SHARED
-#define __S011  PAGE_SHARED_X
-#define __S100  PAGE_READONLY
-#define __S101  PAGE_READONLY_X
-#define __S110  PAGE_SHARED
-#define __S111  PAGE_SHARED_X
-
-#ifndef __ASSEMBLY__
-/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
- * kernel without large page PMD support */
-extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
-
-/*
- * Conversions between PTE values and page frame numbers.
- */
-
-/* in some case we want to additionaly adjust where the pfn is in the pte to
- * allow room for more flags */
-#define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
-
-#define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
-#define pte_page(x)             pfn_to_page(pte_pfn(x))
-
-#define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
-                                        pgprot_val(prot))
-#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[1024];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-#endif /* __ASSEMBLY__ */
-
-#define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
-#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
-
-#define pmd_none(pmd)           (!pmd_val(pmd))
-#define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
-#define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
-#define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
-
-#ifndef __ASSEMBLY__
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)           { return 0; }
-static inline int pgd_bad(pgd_t pgd)            { return 0; }
-static inline int pgd_present(pgd_t pgd)        { return 1; }
-#define pgd_clear(xp)                           do { } while (0)
-
-#define pgd_page_vaddr(pgd) \
-        ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
-static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_special(pte_t pte)        { return 0; }
-
-static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
-static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
-
-static inline pte_t pte_wrprotect(pte_t pte) {
-        pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
-static inline pte_t pte_mkclean(pte_t pte) {
-        pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
-static inline pte_t pte_mkold(pte_t pte) {
-        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-
-static inline pte_t pte_mkwrite(pte_t pte) {
-        pte_val(pte) |= _PAGE_RW; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) {
-        pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) {
-        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte) {
-        return pte; }
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-        pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
-        return pte;
-}
-
-/*
- * When flushing the tlb entry for a page, we also need to flush the hash
- * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
- */
-extern int flush_hash_pages(unsigned context, unsigned long va,
-                            unsigned long pmdval, int count);
-
-/* Add an HPTE to the hash table */
-extern void add_hash_page(unsigned context, unsigned long va,
-                          unsigned long pmdval);
-
-/*
- * Atomic PTE updates.
- *
- * pte_update clears and sets bit atomically, and returns
- * the old pte value.  In the 64-bit PTE case we lock around the
- * low PTE word since we expect ALL flag bits to be there
- */
-#ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p, unsigned long clr,
-                                       unsigned long set)
-{
-        unsigned long old, tmp;
-
-        __asm__ __volatile__("\
-1:      lwarx   %0,0,%3\n\
-        andc    %1,%0,%4\n\
-        or      %1,%1,%5\n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %1,0,%3\n\
-        bne-    1b"
-        : "=&r" (old), "=&r" (tmp), "=m" (*p)
-        : "r" (p), "r" (clr), "r" (set), "m" (*p)
-        : "cc" );
-        return old;
-}
-#else
-static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
-                                       unsigned long set)
-{
-        unsigned long long old;
-        unsigned long tmp;
-
-        __asm__ __volatile__("\
-1:      lwarx   %L0,0,%4\n\
-        lwzx    %0,0,%3\n\
-        andc    %1,%L0,%5\n\
-        or      %1,%1,%6\n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %1,0,%4\n\
-        bne-    1b"
-        : "=&r" (old), "=&r" (tmp), "=m" (*p)
-        : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
-        : "cc" );
-        return old;
-}
-#endif
-
-/*
- * set_pte stores a linux PTE into the linux page table.
- * On machines which use an MMU hash table we avoid changing the
- * _PAGE_HASHPTE bit.
- */
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
-                              pte_t *ptep, pte_t pte)
-{
-#if _PAGE_HASHPTE != 0
-        pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
-#else
-        *ptep = pte;
-#endif
-}
-
-/*
- * 2.6 calles this without flushing the TLB entry, this is wrong
- * for our hash-based implementation, we fix that up here
- */
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
-{
-        unsigned long old;
-        old = pte_update(ptep, _PAGE_ACCESSED, 0);
-#if _PAGE_HASHPTE != 0
-        if (old & _PAGE_HASHPTE) {
-                unsigned long ptephys = __pa(ptep) & PAGE_MASK;
-                flush_hash_pages(context, addr, ptephys, 1);
-        }
-#endif
-        return (old & _PAGE_ACCESSED) != 0;
-}
-#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
-        __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
-                                       pte_t *ptep)
-{
-        return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
-}
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
-                                      pte_t *ptep)
-{
-        pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
-}
-
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
-{
-        unsigned long bits = pte_val(entry) &
-                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
-        pte_update(ptep, 0, bits);
-}
-
-#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-({                                                                         \
-        int __changed = !pte_same(*(__ptep), __entry);                     \
-        if (__changed) {                                                   \
-                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
-                flush_tlb_page_nohash(__vma, __address);                   \
-        }                                                                  \
-        __changed;                                                         \
-})
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- */
-#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
-
-struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-                                     unsigned long size, pgprot_t vma_prot);
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-
-#define __HAVE_ARCH_PTE_SAME
-#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
-
-/*
- * Note that on Book E processors, the pmd contains the kernel virtual
- * (lowmem) address of the pte page.  The physical address is less useful
- * because everything runs with translation enabled (even the TLB miss
- * handler).  On everything else the pmd contains the physical address
- * of the pte page.  -- paulus
- */
-#ifndef CONFIG_BOOKE
-#define pmd_page_vaddr(pmd)     \
-        ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd)           \
-        (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
-#else
-#define pmd_page_vaddr(pmd)     \
-        ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd)           \
-        (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
-#endif
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* to find an entry in a page-table-directory */
-#define pgd_index(address)       ((address) >> PGDIR_SHIFT)
-#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
-
-/* Find an entry in the second-level page table.. */
-static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
-
-/* Find an entry in the third-level page table.. */
-#define pte_index(address)              \
-        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, addr)    \
-        ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
-#define pte_offset_map(dir, addr)               \
-        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
-#define pte_offset_map_nested(dir, addr)        \
-        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
-
-#define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
-#define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
-extern void paging_init(void);
-
-/*
- * Encode and decode a swap entry.
- * Note that the bits we use in a PTE for representing a swap entry
- * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
- *_PAGE_HASHPTE bit (if used).  -- paulus
- */
-#define __swp_type(entry)               ((entry).val & 0x1f)
-#define __swp_offset(entry)             ((entry).val >> 5)
-#define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
-#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
-#define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
-
-/* Encode and decode a nonlinear file mapping entry */
-#define PTE_FILE_MAX_BITS       29
-#define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
-#define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
-
-/* Values for nocacheflag and cmode */
-/* These are not used by the APUS kernel_map, but prevents
-   compilation errors. */
-#define KERNELMAP_FULL_CACHING          0
-#define KERNELMAP_NOCACHE_SER           1
-#define KERNELMAP_NOCACHE_NONSER        2
-#define KERNELMAP_NO_COPYBACK           3
-
-/*
- * Map some physical address range into the kernel address space.
- */
-extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
-                                int nocacheflag, unsigned long *memavailp );
-
-/*
- * Set cache mode of (kernel space) address range.
- */
-extern void kernel_set_cachemode (unsigned long address, unsigned long size,
-                                 unsigned int cmode);
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define kern_addr_valid(addr)   (1)
-
-#ifdef CONFIG_PHYS_64BIT
-extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
-                        unsigned long paddr, unsigned long size, pgprot_t prot);
-
-static inline int io_remap_pfn_range(struct vm_area_struct *vma,
-                                        unsigned long vaddr,
-                                        unsigned long pfn,
-                                        unsigned long size,
-                                        pgprot_t prot)
-{
-        phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-        return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
-}
-#else
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-#endif
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()    do { } while (0)
-
-extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
-                      pmd_t **pmdp);
-
-#include <asm-generic/pgtable.h>
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _PPC_PGTABLE_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h
deleted file mode 100644
index 6f6760b30dd8..000000000000
--- a/include/asm-ppc/pnp.h
+++ /dev/null
@@ -1,645 +0,0 @@
-#ifdef __KERNEL__
-/* 11/02/95                                                                   */
-/*----------------------------------------------------------------------------*/
-/*      Plug and Play header definitions                                      */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for PnP on PowerPC Reference Platform                        */
-/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
-/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
-/* This code has extensions to that specification, namely new short and       */
-/* long tag types for platform dependent information                          */
-
-/* Warning: LE notation used throughout this file                             */
-
-/* For enum's: if given in hex then they are bit significant, i.e.            */
-/* only one bit is on for each enum                                           */
-
-#ifndef _PNP_
-#define _PNP_
-
-#ifndef __ASSEMBLY__
-#define MAX_MEM_REGISTERS 9
-#define MAX_IO_PORTS 20
-#define MAX_IRQS 7
-/*#define MAX_DMA_CHANNELS 7*/
-
-/* Interrupt controllers */
-
-#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
-#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
-#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
-#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
-#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
-
-/* Timers */
-
-#define PNPtimer0     "PNP0100"      /* AT Timer                              */
-#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
-#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
-
-/* DMA controllers */
-
-#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
-#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
-#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
-
-/* start of August 15, 1994 additions */
-/* CMOS */
-#define PNPCMOS       "IBM0009"      /* CMOS                                  */
-
-/* L2 Cache */
-#define PNPL2         "IBM0007"      /* L2 Cache                              */
-
-/* NVRAM */
-#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
-
-/* Power Management */
-#define PNPPM         "IBM0005"      /* Power Management                      */
-/* end of August 15, 1994 additions */
-
-/* Keyboards */
-
-#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
-#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
-#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
-#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
-#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
-#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
-#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
-#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
-
-/* Parallel port controllers */
-
-#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
-#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
-#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
-
-/* Serial port controllers */
-
-#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
-#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
-
-/* Disk controllers */
-
-#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
-#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
-#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
-
-/* Diskette controllers */
-
-#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
-
-/* Display controllers */
-
-#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
-#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
-#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
-#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
-#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
-#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
-#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
-#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
-#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
-#define PNPdisplay9  "PNP0909"       /* S3                                    */
-#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
-#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
-#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
-#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
-#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
-#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
-
-/* Peripheral busses */
-
-#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
-#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
-#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
-#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
-#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
-
-/* RTC, BIOS, planar devices */
-
-#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
-#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
-#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
-#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
-#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
-#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
-
-/* PCMCIA controller */
-
-#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
-
-/* Mice */
-
-#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
-#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
-#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
-#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
-#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
-#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
-#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
-#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
-#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
-#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
-#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
-#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
-
-/* Modems */
-
-#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
-
-/* Network controllers */
-
-#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
-#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
-#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
-#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
-#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
-#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
-#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
-#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
-
-/* SCSI controllers */
-
-#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
-#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
-#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
-#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
-#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
-#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
-#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
-
-/* Sound/Video, Multimedia */
-
-#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
-#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
-#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
-#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
-#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
-#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
-#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
-#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
-
-/* Operator Panel */
-#define PNPopctl     "IBM000B"       /* Operator's panel                      */
-
-/* Service Processor */
-#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
-#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
-#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
-
-/* Memory Controller */
-#define PNPmemctl    "IBM000A"       /* Memory controller                     */
-
-/* Graphics Assist */
-#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
-
-/* Miscellaneous Device Controllers */
-#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
-
-/* PNP Packet Handles */
-
-#define S1_Packet                0x0A   /* Version resource                   */
-#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
-#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
-#define S3_Packet                0x1C   /* Compatible device ID               */
-#define S4_Packet                0x22   /* IRQ resource (without flags)       */
-#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
-#define S5_Packet                0x2A   /* DMA resource                       */
-#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
-#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
-#define S7_Packet                0x38   /* Depend funct end                   */
-#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
-#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
-#define S14_Packet               0x71   /* Vendor defined                     */
-#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
-#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
-#define L1_Packet                0x81   /* Memory range                       */
-#define L1_Shadow                0x20   /* Memory is shadowable               */
-#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
-#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
-#define L1_Decode_Hi             0x04   /* decode supports high address       */
-#define L1_Cache                 0x02   /* read cacheable, write-through      */
-#define L1_Writeable             0x01   /* Memory is writeable                */
-#define L2_Packet                0x82   /* ANSI ID string                     */
-#define L3_Packet                0x83   /* Unicode ID string                  */
-#define L4_Packet                0x84   /* Vendor defined                     */
-#define L5_Packet                0x85   /* Large I/O                          */
-#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
-#define END_TAG                  0x78   /* End of resource                    */
-#define DF_START_TAG             0x30   /* Dependent function start           */
-#define DF_START_TAG_priority    0x31   /* Dependent function start           */
-#define DF_END_TAG               0x38   /* Dependent function end             */
-#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
-
-/* Device Base Type Codes */
-
-typedef enum _PnP_BASE_TYPE {
-  Reserved = 0,
-  MassStorageDevice = 1,
-  NetworkInterfaceController = 2,
-  DisplayController = 3,
-  MultimediaController = 4,
-  MemoryController = 5,
-  BridgeController = 6,
-  CommunicationsDevice = 7,
-  SystemPeripheral = 8,
-  InputDevice = 9,
-  ServiceProcessor = 0x0A,              /* 11/2/95                            */
-  } PnP_BASE_TYPE;
-
-/* Device Sub Type Codes */
-
-typedef enum _PnP_SUB_TYPE {
-  SCSIController = 0,
-  IDEController = 1,
-  FloppyController = 2,
-  IPIController = 3,
-  OtherMassStorageController = 0x80,
-
-  EthernetController = 0,
-  TokenRingController = 1,
-  FDDIController = 2,
-  OtherNetworkController = 0x80,
-
-  VGAController= 0,
-  SVGAController= 1,
-  XGAController= 2,
-  OtherDisplayController = 0x80,
-
-  VideoController = 0,
-  AudioController = 1,
-  OtherMultimediaController = 0x80,
-
-  RAM = 0,
-  FLASH = 1,
-  OtherMemoryDevice = 0x80,
-
-  HostProcessorBridge = 0,
-  ISABridge = 1,
-  EISABridge = 2,
-  MicroChannelBridge = 3,
-  PCIBridge = 4,
-  PCMCIABridge = 5,
-  VMEBridge = 6,
-  OtherBridgeDevice = 0x80,
-
-  RS232Device = 0,
-  ATCompatibleParallelPort = 1,
-  OtherCommunicationsDevice = 0x80,
-
-  ProgrammableInterruptController = 0,
-  DMAController = 1,
-  SystemTimer = 2,
-  RealTimeClock = 3,
-  L2Cache = 4,
-  NVRAM = 5,
-  PowerManagement = 6,
-  CMOS = 7,
-  OperatorPanel = 8,
-  ServiceProcessorClass1 = 9,
-  ServiceProcessorClass2 = 0xA,
-  ServiceProcessorClass3 = 0xB,
-  GraphicAssist = 0xC,
-  SystemPlanar = 0xF,                   /* 10/5/95                            */
-  OtherSystemPeripheral = 0x80,
-
-  KeyboardController = 0,
-  Digitizer = 1,
-  MouseController = 2,
-  TabletController = 3,                 /* 10/27/95                           */
-  OtherInputController = 0x80,
-
-  GeneralMemoryController = 0,
-  } PnP_SUB_TYPE;
-
-/* Device Interface Type Codes */
-
-typedef enum _PnP_INTERFACE {
-  General = 0,
-  GeneralSCSI = 0,
-  GeneralIDE = 0,
-  ATACompatible = 1,
-
-  GeneralFloppy = 0,
-  Compatible765 = 1,
-  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
-                                           register at port 398 and data
-                                           register at port 399               */
-  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
-  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
-  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
-  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
-
-  GeneralIPI = 0,
-
-  GeneralEther = 0,
-  GeneralToken = 0,
-  GeneralFDDI = 0,
-
-  GeneralVGA = 0,
-  GeneralSVGA = 0,
-  GeneralXGA = 0,
-
-  GeneralVideo = 0,
-  GeneralAudio = 0,
-  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
-
-  GeneralRAM = 0,
-  GeneralFLASH = 0,
-  PCIMemoryController = 0,              /* PCI Config Method                  */
-  RS6KMemoryController = 1,             /* RS6K Config Method                 */
-
-  GeneralHostBridge = 0,
-  GeneralISABridge = 0,
-  GeneralEISABridge = 0,
-  GeneralMCABridge = 0,
-  GeneralPCIBridge = 0,
-  PCIBridgeDirect = 0,
-  PCIBridgeIndirect = 1,
-  PCIBridgeRS6K = 2,
-  GeneralPCMCIABridge = 0,
-  GeneralVMEBridge = 0,
-
-  GeneralRS232 = 0,
-  COMx = 1,
-  Compatible16450 = 2,
-  Compatible16550 = 3,
-  NS398SerPort = 4,                     /* NS Super I/O wired to use index
-                                           register at port 398 and data
-                                           register at port 399               */
-  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
-  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
-  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
-
-  GeneralParPort = 0,
-  LPTx = 1,
-  NS398ParPort = 2,                     /* NS Super I/O wired to use index
-                                           register at port 398 and data
-                                           register at port 399               */
-  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
-  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
-  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
-
-  GeneralPIC = 0,
-  ISA_PIC = 1,
-  EISA_PIC = 2,
-  MPIC = 3,
-  RS6K_PIC = 4,
-
-  GeneralDMA = 0,
-  ISA_DMA = 1,
-  EISA_DMA = 2,
-
-  GeneralTimer = 0,
-  ISA_Timer = 1,
-  EISA_Timer = 2,
-  GeneralRTC = 0,
-  ISA_RTC = 1,
-
-  StoreThruOnly = 1,
-  StoreInEnabled = 2,
-  RS6KL2Cache = 3,
-
-  IndirectNVRAM = 0,                    /* Indirectly addressed               */
-  DirectNVRAM = 1,                      /* Memory Mapped                      */
-  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
-
-  GeneralPowerManagement = 0,
-  EPOWPowerManagement = 1,
-  PowerControl = 2,                    // d1378
-
-  GeneralCMOS = 0,
-
-  GeneralOPPanel = 0,
-  HarddiskLight = 1,
-  CDROMLight = 2,
-  PowerLight = 3,
-  KeyLock = 4,
-  ANDisplay = 5,                        /* AlphaNumeric Display               */
-  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
-  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
-
-  GeneralServiceProcessor = 0,
-
-  TransferData = 1,
-  IGMC32 = 2,
-  IGMC64 = 3,
-
-  GeneralSystemPlanar = 0,              /* 10/5/95                            */
-
-  } PnP_INTERFACE;
-
-/* PnP resources */
-
-/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
-
-typedef struct _SERIAL_ID {
-  unsigned char VendorID0;              /*    Bit(7)=0                        */
-                                        /*    Bits(6:2)=1st character in      */
-                                        /*       compressed ASCII             */
-                                        /*    Bits(1:0)=2nd character in      */
-                                        /*       compressed ASCII bits(4:3)   */
-  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
-                                        /*       compressed ASCII bits(2:0)   */
-                                        /*    Bits(4:0)=3rd character in      */
-                                        /*       compressed ASCII             */
-  unsigned char VendorID2;              /* Product number - vendor assigned   */
-  unsigned char VendorID3;              /* Product number - vendor assigned   */
-
-/* Serial number is to provide uniqueness if more than one board of same      */
-/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
-
-  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
-  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
-  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
-  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
-  unsigned char Checksum;
-  } SERIAL_ID;
-
-typedef enum _PnPItemName {
-  Unused = 0,
-  PnPVersion = 1,
-  LogicalDevice = 2,
-  CompatibleDevice = 3,
-  IRQFormat = 4,
-  DMAFormat = 5,
-  StartDepFunc = 6,
-  EndDepFunc = 7,
-  IOPort = 8,
-  FixedIOPort = 9,
-  Res1 = 10,
-  Res2 = 11,
-  Res3 = 12,
-  SmallVendorItem = 14,
-  EndTag = 15,
-  MemoryRange = 1,
-  ANSIIdentifier = 2,
-  UnicodeIdentifier = 3,
-  LargeVendorItem = 4,
-  MemoryRange32 = 5,
-  MemoryRangeFixed32 = 6,
-  } PnPItemName;
-
-/* Define a bunch of access functions for the bits in the tag field */
-
-/* Tag type - 0 = small; 1 = large */
-#define tag_type(t) (((t) & 0x80)>>7)
-#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
-
-/* Small item name is 4 bits - one of PnPItemName enum above */
-#define tag_small_item_name(t) (((t) & 0x78)>>3)
-#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
-
-/* Small item count is 3 bits - count of further bytes in packet */
-#define tag_small_count(t) ((t) & 0x07)
-#define set_tag_count(t,v) (t = (t & 0x78) | (v))
-
-/* Large item name is 7 bits - one of PnPItemName enum above */
-#define tag_large_item_name(t) ((t) & 0x7f)
-#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
-
-/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
-
-typedef union _PnP_TAG_PACKET {
-  struct _S1_Pack{                      /* VERSION PACKET                     */
-    unsigned char Tag;                  /* small tag = 0x0a                   */
-    unsigned char Version[2];           /* PnP version, Vendor version        */
-    } S1_Pack;
-
-  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
-    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
-    unsigned char DevId[4];             /* Logical device id                  */
-    unsigned char Flags[2];             /* bit(0) boot device;                */
-                                        /* bit(7:1) cmd in range x31-x37      */
-                                        /* bit(7:0) cmd in range x28-x3f (opt)*/
-    } S2_Pack;
-
-  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
-    unsigned char Tag;                  /* small tag = 0x1c                   */
-    unsigned char CompatId[4];          /* Compatible device id               */
-    } S3_Pack;
-
-  struct _S4_Pack{                      /* IRQ PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
-    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
-                                        /* bit(0) is IRQ8 ...                 */
-    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
-                                        /*  bit(0) - high true edge sensitive */
-                                        /*  bit(1) - low true edge sensitive  */
-                                        /*  bit(2) - high true level sensitive*/
-                                        /*  bit(3) - low true level sensitive */
-                                        /*  bit(7:4) - must be 0              */
-    } S4_Pack;
-
-  struct _S5_Pack{                      /* DMA PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x2a                   */
-    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
-    unsigned char DMAInfo;
-    } S5_Pack;
-
-  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
-    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
-    unsigned char Priority;             /* Optional; if missing then x01; else*/
-                                        /*  x00 = best possible               */
-                                        /*  x01 = acceptible                  */
-                                        /*  x02 = sub-optimal but functional  */
-    } S6_Pack;
-
-  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
-    unsigned char Tag;                  /* small tag = 0x38                   */
-    } S7_Pack;
-
-  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
-    unsigned char Tag;                  /* small tag x47                      */
-    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
-#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
-    unsigned char RangeMin[2];          /* Min base address                   */
-    unsigned char RangeMax[2];          /* Max base address                   */
-    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S8_Pack;
-
-  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
-    unsigned char Tag;                  /* small tag = 0x4b                   */
-    unsigned char Range[2];             /* base address 10 bits               */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S9_Pack;
-
-  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
-    union _S14_Data{
-      unsigned char Data[7];            /* Vendor defined                     */
-      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
-         unsigned char Type;            /* 00=non-IBM                         */
-         unsigned char PPCData[6];      /* Vendor defined                     */
-        } S14_PPCPack;
-      } S14_Data;
-    } S14_Pack;
-
-  struct _S15_Pack{                     /* END PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
-    unsigned char Check;                /* optional - checksum                */
-    } S15_Pack;
-
-  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
-    unsigned char Tag;                  /* large tag = 0x81                   */
-    unsigned char Count0;               /* x09                                */
-    unsigned char Count1;               /* x00                                */
-    unsigned char Data[9];              /* a variable array of bytes,         */
-                                        /* count in tag                       */
-    } L1_Pack;
-
-  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
-    unsigned char Tag;                  /* large tag = 0x82                   */
-    unsigned char Count0;               /* Length of string                   */
-    unsigned char Count1;
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-                                        /* count in tag                       */
-    } L2_Pack;
-
-  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
-    unsigned char Tag;                  /* large tag = 0x83                   */
-    unsigned char Count0;               /* Length + 2 of string               */
-    unsigned char Count1;
-    unsigned char Country0;             /* TBD                                */
-    unsigned char Country1;             /* TBD                                */
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-                                        /* count in tag                       */
-    } L3_Pack;
-
-  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* large tag = 0x84                   */
-    unsigned char Count0;
-    unsigned char Count1;
-    union _L4_Data{
-      unsigned char Data[1];            /* a variable array of bytes,         */
-                                        /* count in tag                       */
-      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
-         unsigned char Type;            /* 00=non-IBM                         */
-         unsigned char PPCData[1];      /* a variable array of bytes,         */
-                                        /* count in tag                       */
-        } L4_PPCPack;
-      } L4_Data;
-    } L4_Pack;
-
-  struct _L5_Pack{
-    unsigned char Tag;                  /* large tag = 0x85                   */
-    unsigned char Count0;               /* Count = 17                         */
-    unsigned char Count1;
-    unsigned char Data[17];
-    } L5_Pack;
-
-  struct _L6_Pack{
-    unsigned char Tag;                  /* large tag = 0x86                   */
-    unsigned char Count0;               /* Count = 9                          */
-    unsigned char Count1;
-    unsigned char Data[9];
-    } L6_Pack;
-
-  } PnP_TAG_PACKET;
-
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _PNP_ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h
deleted file mode 100644
index 935d1e05366b..000000000000
--- a/include/asm-ppc/ppc4xx_dma.h
+++ /dev/null
@@ -1,579 +0,0 @@
-/*
- * include/asm-ppc/ppc4xx_dma.h
- *
- * IBM PPC4xx DMA engine library
- *
- * Copyright 2000-2004 MontaVista Software Inc.
- *
- * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org>
- *
- * Original code by Armin Kuster <akuster@mvista.com>
- * and Pete Popov <ppopov@mvista.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASMPPC_PPC4xx_DMA_H
-#define __ASMPPC_PPC4xx_DMA_H
-
-#include <linux/types.h>
-#include <asm/mmu.h>
-#include <asm/ibm4xx.h>
-
-#undef DEBUG_4xxDMA
-
-#define MAX_PPC4xx_DMA_CHANNELS         4
-
-/*
- * Function return status codes
- * These values are used to indicate whether or not the function
- * call was successful, or a bad/invalid parameter was passed.
- */
-#define DMA_STATUS_GOOD                 0
-#define DMA_STATUS_BAD_CHANNEL          1
-#define DMA_STATUS_BAD_HANDLE           2
-#define DMA_STATUS_BAD_MODE             3
-#define DMA_STATUS_NULL_POINTER         4
-#define DMA_STATUS_OUT_OF_MEMORY        5
-#define DMA_STATUS_SGL_LIST_EMPTY       6
-#define DMA_STATUS_GENERAL_ERROR        7
-#define DMA_STATUS_CHANNEL_NOTFREE      8
-
-#define DMA_CHANNEL_BUSY                0x80000000
-
-/*
- * These indicate status as returned from the DMA Status Register.
- */
-#define DMA_STATUS_NO_ERROR     0
-#define DMA_STATUS_CS           1       /* Count Status        */
-#define DMA_STATUS_TS           2       /* Transfer Status     */
-#define DMA_STATUS_DMA_ERROR    3       /* DMA Error Occurred  */
-#define DMA_STATUS_DMA_BUSY     4       /* The channel is busy */
-
-
-/*
- * DMA Channel Control Registers
- */
-
-#ifdef CONFIG_44x
-#define PPC4xx_DMA_64BIT
-#define DMA_CR_OFFSET 1
-#else
-#define DMA_CR_OFFSET 0
-#endif
-
-#define DMA_CE_ENABLE        (1<<31)    /* DMA Channel Enable */
-#define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31)
-#define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31)
-
-#define DMA_CIE_ENABLE        (1<<30)   /* DMA Channel Interrupt Enable */
-#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30)
-#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30)
-
-#define DMA_TD                (1<<29)
-#define SET_DMA_TD(x)         (((x)&0x1)<<29)
-#define GET_DMA_TD(x)         (((x)&DMA_TD)>>29)
-
-#define DMA_PL                (1<<28)   /* Peripheral Location */
-#define SET_DMA_PL(x)         (((x)&0x1)<<28)
-#define GET_DMA_PL(x)         (((x)&DMA_PL)>>28)
-
-#define EXTERNAL_PERIPHERAL    0
-#define INTERNAL_PERIPHERAL    1
-
-#define SET_DMA_PW(x)     (((x)&0x3)<<(26-DMA_CR_OFFSET))       /* Peripheral Width */
-#define DMA_PW_MASK       SET_DMA_PW(3)
-#define   PW_8                 0
-#define   PW_16                1
-#define   PW_32                2
-#define   PW_64                3
-/* FIXME: Add PW_128 support for 440GP DMA block */
-#define GET_DMA_PW(x)     (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET))
-
-#define DMA_DAI           (1<<(25-DMA_CR_OFFSET))       /* Destination Address Increment */
-#define SET_DMA_DAI(x)    (((x)&0x1)<<(25-DMA_CR_OFFSET))
-
-#define DMA_SAI           (1<<(24-DMA_CR_OFFSET))       /* Source Address Increment */
-#define SET_DMA_SAI(x)    (((x)&0x1)<<(24-DMA_CR_OFFSET))
-
-#define DMA_BEN           (1<<(23-DMA_CR_OFFSET))       /* Buffer Enable */
-#define SET_DMA_BEN(x)    (((x)&0x1)<<(23-DMA_CR_OFFSET))
-
-#define SET_DMA_TM(x)     (((x)&0x3)<<(21-DMA_CR_OFFSET))       /* Transfer Mode */
-#define DMA_TM_MASK       SET_DMA_TM(3)
-#define   TM_PERIPHERAL        0        /* Peripheral */
-#define   TM_RESERVED          1        /* Reserved */
-#define   TM_S_MM              2        /* Memory to Memory */
-#define   TM_D_MM              3        /* Device Paced Memory to Memory */
-#define GET_DMA_TM(x)     (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET))
-
-#define SET_DMA_PSC(x)    (((x)&0x3)<<(19-DMA_CR_OFFSET))       /* Peripheral Setup Cycles */
-#define DMA_PSC_MASK      SET_DMA_PSC(3)
-#define GET_DMA_PSC(x)    (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET))
-
-#define SET_DMA_PWC(x)    (((x)&0x3F)<<(13-DMA_CR_OFFSET))      /* Peripheral Wait Cycles */
-#define DMA_PWC_MASK      SET_DMA_PWC(0x3F)
-#define GET_DMA_PWC(x)    (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET))
-
-#define SET_DMA_PHC(x)    (((x)&0x7)<<(10-DMA_CR_OFFSET))       /* Peripheral Hold Cycles */
-#define DMA_PHC_MASK      SET_DMA_PHC(0x7)
-#define GET_DMA_PHC(x)    (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET))
-
-#define DMA_ETD_OUTPUT     (1<<(9-DMA_CR_OFFSET))       /* EOT pin is a TC output */
-#define SET_DMA_ETD(x)     (((x)&0x1)<<(9-DMA_CR_OFFSET))
-
-#define DMA_TCE_ENABLE     (1<<(8-DMA_CR_OFFSET))
-#define SET_DMA_TCE(x)     (((x)&0x1)<<(8-DMA_CR_OFFSET))
-
-#define DMA_DEC            (1<<(2))     /* Address Decrement */
-#define SET_DMA_DEC(x)     (((x)&0x1)<<2)
-#define GET_DMA_DEC(x)     (((x)&DMA_DEC)>>2)
-
-
-/*
- * Transfer Modes
- * These modes are defined in a way that makes it possible to
- * simply "or" in the value in the control register.
- */
-
-#define DMA_MODE_MM             (SET_DMA_TM(TM_S_MM))   /* memory to memory */
-
-                                /* Device-paced memory to memory, */
-                                /* device is at source address    */
-#define DMA_MODE_MM_DEVATSRC    (DMA_TD | SET_DMA_TM(TM_D_MM))
-
-                                /* Device-paced memory to memory,      */
-                                /* device is at destination address    */
-#define DMA_MODE_MM_DEVATDST    (SET_DMA_TM(TM_D_MM))
-
-/* 405gp/440gp */
-#define SET_DMA_PREFETCH(x)   (((x)&0x3)<<(4-DMA_CR_OFFSET))    /* Memory Read Prefetch */
-#define DMA_PREFETCH_MASK      SET_DMA_PREFETCH(3)
-#define   PREFETCH_1           0        /* Prefetch 1 Double Word */
-#define   PREFETCH_2           1
-#define   PREFETCH_4           2
-#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET))
-
-#define DMA_PCE            (1<<(3-DMA_CR_OFFSET))       /* Parity Check Enable */
-#define SET_DMA_PCE(x)     (((x)&0x1)<<(3-DMA_CR_OFFSET))
-#define GET_DMA_PCE(x)     (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET))
-
-/* stb3x */
-
-#define DMA_ECE_ENABLE (1<<5)
-#define SET_DMA_ECE(x) (((x)&0x1)<<5)
-#define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5)
-
-#define DMA_TCD_DISABLE (1<<4)
-#define SET_DMA_TCD(x) (((x)&0x1)<<4)
-#define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4)
-
-typedef uint32_t sgl_handle_t;
-
-#ifdef CONFIG_PPC4xx_EDMA
-
-#define SGL_LIST_SIZE 4096
-#define DMA_PPC4xx_SIZE SGL_LIST_SIZE
-
-#define SET_DMA_PRIORITY(x)   (((x)&0x3)<<(6-DMA_CR_OFFSET))    /* DMA Channel Priority */
-#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3)
-#define PRIORITY_LOW           0
-#define PRIORITY_MID_LOW       1
-#define PRIORITY_MID_HIGH      2
-#define PRIORITY_HIGH          3
-#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET))
-
-/*
- * DMA Polarity Configuration Register
- */
-#define DMAReq_ActiveLow(chan) (1<<(31-(chan*3)))
-#define DMAAck_ActiveLow(chan) (1<<(30-(chan*3)))
-#define EOT_ActiveLow(chan)    (1<<(29-(chan*3)))       /* End of Transfer */
-
-/*
- * DMA Sleep Mode Register
- */
-#define SLEEP_MODE_ENABLE (1<<21)
-
-/*
- * DMA Status Register
- */
-#define DMA_CS0           (1<<31)       /* Terminal Count has been reached */
-#define DMA_CS1           (1<<30)
-#define DMA_CS2           (1<<29)
-#define DMA_CS3           (1<<28)
-
-#define DMA_TS0           (1<<27)       /* End of Transfer has been requested */
-#define DMA_TS1           (1<<26)
-#define DMA_TS2           (1<<25)
-#define DMA_TS3           (1<<24)
-
-#define DMA_CH0_ERR       (1<<23)       /* DMA Chanel 0 Error */
-#define DMA_CH1_ERR       (1<<22)
-#define DMA_CH2_ERR       (1<<21)
-#define DMA_CH3_ERR       (1<<20)
-
-#define DMA_IN_DMA_REQ0   (1<<19)       /* Internal DMA Request is pending */
-#define DMA_IN_DMA_REQ1   (1<<18)
-#define DMA_IN_DMA_REQ2   (1<<17)
-#define DMA_IN_DMA_REQ3   (1<<16)
-
-#define DMA_EXT_DMA_REQ0  (1<<15)       /* External DMA Request is pending */
-#define DMA_EXT_DMA_REQ1  (1<<14)
-#define DMA_EXT_DMA_REQ2  (1<<13)
-#define DMA_EXT_DMA_REQ3  (1<<12)
-
-#define DMA_CH0_BUSY      (1<<11)       /* DMA Channel 0 Busy */
-#define DMA_CH1_BUSY      (1<<10)
-#define DMA_CH2_BUSY       (1<<9)
-#define DMA_CH3_BUSY       (1<<8)
-
-#define DMA_SG0            (1<<7)       /* DMA Channel 0 Scatter/Gather in progress */
-#define DMA_SG1            (1<<6)
-#define DMA_SG2            (1<<5)
-#define DMA_SG3            (1<<4)
-
-/* DMA Channel Count Register */
-#define DMA_CTC_BTEN     (1<<23)    /* Burst Enable/Disable bit */
-#define DMA_CTC_BSIZ_MSK (3<<21)    /* Mask of the Burst size bits */
-#define DMA_CTC_BSIZ_2   (0)
-#define DMA_CTC_BSIZ_4   (1<<21)
-#define DMA_CTC_BSIZ_8   (2<<21)
-#define DMA_CTC_BSIZ_16  (3<<21)
-
-/*
- * DMA SG Command Register
- */
-#define SSG_ENABLE(chan)        (1<<(31-chan))  /* Start Scatter Gather */
-#define SSG_MASK_ENABLE(chan)   (1<<(15-chan))  /* Enable writing to SSG0 bit */
-
-/*
- * DMA Scatter/Gather Descriptor Bit fields
- */
-#define SG_LINK            (1<<31)      /* Link */
-#define SG_TCI_ENABLE      (1<<29)      /* Enable Terminal Count Interrupt */
-#define SG_ETI_ENABLE      (1<<28)      /* Enable End of Transfer Interrupt */
-#define SG_ERI_ENABLE      (1<<27)      /* Enable Error Interrupt */
-#define SG_COUNT_MASK       0xFFFF      /* Count Field */
-
-#define SET_DMA_CONTROL \
-                (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable         */ \
-                SET_DMA_BEN(p_init->buffer_enable)     | /* buffer enable            */\
-                SET_DMA_ETD(p_init->etd_output)        | /* end of transfer pin      */ \
-                SET_DMA_TCE(p_init->tce_enable)        | /* terminal count enable    */ \
-                SET_DMA_PL(p_init->pl)                 | /* peripheral location      */ \
-                SET_DMA_DAI(p_init->dai)               | /* dest addr increment      */ \
-                SET_DMA_SAI(p_init->sai)               | /* src addr increment       */ \
-                SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */ \
-                SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
-                SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
-                SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
-                SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
-                SET_DMA_PREFETCH(p_init->pf)              /* read prefetch           */)
-
-#define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan))
-
-#elif defined(CONFIG_STB03xxx)          /* stb03xxx */
-
-#define DMA_PPC4xx_SIZE 4096
-
-/*
- * DMA Status Register
- */
-
-#define SET_DMA_PRIORITY(x)   (((x)&0x00800001))        /* DMA Channel Priority */
-#define DMA_PRIORITY_MASK       0x00800001
-#define   PRIORITY_LOW          0x00000000
-#define   PRIORITY_MID_LOW      0x00000001
-#define   PRIORITY_MID_HIGH     0x00800000
-#define   PRIORITY_HIGH         0x00800001
-#define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001))
-
-#define DMA_CS0           (1<<31)       /* Terminal Count has been reached */
-#define DMA_CS1           (1<<30)
-#define DMA_CS2           (1<<29)
-#define DMA_CS3           (1<<28)
-
-#define DMA_TS0           (1<<27)       /* End of Transfer has been requested */
-#define DMA_TS1           (1<<26)
-#define DMA_TS2           (1<<25)
-#define DMA_TS3           (1<<24)
-
-#define DMA_CH0_ERR       (1<<23)       /* DMA Chanel 0 Error */
-#define DMA_CH1_ERR       (1<<22)
-#define DMA_CH2_ERR       (1<<21)
-#define DMA_CH3_ERR       (1<<20)
-
-#define DMA_CT0           (1<<19)       /* Chained transfere */
-
-#define DMA_IN_DMA_REQ0   (1<<18)       /* Internal DMA Request is pending */
-#define DMA_IN_DMA_REQ1   (1<<17)
-#define DMA_IN_DMA_REQ2   (1<<16)
-#define DMA_IN_DMA_REQ3   (1<<15)
-
-#define DMA_EXT_DMA_REQ0  (1<<14)       /* External DMA Request is pending */
-#define DMA_EXT_DMA_REQ1  (1<<13)
-#define DMA_EXT_DMA_REQ2  (1<<12)
-#define DMA_EXT_DMA_REQ3  (1<<11)
-
-#define DMA_CH0_BUSY      (1<<10)       /* DMA Channel 0 Busy */
-#define DMA_CH1_BUSY      (1<<9)
-#define DMA_CH2_BUSY       (1<<8)
-#define DMA_CH3_BUSY       (1<<7)
-
-#define DMA_CT1            (1<<6)       /* Chained transfere */
-#define DMA_CT2            (1<<5)
-#define DMA_CT3            (1<<4)
-
-#define DMA_CH_ENABLE (1<<7)
-#define SET_DMA_CH(x) (((x)&0x1)<<7)
-#define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7)
-
-/* STBx25xxx dma unique */
-/* enable device port on a dma channel
- * example ext 0 on dma 1
- */
-
-#define SSP0_RECV       15
-#define SSP0_XMIT       14
-#define EXT_DMA_0       12
-#define SC1_XMIT        11
-#define SC1_RECV        10
-#define EXT_DMA_2       9
-#define EXT_DMA_3       8
-#define SERIAL2_XMIT    7
-#define SERIAL2_RECV    6
-#define SC0_XMIT        5
-#define SC0_RECV        4
-#define SERIAL1_XMIT    3
-#define SERIAL1_RECV    2
-#define SERIAL0_XMIT    1
-#define SERIAL0_RECV    0
-
-#define DMA_CHAN_0      1
-#define DMA_CHAN_1      2
-#define DMA_CHAN_2      3
-#define DMA_CHAN_3      4
-
-/* end STBx25xx */
-
-/*
- * Bit 30 must be one for Redwoods, otherwise transfers may receive errors.
- */
-#define DMA_CR_MB0 0x2
-
-#define SET_DMA_CONTROL \
-                (SET_DMA_CIE_ENABLE(p_init->int_enable) |  /* interrupt enable         */ \
-                SET_DMA_ETD(p_init->etd_output)        |  /* end of transfer pin      */ \
-                SET_DMA_TCE(p_init->tce_enable)        |  /* terminal count enable    */ \
-                SET_DMA_PL(p_init->pl)                 |  /* peripheral location      */ \
-                SET_DMA_DAI(p_init->dai)               |  /* dest addr increment      */ \
-                SET_DMA_SAI(p_init->sai)               |  /* src addr increment       */ \
-                SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */  \
-                SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
-                SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
-                SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
-                SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
-                SET_DMA_TCD(p_init->tcd_disable)          |  /* TC chain mode disable   */ \
-                SET_DMA_ECE(p_init->ece_enable)   |  /* ECE chanin mode enable  */ \
-                SET_DMA_CH(p_init->ch_enable)   |    /* Chain enable            */ \
-                DMA_CR_MB0                              /* must be one */)
-
-#define GET_DMA_POLARITY(chan) chan
-
-#endif
-
-typedef struct {
-        unsigned short in_use;  /* set when channel is being used, clr when
-                                 * available.
-                                 */
-        /*
-         * Valid polarity settings:
-         *   DMAReq_ActiveLow(n)
-         *   DMAAck_ActiveLow(n)
-         *   EOT_ActiveLow(n)
-         *
-         *   n is 0 to max dma chans
-         */
-        unsigned int polarity;
-
-        char buffer_enable;     /* Boolean: buffer enable            */
-        char tce_enable;        /* Boolean: terminal count enable    */
-        char etd_output;        /* Boolean: eot pin is a tc output   */
-        char pce;               /* Boolean: parity check enable      */
-
-        /*
-         * Peripheral location:
-         * INTERNAL_PERIPHERAL (UART0 on the 405GP)
-         * EXTERNAL_PERIPHERAL
-         */
-        char pl;                /* internal/external peripheral      */
-
-        /*
-         * Valid pwidth settings:
-         *   PW_8
-         *   PW_16
-         *   PW_32
-         *   PW_64
-         */
-        unsigned int pwidth;
-
-        char dai;               /* Boolean: dst address increment   */
-        char sai;               /* Boolean: src address increment   */
-
-        /*
-         * Valid psc settings: 0-3
-         */
-        unsigned int psc;       /* Peripheral Setup Cycles         */
-
-        /*
-         * Valid pwc settings:
-         * 0-63
-         */
-        unsigned int pwc;       /* Peripheral Wait Cycles          */
-
-        /*
-         * Valid phc settings:
-         * 0-7
-         */
-        unsigned int phc;       /* Peripheral Hold Cycles          */
-
-        /*
-         * Valid cp (channel priority) settings:
-         *   PRIORITY_LOW
-         *   PRIORITY_MID_LOW
-         *   PRIORITY_MID_HIGH
-         *   PRIORITY_HIGH
-         */
-        unsigned int cp;        /* channel priority                */
-
-        /*
-         * Valid pf (memory read prefetch) settings:
-         *
-         *   PREFETCH_1
-         *   PREFETCH_2
-         *   PREFETCH_4
-         */
-        unsigned int pf;        /* memory read prefetch            */
-
-        /*
-         * Boolean: channel interrupt enable
-         * NOTE: for sgl transfers, only the last descriptor will be setup to
-         * interrupt.
-         */
-        char int_enable;
-
-        char shift;             /* easy access to byte_count shift, based on */
-        /* the width of the channel                  */
-
-        uint32_t control;       /* channel control word                      */
-
-        /* These variabled are used ONLY in single dma transfers              */
-        unsigned int mode;      /* transfer mode                     */
-        phys_addr_t addr;
-        char ce;                /* channel enable */
-#ifdef CONFIG_STB03xxx
-        char ch_enable;
-        char tcd_disable;
-        char ece_enable;
-        char td;                /* transfer direction */
-#endif
-
-        char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */
-} ppc_dma_ch_t;
-
-/*
- * PPC44x DMA implementations have a slightly different
- * descriptor layout.  Probably moved about due to the
- * change to 64-bit addresses and link pointer. I don't
- * know why they didn't just leave control_count after
- * the dst_addr.
- */
-#ifdef PPC4xx_DMA_64BIT
-typedef struct {
-        uint32_t control;
-        uint32_t control_count;
-        phys_addr_t src_addr;
-        phys_addr_t dst_addr;
-        phys_addr_t next;
-} ppc_sgl_t;
-#else
-typedef struct {
-        uint32_t control;
-        phys_addr_t src_addr;
-        phys_addr_t dst_addr;
-        uint32_t control_count;
-        uint32_t next;
-} ppc_sgl_t;
-#endif
-
-typedef struct {
-        unsigned int dmanr;
-        uint32_t control;       /* channel ctrl word; loaded from each descrptr */
-        uint32_t sgl_control;   /* LK, TCI, ETI, and ERI bits in sgl descriptor */
-        dma_addr_t dma_addr;    /* dma (physical) address of this list          */
-        ppc_sgl_t *phead;
-        dma_addr_t phead_dma;
-        ppc_sgl_t *ptail;
-        dma_addr_t ptail_dma;
-} sgl_list_info_t;
-
-typedef struct {
-        phys_addr_t *src_addr;
-        phys_addr_t *dst_addr;
-        phys_addr_t dma_src_addr;
-        phys_addr_t dma_dst_addr;
-} pci_alloc_desc_t;
-
-extern ppc_dma_ch_t dma_channels[];
-
-/*
- * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c
- */
-extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *);
-extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *);
-extern int ppc4xx_set_channel_priority(unsigned int, unsigned int);
-extern unsigned int ppc4xx_get_peripheral_width(unsigned int);
-extern void ppc4xx_set_sg_addr(int, phys_addr_t);
-extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int);
-extern void ppc4xx_enable_dma_sgl(sgl_handle_t);
-extern void ppc4xx_disable_dma_sgl(sgl_handle_t);
-extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *);
-extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *);
-extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int);
-extern void ppc4xx_free_dma_handle(sgl_handle_t);
-extern int ppc4xx_get_dma_status(void);
-extern int ppc4xx_enable_burst(unsigned int);
-extern int ppc4xx_disable_burst(unsigned int);
-extern int ppc4xx_set_burst_size(unsigned int, unsigned int);
-extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr);
-extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr);
-extern void ppc4xx_enable_dma(unsigned int dmanr);
-extern void ppc4xx_disable_dma(unsigned int dmanr);
-extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count);
-extern int ppc4xx_get_dma_residue(unsigned int dmanr);
-extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
-                                 phys_addr_t dst_dma_addr);
-extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr);
-extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr);
-extern int ppc4xx_clr_dma_status(unsigned int dmanr);
-extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
-extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
-extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode);
-
-/* These are in kernel/dma.c: */
-
-/* reserve a DMA channel */
-extern int request_dma(unsigned int dmanr, const char *device_id);
-/* release it again */
-extern void free_dma(unsigned int dmanr);
-#endif
-#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h
deleted file mode 100644
index e44261206f8b..000000000000
--- a/include/asm-ppc/ppc4xx_pic.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * include/asm-ppc/ppc4xx_pic.h
- *
- * Interrupt controller driver for PowerPC 4xx-based processors.
- *
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __PPC4XX_PIC_H__
-#define __PPC4XX_PIC_H__
-
-#include <linux/types.h>
-#include <linux/irq.h>
-
-/* "Fixed" UIC settings (they are chip, not board specific),
- * e.g. polarity/triggerring for internal interrupt sources.
- *
- * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg
- * with these "fixed" settings: .polarity contains exact value which will
- * be written (masked with "ext_irq_mask") into UICx_PR register,
- * .triggering - to UICx_TR.
- *
- * Settings for external IRQs can be specified separately by the
- * board support code. In this case properly sized array of unsigned
- * char named ppc4xx_uic_ext_irq_cfg should be filled with correct
- * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines.
- *
- * If these arrays aren't provided, UIC initialization code keeps firmware
- * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg
- * is defined.
- *
- * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as
- * "weak" symbols in ppc4xx_pic.c
- *
- */
-struct ppc4xx_uic_settings {
-        u32 polarity;
-        u32 triggering;
-        u32 ext_irq_mask;
-};
-
-extern void ppc4xx_pic_init(void);
-
-#endif                          /* __PPC4XX_PIC_H__ */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
deleted file mode 100644
index d2fee41d600b..000000000000
--- a/include/asm-ppc/ppc_sys.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * include/asm-ppc/ppc_sys.h
- *
- * PPC system definitions and library functions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_SYS_H
-#define __ASM_PPC_SYS_H
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_8260)
-#include <asm/mpc8260.h>
-#elif defined(CONFIG_8xx)
-#include <asm/mpc8xx.h>
-#elif defined(CONFIG_PPC_MPC52xx)
-#include <asm/mpc52xx.h>
-#elif defined(CONFIG_MPC10X_BRIDGE)
-#include <asm/mpc10x.h>
-#else
-#error "need definition of ppc_sys_devices"
-#endif
-
-#define PPC_SYS_IORESOURCE_FIXUPPED     0x00000001      
-
-struct ppc_sys_spec {
-        /* PPC sys is matched via (ID & mask) == value, id could be
-         * PVR, SVR, IMMR, * etc. */
-        u32                     mask;
-        u32                     value;
-        u32                     num_devices;
-        char                    *ppc_sys_name;
-        u8                      config[NUM_PPC_SYS_DEVS];
-        enum ppc_sys_devices    *device_list;
-};
-
-struct platform_notify_dev_map {
-        const char *bus_id;
-        void (*rtn)(struct platform_device * pdev, int idx);
-};
-
-enum platform_device_func {
-        PPC_SYS_FUNC_DUMMY = 0,
-        PPC_SYS_FUNC_ETH = 1,
-        PPC_SYS_FUNC_UART = 2,
-        PPC_SYS_FUNC_HLDC = 3,
-        PPC_SYS_FUNC_USB = 4,
-        PPC_SYS_FUNC_IRDA = 5,
-};
-
-#define PPC_SYS_CONFIG_DISABLED         1
-
-/* describes all specific chips and which devices they have on them */
-extern struct ppc_sys_spec ppc_sys_specs[];
-extern struct ppc_sys_spec *cur_ppc_sys_spec;
-
-/* determine which specific SOC we are */
-extern void identify_ppc_sys_by_id(u32 id) __init;
-extern void identify_ppc_sys_by_name(char *name) __init;
-extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init;
-
-/* describes all devices that may exist in a given family of processors */
-extern struct platform_device ppc_sys_platform_devices[];
-
-/* allow any platform_device fixup to occur before device is registered */
-extern int (*ppc_sys_device_fixup) (struct platform_device * pdev);
-
-/* Update all memory resources by paddr, call before platform_device_register */
-extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev,
-                                       phys_addr_t paddr) __init;
-
-/* Get platform_data pointer out of platform device, call before platform_device_register */
-extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init;
-
-/* remove a device from the system */
-extern void ppc_sys_device_remove(enum ppc_sys_devices dev);
-
-/* Function assignment stuff */
-void ppc_sys_device_initfunc(void);
-void ppc_sys_device_setfunc(enum ppc_sys_devices dev,
-                            enum platform_device_func func);
-void ppc_sys_device_set_func_all(enum platform_device_func func);
-
-void platform_notify_map(const struct platform_notify_dev_map *map,
-                         struct device *dev);
-
-/* Enable / disable stuff */
-void ppc_sys_device_disable(enum ppc_sys_devices dev);
-void ppc_sys_device_enable(enum ppc_sys_devices dev);
-void ppc_sys_device_enable_all(void);
-void ppc_sys_device_disable_all(void);
-
-#endif                          /* __ASM_PPC_SYS_H */
-#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h
deleted file mode 100644
index 3819e17cd7b0..000000000000
--- a/include/asm-ppc/ppcboot.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_PPCBOOT_H__
-#define __ASM_PPCBOOT_H__
-
-/*
- * Board information passed to kernel from PPCBoot
- *
- * include/asm-ppc/ppcboot.h
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-typedef struct bd_info {
-        unsigned long   bi_memstart;    /* start of DRAM memory */
-        unsigned long   bi_memsize;     /* size  of DRAM memory in bytes */
-        unsigned long   bi_flashstart;  /* start of FLASH memory */
-        unsigned long   bi_flashsize;   /* size  of FLASH memory */
-        unsigned long   bi_flashoffset; /* reserved area for startup monitor */
-        unsigned long   bi_sramstart;   /* start of SRAM memory */
-        unsigned long   bi_sramsize;    /* size  of SRAM memory */
-#if defined(CONFIG_8xx) || defined(CONFIG_CPM2)
-        unsigned long   bi_immr_base;   /* base of IMMR register */
-#endif
-#if defined(CONFIG_PPC_MPC52xx)
-        unsigned long   bi_mbar_base;   /* base of internal registers */
-#endif
-        unsigned long   bi_bootflags;   /* boot / reboot flag (for LynxOS) */
-        unsigned long   bi_ip_addr;     /* IP Address */
-        unsigned char   bi_enetaddr[6]; /* Ethernet address */
-        unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
-        unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
-        unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
-        unsigned long   bi_cpmfreq;     /* CPM_CLK Freq, in MHz */
-        unsigned long   bi_brgfreq;     /* BRG_CLK Freq, in MHz */
-        unsigned long   bi_sccfreq;     /* SCC_CLK Freq, in MHz */
-        unsigned long   bi_vco;         /* VCO Out from PLL, in MHz */
-#endif
-#if defined(CONFIG_PPC_MPC52xx)
-        unsigned long   bi_ipbfreq;     /* IPB Bus Freq, in MHz */
-        unsigned long   bi_pcifreq;     /* PCI Bus Freq, in MHz */
-#endif
-        unsigned long   bi_baudrate;    /* Console Baudrate */
-#if defined(CONFIG_4xx)
-        unsigned char   bi_s_version[4];        /* Version of this structure */
-        unsigned char   bi_r_version[32];       /* Version of the ROM (IBM) */
-        unsigned int    bi_procfreq;    /* CPU (Internal) Freq, in Hz */
-        unsigned int    bi_plb_busfreq; /* PLB Bus speed, in Hz */
-        unsigned int    bi_pci_busfreq; /* PCI Bus speed, in Hz */
-        unsigned char   bi_pci_enetaddr[6];     /* PCI Ethernet MAC address */
-#endif
-#if defined(CONFIG_HYMOD)
-        hymod_conf_t    bi_hymod_conf;  /* hymod configuration information */
-#endif
-#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x)
-        /* second onboard ethernet port */
-        unsigned char   bi_enet1addr[6];
-#endif
-#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX)
-        /* third onboard ethernet ports */
-        unsigned char   bi_enet2addr[6];
-#endif
-#if defined(CONFIG_440GX)
-        /* fourth onboard ethernet ports */
-        unsigned char   bi_enet3addr[6];
-#endif
-#if defined(CONFIG_4xx)
-        unsigned int    bi_opbfreq;             /* OB clock in Hz */
-        int             bi_iic_fast[2];         /* Use fast i2c mode */
-#endif
-#if defined(CONFIG_440GX)
-        int             bi_phynum[4];           /* phy mapping */
-        int             bi_phymode[4];          /* phy mode */
-#endif
-} bd_t;
-
-#define bi_tbfreq       bi_intfreq
-
-#endif /* __ASSEMBLY__ */
-#endif  /* __ASM_PPCBOOT_H__ */
diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h
deleted file mode 100644
index 6dbc36a84df2..000000000000
--- a/include/asm-ppc/prep_nvram.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * PreP compliant NVRAM access
- */
-
-/* Corey Minyard (minyard@acm.org) - Stolen from PReP book.   Per the
-   license I must say:
-     (C) Copyright (Corey Minyard), (1998).  All rights reserved
- */
-
-/* Structure map for NVRAM on PowerPC Reference Platform */
-/* All fields are either character/byte strings which are valid either
-  endian or they are big-endian numbers.
-
-  There are a number of Date and Time fields which are in RTC format,
-  big-endian. These are stored in UT (GMT).
-
-  For enum's: if given in hex then they are bit significant, i.e. only
-  one bit is on for each enum.
-*/
-#ifdef __KERNEL__
-#ifndef _PPC_PREP_NVRAM_H
-#define _PPC_PREP_NVRAM_H
-
-#define MAX_PREP_NVRAM 0x8000
-#define PREP_NVRAM_AS0  0x74
-#define PREP_NVRAM_AS1  0x75
-#define PREP_NVRAM_DATA 0x77
-
-#define NVSIZE 4096     /* size of NVRAM */
-#define OSAREASIZE 512  /* size of OSArea space */
-#define CONFSIZE 1024   /* guess at size of Configuration space */
-
-typedef struct _SECURITY {
-  unsigned long BootErrCnt;         /* Count of boot password errors */
-  unsigned long ConfigErrCnt;       /* Count of config password errors */
-  unsigned long BootErrorDT[2];     /* Date&Time from RTC of last error in pw */
-  unsigned long ConfigErrorDT[2];   /* Date&Time from RTC of last error in pw */
-  unsigned long BootCorrectDT[2];   /* Date&Time from RTC of last correct pw */
-  unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */
-  unsigned long BootSetDT[2];       /* Date&Time from RTC of last set of pw */
-  unsigned long ConfigSetDT[2];     /* Date&Time from RTC of last set of pw */
-  unsigned char Serial[16];         /* Box serial number */
-} SECURITY;
-
-typedef enum _OS_ID {
-  Unknown = 0,
-  Firmware = 1,
-  AIX = 2,
-  NT = 3,
-  MKOS2 = 4,
-  MKAIX = 5,
-  Taligent = 6,
-  Solaris = 7,
-  MK = 12
-} OS_ID;
-
-typedef struct _ERROR_LOG {
-  unsigned char ErrorLogEntry[40]; /* To be architected */
-} ERROR_LOG;
-
-typedef enum _BOOT_STATUS {
-  BootStarted = 0x01,
-  BootFinished = 0x02,
-  RestartStarted = 0x04,
-  RestartFinished = 0x08,
-  PowerFailStarted = 0x10,
-  PowerFailFinished = 0x20,
-  ProcessorReady = 0x40,
-  ProcessorRunning = 0x80,
-  ProcessorStart = 0x0100
-} BOOT_STATUS;
-
-typedef struct _RESTART_BLOCK {
-  unsigned short Version;
-  unsigned short Revision;
-  unsigned long ResumeReserve1[2];
-  volatile unsigned long BootStatus;
-  unsigned long CheckSum; /* Checksum of RESTART_BLOCK */
-  void * RestartAddress;
-  void * SaveAreaAddr;
-  unsigned long SaveAreaLength;
-} RESTART_BLOCK;
-
-typedef enum _OSAREA_USAGE {
-  Empty = 0,
-  Used = 1
-} OSAREA_USAGE;
-
-typedef enum _PM_MODE {
-  Suspend = 0x80, /* Part of state is in memory */
-  Normal = 0x00   /* No power management in effect */
-} PMMODE;
-
-typedef struct _HEADER {
-  unsigned short Size;       /* NVRAM size in K(1024) */
-  unsigned char Version;     /* Structure map different */
-  unsigned char Revision;    /* Structure map the same -may
-                                be new values in old fields
-                                in other words old code still works */
-  unsigned short Crc1;       /* check sum from beginning of nvram to OSArea */
-  unsigned short Crc2;       /* check sum of config */
-  unsigned char LastOS;      /* OS_ID */
-  unsigned char Endian;      /* B if big endian, L if little endian */
-  unsigned char OSAreaUsage; /* OSAREA_USAGE */
-  unsigned char PMMode;      /* Shutdown mode */
-  RESTART_BLOCK RestartBlock;
-  SECURITY Security;
-  ERROR_LOG ErrorLog[2];
-
-  /* Global Environment information */
-  void * GEAddress;
-  unsigned long GELength;
-
-  /* Date&Time from RTC of last change to Global Environment */
-  unsigned long GELastWriteDT[2];
-
-  /* Configuration information */
-  void * ConfigAddress;
-  unsigned long ConfigLength;
-
-  /* Date&Time from RTC of last change to Configuration */
-  unsigned long ConfigLastWriteDT[2];
-  unsigned long ConfigCount; /* Count of entries in Configuration */
-
-  /* OS dependent temp area */
-  void * OSAreaAddress;
-  unsigned long OSAreaLength;
-
-  /* Date&Time from RTC of last change to OSAreaArea */
-  unsigned long OSAreaLastWriteDT[2];
-} HEADER;
-
-/* Here is the whole map of the NVRAM */
-typedef struct _NVRAM_MAP {
-  HEADER Header;
-  unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)];
-  unsigned char OSArea[OSAREASIZE];
-  unsigned char ConfigArea[CONFSIZE];
-} NVRAM_MAP;
-
-/* Routines to manipulate the NVRAM */
-void init_prep_nvram(void);
-char *prep_nvram_get_var(const char *name);
-char *prep_nvram_first_var(void);
-char *prep_nvram_next_var(char *name);
-
-/* Routines to read and write directly to the NVRAM */
-unsigned char prep_nvram_read_val(int addr);
-void prep_nvram_write_val(int           addr,
-                          unsigned char val);
-
-#endif /* _PPC_PREP_NVRAM_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h
deleted file mode 100644
index 71f4c996fe75..000000000000
--- a/include/asm-ppc/prom.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Definitions for talking to the Open Firmware PROM on
- * Power Macintosh computers.
- *
- * Copyright (C) 1996 Paul Mackerras.
- */
-#ifdef __KERNEL__
-#ifndef _PPC_PROM_H
-#define _PPC_PROM_H
-
-/* This is used in arch/ppc/mm/mem_pieces.h */
-struct reg_property {
-        unsigned int address;
-        unsigned int size;
-};
-
-/*
- * These macros assist in performing the address calculations that we
- * need to do to access data when the kernel is running at an address
- * that is different from the address that the kernel is linked at.
- * The reloc_offset() function returns the difference between these
- * two addresses and the macros simplify the process of adding or
- * subtracting this offset to/from pointer values.
- */
-extern unsigned long reloc_offset(void);
-extern unsigned long add_reloc_offset(unsigned long);
-extern unsigned long sub_reloc_offset(unsigned long);
-
-#define PTRRELOC(x)     ((typeof(x))add_reloc_offset((unsigned long)(x)))
-#define PTRUNRELOC(x)   ((typeof(x))sub_reloc_offset((unsigned long)(x)))
-
-/*
- * Fallback definitions since we don't support OF in arch/ppc any more.
- */
-#define machine_is_compatible(x)                0
-#define of_find_compatible_node(f, t, c)        NULL
-#define of_get_property(p, n, l)                NULL
-
-#endif /* _PPC_PROM_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h
deleted file mode 100644
index 66f52cc0a03c..000000000000
--- a/include/asm-ppc/raven.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  include/asm-ppc/raven.h -- Raven MPIC chip.
- *
- *  Copyright (C) 1998 Johnnie Peters
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifdef __KERNEL__
-#ifndef _ASMPPC_RAVEN_H
-#define _ASMPPC_RAVEN_H
-
-#define MVME2600_INT_SIO                0
-#define MVME2600_INT_FALCN_ECC_ERR      1
-#define MVME2600_INT_PCI_ETHERNET       2
-#define MVME2600_INT_PCI_SCSI           3
-#define MVME2600_INT_PCI_GRAPHICS       4
-#define MVME2600_INT_PCI_VME0           5
-#define MVME2600_INT_PCI_VME1           6
-#define MVME2600_INT_PCI_VME2           7
-#define MVME2600_INT_PCI_VME3           8
-#define MVME2600_INT_PCI_INTA           9
-#define MVME2600_INT_PCI_INTB           10
-#define MVME2600_INT_PCI_INTC           11
-#define MVME2600_INT_PCI_INTD           12
-#define MVME2600_INT_LM_SIG0            13
-#define MVME2600_INT_LM_SIG1            14
-
-extern struct hw_interrupt_type raven_pic;
-
-extern int raven_init(void);
-#endif /* _ASMPPC_RAVEN_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
deleted file mode 100644
index 91e96af88bd8..000000000000
--- a/include/asm-ppc/reg_booke.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * Contains register definitions common to the Book E PowerPC
- * specification.  Notice that while the IBM-40x series of CPUs
- * are not true Book E PowerPCs, they borrowed a number of features
- * before Book E was finalized, and are included here as well.  Unfortunatly,
- * they sometimes used different locations than true Book E CPUs did.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_REG_BOOKE_H__
-#define __ASM_PPC_REG_BOOKE_H__
-
-#ifndef __ASSEMBLY__
-/* Performance Monitor Registers */
-#define mfpmr(rn)       ({unsigned int rval; \
-                        asm volatile("mfpmr %0," __stringify(rn) \
-                                     : "=r" (rval)); rval;})
-#define mtpmr(rn, v)    asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
-#endif /* __ASSEMBLY__ */
-
-/* Freescale Book E Performance Monitor APU Registers */
-#define PMRN_PMC0       0x010   /* Performance Monitor Counter 0 */
-#define PMRN_PMC1       0x011   /* Performance Monitor Counter 1 */
-#define PMRN_PMC2       0x012   /* Performance Monitor Counter 1 */
-#define PMRN_PMC3       0x013   /* Performance Monitor Counter 1 */
-#define PMRN_PMLCA0     0x090   /* PM Local Control A0 */
-#define PMRN_PMLCA1     0x091   /* PM Local Control A1 */
-#define PMRN_PMLCA2     0x092   /* PM Local Control A2 */
-#define PMRN_PMLCA3     0x093   /* PM Local Control A3 */
-
-#define PMLCA_FC        0x80000000      /* Freeze Counter */
-#define PMLCA_FCS       0x40000000      /* Freeze in Supervisor */
-#define PMLCA_FCU       0x20000000      /* Freeze in User */
-#define PMLCA_FCM1      0x10000000      /* Freeze when PMM==1 */
-#define PMLCA_FCM0      0x08000000      /* Freeze when PMM==0 */
-#define PMLCA_CE        0x04000000      /* Condition Enable */
-
-#define PMLCA_EVENT_MASK 0x007f0000     /* Event field */
-#define PMLCA_EVENT_SHIFT       16
-
-#define PMRN_PMLCB0     0x110   /* PM Local Control B0 */
-#define PMRN_PMLCB1     0x111   /* PM Local Control B1 */
-#define PMRN_PMLCB2     0x112   /* PM Local Control B2 */
-#define PMRN_PMLCB3     0x113   /* PM Local Control B3 */
-
-#define PMLCB_THRESHMUL_MASK    0x0700  /* Threshhold Multiple Field */
-#define PMLCB_THRESHMUL_SHIFT   8
-
-#define PMLCB_THRESHOLD_MASK    0x003f  /* Threshold Field */
-#define PMLCB_THRESHOLD_SHIFT   0
-
-#define PMRN_PMGC0      0x190   /* PM Global Control 0 */
-
-#define PMGC0_FAC       0x80000000      /* Freeze all Counters */
-#define PMGC0_PMIE      0x40000000      /* Interrupt Enable */
-#define PMGC0_FCECE     0x20000000      /* Freeze countes on
-                                           Enabled Condition or
-                                           Event */
-
-#define PMRN_UPMC0      0x000   /* User Performance Monitor Counter 0 */
-#define PMRN_UPMC1      0x001   /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC2      0x002   /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC3      0x003   /* User Performance Monitor Counter 1 */
-#define PMRN_UPMLCA0    0x080   /* User PM Local Control A0 */
-#define PMRN_UPMLCA1    0x081   /* User PM Local Control A1 */
-#define PMRN_UPMLCA2    0x082   /* User PM Local Control A2 */
-#define PMRN_UPMLCA3    0x083   /* User PM Local Control A3 */
-#define PMRN_UPMLCB0    0x100   /* User PM Local Control B0 */
-#define PMRN_UPMLCB1    0x101   /* User PM Local Control B1 */
-#define PMRN_UPMLCB2    0x102   /* User PM Local Control B2 */
-#define PMRN_UPMLCB3    0x103   /* User PM Local Control B3 */
-#define PMRN_UPMGC0     0x180   /* User PM Global Control 0 */
-
-
-/* Machine State Register (MSR) Fields */
-#define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
-#define MSR_SPE         (1<<25) /* Enable SPE */
-#define MSR_DWE         (1<<10) /* Debug Wait Enable */
-#define MSR_UBLE        (1<<10) /* BTB lock enable (e500) */
-#define MSR_IS          MSR_IR  /* Instruction Space */
-#define MSR_DS          MSR_DR  /* Data Space */
-#define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
-
-/* Default MSR for kernel mode. */
-#if defined (CONFIG_40x)
-#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#elif defined(CONFIG_BOOKE)
-#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
-#endif
-
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
-#define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
-#define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R     0x107   /* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W     0x114   /* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
-#define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
-#define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
-#define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
-#define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
-#define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
-#define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3      0x193   /* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4      0x194   /* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5      0x195   /* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6      0x196   /* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7      0x197   /* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8      0x198   /* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9      0x199   /* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10     0x19A   /* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11     0x19B   /* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12     0x19C   /* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13     0x19D   /* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14     0x19E   /* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15     0x19F   /* Interrupt Vector Offset Register 15 */
-#define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
-#define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
-#define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34     0x212   /* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35     0x213   /* Interrupt Vector Offset Register 35 */
-#define SPRN_MCSRR0     0x23A   /* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1     0x23B   /* Machine Check Save and Restore Register 1 */
-#define SPRN_MCSR       0x23C   /* Machine Check Status Register */
-#define SPRN_MCAR       0x23D   /* Machine Check Address Register */
-#define SPRN_DSRR0      0x23E   /* Debug Save and Restore Register 0 */
-#define SPRN_DSRR1      0x23F   /* Debug Save and Restore Register 1 */
-#define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
-#define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
-#define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
-#define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
-#define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
-#define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
-#define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
-#define SPRN_MAS7       0x3b0   /* MMU Assist Register 7 */
-#define SPRN_PID1       0x279   /* Process ID Register 1 */
-#define SPRN_PID2       0x27A   /* Process ID Register 2 */
-#define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
-#define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
-#define SPRN_CCR1       0x378   /* Core Configuration Register 1 */
-#define SPRN_ZPR        0x3B0   /* Zone Protection Register (40x) */
-#define SPRN_MMUCR      0x3B2   /* MMU Control Register */
-#define SPRN_CCR0       0x3B3   /* Core Configuration Register 0 */
-#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
-#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
-#define SPRN_SLER       0x3BB   /* Little-endian real mode */
-#define SPRN_SU0R       0x3BC   /* "User 0" real mode (40x) */
-#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
-#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
-#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
-#define SPRN_L1CSR0     0x3F2   /* L1 Cache Control and Status Register 0 */
-#define SPRN_L1CSR1     0x3F3   /* L1 Cache Control and Status Register 1 */
-#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
-#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
-#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
-#define SPRN_SVR        0x3FF   /* System Version Register */
-
-/*
- * SPRs which have conflicting definitions on true Book E versus classic,
- * or IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define SPRN_PID        0x030   /* Process ID */
-#define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
-#define SPRN_CSRR0      0x03A   /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1      0x03B   /* Critical Save and Restore Register 1 */
-#define SPRN_DEAR       0x03D   /* Data Error Address Register */
-#define SPRN_ESR        0x03E   /* Exception Syndrome Register */
-#define SPRN_PIR        0x11E   /* Processor Identification Register */
-#define SPRN_DBSR       0x130   /* Debug Status Register */
-#define SPRN_DBCR0      0x134   /* Debug Control Register 0 */
-#define SPRN_DBCR1      0x135   /* Debug Control Register 1 */
-#define SPRN_IAC1       0x138   /* Instruction Address Compare 1 */
-#define SPRN_IAC2       0x139   /* Instruction Address Compare 2 */
-#define SPRN_DAC1       0x13C   /* Data Address Compare 1 */
-#define SPRN_DAC2       0x13D   /* Data Address Compare 2 */
-#define SPRN_TSR        0x150   /* Timer Status Register */
-#define SPRN_TCR        0x154   /* Timer Control Register */
-#endif /* Book E */
-#ifdef CONFIG_40x
-#define SPRN_PID        0x3B1   /* Process ID */
-#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */          
-#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
-#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
-#define SPRN_TSR        0x3D8   /* Timer Status Register */
-#define SPRN_TCR        0x3DA   /* Timer Control Register */
-#define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
-#define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
-#define SPRN_DBSR       0x3F0   /* Debug Status Register */             
-#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
-#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
-#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
-#define SPRN_CSRR0      SPRN_SRR2 /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
-#endif
-
-/* Bit definitions for CCR1. */
-#define CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
-#define CCR1_TCS        0x00000080 /* Timer Clock Select */
-
-/* Bit definitions for the MCSR. */
-#ifdef CONFIG_4xx
-#define MCSR_MCS        0x80000000 /* Machine Check Summary */
-#define MCSR_IB         0x40000000 /* Instruction PLB Error */
-#define MCSR_DRB        0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB        0x10000000 /* Data Write PLB Error */
-#define MCSR_TLBP       0x08000000 /* TLB Parity Error */
-#define MCSR_ICP        0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP       0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
-#endif
-
-/* Bit definitions for the DBSR. */
-/*
- * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define DBSR_IC         0x08000000      /* Instruction Completion */
-#define DBSR_BT         0x04000000      /* Branch Taken */
-#define DBSR_TIE        0x01000000      /* Trap Instruction Event */
-#define DBSR_IAC1       0x00800000      /* Instr Address Compare 1 Event */
-#define DBSR_IAC2       0x00400000      /* Instr Address Compare 2 Event */
-#define DBSR_IAC3       0x00200000      /* Instr Address Compare 3 Event */
-#define DBSR_IAC4       0x00100000      /* Instr Address Compare 4 Event */
-#define DBSR_DAC1R      0x00080000      /* Data Addr Compare 1 Read Event */
-#define DBSR_DAC1W      0x00040000      /* Data Addr Compare 1 Write Event */
-#define DBSR_DAC2R      0x00020000      /* Data Addr Compare 2 Read Event */
-#define DBSR_DAC2W      0x00010000      /* Data Addr Compare 2 Write Event */
-#endif
-#ifdef CONFIG_40x
-#define DBSR_IC         0x80000000      /* Instruction Completion */
-#define DBSR_BT         0x40000000      /* Branch taken */
-#define DBSR_TIE        0x10000000      /* Trap Instruction debug Event */
-#define DBSR_IAC1       0x04000000      /* Instruction Address Compare 1 Event */
-#define DBSR_IAC2       0x02000000      /* Instruction Address Compare 2 Event */
-#define DBSR_IAC3       0x00080000      /* Instruction Address Compare 3 Event */
-#define DBSR_IAC4       0x00040000      /* Instruction Address Compare 4 Event */
-#define DBSR_DAC1R      0x01000000      /* Data Address Compare 1 Read Event */
-#define DBSR_DAC1W      0x00800000      /* Data Address Compare 1 Write Event */
-#define DBSR_DAC2R      0x00400000      /* Data Address Compare 2 Read Event */
-#define DBSR_DAC2W      0x00200000      /* Data Address Compare 2 Write Event */
-#endif
-
-/* Bit definitions related to the ESR. */
-#define ESR_MCI         0x80000000      /* Machine Check - Instruction */
-#define ESR_IMCP        0x80000000      /* Instr. Machine Check - Protection */
-#define ESR_IMCN        0x40000000      /* Instr. Machine Check - Non-config */
-#define ESR_IMCB        0x20000000      /* Instr. Machine Check - Bus error */
-#define ESR_IMCT        0x10000000      /* Instr. Machine Check - Timeout */
-#define ESR_PIL         0x08000000      /* Program Exception - Illegal */
-#define ESR_PPR         0x04000000      /* Program Exception - Privileged */
-#define ESR_PTR         0x02000000      /* Program Exception - Trap */
-#define ESR_FP          0x01000000      /* Floating Point Operation */
-#define ESR_DST         0x00800000      /* Storage Exception - Data miss */
-#define ESR_DIZ         0x00400000      /* Storage Exception - Zone fault */
-#define ESR_ST          0x00800000      /* Store Operation */
-#define ESR_DLK         0x00200000      /* Data Cache Locking */
-#define ESR_ILK         0x00100000      /* Instr. Cache Locking */
-#define ESR_PUO         0x00040000      /* Unimplemented Operation exception */
-#define ESR_BO          0x00020000      /* Byte Ordering */
-
-/* Bit definitions related to the DBCR0. */
-#define DBCR0_EDM       0x80000000      /* External Debug Mode */
-#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
-#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
-#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
-#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
-#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
-#define DBCR0_RST_NONE  0x00000000      /* No Reset */
-#define DBCR0_IC        0x08000000      /* Instruction Completion */
-#define DBCR0_BT        0x04000000      /* Branch Taken */
-#define DBCR0_EDE       0x02000000      /* Exception Debug Event */
-#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
-#define DBCR0_IA1       0x00800000      /* Instr Addr compare 1 enable */
-#define DBCR0_IA2       0x00400000      /* Instr Addr compare 2 enable */
-#define DBCR0_IA12      0x00200000      /* Instr Addr 1-2 range enable */
-#define DBCR0_IA12X     0x00100000      /* Instr Addr 1-2 range eXclusive */
-#define DBCR0_IA3       0x00080000      /* Instr Addr compare 3 enable */
-#define DBCR0_IA4       0x00040000      /* Instr Addr compare 4 enable */
-#define DBCR0_IA34      0x00020000      /* Instr Addr 3-4 range Enable */
-#define DBCR0_IA34X     0x00010000      /* Instr Addr 3-4 range eXclusive */
-#define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
-#define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
-#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
-
-/* Bit definitions related to the TCR. */
-#define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
-#define TCR_WP_MASK     TCR_WP(3)
-#define WP_2_17         0               /* 2^17 clocks */
-#define WP_2_21         1               /* 2^21 clocks */
-#define WP_2_25         2               /* 2^25 clocks */
-#define WP_2_29         3               /* 2^29 clocks */
-#define TCR_WRC(x)      (((x)&0x3)<<28) /* WDT Reset Control */
-#define TCR_WRC_MASK    TCR_WRC(3)
-#define WRC_NONE        0               /* No reset will occur */
-#define WRC_CORE        1               /* Core reset will occur */
-#define WRC_CHIP        2               /* Chip reset will occur */
-#define WRC_SYSTEM      3               /* System reset will occur */
-#define TCR_WIE         0x08000000      /* WDT Interrupt Enable */
-#define TCR_PIE         0x04000000      /* PIT Interrupt Enable */
-#define TCR_DIE         TCR_PIE         /* DEC Interrupt Enable */
-#define TCR_FP(x)       (((x)&0x3)<<24) /* FIT Period */
-#define TCR_FP_MASK     TCR_FP(3)
-#define FP_2_9          0               /* 2^9 clocks */
-#define FP_2_13         1               /* 2^13 clocks */
-#define FP_2_17         2               /* 2^17 clocks */
-#define FP_2_21         3               /* 2^21 clocks */
-#define TCR_FIE         0x00800000      /* FIT Interrupt Enable */
-#define TCR_ARE         0x00400000      /* Auto Reload Enable */
-
-/* Bit definitions for the TSR. */
-#define TSR_ENW         0x80000000      /* Enable Next Watchdog */
-#define TSR_WIS         0x40000000      /* WDT Interrupt Status */
-#define TSR_WRS(x)      (((x)&0x3)<<28) /* WDT Reset Status */
-#define WRS_NONE        0               /* No WDT reset occurred */
-#define WRS_CORE        1               /* WDT forced core reset */
-#define WRS_CHIP        2               /* WDT forced chip reset */
-#define WRS_SYSTEM      3               /* WDT forced system reset */
-#define TSR_PIS         0x08000000      /* PIT Interrupt Status */
-#define TSR_DIS         TSR_PIS         /* DEC Interrupt Status */
-#define TSR_FIS         0x04000000      /* FIT Interrupt Status */
-
-/* Bit definitions for the DCCR. */
-#define DCCR_NOCACHE    0               /* Noncacheable */
-#define DCCR_CACHE      1               /* Cacheable */
-
-/* Bit definitions for DCWR. */
-#define DCWR_COPY       0               /* Copy-back */
-#define DCWR_WRITE      1               /* Write-through */
-
-/* Bit definitions for ICCR. */
-#define ICCR_NOCACHE    0               /* Noncacheable */
-#define ICCR_CACHE      1               /* Cacheable */
-
-/* Bit definitions for L1CSR0. */
-#define L1CSR0_CLFC     0x00000100      /* Cache Lock Bits Flash Clear */
-#define L1CSR0_DCFI     0x00000002      /* Data Cache Flash Invalidate */
-#define L1CSR0_CFI      0x00000002      /* Cache Flash Invalidate */
-#define L1CSR0_DCE      0x00000001      /* Data Cache Enable */
-
-/* Bit definitions for L1CSR1. */
-#define L1CSR1_ICLFR    0x00000100      /* Instr Cache Lock Bits Flash Reset */
-#define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
-#define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
-
-/* Bit definitions for SGR. */
-#define SGR_NORMAL      0               /* Speculative fetching allowed. */
-#define SGR_GUARDED     1               /* Speculative fetching disallowed. */
-
-/* Bit definitions for SPEFSCR. */
-#define SPEFSCR_SOVH    0x80000000      /* Summary integer overflow high */
-#define SPEFSCR_OVH     0x40000000      /* Integer overflow high */
-#define SPEFSCR_FGH     0x20000000      /* Embedded FP guard bit high */
-#define SPEFSCR_FXH     0x10000000      /* Embedded FP sticky bit high */
-#define SPEFSCR_FINVH   0x08000000      /* Embedded FP invalid operation high */
-#define SPEFSCR_FDBZH   0x04000000      /* Embedded FP div by zero high */
-#define SPEFSCR_FUNFH   0x02000000      /* Embedded FP underflow high */
-#define SPEFSCR_FOVFH   0x01000000      /* Embedded FP overflow high */
-#define SPEFSCR_FINXS   0x00200000      /* Embedded FP inexact sticky */
-#define SPEFSCR_FINVS   0x00100000      /* Embedded FP invalid op. sticky */
-#define SPEFSCR_FDBZS   0x00080000      /* Embedded FP div by zero sticky */
-#define SPEFSCR_FUNFS   0x00040000      /* Embedded FP underflow sticky */
-#define SPEFSCR_FOVFS   0x00020000      /* Embedded FP overflow sticky */
-#define SPEFSCR_MODE    0x00010000      /* Embedded FP mode */
-#define SPEFSCR_SOV     0x00008000      /* Integer summary overflow */
-#define SPEFSCR_OV      0x00004000      /* Integer overflow */
-#define SPEFSCR_FG      0x00002000      /* Embedded FP guard bit */
-#define SPEFSCR_FX      0x00001000      /* Embedded FP sticky bit */
-#define SPEFSCR_FINV    0x00000800      /* Embedded FP invalid operation */
-#define SPEFSCR_FDBZ    0x00000400      /* Embedded FP div by zero */
-#define SPEFSCR_FUNF    0x00000200      /* Embedded FP underflow */
-#define SPEFSCR_FOVF    0x00000100      /* Embedded FP overflow */
-#define SPEFSCR_FINXE   0x00000040      /* Embedded FP inexact enable */
-#define SPEFSCR_FINVE   0x00000020      /* Embedded FP invalid op. enable */
-#define SPEFSCR_FDBZE   0x00000010      /* Embedded FP div by zero enable */
-#define SPEFSCR_FUNFE   0x00000008      /* Embedded FP underflow enable */
-#define SPEFSCR_FOVFE   0x00000004      /* Embedded FP overflow enable */
-#define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
-
-/*
- * The IBM-403 is an even more odd special case, as it is much
- * older than the IBM-405 series.  We put these down here incase someone
- * wishes to support these machines again.
- */
-#ifdef CONFIG_403GCX
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_TBHU       0x3CC   /* Time Base High User-mode */
-#define SPRN_TBLU       0x3CD   /* Time Base Low User-mode */
-#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
-#define SPRN_TBHI       0x3DC   /* Time Base High */
-#define SPRN_TBLO       0x3DD   /* Time Base Low */
-#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
-#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
-#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
-#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
-#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
-
-
-/* Bit definitions for the DBCR. */
-#define DBCR_EDM        DBCR0_EDM
-#define DBCR_IDM        DBCR0_IDM
-#define DBCR_RST(x)     (((x) & 0x3) << 28)
-#define DBCR_RST_NONE   0
-#define DBCR_RST_CORE   1
-#define DBCR_RST_CHIP   2
-#define DBCR_RST_SYSTEM 3
-#define DBCR_IC         DBCR0_IC        /* Instruction Completion Debug Evnt */
-#define DBCR_BT         DBCR0_BT        /* Branch Taken Debug Event */
-#define DBCR_EDE        DBCR0_EDE       /* Exception Debug Event */
-#define DBCR_TDE        DBCR0_TDE       /* TRAP Debug Event */
-#define DBCR_FER        0x00F80000      /* First Events Remaining Mask */
-#define DBCR_FT         0x00040000      /* Freeze Timers on Debug Event */
-#define DBCR_IA1        0x00020000      /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2        0x00010000      /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R        0x00008000      /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W        0x00004000      /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x)     (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
-#define DAC_BYTE        0
-#define DAC_HALF        1
-#define DAC_WORD        2
-#define DAC_QUAD        3
-#define DBCR_D2R        0x00000800      /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W        0x00000400      /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x)     (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
-#define DBCR_SBT        0x00000040      /* Second Branch Taken Debug Event */
-#define DBCR_SED        0x00000020      /* Second Exception Debug Event */
-#define DBCR_STD        0x00000010      /* Second Trap Debug Event */
-#define DBCR_SIA        0x00000008      /* Second IAC Enable */
-#define DBCR_SDA        0x00000004      /* Second DAC Enable */
-#define DBCR_JOI        0x00000002      /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII        0x00000001      /* JTAG Serial Inbound Int. Enable */
-#endif /* 403GCX */
-#endif /* __ASM_PPC_REG_BOOKE_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h
deleted file mode 100644
index 934810d25667..000000000000
--- a/include/asm-ppc/residual.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* 7/18/95                                                                    */
-/*----------------------------------------------------------------------------*/
-/*      Residual Data header definitions and prototypes                       */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
-/* residual.h - Residual data structure passed in r3.                         */
-/*              Load point passed in r4 to boot image.                        */
-/* For enum's: if given in hex then they are bit significant,                 */
-/*             i.e. only one bit is on for each enum                          */
-/* Reserved fields must be filled with zeros.                                */
-
-#ifdef __KERNEL__
-#ifndef _RESIDUAL_
-#define _RESIDUAL_
-
-#ifndef __ASSEMBLY__
-
-#define MAX_CPUS 32                     /* These should be set to the maximum */
-#define MAX_MEMS 64                     /* number possible for this system.   */
-#define MAX_DEVICES 256                 /* Changing these will change the     */
-#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
-#define MAX_MEM_SEGS 64                 /* this header file.                  */
-
-/*----------------------------------------------------------------------------*/
-/*               Public structures...                                         */
-/*----------------------------------------------------------------------------*/
-
-#include <asm/pnp.h>
-
-typedef enum _L1CACHE_TYPE {
-  NoneCAC = 0,
-  SplitCAC = 1,
-  CombinedCAC = 2
-  } L1CACHE_TYPE;
-
-typedef enum _TLB_TYPE {
-  NoneTLB = 0,
-  SplitTLB = 1,
-  CombinedTLB = 2
-  } TLB_TYPE;
-
-typedef enum _FIRMWARE_SUPPORT {
-  Conventional = 0x01,
-  OpenFirmware = 0x02,
-  Diagnostics = 0x04,
-  LowDebug = 0x08,
-  Multiboot = 0x10,
-  LowClient = 0x20,
-  Hex41 = 0x40,
-  FAT = 0x80,
-  ISO9660 = 0x0100,
-  SCSI_InitiatorID_Override = 0x0200,
-  Tape_Boot = 0x0400,
-  FW_Boot_Path = 0x0800
-  } FIRMWARE_SUPPORT;
-
-typedef enum _FIRMWARE_SUPPLIERS {
-  IBMFirmware = 0x00,
-  MotoFirmware = 0x01,                  /* 7/18/95                            */
-  FirmWorks = 0x02,                     /* 10/5/95                            */
-  Bull = 0x03,                          /* 04/03/96                           */
-  } FIRMWARE_SUPPLIERS;
-
-typedef enum _ENDIAN_SWITCH_METHODS {
-  UsePort92 = 0x01,
-  UsePCIConfigA8 = 0x02,
-  UseFF001030 = 0x03,
-  } ENDIAN_SWITCH_METHODS;
-
-typedef enum _SPREAD_IO_METHODS {
-  UsePort850 = 0x00,
-/*UsePCIConfigA8 = 0x02,*/
-  } SPREAD_IO_METHODS;
-
-typedef struct _VPD {
-
-  /* Box dependent stuff */
-  unsigned char PrintableModel[32];     /* Null terminated string.
-                                           Must be of the form:
-                                           vvv,<20h>,<model designation>,<0x0>
-                                           where vvv is the vendor ID
-                                           e.g. IBM PPS MODEL 6015<0x0>       */
-  unsigned char Serial[16];             /* 12/94:
-                                           Serial Number; must be of the form:
-                                           vvv<serial number> where vvv is the
-                                           vendor ID.
-                                           e.g. IBM60151234567<20h><20h>      */
-  unsigned char Reserved[48];
-  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
-  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
-  unsigned long NvramSize;              /* Size of nvram in bytes             */
-  unsigned long NumSIMMSlots;
-  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
-  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
-  unsigned long SmpIar;
-  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
-  unsigned long Reserved5;
-  unsigned long Reserved6;
-  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
-  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
-  unsigned long Reserved7;
-  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
-  unsigned long WordWidth;              /* Word width in bits                 */
-  unsigned long PageSize;               /* Page size in bytes                 */
-  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
-                                           for which coherency is maintained;
-                                           normally <= CacheLineSize.         */
-  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
-                                        /*   false sharing of locks.          */
-
-  /* L1 Cache variables */
-  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
-                                        /*   total size of the L1, whether    */
-                                        /*   combined or split                */
-  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
-  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
-                                           for combined cache. If split, put
-                                           zeros here.                        */
-  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
-                                           for combined cache. If split, put
-                                           zeros here.                        */
-  /* For split L1 Cache: (= combined if combined cache) */
-  unsigned long I_CacheSize;
-  unsigned long I_CacheAssoc;
-  unsigned long I_CacheLineSize;
-  unsigned long D_CacheSize;
-  unsigned long D_CacheAssoc;
-  unsigned long D_CacheLineSize;
-
-  /* Translation Lookaside Buffer variables */
-  unsigned long TLBSize;                /* Total number of TLBs on the system */
-  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
-  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
-                                           combined TLB. If split, put zeros
-                                           here.                              */
-  /* For split TLB: (= combined if combined TLB) */
-  unsigned long I_TLBSize;
-  unsigned long I_TLBAssoc;
-  unsigned long D_TLBSize;
-  unsigned long D_TLBAssoc;
-
-  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
-                                           null if unused                     */
-  } VPD;
-
-typedef enum _DEVICE_FLAGS {
-  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
-  Integrated = 0x2000,
-  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
-  Static = 0x0800,                      /* 0 - dynamically configurable
-                                           1 - static                         */
-  Dock = 0x0400,                        /* 0 - not a docking station device
-                                           1 - is a docking station device    */
-  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
-                                           1 - can be a BOOT device           */
-  Configurable = 0x0100,                /* 1 - device is configurable         */
-  Disableable = 0x80,                   /* 1 - device can be disabled         */
-  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
-  ReadOnly = 0x20,                      /* 1 - device is read only            */
-  Removable = 0x10,                     /* 1 - device is removable            */
-  ConsoleIn = 0x08,
-  ConsoleOut = 0x04,
-  Input = 0x02,
-  Output = 0x01
-  } DEVICE_FLAGS;
-
-typedef enum _BUS_ID {
-  ISADEVICE = 0x01,
-  EISADEVICE = 0x02,
-  PCIDEVICE = 0x04,
-  PCMCIADEVICE = 0x08,
-  PNPISADEVICE = 0x10,
-  MCADEVICE = 0x20,
-  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
-  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
-  VMEDEVICE = 0x100,
-  } BUS_ID;
-
-typedef struct _DEVICE_ID {
-  unsigned long BusId;                  /* See BUS_ID enum above              */
-  unsigned long DevId;                  /* Big Endian format                  */
-  unsigned long SerialNum;              /* For multiple usage of a single
-                                           DevId                              */
-  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
-  unsigned char BaseType;               /* See pnp.h for bit definitions      */
-  unsigned char SubType;                /* See pnp.h for bit definitions      */
-  unsigned char Interface;              /* See pnp.h for bit definitions      */
-  unsigned char Spare;
-  } DEVICE_ID;
-
-typedef union _BUS_ACCESS {
-  struct _PnPAccess{
-    unsigned char CSN;
-    unsigned char LogicalDevNumber;
-    unsigned short ReadDataPort;
-    } PnPAccess;
-  struct _ISAAccess{
-    unsigned char SlotNumber;           /* ISA Slot Number generally not
-                                           available; 0 if unknown            */
-    unsigned char LogicalDevNumber;
-    unsigned short ISAReserved;
-    } ISAAccess;
-  struct _MCAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short MCAReserved;
-    } MCAAccess;
-  struct _PCMCIAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short PCMCIAReserved;
-    } PCMCIAAccess;
-  struct _EISAAccess{
-    unsigned char SlotNumber;
-    unsigned char FunctionNumber;
-    unsigned short EISAReserved;
-    } EISAAccess;
-  struct _PCIAccess{
-    unsigned char BusNumber;
-    unsigned char DevFuncNumber;
-    unsigned short PCIReserved;
-    } PCIAccess;
-  struct _ProcBusAccess{
-    unsigned char BusNumber;
-    unsigned char BUID;
-    unsigned short ProcBusReserved;
-    } ProcBusAccess;
-  } BUS_ACCESS;
-
-/* Per logical device information */
-typedef struct _PPC_DEVICE {
-  DEVICE_ID DeviceId;
-  BUS_ACCESS BusAccess;
-
-  /* The following three are offsets into the DevicePnPHeap */
-  /* All are in PnP compressed format                       */
-  unsigned long AllocatedOffset;        /* Allocated resource description     */
-  unsigned long PossibleOffset;         /* Possible resource description      */
-  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
-  } PPC_DEVICE;
-
-typedef enum _CPU_STATE {
-  CPU_GOOD = 0,                         /* CPU is present, and active         */
-  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
-  CPU_OFF = 2,                          /* CPU is present, but inactive       */
-  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
-  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
-  } CPU_STATE;
-
-typedef struct _PPC_CPU {
-  unsigned long CpuType;                /* Result of mfspr from Processor
-                                           Version Register (PVR).
-                                           PVR(0-15) = Version (e.g. 601)
-                                           PVR(16-31 = EC Level               */
-  unsigned char CpuNumber;              /* CPU Number for this processor      */
-  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
-  unsigned short Reserved;
-  } PPC_CPU;
-
-typedef struct _PPC_MEM {
-  unsigned long SIMMSize;               /* 0 - absent or bad
-                                           8M, 32M (in MB)                    */
-  } PPC_MEM;
-
-typedef enum _MEM_USAGE {
-  Other = 0x8000,
-  ResumeBlock = 0x4000,                 /* for use by power management        */
-  SystemROM = 0x2000,                   /* Flash memory (populated)           */
-  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
-  IOMemory = 0x0800,
-  SystemIO = 0x0400,
-  SystemRegs = 0x0200,
-  PCIAddr = 0x0100,
-  PCIConfig = 0x80,
-  ISAAddr = 0x40,
-  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
-  Free = 0x10,                          /* Free part of System Memory         */
-  BootImage = 0x08,                     /* BootImage part of System Memory    */
-  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
-  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
-  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
-  } MEM_USAGE;
-
-typedef struct _MEM_MAP {
-  unsigned long Usage;                  /* See MEM_USAGE above                */
-  unsigned long BasePage;               /* Page number measured in 4KB pages  */
-  unsigned long PageCount;              /* Page count measured in 4KB pages   */
-  } MEM_MAP;
-
-typedef struct _RESIDUAL {
-  unsigned long ResidualLength;         /* Length of Residual                 */
-  unsigned char Version;                /* of this data structure             */
-  unsigned char Revision;               /* of this data structure             */
-  unsigned short EC;                    /* of this data structure             */
-  /* VPD */
-  VPD VitalProductData;
-  /* CPU */
-  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
-  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
-                                        /* that there are unpopulated or      */
-                                        /* otherwise unusable cpu locations   */
-  PPC_CPU Cpus[MAX_CPUS];
-  /* Memory */
-  unsigned long TotalMemory;            /* Total amount of memory installed   */
-  unsigned long GoodMemory;             /* Total amount of good memory        */
-  unsigned long ActualNumMemSegs;
-  MEM_MAP Segs[MAX_MEM_SEGS];
-  unsigned long ActualNumMemories;
-  PPC_MEM Memories[MAX_MEMS];
-  /* Devices */
-  unsigned long ActualNumDevices;
-  PPC_DEVICE Devices[MAX_DEVICES];
-  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
-  } RESIDUAL;
-
-
-/*
- * Forward declaration - we can't include <linux/pci.h> because it
- * breaks the boot loader
- */
-struct pci_dev;
-
-extern RESIDUAL *res;
-extern void print_residual_device_info(void);
-extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
-                                        unsigned char * DevID, int BaseType,
-                                        int SubType, int Interface, int n);
-extern int residual_pcidev_irq(struct pci_dev *dev);
-extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern unsigned int residual_isapic_addr(void);
-extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
-                                       int n);
-extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
-                                                    unsigned packet_type,
-                                                    int n);
-extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
-                                                    unsigned packet_type,
-                                                    int n);
-
-#ifdef CONFIG_PREP_RESIDUAL
-#define have_residual_data      (res && res->ResidualLength)
-#else
-#define have_residual_data      0
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _RESIDUAL_ */
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h
deleted file mode 100644
index 6025b46d0a2a..000000000000
--- a/include/asm-ppc/rtc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * include/asm-ppc/rtc.h
- *
- * Author: Tom Rini <trini@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Based on:
- * include/asm-m68k/rtc.h
- *
- * Copyright Richard Zidlicky
- * implementation details for genrtc/q40rtc driver
- *
- * And the old drivers/macintosh/rtc.c which was heavily based on:
- * Linux/SPARC Real Time Clock Driver
- * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
- *
- * With additional work by Paul Mackerras and Franz Sirl.
- */
-
-#ifndef __ASM_RTC_H__
-#define __ASM_RTC_H__
-
-#ifdef __KERNEL__
-
-#include <linux/rtc.h>
-
-#include <asm/machdep.h>
-#include <asm/time.h>
-
-#define RTC_PIE 0x40            /* periodic interrupt enable */
-#define RTC_AIE 0x20            /* alarm interrupt enable */
-#define RTC_UIE 0x10            /* update-finished interrupt enable */
-
-/* some dummy definitions */
-#define RTC_BATT_BAD 0x100      /* battery bad */
-#define RTC_SQWE 0x08           /* enable square-wave output */
-#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
-#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
-#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
-
-static inline unsigned int get_rtc_time(struct rtc_time *time)
-{
-        if (ppc_md.get_rtc_time) {
-                unsigned long nowtime;
-
-                nowtime = (ppc_md.get_rtc_time)();
-
-                to_tm(nowtime, time);
-
-                time->tm_year -= 1900;
-                time->tm_mon -= 1; /* Make sure userland has a 0-based month */
-        }
-        return RTC_24H;
-}
-
-/* Set the current date and time in the real time clock. */
-static inline int set_rtc_time(struct rtc_time *time)
-{
-        if (ppc_md.get_rtc_time) {
-                unsigned long nowtime;
-
-                nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
-                                time->tm_mday, time->tm_hour, time->tm_min,
-                                time->tm_sec);
-
-                (ppc_md.set_rtc_time)(nowtime);
-
-                return 0;
-        } else
-                return -EINVAL;
-}
-
-static inline unsigned int get_rtc_ss(void)
-{
-        struct rtc_time h;
-
-        get_rtc_time(&h);
-        return h.tm_sec;
-}
-
-static inline int get_rtc_pll(struct rtc_pll_info *pll)
-{
-        return -EINVAL;
-}
-static inline int set_rtc_pll(struct rtc_pll_info *pll)
-{
-        return -EINVAL;
-}
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_RTC_H__ */
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
deleted file mode 100644
index d35ed10315b1..000000000000
--- a/include/asm-ppc/serial.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * include/asm-ppc/serial.h
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_SERIAL_H__
-#define __ASM_SERIAL_H__
-
-
-#if defined(CONFIG_EV64260)
-#include <platforms/ev64260.h>
-#elif defined(CONFIG_CHESTNUT)
-#include <platforms/chestnut.h>
-#elif defined(CONFIG_POWERPMC250)
-#include <platforms/powerpmc250.h>
-#elif defined(CONFIG_LOPEC)
-#include <platforms/lopec.h>
-#elif defined(CONFIG_MVME5100)
-#include <platforms/mvme5100.h>
-#elif defined(CONFIG_PAL4)
-#include <platforms/pal4_serial.h>
-#elif defined(CONFIG_PRPMC750)
-#include <platforms/prpmc750.h>
-#elif defined(CONFIG_PRPMC800)
-#include <platforms/prpmc800.h>
-#elif defined(CONFIG_SANDPOINT)
-#include <platforms/sandpoint.h>
-#elif defined(CONFIG_SPRUCE)
-#include <platforms/spruce.h>
-#elif defined(CONFIG_4xx)
-#include <asm/ibm4xx.h>
-#elif defined(CONFIG_RADSTONE_PPC7D)
-#include <platforms/radstone_ppc7d.h>
-#else
-
-/*
- * XXX Assume it has PC-style ISA serial ports - true for PReP at least.
- */
-#include <asm/pc_serial.h>
-
-#endif /* !CONFIG_GEMINI and others */
-#endif /* __ASM_SERIAL_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
deleted file mode 100644
index e75791ea33a6..000000000000
--- a/include/asm-ppc/smp.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* smp.h: PPC specific SMP stuff.
- *
- * Original was a copy of sparc smp.h.  Now heavily modified
- * for PPC.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
- */
-#ifdef __KERNEL__
-#ifndef _PPC_SMP_H
-#define _PPC_SMP_H
-
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/cpumask.h>
-#include <linux/threads.h>
-
-#ifdef CONFIG_SMP
-
-#ifndef __ASSEMBLY__
-
-struct cpuinfo_PPC {
-        unsigned long loops_per_jiffy;
-        unsigned long pvr;
-        unsigned long *pgd_cache;
-        unsigned long *pte_cache;
-        unsigned long pgtable_cache_sz;
-};
-
-extern struct cpuinfo_PPC cpu_data[];
-extern cpumask_t cpu_online_map;
-extern cpumask_t cpu_possible_map;
-extern unsigned long smp_proc_in_lock[];
-extern volatile unsigned long cpu_callin_map[];
-extern int smp_tb_synchronized;
-extern struct smp_ops_t *smp_ops;
-
-extern void smp_send_tlb_invalidate(int);
-extern void smp_send_xmon_break(int cpu);
-struct pt_regs;
-extern void smp_message_recv(int);
-
-extern int __cpu_disable(void);
-extern void __cpu_die(unsigned int cpu);
-extern void cpu_die(void) __attribute__((noreturn));
-
-#define raw_smp_processor_id()  (current_thread_info()->cpu)
-
-extern int __cpu_up(unsigned int cpu);
-
-extern int smp_hw_index[];
-#define hard_smp_processor_id()         (smp_hw_index[smp_processor_id()])
-#define get_hard_smp_processor_id(cpu)  (smp_hw_index[(cpu)])
-#define set_hard_smp_processor_id(cpu, phys)\
-                                        (smp_hw_index[(cpu)] = (phys))
- 
-#endif /* __ASSEMBLY__ */
-
-#else /* !(CONFIG_SMP) */
-
-static inline void cpu_die(void) { }
-#define get_hard_smp_processor_id(cpu) 0
-#define set_hard_smp_processor_id(cpu, phys)
-#define hard_smp_processor_id() 0
-
-#endif /* !(CONFIG_SMP) */
-
-#ifndef __ASSEMBLY__
-extern int boot_cpuid;
-extern int boot_cpuid_phys;
-#endif
-
-#endif /* !(_PPC_SMP_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
deleted file mode 100644
index fccaf5531e57..000000000000
--- a/include/asm-ppc/spinlock.h
+++ /dev/null
@@ -1,168 +0,0 @@
-#ifndef __ASM_SPINLOCK_H
-#define __ASM_SPINLOCK_H
-
-#include <asm/system.h>
-
-/*
- * Simple spin lock operations.
- *
- * (the type definitions are in asm/raw_spinlock_types.h)
- */
-
-#define __raw_spin_is_locked(x)         ((x)->slock != 0)
-#define __raw_spin_unlock_wait(lock) \
-        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
-        unsigned long tmp;
-
-        __asm__ __volatile__(
-        "b      1f              # __raw_spin_lock\n\
-2:      lwzx    %0,0,%1\n\
-        cmpwi   0,%0,0\n\
-        bne+    2b\n\
-1:      lwarx   %0,0,%1\n\
-        cmpwi   0,%0,0\n\
-        bne-    2b\n"
-        PPC405_ERR77(0,%1)
-"       stwcx.  %2,0,%1\n\
-        bne-    2b\n\
-        isync"
-        : "=&r"(tmp)
-        : "r"(&lock->slock), "r"(1)
-        : "cr0", "memory");
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
-        __asm__ __volatile__("eieio     # __raw_spin_unlock": : :"memory");
-        lock->slock = 0;
-}
-
-#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- */
-
-#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
-#define __raw_write_can_lock(rw)        (!(rw)->lock)
-
-static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
-{
-        signed int tmp;
-
-        __asm__ __volatile__(
-"2:     lwarx   %0,0,%1         # read_trylock\n\
-        addic.  %0,%0,1\n\
-        ble-    1f\n"
-        PPC405_ERR77(0,%1)
-"       stwcx.  %0,0,%1\n\
-        bne-    2b\n\
-        isync\n\
-1:"
-        : "=&r"(tmp)
-        : "r"(&rw->lock)
-        : "cr0", "memory");
-
-        return tmp > 0;
-}
-
-static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
-{
-        signed int tmp;
-
-        __asm__ __volatile__(
-        "b      2f              # read_lock\n\
-1:      lwzx    %0,0,%1\n\
-        cmpwi   0,%0,0\n\
-        blt+    1b\n\
-2:      lwarx   %0,0,%1\n\
-        addic.  %0,%0,1\n\
-        ble-    1b\n"
-        PPC405_ERR77(0,%1)
-"       stwcx.  %0,0,%1\n\
-        bne-    2b\n\
-        isync"
-        : "=&r"(tmp)
-        : "r"(&rw->lock)
-        : "cr0", "memory");
-}
-
-static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
-{
-        signed int tmp;
-
-        __asm__ __volatile__(
-        "eieio                  # read_unlock\n\
-1:      lwarx   %0,0,%1\n\
-        addic   %0,%0,-1\n"
-        PPC405_ERR77(0,%1)
-"       stwcx.  %0,0,%1\n\
-        bne-    1b"
-        : "=&r"(tmp)
-        : "r"(&rw->lock)
-        : "cr0", "memory");
-}
-
-static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
-{
-        signed int tmp;
-
-        __asm__ __volatile__(
-"2:     lwarx   %0,0,%1         # write_trylock\n\
-        cmpwi   0,%0,0\n\
-        bne-    1f\n"
-        PPC405_ERR77(0,%1)
-"       stwcx.  %2,0,%1\n\
-        bne-    2b\n\
-        isync\n\
-1:"
-        : "=&r"(tmp)
-        : "r"(&rw->lock), "r"(-1)
-        : "cr0", "memory");
-
-        return tmp == 0;
-}
-
-static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
-{
-        signed int tmp;
-
-        __asm__ __volatile__(
-        "b      2f              # write_lock\n\
-1:      lwzx    %0,0,%1\n\
-        cmpwi   0,%0,0\n\
-        bne+    1b\n\
-2:      lwarx   %0,0,%1\n\
-        cmpwi   0,%0,0\n\
-        bne-    1b\n"
-        PPC405_ERR77(0,%1)
-"       stwcx.  %2,0,%1\n\
-        bne-    2b\n\
-        isync"
-        : "=&r"(tmp)
-        : "r"(&rw->lock), "r"(-1)
-        : "cr0", "memory");
-}
-
-static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
-{
-        __asm__ __volatile__("eieio             # write_unlock": : :"memory");
-        rw->lock = 0;
-}
-
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
-
-#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h
deleted file mode 100644
index 3df9f32bd834..000000000000
--- a/include/asm-ppc/suspend.h
+++ /dev/null
@@ -1,12 +0,0 @@
-static inline int arch_prepare_suspend(void)
-{
-        return 0;
-}
-
-static inline void save_processor_state(void)
-{
-}
-
-static inline void restore_processor_state(void)
-{
-}
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
deleted file mode 100644
index 70ebd333c55b..000000000000
--- a/include/asm-ppc/system.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef __PPC_SYSTEM_H
-#define __PPC_SYSTEM_H
-
-#include <linux/kernel.h>
-
-#include <asm/hw_irq.h>
-
-/*
- * Memory barrier.
- * The sync instruction guarantees that all memory accesses initiated
- * by this processor have been performed (with respect to all other
- * mechanisms that access memory).  The eieio instruction is a barrier
- * providing an ordering (separately) for (a) cacheable stores and (b)
- * loads and stores to non-cacheable memory (e.g. I/O devices).
- *
- * mb() prevents loads and stores being reordered across this point.
- * rmb() prevents loads being reordered across this point.
- * wmb() prevents stores being reordered across this point.
- * read_barrier_depends() prevents data-dependent loads being reordered
- *      across this point (nop on PPC).
- *
- * We can use the eieio instruction for wmb, but since it doesn't
- * give any ordering guarantees about loads, we have to use the
- * stronger but slower sync instruction for mb and rmb.
- */
-#define mb()  __asm__ __volatile__ ("sync" : : : "memory")
-#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
-#define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
-#define read_barrier_depends()  do { } while(0)
-
-#define set_mb(var, value)      do { var = value; mb(); } while (0)
-
-#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while(0)
-#endif /* CONFIG_SMP */
-
-#ifdef __KERNEL__
-struct task_struct;
-struct pt_regs;
-
-extern void print_backtrace(unsigned long *);
-extern void show_regs(struct pt_regs * regs);
-extern void flush_instruction_cache(void);
-extern void hard_reset_now(void);
-extern void poweroff_now(void);
-extern int set_dabr(unsigned long dabr);
-#ifdef CONFIG_6xx
-extern long _get_L2CR(void);
-extern long _get_L3CR(void);
-extern void _set_L2CR(unsigned long);
-extern void _set_L3CR(unsigned long);
-#else
-#define _get_L2CR()     0L
-#define _get_L3CR()     0L
-#define _set_L2CR(val)  do { } while(0)
-#define _set_L3CR(val)  do { } while(0)
-#endif
-extern void via_cuda_init(void);
-extern void pmac_nvram_init(void);
-extern void chrp_nvram_init(void);
-extern void read_rtc_time(void);
-extern void pmac_find_display(void);
-extern void giveup_fpu(struct task_struct *);
-extern void disable_kernel_fp(void);
-extern void enable_kernel_fp(void);
-extern void flush_fp_to_thread(struct task_struct *);
-extern void enable_kernel_altivec(void);
-extern void giveup_altivec(struct task_struct *);
-extern void load_up_altivec(struct task_struct *);
-extern int emulate_altivec(struct pt_regs *);
-extern void giveup_spe(struct task_struct *);
-extern void load_up_spe(struct task_struct *);
-extern int fix_alignment(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
-extern void cvt_df(double *from, float *to, struct thread_struct *thread);
-
-#ifndef CONFIG_SMP
-extern void discard_lazy_cpu_state(void);
-#else
-static inline void discard_lazy_cpu_state(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ALTIVEC
-extern void flush_altivec_to_thread(struct task_struct *);
-#else
-static inline void flush_altivec_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-#ifdef CONFIG_SPE
-extern void flush_spe_to_thread(struct task_struct *);
-#else
-static inline void flush_spe_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-extern int call_rtas(const char *, int, int, unsigned long *, ...);
-extern void cacheable_memzero(void *p, unsigned int nb);
-extern void *cacheable_memcpy(void *, const void *, unsigned int);
-extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
-extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern int die(const char *, struct pt_regs *, long);
-extern void _exception(int, struct pt_regs *, int, unsigned long);
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-#endif /* CONFIG_BOOKE_WDT */
-
-struct device_node;
-extern void note_scsi_host(struct device_node *, void *);
-
-extern struct task_struct *__switch_to(struct task_struct *,
-        struct task_struct *);
-#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
-
-struct thread_struct;
-extern struct task_struct *_switch(struct thread_struct *prev,
-                                   struct thread_struct *next);
-
-extern unsigned int rtas_data;
-
-static __inline__ unsigned long
-xchg_u32(volatile void *p, unsigned long val)
-{
-        unsigned long prev;
-
-        __asm__ __volatile__ ("\n\
-1:      lwarx   %0,0,%2 \n"
-        PPC405_ERR77(0,%2)
-"       stwcx.  %3,0,%2 \n\
-        bne-    1b"
-        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
-        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
-        : "cc", "memory");
-
-        return prev;
-}
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid xchg().
- */
-extern void __xchg_called_with_bad_pointer(void);
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
-{
-        switch (size) {
-        case 4:
-                return (unsigned long) xchg_u32(ptr, x);
-#if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
-        case 8:
-                return (unsigned long) xchg_u64(ptr, x);
-#endif /* 0 */
-        }
-        __xchg_called_with_bad_pointer();
-        return x;
-
-
-}
-
-static inline void * xchg_ptr(void * m, void * val)
-{
-        return (void *) xchg_u32(m, (unsigned long) val);
-}
-
-
-#define __HAVE_ARCH_CMPXCHG     1
-
-static __inline__ unsigned long
-__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
-{
-        unsigned int prev;
-
-        __asm__ __volatile__ ("\n\
-1:      lwarx   %0,0,%2 \n\
-        cmpw    0,%0,%3 \n\
-        bne     2f \n"
-        PPC405_ERR77(0,%2)
-"       stwcx.  %4,0,%2 \n\
-        bne-    1b\n"
-#ifdef CONFIG_SMP
-"       sync\n"
-#endif /* CONFIG_SMP */
-"2:"
-        : "=&r" (prev), "=m" (*p)
-        : "r" (p), "r" (old), "r" (new), "m" (*p)
-        : "cc", "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u32_local(volatile unsigned int *p, unsigned int old,
-        unsigned int new)
-{
-        unsigned int prev;
-
-        __asm__ __volatile__ ("\n\
-1:      lwarx   %0,0,%2 \n\
-        cmpw    0,%0,%3 \n\
-        bne     2f \n"
-        PPC405_ERR77(0,%2)
-"       stwcx.  %4,0,%2 \n\
-        bne-    1b\n"
-"2:"
-        : "=&r" (prev), "=m" (*p)
-        : "r" (p), "r" (old), "r" (new), "m" (*p)
-        : "cc", "memory");
-
-        return prev;
-}
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid cmpxchg().  */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static __inline__ unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
-        unsigned int size)
-{
-        switch (size) {
-        case 4:
-                return __cmpxchg_u32(ptr, old, new);
-#if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
-        case 8:
-                return __cmpxchg_u64(ptr, old, new);
-#endif /* 0 */
-        }
-        __cmpxchg_called_with_bad_pointer();
-        return old;
-}
-
-#define cmpxchg(ptr, o, n)                                               \
-  ({                                                                     \
-     __typeof__(*(ptr)) _o_ = (o);                                       \
-     __typeof__(*(ptr)) _n_ = (n);                                       \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
-                                    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-                                      unsigned long old,
-                                      unsigned long new, int size)
-{
-        switch (size) {
-        case 4:
-                return __cmpxchg_u32_local(ptr, old, new);
-        default:
-                return __cmpxchg_local_generic(ptr, old, new, size);
-        }
-
-        return old;
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)                                        \
-        ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
-                        (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-#endif /* __PPC_SYSTEM_H */
diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h
deleted file mode 100644
index 81dbcd43a501..000000000000
--- a/include/asm-ppc/time.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Common time prototypes and such for all ppc machines.
- *
- * Written by Cort Dougan (cort@fsmlabs.com) to merge
- * Paul Mackerras' version and mine for PReP and Pmac.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_TIME_H__
-#define __ASM_TIME_H__
-
-#include <linux/types.h>
-#include <linux/rtc.h>
-#include <linux/threads.h>
-
-#include <asm/reg.h>
-
-/* time.c */
-extern unsigned tb_ticks_per_jiffy;
-extern unsigned tb_to_us;
-extern unsigned tb_last_stamp;
-extern unsigned long disarm_decr[NR_CPUS];
-
-extern void to_tm(int tim, struct rtc_time * tm);
-extern time_t last_rtc_update;
-
-extern void set_dec_cpu6(unsigned int val);
-
-int via_calibrate_decr(void);
-
-/* Accessor functions for the decrementer register.
- * The 4xx doesn't even have a decrementer.  I tried to use the
- * generic timer interrupt code, which seems OK, with the 4xx PIT
- * in auto-reload mode.  The problem is PIT stops counting when it
- * hits zero.  If it would wrap, we could use it just like a decrementer.
- */
-static __inline__ unsigned int get_dec(void)
-{
-#if defined(CONFIG_40x)
-        return (mfspr(SPRN_PIT));
-#else
-        return (mfspr(SPRN_DEC));
-#endif
-}
-
-static __inline__ void set_dec(unsigned int val)
-{
-#if defined(CONFIG_40x)
-        return;         /* Have to let it auto-reload */
-#elif defined(CONFIG_8xx_CPU6)
-        set_dec_cpu6(val);
-#else
-        mtspr(SPRN_DEC, val);
-#endif
-}
-
-/* Accessor functions for the timebase (RTC on 601) registers. */
-/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
-#ifdef CONFIG_6xx
-extern __inline__ int __pure __USE_RTC(void) {
-        return (mfspr(SPRN_PVR)>>16) == 1;
-}
-#else
-#define __USE_RTC() 0
-#endif
-
-extern __inline__ unsigned long get_tbl(void) {
-        unsigned long tbl;
-#if defined(CONFIG_403GCX)
-        asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
-#else
-        asm volatile("mftb %0" : "=r" (tbl));
-#endif
-        return tbl;
-}
-
-extern __inline__ unsigned long get_tbu(void) {
-        unsigned long tbl;
-#if defined(CONFIG_403GCX)
-        asm volatile("mfspr %0, 0x3dc" : "=r" (tbl));
-#else
-        asm volatile("mftbu %0" : "=r" (tbl));
-#endif
-        return tbl;
-}
-
-extern __inline__ void set_tb(unsigned int upper, unsigned int lower)
-{
-        mtspr(SPRN_TBWL, 0);
-        mtspr(SPRN_TBWU, upper);
-        mtspr(SPRN_TBWL, lower);
-}
-
-extern __inline__ unsigned long get_rtcl(void) {
-        unsigned long rtcl;
-        asm volatile("mfrtcl %0" : "=r" (rtcl));
-        return rtcl;
-}
-
-extern __inline__ unsigned long get_rtcu(void)
-{
-        unsigned long rtcu;
-        asm volatile("mfrtcu %0" : "=r" (rtcu));
-        return rtcu;
-}
-
-extern __inline__ unsigned get_native_tbl(void) {
-        if (__USE_RTC())
-                return get_rtcl();
-        else
-                return get_tbl();
-}
-
-/* On machines with RTC, this function can only be used safely
- * after the timestamp and for 1 second. It is only used by gettimeofday
- * however so it should not matter.
- */
-extern __inline__ unsigned tb_ticks_since(unsigned tstamp) {
-        if (__USE_RTC()) {
-                int delta = get_rtcl() - tstamp;
-                return delta<0 ? delta + 1000000000 : delta;
-        } else {
-                return get_tbl() - tstamp;
-        }
-}
-
-#if 0
-extern __inline__ unsigned long get_bin_rtcl(void) {
-      unsigned long rtcl, rtcu1, rtcu2;
-      asm volatile("\
-1:    mfrtcu  %0\n\
-      mfrtcl  %1\n\
-      mfrtcu  %2\n\
-      cmpw    %0,%2\n\
-      bne-    1b\n"
-      : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2)
-      : : "cr0");
-      return rtcu2*1000000000+rtcl;
-}
-
-extern __inline__ unsigned binary_tbl(void) {
-      if (__USE_RTC())
-              return get_bin_rtcl();
-      else
-              return get_tbl();
-}
-#endif
-
-/* Use mulhwu to scale processor timebase to timeval */
-/* Specifically, this computes (x * y) / 2^32.  -- paulus */
-#define mulhwu(x,y) \
-({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-
-unsigned mulhwu_scale_factor(unsigned, unsigned);
-
-#define account_process_vtime(tsk)              do { } while (0)
-#define calculate_steal_time()                  do { } while (0)
-#define snapshot_timebases()                    do { } while (0)
-
-#endif /* __ASM_TIME_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h
deleted file mode 100644
index 937c7dbe6e5c..000000000000
--- a/include/asm-ppc/todc.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
- * Clock chips.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
- * Purpose is to make one generic file that handles all of these chips instead
- * of every platform implementing the same code over & over again.
- */
-
-#ifndef __PPC_KERNEL_TODC_H
-#define __PPC_KERNEL_TODC_H
-
-typedef struct {
-        uint rtc_type;          /* your particular chip */
-
-        /*
-         * Following are the addresses of the AS0, AS1, and DATA registers
-         * of these chips.  Note that these are board-specific.
-         */
-        unsigned int nvram_as0;
-        unsigned int nvram_as1;
-        unsigned int nvram_data;
-
-        /*
-         * Define bits to stop external set of regs from changing so
-         * the chip can be read/written reliably.
-         */
-        unsigned char enable_read;
-        unsigned char enable_write;
-
-        /*
-         * Following is the number of AS0 address bits.  This is normally
-         * 8 but some bad hardware routes address lines incorrectly.
-         */
-        int as0_bits;
-
-        int nvram_size; /* Size of NVRAM on chip */
-        int sw_flags;   /* Software control flags */
-
-        /* Following are the register offsets for the particular chip */
-        int year;
-        int month;
-        int day_of_month;
-        int day_of_week;
-        int hours;
-        int minutes;
-        int seconds;
-        int control_b;
-        int control_a;
-        int watchdog;
-        int interrupts;
-        int alarm_date;
-        int alarm_hour;
-        int alarm_minutes;
-        int alarm_seconds;
-        int century;
-        int flags;
-
-        /*
-         * Some RTC chips have their NVRAM buried behind a addr/data pair of
-         * regs on the first level/clock registers.  The following fields
-         * are the addresses for those addr/data regs.
-         */
-        int nvram_addr_reg;
-        int nvram_data_reg;
-} todc_info_t;
-
-/*
- * Define the types of TODC/RTC variants that are supported in
- * arch/ppc/kernel/todc_time.c
- * Make a new one of these for any chip somehow differs from what's already
- * defined.  That way, if you ever need to put in code to touch those
- * bits/registers in todc_time.c, you can put it inside an
- * 'if (todc_info->rtc_type ==  TODC_TYPE_XXX)' so you won't break
- * anyone else.
- */
-#define TODC_TYPE_MK48T35               1
-#define TODC_TYPE_MK48T37               2
-#define TODC_TYPE_MK48T59               3
-#define TODC_TYPE_DS1693                4       /* Dallas DS1693 RTC */
-#define TODC_TYPE_DS1743                5       /* Dallas DS1743 RTC */
-#define TODC_TYPE_DS1746                6       /* Dallas DS1746 RTC */
-#define TODC_TYPE_DS1747                7       /* Dallas DS1747 RTC */
-#define TODC_TYPE_DS1501                8       /* Dallas DS1501 RTC */
-#define TODC_TYPE_DS1643                9       /* Dallas DS1643 RTC */
-#define TODC_TYPE_PC97307               10      /* PC97307 internal RTC */
-#define TODC_TYPE_DS1557                11      /* Dallas DS1557 RTC */
-#define TODC_TYPE_DS17285               12      /* Dallas DS17285 RTC */
-#define TODC_TYPE_DS1553                13      /* Dallas DS1553 RTC */
-#define TODC_TYPE_MC146818              100     /* Leave room for m48txx's */
-
-/*
- * Bit to clear/set to enable reads/writes to the chip
- */
-#define TODC_MK48TXX_CNTL_A_R           0x40
-#define TODC_MK48TXX_CNTL_A_W           0x80
-#define TODC_MK48TXX_DAY_CB             0x80
-
-#define TODC_DS1501_CNTL_B_TE           0x80
-
-/*
- * Define flag bits used by todc routines.
- */
-#define TODC_FLAG_2_LEVEL_NVRAM         0x00000001
-
-/*
- * Define the values for the various RTC's that should to into the todc_info
- * table.
- * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
- * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
- */
-#define TODC_TYPE_MK48T35_NVRAM_SIZE            0x7ff8
-#define TODC_TYPE_MK48T35_SW_FLAGS              0
-#define TODC_TYPE_MK48T35_YEAR                  0x7fff
-#define TODC_TYPE_MK48T35_MONTH                 0x7ffe
-#define TODC_TYPE_MK48T35_DOM                   0x7ffd  /* Day of Month */
-#define TODC_TYPE_MK48T35_DOW                   0x7ffc  /* Day of Week */
-#define TODC_TYPE_MK48T35_HOURS                 0x7ffb
-#define TODC_TYPE_MK48T35_MINUTES               0x7ffa
-#define TODC_TYPE_MK48T35_SECONDS               0x7ff9
-#define TODC_TYPE_MK48T35_CNTL_B                0x7ff9
-#define TODC_TYPE_MK48T35_CNTL_A                0x7ff8
-#define TODC_TYPE_MK48T35_WATCHDOG              0x0000
-#define TODC_TYPE_MK48T35_INTERRUPTS            0x0000
-#define TODC_TYPE_MK48T35_ALARM_DATE            0x0000
-#define TODC_TYPE_MK48T35_ALARM_HOUR            0x0000
-#define TODC_TYPE_MK48T35_ALARM_MINUTES         0x0000
-#define TODC_TYPE_MK48T35_ALARM_SECONDS         0x0000
-#define TODC_TYPE_MK48T35_CENTURY               0x0000
-#define TODC_TYPE_MK48T35_FLAGS                 0x0000
-#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG        0
-#define TODC_TYPE_MK48T35_NVRAM_DATA_REG        0
-
-#define TODC_TYPE_MK48T37_NVRAM_SIZE            0x7ff0
-#define TODC_TYPE_MK48T37_SW_FLAGS              0
-#define TODC_TYPE_MK48T37_YEAR                  0x7fff
-#define TODC_TYPE_MK48T37_MONTH                 0x7ffe
-#define TODC_TYPE_MK48T37_DOM                   0x7ffd  /* Day of Month */
-#define TODC_TYPE_MK48T37_DOW                   0x7ffc  /* Day of Week */
-#define TODC_TYPE_MK48T37_HOURS                 0x7ffb
-#define TODC_TYPE_MK48T37_MINUTES               0x7ffa
-#define TODC_TYPE_MK48T37_SECONDS               0x7ff9
-#define TODC_TYPE_MK48T37_CNTL_B                0x7ff9
-#define TODC_TYPE_MK48T37_CNTL_A                0x7ff8
-#define TODC_TYPE_MK48T37_WATCHDOG              0x7ff7
-#define TODC_TYPE_MK48T37_INTERRUPTS            0x7ff6
-#define TODC_TYPE_MK48T37_ALARM_DATE            0x7ff5
-#define TODC_TYPE_MK48T37_ALARM_HOUR            0x7ff4
-#define TODC_TYPE_MK48T37_ALARM_MINUTES         0x7ff3
-#define TODC_TYPE_MK48T37_ALARM_SECONDS         0x7ff2
-#define TODC_TYPE_MK48T37_CENTURY               0x7ff1
-#define TODC_TYPE_MK48T37_FLAGS                 0x7ff0
-#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG        0
-#define TODC_TYPE_MK48T37_NVRAM_DATA_REG        0
-
-#define TODC_TYPE_MK48T59_NVRAM_SIZE            0x1ff0
-#define TODC_TYPE_MK48T59_SW_FLAGS              0
-#define TODC_TYPE_MK48T59_YEAR                  0x1fff
-#define TODC_TYPE_MK48T59_MONTH                 0x1ffe
-#define TODC_TYPE_MK48T59_DOM                   0x1ffd  /* Day of Month */
-#define TODC_TYPE_MK48T59_DOW                   0x1ffc  /* Day of Week */
-#define TODC_TYPE_MK48T59_HOURS                 0x1ffb
-#define TODC_TYPE_MK48T59_MINUTES               0x1ffa
-#define TODC_TYPE_MK48T59_SECONDS               0x1ff9
-#define TODC_TYPE_MK48T59_CNTL_B                0x1ff9
-#define TODC_TYPE_MK48T59_CNTL_A                0x1ff8
-#define TODC_TYPE_MK48T59_WATCHDOG              0x1fff
-#define TODC_TYPE_MK48T59_INTERRUPTS            0x1fff
-#define TODC_TYPE_MK48T59_ALARM_DATE            0x1fff
-#define TODC_TYPE_MK48T59_ALARM_HOUR            0x1fff
-#define TODC_TYPE_MK48T59_ALARM_MINUTES         0x1fff
-#define TODC_TYPE_MK48T59_ALARM_SECONDS         0x1fff
-#define TODC_TYPE_MK48T59_CENTURY               0x1fff
-#define TODC_TYPE_MK48T59_FLAGS                 0x1fff
-#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG        0
-#define TODC_TYPE_MK48T59_NVRAM_DATA_REG        0
-
-#define TODC_TYPE_DS1501_NVRAM_SIZE     0x100
-#define TODC_TYPE_DS1501_SW_FLAGS       TODC_FLAG_2_LEVEL_NVRAM
-#define TODC_TYPE_DS1501_YEAR           (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
-#define TODC_TYPE_DS1501_MONTH          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
-#define TODC_TYPE_DS1501_DOM            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
-#define TODC_TYPE_DS1501_DOW            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
-#define TODC_TYPE_DS1501_HOURS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
-#define TODC_TYPE_DS1501_MINUTES        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
-#define TODC_TYPE_DS1501_SECONDS        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
-#define TODC_TYPE_DS1501_CNTL_B         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
-#define TODC_TYPE_DS1501_CNTL_A         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
-#define TODC_TYPE_DS1501_WATCHDOG       (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define TODC_TYPE_DS1501_INTERRUPTS     (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define TODC_TYPE_DS1501_ALARM_DATE     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
-#define TODC_TYPE_DS1501_ALARM_HOUR     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
-#define TODC_TYPE_DS1501_ALARM_MINUTES  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
-#define TODC_TYPE_DS1501_ALARM_SECONDS  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
-#define TODC_TYPE_DS1501_CENTURY        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
-#define TODC_TYPE_DS1501_FLAGS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
-#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
-
-#define TODC_TYPE_DS1553_NVRAM_SIZE             0x1ff0
-#define TODC_TYPE_DS1553_SW_FLAGS               0
-#define TODC_TYPE_DS1553_YEAR                   0x1fff
-#define TODC_TYPE_DS1553_MONTH                  0x1ffe
-#define TODC_TYPE_DS1553_DOM                    0x1ffd  /* Day of Month */
-#define TODC_TYPE_DS1553_DOW                    0x1ffc  /* Day of Week */
-#define TODC_TYPE_DS1553_HOURS                  0x1ffb
-#define TODC_TYPE_DS1553_MINUTES                0x1ffa
-#define TODC_TYPE_DS1553_SECONDS                0x1ff9
-#define TODC_TYPE_DS1553_CNTL_B                 0x1ff9
-#define TODC_TYPE_DS1553_CNTL_A                 0x1ff8  /* control_a R/W regs */
-#define TODC_TYPE_DS1553_WATCHDOG               0x1ff7
-#define TODC_TYPE_DS1553_INTERRUPTS             0x1ff6
-#define TODC_TYPE_DS1553_ALARM_DATE             0x1ff5
-#define TODC_TYPE_DS1553_ALARM_HOUR             0x1ff4
-#define TODC_TYPE_DS1553_ALARM_MINUTES          0x1ff3
-#define TODC_TYPE_DS1553_ALARM_SECONDS          0x1ff2
-#define TODC_TYPE_DS1553_CENTURY                0x1ff8
-#define TODC_TYPE_DS1553_FLAGS                  0x1ff0
-#define TODC_TYPE_DS1553_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1553_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS1557_NVRAM_SIZE             0x7fff0
-#define TODC_TYPE_DS1557_SW_FLAGS               0
-#define TODC_TYPE_DS1557_YEAR                   0x7ffff
-#define TODC_TYPE_DS1557_MONTH                  0x7fffe
-#define TODC_TYPE_DS1557_DOM                    0x7fffd /* Day of Month */
-#define TODC_TYPE_DS1557_DOW                    0x7fffc /* Day of Week */
-#define TODC_TYPE_DS1557_HOURS                  0x7fffb
-#define TODC_TYPE_DS1557_MINUTES                0x7fffa
-#define TODC_TYPE_DS1557_SECONDS                0x7fff9
-#define TODC_TYPE_DS1557_CNTL_B                 0x7fff9
-#define TODC_TYPE_DS1557_CNTL_A                 0x7fff8 /* control_a R/W regs */
-#define TODC_TYPE_DS1557_WATCHDOG               0x7fff7
-#define TODC_TYPE_DS1557_INTERRUPTS             0x7fff6
-#define TODC_TYPE_DS1557_ALARM_DATE             0x7fff5
-#define TODC_TYPE_DS1557_ALARM_HOUR             0x7fff4
-#define TODC_TYPE_DS1557_ALARM_MINUTES          0x7fff3
-#define TODC_TYPE_DS1557_ALARM_SECONDS          0x7fff2
-#define TODC_TYPE_DS1557_CENTURY                0x7fff8
-#define TODC_TYPE_DS1557_FLAGS                  0x7fff0
-#define TODC_TYPE_DS1557_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1557_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS1643_NVRAM_SIZE             0x1ff8
-#define TODC_TYPE_DS1643_SW_FLAGS               0
-#define TODC_TYPE_DS1643_YEAR                   0x1fff
-#define TODC_TYPE_DS1643_MONTH                  0x1ffe
-#define TODC_TYPE_DS1643_DOM                    0x1ffd  /* Day of Month */
-#define TODC_TYPE_DS1643_DOW                    0x1ffc  /* Day of Week */
-#define TODC_TYPE_DS1643_HOURS                  0x1ffb
-#define TODC_TYPE_DS1643_MINUTES                0x1ffa
-#define TODC_TYPE_DS1643_SECONDS                0x1ff9
-#define TODC_TYPE_DS1643_CNTL_B                 0x1ff9
-#define TODC_TYPE_DS1643_CNTL_A                 0x1ff8  /* control_a R/W regs */
-#define TODC_TYPE_DS1643_WATCHDOG               0x1fff
-#define TODC_TYPE_DS1643_INTERRUPTS             0x1fff
-#define TODC_TYPE_DS1643_ALARM_DATE             0x1fff
-#define TODC_TYPE_DS1643_ALARM_HOUR             0x1fff
-#define TODC_TYPE_DS1643_ALARM_MINUTES          0x1fff
-#define TODC_TYPE_DS1643_ALARM_SECONDS          0x1fff
-#define TODC_TYPE_DS1643_CENTURY                0x1ff8
-#define TODC_TYPE_DS1643_FLAGS                  0x1fff
-#define TODC_TYPE_DS1643_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1643_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS1693_NVRAM_SIZE             0 /* Not handled yet */
-#define TODC_TYPE_DS1693_SW_FLAGS               0
-#define TODC_TYPE_DS1693_YEAR                   0x09
-#define TODC_TYPE_DS1693_MONTH                  0x08
-#define TODC_TYPE_DS1693_DOM                    0x07    /* Day of Month */
-#define TODC_TYPE_DS1693_DOW                    0x06    /* Day of Week */
-#define TODC_TYPE_DS1693_HOURS                  0x04
-#define TODC_TYPE_DS1693_MINUTES                0x02
-#define TODC_TYPE_DS1693_SECONDS                0x00
-#define TODC_TYPE_DS1693_CNTL_B                 0x0b
-#define TODC_TYPE_DS1693_CNTL_A                 0x0a
-#define TODC_TYPE_DS1693_WATCHDOG               0xff
-#define TODC_TYPE_DS1693_INTERRUPTS             0xff
-#define TODC_TYPE_DS1693_ALARM_DATE             0x49
-#define TODC_TYPE_DS1693_ALARM_HOUR             0x05
-#define TODC_TYPE_DS1693_ALARM_MINUTES          0x03
-#define TODC_TYPE_DS1693_ALARM_SECONDS          0x01
-#define TODC_TYPE_DS1693_CENTURY                0x48
-#define TODC_TYPE_DS1693_FLAGS                  0xff
-#define TODC_TYPE_DS1693_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1693_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS1743_NVRAM_SIZE             0x1ff8
-#define TODC_TYPE_DS1743_SW_FLAGS               0
-#define TODC_TYPE_DS1743_YEAR                   0x1fff
-#define TODC_TYPE_DS1743_MONTH                  0x1ffe
-#define TODC_TYPE_DS1743_DOM                    0x1ffd  /* Day of Month */
-#define TODC_TYPE_DS1743_DOW                    0x1ffc  /* Day of Week */
-#define TODC_TYPE_DS1743_HOURS                  0x1ffb
-#define TODC_TYPE_DS1743_MINUTES                0x1ffa
-#define TODC_TYPE_DS1743_SECONDS                0x1ff9
-#define TODC_TYPE_DS1743_CNTL_B                 0x1ff9
-#define TODC_TYPE_DS1743_CNTL_A                 0x1ff8  /* control_a R/W regs */
-#define TODC_TYPE_DS1743_WATCHDOG               0x1fff
-#define TODC_TYPE_DS1743_INTERRUPTS             0x1fff
-#define TODC_TYPE_DS1743_ALARM_DATE             0x1fff
-#define TODC_TYPE_DS1743_ALARM_HOUR             0x1fff
-#define TODC_TYPE_DS1743_ALARM_MINUTES          0x1fff
-#define TODC_TYPE_DS1743_ALARM_SECONDS          0x1fff
-#define TODC_TYPE_DS1743_CENTURY                0x1ff8
-#define TODC_TYPE_DS1743_FLAGS                  0x1fff
-#define TODC_TYPE_DS1743_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1743_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS1746_NVRAM_SIZE             0x1fff8
-#define TODC_TYPE_DS1746_SW_FLAGS               0
-#define TODC_TYPE_DS1746_YEAR                   0x1ffff
-#define TODC_TYPE_DS1746_MONTH                  0x1fffe
-#define TODC_TYPE_DS1746_DOM                    0x1fffd /* Day of Month */
-#define TODC_TYPE_DS1746_DOW                    0x1fffc /* Day of Week */
-#define TODC_TYPE_DS1746_HOURS                  0x1fffb
-#define TODC_TYPE_DS1746_MINUTES                0x1fffa
-#define TODC_TYPE_DS1746_SECONDS                0x1fff9
-#define TODC_TYPE_DS1746_CNTL_B                 0x1fff9
-#define TODC_TYPE_DS1746_CNTL_A                 0x1fff8 /* control_a R/W regs */
-#define TODC_TYPE_DS1746_WATCHDOG               0x00000
-#define TODC_TYPE_DS1746_INTERRUPTS             0x00000
-#define TODC_TYPE_DS1746_ALARM_DATE             0x00000
-#define TODC_TYPE_DS1746_ALARM_HOUR             0x00000
-#define TODC_TYPE_DS1746_ALARM_MINUTES          0x00000
-#define TODC_TYPE_DS1746_ALARM_SECONDS          0x00000
-#define TODC_TYPE_DS1746_CENTURY                0x00000
-#define TODC_TYPE_DS1746_FLAGS                  0x00000
-#define TODC_TYPE_DS1746_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1746_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS1747_NVRAM_SIZE             0x7fff8
-#define TODC_TYPE_DS1747_SW_FLAGS               0
-#define TODC_TYPE_DS1747_YEAR                   0x7ffff
-#define TODC_TYPE_DS1747_MONTH                  0x7fffe
-#define TODC_TYPE_DS1747_DOM                    0x7fffd /* Day of Month */
-#define TODC_TYPE_DS1747_DOW                    0x7fffc /* Day of Week */
-#define TODC_TYPE_DS1747_HOURS                  0x7fffb
-#define TODC_TYPE_DS1747_MINUTES                0x7fffa
-#define TODC_TYPE_DS1747_SECONDS                0x7fff9
-#define TODC_TYPE_DS1747_CNTL_B                 0x7fff9
-#define TODC_TYPE_DS1747_CNTL_A                 0x7fff8 /* control_a R/W regs */
-#define TODC_TYPE_DS1747_WATCHDOG               0x00000
-#define TODC_TYPE_DS1747_INTERRUPTS             0x00000
-#define TODC_TYPE_DS1747_ALARM_DATE             0x00000
-#define TODC_TYPE_DS1747_ALARM_HOUR             0x00000
-#define TODC_TYPE_DS1747_ALARM_MINUTES          0x00000
-#define TODC_TYPE_DS1747_ALARM_SECONDS          0x00000
-#define TODC_TYPE_DS1747_CENTURY                0x00000
-#define TODC_TYPE_DS1747_FLAGS                  0x00000
-#define TODC_TYPE_DS1747_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1747_NVRAM_DATA_REG         0
-
-#define TODC_TYPE_DS17285_NVRAM_SIZE            (0x1000-0x80)    /* 4Kx8 NVRAM (minus RTC regs) */
-#define TODC_TYPE_DS17285_SW_FLAGS              TODC_FLAG_2_LEVEL_NVRAM
-#define TODC_TYPE_DS17285_SECONDS               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
-#define TODC_TYPE_DS17285_ALARM_SECONDS         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
-#define TODC_TYPE_DS17285_MINUTES               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
-#define TODC_TYPE_DS17285_ALARM_MINUTES         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
-#define TODC_TYPE_DS17285_HOURS                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
-#define TODC_TYPE_DS17285_ALARM_HOUR            (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
-#define TODC_TYPE_DS17285_DOW                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
-#define TODC_TYPE_DS17285_DOM                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
-#define TODC_TYPE_DS17285_MONTH                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
-#define TODC_TYPE_DS17285_YEAR                  (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
-#define TODC_TYPE_DS17285_CNTL_A                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
-#define TODC_TYPE_DS17285_CNTL_B                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
-#define TODC_TYPE_DS17285_CNTL_C                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
-#define TODC_TYPE_DS17285_CNTL_D                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
-#define TODC_TYPE_DS17285_WATCHDOG              0
-#define TODC_TYPE_DS17285_INTERRUPTS            0
-#define TODC_TYPE_DS17285_ALARM_DATE            0
-#define TODC_TYPE_DS17285_CENTURY               0
-#define TODC_TYPE_DS17285_FLAGS                 0
-#define TODC_TYPE_DS17285_NVRAM_ADDR_REG        0x50
-#define TODC_TYPE_DS17285_NVRAM_DATA_REG        0x53
- 
-#define TODC_TYPE_MC146818_NVRAM_SIZE           0       /* XXXX */
-#define TODC_TYPE_MC146818_SW_FLAGS             0
-#define TODC_TYPE_MC146818_YEAR                 0x09
-#define TODC_TYPE_MC146818_MONTH                0x08
-#define TODC_TYPE_MC146818_DOM                  0x07    /* Day of Month */
-#define TODC_TYPE_MC146818_DOW                  0x06    /* Day of Week */
-#define TODC_TYPE_MC146818_HOURS                0x04
-#define TODC_TYPE_MC146818_MINUTES              0x02
-#define TODC_TYPE_MC146818_SECONDS              0x00
-#define TODC_TYPE_MC146818_CNTL_B               0x0a
-#define TODC_TYPE_MC146818_CNTL_A               0x0b    /* control_a R/W regs */
-#define TODC_TYPE_MC146818_WATCHDOG             0
-#define TODC_TYPE_MC146818_INTERRUPTS           0x0c
-#define TODC_TYPE_MC146818_ALARM_DATE           0xff
-#define TODC_TYPE_MC146818_ALARM_HOUR           0x05
-#define TODC_TYPE_MC146818_ALARM_MINUTES        0x03
-#define TODC_TYPE_MC146818_ALARM_SECONDS        0x01
-#define TODC_TYPE_MC146818_CENTURY              0xff
-#define TODC_TYPE_MC146818_FLAGS                0xff
-#define TODC_TYPE_MC146818_NVRAM_ADDR_REG       0
-#define TODC_TYPE_MC146818_NVRAM_DATA_REG       0
-  
-#define TODC_TYPE_PC97307_NVRAM_SIZE            0       /* No NVRAM? */
-#define TODC_TYPE_PC97307_SW_FLAGS              0
-#define TODC_TYPE_PC97307_YEAR                  0x09
-#define TODC_TYPE_PC97307_MONTH                 0x08
-#define TODC_TYPE_PC97307_DOM                   0x07    /* Day of Month */
-#define TODC_TYPE_PC97307_DOW                   0x06    /* Day of Week */
-#define TODC_TYPE_PC97307_HOURS                 0x04
-#define TODC_TYPE_PC97307_MINUTES               0x02
-#define TODC_TYPE_PC97307_SECONDS               0x00
-#define TODC_TYPE_PC97307_CNTL_B                0x0a
-#define TODC_TYPE_PC97307_CNTL_A                0x0b    /* control_a R/W regs */
-#define TODC_TYPE_PC97307_WATCHDOG              0x0c
-#define TODC_TYPE_PC97307_INTERRUPTS            0x0d
-#define TODC_TYPE_PC97307_ALARM_DATE            0xff
-#define TODC_TYPE_PC97307_ALARM_HOUR            0x05
-#define TODC_TYPE_PC97307_ALARM_MINUTES         0x03
-#define TODC_TYPE_PC97307_ALARM_SECONDS         0x01
-#define TODC_TYPE_PC97307_CENTURY               0xff
-#define TODC_TYPE_PC97307_FLAGS                 0xff
-#define TODC_TYPE_PC97307_NVRAM_ADDR_REG        0
-#define TODC_TYPE_PC97307_NVRAM_DATA_REG        0
-
-/*
- * Define macros to allocate and init the todc_info_t table that will
- * be used by the todc_time.c routines.
- */
-#define TODC_ALLOC()                                                    \
-        static todc_info_t todc_info_alloc;                             \
-        todc_info_t *todc_info = &todc_info_alloc;
-
-#define TODC_INIT(clock_type, as0, as1, data, bits) {                   \
-        todc_info->rtc_type = clock_type;                               \
-                                                                        \
-        todc_info->nvram_as0  = (unsigned int)(as0);                    \
-        todc_info->nvram_as1  = (unsigned int)(as1);                    \
-        todc_info->nvram_data = (unsigned int)(data);                   \
-                                                                        \
-        todc_info->as0_bits = (bits);                                   \
-                                                                        \
-        todc_info->nvram_size     = clock_type ##_NVRAM_SIZE;           \
-        todc_info->sw_flags       = clock_type ##_SW_FLAGS;             \
-                                                                        \
-        todc_info->year           = clock_type ##_YEAR;                 \
-        todc_info->month          = clock_type ##_MONTH;                \
-        todc_info->day_of_month   = clock_type ##_DOM;                  \
-        todc_info->day_of_week    = clock_type ##_DOW;                  \
-        todc_info->hours          = clock_type ##_HOURS;                \
-        todc_info->minutes        = clock_type ##_MINUTES;              \
-        todc_info->seconds        = clock_type ##_SECONDS;              \
-        todc_info->control_b      = clock_type ##_CNTL_B;               \
-        todc_info->control_a      = clock_type ##_CNTL_A;               \
-        todc_info->watchdog       = clock_type ##_WATCHDOG;             \
-        todc_info->interrupts     = clock_type ##_INTERRUPTS;           \
-        todc_info->alarm_date     = clock_type ##_ALARM_DATE;           \
-        todc_info->alarm_hour     = clock_type ##_ALARM_HOUR;           \
-        todc_info->alarm_minutes  = clock_type ##_ALARM_MINUTES;        \
-        todc_info->alarm_seconds  = clock_type ##_ALARM_SECONDS;        \
-        todc_info->century        = clock_type ##_CENTURY;              \
-        todc_info->flags          = clock_type ##_FLAGS;                \
-                                                                        \
-        todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;       \
-        todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;       \
-}
-
-extern todc_info_t *todc_info;
-
-unsigned char todc_direct_read_val(int addr);
-void todc_direct_write_val(int addr, unsigned char val);
-unsigned char todc_m48txx_read_val(int addr);
-void todc_m48txx_write_val(int addr, unsigned char val);
-unsigned char todc_mc146818_read_val(int addr);
-void todc_mc146818_write_val(int addr, unsigned char val);
-
-long todc_time_init(void);
-unsigned long todc_get_rtc_time(void);
-int todc_set_rtc_time(unsigned long nowtime);
-void todc_calibrate_decr(void);
-
-#endif                          /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h
deleted file mode 100644
index 68e7326b56f1..000000000000
--- a/include/asm-ppc/traps.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/traps.h>
diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h
deleted file mode 100644
index 1e5fbc65e77b..000000000000
--- a/include/asm-ppc/zorro.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ASM_PPC_ZORRO_H
-#define _ASM_PPC_ZORRO_H
-
-#include <asm/io.h>
-
-#define z_readb in_8
-#define z_readw in_be16
-#define z_readl in_be32
-
-#define z_writeb(val, port) out_8((port), (val))
-#define z_writew(val, port) out_be16((port), (val))
-#define z_writel(val, port) out_be32((port), (val))
-
-#define z_memset_io(a,b,c)      memset((void *)(a),(b),(c))
-#define z_memcpy_fromio(a,b,c)  memcpy((a),(void *)(b),(c))
-#define z_memcpy_toio(a,b,c)    memcpy((void *)(a),(b),(c))
-
-extern void *__ioremap(unsigned long address, unsigned long size,
-                       unsigned long flags);
-
-extern void *ioremap(unsigned long address, unsigned long size);
-extern void iounmap(void *addr);
-
-extern void *__ioremap(unsigned long address, unsigned long size,
-                       unsigned long flags);
-
-#define z_ioremap ioremap
-#define z_iounmap iounmap
-
-#endif /* _ASM_PPC_ZORRO_H */
diff --git a/include/asm-s390/Kbuild b/include/asm-s390/Kbuild
index 13c9805349f1..bb5e9edb9825 100644
--- a/include/asm-s390/Kbuild
+++ b/include/asm-s390/Kbuild
@@ -8,6 +8,9 @@ header-y += ucontext.h
 header-y += vtoc.h
 header-y += zcrypt.h
 header-y += kvm.h
+header-y += chsc.h
 
 unifdef-y += cmb.h
 unifdef-y += debug.h
+unifdef-y += chpid.h
+unifdef-y += schid.h
diff --git a/include/asm-s390/airq.h b/include/asm-s390/airq.h
index 41d028cb52a4..1ac80d6b0588 100644
--- a/include/asm-s390/airq.h
+++ b/include/asm-s390/airq.h
@@ -13,7 +13,7 @@
 
 typedef void (*adapter_int_handler_t)(void *, void *);
 
-void *s390_register_adapter_interrupt(adapter_int_handler_t, void *);
-void s390_unregister_adapter_interrupt(void *);
+void *s390_register_adapter_interrupt(adapter_int_handler_t, void *, u8);
+void s390_unregister_adapter_interrupt(void *, u8);
 
 #endif /* _ASM_S390_AIRQ_H */
diff --git a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h
index 066aa70518ce..ba007d8df941 100644
--- a/include/asm-s390/ccwdev.h
+++ b/include/asm-s390/ccwdev.h
@@ -12,6 +12,7 @@
 
 #include <linux/device.h>
 #include <linux/mod_devicetable.h>
+#include <asm/fcx.h>
 
 /* structs from asm/cio.h */
 struct irb;
@@ -157,6 +158,17 @@ extern int ccw_device_start_timeout_key(struct ccw_device *, struct ccw1 *,
 extern int ccw_device_resume(struct ccw_device *);
 extern int ccw_device_halt(struct ccw_device *, unsigned long);
 extern int ccw_device_clear(struct ccw_device *, unsigned long);
+int ccw_device_tm_start_key(struct ccw_device *cdev, struct tcw *tcw,
+                            unsigned long intparm, u8 lpm, u8 key);
+int ccw_device_tm_start_key(struct ccw_device *, struct tcw *,
+                            unsigned long, u8, u8);
+int ccw_device_tm_start_timeout_key(struct ccw_device *, struct tcw *,
+                            unsigned long, u8, u8, int);
+int ccw_device_tm_start(struct ccw_device *, struct tcw *,
+                            unsigned long, u8);
+int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *,
+                            unsigned long, u8, int);
+int ccw_device_tm_intrg(struct ccw_device *cdev);
 
 extern int ccw_device_set_online(struct ccw_device *cdev);
 extern int ccw_device_set_offline(struct ccw_device *cdev);
diff --git a/include/asm-s390/chpid.h b/include/asm-s390/chpid.h
index b203336fd892..dfe3c7f3439a 100644
--- a/include/asm-s390/chpid.h
+++ b/include/asm-s390/chpid.h
@@ -10,7 +10,6 @@
 
 #include <linux/string.h>
 #include <asm/types.h>
-#include <asm/cio.h>
 
 #define __MAX_CHPID 255
 
@@ -21,6 +20,9 @@ struct chp_id {
         u8 id;
 } __attribute__((packed));
 
+#ifdef __KERNEL__
+#include <asm/cio.h>
+
 static inline void chp_id_init(struct chp_id *chpid)
 {
         memset(chpid, 0, sizeof(struct chp_id));
@@ -49,5 +51,6 @@ static inline int chp_id_is_valid(struct chp_id *chpid)
 
 #define chp_id_for_each(c) \
         for (chp_id_init(c); chp_id_is_valid(c); chp_id_next(c))
+#endif /* __KERNEL */
 
 #endif /* _ASM_S390_CHPID_H */
diff --git a/include/asm-s390/chsc.h b/include/asm-s390/chsc.h
new file mode 100644
index 000000000000..d38d0cf62d4b
--- /dev/null
+++ b/include/asm-s390/chsc.h
@@ -0,0 +1,127 @@
+/*
+ * ioctl interface for /dev/chsc
+ *
+ * Copyright 2008 IBM Corp.
+ * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
+ */
+
+#ifndef _ASM_CHSC_H
+#define _ASM_CHSC_H
+
+#include <asm/chpid.h>
+#include <asm/schid.h>
+
+struct chsc_async_header {
+        __u16 length;
+        __u16 code;
+        __u32 cmd_dependend;
+        __u32 key : 4;
+        __u32 : 28;
+        struct subchannel_id sid;
+} __attribute__ ((packed));
+
+struct chsc_async_area {
+        struct chsc_async_header header;
+        __u8 data[PAGE_SIZE - 16 /* size of chsc_async_header */];
+} __attribute__ ((packed));
+
+
+struct chsc_response_struct {
+        __u16 length;
+        __u16 code;
+        __u32 parms;
+        __u8 data[PAGE_SIZE - 8];
+} __attribute__ ((packed));
+
+struct chsc_chp_cd {
+        struct chp_id chpid;
+        int m;
+        int fmt;
+        struct chsc_response_struct cpcb;
+};
+
+struct chsc_cu_cd {
+        __u16 cun;
+        __u8 cssid;
+        int m;
+        int fmt;
+        struct chsc_response_struct cucb;
+};
+
+struct chsc_sch_cud {
+        struct subchannel_id schid;
+        int fmt;
+        struct chsc_response_struct scub;
+};
+
+struct conf_id {
+        int m;
+        __u8 cssid;
+        __u8 ssid;
+};
+
+struct chsc_conf_info {
+        struct conf_id id;
+        int fmt;
+        struct chsc_response_struct scid;
+};
+
+struct ccl_parm_chpid {
+        int m;
+        struct chp_id chp;
+};
+
+struct ccl_parm_cssids {
+        __u8 f_cssid;
+        __u8 l_cssid;
+};
+
+struct chsc_comp_list {
+        struct {
+                enum {
+                        CCL_CU_ON_CHP = 1,
+                        CCL_CHP_TYPE_CAP = 2,
+                        CCL_CSS_IMG = 4,
+                        CCL_CSS_IMG_CONF_CHAR = 5,
+                        CCL_IOP_CHP = 6,
+                } ctype;
+                int fmt;
+                struct ccl_parm_chpid chpid;
+                struct ccl_parm_cssids cssids;
+        } req;
+        struct chsc_response_struct sccl;
+};
+
+struct chsc_dcal {
+        struct {
+                enum {
+                        DCAL_CSS_IID_PN = 4,
+                } atype;
+                __u32 list_parm[2];
+                int fmt;
+        } req;
+        struct chsc_response_struct sdcal;
+};
+
+struct chsc_cpd_info {
+        struct chp_id chpid;
+        int m;
+        int fmt;
+        int rfmt;
+        int c;
+        struct chsc_response_struct chpdb;
+};
+
+#define CHSC_IOCTL_MAGIC 'c'
+
+#define CHSC_START _IOWR(CHSC_IOCTL_MAGIC, 0x81, struct chsc_async_area)
+#define CHSC_INFO_CHANNEL_PATH _IOWR(CHSC_IOCTL_MAGIC, 0x82, \
+                                    struct chsc_chp_cd)
+#define CHSC_INFO_CU _IOWR(CHSC_IOCTL_MAGIC, 0x83, struct chsc_cu_cd)
+#define CHSC_INFO_SCH_CU _IOWR(CHSC_IOCTL_MAGIC, 0x84, struct chsc_sch_cud)
+#define CHSC_INFO_CI _IOWR(CHSC_IOCTL_MAGIC, 0x85, struct chsc_conf_info)
+#define CHSC_INFO_CCL _IOWR(CHSC_IOCTL_MAGIC, 0x86, struct chsc_comp_list)
+#define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info)
+#define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal)
+
+#endif
diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h
index 0818ecd30ca6..6dccb071aec3 100644
--- a/include/asm-s390/cio.h
+++ b/include/asm-s390/cio.h
@@ -16,7 +16,7 @@
 #define __MAX_CSSID 0
 
 /**
- * struct scsw - subchannel status word
+ * struct cmd_scsw - command-mode subchannel status word
  * @key: subchannel key
  * @sctl: suspend control
  * @eswf: esw format
@@ -38,7 +38,7 @@
  * @cstat: subchannel status
  * @count: residual count
  */
-struct scsw {
+struct cmd_scsw {
         __u32 key  : 4;
         __u32 sctl : 1;
         __u32 eswf : 1;
@@ -61,6 +61,114 @@ struct scsw {
         __u32 count : 16;
 } __attribute__ ((packed));
 
+/**
+ * struct tm_scsw - transport-mode subchannel status word
+ * @key: subchannel key
+ * @eswf: esw format
+ * @cc: deferred condition code
+ * @fmt: format
+ * @x: IRB-format control
+ * @q: interrogate-complete
+ * @ectl: extended control
+ * @pno: path not operational
+ * @fctl: function control
+ * @actl: activity control
+ * @stctl: status control
+ * @tcw: TCW address
+ * @dstat: device status
+ * @cstat: subchannel status
+ * @fcxs: FCX status
+ * @schxs: subchannel-extended status
+ */
+struct tm_scsw {
+        u32 key:4;
+        u32 :1;
+        u32 eswf:1;
+        u32 cc:2;
+        u32 fmt:3;
+        u32 x:1;
+        u32 q:1;
+        u32 :1;
+        u32 ectl:1;
+        u32 pno:1;
+        u32 :1;
+        u32 fctl:3;
+        u32 actl:7;
+        u32 stctl:5;
+        u32 tcw;
+        u32 dstat:8;
+        u32 cstat:8;
+        u32 fcxs:8;
+        u32 schxs:8;
+} __attribute__ ((packed));
+
+/**
+ * union scsw - subchannel status word
+ * @cmd: command-mode SCSW
+ * @tm: transport-mode SCSW
+ */
+union scsw {
+        struct cmd_scsw cmd;
+        struct tm_scsw tm;
+} __attribute__ ((packed));
+
+int scsw_is_tm(union scsw *scsw);
+u32 scsw_key(union scsw *scsw);
+u32 scsw_eswf(union scsw *scsw);
+u32 scsw_cc(union scsw *scsw);
+u32 scsw_ectl(union scsw *scsw);
+u32 scsw_pno(union scsw *scsw);
+u32 scsw_fctl(union scsw *scsw);
+u32 scsw_actl(union scsw *scsw);
+u32 scsw_stctl(union scsw *scsw);
+u32 scsw_dstat(union scsw *scsw);
+u32 scsw_cstat(union scsw *scsw);
+int scsw_is_solicited(union scsw *scsw);
+int scsw_is_valid_key(union scsw *scsw);
+int scsw_is_valid_eswf(union scsw *scsw);
+int scsw_is_valid_cc(union scsw *scsw);
+int scsw_is_valid_ectl(union scsw *scsw);
+int scsw_is_valid_pno(union scsw *scsw);
+int scsw_is_valid_fctl(union scsw *scsw);
+int scsw_is_valid_actl(union scsw *scsw);
+int scsw_is_valid_stctl(union scsw *scsw);
+int scsw_is_valid_dstat(union scsw *scsw);
+int scsw_is_valid_cstat(union scsw *scsw);
+int scsw_cmd_is_valid_key(union scsw *scsw);
+int scsw_cmd_is_valid_sctl(union scsw *scsw);
+int scsw_cmd_is_valid_eswf(union scsw *scsw);
+int scsw_cmd_is_valid_cc(union scsw *scsw);
+int scsw_cmd_is_valid_fmt(union scsw *scsw);
+int scsw_cmd_is_valid_pfch(union scsw *scsw);
+int scsw_cmd_is_valid_isic(union scsw *scsw);
+int scsw_cmd_is_valid_alcc(union scsw *scsw);
+int scsw_cmd_is_valid_ssi(union scsw *scsw);
+int scsw_cmd_is_valid_zcc(union scsw *scsw);
+int scsw_cmd_is_valid_ectl(union scsw *scsw);
+int scsw_cmd_is_valid_pno(union scsw *scsw);
+int scsw_cmd_is_valid_fctl(union scsw *scsw);
+int scsw_cmd_is_valid_actl(union scsw *scsw);
+int scsw_cmd_is_valid_stctl(union scsw *scsw);
+int scsw_cmd_is_valid_dstat(union scsw *scsw);
+int scsw_cmd_is_valid_cstat(union scsw *scsw);
+int scsw_cmd_is_solicited(union scsw *scsw);
+int scsw_tm_is_valid_key(union scsw *scsw);
+int scsw_tm_is_valid_eswf(union scsw *scsw);
+int scsw_tm_is_valid_cc(union scsw *scsw);
+int scsw_tm_is_valid_fmt(union scsw *scsw);
+int scsw_tm_is_valid_x(union scsw *scsw);
+int scsw_tm_is_valid_q(union scsw *scsw);
+int scsw_tm_is_valid_ectl(union scsw *scsw);
+int scsw_tm_is_valid_pno(union scsw *scsw);
+int scsw_tm_is_valid_fctl(union scsw *scsw);
+int scsw_tm_is_valid_actl(union scsw *scsw);
+int scsw_tm_is_valid_stctl(union scsw *scsw);
+int scsw_tm_is_valid_dstat(union scsw *scsw);
+int scsw_tm_is_valid_cstat(union scsw *scsw);
+int scsw_tm_is_valid_fcxs(union scsw *scsw);
+int scsw_tm_is_valid_schxs(union scsw *scsw);
+int scsw_tm_is_solicited(union scsw *scsw);
+
 #define SCSW_FCTL_CLEAR_FUNC     0x1
 #define SCSW_FCTL_HALT_FUNC      0x2
 #define SCSW_FCTL_START_FUNC     0x4
@@ -303,7 +411,7 @@ struct esw3 {
  * if applicable).
  */
 struct irb {
-        struct scsw scsw;
+        union scsw scsw;
         union {
                 struct esw0 esw0;
                 struct esw1 esw1;
diff --git a/include/asm-s390/elf.h b/include/asm-s390/elf.h
index b3ac262c4582..3cad56923815 100644
--- a/include/asm-s390/elf.h
+++ b/include/asm-s390/elf.h
@@ -113,6 +113,9 @@
 typedef s390_fp_regs elf_fpregset_t;
 typedef s390_regs elf_gregset_t;
 
+typedef s390_fp_regs compat_elf_fpregset_t;
+typedef s390_compat_regs compat_elf_gregset_t;
+
 #include <linux/sched.h>        /* for task_struct */
 #include <asm/system.h>         /* for save_access_regs */
 #include <asm/mmu_context.h>
@@ -123,6 +126,10 @@ typedef s390_regs elf_gregset_t;
 #define elf_check_arch(x) \
         (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
          && (x)->e_ident[EI_CLASS] == ELF_CLASS) 
+#define compat_elf_check_arch(x) \
+        (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
+         && (x)->e_ident[EI_CLASS] == ELF_CLASS)
+#define compat_start_thread     start_thread31
 
 /* For SVR4/S390 the function pointer to be registered with `atexit` is
    passed in R14. */
@@ -131,6 +138,7 @@ typedef s390_regs elf_gregset_t;
                 _r->gprs[14] = 0; \
         } while (0)
 
+#define CORE_DUMP_USE_REGSET
 #define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
@@ -140,44 +148,6 @@ typedef s390_regs elf_gregset_t;
    that it will "exec", and that there is sufficient room for the brk.  */
 #define ELF_ET_DYN_BASE         (STACK_TOP / 3 * 2)
 
-/* Wow, the "main" arch needs arch dependent functions too.. :) */
-
-/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
-   now struct_user_regs, they are different) */
-
-static inline int dump_regs(struct pt_regs *ptregs, elf_gregset_t *regs)
-{
-        memcpy(&regs->psw, &ptregs->psw, sizeof(regs->psw)+sizeof(regs->gprs));
-        save_access_regs(regs->acrs);
-        regs->orig_gpr2 = ptregs->orig_gpr2;
-        return 1;
-}
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) dump_regs(regs, &pr_reg);
-
-static inline int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
-{
-        struct pt_regs *ptregs = task_pt_regs(tsk);
-        memcpy(&regs->psw, &ptregs->psw, sizeof(regs->psw)+sizeof(regs->gprs));
-        memcpy(regs->acrs, tsk->thread.acrs, sizeof(regs->acrs));
-        regs->orig_gpr2 = ptregs->orig_gpr2;
-        return 1;
-}
-
-#define ELF_CORE_COPY_TASK_REGS(tsk, regs) dump_task_regs(tsk, regs)
-
-static inline int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs)
-{
-        if (tsk == current)
-                save_fp_regs(fpregs);
-        else
-                memcpy(fpregs, &tsk->thread.fp_regs, sizeof(elf_fpregset_t));
-        return 1;
-}
-
-#define ELF_CORE_COPY_FPREGS(tsk, fpregs) dump_task_fpu(tsk, fpregs)
-
-
 /* This yields a mask that user programs can use to figure out what
    instruction set this CPU supports. */
 
@@ -204,7 +174,10 @@ do {							\
                 set_personality(PER_SVR4);              \
         else if (current->personality != PER_LINUX32)   \
                 set_personality(PER_LINUX);             \
-        clear_thread_flag(TIF_31BIT);                   \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)       \
+                set_thread_flag(TIF_31BIT);             \
+        else                                            \
+                clear_thread_flag(TIF_31BIT);           \
 } while (0)
 #endif /* __s390x__ */
 
diff --git a/include/asm-s390/etr.h b/include/asm-s390/etr.h
index b498f19bb9a7..80ef58c61970 100644
--- a/include/asm-s390/etr.h
+++ b/include/asm-s390/etr.h
@@ -122,7 +122,7 @@ struct etr_aib {
 } __attribute__ ((packed,aligned(8)));
 
 /* ETR interruption parameter */
-struct etr_interruption_parameter {
+struct etr_irq_parm {
         unsigned int _pad0      : 8;
         unsigned int pc0        : 1;    /* port 0 state change */
         unsigned int pc1        : 1;    /* port 1 state change */
@@ -213,7 +213,46 @@ static inline int etr_ptff(void *ptff_block, unsigned int func)
 #define ETR_PTFF_SGS    0x43    /* set gross steering rate */
 
 /* Functions needed by the machine check handler */
-extern void etr_switch_to_local(void);
-extern void etr_sync_check(void);
+void etr_switch_to_local(void);
+void etr_sync_check(void);
+
+/* STP interruption parameter */
+struct stp_irq_parm {
+        unsigned int _pad0      : 14;
+        unsigned int tsc        : 1;    /* Timing status change */
+        unsigned int lac        : 1;    /* Link availability change */
+        unsigned int tcpc       : 1;    /* Time control parameter change */
+        unsigned int _pad2      : 15;
+} __attribute__ ((packed));
+
+#define STP_OP_SYNC     1
+#define STP_OP_CTRL     3
+
+struct stp_sstpi {
+        unsigned int rsvd0;
+        unsigned int rsvd1 : 8;
+        unsigned int stratum : 8;
+        unsigned int vbits : 16;
+        unsigned int leaps : 16;
+        unsigned int tmd : 4;
+        unsigned int ctn : 4;
+        unsigned int rsvd2 : 3;
+        unsigned int c : 1;
+        unsigned int tst : 4;
+        unsigned int tzo : 16;
+        unsigned int dsto : 16;
+        unsigned int ctrl : 16;
+        unsigned int rsvd3 : 16;
+        unsigned int tto;
+        unsigned int rsvd4;
+        unsigned int ctnid[3];
+        unsigned int rsvd5;
+        unsigned int todoff[4];
+        unsigned int rsvd6[48];
+} __attribute__ ((packed));
+
+/* Functions needed by the machine check handler */
+void stp_sync_check(void);
+void stp_island_check(void);
 
 #endif /* __S390_ETR_H */
diff --git a/include/asm-s390/fcx.h b/include/asm-s390/fcx.h
new file mode 100644
index 000000000000..8be1f3a58042
--- /dev/null
+++ b/include/asm-s390/fcx.h
@@ -0,0 +1,311 @@
+/*
+ *  Functions for assembling fcx enabled I/O control blocks.
+ *
+ *    Copyright IBM Corp. 2008
+ *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_FCX_H
+#define _ASM_S390_FCX_H _ASM_S390_FCX_H
+
+#include <linux/types.h>
+
+#define TCW_FORMAT_DEFAULT              0
+#define TCW_TIDAW_FORMAT_DEFAULT        0
+#define TCW_FLAGS_INPUT_TIDA            1 << (23 - 5)
+#define TCW_FLAGS_TCCB_TIDA             1 << (23 - 6)
+#define TCW_FLAGS_OUTPUT_TIDA           1 << (23 - 7)
+#define TCW_FLAGS_TIDAW_FORMAT(x)       ((x) & 3) << (23 - 9)
+#define TCW_FLAGS_GET_TIDAW_FORMAT(x)   (((x) >> (23 - 9)) & 3)
+
+/**
+ * struct tcw - Transport Control Word (TCW)
+ * @format: TCW format
+ * @flags: TCW flags
+ * @tccbl: Transport-Command-Control-Block Length
+ * @r: Read Operations
+ * @w: Write Operations
+ * @output: Output-Data Address
+ * @input: Input-Data Address
+ * @tsb: Transport-Status-Block Address
+ * @tccb: Transport-Command-Control-Block Address
+ * @output_count: Output Count
+ * @input_count: Input Count
+ * @intrg: Interrogate TCW Address
+ */
+struct tcw {
+        u32 format:2;
+        u32 :6;
+        u32 flags:24;
+        u32 :8;
+        u32 tccbl:6;
+        u32 r:1;
+        u32 w:1;
+        u32 :16;
+        u64 output;
+        u64 input;
+        u64 tsb;
+        u64 tccb;
+        u32 output_count;
+        u32 input_count;
+        u32 :32;
+        u32 :32;
+        u32 :32;
+        u32 intrg;
+} __attribute__ ((packed, aligned(64)));
+
+#define TIDAW_FLAGS_LAST                1 << (7 - 0)
+#define TIDAW_FLAGS_SKIP                1 << (7 - 1)
+#define TIDAW_FLAGS_DATA_INT            1 << (7 - 2)
+#define TIDAW_FLAGS_TTIC                1 << (7 - 3)
+#define TIDAW_FLAGS_INSERT_CBC          1 << (7 - 4)
+
+/**
+ * struct tidaw - Transport-Indirect-Addressing Word (TIDAW)
+ * @flags: TIDAW flags. Can be an arithmetic OR of the following constants:
+ * %TIDAW_FLAGS_LAST, %TIDAW_FLAGS_SKIP, %TIDAW_FLAGS_DATA_INT,
+ * %TIDAW_FLAGS_TTIC, %TIDAW_FLAGS_INSERT_CBC
+ * @count: Count
+ * @addr: Address
+ */
+struct tidaw {
+        u32 flags:8;
+        u32 :24;
+        u32 count;
+        u64 addr;
+} __attribute__ ((packed, aligned(16)));
+
+/**
+ * struct tsa_iostat - I/O-Status Transport-Status Area (IO-Stat TSA)
+ * @dev_time: Device Time
+ * @def_time: Defer Time
+ * @queue_time: Queue Time
+ * @dev_busy_time: Device-Busy Time
+ * @dev_act_time: Device-Active-Only Time
+ * @sense: Sense Data (if present)
+ */
+struct tsa_iostat {
+        u32 dev_time;
+        u32 def_time;
+        u32 queue_time;
+        u32 dev_busy_time;
+        u32 dev_act_time;
+        u8 sense[32];
+} __attribute__ ((packed));
+
+/**
+ * struct tsa_ddpcs - Device-Detected-Program-Check Transport-Status Area (DDPC TSA)
+ * @rc: Reason Code
+ * @rcq: Reason Code Qualifier
+ * @sense: Sense Data (if present)
+ */
+struct tsa_ddpc {
+        u32 :24;
+        u32 rc:8;
+        u8 rcq[16];
+        u8 sense[32];
+} __attribute__ ((packed));
+
+#define TSA_INTRG_FLAGS_CU_STATE_VALID          1 << (7 - 0)
+#define TSA_INTRG_FLAGS_DEV_STATE_VALID         1 << (7 - 1)
+#define TSA_INTRG_FLAGS_OP_STATE_VALID          1 << (7 - 2)
+
+/**
+ * struct tsa_intrg - Interrogate Transport-Status Area (Intrg. TSA)
+ * @format: Format
+ * @flags: Flags. Can be an arithmetic OR of the following constants:
+ * %TSA_INTRG_FLAGS_CU_STATE_VALID, %TSA_INTRG_FLAGS_DEV_STATE_VALID,
+ * %TSA_INTRG_FLAGS_OP_STATE_VALID
+ * @cu_state: Controle-Unit State
+ * @dev_state: Device State
+ * @op_state: Operation State
+ * @sd_info: State-Dependent Information
+ * @dl_id: Device-Level Identifier
+ * @dd_data: Device-Dependent Data
+ */
+struct tsa_intrg {
+        u32 format:8;
+        u32 flags:8;
+        u32 cu_state:8;
+        u32 dev_state:8;
+        u32 op_state:8;
+        u32 :24;
+        u8 sd_info[12];
+        u32 dl_id;
+        u8 dd_data[28];
+} __attribute__ ((packed));
+
+#define TSB_FORMAT_NONE         0
+#define TSB_FORMAT_IOSTAT       1
+#define TSB_FORMAT_DDPC         2
+#define TSB_FORMAT_INTRG        3
+
+#define TSB_FLAGS_DCW_OFFSET_VALID      1 << (7 - 0)
+#define TSB_FLAGS_COUNT_VALID           1 << (7 - 1)
+#define TSB_FLAGS_CACHE_MISS            1 << (7 - 2)
+#define TSB_FLAGS_TIME_VALID            1 << (7 - 3)
+#define TSB_FLAGS_FORMAT(x)             ((x) & 7)
+#define TSB_FORMAT(t)                   ((t)->flags & 7)
+
+/**
+ * struct tsb - Transport-Status Block (TSB)
+ * @length: Length
+ * @flags: Flags. Can be an arithmetic OR of the following constants:
+ * %TSB_FLAGS_DCW_OFFSET_VALID, %TSB_FLAGS_COUNT_VALID, %TSB_FLAGS_CACHE_MISS,
+ * %TSB_FLAGS_TIME_VALID
+ * @dcw_offset: DCW Offset
+ * @count: Count
+ * @tsa: Transport-Status-Area
+ */
+struct tsb {
+        u32 length:8;
+        u32 flags:8;
+        u32 dcw_offset:16;
+        u32 count;
+        u32 :32;
+        union {
+                struct tsa_iostat iostat;
+                struct tsa_ddpc ddpc;
+                struct tsa_intrg intrg;
+        } __attribute__ ((packed)) tsa;
+} __attribute__ ((packed, aligned(8)));
+
+#define DCW_INTRG_FORMAT_DEFAULT        0
+
+#define DCW_INTRG_RC_UNSPECIFIED        0
+#define DCW_INTRG_RC_TIMEOUT            1
+
+#define DCW_INTRG_RCQ_UNSPECIFIED       0
+#define DCW_INTRG_RCQ_PRIMARY           1
+#define DCW_INTRG_RCQ_SECONDARY         2
+
+#define DCW_INTRG_FLAGS_MPM             1 < (7 - 0)
+#define DCW_INTRG_FLAGS_PPR             1 < (7 - 1)
+#define DCW_INTRG_FLAGS_CRIT            1 < (7 - 2)
+
+/**
+ * struct dcw_intrg_data - Interrogate DCW data
+ * @format: Format. Should be %DCW_INTRG_FORMAT_DEFAULT
+ * @rc: Reason Code. Can be one of %DCW_INTRG_RC_UNSPECIFIED,
+ * %DCW_INTRG_RC_TIMEOUT
+ * @rcq: Reason Code Qualifier: Can be one of %DCW_INTRG_RCQ_UNSPECIFIED,
+ * %DCW_INTRG_RCQ_PRIMARY, %DCW_INTRG_RCQ_SECONDARY
+ * @lpm: Logical-Path Mask
+ * @pam: Path-Available Mask
+ * @pim: Path-Installed Mask
+ * @timeout: Timeout
+ * @flags: Flags. Can be an arithmetic OR of %DCW_INTRG_FLAGS_MPM,
+ * %DCW_INTRG_FLAGS_PPR, %DCW_INTRG_FLAGS_CRIT
+ * @time: Time
+ * @prog_id: Program Identifier
+ * @prog_data: Program-Dependent Data
+ */
+struct dcw_intrg_data {
+        u32 format:8;
+        u32 rc:8;
+        u32 rcq:8;
+        u32 lpm:8;
+        u32 pam:8;
+        u32 pim:8;
+        u32 timeout:16;
+        u32 flags:8;
+        u32 :24;
+        u32 :32;
+        u64 time;
+        u64 prog_id;
+        u8  prog_data[0];
+} __attribute__ ((packed));
+
+#define DCW_FLAGS_CC            1 << (7 - 1)
+
+#define DCW_CMD_WRITE           0x01
+#define DCW_CMD_READ            0x02
+#define DCW_CMD_CONTROL         0x03
+#define DCW_CMD_SENSE           0x04
+#define DCW_CMD_SENSE_ID        0xe4
+#define DCW_CMD_INTRG           0x40
+
+/**
+ * struct dcw - Device-Command Word (DCW)
+ * @cmd: Command Code. Can be one of %DCW_CMD_WRITE, %DCW_CMD_READ,
+ * %DCW_CMD_CONTROL, %DCW_CMD_SENSE, %DCW_CMD_SENSE_ID, %DCW_CMD_INTRG
+ * @flags: Flags. Can be an arithmetic OR of %DCW_FLAGS_CC
+ * @cd_count: Control-Data Count
+ * @count: Count
+ * @cd: Control Data
+ */
+struct dcw {
+        u32 cmd:8;
+        u32 flags:8;
+        u32 :8;
+        u32 cd_count:8;
+        u32 count;
+        u8 cd[0];
+} __attribute__ ((packed));
+
+#define TCCB_FORMAT_DEFAULT     0x7f
+#define TCCB_MAX_DCW            30
+#define TCCB_MAX_SIZE           (sizeof(struct tccb_tcah) + \
+                                 TCCB_MAX_DCW * sizeof(struct dcw) + \
+                                 sizeof(struct tccb_tcat))
+#define TCCB_SAC_DEFAULT        0xf901
+#define TCCB_SAC_INTRG          0xf902
+
+/**
+ * struct tccb_tcah - Transport-Command-Area Header (TCAH)
+ * @format: Format. Should be %TCCB_FORMAT_DEFAULT
+ * @tcal: Transport-Command-Area Length
+ * @sac: Service-Action Code. Can be one of %TCCB_SAC_DEFAULT, %TCCB_SAC_INTRG
+ * @prio: Priority
+ */
+struct tccb_tcah {
+        u32 format:8;
+        u32 :24;
+        u32 :24;
+        u32 tcal:8;
+        u32 sac:16;
+        u32 :8;
+        u32 prio:8;
+        u32 :32;
+} __attribute__ ((packed));
+
+/**
+ * struct tccb_tcat - Transport-Command-Area Trailer (TCAT)
+ * @count: Transport Count
+ */
+struct tccb_tcat {
+        u32 :32;
+        u32 count;
+} __attribute__ ((packed));
+
+/**
+ * struct tccb - (partial) Transport-Command-Control Block (TCCB)
+ * @tcah: TCAH
+ * @tca: Transport-Command Area
+ */
+struct tccb {
+        struct tccb_tcah tcah;
+        u8 tca[0];
+} __attribute__ ((packed, aligned(8)));
+
+struct tcw *tcw_get_intrg(struct tcw *tcw);
+void *tcw_get_data(struct tcw *tcw);
+struct tccb *tcw_get_tccb(struct tcw *tcw);
+struct tsb *tcw_get_tsb(struct tcw *tcw);
+
+void tcw_init(struct tcw *tcw, int r, int w);
+void tcw_finalize(struct tcw *tcw, int num_tidaws);
+
+void tcw_set_intrg(struct tcw *tcw, struct tcw *intrg_tcw);
+void tcw_set_data(struct tcw *tcw, void *data, int use_tidal);
+void tcw_set_tccb(struct tcw *tcw, struct tccb *tccb);
+void tcw_set_tsb(struct tcw *tcw, struct tsb *tsb);
+
+void tccb_init(struct tccb *tccb, size_t tccb_size, u32 sac);
+void tsb_init(struct tsb *tsb);
+struct dcw *tccb_add_dcw(struct tccb *tccb, size_t tccb_size, u8 cmd, u8 flags,
+                         void *cd, u8 cd_count, u32 count);
+struct tidaw *tcw_add_tidaw(struct tcw *tcw, int num_tidaws, u8 flags,
+                            void *addr, u32 count);
+
+#endif /* _ASM_S390_FCX_H */
diff --git a/include/asm-s390/ipl.h b/include/asm-s390/ipl.h
index c1b2e50392bb..eaca6dff5405 100644
--- a/include/asm-s390/ipl.h
+++ b/include/asm-s390/ipl.h
@@ -56,15 +56,19 @@ struct ipl_block_fcp {
         u8  scp_data[];
 } __attribute__((packed));
 
+#define DIAG308_VMPARM_SIZE     64
+
 struct ipl_block_ccw {
-        u8  load_param[8];
+        u8  load_parm[8];
         u8  reserved1[84];
         u8  reserved2[2];
         u16 devno;
         u8  vm_flags;
         u8  reserved3[3];
         u32 vm_parm_len;
-        u8  reserved4[80];
+        u8  nss_name[8];
+        u8  vm_parm[DIAG308_VMPARM_SIZE];
+        u8  reserved4[8];
 } __attribute__((packed));
 
 struct ipl_parameter_block {
@@ -73,7 +77,7 @@ struct ipl_parameter_block {
                 struct ipl_block_fcp fcp;
                 struct ipl_block_ccw ccw;
         } ipl_info;
-} __attribute__((packed));
+} __attribute__((packed,aligned(4096)));
 
 /*
  * IPL validity flags
@@ -86,6 +90,8 @@ extern void do_reipl(void);
 extern void do_halt(void);
 extern void do_poff(void);
 extern void ipl_save_parameters(void);
+extern void ipl_update_parameters(void);
+extern void get_ipl_vmparm(char *);
 
 enum {
         IPL_DEVNO_VALID         = 1,
@@ -147,6 +153,11 @@ enum diag308_flags {
         DIAG308_FLAGS_LP_VALID  = 0x80,
 };
 
+enum diag308_vm_flags {
+        DIAG308_VM_FLAGS_NSS_VALID      = 0x80,
+        DIAG308_VM_FLAGS_VP_VALID       = 0x40,
+};
+
 enum diag308_rc {
         DIAG308_RC_OK   = 1,
 };
diff --git a/include/asm-s390/isc.h b/include/asm-s390/isc.h
new file mode 100644
index 000000000000..34bb8916db4f
--- /dev/null
+++ b/include/asm-s390/isc.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_S390_ISC_H
+#define _ASM_S390_ISC_H
+
+#include <linux/types.h>
+
+/*
+ * I/O interruption subclasses used by drivers.
+ * Please add all used iscs here so that it is possible to distribute
+ * isc usage between drivers.
+ * Reminder: 0 is highest priority, 7 lowest.
+ */
+#define MAX_ISC 7
+
+/* Regular I/O interrupts. */
+#define IO_SCH_ISC 3                    /* regular I/O subchannels */
+#define CONSOLE_ISC 1                   /* console I/O subchannel */
+#define CHSC_SCH_ISC 7                  /* CHSC subchannels */
+/* Adapter interrupts. */
+#define QDIO_AIRQ_ISC IO_SCH_ISC        /* I/O subchannel in qdio mode */
+
+/* Functions for registration of I/O interruption subclasses */
+void isc_register(unsigned int isc);
+void isc_unregister(unsigned int isc);
+
+#endif /* _ASM_S390_ISC_H */
diff --git a/include/asm-s390/itcw.h b/include/asm-s390/itcw.h
new file mode 100644
index 000000000000..a9bc5c36b32a
--- /dev/null
+++ b/include/asm-s390/itcw.h
@@ -0,0 +1,30 @@
+/*
+ *  Functions for incremental construction of fcx enabled I/O control blocks.
+ *
+ *    Copyright IBM Corp. 2008
+ *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_ITCW_H
+#define _ASM_S390_ITCW_H _ASM_S390_ITCW_H
+
+#include <linux/types.h>
+#include <asm/fcx.h>
+
+#define ITCW_OP_READ    0
+#define ITCW_OP_WRITE   1
+
+struct itcw;
+
+struct tcw *itcw_get_tcw(struct itcw *itcw);
+size_t itcw_calc_size(int intrg, int max_tidaws, int intrg_max_tidaws);
+struct itcw *itcw_init(void *buffer, size_t size, int op, int intrg,
+                       int max_tidaws, int intrg_max_tidaws);
+struct dcw *itcw_add_dcw(struct itcw *itcw, u8 cmd, u8 flags, void *cd,
+                         u8 cd_count, u32 count);
+struct tidaw *itcw_add_tidaw(struct itcw *itcw, u8 flags, void *addr,
+                             u32 count);
+void itcw_set_data(struct itcw *itcw, void *addr, int use_tidal);
+void itcw_finalize(struct itcw *itcw);
+
+#endif /* _ASM_S390_ITCW_H */
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index bd0ea191dfa9..0bdb704ae051 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -29,6 +29,7 @@
  * the S390 page table tree.
  */
 #ifndef __ASSEMBLY__
+#include <linux/sched.h>
 #include <linux/mm_types.h>
 #include <asm/bitops.h>
 #include <asm/bug.h>
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index a00f79dd323b..4af80af2a88f 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -143,11 +143,19 @@ struct stack_frame {
 /*
  * Do necessary setup to start up a new thread.
  */
-#define start_thread(regs, new_psw, new_stackp) do {            \
+#define start_thread(regs, new_psw, new_stackp) do {            \
         set_fs(USER_DS);                                        \
         regs->psw.mask  = psw_user_bits;                        \
-        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;             \
-        regs->gprs[15]  = new_stackp ;                          \
+        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;             \
+        regs->gprs[15]  = new_stackp;                           \
+} while (0)
+
+#define start_thread31(regs, new_psw, new_stackp) do {          \
+        set_fs(USER_DS);                                        \
+        regs->psw.mask  = psw_user32_bits;                      \
+        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;             \
+        regs->gprs[15]  = new_stackp;                           \
+        crst_table_downgrade(current->mm, 1UL << 31);           \
 } while (0)
 
 /* Forward declaration, a strange C thing */
@@ -328,16 +336,6 @@ extern void (*s390_base_mcck_handler_fn)(void);
 extern void (*s390_base_pgm_handler_fn)(void);
 extern void (*s390_base_ext_handler_fn)(void);
 
-/*
- * CPU idle notifier chain.
- */
-#define S390_CPU_IDLE           0
-#define S390_CPU_NOT_IDLE       1
-
-struct notifier_block;
-int register_idle_notifier(struct notifier_block *nb);
-int unregister_idle_notifier(struct notifier_block *nb);
-
 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 
 #endif
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index d7d4e2eb3e6f..af2c9ac28a07 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -215,6 +215,12 @@ typedef struct
         unsigned long addr;
 } __attribute__ ((aligned(8))) psw_t;
 
+typedef struct
+{
+        __u32   mask;
+        __u32   addr;
+} __attribute__ ((aligned(8))) psw_compat_t;
+
 #ifndef __s390x__
 
 #define PSW_MASK_PER            0x40000000UL
@@ -292,6 +298,15 @@ typedef struct
         unsigned long orig_gpr2;
 } s390_regs;
 
+typedef struct
+{
+        psw_compat_t    psw;
+        __u32           gprs[NUM_GPRS];
+        __u32           acrs[NUM_ACRS];
+        __u32           orig_gpr2;
+} s390_compat_regs;
+
+
 #ifdef __KERNEL__
 #include <asm/setup.h>
 #include <asm/page.h>
diff --git a/include/asm-s390/qdio.h b/include/asm-s390/qdio.h
index 11240342a0f4..6813772171f2 100644
--- a/include/asm-s390/qdio.h
+++ b/include/asm-s390/qdio.h
@@ -1,404 +1,382 @@
 /*
  * linux/include/asm-s390/qdio.h
  *
- * Linux for S/390 QDIO base support, Hipersocket base support
- * version 2
- *
- * Copyright 2000,2002 IBM Corporation
+ * Copyright 2000,2008 IBM Corp.
  * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
+ *            Jan Glauber <jang@linux.vnet.ibm.com>
  *
  */
 #ifndef __QDIO_H__
 #define __QDIO_H__
 
-/* note, that most of the typedef's are from ingo. */
-
 #include <linux/interrupt.h>
 #include <asm/cio.h>
 #include <asm/ccwdev.h>
 
-#define QDIO_NAME "qdio "
-
-#ifndef __s390x__
-#define QDIO_32_BIT
-#endif /* __s390x__ */
-
-/**** CONSTANTS, that are relied on without using these symbols *****/
-#define QDIO_MAX_QUEUES_PER_IRQ 32 /* used in width of unsigned int */
-/************************ END of CONSTANTS **************************/
-#define QDIO_MAX_BUFFERS_PER_Q 128 /* must be a power of 2 (%x=&(x-1)*/
-#define QDIO_BUF_ORDER 7 /* 2**this == number of pages used for sbals in 1 q */
-#define QDIO_MAX_ELEMENTS_PER_BUFFER 16
-#define SBAL_SIZE 256
-
-#define QDIO_QETH_QFMT 0
-#define QDIO_ZFCP_QFMT 1
-#define QDIO_IQDIO_QFMT 2
-#define QDIO_IQDIO_QFMT_ASYNCH 3
-
-struct qdio_buffer_element{
-        unsigned int flags;
-        unsigned int length;
-#ifdef QDIO_32_BIT
-        void *reserved;
-#endif /* QDIO_32_BIT */
-        void *addr;
-} __attribute__ ((packed,aligned(16)));
-
-struct qdio_buffer{
-        volatile struct qdio_buffer_element element[16];
-} __attribute__ ((packed,aligned(256)));
-
-
-/* params are: ccw_device, status, qdio_error, siga_error,
-   queue_number, first element processed, number of elements processed,
-   int_parm */
-typedef void qdio_handler_t(struct ccw_device *,unsigned int,unsigned int,
-                            unsigned int,unsigned int,int,int,unsigned long);
-
-
-#define QDIO_STATUS_INBOUND_INT 0x01
-#define QDIO_STATUS_OUTBOUND_INT 0x02
-#define QDIO_STATUS_LOOK_FOR_ERROR 0x04
-#define QDIO_STATUS_MORE_THAN_ONE_QDIO_ERROR 0x08
-#define QDIO_STATUS_MORE_THAN_ONE_SIGA_ERROR 0x10
-#define QDIO_STATUS_ACTIVATE_CHECK_CONDITION 0x20
-
-#define QDIO_SIGA_ERROR_ACCESS_EXCEPTION 0x10
-#define QDIO_SIGA_ERROR_B_BIT_SET 0x20
-
-/* for qdio_initialize */
-#define QDIO_INBOUND_0COPY_SBALS 0x01
-#define QDIO_OUTBOUND_0COPY_SBALS 0x02
-#define QDIO_USE_OUTBOUND_PCIS 0x04
-
-/* for qdio_cleanup */
-#define QDIO_FLAG_CLEANUP_USING_CLEAR 0x01
-#define QDIO_FLAG_CLEANUP_USING_HALT 0x02
-
-struct qdio_initialize {
-        struct ccw_device *cdev;
-        unsigned char q_format;
-        unsigned char adapter_name[8];
-        unsigned int qib_param_field_format; /*adapter dependent*/
-        /* pointer to 128 bytes or NULL, if no param field */
-        unsigned char *qib_param_field; /* adapter dependent */
-        /* pointer to no_queues*128 words of data or NULL */
-        unsigned long *input_slib_elements;
-        unsigned long *output_slib_elements;
-        unsigned int min_input_threshold;
-        unsigned int max_input_threshold;
-        unsigned int min_output_threshold;
-        unsigned int max_output_threshold;
-        unsigned int no_input_qs;
-        unsigned int no_output_qs;
-        qdio_handler_t *input_handler;
-        qdio_handler_t *output_handler;
-        unsigned long int_parm;
-        unsigned long flags;
-        void **input_sbal_addr_array; /* addr of n*128 void ptrs */
-        void **output_sbal_addr_array; /* addr of n*128 void ptrs */
-};
-
-extern int qdio_initialize(struct qdio_initialize *init_data);
-extern int qdio_allocate(struct qdio_initialize *init_data);
-extern int qdio_establish(struct qdio_initialize *init_data);
-
-extern int qdio_activate(struct ccw_device *,int flags);
-
-#define QDIO_STATE_MUST_USE_OUTB_PCI    0x00000001
-#define QDIO_STATE_INACTIVE             0x00000002 /* after qdio_cleanup */
-#define QDIO_STATE_ESTABLISHED          0x00000004 /* after qdio_initialize */
-#define QDIO_STATE_ACTIVE               0x00000008 /* after qdio_activate */
-#define QDIO_STATE_STOPPED              0x00000010 /* after queues went down */
-extern unsigned long qdio_get_status(int irq);
-
-
-#define QDIO_FLAG_SYNC_INPUT     0x01
-#define QDIO_FLAG_SYNC_OUTPUT    0x02
-#define QDIO_FLAG_UNDER_INTERRUPT 0x04
-#define QDIO_FLAG_NO_INPUT_INTERRUPT_CONTEXT 0x08 /* no effect on
-                                                     adapter interrupts */
-#define QDIO_FLAG_DONT_SIGA 0x10
-#define QDIO_FLAG_PCI_OUT   0x20
-
-extern int do_QDIO(struct ccw_device*, unsigned int flags, 
-                   unsigned int queue_number,
-                   unsigned int qidx,unsigned int count,
-                   struct qdio_buffer *buffers);
-
-extern int qdio_get_ssqd_pct(struct ccw_device*);
-extern int qdio_synchronize(struct ccw_device*, unsigned int flags,
-                            unsigned int queue_number);
-
-extern int qdio_cleanup(struct ccw_device*, int how);
-extern int qdio_shutdown(struct ccw_device*, int how);
-extern int qdio_free(struct ccw_device*);
-
-unsigned char qdio_get_slsb_state(struct ccw_device*, unsigned int flag,
-                                  unsigned int queue_number,
-                                  unsigned int qidx);
-
-extern void qdio_init_scrubber(void);
-
+#define QDIO_MAX_QUEUES_PER_IRQ         32
+#define QDIO_MAX_BUFFERS_PER_Q          128
+#define QDIO_MAX_BUFFERS_MASK           (QDIO_MAX_BUFFERS_PER_Q - 1)
+#define QDIO_MAX_ELEMENTS_PER_BUFFER    16
+#define QDIO_SBAL_SIZE                  256
+
+#define QDIO_QETH_QFMT                  0
+#define QDIO_ZFCP_QFMT                  1
+#define QDIO_IQDIO_QFMT                 2
+
+/**
+ * struct qdesfmt0 - queue descriptor, format 0
+ * @sliba: storage list information block address
+ * @sla: storage list address
+ * @slsba: storage list state block address
+ * @akey: access key for DLIB
+ * @bkey: access key for SL
+ * @ckey: access key for SBALs
+ * @dkey: access key for SLSB
+ */
 struct qdesfmt0 {
-#ifdef QDIO_32_BIT
-        unsigned long res1;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long sliba;            /* storage-list-information-block
-                                           address */
-#ifdef QDIO_32_BIT
-        unsigned long res2;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long sla;              /* storage-list address */
-#ifdef QDIO_32_BIT
-        unsigned long res3;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long slsba;            /* storage-list-state-block address */
-        unsigned int  res4;             /* reserved */
-        unsigned int  akey  :  4;       /* access key for DLIB */
-        unsigned int  bkey  :  4;       /* access key for SL */
-        unsigned int  ckey  :  4;       /* access key for SBALs */
-        unsigned int  dkey  :  4;       /* access key for SLSB */
-        unsigned int  res5  : 16;       /* reserved */
+        u64 sliba;
+        u64 sla;
+        u64 slsba;
+        u32      : 32;
+        u32 akey : 4;
+        u32 bkey : 4;
+        u32 ckey : 4;
+        u32 dkey : 4;
+        u32      : 16;
 } __attribute__ ((packed));
 
-/*
- * Queue-Description record (QDR)
+/**
+ * struct qdr - queue description record (QDR)
+ * @qfmt: queue format
+ * @pfmt: implementation dependent parameter format
+ * @ac: adapter characteristics
+ * @iqdcnt: input queue descriptor count
+ * @oqdcnt: output queue descriptor count
+ * @iqdsz: inpout queue descriptor size
+ * @oqdsz: output queue descriptor size
+ * @qiba: queue information block address
+ * @qkey: queue information block key
+ * @qdf0: queue descriptions
  */
 struct qdr {
-        unsigned int  qfmt    :  8;     /* queue format */
-        unsigned int  pfmt    :  8;     /* impl. dep. parameter format */
-        unsigned int  res1    :  8;     /* reserved */
-        unsigned int  ac      :  8;     /* adapter characteristics */
-        unsigned int  res2    :  8;     /* reserved */
-        unsigned int  iqdcnt  :  8;     /* input-queue-descriptor count */
-        unsigned int  res3    :  8;     /* reserved */
-        unsigned int  oqdcnt  :  8;     /* output-queue-descriptor count */
-        unsigned int  res4    :  8;     /* reserved */
-        unsigned int  iqdsz   :  8;     /* input-queue-descriptor size */
-        unsigned int  res5    :  8;     /* reserved */
-        unsigned int  oqdsz   :  8;     /* output-queue-descriptor size */
-        unsigned int  res6[9];          /* reserved */
-#ifdef QDIO_32_BIT
-        unsigned long res7;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long qiba;             /* queue-information-block address */
-        unsigned int  res8;             /* reserved */
-        unsigned int  qkey    :  4;     /* queue-information-block key */
-        unsigned int  res9    : 28;     /* reserved */
-/*      union _qd {*/ /* why this? */
-                struct qdesfmt0 qdf0[126];
-/*      } qd;*/
-} __attribute__ ((packed,aligned(4096)));
-
-
-/*
- * queue information block (QIB)
- */
-#define QIB_AC_INBOUND_PCI_SUPPORTED    0x80
-#define QIB_AC_OUTBOUND_PCI_SUPPORTED   0x40
+        u32 qfmt   : 8;
+        u32 pfmt   : 8;
+        u32        : 8;
+        u32 ac     : 8;
+        u32        : 8;
+        u32 iqdcnt : 8;
+        u32        : 8;
+        u32 oqdcnt : 8;
+        u32        : 8;
+        u32 iqdsz  : 8;
+        u32        : 8;
+        u32 oqdsz  : 8;
+        /* private: */
+        u32 res[9];
+        /* public: */
+        u64 qiba;
+        u32        : 32;
+        u32 qkey   : 4;
+        u32        : 28;
+        struct qdesfmt0 qdf0[126];
+} __attribute__ ((packed, aligned(4096)));
+
+#define QIB_AC_OUTBOUND_PCI_SUPPORTED   0x40
 #define QIB_RFLAGS_ENABLE_QEBSM         0x80
 
+/**
+ * struct qib - queue information block (QIB)
+ * @qfmt: queue format
+ * @pfmt: implementation dependent parameter format
+ * @rflags: QEBSM
+ * @ac: adapter characteristics
+ * @isliba: absolute address of first input SLIB
+ * @osliba: absolute address of first output SLIB
+ * @ebcnam: adapter identifier in EBCDIC
+ * @parm: implementation dependent parameters
+ */
 struct qib {
-        unsigned int  qfmt    :  8;     /* queue format */
-        unsigned int  pfmt    :  8;     /* impl. dep. parameter format */
-        unsigned int  rflags  :  8;     /* QEBSM */
-        unsigned int  ac      :  8;     /* adapter characteristics */
-        unsigned int  res2;             /* reserved */
-#ifdef QDIO_32_BIT
-        unsigned long res3;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long isliba;           /* absolute address of 1st
-                                           input SLIB */
-#ifdef QDIO_32_BIT
-        unsigned long res4;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long osliba;           /* absolute address of 1st
-                                           output SLIB */
-        unsigned int  res5;             /* reserved */
-        unsigned int  res6;             /* reserved */
-        unsigned char ebcnam[8];        /* adapter identifier in EBCDIC */
-        unsigned char res7[88];         /* reserved */
-        unsigned char parm[QDIO_MAX_BUFFERS_PER_Q];
-                                        /* implementation dependent
-                                           parameters */
-} __attribute__ ((packed,aligned(256)));
-
-
-/*
- * storage-list-information block element (SLIBE)
+        u32 qfmt   : 8;
+        u32 pfmt   : 8;
+        u32 rflags : 8;
+        u32 ac     : 8;
+        u32        : 32;
+        u64 isliba;
+        u64 osliba;
+        u32        : 32;
+        u32        : 32;
+        u8 ebcnam[8];
+        /* private: */
+        u8 res[88];
+        /* public: */
+        u8 parm[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(256)));
+
+/**
+ * struct slibe - storage list information block element (SLIBE)
+ * @parms: implementation dependent parameters
  */
 struct slibe {
-#ifdef QDIO_32_BIT
-        unsigned long res;              /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long parms;            /* implementation dependent
-                                           parameters */
+        u64 parms;
 };
 
-/*
- * storage-list-information block (SLIB)
+/**
+ * struct slib - storage list information block (SLIB)
+ * @nsliba: next SLIB address (if any)
+ * @sla: SL address
+ * @slsba: SLSB address
+ * @slibe: SLIB elements
  */
 struct slib {
-#ifdef QDIO_32_BIT
-        unsigned long res1;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long nsliba;           /* next SLIB address (if any) */
-#ifdef QDIO_32_BIT
-        unsigned long res2;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long sla;              /* SL address */
-#ifdef QDIO_32_BIT
-        unsigned long res3;             /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long slsba;            /* SLSB address */
-        unsigned char res4[1000];       /* reserved */
-        struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q];    /* SLIB elements */
-} __attribute__ ((packed,aligned(2048)));
-
+        u64 nsliba;
+        u64 sla;
+        u64 slsba;
+        /* private: */
+        u8 res[1000];
+        /* public: */
+        struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(2048)));
+
+/**
+ * struct sbal_flags - storage block address list flags
+ * @last: last entry
+ * @cont: contiguous storage
+ * @frag: fragmentation
+ */
 struct sbal_flags {
-        unsigned char res1  : 1;   /* reserved */
-        unsigned char last  : 1;   /* last entry */
-        unsigned char cont  : 1;   /* contiguous storage */
-        unsigned char res2  : 1;   /* reserved */
-        unsigned char frag  : 2;   /* fragmentation (s.below) */
-        unsigned char res3  : 2;   /* reserved */
+        u8      : 1;
+        u8 last : 1;
+        u8 cont : 1;
+        u8      : 1;
+        u8 frag : 2;
+        u8      : 2;
 } __attribute__ ((packed));
 
-#define SBAL_FLAGS_FIRST_FRAG        0x04000000UL
-#define SBAL_FLAGS_MIDDLE_FRAG       0x08000000UL
-#define SBAL_FLAGS_LAST_FRAG         0x0c000000UL
-#define SBAL_FLAGS_LAST_ENTRY        0x40000000UL
-#define SBAL_FLAGS_CONTIGUOUS        0x20000000UL
+#define SBAL_FLAGS_FIRST_FRAG           0x04000000UL
+#define SBAL_FLAGS_MIDDLE_FRAG          0x08000000UL
+#define SBAL_FLAGS_LAST_FRAG            0x0c000000UL
+#define SBAL_FLAGS_LAST_ENTRY           0x40000000UL
+#define SBAL_FLAGS_CONTIGUOUS           0x20000000UL
 
-#define SBAL_FLAGS0_DATA_CONTINUATION 0x20UL
+#define SBAL_FLAGS0_DATA_CONTINUATION   0x20UL
 
 /* Awesome OpenFCP extensions */
-#define SBAL_FLAGS0_TYPE_STATUS       0x00UL
-#define SBAL_FLAGS0_TYPE_WRITE        0x08UL
-#define SBAL_FLAGS0_TYPE_READ         0x10UL
-#define SBAL_FLAGS0_TYPE_WRITE_READ   0x18UL
-#define SBAL_FLAGS0_MORE_SBALS        0x04UL
-#define SBAL_FLAGS0_COMMAND           0x02UL
-#define SBAL_FLAGS0_LAST_SBAL         0x00UL
-#define SBAL_FLAGS0_ONLY_SBAL         SBAL_FLAGS0_COMMAND
-#define SBAL_FLAGS0_MIDDLE_SBAL       SBAL_FLAGS0_MORE_SBALS
-#define SBAL_FLAGS0_FIRST_SBAL        SBAL_FLAGS0_MORE_SBALS | SBAL_FLAGS0_COMMAND
-/* Naught of interest beyond this point */
-
-#define SBAL_FLAGS0_PCI         0x40
+#define SBAL_FLAGS0_TYPE_STATUS         0x00UL
+#define SBAL_FLAGS0_TYPE_WRITE          0x08UL
+#define SBAL_FLAGS0_TYPE_READ           0x10UL
+#define SBAL_FLAGS0_TYPE_WRITE_READ     0x18UL
+#define SBAL_FLAGS0_MORE_SBALS          0x04UL
+#define SBAL_FLAGS0_COMMAND             0x02UL
+#define SBAL_FLAGS0_LAST_SBAL           0x00UL
+#define SBAL_FLAGS0_ONLY_SBAL           SBAL_FLAGS0_COMMAND
+#define SBAL_FLAGS0_MIDDLE_SBAL         SBAL_FLAGS0_MORE_SBALS
+#define SBAL_FLAGS0_FIRST_SBAL SBAL_FLAGS0_MORE_SBALS | SBAL_FLAGS0_COMMAND
+#define SBAL_FLAGS0_PCI                 0x40
+
+/**
+ * struct sbal_sbalf_0 - sbal flags for sbale 0
+ * @pci: PCI indicator
+ * @cont: data continuation
+ * @sbtype: storage-block type (FCP)
+ */
 struct sbal_sbalf_0 {
-        unsigned char res1  : 1;   /* reserved */
-        unsigned char pci   : 1;   /* PCI indicator */
-        unsigned char cont  : 1;   /* data continuation */
-        unsigned char sbtype: 2;   /* storage-block type (OpenFCP) */
-        unsigned char res2  : 3;   /* reserved */
+        u8        : 1;
+        u8 pci    : 1;
+        u8 cont   : 1;
+        u8 sbtype : 2;
+        u8        : 3;
 } __attribute__ ((packed));
 
+/**
+ * struct sbal_sbalf_1 - sbal flags for sbale 1
+ * @key: storage key
+ */
 struct sbal_sbalf_1 {
-        unsigned char res1  : 4;   /* reserved */
-        unsigned char key   : 4;   /* storage key */
+        u8     : 4;
+        u8 key : 4;
 } __attribute__ ((packed));
 
+/**
+ * struct sbal_sbalf_14 - sbal flags for sbale 14
+ * @erridx: error index
+ */
 struct sbal_sbalf_14 {
-        unsigned char res1   : 4;  /* reserved */
-        unsigned char erridx : 4;  /* error index */
+        u8        : 4;
+        u8 erridx : 4;
 } __attribute__ ((packed));
 
+/**
+ * struct sbal_sbalf_15 - sbal flags for sbale 15
+ * @reason: reason for error state
+ */
 struct sbal_sbalf_15 {
-        unsigned char reason;      /* reserved */
+        u8 reason;
 } __attribute__ ((packed));
 
+/**
+ * union sbal_sbalf - storage block address list flags
+ * @i0: sbalf0
+ * @i1: sbalf1
+ * @i14: sbalf14
+ * @i15: sblaf15
+ * @value: raw value
+ */
 union sbal_sbalf {
         struct sbal_sbalf_0  i0;
         struct sbal_sbalf_1  i1;
         struct sbal_sbalf_14 i14;
         struct sbal_sbalf_15 i15;
-        unsigned char value;
+        u8 value;
 };
 
-struct sbal_element {
-        union {
-                struct sbal_flags  bits;       /* flags */
-                unsigned char value;
-        } flags;
-        unsigned int  res1  : 16;   /* reserved */
-        union sbal_sbalf  sbalf;       /* SBAL flags */
-        unsigned int  res2  : 16;  /* reserved */
-        unsigned int  count : 16;  /* data count */
-#ifdef QDIO_32_BIT
-        unsigned long res3;        /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long addr;        /* absolute data address */
-} __attribute__ ((packed,aligned(16)));
+/**
+ * struct qdio_buffer_element - SBAL entry
+ * @flags: flags
+ * @length: length
+ * @addr: address
+*/
+struct qdio_buffer_element {
+        u32 flags;
+        u32 length;
+#ifdef CONFIG_32BIT
+        /* private: */
+        void *reserved;
+        /* public: */
+#endif
+        void *addr;
+} __attribute__ ((packed, aligned(16)));
 
-/*
- * strorage-block access-list (SBAL)
+/**
+ * struct qdio_buffer - storage block address list (SBAL)
+ * @element: SBAL entries
  */
-struct sbal {
-        struct sbal_element element[QDIO_MAX_ELEMENTS_PER_BUFFER];
-} __attribute__ ((packed,aligned(256)));
+struct qdio_buffer {
+        struct qdio_buffer_element element[QDIO_MAX_ELEMENTS_PER_BUFFER];
+} __attribute__ ((packed, aligned(256)));
 
-/*
- * storage-list (SL)
+/**
+ * struct sl_element - storage list entry
+ * @sbal: absolute SBAL address
  */
 struct sl_element {
-#ifdef QDIO_32_BIT
-        unsigned long res;     /* reserved */
-#endif /* QDIO_32_BIT */
-        unsigned long sbal;    /* absolute SBAL address */
+#ifdef CONFIG_32BIT
+        /* private: */
+        unsigned long reserved;
+        /* public: */
+#endif
+        unsigned long sbal;
 } __attribute__ ((packed));
 
+/**
+ * struct sl - storage list (SL)
+ * @element: SL entries
+ */
 struct sl {
         struct sl_element element[QDIO_MAX_BUFFERS_PER_Q];
-} __attribute__ ((packed,aligned(1024)));
+} __attribute__ ((packed, aligned(1024)));
 
-/*
- * storage-list-state block (SLSB)
+/**
+ * struct slsb - storage list state block (SLSB)
+ * @val: state per buffer
  */
-struct slsb_flags {
-        unsigned char owner  : 2;   /* SBAL owner */
-        unsigned char type   : 1;   /* buffer type */
-        unsigned char state  : 5;   /* processing state */
+struct slsb {
+        u8 val[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(256)));
+
+struct qdio_ssqd_desc {
+        u8 flags;
+        u8:8;
+        u16 sch;
+        u8 qfmt;
+        u8 parm;
+        u8 qdioac1;
+        u8 sch_class;
+        u8 pcnt;
+        u8 icnt;
+        u8:8;
+        u8 ocnt;
+        u8:8;
+        u8 mbccnt;
+        u16 qdioac2;
+        u64 sch_token;
+        u64:64;
 } __attribute__ ((packed));
 
+/* params are: ccw_device, qdio_error, queue_number,
+   first element processed, number of elements processed, int_parm */
+typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
+                            int, int, unsigned long);
 
-struct slsb {
-        union {
-                unsigned char val[QDIO_MAX_BUFFERS_PER_Q];
-                struct slsb_flags flags[QDIO_MAX_BUFFERS_PER_Q];
-        } acc;
-} __attribute__ ((packed,aligned(256)));
+/* qdio errors reported to the upper-layer program */
+#define QDIO_ERROR_SIGA_ACCESS_EXCEPTION        0x10
+#define QDIO_ERROR_SIGA_BUSY                    0x20
+#define QDIO_ERROR_ACTIVATE_CHECK_CONDITION     0x40
+#define QDIO_ERROR_SLSB_STATE                   0x80
 
-/*
- * SLSB values
+/* for qdio_initialize */
+#define QDIO_INBOUND_0COPY_SBALS                0x01
+#define QDIO_OUTBOUND_0COPY_SBALS               0x02
+#define QDIO_USE_OUTBOUND_PCIS                  0x04
+
+/* for qdio_cleanup */
+#define QDIO_FLAG_CLEANUP_USING_CLEAR           0x01
+#define QDIO_FLAG_CLEANUP_USING_HALT            0x02
+
+/**
+ * struct qdio_initialize - qdio initalization data
+ * @cdev: associated ccw device
+ * @q_format: queue format
+ * @adapter_name: name for the adapter
+ * @qib_param_field_format: format for qib_parm_field
+ * @qib_param_field: pointer to 128 bytes or NULL, if no param field
+ * @input_slib_elements: pointer to no_input_qs * 128 words of data or NULL
+ * @output_slib_elements: pointer to no_output_qs * 128 words of data or NULL
+ * @no_input_qs: number of input queues
+ * @no_output_qs: number of output queues
+ * @input_handler: handler to be called for input queues
+ * @output_handler: handler to be called for output queues
+ * @int_parm: interruption parameter
+ * @flags: initialization flags
+ * @input_sbal_addr_array:  address of no_input_qs * 128 pointers
+ * @output_sbal_addr_array: address of no_output_qs * 128 pointers
  */
-#define SLSB_OWNER_PROG              1
-#define SLSB_OWNER_CU                2
-
-#define SLSB_TYPE_INPUT              0
-#define SLSB_TYPE_OUTPUT             1
-
-#define SLSB_STATE_NOT_INIT          0
-#define SLSB_STATE_EMPTY             1
-#define SLSB_STATE_PRIMED            2
-#define SLSB_STATE_HALTED          0xe
-#define SLSB_STATE_ERROR           0xf
-
-#define SLSB_P_INPUT_NOT_INIT     0x80
-#define SLSB_P_INPUT_PROCESSING   0x81
-#define SLSB_CU_INPUT_EMPTY       0x41
-#define SLSB_P_INPUT_PRIMED       0x82
-#define SLSB_P_INPUT_HALTED       0x8E
-#define SLSB_P_INPUT_ERROR        0x8F
-
-#define SLSB_P_OUTPUT_NOT_INIT    0xA0
-#define SLSB_P_OUTPUT_EMPTY       0xA1
-#define SLSB_CU_OUTPUT_PRIMED     0x62
-#define SLSB_P_OUTPUT_HALTED      0xAE
-#define SLSB_P_OUTPUT_ERROR       0xAF
-
-#define SLSB_ERROR_DURING_LOOKUP  0xFF
+struct qdio_initialize {
+        struct ccw_device *cdev;
+        unsigned char q_format;
+        unsigned char adapter_name[8];
+        unsigned int qib_param_field_format;
+        unsigned char *qib_param_field;
+        unsigned long *input_slib_elements;
+        unsigned long *output_slib_elements;
+        unsigned int no_input_qs;
+        unsigned int no_output_qs;
+        qdio_handler_t *input_handler;
+        qdio_handler_t *output_handler;
+        unsigned long int_parm;
+        unsigned long flags;
+        void **input_sbal_addr_array;
+        void **output_sbal_addr_array;
+};
+
+#define QDIO_STATE_INACTIVE             0x00000002 /* after qdio_cleanup */
+#define QDIO_STATE_ESTABLISHED          0x00000004 /* after qdio_establish */
+#define QDIO_STATE_ACTIVE               0x00000008 /* after qdio_activate */
+#define QDIO_STATE_STOPPED              0x00000010 /* after queues went down */
+
+#define QDIO_FLAG_SYNC_INPUT            0x01
+#define QDIO_FLAG_SYNC_OUTPUT           0x02
+#define QDIO_FLAG_PCI_OUT               0x10
+
+extern int qdio_initialize(struct qdio_initialize *init_data);
+extern int qdio_allocate(struct qdio_initialize *init_data);
+extern int qdio_establish(struct qdio_initialize *init_data);
+extern int qdio_activate(struct ccw_device *);
+
+extern int do_QDIO(struct ccw_device*, unsigned int flags,
+                   int q_nr, int qidx, int count);
+extern int qdio_cleanup(struct ccw_device*, int how);
+extern int qdio_shutdown(struct ccw_device*, int how);
+extern int qdio_free(struct ccw_device *);
+extern struct qdio_ssqd_desc *qdio_get_ssqd_desc(struct ccw_device *cdev);
 
 #endif /* __QDIO_H__ */
diff --git a/include/asm-s390/schid.h b/include/asm-s390/schid.h
new file mode 100644
index 000000000000..7bdc0fe15691
--- /dev/null
+++ b/include/asm-s390/schid.h
@@ -0,0 +1,31 @@
+#ifndef ASM_SCHID_H
+#define ASM_SCHID_H
+
+struct subchannel_id {
+        __u32 cssid : 8;
+        __u32 : 4;
+        __u32 m : 1;
+        __u32 ssid : 2;
+        __u32 one : 1;
+        __u32 sch_no : 16;
+} __attribute__ ((packed, aligned(4)));
+
+#ifdef __KERNEL__
+
+/* Helper function for sane state of pre-allocated subchannel_id. */
+static inline void
+init_subchannel_id(struct subchannel_id *schid)
+{
+        memset(schid, 0, sizeof(struct subchannel_id));
+        schid->one = 1;
+}
+
+static inline int
+schid_equal(struct subchannel_id *schid1, struct subchannel_id *schid2)
+{
+        return !memcmp(schid1, schid2, sizeof(struct subchannel_id));
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* ASM_SCHID_H */
diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h
index b5f2843013a3..fed7bee650a0 100644
--- a/include/asm-s390/sclp.h
+++ b/include/asm-s390/sclp.h
@@ -45,9 +45,9 @@ struct sclp_cpu_info {
 int sclp_get_cpu_info(struct sclp_cpu_info *info);
 int sclp_cpu_configure(u8 cpu);
 int sclp_cpu_deconfigure(u8 cpu);
-void sclp_read_info_early(void);
 void sclp_facilities_detect(void);
-unsigned long long sclp_memory_detect(void);
+unsigned long long sclp_get_rnmax(void);
+unsigned long long sclp_get_rzm(void);
 int sclp_sdias_blk_count(void);
 int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
 int sclp_chp_configure(struct chp_id chpid);
diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h
index ba69674012a7..4ba14e463e83 100644
--- a/include/asm-s390/setup.h
+++ b/include/asm-s390/setup.h
@@ -8,14 +8,16 @@
 #ifndef _ASM_S390_SETUP_H
 #define _ASM_S390_SETUP_H
 
-#define COMMAND_LINE_SIZE       896
+#define COMMAND_LINE_SIZE       1024
+
+#define ARCH_COMMAND_LINE_SIZE  896
 
 #ifdef __KERNEL__
 
 #include <asm/types.h>
 
 #define PARMAREA                0x10400
-#define MEMORY_CHUNKS           16      /* max 0x7fff */
+#define MEMORY_CHUNKS           256
 
 #ifndef __ASSEMBLY__
 
@@ -36,12 +38,14 @@
 struct mem_chunk {
         unsigned long addr;
         unsigned long size;
-        unsigned long type;
+        int type;
 };
 
 extern struct mem_chunk memory_chunk[];
 extern unsigned long real_memory_size;
 
+void detect_memory_layout(struct mem_chunk chunk[]);
+
 #ifdef CONFIG_S390_SWITCH_AMODE
 extern unsigned int switch_amode;
 #else
@@ -74,7 +78,6 @@ extern unsigned long machine_flags;
 
 #define MACHINE_IS_VM           (machine_flags & MACHINE_FLAG_VM)
 #define MACHINE_IS_KVM          (machine_flags & MACHINE_FLAG_KVM)
-#define MACHINE_IS_P390         (machine_flags & MACHINE_FLAG_P390)
 #define MACHINE_HAS_DIAG9C      (machine_flags & MACHINE_FLAG_DIAG9C)
 
 #ifndef __s390x__
@@ -97,7 +100,6 @@ extern unsigned long machine_flags;
 #define MACHINE_HAS_PFMF        (machine_flags & MACHINE_FLAG_PFMF)
 #endif /* __s390x__ */
 
-#define MACHINE_HAS_SCLP        (!MACHINE_IS_P390)
 #define ZFCPDUMP_HSA_SIZE       (32UL<<20)
 
 /*
diff --git a/include/asm-s390/sparsemem.h b/include/asm-s390/sparsemem.h
index 06dfdab6c0e8..545d219e6a2d 100644
--- a/include/asm-s390/sparsemem.h
+++ b/include/asm-s390/sparsemem.h
@@ -1,15 +1,15 @@
 #ifndef _ASM_S390_SPARSEMEM_H
 #define _ASM_S390_SPARSEMEM_H
 
-#define SECTION_SIZE_BITS       25
-
 #ifdef CONFIG_64BIT
 
+#define SECTION_SIZE_BITS       28
 #define MAX_PHYSADDR_BITS       42
 #define MAX_PHYSMEM_BITS        42
 
 #else
 
+#define SECTION_SIZE_BITS       25
 #define MAX_PHYSADDR_BITS       31
 #define MAX_PHYSMEM_BITS        31
 
diff --git a/include/asm-s390/timer.h b/include/asm-s390/timer.h
index adb34860a543..d98d79e35cd6 100644
--- a/include/asm-s390/timer.h
+++ b/include/asm-s390/timer.h
@@ -48,6 +48,18 @@ extern int del_virt_timer(struct vtimer_list *timer);
 extern void init_cpu_vtimer(void);
 extern void vtime_init(void);
 
+#ifdef CONFIG_VIRT_TIMER
+
+extern void vtime_start_cpu_timer(void);
+extern void vtime_stop_cpu_timer(void);
+
+#else
+
+static inline void vtime_start_cpu_timer(void) { }
+static inline void vtime_stop_cpu_timer(void) { }
+
+#endif /* CONFIG_VIRT_TIMER */
+
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_S390_TIMER_H */
diff --git a/include/asm-s390/zcrypt.h b/include/asm-s390/zcrypt.h
index f228f1b86877..00d3bbd44117 100644
--- a/include/asm-s390/zcrypt.h
+++ b/include/asm-s390/zcrypt.h
@@ -29,7 +29,7 @@
 
 #define ZCRYPT_VERSION 2
 #define ZCRYPT_RELEASE 1
-#define ZCRYPT_VARIANT 0
+#define ZCRYPT_VARIANT 1
 
 #include <linux/ioctl.h>
 #include <linux/compiler.h>
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index 9c8d34b07ebf..593343cd26ee 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -26,18 +26,10 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define NO_PROC_ID      (-1)
 
-struct smp_fn_call_struct {
-        spinlock_t lock;
-        atomic_t   finished;
-        void (*fn)(void *);
-        void *data;
-};
-
-extern struct smp_fn_call_struct smp_fn_call;
-
 #define SMP_MSG_FUNCTION        0
 #define SMP_MSG_RESCHEDULE      1
-#define SMP_MSG_NR              2
+#define SMP_MSG_FUNCTION_SINGLE 2
+#define SMP_MSG_NR              3
 
 void plat_smp_setup(void);
 void plat_prepare_cpus(unsigned int max_cpus);
@@ -46,6 +38,8 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
 void plat_send_ipi(unsigned int cpu, unsigned int message);
 int plat_register_ipi_handler(unsigned int message,
                               void (*handler)(void *), void *arg);
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
 
 #else
 
diff --git a/include/asm-sparc/smp.h b/include/asm-sparc/smp.h
index e6d561599726..b61e74bea06a 100644
--- a/include/asm-sparc/smp.h
+++ b/include/asm-sparc/smp.h
@@ -72,7 +72,7 @@ static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
                            unsigned long arg3, unsigned long arg4, unsigned long arg5)
 { smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
 
-static inline int smp_call_function(void (*func)(void *info), void *info, int nonatomic, int wait)
+static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
 {
         xc1((smpfunc_t)func, (unsigned long)info);
         return 0;
diff --git a/include/asm-sparc64/ftrace.h b/include/asm-sparc64/ftrace.h
new file mode 100644
index 000000000000..d27716cd38c1
--- /dev/null
+++ b/include/asm-sparc64/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_SPARC64_FTRACE
+#define _ASM_SPARC64_FTRACE
+
+#ifdef CONFIG_MCOUNT
+#define MCOUNT_ADDR             ((long)(_mcount))
+#define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#endif
+
+#endif
+
+#endif /* _ASM_SPARC64_FTRACE */
diff --git a/include/asm-x86/alternative.h b/include/asm-x86/alternative.h
index 1f6a9ca10126..f6aa18eadf71 100644
--- a/include/asm-x86/alternative.h
+++ b/include/asm-x86/alternative.h
@@ -72,6 +72,8 @@ static inline void alternatives_smp_module_del(struct module *mod) {}
 static inline void alternatives_smp_switch(int smp) {}
 #endif  /* CONFIG_SMP */
 
+const unsigned char *const *find_nop_table(void);
+
 /*
  * Alternative instructions for different CPU types or capabilities.
  *
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
index a29807737d3d..4e2c1e517f06 100644
--- a/include/asm-x86/apic.h
+++ b/include/asm-x86/apic.h
@@ -121,12 +121,17 @@ extern void enable_NMI_through_LVT0(void);
  */
 #ifdef CONFIG_X86_64
 extern void early_init_lapic_mapping(void);
+extern int apic_is_clustered_box(void);
+#else
+static inline int apic_is_clustered_box(void)
+{
+        return 0;
+}
 #endif
 
 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 
-extern int apic_is_clustered_box(void);
 
 #else /* !CONFIG_X86_LOCAL_APIC */
 static inline void lapic_shutdown(void) { }
diff --git a/include/asm-x86/asm.h b/include/asm-x86/asm.h
index 70939820c55f..97220321f39d 100644
--- a/include/asm-x86/asm.h
+++ b/include/asm-x86/asm.h
@@ -3,8 +3,10 @@
 
 #ifdef __ASSEMBLY__
 # define __ASM_FORM(x)  x
+# define __ASM_EX_SEC   .section __ex_table
 #else
 # define __ASM_FORM(x)  " " #x " "
+# define __ASM_EX_SEC   " .section __ex_table,\"a\"\n"
 #endif
 
 #ifdef CONFIG_X86_32
@@ -14,6 +16,7 @@
 #endif
 
 #define __ASM_SIZE(inst)        __ASM_SEL(inst##l, inst##q)
+#define __ASM_REG(reg)          __ASM_SEL(e##reg, r##reg)
 
 #define _ASM_PTR        __ASM_SEL(.long, .quad)
 #define _ASM_ALIGN      __ASM_SEL(.balign 4, .balign 8)
@@ -24,10 +27,14 @@
 #define _ASM_ADD        __ASM_SIZE(add)
 #define _ASM_SUB        __ASM_SIZE(sub)
 #define _ASM_XADD       __ASM_SIZE(xadd)
+#define _ASM_AX         __ASM_REG(ax)
+#define _ASM_BX         __ASM_REG(bx)
+#define _ASM_CX         __ASM_REG(cx)
+#define _ASM_DX         __ASM_REG(dx)
 
 /* Exception table entry */
 # define _ASM_EXTABLE(from,to) \
-        " .section __ex_table,\"a\"\n" \
+        __ASM_EX_SEC    \
         _ASM_ALIGN "\n" \
         _ASM_PTR #from "," #to "\n" \
         " .previous\n"
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 84a56da397b1..75ef959db329 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -74,8 +74,8 @@
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
 #define X86_FEATURE_PEBS        (3*32+12)  /* Precise-Event Based Sampling */
 #define X86_FEATURE_BTS         (3*32+13)  /* Branch Trace Store */
-/* 14 free */
-/* 15 free */
+#define X86_FEATURE_SYSCALL32   (3*32+14)  /* syscall in ia32 userspace */
+#define X86_FEATURE_SYSENTER32  (3*32+15)  /* sysenter in ia32 userspace */
 #define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well on this CPU */
 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
diff --git a/include/asm-x86/dwarf2.h b/include/asm-x86/dwarf2.h
index b3cbb0ccae18..738bb9fb3e53 100644
--- a/include/asm-x86/dwarf2.h
+++ b/include/asm-x86/dwarf2.h
@@ -1,5 +1,61 @@
-#ifdef CONFIG_X86_32
-# include "dwarf2_32.h"
+#ifndef _DWARF2_H
+#define _DWARF2_H
+
+#ifndef __ASSEMBLY__
+#warning "asm/dwarf2.h should be only included in pure assembly files"
+#endif
+
+/*
+   Macros for dwarf2 CFI unwind table entries.
+   See "as.info" for details on these pseudo ops. Unfortunately
+   they are only supported in very new binutils, so define them
+   away for older version.
+ */
+
+#ifdef CONFIG_AS_CFI
+
+#define CFI_STARTPROC .cfi_startproc
+#define CFI_ENDPROC .cfi_endproc
+#define CFI_DEF_CFA .cfi_def_cfa
+#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
+#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
+#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
+#define CFI_OFFSET .cfi_offset
+#define CFI_REL_OFFSET .cfi_rel_offset
+#define CFI_REGISTER .cfi_register
+#define CFI_RESTORE .cfi_restore
+#define CFI_REMEMBER_STATE .cfi_remember_state
+#define CFI_RESTORE_STATE .cfi_restore_state
+#define CFI_UNDEFINED .cfi_undefined
+
+#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
+#define CFI_SIGNAL_FRAME .cfi_signal_frame
+#else
+#define CFI_SIGNAL_FRAME
+#endif
+
 #else
-# include "dwarf2_64.h"
+
+/* Due to the structure of pre-exisiting code, don't use assembler line
+   comment character # to ignore the arguments. Instead, use a dummy macro. */
+.macro cfi_ignore a=0, b=0, c=0, d=0
+.endm
+
+#define CFI_STARTPROC   cfi_ignore
+#define CFI_ENDPROC     cfi_ignore
+#define CFI_DEF_CFA     cfi_ignore
+#define CFI_DEF_CFA_REGISTER    cfi_ignore
+#define CFI_DEF_CFA_OFFSET      cfi_ignore
+#define CFI_ADJUST_CFA_OFFSET   cfi_ignore
+#define CFI_OFFSET      cfi_ignore
+#define CFI_REL_OFFSET  cfi_ignore
+#define CFI_REGISTER    cfi_ignore
+#define CFI_RESTORE     cfi_ignore
+#define CFI_REMEMBER_STATE cfi_ignore
+#define CFI_RESTORE_STATE cfi_ignore
+#define CFI_UNDEFINED cfi_ignore
+#define CFI_SIGNAL_FRAME cfi_ignore
+
+#endif
+
 #endif
diff --git a/include/asm-x86/dwarf2_32.h b/include/asm-x86/dwarf2_32.h
deleted file mode 100644
index 6d66398a307d..000000000000
--- a/include/asm-x86/dwarf2_32.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef _DWARF2_H
-#define _DWARF2_H
-
-#ifndef __ASSEMBLY__
-#warning "asm/dwarf2.h should be only included in pure assembly files"
-#endif
-
-/*
-   Macros for dwarf2 CFI unwind table entries.
-   See "as.info" for details on these pseudo ops. Unfortunately
-   they are only supported in very new binutils, so define them
-   away for older version.
- */
-
-#ifdef CONFIG_UNWIND_INFO
-
-#define CFI_STARTPROC .cfi_startproc
-#define CFI_ENDPROC .cfi_endproc
-#define CFI_DEF_CFA .cfi_def_cfa
-#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
-#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
-#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
-#define CFI_OFFSET .cfi_offset
-#define CFI_REL_OFFSET .cfi_rel_offset
-#define CFI_REGISTER .cfi_register
-#define CFI_RESTORE .cfi_restore
-#define CFI_REMEMBER_STATE .cfi_remember_state
-#define CFI_RESTORE_STATE .cfi_restore_state
-#define CFI_UNDEFINED .cfi_undefined
-
-#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
-#define CFI_SIGNAL_FRAME .cfi_signal_frame
-#else
-#define CFI_SIGNAL_FRAME
-#endif
-
-#else
-
-/* Due to the structure of pre-exisiting code, don't use assembler line
-   comment character # to ignore the arguments. Instead, use a dummy macro. */
-.macro ignore a=0, b=0, c=0, d=0
-.endm
-
-#define CFI_STARTPROC   ignore
-#define CFI_ENDPROC     ignore
-#define CFI_DEF_CFA     ignore
-#define CFI_DEF_CFA_REGISTER    ignore
-#define CFI_DEF_CFA_OFFSET      ignore
-#define CFI_ADJUST_CFA_OFFSET   ignore
-#define CFI_OFFSET      ignore
-#define CFI_REL_OFFSET  ignore
-#define CFI_REGISTER    ignore
-#define CFI_RESTORE     ignore
-#define CFI_REMEMBER_STATE ignore
-#define CFI_RESTORE_STATE ignore
-#define CFI_UNDEFINED ignore
-#define CFI_SIGNAL_FRAME ignore
-
-#endif
-
-#endif
diff --git a/include/asm-x86/dwarf2_64.h b/include/asm-x86/dwarf2_64.h
deleted file mode 100644
index c950519a264d..000000000000
--- a/include/asm-x86/dwarf2_64.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _DWARF2_H
-#define _DWARF2_H 1
-
-#ifndef __ASSEMBLY__
-#warning "asm/dwarf2.h should be only included in pure assembly files"
-#endif
-
-/*
-   Macros for dwarf2 CFI unwind table entries.
-   See "as.info" for details on these pseudo ops. Unfortunately
-   they are only supported in very new binutils, so define them
-   away for older version.
- */
-
-#ifdef CONFIG_AS_CFI
-
-#define CFI_STARTPROC .cfi_startproc
-#define CFI_ENDPROC .cfi_endproc
-#define CFI_DEF_CFA .cfi_def_cfa
-#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
-#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
-#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
-#define CFI_OFFSET .cfi_offset
-#define CFI_REL_OFFSET .cfi_rel_offset
-#define CFI_REGISTER .cfi_register
-#define CFI_RESTORE .cfi_restore
-#define CFI_REMEMBER_STATE .cfi_remember_state
-#define CFI_RESTORE_STATE .cfi_restore_state
-#define CFI_UNDEFINED .cfi_undefined
-#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
-#define CFI_SIGNAL_FRAME .cfi_signal_frame
-#else
-#define CFI_SIGNAL_FRAME
-#endif
-
-#else
-
-/* use assembler line comment character # to ignore the arguments. */
-#define CFI_STARTPROC   #
-#define CFI_ENDPROC     #
-#define CFI_DEF_CFA     #
-#define CFI_DEF_CFA_REGISTER    #
-#define CFI_DEF_CFA_OFFSET      #
-#define CFI_ADJUST_CFA_OFFSET   #
-#define CFI_OFFSET      #
-#define CFI_REL_OFFSET  #
-#define CFI_REGISTER    #
-#define CFI_RESTORE     #
-#define CFI_REMEMBER_STATE      #
-#define CFI_RESTORE_STATE       #
-#define CFI_UNDEFINED   #
-#define CFI_SIGNAL_FRAME        #
-
-#endif
-
-#endif
diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h
index 4b26604b3c19..06633b01dd5b 100644
--- a/include/asm-x86/e820.h
+++ b/include/asm-x86/e820.h
@@ -59,7 +59,10 @@ struct e820map {
         struct e820entry map[E820_X_MAX];
 };
 
+#ifdef __KERNEL__
+/* see comment in arch/x86/kernel/e820.c */
 extern struct e820map e820;
+extern struct e820map e820_saved;
 
 extern int e820_any_mapped(u64 start, u64 end, unsigned type);
 extern int e820_all_mapped(u64 start, u64 end, unsigned type);
@@ -97,7 +100,8 @@ extern void free_early(u64 start, u64 end);
 extern void early_res_to_bootmem(u64 start, u64 end);
 extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align);
 
-extern unsigned long e820_end_of_ram(void);
+extern unsigned long e820_end_of_ram_pfn(void);
+extern unsigned long e820_end_of_low_ram_pfn(void);
 extern int e820_find_active_region(const struct e820entry *ei,
                                   unsigned long start_pfn,
                                   unsigned long last_pfn,
@@ -112,7 +116,7 @@ extern void setup_memory_map(void);
 extern char *default_machine_specific_memory_setup(void);
 extern char *machine_specific_memory_setup(void);
 extern char *memory_setup(void);
-
+#endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
 
 #define ISA_START_ADDRESS       0xa0000
diff --git a/include/asm-x86/fixmap_64.h b/include/asm-x86/fixmap_64.h
index 1a0b61eb02ff..00f3d74a0524 100644
--- a/include/asm-x86/fixmap_64.h
+++ b/include/asm-x86/fixmap_64.h
@@ -12,6 +12,7 @@
 #define _ASM_FIXMAP_64_H
 
 #include <linux/kernel.h>
+#include <asm/acpi.h>
 #include <asm/apicdef.h>
 #include <asm/page.h>
 #include <asm/vsyscall.h>
@@ -39,7 +40,6 @@ enum fixed_addresses {
         VSYSCALL_HPET,
         FIX_DBGP_BASE,
         FIX_EARLYCON_MEM_BASE,
-        FIX_HPET_BASE,
         FIX_APIC_BASE,  /* local (CPU) APIC) -- required for SMP or not */
         FIX_IO_APIC_BASE_0,
         FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
@@ -49,6 +49,10 @@ enum fixed_addresses {
 #ifdef CONFIG_PARAVIRT
         FIX_PARAVIRT_BOOTMAP,
 #endif
+#ifdef CONFIG_ACPI
+        FIX_ACPI_BEGIN,
+        FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
+#endif
 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
         FIX_OHCI1394_BASE,
 #endif
diff --git a/include/asm-x86/ftrace.h b/include/asm-x86/ftrace.h
new file mode 100644
index 000000000000..c184441133f2
--- /dev/null
+++ b/include/asm-x86/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_X86_FTRACE
+#define _ASM_SPARC64_FTRACE
+
+#ifdef CONFIG_FTRACE
+#define MCOUNT_ADDR             ((long)(mcount))
+#define MCOUNT_INSN_SIZE        5 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void mcount(void);
+#endif
+
+#endif /* CONFIG_FTRACE */
+
+#endif /* _ASM_X86_FTRACE */
diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h
index 417f76ea677b..33b9aeeb35a2 100644
--- a/include/asm-x86/gart.h
+++ b/include/asm-x86/gart.h
@@ -1,40 +1,14 @@
-#ifndef _ASM_X8664_IOMMU_H
-#define _ASM_X8664_IOMMU_H 1
+#ifndef _ASM_X8664_GART_H
+#define _ASM_X8664_GART_H 1
 
 #include <asm/e820.h>
+#include <asm/iommu.h>
 
-extern void pci_iommu_shutdown(void);
-extern void no_iommu_init(void);
-extern int force_iommu, no_iommu;
-extern int iommu_detected;
-extern int agp_amd64_init(void);
-#ifdef CONFIG_GART_IOMMU
-extern void gart_iommu_init(void);
-extern void gart_iommu_shutdown(void);
-extern void __init gart_parse_options(char *);
-extern void early_gart_iommu_check(void);
-extern void gart_iommu_hole_init(void);
 extern void set_up_gart_resume(u32, u32);
+
 extern int fallback_aper_order;
 extern int fallback_aper_force;
-extern int gart_iommu_aperture;
-extern int gart_iommu_aperture_allowed;
-extern int gart_iommu_aperture_disabled;
 extern int fix_aperture;
-#else
-#define gart_iommu_aperture             0
-#define gart_iommu_aperture_allowed     0
-#define gart_iommu_aperture_disabled    1
-
-static inline void early_gart_iommu_check(void)
-{
-}
-
-static inline void gart_iommu_shutdown(void)
-{
-}
-
-#endif
 
 /* PTE bits. */
 #define GPTE_VALID      1
diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h
index 6a9b4ac59bf7..82f1ac641bd7 100644
--- a/include/asm-x86/hpet.h
+++ b/include/asm-x86/hpet.h
@@ -86,8 +86,8 @@ extern void hpet_unregister_irq_handler(rtc_irq_handler handler);
 #else /* CONFIG_HPET_TIMER */
 
 static inline int hpet_enable(void) { return 0; }
-static inline unsigned long hpet_readl(unsigned long a) { return 0; }
 static inline int is_hpet_enabled(void) { return 0; }
+#define hpet_readl(a) 0
 
 #endif
 #endif /* ASM_X86_HPET_H */
diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h
index 18f067c310f7..77ba51df5668 100644
--- a/include/asm-x86/hw_irq.h
+++ b/include/asm-x86/hw_irq.h
@@ -48,6 +48,7 @@ extern void irq_move_cleanup_interrupt(void);
 extern void threshold_interrupt(void);
 
 extern void call_function_interrupt(void);
+extern void call_function_single_interrupt(void);
 
 /* PIC specific functions */
 extern void disable_8259A_irq(unsigned int irq);
diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h
index 07862fdd23c0..068c9a40aa5b 100644
--- a/include/asm-x86/iommu.h
+++ b/include/asm-x86/iommu.h
@@ -1,29 +1,34 @@
-#ifndef _ASM_X8664_GART_H
-#define _ASM_X8664_GART_H 1
+#ifndef _ASM_X8664_IOMMU_H
+#define _ASM_X8664_IOMMU_H 1
 
 extern void pci_iommu_shutdown(void);
 extern void no_iommu_init(void);
 extern int force_iommu, no_iommu;
 extern int iommu_detected;
-#ifdef CONFIG_IOMMU
+
+#ifdef CONFIG_GART_IOMMU
+extern int gart_iommu_aperture;
+extern int gart_iommu_aperture_allowed;
+extern int gart_iommu_aperture_disabled;
+
+extern void early_gart_iommu_check(void);
 extern void gart_iommu_init(void);
 extern void gart_iommu_shutdown(void);
 extern void __init gart_parse_options(char *);
-extern void iommu_hole_init(void);
-extern int fallback_aper_order;
-extern int fallback_aper_force;
-extern int iommu_aperture;
-extern int iommu_aperture_allowed;
-extern int iommu_aperture_disabled;
-extern int fix_aperture;
+extern void gart_iommu_hole_init(void);
+
 #else
-#define iommu_aperture 0
-#define iommu_aperture_allowed 0
+#define gart_iommu_aperture            0
+#define gart_iommu_aperture_allowed    0
+#define gart_iommu_aperture_disabled   1
 
-static inline void gart_iommu_shutdown(void)
+static inline void early_gart_iommu_check(void)
 {
 }
 
+static inline void gart_iommu_shutdown(void)
+{
+}
 #endif
 
 #endif
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
index b58581e2e24e..90b1d1f12f08 100644
--- a/include/asm-x86/irq_vectors.h
+++ b/include/asm-x86/irq_vectors.h
@@ -64,6 +64,7 @@
 # define INVALIDATE_TLB_VECTOR          0xfd
 # define RESCHEDULE_VECTOR              0xfc
 # define CALL_FUNCTION_VECTOR           0xfb
+# define CALL_FUNCTION_SINGLE_VECTOR    0xfa
 # define THERMAL_APIC_VECTOR            0xf0
 
 #else
@@ -72,6 +73,7 @@
 #define ERROR_APIC_VECTOR               0xfe
 #define RESCHEDULE_VECTOR               0xfd
 #define CALL_FUNCTION_VECTOR            0xfc
+#define CALL_FUNCTION_SINGLE_VECTOR     0xfb
 #define THERMAL_APIC_VECTOR             0xfa
 #define THRESHOLD_APIC_VECTOR           0xf9
 #define INVALIDATE_TLB_VECTOR_END       0xf7
@@ -107,9 +109,9 @@
 #define LAST_VM86_IRQ           15
 #define invalid_vm86_irq(irq)   ((irq) < 3 || (irq) > 15)
 
-#if !defined(CONFIG_X86_VISWS) && !defined(CONFIG_X86_VOYAGER)
+#if !defined(CONFIG_X86_VOYAGER)
 
-# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT)
+# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)
 
 #  define NR_IRQS               224
 
@@ -143,6 +145,7 @@
 #define VIC_RESCHEDULE_CPI              4
 #define VIC_ENABLE_IRQ_CPI              5
 #define VIC_CALL_FUNCTION_CPI           6
+#define VIC_CALL_FUNCTION_SINGLE_CPI    7
 
 /* Now the QIC CPIs:  Since we don't need the two initial levels,
  * these are 2 less than the VIC CPIs */
@@ -152,9 +155,10 @@
 #define QIC_RESCHEDULE_CPI              (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
 #define QIC_ENABLE_IRQ_CPI              (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
 #define QIC_CALL_FUNCTION_CPI           (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
+#define QIC_CALL_FUNCTION_SINGLE_CPI    (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)
 
 #define VIC_START_FAKE_CPI              VIC_TIMER_CPI
-#define VIC_END_FAKE_CPI                VIC_CALL_FUNCTION_CPI
+#define VIC_END_FAKE_CPI                VIC_CALL_FUNCTION_SINGLE_CPI
 
 /* this is the SYS_INT CPI. */
 #define VIC_SYS_INT                     8
diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h
index 17e7a1701c97..424acb48cd61 100644
--- a/include/asm-x86/irqflags.h
+++ b/include/asm-x86/irqflags.h
@@ -190,8 +190,6 @@ static inline void trace_hardirqs_fixup(void)
 #else
 
 #ifdef CONFIG_X86_64
-#define ARCH_TRACE_IRQS_ON              call trace_hardirqs_on_thunk
-#define ARCH_TRACE_IRQS_OFF             call trace_hardirqs_off_thunk
 #define ARCH_LOCKDEP_SYS_EXIT           call lockdep_sys_exit_thunk
 #define ARCH_LOCKDEP_SYS_EXIT_IRQ       \
         TRACE_IRQS_ON; \
@@ -203,24 +201,6 @@ static inline void trace_hardirqs_fixup(void)
         TRACE_IRQS_OFF;
 
 #else
-#define ARCH_TRACE_IRQS_ON                      \
-        pushl %eax;                             \
-        pushl %ecx;                             \
-        pushl %edx;                             \
-        call trace_hardirqs_on;                 \
-        popl %edx;                              \
-        popl %ecx;                              \
-        popl %eax;
-
-#define ARCH_TRACE_IRQS_OFF                     \
-        pushl %eax;                             \
-        pushl %ecx;                             \
-        pushl %edx;                             \
-        call trace_hardirqs_off;                \
-        popl %edx;                              \
-        popl %ecx;                              \
-        popl %eax;
-
 #define ARCH_LOCKDEP_SYS_EXIT                   \
         pushl %eax;                             \
         pushl %ecx;                             \
@@ -234,8 +214,8 @@ static inline void trace_hardirqs_fixup(void)
 #endif
 
 #ifdef CONFIG_TRACE_IRQFLAGS
-#  define TRACE_IRQS_ON         ARCH_TRACE_IRQS_ON
-#  define TRACE_IRQS_OFF        ARCH_TRACE_IRQS_OFF
+#  define TRACE_IRQS_ON         call trace_hardirqs_on_thunk;
+#  define TRACE_IRQS_OFF        call trace_hardirqs_off_thunk;
 #else
 #  define TRACE_IRQS_ON
 #  define TRACE_IRQS_OFF
diff --git a/include/asm-x86/mach-default/entry_arch.h b/include/asm-x86/mach-default/entry_arch.h
index bc861469bdba..9283b60a1dd2 100644
--- a/include/asm-x86/mach-default/entry_arch.h
+++ b/include/asm-x86/mach-default/entry_arch.h
@@ -13,6 +13,7 @@
 BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
 BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
 BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
+BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
 #endif
 
 /*
diff --git a/include/asm-x86/mach-default/smpboot_hooks.h b/include/asm-x86/mach-default/smpboot_hooks.h
index b63c52182006..56d001b9dce4 100644
--- a/include/asm-x86/mach-default/smpboot_hooks.h
+++ b/include/asm-x86/mach-default/smpboot_hooks.h
@@ -3,7 +3,9 @@
 
 static inline void smpboot_clear_io_apic_irqs(void)
 {
+#ifdef CONFIG_X86_IO_APIC
         io_apic_irqs = 0;
+#endif
 }
 
 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
@@ -35,6 +37,7 @@ static inline void smpboot_restore_warm_reset_vector(void)
 
 static inline void __init smpboot_setup_io_apic(void)
 {
+#ifdef CONFIG_X86_IO_APIC
         /*
          * Here we can be sure that there is an IO-APIC in the system. Let's
          * go and set it up:
@@ -45,9 +48,12 @@ static inline void __init smpboot_setup_io_apic(void)
                 nr_ioapics = 0;
                 localise_nmi_watchdog();
         }
+#endif
 }
 
 static inline void smpboot_clear_io_apic(void)
 {
+#ifdef CONFIG_X86_IO_APIC
         nr_ioapics = 0;
+#endif
 }
diff --git a/include/asm-x86/mach-visws/entry_arch.h b/include/asm-x86/mach-visws/entry_arch.h
index b183fa6d83d9..86be554342d4 100644
--- a/include/asm-x86/mach-visws/entry_arch.h
+++ b/include/asm-x86/mach-visws/entry_arch.h
@@ -1,23 +1,5 @@
 /*
- * The following vectors are part of the Linux architecture, there
- * is no hardware IRQ pin equivalent for them, they are triggered
- * through the ICC by us (IPIs)
+ * VISWS uses the standard Linux entry points:
  */
-#ifdef CONFIG_X86_SMP
-BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
-BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
-BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
-#endif
 
-/*
- * every pentium local APIC has two 'local interrupts', with a
- * soft-definable vector attached to both interrupts, one of
- * which is a timer interrupt, the other one is error counter
- * overflow. Linux uses the local APIC timer interrupt to get
- * a much simpler SMP time architecture:
- */
-#ifdef CONFIG_X86_LOCAL_APIC
-BUILD_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
-BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
-BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
-#endif
+#include "../mach-default/entry_arch.h"
diff --git a/include/asm-x86/mach-visws/mach_apic.h b/include/asm-x86/mach-visws/mach_apic.h
index a9ef33a8a995..6943e7a1d0e6 100644
--- a/include/asm-x86/mach-visws/mach_apic.h
+++ b/include/asm-x86/mach-visws/mach_apic.h
@@ -1,103 +1 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
-
-#include <mach_apicdef.h>
-#include <asm/smp.h>
-
-#define APIC_DFR_VALUE  (APIC_DFR_FLAT)
-
-#define no_balance_irq (0)
-#define esr_disable (0)
-
-#define INT_DELIVERY_MODE dest_LowestPrio
-#define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
-
-#ifdef CONFIG_SMP
- #define TARGET_CPUS cpu_online_map
-#else
- #define TARGET_CPUS cpumask_of_cpu(0)
-#endif
-
-#define check_apicid_used(bitmap, apicid)       physid_isset(apicid, bitmap)
-#define check_apicid_present(bit)               physid_isset(bit, phys_cpu_present_map)
-
-static inline int apic_id_registered(void)
-{
-        return physid_isset(GET_APIC_ID(read_apic_id()), phys_cpu_present_map);
-}
-
-/*
- * Set up the logical destination ID.
- *
- * Intel recommends to set DFR, LDR and TPR before enabling
- * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
- * document number 292116).  So here it goes...
- */
-static inline void init_apic_ldr(void)
-{
-        unsigned long val;
-
-        apic_write_around(APIC_DFR, APIC_DFR_VALUE);
-        val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
-        val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
-        apic_write_around(APIC_LDR, val);
-}
-
-static inline void summit_check(char *oem, char *productid) 
-{
-}
-
-static inline void setup_apic_routing(void)
-{
-}
-
-static inline int apicid_to_node(int logical_apicid)
-{
-        return 0;
-}
-
-/* Mapping from cpu number to logical apicid */
-static inline int cpu_to_logical_apicid(int cpu)
-{
-        return 1 << cpu;
-}
-
-static inline int cpu_present_to_apicid(int mps_cpu)
-{
-        if (mps_cpu < get_physical_broadcast())
-                return mps_cpu;
-        else
-                return BAD_APICID;
-}
-
-static inline physid_mask_t apicid_to_cpu_present(int apicid)
-{
-        return physid_mask_of_physid(apicid);
-}
-
-#define WAKE_SECONDARY_VIA_INIT
-
-static inline void setup_portio_remap(void)
-{
-}
-
-static inline void enable_apic_mode(void)
-{
-}
-
-static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
-{
-        return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
-}
-
-static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
-{
-        return cpus_addr(cpumask)[0];
-}
-
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
-{
-        return cpuid_apic >> index_msb;
-}
-
-#endif /* __ASM_MACH_APIC_H */
+#include "../mach-default/mach_apic.h"
diff --git a/include/asm-x86/mach-visws/mach_apicdef.h b/include/asm-x86/mach-visws/mach_apicdef.h
index 826cfa97d778..42711d152a93 100644
--- a/include/asm-x86/mach-visws/mach_apicdef.h
+++ b/include/asm-x86/mach-visws/mach_apicdef.h
@@ -1,12 +1 @@
-#ifndef __ASM_MACH_APICDEF_H
-#define __ASM_MACH_APICDEF_H
-
-#define         APIC_ID_MASK            (0xF<<24)
-
-static inline unsigned get_apic_id(unsigned long x)
-{
-                return (((x)>>24)&0xF);
-}
-#define         GET_APIC_ID(x)  get_apic_id(x)
-
-#endif
+#include "../mach-default/mach_apicdef.h"
diff --git a/include/asm-x86/mach-visws/setup_arch.h b/include/asm-x86/mach-visws/setup_arch.h
index b8f5dd829dba..fa4766ca2d10 100644
--- a/include/asm-x86/mach-visws/setup_arch.h
+++ b/include/asm-x86/mach-visws/setup_arch.h
@@ -1,6 +1 @@
-/* Hook to call BIOS initialisation function */
-
-extern unsigned long sgivwfb_mem_phys;
-extern unsigned long sgivwfb_mem_size;
-
-/* no action for visws */
+#include "../mach-default/setup_arch.h"
diff --git a/include/asm-x86/mach-visws/smpboot_hooks.h b/include/asm-x86/mach-visws/smpboot_hooks.h
index c9b83e395a2e..e4433ca88715 100644
--- a/include/asm-x86/mach-visws/smpboot_hooks.h
+++ b/include/asm-x86/mach-visws/smpboot_hooks.h
@@ -1,28 +1 @@
-static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
-{
-        CMOS_WRITE(0xa, 0xf);
-        local_flush_tlb();
-        Dprintk("1.\n");
-        *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4;
-        Dprintk("2.\n");
-        *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf;
-        Dprintk("3.\n");
-}
-
-/* for visws do nothing for any of these */
-
-static inline void smpboot_clear_io_apic_irqs(void)
-{
-}
-
-static inline void smpboot_restore_warm_reset_vector(void)
-{
-}
-
-static inline void smpboot_setup_io_apic(void)
-{
-}
-
-static inline void smpboot_clear_io_apic(void)
-{
-}
+#include "../mach-default/smpboot_hooks.h"
diff --git a/include/asm-x86/mach-voyager/entry_arch.h b/include/asm-x86/mach-voyager/entry_arch.h
index 4a1e1e8c10b6..ae52624b5937 100644
--- a/include/asm-x86/mach-voyager/entry_arch.h
+++ b/include/asm-x86/mach-voyager/entry_arch.h
@@ -23,4 +23,4 @@ BUILD_INTERRUPT(qic_invalidate_interrupt, QIC_INVALIDATE_CPI);
 BUILD_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI);
 BUILD_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI);
 BUILD_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI);
-
+BUILD_INTERRUPT(qic_call_function_single_interrupt, QIC_CALL_FUNCTION_SINGLE_CPI);
diff --git a/include/asm-x86/numaq.h b/include/asm-x86/numaq.h
index ef068d2465d6..34b92d581fa3 100644
--- a/include/asm-x86/numaq.h
+++ b/include/asm-x86/numaq.h
@@ -157,6 +157,8 @@ struct sys_cfg_data {
         struct          eachquadmem eq[MAX_NUMNODES];   /* indexed by quad id */
 };
 
+void numaq_tsc_disable(void);
+
 #else
 static inline int get_memcfg_numaq(void)
 {
diff --git a/include/asm-x86/page.h b/include/asm-x86/page.h
index b52ed85f32f5..28d7b4533b1a 100644
--- a/include/asm-x86/page.h
+++ b/include/asm-x86/page.h
@@ -61,6 +61,7 @@ extern void map_devmem(unsigned long pfn, unsigned long size,
 extern void unmap_devmem(unsigned long pfn, unsigned long size,
                          pgprot_t vma_prot);
 
+extern unsigned long max_low_pfn_mapped;
 extern unsigned long max_pfn_mapped;
 
 struct page;
diff --git a/include/asm-x86/page_64.h b/include/asm-x86/page_64.h
index 010d12db80dc..c6916c83e6b1 100644
--- a/include/asm-x86/page_64.h
+++ b/include/asm-x86/page_64.h
@@ -91,6 +91,10 @@ extern unsigned long init_memory_mapping(unsigned long start,
                                          unsigned long end);
 
 extern void initmem_init(unsigned long start_pfn, unsigned long end_pfn);
+
+extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
+extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
+
 #endif  /* !__ASSEMBLY__ */
 
 #ifdef CONFIG_FLATMEM
diff --git a/include/asm-x86/paravirt.h b/include/asm-x86/paravirt.h
index 6d8966f9d190..ef5e8ec6a6ab 100644
--- a/include/asm-x86/paravirt.h
+++ b/include/asm-x86/paravirt.h
@@ -84,7 +84,7 @@ struct pv_time_ops {
         int (*set_wallclock)(unsigned long);
 
         unsigned long long (*sched_clock)(void);
-        unsigned long (*get_cpu_khz)(void);
+        unsigned long (*get_tsc_khz)(void);
 };
 
 struct pv_cpu_ops {
@@ -779,7 +779,7 @@ static inline unsigned long long paravirt_sched_clock(void)
 {
         return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
 }
-#define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
+#define calibrate_tsc() (pv_time_ops.get_tsc_khz())
 
 static inline unsigned long long paravirt_read_pmc(int counter)
 {
diff --git a/include/asm-x86/pci-direct.h b/include/asm-x86/pci-direct.h
index 5b21485be573..80c775d9fe20 100644
--- a/include/asm-x86/pci-direct.h
+++ b/include/asm-x86/pci-direct.h
@@ -11,7 +11,11 @@ extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset);
 extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset);
 extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val);
 extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val);
+extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val);
 
 extern int early_pci_allowed(void);
 
+extern unsigned int pci_early_dump_regs;
+extern void early_dump_pci_device(u8 bus, u8 slot, u8 func);
+extern void early_dump_pci_devices(void);
 #endif
diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h
index 64de07e25329..49cbd76b9547 100644
--- a/include/asm-x86/pgtable.h
+++ b/include/asm-x86/pgtable.h
@@ -91,6 +91,7 @@
 #define __PAGE_KERNEL_VSYSCALL          (__PAGE_KERNEL_RX | _PAGE_USER)
 #define __PAGE_KERNEL_VSYSCALL_NOCACHE  (__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT)
 #define __PAGE_KERNEL_LARGE             (__PAGE_KERNEL | _PAGE_PSE)
+#define __PAGE_KERNEL_LARGE_NOCACHE     (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
 #define __PAGE_KERNEL_LARGE_EXEC        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
 
 #define PAGE_KERNEL                     __pgprot(__PAGE_KERNEL)
@@ -102,6 +103,7 @@
 #define PAGE_KERNEL_UC_MINUS            __pgprot(__PAGE_KERNEL_UC_MINUS)
 #define PAGE_KERNEL_EXEC_NOCACHE        __pgprot(__PAGE_KERNEL_EXEC_NOCACHE)
 #define PAGE_KERNEL_LARGE               __pgprot(__PAGE_KERNEL_LARGE)
+#define PAGE_KERNEL_LARGE_NOCACHE       __pgprot(__PAGE_KERNEL_LARGE_NOCACHE)
 #define PAGE_KERNEL_LARGE_EXEC          __pgprot(__PAGE_KERNEL_LARGE_EXEC)
 #define PAGE_KERNEL_VSYSCALL            __pgprot(__PAGE_KERNEL_VSYSCALL)
 #define PAGE_KERNEL_VSYSCALL_NOCACHE    __pgprot(__PAGE_KERNEL_VSYSCALL_NOCACHE)
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 7f7382704592..55402d2ab938 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -727,6 +727,8 @@ extern int			force_mwait;
 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 
 extern unsigned long            boot_option_idle_override;
+extern unsigned long            idle_halt;
+extern unsigned long            idle_nomwait;
 
 extern void enable_sep_cpu(void);
 extern int sysenter_setup(void);
diff --git a/include/asm-x86/setup.h b/include/asm-x86/setup.h
index 1d121c632d9e..90ab2225e71b 100644
--- a/include/asm-x86/setup.h
+++ b/include/asm-x86/setup.h
@@ -8,6 +8,25 @@
 /* Interrupt control for vSMPowered x86_64 systems */
 void vsmp_init(void);
 
+#ifdef CONFIG_X86_VISWS
+extern void visws_early_detect(void);
+extern int is_visws_box(void);
+#else
+static inline void visws_early_detect(void) { }
+static inline int is_visws_box(void) { return 0; }
+#endif
+
+/*
+ * Any setup quirks to be performed?
+ */
+extern int (*arch_time_init_quirk)(void);
+extern int (*arch_pre_intr_init_quirk)(void);
+extern int (*arch_intr_init_quirk)(void);
+extern int (*arch_trap_init_quirk)(void);
+extern char * (*arch_memory_setup_quirk)(void);
+extern int (*mach_get_smp_config_quirk)(unsigned int early);
+extern int (*mach_find_smp_config_quirk)(unsigned int reserve);
+
 #ifndef CONFIG_PARAVIRT
 #define paravirt_post_allocator_init()  do {} while (0)
 #endif
diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
index 2e221f1ce0b2..c2784b3e0b77 100644
--- a/include/asm-x86/smp.h
+++ b/include/asm-x86/smp.h
@@ -50,9 +50,9 @@ struct smp_ops {
 
         void (*smp_send_stop)(void);
         void (*smp_send_reschedule)(int cpu);
-        int (*smp_call_function_mask)(cpumask_t mask,
-                                      void (*func)(void *info), void *info,
-                                      int wait);
+
+        void (*send_call_func_ipi)(cpumask_t mask);
+        void (*send_call_func_single_ipi)(int cpu);
 };
 
 /* Globals due to paravirt */
@@ -94,17 +94,22 @@ static inline void smp_send_reschedule(int cpu)
         smp_ops.smp_send_reschedule(cpu);
 }
 
-static inline int smp_call_function_mask(cpumask_t mask,
-                                         void (*func) (void *info), void *info,
-                                         int wait)
+static inline void arch_send_call_function_single_ipi(int cpu)
+{
+        smp_ops.send_call_func_single_ipi(cpu);
+}
+
+static inline void arch_send_call_function_ipi(cpumask_t mask)
 {
-        return smp_ops.smp_call_function_mask(mask, func, info, wait);
+        smp_ops.send_call_func_ipi(mask);
 }
 
 void native_smp_prepare_boot_cpu(void);
 void native_smp_prepare_cpus(unsigned int max_cpus);
 void native_smp_cpus_done(unsigned int max_cpus);
 int native_cpu_up(unsigned int cpunum);
+void native_send_call_func_ipi(cpumask_t mask);
+void native_send_call_func_single_ipi(int cpu);
 
 extern int __cpu_disable(void);
 extern void __cpu_die(unsigned int cpu);
@@ -197,7 +202,5 @@ static inline int hard_smp_processor_id(void)
 extern void cpu_uninit(void);
 #endif
 
-extern void lock_ipi_call_lock(void);
-extern void unlock_ipi_call_lock(void);
 #endif /* __ASSEMBLY__ */
 #endif
diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h
index c4946c5964bf..983ce37c491f 100644
--- a/include/asm-x86/system.h
+++ b/include/asm-x86/system.h
@@ -160,7 +160,7 @@ extern void native_load_gs_index(unsigned);
  * Save a segment register away
  */
 #define savesegment(seg, value)                         \
-        asm("mov %%" #seg ",%0":"=rm" (value) : : "memory")
+        asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 
 static inline unsigned long get_limit(unsigned long segment)
 {
diff --git a/include/asm-x86/time.h b/include/asm-x86/time.h
index bce72d7a958c..a17fa473e91d 100644
--- a/include/asm-x86/time.h
+++ b/include/asm-x86/time.h
@@ -56,4 +56,6 @@ static inline int native_set_wallclock(unsigned long nowtime)
 
 #endif /* CONFIG_PARAVIRT */
 
+extern unsigned long __init calibrate_cpu(void);
+
 #endif
diff --git a/include/asm-x86/timer.h b/include/asm-x86/timer.h
index 4f6fcb050c11..fb2a4ddddf3d 100644
--- a/include/asm-x86/timer.h
+++ b/include/asm-x86/timer.h
@@ -7,14 +7,14 @@
 #define TICK_SIZE (tick_nsec / 1000)
 
 unsigned long long native_sched_clock(void);
-unsigned long native_calculate_cpu_khz(void);
+unsigned long native_calibrate_tsc(void);
 
 extern int timer_ack;
 extern int no_timer_check;
 extern int recalibrate_cpu_khz(void);
 
 #ifndef CONFIG_PARAVIRT
-#define calculate_cpu_khz() native_calculate_cpu_khz()
+#define calibrate_tsc() native_calibrate_tsc()
 #endif
 
 /* Accelerators for sched_clock()
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 98e5f17ea856..90ac7718469a 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -82,7 +82,7 @@ DECLARE_EARLY_PER_CPU(int, x86_cpu_to_node_map);
 #ifdef CONFIG_DEBUG_PER_CPU_MAPS
 extern int cpu_to_node(int cpu);
 extern int early_cpu_to_node(int cpu);
-extern cpumask_t *_node_to_cpumask_ptr(int node);
+extern const cpumask_t *_node_to_cpumask_ptr(int node);
 extern cpumask_t node_to_cpumask(int node);
 
 #else   /* !CONFIG_DEBUG_PER_CPU_MAPS */
@@ -103,7 +103,7 @@ static inline int early_cpu_to_node(int cpu)
 }
 
 /* Returns a pointer to the cpumask of CPUs on Node 'node'. */
-static inline cpumask_t *_node_to_cpumask_ptr(int node)
+static inline const cpumask_t *_node_to_cpumask_ptr(int node)
 {
         return &node_to_cpumask_map[node];
 }
@@ -118,7 +118,7 @@ static inline cpumask_t node_to_cpumask(int node)
 
 /* Replace default node_to_cpumask_ptr with optimized version */
 #define node_to_cpumask_ptr(v, node)            \
-                cpumask_t *v = _node_to_cpumask_ptr(node)
+                const cpumask_t *v = _node_to_cpumask_ptr(node)
 
 #define node_to_cpumask_ptr_next(v, node)       \
                            v = _node_to_cpumask_ptr(node)
@@ -186,7 +186,7 @@ extern int __node_distance(int, int);
 #define cpu_to_node(cpu)        0
 #define early_cpu_to_node(cpu)  0
 
-static inline cpumask_t *_node_to_cpumask_ptr(int node)
+static inline const cpumask_t *_node_to_cpumask_ptr(int node)
 {
         return &cpu_online_map;
 }
@@ -201,7 +201,7 @@ static inline int node_to_first_cpu(int node)
 
 /* Replace default node_to_cpumask_ptr with optimized version */
 #define node_to_cpumask_ptr(v, node)            \
-                cpumask_t *v = _node_to_cpumask_ptr(node)
+                const cpumask_t *v = _node_to_cpumask_ptr(node)
 
 #define node_to_cpumask_ptr_next(v, node)       \
                            v = _node_to_cpumask_ptr(node)
diff --git a/include/asm-x86/tsc.h b/include/asm-x86/tsc.h
index 548873ab5fc1..cb6f6ee45b8f 100644
--- a/include/asm-x86/tsc.h
+++ b/include/asm-x86/tsc.h
@@ -48,7 +48,6 @@ static __always_inline cycles_t vget_cycles(void)
 extern void tsc_init(void);
 extern void mark_tsc_unstable(char *reason);
 extern int unsynchronized_tsc(void);
-extern void init_tsc_clocksource(void);
 int check_tsc_unstable(void);
 
 /*
@@ -58,7 +57,6 @@ int check_tsc_unstable(void);
 extern void check_tsc_sync_source(int cpu);
 extern void check_tsc_sync_target(void);
 
-extern void tsc_calibrate(void);
 extern int notsc_setup(char *);
 
 #endif
diff --git a/include/asm-x86/uaccess.h b/include/asm-x86/uaccess.h
index 9fefd2947e78..f6fa4d841bbc 100644
--- a/include/asm-x86/uaccess.h
+++ b/include/asm-x86/uaccess.h
@@ -1,5 +1,453 @@
+#ifndef _ASM_UACCES_H_
+#define _ASM_UACCES_H_
+/*
+ * User space memory access functions
+ */
+#include <linux/errno.h>
+#include <linux/compiler.h>
+#include <linux/thread_info.h>
+#include <linux/prefetch.h>
+#include <linux/string.h>
+#include <asm/asm.h>
+#include <asm/page.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+
+#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
+
+#define KERNEL_DS       MAKE_MM_SEG(-1UL)
+#define USER_DS         MAKE_MM_SEG(PAGE_OFFSET)
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current_thread_info()->addr_limit)
+#define set_fs(x)       (current_thread_info()->addr_limit = (x))
+
+#define segment_eq(a, b)        ((a).seg == (b).seg)
+
+#define __addr_ok(addr)                                 \
+        ((unsigned long __force)(addr) <                \
+         (current_thread_info()->addr_limit.seg))
+
+/*
+ * Test whether a block of memory is a valid user space address.
+ * Returns 0 if the range is valid, nonzero otherwise.
+ *
+ * This is equivalent to the following test:
+ * (u33)addr + (u33)size >= (u33)current->addr_limit.seg (u65 for x86_64)
+ *
+ * This needs 33-bit (65-bit for x86_64) arithmetic. We have a carry...
+ */
+
+#define __range_not_ok(addr, size)                                      \
+({                                                                      \
+        unsigned long flag, roksum;                                     \
+        __chk_user_ptr(addr);                                           \
+        asm("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0"             \
+            : "=&r" (flag), "=r" (roksum)                               \
+            : "1" (addr), "g" ((long)(size)),                           \
+              "rm" (current_thread_info()->addr_limit.seg));            \
+        flag;                                                           \
+})
+
+/**
+ * access_ok: - Checks if a user space pointer is valid
+ * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
+ *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
+ *        to write to a block, it is always safe to read from it.
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns true (nonzero) if the memory block may be valid, false (zero)
+ * if it is definitely invalid.
+ *
+ * Note that, depending on architecture, this function probably just
+ * checks that the pointer is in the user space range - after calling
+ * this function, memory access functions may still return -EFAULT.
+ */
+#define access_ok(type, addr, size) (likely(__range_not_ok(addr, size) == 0))
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+        unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ */
+
+extern int __get_user_1(void);
+extern int __get_user_2(void);
+extern int __get_user_4(void);
+extern int __get_user_8(void);
+extern int __get_user_bad(void);
+
+#define __get_user_x(size, ret, x, ptr)               \
+        asm volatile("call __get_user_" #size         \
+                     : "=a" (ret),"=d" (x)            \
+                     : "0" (ptr))                     \
+
+/* Careful: we have to cast the result to the type of the pointer
+ * for sign reasons */
+
+/**
+ * get_user: - Get a simple variable from user space.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#ifdef CONFIG_X86_32
+#define __get_user_8(__ret_gu, __val_gu, ptr)                           \
+                __get_user_x(X, __ret_gu, __val_gu, ptr)
+#else
+#define __get_user_8(__ret_gu, __val_gu, ptr)                           \
+                __get_user_x(8, __ret_gu, __val_gu, ptr)
+#endif
+
+#define get_user(x, ptr)                                                \
+({                                                                      \
+        int __ret_gu;                                                   \
+        unsigned long __val_gu;                                         \
+        __chk_user_ptr(ptr);                                            \
+        switch (sizeof(*(ptr))) {                                       \
+        case 1:                                                         \
+                __get_user_x(1, __ret_gu, __val_gu, ptr);               \
+                break;                                                  \
+        case 2:                                                         \
+                __get_user_x(2, __ret_gu, __val_gu, ptr);               \
+                break;                                                  \
+        case 4:                                                         \
+                __get_user_x(4, __ret_gu, __val_gu, ptr);               \
+                break;                                                  \
+        case 8:                                                         \
+                __get_user_8(__ret_gu, __val_gu, ptr);                  \
+                break;                                                  \
+        default:                                                        \
+                __get_user_x(X, __ret_gu, __val_gu, ptr);               \
+                break;                                                  \
+        }                                                               \
+        (x) = (__typeof__(*(ptr)))__val_gu;                             \
+        __ret_gu;                                                       \
+})
+
+#define __put_user_x(size, x, ptr, __ret_pu)                    \
+        asm volatile("call __put_user_" #size : "=a" (__ret_pu) \
+                     :"0" ((typeof(*(ptr)))(x)), "c" (ptr) : "ebx")
+
+
+
+#ifdef CONFIG_X86_32
+#define __put_user_u64(x, addr, err)                                    \
+        asm volatile("1:        movl %%eax,0(%2)\n"                     \
+                     "2:        movl %%edx,4(%2)\n"                     \
+                     "3:\n"                                             \
+                     ".section .fixup,\"ax\"\n"                         \
+                     "4:        movl %3,%0\n"                           \
+                     "  jmp 3b\n"                                       \
+                     ".previous\n"                                      \
+                     _ASM_EXTABLE(1b, 4b)                               \
+                     _ASM_EXTABLE(2b, 4b)                               \
+                     : "=r" (err)                                       \
+                     : "A" (x), "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __put_user_x8(x, ptr, __ret_pu)                         \
+        asm volatile("call __put_user_8" : "=a" (__ret_pu)      \
+                     : "A" ((typeof(*(ptr)))(x)), "c" (ptr) : "ebx")
+#else
+#define __put_user_u64(x, ptr, retval) \
+        __put_user_asm(x, ptr, retval, "q", "", "Zr", -EFAULT)
+#define __put_user_x8(x, ptr, __ret_pu) __put_user_x(8, x, ptr, __ret_pu)
+#endif
+
+extern void __put_user_bad(void);
+
+/*
+ * Strange magic calling convention: pointer in %ecx,
+ * value in %eax(:%edx), return value in %eax. clobbers %rbx
+ */
+extern void __put_user_1(void);
+extern void __put_user_2(void);
+extern void __put_user_4(void);
+extern void __put_user_8(void);
+
+#ifdef CONFIG_X86_WP_WORKS_OK
+
+/**
+ * put_user: - Write a simple value into user space.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define put_user(x, ptr)                                        \
+({                                                              \
+        int __ret_pu;                                           \
+        __typeof__(*(ptr)) __pu_val;                            \
+        __chk_user_ptr(ptr);                                    \
+        __pu_val = x;                                           \
+        switch (sizeof(*(ptr))) {                               \
+        case 1:                                                 \
+                __put_user_x(1, __pu_val, ptr, __ret_pu);       \
+                break;                                          \
+        case 2:                                                 \
+                __put_user_x(2, __pu_val, ptr, __ret_pu);       \
+                break;                                          \
+        case 4:                                                 \
+                __put_user_x(4, __pu_val, ptr, __ret_pu);       \
+                break;                                          \
+        case 8:                                                 \
+                __put_user_x8(__pu_val, ptr, __ret_pu);         \
+                break;                                          \
+        default:                                                \
+                __put_user_x(X, __pu_val, ptr, __ret_pu);       \
+                break;                                          \
+        }                                                       \
+        __ret_pu;                                               \
+})
+
+#define __put_user_size(x, ptr, size, retval, errret)                   \
+do {                                                                    \
+        retval = 0;                                                     \
+        __chk_user_ptr(ptr);                                            \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                __put_user_asm(x, ptr, retval, "b", "b", "iq", errret); \
+                break;                                                  \
+        case 2:                                                         \
+                __put_user_asm(x, ptr, retval, "w", "w", "ir", errret); \
+                break;                                                  \
+        case 4:                                                         \
+                __put_user_asm(x, ptr, retval, "l", "k",  "ir", errret);\
+                break;                                                  \
+        case 8:                                                         \
+                __put_user_u64((__typeof__(*ptr))(x), ptr, retval);     \
+                break;                                                  \
+        default:                                                        \
+                __put_user_bad();                                       \
+        }                                                               \
+} while (0)
+
+#else
+
+#define __put_user_size(x, ptr, size, retval, errret)                   \
+do {                                                                    \
+        __typeof__(*(ptr))__pus_tmp = x;                                \
+        retval = 0;                                                     \
+                                                                        \
+        if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, size) != 0))    \
+                retval = errret;                                        \
+} while (0)
+
+#define put_user(x, ptr)                                        \
+({                                                              \
+        int __ret_pu;                                           \
+        __typeof__(*(ptr))__pus_tmp = x;                        \
+        __ret_pu = 0;                                           \
+        if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp,         \
+                                       sizeof(*(ptr))) != 0))   \
+                __ret_pu = -EFAULT;                             \
+        __ret_pu;                                               \
+})
+#endif
+
+#ifdef CONFIG_X86_32
+#define __get_user_asm_u64(x, ptr, retval, errret)      (x) = __get_user_bad()
+#else
+#define __get_user_asm_u64(x, ptr, retval, errret) \
+         __get_user_asm(x, ptr, retval, "q", "", "=r", errret)
+#endif
+
+#define __get_user_size(x, ptr, size, retval, errret)                   \
+do {                                                                    \
+        retval = 0;                                                     \
+        __chk_user_ptr(ptr);                                            \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                __get_user_asm(x, ptr, retval, "b", "b", "=q", errret); \
+                break;                                                  \
+        case 2:                                                         \
+                __get_user_asm(x, ptr, retval, "w", "w", "=r", errret); \
+                break;                                                  \
+        case 4:                                                         \
+                __get_user_asm(x, ptr, retval, "l", "k", "=r", errret); \
+                break;                                                  \
+        case 8:                                                         \
+                __get_user_asm_u64(x, ptr, retval, errret);             \
+                break;                                                  \
+        default:                                                        \
+                (x) = __get_user_bad();                                 \
+        }                                                               \
+} while (0)
+
+#define __get_user_asm(x, addr, err, itype, rtype, ltype, errret)       \
+        asm volatile("1:        mov"itype" %2,%"rtype"1\n"              \
+                     "2:\n"                                             \
+                     ".section .fixup,\"ax\"\n"                         \
+                     "3:        mov %3,%0\n"                            \
+                     "  xor"itype" %"rtype"1,%"rtype"1\n"               \
+                     "  jmp 2b\n"                                       \
+                     ".previous\n"                                      \
+                     _ASM_EXTABLE(1b, 3b)                               \
+                     : "=r" (err), ltype(x)                             \
+                     : "m" (__m(addr)), "i" (errret), "0" (err))
+
+#define __put_user_nocheck(x, ptr, size)                        \
+({                                                              \
+        long __pu_err;                                          \
+        __put_user_size((x), (ptr), (size), __pu_err, -EFAULT); \
+        __pu_err;                                               \
+})
+
+#define __get_user_nocheck(x, ptr, size)                                \
+({                                                                      \
+        long __gu_err;                                                  \
+        unsigned long __gu_val;                                         \
+        __get_user_size(__gu_val, (ptr), (size), __gu_err, -EFAULT);    \
+        (x) = (__force __typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                                       \
+})
+
+/* FIXME: this hack is definitely wrong -AK */
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct __user *)(x))
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+#define __put_user_asm(x, addr, err, itype, rtype, ltype, errret)       \
+        asm volatile("1:        mov"itype" %"rtype"1,%2\n"              \
+                     "2:\n"                                             \
+                     ".section .fixup,\"ax\"\n"                         \
+                     "3:        mov %3,%0\n"                            \
+                     "  jmp 2b\n"                                       \
+                     ".previous\n"                                      \
+                     _ASM_EXTABLE(1b, 3b)                               \
+                     : "=r"(err)                                        \
+                     : ltype(x), "m" (__m(addr)), "i" (errret), "0" (err))
+/**
+ * __get_user: - Get a simple variable from user space, with less checking.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+
+#define __get_user(x, ptr)                                              \
+        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+/**
+ * __put_user: - Write a simple value into user space, with less checking.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+
+#define __put_user(x, ptr)                                              \
+        __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
+
+#define __get_user_unaligned __get_user
+#define __put_user_unaligned __put_user
+
+/*
+ * movsl can be slow when source and dest are not both 8-byte aligned
+ */
+#ifdef CONFIG_X86_INTEL_USERCOPY
+extern struct movsl_mask {
+        int mask;
+} ____cacheline_aligned_in_smp movsl_mask;
+#endif
+
+#define ARCH_HAS_NOCACHE_UACCESS 1
+
 #ifdef CONFIG_X86_32
 # include "uaccess_32.h"
 #else
+# define ARCH_HAS_SEARCH_EXTABLE
 # include "uaccess_64.h"
 #endif
+
+#endif
diff --git a/include/asm-x86/uaccess_32.h b/include/asm-x86/uaccess_32.h
index 8e7595c1f34e..6fdef39a0bcb 100644
--- a/include/asm-x86/uaccess_32.h
+++ b/include/asm-x86/uaccess_32.h
@@ -11,426 +11,6 @@
 #include <asm/asm.h>
 #include <asm/page.h>
 
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
-
-
-#define KERNEL_DS       MAKE_MM_SEG(0xFFFFFFFFUL)
-#define USER_DS         MAKE_MM_SEG(PAGE_OFFSET)
-
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current_thread_info()->addr_limit)
-#define set_fs(x)       (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b)        ((a).seg == (b).seg)
-
-/*
- * movsl can be slow when source and dest are not both 8-byte aligned
- */
-#ifdef CONFIG_X86_INTEL_USERCOPY
-extern struct movsl_mask {
-        int mask;
-} ____cacheline_aligned_in_smp movsl_mask;
-#endif
-
-#define __addr_ok(addr)                                 \
-        ((unsigned long __force)(addr) <                \
-         (current_thread_info()->addr_limit.seg))
-
-/*
- * Test whether a block of memory is a valid user space address.
- * Returns 0 if the range is valid, nonzero otherwise.
- *
- * This is equivalent to the following test:
- * (u33)addr + (u33)size >= (u33)current->addr_limit.seg
- *
- * This needs 33-bit arithmetic. We have a carry...
- */
-#define __range_ok(addr, size)                                          \
-({                                                                      \
-        unsigned long flag, roksum;                                     \
-        __chk_user_ptr(addr);                                           \
-        asm("addl %3,%1 ; sbbl %0,%0; cmpl %1,%4; sbbl $0,%0"           \
-            :"=&r" (flag), "=r" (roksum)                                \
-            :"1" (addr), "g" ((int)(size)),                             \
-            "rm" (current_thread_info()->addr_limit.seg));              \
-        flag;                                                           \
-})
-
-/**
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
- *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- *        to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-#define access_ok(type, addr, size) (likely(__range_ok(addr, size) == 0))
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
-        unsigned long insn, fixup;
-};
-
-extern int fixup_exception(struct pt_regs *regs);
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- */
-
-extern void __get_user_1(void);
-extern void __get_user_2(void);
-extern void __get_user_4(void);
-
-#define __get_user_x(size, ret, x, ptr)       \
-        asm volatile("call __get_user_" #size \
-                     :"=a" (ret),"=d" (x)     \
-                     :"0" (ptr))
-
-
-/* Careful: we have to cast the result to the type of the pointer
- * for sign reasons */
-
-/**
- * get_user: - Get a simple variable from user space.
- * @x:   Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple variable from user space to kernel
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define get_user(x, ptr)                                                \
-({                                                                      \
-        int __ret_gu;                                                   \
-        unsigned long __val_gu;                                         \
-        __chk_user_ptr(ptr);                                            \
-        switch (sizeof(*(ptr))) {                                       \
-        case 1:                                                         \
-                __get_user_x(1, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        case 2:                                                         \
-                __get_user_x(2, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        case 4:                                                         \
-                __get_user_x(4, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        default:                                                        \
-                __get_user_x(X, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        }                                                               \
-        (x) = (__typeof__(*(ptr)))__val_gu;                             \
-        __ret_gu;                                                       \
-})
-
-extern void __put_user_bad(void);
-
-/*
- * Strange magic calling convention: pointer in %ecx,
- * value in %eax(:%edx), return value in %eax, no clobbers.
- */
-extern void __put_user_1(void);
-extern void __put_user_2(void);
-extern void __put_user_4(void);
-extern void __put_user_8(void);
-
-#define __put_user_1(x, ptr)                                    \
-        asm volatile("call __put_user_1" : "=a" (__ret_pu)      \
-                     : "0" ((typeof(*(ptr)))(x)), "c" (ptr))
-
-#define __put_user_2(x, ptr)                                    \
-        asm volatile("call __put_user_2" : "=a" (__ret_pu)      \
-                     : "0" ((typeof(*(ptr)))(x)), "c" (ptr))
-
-#define __put_user_4(x, ptr)                                    \
-        asm volatile("call __put_user_4" : "=a" (__ret_pu)      \
-                     : "0" ((typeof(*(ptr)))(x)), "c" (ptr))
-
-#define __put_user_8(x, ptr)                                    \
-        asm volatile("call __put_user_8" : "=a" (__ret_pu)      \
-                     : "A" ((typeof(*(ptr)))(x)), "c" (ptr))
-
-#define __put_user_X(x, ptr)                                    \
-        asm volatile("call __put_user_X" : "=a" (__ret_pu)      \
-                     : "c" (ptr))
-
-/**
- * put_user: - Write a simple value into user space.
- * @x:   Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple value from kernel space to user
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#ifdef CONFIG_X86_WP_WORKS_OK
-
-#define put_user(x, ptr)                                        \
-({                                                              \
-        int __ret_pu;                                           \
-        __typeof__(*(ptr)) __pu_val;                            \
-        __chk_user_ptr(ptr);                                    \
-        __pu_val = x;                                           \
-        switch (sizeof(*(ptr))) {                               \
-        case 1:                                                 \
-                __put_user_1(__pu_val, ptr);                    \
-                break;                                          \
-        case 2:                                                 \
-                __put_user_2(__pu_val, ptr);                    \
-                break;                                          \
-        case 4:                                                 \
-                __put_user_4(__pu_val, ptr);                    \
-                break;                                          \
-        case 8:                                                 \
-                __put_user_8(__pu_val, ptr);                    \
-                break;                                          \
-        default:                                                \
-                __put_user_X(__pu_val, ptr);                    \
-                break;                                          \
-        }                                                       \
-        __ret_pu;                                               \
-})
-
-#else
-#define put_user(x, ptr)                                        \
-({                                                              \
-        int __ret_pu;                                           \
-        __typeof__(*(ptr))__pus_tmp = x;                        \
-        __ret_pu = 0;                                           \
-        if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp,         \
-                                       sizeof(*(ptr))) != 0))   \
-                __ret_pu = -EFAULT;                             \
-        __ret_pu;                                               \
-})
-
-
-#endif
-
-/**
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x:   Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple variable from user space to kernel
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define __get_user(x, ptr)                              \
-        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-
-/**
- * __put_user: - Write a simple value into user space, with less checking.
- * @x:   Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple value from kernel space to user
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define __put_user(x, ptr)                                              \
-        __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __put_user_nocheck(x, ptr, size)                        \
-({                                                              \
-        long __pu_err;                                          \
-        __put_user_size((x), (ptr), (size), __pu_err, -EFAULT); \
-        __pu_err;                                               \
-})
-
-
-#define __put_user_u64(x, addr, err)                                    \
-        asm volatile("1:        movl %%eax,0(%2)\n"                     \
-                     "2:        movl %%edx,4(%2)\n"                     \
-                     "3:\n"                                             \
-                     ".section .fixup,\"ax\"\n"                         \
-                     "4:        movl %3,%0\n"                           \
-                     "  jmp 3b\n"                                       \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 4b)                               \
-                     _ASM_EXTABLE(2b, 4b)                               \
-                     : "=r" (err)                                       \
-                     : "A" (x), "r" (addr), "i" (-EFAULT), "0" (err))
-
-#ifdef CONFIG_X86_WP_WORKS_OK
-
-#define __put_user_size(x, ptr, size, retval, errret)                   \
-do {                                                                    \
-        retval = 0;                                                     \
-        __chk_user_ptr(ptr);                                            \
-        switch (size) {                                                 \
-        case 1:                                                         \
-                __put_user_asm(x, ptr, retval, "b", "b", "iq", errret); \
-                break;                                                  \
-        case 2:                                                         \
-                __put_user_asm(x, ptr, retval, "w", "w", "ir", errret); \
-                break;                                                  \
-        case 4:                                                         \
-                __put_user_asm(x, ptr, retval, "l", "",  "ir", errret); \
-                break;                                                  \
-        case 8:                                                         \
-                __put_user_u64((__typeof__(*ptr))(x), ptr, retval);     \
-                break;                                                  \
-        default:                                                        \
-                __put_user_bad();                                       \
-        }                                                               \
-} while (0)
-
-#else
-
-#define __put_user_size(x, ptr, size, retval, errret)                   \
-do {                                                                    \
-        __typeof__(*(ptr))__pus_tmp = x;                                \
-        retval = 0;                                                     \
-                                                                        \
-        if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, size) != 0))    \
-                retval = errret;                                        \
-} while (0)
-
-#endif
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct __user *)(x))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-#define __put_user_asm(x, addr, err, itype, rtype, ltype, errret)       \
-        asm volatile("1:        mov"itype" %"rtype"1,%2\n"              \
-                     "2:\n"                                             \
-                     ".section .fixup,\"ax\"\n"                         \
-                     "3:        movl %3,%0\n"                           \
-                     "  jmp 2b\n"                                       \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 3b)                               \
-                     : "=r"(err)                                        \
-                     : ltype (x), "m" (__m(addr)), "i" (errret), "0" (err))
-
-
-#define __get_user_nocheck(x, ptr, size)                                \
-({                                                                      \
-        long __gu_err;                                                  \
-        unsigned long __gu_val;                                         \
-        __get_user_size(__gu_val, (ptr), (size), __gu_err, -EFAULT);    \
-        (x) = (__typeof__(*(ptr)))__gu_val;                             \
-        __gu_err;                                                       \
-})
-
-extern long __get_user_bad(void);
-
-#define __get_user_size(x, ptr, size, retval, errret)                   \
-do {                                                                    \
-        retval = 0;                                                     \
-        __chk_user_ptr(ptr);                                            \
-        switch (size) {                                                 \
-        case 1:                                                         \
-                __get_user_asm(x, ptr, retval, "b", "b", "=q", errret); \
-                break;                                                  \
-        case 2:                                                         \
-                __get_user_asm(x, ptr, retval, "w", "w", "=r", errret); \
-                break;                                                  \
-        case 4:                                                         \
-                __get_user_asm(x, ptr, retval, "l", "", "=r", errret);  \
-                break;                                                  \
-        default:                                                        \
-                (x) = __get_user_bad();                                 \
-        }                                                               \
-} while (0)
-
-#define __get_user_asm(x, addr, err, itype, rtype, ltype, errret)       \
-        asm volatile("1:        mov"itype" %2,%"rtype"1\n"              \
-                     "2:\n"                                             \
-                     ".section .fixup,\"ax\"\n"                         \
-                     "3:        movl %3,%0\n"                           \
-                     "  xor"itype" %"rtype"1,%"rtype"1\n"               \
-                     "  jmp 2b\n"                                       \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 3b)                               \
-                     : "=r" (err), ltype (x)                            \
-                     : "m" (__m(addr)), "i" (errret), "0" (err))
-
-
 unsigned long __must_check __copy_to_user_ll
                 (void __user *to, const void *from, unsigned long n);
 unsigned long __must_check __copy_from_user_ll
@@ -576,8 +156,6 @@ __copy_from_user(void *to, const void __user *from, unsigned long n)
         return __copy_from_user_ll(to, from, n);
 }
 
-#define ARCH_HAS_NOCACHE_UACCESS
-
 static __always_inline unsigned long __copy_from_user_nocache(void *to,
                                 const void __user *from, unsigned long n)
 {
diff --git a/include/asm-x86/uaccess_64.h b/include/asm-x86/uaccess_64.h
index b8a2f4339903..515d4dce96b5 100644
--- a/include/asm-x86/uaccess_64.h
+++ b/include/asm-x86/uaccess_64.h
@@ -9,265 +9,6 @@
 #include <linux/prefetch.h>
 #include <asm/page.h>
 
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
-
-#define KERNEL_DS       MAKE_MM_SEG(0xFFFFFFFFFFFFFFFFUL)
-#define USER_DS         MAKE_MM_SEG(PAGE_OFFSET)
-
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current_thread_info()->addr_limit)
-#define set_fs(x)       (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b)        ((a).seg == (b).seg)
-
-#define __addr_ok(addr) (!((unsigned long)(addr) &                      \
-                           (current_thread_info()->addr_limit.seg)))
-
-/*
- * Uhhuh, this needs 65-bit arithmetic. We have a carry..
- */
-#define __range_not_ok(addr, size)                                      \
-({                                                                      \
-        unsigned long flag, roksum;                                     \
-        __chk_user_ptr(addr);                                           \
-        asm("# range_ok\n\r"                                            \
-            "addq %3,%1 ; sbbq %0,%0 ; cmpq %1,%4 ; sbbq $0,%0"         \
-            : "=&r" (flag), "=r" (roksum)                               \
-            : "1" (addr), "g" ((long)(size)),                           \
-              "g" (current_thread_info()->addr_limit.seg));             \
-        flag;                                                           \
-})
-
-#define access_ok(type, addr, size) (__range_not_ok(addr, size) == 0)
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
-        unsigned long insn, fixup;
-};
-
-extern int fixup_exception(struct pt_regs *regs);
-
-#define ARCH_HAS_SEARCH_EXTABLE
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- */
-
-#define __get_user_x(size, ret, x, ptr)               \
-        asm volatile("call __get_user_" #size         \
-                     : "=a" (ret),"=d" (x)            \
-                     : "c" (ptr)                      \
-                     : "r8")
-
-/* Careful: we have to cast the result to the type of the pointer
- * for sign reasons */
-
-#define get_user(x, ptr)                                                \
-({                                                                      \
-        unsigned long __val_gu;                                         \
-        int __ret_gu;                                                   \
-        __chk_user_ptr(ptr);                                            \
-        switch (sizeof(*(ptr))) {                                       \
-        case 1:                                                         \
-                __get_user_x(1, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        case 2:                                                         \
-                __get_user_x(2, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        case 4:                                                         \
-                __get_user_x(4, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        case 8:                                                         \
-                __get_user_x(8, __ret_gu, __val_gu, ptr);               \
-                break;                                                  \
-        default:                                                        \
-                __get_user_bad();                                       \
-                break;                                                  \
-        }                                                               \
-        (x) = (__force typeof(*(ptr)))__val_gu;                         \
-        __ret_gu;                                                       \
-})
-
-extern void __put_user_1(void);
-extern void __put_user_2(void);
-extern void __put_user_4(void);
-extern void __put_user_8(void);
-extern void __put_user_bad(void);
-
-#define __put_user_x(size, ret, x, ptr)                                 \
-        asm volatile("call __put_user_" #size                           \
-                     :"=a" (ret)                                        \
-                     :"c" (ptr),"d" (x)                                 \
-                     :"r8")
-
-#define put_user(x, ptr)                                                \
-        __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user(x, ptr)                                              \
-        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __put_user(x, ptr)                                              \
-        __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user_unaligned __get_user
-#define __put_user_unaligned __put_user
-
-#define __put_user_nocheck(x, ptr, size)                \
-({                                                      \
-        int __pu_err;                                   \
-        __put_user_size((x), (ptr), (size), __pu_err);  \
-        __pu_err;                                       \
-})
-
-
-#define __put_user_check(x, ptr, size)                          \
-({                                                              \
-        int __pu_err;                                           \
-        typeof(*(ptr)) __user *__pu_addr = (ptr);               \
-        switch (size) {                                         \
-        case 1:                                                 \
-                __put_user_x(1, __pu_err, x, __pu_addr);        \
-                break;                                          \
-        case 2:                                                 \
-                __put_user_x(2, __pu_err, x, __pu_addr);        \
-                break;                                          \
-        case 4:                                                 \
-                __put_user_x(4, __pu_err, x, __pu_addr);        \
-                break;                                          \
-        case 8:                                                 \
-                __put_user_x(8, __pu_err, x, __pu_addr);        \
-                break;                                          \
-        default:                                                \
-                __put_user_bad();                               \
-        }                                                       \
-        __pu_err;                                               \
-})
-
-#define __put_user_size(x, ptr, size, retval)                           \
-do {                                                                    \
-        retval = 0;                                                     \
-        __chk_user_ptr(ptr);                                            \
-        switch (size) {                                                 \
-        case 1:                                                         \
-                __put_user_asm(x, ptr, retval, "b", "b", "iq", -EFAULT);\
-                break;                                                  \
-        case 2:                                                         \
-                __put_user_asm(x, ptr, retval, "w", "w", "ir", -EFAULT);\
-                break;                                                  \
-        case 4:                                                         \
-                __put_user_asm(x, ptr, retval, "l", "k", "ir", -EFAULT);\
-                break;                                                  \
-        case 8:                                                         \
-                __put_user_asm(x, ptr, retval, "q", "", "Zr", -EFAULT); \
-                break;                                                  \
-        default:                                                        \
-                __put_user_bad();                                       \
-        }                                                               \
-} while (0)
-
-/* FIXME: this hack is definitely wrong -AK */
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct __user *)(x))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-#define __put_user_asm(x, addr, err, itype, rtype, ltype, errno)        \
-        asm volatile("1:        mov"itype" %"rtype"1,%2\n"              \
-                     "2:\n"                                             \
-                     ".section .fixup, \"ax\"\n"                        \
-                     "3:        mov %3,%0\n"                            \
-                     "  jmp 2b\n"                                       \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 3b)                               \
-                     : "=r"(err)                                        \
-                     : ltype (x), "m" (__m(addr)), "i" (errno), "0" (err))
-
-
-#define __get_user_nocheck(x, ptr, size)                        \
-({                                                              \
-        int __gu_err;                                           \
-        unsigned long __gu_val;                                 \
-        __get_user_size(__gu_val, (ptr), (size), __gu_err);     \
-        (x) = (__force typeof(*(ptr)))__gu_val;                 \
-        __gu_err;                                               \
-})
-
-extern int __get_user_1(void);
-extern int __get_user_2(void);
-extern int __get_user_4(void);
-extern int __get_user_8(void);
-extern int __get_user_bad(void);
-
-#define __get_user_size(x, ptr, size, retval)                           \
-do {                                                                    \
-        retval = 0;                                                     \
-        __chk_user_ptr(ptr);                                            \
-        switch (size) {                                                 \
-        case 1:                                                         \
-                __get_user_asm(x, ptr, retval, "b", "b", "=q", -EFAULT);\
-                break;                                                  \
-        case 2:                                                         \
-                __get_user_asm(x, ptr, retval, "w", "w", "=r", -EFAULT);\
-                break;                                                  \
-        case 4:                                                         \
-                __get_user_asm(x, ptr, retval, "l", "k", "=r", -EFAULT);\
-                break;                                                  \
-        case 8:                                                         \
-                __get_user_asm(x, ptr, retval, "q", "", "=r", -EFAULT); \
-                break;                                                  \
-        default:                                                        \
-                (x) = __get_user_bad();                                 \
-        }                                                               \
-} while (0)
-
-#define __get_user_asm(x, addr, err, itype, rtype, ltype, errno)        \
-        asm volatile("1:        mov"itype" %2,%"rtype"1\n"              \
-                     "2:\n"                                             \
-                     ".section .fixup, \"ax\"\n"                        \
-                     "3:        mov %3,%0\n"                            \
-                     "  xor"itype" %"rtype"1,%"rtype"1\n"               \
-                     "  jmp 2b\n"                                       \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 3b)                               \
-                     : "=r" (err), ltype (x)                            \
-                     : "m" (__m(addr)), "i"(errno), "0"(err))
-
 /*
  * Copy To/From Userspace
  */
@@ -437,7 +178,6 @@ __copy_to_user_inatomic(void __user *dst, const void *src, unsigned size)
         return copy_user_generic((__force void *)dst, src, size);
 }
 
-#define ARCH_HAS_NOCACHE_UACCESS 1
 extern long __copy_user_nocache(void *dst, const void __user *src,
                                 unsigned size, int zerorest);
 
@@ -455,4 +195,7 @@ static inline int __copy_from_user_inatomic_nocache(void *dst,
         return __copy_user_nocache(dst, src, size, 0);
 }
 
+unsigned long
+copy_user_handle_tail(char *to, char *from, unsigned len, unsigned zerorest);
+
 #endif /* __X86_64_UACCESS_H */
diff --git a/include/asm-x86/uv/uv_hub.h b/include/asm-x86/uv/uv_hub.h
index 65004881de5f..a4ef26e5850b 100644
--- a/include/asm-x86/uv/uv_hub.h
+++ b/include/asm-x86/uv/uv_hub.h
@@ -149,6 +149,8 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 #define UV_LOCAL_MMR_BASE               0xf4000000UL
 #define UV_GLOBAL_MMR32_BASE            0xf8000000UL
 #define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
+#define UV_LOCAL_MMR_SIZE               (64UL * 1024 * 1024)
+#define UV_GLOBAL_MMR32_SIZE            (64UL * 1024 * 1024)
 
 #define UV_GLOBAL_MMR32_PNODE_SHIFT     15
 #define UV_GLOBAL_MMR64_PNODE_SHIFT     26
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h
index ac9846076521..151fd7fcb809 100644
--- a/include/asm-x86/uv/uv_mmrs.h
+++ b/include/asm-x86/uv/uv_mmrs.h
@@ -17,7 +17,7 @@
 /*                           UVH_BAU_DATA_CONFIG                             */
 /* ========================================================================= */
 #define UVH_BAU_DATA_CONFIG 0x61680UL
-#define UVH_BAU_DATA_CONFIG_32 0x0450
+#define UVH_BAU_DATA_CONFIG_32 0x0438
 
 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
@@ -53,10 +53,248 @@ union uvh_bau_data_config_u {
 };
 
 /* ========================================================================= */
+/*                           UVH_EVENT_OCCURRED0                             */
+/* ========================================================================= */
+#define UVH_EVENT_OCCURRED0 0x70000UL
+#define UVH_EVENT_OCCURRED0_32 0x005e8
+
+#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
+#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
+#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
+#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
+#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
+#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
+#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
+#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
+#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
+#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
+#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
+#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
+#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
+#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
+#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
+#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
+#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
+#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
+#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
+#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
+#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
+#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
+#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
+#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
+#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
+#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
+#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
+#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
+#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
+#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
+#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
+#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
+#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
+#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
+#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
+#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
+#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
+#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
+#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
+#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
+#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
+#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
+#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
+#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
+#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
+#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
+#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
+#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
+#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
+#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
+#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
+#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
+#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
+#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
+#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
+#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
+#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
+#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
+#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
+#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
+#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
+#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
+#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
+#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
+#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
+#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
+#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
+#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
+#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
+#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
+#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
+#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
+#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
+#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
+union uvh_event_occurred0_u {
+    unsigned long       v;
+    struct uvh_event_occurred0_s {
+        unsigned long   lb_hcerr             :  1;  /* RW, W1C */
+        unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
+        unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
+        unsigned long   lh_hcerr             :  1;  /* RW, W1C */
+        unsigned long   rh_hcerr             :  1;  /* RW, W1C */
+        unsigned long   xn_hcerr             :  1;  /* RW, W1C */
+        unsigned long   si_hcerr             :  1;  /* RW, W1C */
+        unsigned long   lb_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   gr0_aoerr0           :  1;  /* RW, W1C */
+        unsigned long   gr1_aoerr0           :  1;  /* RW, W1C */
+        unsigned long   lh_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   rh_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   xn_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   si_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   lb_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   gr0_aoerr1           :  1;  /* RW, W1C */
+        unsigned long   gr1_aoerr1           :  1;  /* RW, W1C */
+        unsigned long   lh_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   rh_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   xn_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   si_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   rh_vpi_int           :  1;  /* RW, W1C */
+        unsigned long   system_shutdown_int  :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_0         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_1         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_2         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_3         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_4         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_5         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_6         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_7         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_8         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_9         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_10        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_11        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_12        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_13        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_14        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_15        :  1;  /* RW, W1C */
+        unsigned long   l1_nmi_int           :  1;  /* RW, W1C */
+        unsigned long   stop_clock           :  1;  /* RW, W1C */
+        unsigned long   asic_to_l1           :  1;  /* RW, W1C */
+        unsigned long   l1_to_asic           :  1;  /* RW, W1C */
+        unsigned long   ltc_int              :  1;  /* RW, W1C */
+        unsigned long   la_seq_trigger       :  1;  /* RW, W1C */
+        unsigned long   ipi_int              :  1;  /* RW, W1C */
+        unsigned long   extio_int0           :  1;  /* RW, W1C */
+        unsigned long   extio_int1           :  1;  /* RW, W1C */
+        unsigned long   extio_int2           :  1;  /* RW, W1C */
+        unsigned long   extio_int3           :  1;  /* RW, W1C */
+        unsigned long   profile_int          :  1;  /* RW, W1C */
+        unsigned long   rtc0                 :  1;  /* RW, W1C */
+        unsigned long   rtc1                 :  1;  /* RW, W1C */
+        unsigned long   rtc2                 :  1;  /* RW, W1C */
+        unsigned long   rtc3                 :  1;  /* RW, W1C */
+        unsigned long   bau_data             :  1;  /* RW, W1C */
+        unsigned long   power_management_req :  1;  /* RW, W1C */
+        unsigned long   rsvd_57_63           :  7;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                        UVH_EVENT_OCCURRED0_ALIAS                          */
+/* ========================================================================= */
+#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
+#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
+
+/* ========================================================================= */
+/*                               UVH_INT_CMPB                                */
+/* ========================================================================= */
+#define UVH_INT_CMPB 0x22080UL
+
+#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
+#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
+
+union uvh_int_cmpb_u {
+    unsigned long       v;
+    struct uvh_int_cmpb_s {
+        unsigned long   real_time_cmpb : 56;  /* RW */
+        unsigned long   rsvd_56_63     :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                               UVH_INT_CMPC                                */
+/* ========================================================================= */
+#define UVH_INT_CMPC 0x22100UL
+
+#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
+#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
+
+union uvh_int_cmpc_u {
+    unsigned long       v;
+    struct uvh_int_cmpc_s {
+        unsigned long   real_time_cmpc : 56;  /* RW */
+        unsigned long   rsvd_56_63     :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                               UVH_INT_CMPD                                */
+/* ========================================================================= */
+#define UVH_INT_CMPD 0x22180UL
+
+#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
+#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
+
+union uvh_int_cmpd_u {
+    unsigned long       v;
+    struct uvh_int_cmpd_s {
+        unsigned long   real_time_cmpd : 56;  /* RW */
+        unsigned long   rsvd_56_63     :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
 /*                               UVH_IPI_INT                                 */
 /* ========================================================================= */
 #define UVH_IPI_INT 0x60500UL
-#define UVH_IPI_INT_32 0x0360
+#define UVH_IPI_INT_32 0x0348
 
 #define UVH_IPI_INT_VECTOR_SHFT 0
 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
@@ -86,7 +324,7 @@ union uvh_ipi_int_u {
 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009f0
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -108,7 +346,7 @@ union uvh_lb_bau_intd_payload_queue_first_u {
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009f8
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -126,7 +364,7 @@ union uvh_lb_bau_intd_payload_queue_last_u {
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x00a00
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
@@ -144,7 +382,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0aa0
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68
 
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
@@ -205,13 +443,13 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0aa8
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
 
 /* ========================================================================= */
 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009d8
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8
 
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
@@ -234,7 +472,7 @@ union uvh_lb_bau_sb_activation_control_u {
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009e0
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0
 
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
@@ -250,7 +488,7 @@ union uvh_lb_bau_sb_activation_status_0_u {
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009e8
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8
 
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
@@ -266,7 +504,7 @@ union uvh_lb_bau_sb_activation_status_1_u {
 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009d0
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0
 
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
@@ -333,46 +571,48 @@ union uvh_lb_bau_sb_descriptor_base_u {
 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_SHFT 22
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_MASK 0x0000000000400000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 23
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000000800000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 24
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000001000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 25
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000002000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 26
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000004000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 27
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000008000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 28
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 29
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000020000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 30
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000040000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 31
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000080000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 32
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000100000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 33
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000200000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 34
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000400000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 35
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000000800000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 36
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000001000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 37
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000002000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 38
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000004000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 39
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000008000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 40
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000010000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 41
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000020000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42
+#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL
 
 union uvh_lb_mcast_aoerr0_rpt_enable_u {
     unsigned long       v;
@@ -399,7 +639,8 @@ union uvh_lb_mcast_aoerr0_rpt_enable_u {
         unsigned long   macc_rep_runt_msg                       :  1;  /* RW */
         unsigned long   macc_rep_obese_msg                      :  1;  /* RW */
         unsigned long   macc_rep_data_sb_err                    :  1;  /* RW */
-        unsigned long   macc_timeout                            :  1;  /* RW */
+        unsigned long   macc_amo_timeout                        :  1;  /* RW */
+        unsigned long   macc_put_timeout                        :  1;  /* RW */
         unsigned long   macc_spurious_event                     :  1;  /* RW */
         unsigned long   ioh_destination_table_parity            :  1;  /* RW */
         unsigned long   get_had_error_reply                     :  1;  /* RW */
@@ -419,7 +660,7 @@ union uvh_lb_mcast_aoerr0_rpt_enable_u {
         unsigned long   int_rep_obese_msg                       :  1;  /* RW */
         unsigned long   int_rep_command_err                     :  1;  /* RW */
         unsigned long   int_timeout                             :  1;  /* RW */
-        unsigned long   rsvd_42_63                              : 22;  /*    */
+        unsigned long   rsvd_43_63                              : 21;  /*    */
     } s;
 };
 
@@ -713,14 +954,34 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
 };
 
 /* ========================================================================= */
+/*                    UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR                      */
+/* ========================================================================= */
+#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
+
+#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
+#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
+#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_cfg_overlay_config_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_cfg_overlay_config_mmr_s {
+        unsigned long   rsvd_0_25: 26;  /*    */
+        unsigned long   base   : 20;  /* RW */
+        unsigned long   rsvd_46_62: 17;  /*    */
+        unsigned long   enable :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
 
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
@@ -731,8 +992,9 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
     struct uvh_rh_gam_gru_overlay_config_mmr_s {
         unsigned long   rsvd_0_27: 28;  /*    */
         unsigned long   base   : 18;  /* RW */
+        unsigned long   rsvd_46_47:  2;  /*    */
         unsigned long   gr4    :  1;  /* RW */
-        unsigned long   rsvd_47_51:  5;  /*    */
+        unsigned long   rsvd_49_51:  3;  /*    */
         unsigned long   n_gru  :  4;  /* RW */
         unsigned long   rsvd_56_62:  7;  /*    */
         unsigned long   enable :  1;  /* RW */
@@ -740,6 +1002,32 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
 };
 
 /* ========================================================================= */
+/*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
+/* ========================================================================= */
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
+
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_mmioh_overlay_config_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
+        unsigned long   rsvd_0_29: 30;  /*    */
+        unsigned long   base   : 16;  /* RW */
+        unsigned long   m_io   :  6;  /* RW */
+        unsigned long   n_io   :  4;  /* RW */
+        unsigned long   rsvd_56_62:  7;  /*    */
+        unsigned long   enable :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
@@ -765,7 +1053,7 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u {
 /* ========================================================================= */
 /*                                 UVH_RTC                                   */
 /* ========================================================================= */
-#define UVH_RTC 0x28000UL
+#define UVH_RTC 0x340000UL
 
 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
@@ -779,6 +1067,139 @@ union uvh_rtc_u {
 };
 
 /* ========================================================================= */
+/*                           UVH_RTC1_INT_CONFIG                             */
+/* ========================================================================= */
+#define UVH_RTC1_INT_CONFIG 0x615c0UL
+
+#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
+#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
+#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
+#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
+#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_RTC1_INT_CONFIG_P_SHFT 13
+#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_RTC1_INT_CONFIG_T_SHFT 15
+#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_RTC1_INT_CONFIG_M_SHFT 16
+#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
+#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_rtc1_int_config_u {
+    unsigned long       v;
+    struct uvh_rtc1_int_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                           UVH_RTC2_INT_CONFIG                             */
+/* ========================================================================= */
+#define UVH_RTC2_INT_CONFIG 0x61600UL
+
+#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
+#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
+#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
+#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
+#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_RTC2_INT_CONFIG_P_SHFT 13
+#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_RTC2_INT_CONFIG_T_SHFT 15
+#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_RTC2_INT_CONFIG_M_SHFT 16
+#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
+#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_rtc2_int_config_u {
+    unsigned long       v;
+    struct uvh_rtc2_int_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                           UVH_RTC3_INT_CONFIG                             */
+/* ========================================================================= */
+#define UVH_RTC3_INT_CONFIG 0x61640UL
+
+#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
+#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
+#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
+#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
+#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_RTC3_INT_CONFIG_P_SHFT 13
+#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_RTC3_INT_CONFIG_T_SHFT 15
+#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_RTC3_INT_CONFIG_M_SHFT 16
+#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
+#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_rtc3_int_config_u {
+    unsigned long       v;
+    struct uvh_rtc3_int_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                            UVH_RTC_INC_RATIO                              */
+/* ========================================================================= */
+#define UVH_RTC_INC_RATIO 0x350000UL
+
+#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
+#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
+#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
+#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
+
+union uvh_rtc_inc_ratio_u {
+    unsigned long       v;
+    struct uvh_rtc_inc_ratio_s {
+        unsigned long   fraction : 20;  /* RW */
+        unsigned long   ratio    :  3;  /* RW */
+        unsigned long   rsvd_23_63: 41;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
 /*                          UVH_SI_ADDR_MAP_CONFIG                           */
 /* ========================================================================= */
 #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
diff --git a/include/asm-x86/mach-visws/cobalt.h b/include/asm-x86/visws/cobalt.h
index 995258831b7f..995258831b7f 100644
--- a/include/asm-x86/mach-visws/cobalt.h
+++ b/include/asm-x86/visws/cobalt.h
diff --git a/include/asm-x86/mach-visws/lithium.h b/include/asm-x86/visws/lithium.h
index dfcd4f07ab85..dfcd4f07ab85 100644
--- a/include/asm-x86/mach-visws/lithium.h
+++ b/include/asm-x86/visws/lithium.h
diff --git a/include/asm-x86/mach-visws/piix4.h b/include/asm-x86/visws/piix4.h
index 83ea4f46e419..83ea4f46e419 100644
--- a/include/asm-x86/mach-visws/piix4.h
+++ b/include/asm-x86/visws/piix4.h
diff --git a/include/asm-x86/visws/sgivw.h b/include/asm-x86/visws/sgivw.h
new file mode 100644
index 000000000000..5fbf63e1003c
--- /dev/null
+++ b/include/asm-x86/visws/sgivw.h
@@ -0,0 +1,5 @@
+/*
+ * Frame buffer position and size:
+ */
+extern unsigned long sgivwfb_mem_phys;
+extern unsigned long sgivwfb_mem_size;
diff --git a/include/asm-x86/vmi_time.h b/include/asm-x86/vmi_time.h
index 478188130328..c3118c385156 100644
--- a/include/asm-x86/vmi_time.h
+++ b/include/asm-x86/vmi_time.h
@@ -50,7 +50,7 @@ extern void __init vmi_time_init(void);
 extern unsigned long vmi_get_wallclock(void);
 extern int vmi_set_wallclock(unsigned long now);
 extern unsigned long long vmi_sched_clock(void);
-extern unsigned long vmi_cpu_khz(void);
+extern unsigned long vmi_tsc_khz(void);
 
 #ifdef CONFIG_X86_LOCAL_APIC
 extern void __devinit vmi_time_bsp_init(void);
diff --git a/include/asm-x86/vsyscall.h b/include/asm-x86/vsyscall.h
index 17b3700949bf..6b66ff905af0 100644
--- a/include/asm-x86/vsyscall.h
+++ b/include/asm-x86/vsyscall.h
@@ -24,7 +24,8 @@ enum vsyscall_num {
         ((unused, __section__ (".vsyscall_gtod_data"),aligned(16)))
 #define __section_vsyscall_clock __attribute__ \
         ((unused, __section__ (".vsyscall_clock"),aligned(16)))
-#define __vsyscall_fn __attribute__ ((unused,__section__(".vsyscall_fn")))
+#define __vsyscall_fn \
+        __attribute__ ((unused, __section__(".vsyscall_fn"))) notrace
 
 #define VGETCPU_RDTSCP  1
 #define VGETCPU_LSL     2
diff --git a/include/asm-x86/xen/events.h b/include/asm-x86/xen/events.h
index 596312a7bfc9..f8d57ea1f05f 100644
--- a/include/asm-x86/xen/events.h
+++ b/include/asm-x86/xen/events.h
@@ -4,6 +4,7 @@
 enum ipi_vector {
         XEN_RESCHEDULE_VECTOR,
         XEN_CALL_FUNCTION_VECTOR,
+        XEN_CALL_FUNCTION_SINGLE_VECTOR,
 
         XEN_NR_IPIS,
 };
diff --git a/include/crypto/hash.h b/include/crypto/hash.h
new file mode 100644
index 000000000000..d12498ec8a4e
--- /dev/null
+++ b/include/crypto/hash.h
@@ -0,0 +1,154 @@
+/*
+ * Hash: Hash algorithms under the crypto API
+ * 
+ * Copyright (c) 2008 Herbert Xu <herbert@gondor.apana.org.au>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option) 
+ * any later version.
+ *
+ */
+
+#ifndef _CRYPTO_HASH_H
+#define _CRYPTO_HASH_H
+
+#include <linux/crypto.h>
+
+struct crypto_ahash {
+        struct crypto_tfm base;
+};
+
+static inline struct crypto_ahash *__crypto_ahash_cast(struct crypto_tfm *tfm)
+{
+        return (struct crypto_ahash *)tfm;
+}
+
+static inline struct crypto_ahash *crypto_alloc_ahash(const char *alg_name,
+                                                      u32 type, u32 mask)
+{
+        type &= ~CRYPTO_ALG_TYPE_MASK;
+        mask &= ~CRYPTO_ALG_TYPE_MASK;
+        type |= CRYPTO_ALG_TYPE_AHASH;
+        mask |= CRYPTO_ALG_TYPE_AHASH_MASK;
+
+        return __crypto_ahash_cast(crypto_alloc_base(alg_name, type, mask));
+}
+
+static inline struct crypto_tfm *crypto_ahash_tfm(struct crypto_ahash *tfm)
+{
+        return &tfm->base;
+}
+
+static inline void crypto_free_ahash(struct crypto_ahash *tfm)
+{
+        crypto_free_tfm(crypto_ahash_tfm(tfm));
+}
+
+static inline unsigned int crypto_ahash_alignmask(
+        struct crypto_ahash *tfm)
+{
+        return crypto_tfm_alg_alignmask(crypto_ahash_tfm(tfm));
+}
+
+static inline struct ahash_tfm *crypto_ahash_crt(struct crypto_ahash *tfm)
+{
+        return &crypto_ahash_tfm(tfm)->crt_ahash;
+}
+
+static inline unsigned int crypto_ahash_digestsize(struct crypto_ahash *tfm)
+{
+        return crypto_ahash_crt(tfm)->digestsize;
+}
+
+static inline u32 crypto_ahash_get_flags(struct crypto_ahash *tfm)
+{
+        return crypto_tfm_get_flags(crypto_ahash_tfm(tfm));
+}
+
+static inline void crypto_ahash_set_flags(struct crypto_ahash *tfm, u32 flags)
+{
+        crypto_tfm_set_flags(crypto_ahash_tfm(tfm), flags);
+}
+
+static inline void crypto_ahash_clear_flags(struct crypto_ahash *tfm, u32 flags)
+{
+        crypto_tfm_clear_flags(crypto_ahash_tfm(tfm), flags);
+}
+
+static inline struct crypto_ahash *crypto_ahash_reqtfm(
+        struct ahash_request *req)
+{
+        return __crypto_ahash_cast(req->base.tfm);
+}
+
+static inline unsigned int crypto_ahash_reqsize(struct crypto_ahash *tfm)
+{
+        return crypto_ahash_crt(tfm)->reqsize;
+}
+
+static inline int crypto_ahash_setkey(struct crypto_ahash *tfm,
+                                      const u8 *key, unsigned int keylen)
+{
+        struct ahash_tfm *crt = crypto_ahash_crt(tfm);
+
+        return crt->setkey(tfm, key, keylen);
+}
+
+static inline int crypto_ahash_digest(struct ahash_request *req)
+{
+        struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req));
+        return crt->digest(req);
+}
+
+static inline void ahash_request_set_tfm(struct ahash_request *req,
+                                         struct crypto_ahash *tfm)
+{
+        req->base.tfm = crypto_ahash_tfm(tfm);
+}
+
+static inline struct ahash_request *ahash_request_alloc(
+        struct crypto_ahash *tfm, gfp_t gfp)
+{
+        struct ahash_request *req;
+
+        req = kmalloc(sizeof(struct ahash_request) +
+                      crypto_ahash_reqsize(tfm), gfp);
+
+        if (likely(req))
+                ahash_request_set_tfm(req, tfm);
+
+        return req;
+}
+
+static inline void ahash_request_free(struct ahash_request *req)
+{
+        kfree(req);
+}
+
+static inline struct ahash_request *ahash_request_cast(
+        struct crypto_async_request *req)
+{
+        return container_of(req, struct ahash_request, base);
+}
+
+static inline void ahash_request_set_callback(struct ahash_request *req,
+                                              u32 flags,
+                                              crypto_completion_t complete,
+                                              void *data)
+{
+        req->base.complete = complete;
+        req->base.data = data;
+        req->base.flags = flags;
+}
+
+static inline void ahash_request_set_crypt(struct ahash_request *req,
+                                           struct scatterlist *src, u8 *result,
+                                           unsigned int nbytes)
+{
+        req->src = src;
+        req->nbytes = nbytes;
+        req->result = result;
+}
+
+#endif  /* _CRYPTO_HASH_H */
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
new file mode 100644
index 000000000000..917ae57bad4a
--- /dev/null
+++ b/include/crypto/internal/hash.h
@@ -0,0 +1,78 @@
+/*
+ * Hash algorithms.
+ * 
+ * Copyright (c) 2008 Herbert Xu <herbert@gondor.apana.org.au>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option) 
+ * any later version.
+ *
+ */
+
+#ifndef _CRYPTO_INTERNAL_HASH_H
+#define _CRYPTO_INTERNAL_HASH_H
+
+#include <crypto/algapi.h>
+#include <crypto/hash.h>
+
+struct ahash_request;
+struct scatterlist;
+
+struct crypto_hash_walk {
+        char *data;
+
+        unsigned int offset;
+        unsigned int alignmask;
+
+        struct page *pg;
+        unsigned int entrylen;
+
+        unsigned int total;
+        struct scatterlist *sg;
+
+        unsigned int flags;
+};
+
+extern const struct crypto_type crypto_ahash_type;
+
+int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err);
+int crypto_hash_walk_first(struct ahash_request *req,
+                           struct crypto_hash_walk *walk);
+
+static inline void *crypto_ahash_ctx(struct crypto_ahash *tfm)
+{
+        return crypto_tfm_ctx(&tfm->base);
+}
+
+static inline struct ahash_alg *crypto_ahash_alg(
+        struct crypto_ahash *tfm)
+{
+        return &crypto_ahash_tfm(tfm)->__crt_alg->cra_ahash;
+}
+
+static inline int ahash_enqueue_request(struct crypto_queue *queue,
+                                             struct ahash_request *request)
+{
+        return crypto_enqueue_request(queue, &request->base);
+}
+
+static inline struct ahash_request *ahash_dequeue_request(
+        struct crypto_queue *queue)
+{
+        return ahash_request_cast(crypto_dequeue_request(queue));
+}
+
+static inline void *ahash_request_ctx(struct ahash_request *req)
+{
+        return req->__ctx;
+}
+
+static inline int ahash_tfm_in_queue(struct crypto_queue *queue,
+                                          struct crypto_ahash *tfm)
+{
+        return crypto_tfm_in_queue(queue, crypto_ahash_tfm(tfm));
+}
+
+#endif  /* _CRYPTO_INTERNAL_HASH_H */
+
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
new file mode 100644
index 000000000000..82b6983b7fbb
--- /dev/null
+++ b/include/drm/Kbuild
@@ -0,0 +1,10 @@
+unifdef-y += drm.h drm_sarea.h
+unifdef-y += i810_drm.h
+unifdef-y += i830_drm.h
+unifdef-y += i915_drm.h
+unifdef-y += mga_drm.h
+unifdef-y += r128_drm.h
+unifdef-y += radeon_drm.h
+unifdef-y += sis_drm.h
+unifdef-y += savage_drm.h
+unifdef-y += via_drm.h
diff --git a/include/drm/drm.h b/include/drm/drm.h
new file mode 100644
index 000000000000..38d3c6b8276a
--- /dev/null
+++ b/include/drm/drm.h
@@ -0,0 +1,694 @@
+/**
+ * \file drm.h
+ * Header for the Direct Rendering Manager
+ *
+ * \author Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ * \par Acknowledgments:
+ * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
+ */
+
+/*
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DRM_H_
+#define _DRM_H_
+
+#if defined(__linux__)
+#if defined(__KERNEL__)
+#endif
+#include <asm/ioctl.h>          /* For _IO* macros */
+#define DRM_IOCTL_NR(n)         _IOC_NR(n)
+#define DRM_IOC_VOID            _IOC_NONE
+#define DRM_IOC_READ            _IOC_READ
+#define DRM_IOC_WRITE           _IOC_WRITE
+#define DRM_IOC_READWRITE       _IOC_READ|_IOC_WRITE
+#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
+#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
+#if defined(__FreeBSD__) && defined(IN_MODULE)
+/* Prevent name collision when including sys/ioccom.h */
+#undef ioctl
+#include <sys/ioccom.h>
+#define ioctl(a,b,c)            xf86ioctl(a,b,c)
+#else
+#include <sys/ioccom.h>
+#endif                          /* __FreeBSD__ && xf86ioctl */
+#define DRM_IOCTL_NR(n)         ((n) & 0xff)
+#define DRM_IOC_VOID            IOC_VOID
+#define DRM_IOC_READ            IOC_OUT
+#define DRM_IOC_WRITE           IOC_IN
+#define DRM_IOC_READWRITE       IOC_INOUT
+#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
+#endif
+
+#define DRM_MAJOR       226
+#define DRM_MAX_MINOR   15
+
+#define DRM_NAME        "drm"     /**< Name in kernel, /dev, and /proc */
+#define DRM_MIN_ORDER   5         /**< At least 2^5 bytes = 32 bytes */
+#define DRM_MAX_ORDER   22        /**< Up to 2^22 bytes = 4MB */
+#define DRM_RAM_PERCENT 10        /**< How much system ram can we lock? */
+
+#define _DRM_LOCK_HELD  0x80000000U /**< Hardware lock is held */
+#define _DRM_LOCK_CONT  0x40000000U /**< Hardware lock is contended */
+#define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
+#define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
+#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
+
+typedef unsigned int drm_handle_t;
+typedef unsigned int drm_context_t;
+typedef unsigned int drm_drawable_t;
+typedef unsigned int drm_magic_t;
+
+/**
+ * Cliprect.
+ *
+ * \warning: If you change this structure, make sure you change
+ * XF86DRIClipRectRec in the server as well
+ *
+ * \note KW: Actually it's illegal to change either for
+ * backwards-compatibility reasons.
+ */
+struct drm_clip_rect {
+        unsigned short x1;
+        unsigned short y1;
+        unsigned short x2;
+        unsigned short y2;
+};
+
+/**
+ * Drawable information.
+ */
+struct drm_drawable_info {
+        unsigned int num_rects;
+        struct drm_clip_rect *rects;
+};
+
+/**
+ * Texture region,
+ */
+struct drm_tex_region {
+        unsigned char next;
+        unsigned char prev;
+        unsigned char in_use;
+        unsigned char padding;
+        unsigned int age;
+};
+
+/**
+ * Hardware lock.
+ *
+ * The lock structure is a simple cache-line aligned integer.  To avoid
+ * processor bus contention on a multiprocessor system, there should not be any
+ * other data stored in the same cache line.
+ */
+struct drm_hw_lock {
+        __volatile__ unsigned int lock;         /**< lock variable */
+        char padding[60];                       /**< Pad to cache line */
+};
+
+/**
+ * DRM_IOCTL_VERSION ioctl argument type.
+ *
+ * \sa drmGetVersion().
+ */
+struct drm_version {
+        int version_major;        /**< Major version */
+        int version_minor;        /**< Minor version */
+        int version_patchlevel;   /**< Patch level */
+        size_t name_len;          /**< Length of name buffer */
+        char __user *name;        /**< Name of driver */
+        size_t date_len;          /**< Length of date buffer */
+        char __user *date;        /**< User-space buffer to hold date */
+        size_t desc_len;          /**< Length of desc buffer */
+        char __user *desc;        /**< User-space buffer to hold desc */
+};
+
+/**
+ * DRM_IOCTL_GET_UNIQUE ioctl argument type.
+ *
+ * \sa drmGetBusid() and drmSetBusId().
+ */
+struct drm_unique {
+        size_t unique_len;        /**< Length of unique */
+        char __user *unique;      /**< Unique name for driver instantiation */
+};
+
+struct drm_list {
+        int count;                /**< Length of user-space structures */
+        struct drm_version __user *version;
+};
+
+struct drm_block {
+        int unused;
+};
+
+/**
+ * DRM_IOCTL_CONTROL ioctl argument type.
+ *
+ * \sa drmCtlInstHandler() and drmCtlUninstHandler().
+ */
+struct drm_control {
+        enum {
+                DRM_ADD_COMMAND,
+                DRM_RM_COMMAND,
+                DRM_INST_HANDLER,
+                DRM_UNINST_HANDLER
+        } func;
+        int irq;
+};
+
+/**
+ * Type of memory to map.
+ */
+enum drm_map_type {
+        _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
+        _DRM_REGISTERS = 1,       /**< no caching, no core dump */
+        _DRM_SHM = 2,             /**< shared, cached */
+        _DRM_AGP = 3,             /**< AGP/GART */
+        _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
+        _DRM_CONSISTENT = 5,      /**< Consistent memory for PCI DMA */
+};
+
+/**
+ * Memory mapping flags.
+ */
+enum drm_map_flags {
+        _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
+        _DRM_READ_ONLY = 0x02,
+        _DRM_LOCKED = 0x04,          /**< shared, cached, locked */
+        _DRM_KERNEL = 0x08,          /**< kernel requires access */
+        _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
+        _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
+        _DRM_REMOVABLE = 0x40,       /**< Removable mapping */
+        _DRM_DRIVER = 0x80           /**< Managed by driver */
+};
+
+struct drm_ctx_priv_map {
+        unsigned int ctx_id;     /**< Context requesting private mapping */
+        void *handle;            /**< Handle of map */
+};
+
+/**
+ * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
+ * argument type.
+ *
+ * \sa drmAddMap().
+ */
+struct drm_map {
+        unsigned long offset;    /**< Requested physical address (0 for SAREA)*/
+        unsigned long size;      /**< Requested physical size (bytes) */
+        enum drm_map_type type;  /**< Type of memory to map */
+        enum drm_map_flags flags;        /**< Flags */
+        void *handle;            /**< User-space: "Handle" to pass to mmap() */
+                                 /**< Kernel-space: kernel-virtual address */
+        int mtrr;                /**< MTRR slot used */
+        /*   Private data */
+};
+
+/**
+ * DRM_IOCTL_GET_CLIENT ioctl argument type.
+ */
+struct drm_client {
+        int idx;                /**< Which client desired? */
+        int auth;               /**< Is client authenticated? */
+        unsigned long pid;      /**< Process ID */
+        unsigned long uid;      /**< User ID */
+        unsigned long magic;    /**< Magic */
+        unsigned long iocs;     /**< Ioctl count */
+};
+
+enum drm_stat_type {
+        _DRM_STAT_LOCK,
+        _DRM_STAT_OPENS,
+        _DRM_STAT_CLOSES,
+        _DRM_STAT_IOCTLS,
+        _DRM_STAT_LOCKS,
+        _DRM_STAT_UNLOCKS,
+        _DRM_STAT_VALUE,        /**< Generic value */
+        _DRM_STAT_BYTE,         /**< Generic byte counter (1024bytes/K) */
+        _DRM_STAT_COUNT,        /**< Generic non-byte counter (1000/k) */
+
+        _DRM_STAT_IRQ,          /**< IRQ */
+        _DRM_STAT_PRIMARY,      /**< Primary DMA bytes */
+        _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
+        _DRM_STAT_DMA,          /**< DMA */
+        _DRM_STAT_SPECIAL,      /**< Special DMA (e.g., priority or polled) */
+        _DRM_STAT_MISSED        /**< Missed DMA opportunity */
+            /* Add to the *END* of the list */
+};
+
+/**
+ * DRM_IOCTL_GET_STATS ioctl argument type.
+ */
+struct drm_stats {
+        unsigned long count;
+        struct {
+                unsigned long value;
+                enum drm_stat_type type;
+        } data[15];
+};
+
+/**
+ * Hardware locking flags.
+ */
+enum drm_lock_flags {
+        _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
+        _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
+        _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
+        _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
+        /* These *HALT* flags aren't supported yet
+           -- they will be used to support the
+           full-screen DGA-like mode. */
+        _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
+        _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
+};
+
+/**
+ * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
+ *
+ * \sa drmGetLock() and drmUnlock().
+ */
+struct drm_lock {
+        int context;
+        enum drm_lock_flags flags;
+};
+
+/**
+ * DMA flags
+ *
+ * \warning
+ * These values \e must match xf86drm.h.
+ *
+ * \sa drm_dma.
+ */
+enum drm_dma_flags {
+        /* Flags for DMA buffer dispatch */
+        _DRM_DMA_BLOCK = 0x01,        /**<
+                                       * Block until buffer dispatched.
+                                       *
+                                       * \note The buffer may not yet have
+                                       * been processed by the hardware --
+                                       * getting a hardware lock with the
+                                       * hardware quiescent will ensure
+                                       * that the buffer has been
+                                       * processed.
+                                       */
+        _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
+        _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
+
+        /* Flags for DMA buffer request */
+        _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
+        _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
+        _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
+};
+
+/**
+ * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
+ *
+ * \sa drmAddBufs().
+ */
+struct drm_buf_desc {
+        int count;               /**< Number of buffers of this size */
+        int size;                /**< Size in bytes */
+        int low_mark;            /**< Low water mark */
+        int high_mark;           /**< High water mark */
+        enum {
+                _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
+                _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
+                _DRM_SG_BUFFER = 0x04,  /**< Scatter/gather memory buffer */
+                _DRM_FB_BUFFER = 0x08,  /**< Buffer is in frame buffer */
+                _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
+        } flags;
+        unsigned long agp_start; /**<
+                                  * Start address of where the AGP buffers are
+                                  * in the AGP aperture
+                                  */
+};
+
+/**
+ * DRM_IOCTL_INFO_BUFS ioctl argument type.
+ */
+struct drm_buf_info {
+        int count;              /**< Entries in list */
+        struct drm_buf_desc __user *list;
+};
+
+/**
+ * DRM_IOCTL_FREE_BUFS ioctl argument type.
+ */
+struct drm_buf_free {
+        int count;
+        int __user *list;
+};
+
+/**
+ * Buffer information
+ *
+ * \sa drm_buf_map.
+ */
+struct drm_buf_pub {
+        int idx;                       /**< Index into the master buffer list */
+        int total;                     /**< Buffer size */
+        int used;                      /**< Amount of buffer in use (for DMA) */
+        void __user *address;          /**< Address of buffer */
+};
+
+/**
+ * DRM_IOCTL_MAP_BUFS ioctl argument type.
+ */
+struct drm_buf_map {
+        int count;              /**< Length of the buffer list */
+        void __user *virtual;           /**< Mmap'd area in user-virtual */
+        struct drm_buf_pub __user *list;        /**< Buffer information */
+};
+
+/**
+ * DRM_IOCTL_DMA ioctl argument type.
+ *
+ * Indices here refer to the offset into the buffer list in drm_buf_get.
+ *
+ * \sa drmDMA().
+ */
+struct drm_dma {
+        int context;                      /**< Context handle */
+        int send_count;                   /**< Number of buffers to send */
+        int __user *send_indices;         /**< List of handles to buffers */
+        int __user *send_sizes;           /**< Lengths of data to send */
+        enum drm_dma_flags flags;         /**< Flags */
+        int request_count;                /**< Number of buffers requested */
+        int request_size;                 /**< Desired size for buffers */
+        int __user *request_indices;      /**< Buffer information */
+        int __user *request_sizes;
+        int granted_count;                /**< Number of buffers granted */
+};
+
+enum drm_ctx_flags {
+        _DRM_CONTEXT_PRESERVED = 0x01,
+        _DRM_CONTEXT_2DONLY = 0x02
+};
+
+/**
+ * DRM_IOCTL_ADD_CTX ioctl argument type.
+ *
+ * \sa drmCreateContext() and drmDestroyContext().
+ */
+struct drm_ctx {
+        drm_context_t handle;
+        enum drm_ctx_flags flags;
+};
+
+/**
+ * DRM_IOCTL_RES_CTX ioctl argument type.
+ */
+struct drm_ctx_res {
+        int count;
+        struct drm_ctx __user *contexts;
+};
+
+/**
+ * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
+ */
+struct drm_draw {
+        drm_drawable_t handle;
+};
+
+/**
+ * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
+ */
+typedef enum {
+        DRM_DRAWABLE_CLIPRECTS,
+} drm_drawable_info_type_t;
+
+struct drm_update_draw {
+        drm_drawable_t handle;
+        unsigned int type;
+        unsigned int num;
+        unsigned long long data;
+};
+
+/**
+ * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
+ */
+struct drm_auth {
+        drm_magic_t magic;
+};
+
+/**
+ * DRM_IOCTL_IRQ_BUSID ioctl argument type.
+ *
+ * \sa drmGetInterruptFromBusID().
+ */
+struct drm_irq_busid {
+        int irq;        /**< IRQ number */
+        int busnum;     /**< bus number */
+        int devnum;     /**< device number */
+        int funcnum;    /**< function number */
+};
+
+enum drm_vblank_seq_type {
+        _DRM_VBLANK_ABSOLUTE = 0x0,     /**< Wait for specific vblank sequence number */
+        _DRM_VBLANK_RELATIVE = 0x1,     /**< Wait for given number of vblanks */
+        _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
+        _DRM_VBLANK_SECONDARY = 0x20000000,     /**< Secondary display controller */
+        _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
+};
+
+#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
+#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
+                                _DRM_VBLANK_NEXTONMISS)
+
+struct drm_wait_vblank_request {
+        enum drm_vblank_seq_type type;
+        unsigned int sequence;
+        unsigned long signal;
+};
+
+struct drm_wait_vblank_reply {
+        enum drm_vblank_seq_type type;
+        unsigned int sequence;
+        long tval_sec;
+        long tval_usec;
+};
+
+/**
+ * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
+ *
+ * \sa drmWaitVBlank().
+ */
+union drm_wait_vblank {
+        struct drm_wait_vblank_request request;
+        struct drm_wait_vblank_reply reply;
+};
+
+/**
+ * DRM_IOCTL_AGP_ENABLE ioctl argument type.
+ *
+ * \sa drmAgpEnable().
+ */
+struct drm_agp_mode {
+        unsigned long mode;     /**< AGP mode */
+};
+
+/**
+ * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
+ *
+ * \sa drmAgpAlloc() and drmAgpFree().
+ */
+struct drm_agp_buffer {
+        unsigned long size;     /**< In bytes -- will round to page boundary */
+        unsigned long handle;   /**< Used for binding / unbinding */
+        unsigned long type;     /**< Type of memory to allocate */
+        unsigned long physical; /**< Physical used by i810 */
+};
+
+/**
+ * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
+ *
+ * \sa drmAgpBind() and drmAgpUnbind().
+ */
+struct drm_agp_binding {
+        unsigned long handle;   /**< From drm_agp_buffer */
+        unsigned long offset;   /**< In bytes -- will round to page boundary */
+};
+
+/**
+ * DRM_IOCTL_AGP_INFO ioctl argument type.
+ *
+ * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
+ * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
+ * drmAgpVendorId() and drmAgpDeviceId().
+ */
+struct drm_agp_info {
+        int agp_version_major;
+        int agp_version_minor;
+        unsigned long mode;
+        unsigned long aperture_base;    /* physical address */
+        unsigned long aperture_size;    /* bytes */
+        unsigned long memory_allowed;   /* bytes */
+        unsigned long memory_used;
+
+        /* PCI information */
+        unsigned short id_vendor;
+        unsigned short id_device;
+};
+
+/**
+ * DRM_IOCTL_SG_ALLOC ioctl argument type.
+ */
+struct drm_scatter_gather {
+        unsigned long size;     /**< In bytes -- will round to page boundary */
+        unsigned long handle;   /**< Used for mapping / unmapping */
+};
+
+/**
+ * DRM_IOCTL_SET_VERSION ioctl argument type.
+ */
+struct drm_set_version {
+        int drm_di_major;
+        int drm_di_minor;
+        int drm_dd_major;
+        int drm_dd_minor;
+};
+
+#define DRM_IOCTL_BASE                  'd'
+#define DRM_IO(nr)                      _IO(DRM_IOCTL_BASE,nr)
+#define DRM_IOR(nr,type)                _IOR(DRM_IOCTL_BASE,nr,type)
+#define DRM_IOW(nr,type)                _IOW(DRM_IOCTL_BASE,nr,type)
+#define DRM_IOWR(nr,type)               _IOWR(DRM_IOCTL_BASE,nr,type)
+
+#define DRM_IOCTL_VERSION               DRM_IOWR(0x00, struct drm_version)
+#define DRM_IOCTL_GET_UNIQUE            DRM_IOWR(0x01, struct drm_unique)
+#define DRM_IOCTL_GET_MAGIC             DRM_IOR( 0x02, struct drm_auth)
+#define DRM_IOCTL_IRQ_BUSID             DRM_IOWR(0x03, struct drm_irq_busid)
+#define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
+#define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
+#define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
+#define DRM_IOCTL_SET_VERSION           DRM_IOWR(0x07, struct drm_set_version)
+
+#define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, struct drm_unique)
+#define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, struct drm_auth)
+#define DRM_IOCTL_BLOCK                 DRM_IOWR(0x12, struct drm_block)
+#define DRM_IOCTL_UNBLOCK               DRM_IOWR(0x13, struct drm_block)
+#define DRM_IOCTL_CONTROL               DRM_IOW( 0x14, struct drm_control)
+#define DRM_IOCTL_ADD_MAP               DRM_IOWR(0x15, struct drm_map)
+#define DRM_IOCTL_ADD_BUFS              DRM_IOWR(0x16, struct drm_buf_desc)
+#define DRM_IOCTL_MARK_BUFS             DRM_IOW( 0x17, struct drm_buf_desc)
+#define DRM_IOCTL_INFO_BUFS             DRM_IOWR(0x18, struct drm_buf_info)
+#define DRM_IOCTL_MAP_BUFS              DRM_IOWR(0x19, struct drm_buf_map)
+#define DRM_IOCTL_FREE_BUFS             DRM_IOW( 0x1a, struct drm_buf_free)
+
+#define DRM_IOCTL_RM_MAP                DRM_IOW( 0x1b, struct drm_map)
+
+#define DRM_IOCTL_SET_SAREA_CTX         DRM_IOW( 0x1c, struct drm_ctx_priv_map)
+#define DRM_IOCTL_GET_SAREA_CTX         DRM_IOWR(0x1d, struct drm_ctx_priv_map)
+
+#define DRM_IOCTL_ADD_CTX               DRM_IOWR(0x20, struct drm_ctx)
+#define DRM_IOCTL_RM_CTX                DRM_IOWR(0x21, struct drm_ctx)
+#define DRM_IOCTL_MOD_CTX               DRM_IOW( 0x22, struct drm_ctx)
+#define DRM_IOCTL_GET_CTX               DRM_IOWR(0x23, struct drm_ctx)
+#define DRM_IOCTL_SWITCH_CTX            DRM_IOW( 0x24, struct drm_ctx)
+#define DRM_IOCTL_NEW_CTX               DRM_IOW( 0x25, struct drm_ctx)
+#define DRM_IOCTL_RES_CTX               DRM_IOWR(0x26, struct drm_ctx_res)
+#define DRM_IOCTL_ADD_DRAW              DRM_IOWR(0x27, struct drm_draw)
+#define DRM_IOCTL_RM_DRAW               DRM_IOWR(0x28, struct drm_draw)
+#define DRM_IOCTL_DMA                   DRM_IOWR(0x29, struct drm_dma)
+#define DRM_IOCTL_LOCK                  DRM_IOW( 0x2a, struct drm_lock)
+#define DRM_IOCTL_UNLOCK                DRM_IOW( 0x2b, struct drm_lock)
+#define DRM_IOCTL_FINISH                DRM_IOW( 0x2c, struct drm_lock)
+
+#define DRM_IOCTL_AGP_ACQUIRE           DRM_IO(  0x30)
+#define DRM_IOCTL_AGP_RELEASE           DRM_IO(  0x31)
+#define DRM_IOCTL_AGP_ENABLE            DRM_IOW( 0x32, struct drm_agp_mode)
+#define DRM_IOCTL_AGP_INFO              DRM_IOR( 0x33, struct drm_agp_info)
+#define DRM_IOCTL_AGP_ALLOC             DRM_IOWR(0x34, struct drm_agp_buffer)
+#define DRM_IOCTL_AGP_FREE              DRM_IOW( 0x35, struct drm_agp_buffer)
+#define DRM_IOCTL_AGP_BIND              DRM_IOW( 0x36, struct drm_agp_binding)
+#define DRM_IOCTL_AGP_UNBIND            DRM_IOW( 0x37, struct drm_agp_binding)
+
+#define DRM_IOCTL_SG_ALLOC              DRM_IOWR(0x38, struct drm_scatter_gather)
+#define DRM_IOCTL_SG_FREE               DRM_IOW( 0x39, struct drm_scatter_gather)
+
+#define DRM_IOCTL_WAIT_VBLANK           DRM_IOWR(0x3a, union drm_wait_vblank)
+
+#define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, struct drm_update_draw)
+
+/**
+ * Device specific ioctls should only be in their respective headers
+ * The device specific ioctl range is from 0x40 to 0x99.
+ * Generic IOCTLS restart at 0xA0.
+ *
+ * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
+ * drmCommandReadWrite().
+ */
+#define DRM_COMMAND_BASE                0x40
+#define DRM_COMMAND_END                 0xA0
+
+/* typedef area */
+#ifndef __KERNEL__
+typedef struct drm_clip_rect drm_clip_rect_t;
+typedef struct drm_drawable_info drm_drawable_info_t;
+typedef struct drm_tex_region drm_tex_region_t;
+typedef struct drm_hw_lock drm_hw_lock_t;
+typedef struct drm_version drm_version_t;
+typedef struct drm_unique drm_unique_t;
+typedef struct drm_list drm_list_t;
+typedef struct drm_block drm_block_t;
+typedef struct drm_control drm_control_t;
+typedef enum drm_map_type drm_map_type_t;
+typedef enum drm_map_flags drm_map_flags_t;
+typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
+typedef struct drm_map drm_map_t;
+typedef struct drm_client drm_client_t;
+typedef enum drm_stat_type drm_stat_type_t;
+typedef struct drm_stats drm_stats_t;
+typedef enum drm_lock_flags drm_lock_flags_t;
+typedef struct drm_lock drm_lock_t;
+typedef enum drm_dma_flags drm_dma_flags_t;
+typedef struct drm_buf_desc drm_buf_desc_t;
+typedef struct drm_buf_info drm_buf_info_t;
+typedef struct drm_buf_free drm_buf_free_t;
+typedef struct drm_buf_pub drm_buf_pub_t;
+typedef struct drm_buf_map drm_buf_map_t;
+typedef struct drm_dma drm_dma_t;
+typedef union drm_wait_vblank drm_wait_vblank_t;
+typedef struct drm_agp_mode drm_agp_mode_t;
+typedef enum drm_ctx_flags drm_ctx_flags_t;
+typedef struct drm_ctx drm_ctx_t;
+typedef struct drm_ctx_res drm_ctx_res_t;
+typedef struct drm_draw drm_draw_t;
+typedef struct drm_update_draw drm_update_draw_t;
+typedef struct drm_auth drm_auth_t;
+typedef struct drm_irq_busid drm_irq_busid_t;
+typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
+
+typedef struct drm_agp_buffer drm_agp_buffer_t;
+typedef struct drm_agp_binding drm_agp_binding_t;
+typedef struct drm_agp_info drm_agp_info_t;
+typedef struct drm_scatter_gather drm_scatter_gather_t;
+typedef struct drm_set_version drm_set_version_t;
+#endif
+
+#endif
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
new file mode 100644
index 000000000000..1c1b13e29223
--- /dev/null
+++ b/include/drm/drmP.h
@@ -0,0 +1,1154 @@
+/**
+ * \file drmP.h
+ * Private header for Direct Rendering Manager
+ *
+ * \author Rickard E. (Rik) Faith <faith@valinux.com>
+ * \author Gareth Hughes <gareth@valinux.com>
+ */
+
+/*
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DRM_P_H_
+#define _DRM_P_H_
+
+/* If you want the memory alloc debug functionality, change define below */
+/* #define DEBUG_MEMORY */
+
+#ifdef __KERNEL__
+#ifdef __alpha__
+/* add include of current.h so that "current" is defined
+ * before static inline funcs in wait.h. Doing this so we
+ * can build the DRM (part of PI DRI). 4/21/2000 S + B */
+#include <asm/current.h>
+#endif                          /* __alpha__ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/file.h>
+#include <linux/pci.h>
+#include <linux/jiffies.h>
+#include <linux/smp_lock.h>     /* For (un)lock_kernel */
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/cdev.h>
+#include <linux/mutex.h>
+#if defined(__alpha__) || defined(__powerpc__)
+#include <asm/pgtable.h>        /* For pte_wrprotect */
+#endif
+#include <asm/io.h>
+#include <asm/mman.h>
+#include <asm/uaccess.h>
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+#include <linux/types.h>
+#include <linux/agp_backend.h>
+#endif
+#include <linux/workqueue.h>
+#include <linux/poll.h>
+#include <asm/pgalloc.h>
+#include "drm.h"
+
+#include <linux/idr.h>
+
+#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
+#define __OS_HAS_MTRR (defined(CONFIG_MTRR))
+
+struct drm_file;
+struct drm_device;
+
+#include "drm_os_linux.h"
+#include "drm_hashtab.h"
+
+/***********************************************************************/
+/** \name DRM template customization defaults */
+/*@{*/
+
+/* driver capabilities and requirements mask */
+#define DRIVER_USE_AGP     0x1
+#define DRIVER_REQUIRE_AGP 0x2
+#define DRIVER_USE_MTRR    0x4
+#define DRIVER_PCI_DMA     0x8
+#define DRIVER_SG          0x10
+#define DRIVER_HAVE_DMA    0x20
+#define DRIVER_HAVE_IRQ    0x40
+#define DRIVER_IRQ_SHARED  0x80
+#define DRIVER_IRQ_VBL     0x100
+#define DRIVER_DMA_QUEUE   0x200
+#define DRIVER_FB_DMA      0x400
+#define DRIVER_IRQ_VBL2    0x800
+
+/***********************************************************************/
+/** \name Begin the DRM... */
+/*@{*/
+
+#define DRM_DEBUG_CODE 2          /**< Include debugging code if > 1, then
+                                     also include looping detection. */
+
+#define DRM_MAGIC_HASH_ORDER  4  /**< Size of key hash table. Must be power of 2. */
+#define DRM_KERNEL_CONTEXT    0  /**< Change drm_resctx if changed */
+#define DRM_RESERVED_CONTEXTS 1  /**< Change drm_resctx if changed */
+#define DRM_LOOPING_LIMIT     5000000
+#define DRM_TIME_SLICE        (HZ/20)  /**< Time slice for GLXContexts */
+#define DRM_LOCK_SLICE        1 /**< Time slice for lock, in jiffies */
+
+#define DRM_FLAG_DEBUG    0x01
+
+#define DRM_MEM_DMA        0
+#define DRM_MEM_SAREA      1
+#define DRM_MEM_DRIVER     2
+#define DRM_MEM_MAGIC      3
+#define DRM_MEM_IOCTLS     4
+#define DRM_MEM_MAPS       5
+#define DRM_MEM_VMAS       6
+#define DRM_MEM_BUFS       7
+#define DRM_MEM_SEGS       8
+#define DRM_MEM_PAGES      9
+#define DRM_MEM_FILES     10
+#define DRM_MEM_QUEUES    11
+#define DRM_MEM_CMDS      12
+#define DRM_MEM_MAPPINGS  13
+#define DRM_MEM_BUFLISTS  14
+#define DRM_MEM_AGPLISTS  15
+#define DRM_MEM_TOTALAGP  16
+#define DRM_MEM_BOUNDAGP  17
+#define DRM_MEM_CTXBITMAP 18
+#define DRM_MEM_STUB      19
+#define DRM_MEM_SGLISTS   20
+#define DRM_MEM_CTXLIST   21
+#define DRM_MEM_MM        22
+#define DRM_MEM_HASHTAB   23
+
+#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
+#define DRM_MAP_HASH_OFFSET 0x10000000
+
+/*@}*/
+
+/***********************************************************************/
+/** \name Macros to make printk easier */
+/*@{*/
+
+/**
+ * Error output.
+ *
+ * \param fmt printf() like format string.
+ * \param arg arguments
+ */
+#define DRM_ERROR(fmt, arg...) \
+        printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg)
+
+/**
+ * Memory error output.
+ *
+ * \param area memory area where the error occurred.
+ * \param fmt printf() like format string.
+ * \param arg arguments
+ */
+#define DRM_MEM_ERROR(area, fmt, arg...) \
+        printk(KERN_ERR "[" DRM_NAME ":%s:%s] *ERROR* " fmt , __func__, \
+               drm_mem_stats[area].name , ##arg)
+
+#define DRM_INFO(fmt, arg...)  printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg)
+
+/**
+ * Debug output.
+ *
+ * \param fmt printf() like format string.
+ * \param arg arguments
+ */
+#if DRM_DEBUG_CODE
+#define DRM_DEBUG(fmt, arg...)                                          \
+        do {                                                            \
+                if ( drm_debug )                        \
+                        printk(KERN_DEBUG                               \
+                               "[" DRM_NAME ":%s] " fmt ,       \
+                               __func__ , ##arg);                       \
+        } while (0)
+#else
+#define DRM_DEBUG(fmt, arg...)           do { } while (0)
+#endif
+
+#define DRM_PROC_LIMIT (PAGE_SIZE-80)
+
+#define DRM_PROC_PRINT(fmt, arg...)                                     \
+   len += sprintf(&buf[len], fmt , ##arg);                              \
+   if (len > DRM_PROC_LIMIT) { *eof = 1; return len - offset; }
+
+#define DRM_PROC_PRINT_RET(ret, fmt, arg...)                            \
+   len += sprintf(&buf[len], fmt , ##arg);                              \
+   if (len > DRM_PROC_LIMIT) { ret; *eof = 1; return len - offset; }
+
+/*@}*/
+
+/***********************************************************************/
+/** \name Internal types and structures */
+/*@{*/
+
+#define DRM_ARRAY_SIZE(x) ARRAY_SIZE(x)
+
+#define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1))
+#define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x))
+#define DRM_WAITCOUNT(dev,idx) DRM_BUFCOUNT(&dev->queuelist[idx]->waitlist)
+
+#define DRM_IF_VERSION(maj, min) (maj << 16 | min)
+/**
+ * Get the private SAREA mapping.
+ *
+ * \param _dev DRM device.
+ * \param _ctx context number.
+ * \param _map output mapping.
+ */
+#define DRM_GET_PRIV_SAREA(_dev, _ctx, _map) do {       \
+        (_map) = (_dev)->context_sareas[_ctx];          \
+} while(0)
+
+/**
+ * Test that the hardware lock is held by the caller, returning otherwise.
+ *
+ * \param dev DRM device.
+ * \param filp file pointer of the caller.
+ */
+#define LOCK_TEST_WITH_RETURN( dev, file_priv )                         \
+do {                                                                    \
+        if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||           \
+             dev->lock.file_priv != file_priv ) {                       \
+                DRM_ERROR( "%s called without lock held, held  %d owner %p %p\n",\
+                           __func__, _DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ),\
+                           dev->lock.file_priv, file_priv );            \
+                return -EINVAL;                                         \
+        }                                                               \
+} while (0)
+
+/**
+ * Copy and IOCTL return string to user space
+ */
+#define DRM_COPY( name, value )                                         \
+        len = strlen( value );                                          \
+        if ( len > name##_len ) len = name##_len;                       \
+        name##_len = strlen( value );                                   \
+        if ( len && name ) {                                            \
+                if ( copy_to_user( name, value, len ) )                 \
+                        return -EFAULT;                                 \
+        }
+
+/**
+ * Ioctl function type.
+ *
+ * \param inode device inode.
+ * \param file_priv DRM file private pointer.
+ * \param cmd command.
+ * \param arg argument.
+ */
+typedef int drm_ioctl_t(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+
+typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
+                               unsigned long arg);
+
+#define DRM_AUTH        0x1
+#define DRM_MASTER      0x2
+#define DRM_ROOT_ONLY   0x4
+
+struct drm_ioctl_desc {
+        unsigned int cmd;
+        drm_ioctl_t *func;
+        int flags;
+};
+
+/**
+ * Creates a driver or general drm_ioctl_desc array entry for the given
+ * ioctl, for use by drm_ioctl().
+ */
+#define DRM_IOCTL_DEF(ioctl, func, flags) \
+        [DRM_IOCTL_NR(ioctl)] = {ioctl, func, flags}
+
+struct drm_magic_entry {
+        struct list_head head;
+        struct drm_hash_item hash_item;
+        struct drm_file *priv;
+};
+
+struct drm_vma_entry {
+        struct list_head head;
+        struct vm_area_struct *vma;
+        pid_t pid;
+};
+
+/**
+ * DMA buffer.
+ */
+struct drm_buf {
+        int idx;                       /**< Index into master buflist */
+        int total;                     /**< Buffer size */
+        int order;                     /**< log-base-2(total) */
+        int used;                      /**< Amount of buffer in use (for DMA) */
+        unsigned long offset;          /**< Byte offset (used internally) */
+        void *address;                 /**< Address of buffer */
+        unsigned long bus_address;     /**< Bus address of buffer */
+        struct drm_buf *next;          /**< Kernel-only: used for free list */
+        __volatile__ int waiting;      /**< On kernel DMA queue */
+        __volatile__ int pending;      /**< On hardware DMA queue */
+        wait_queue_head_t dma_wait;    /**< Processes waiting */
+        struct drm_file *file_priv;    /**< Private of holding file descr */
+        int context;                   /**< Kernel queue for this buffer */
+        int while_locked;              /**< Dispatch this buffer while locked */
+        enum {
+                DRM_LIST_NONE = 0,
+                DRM_LIST_FREE = 1,
+                DRM_LIST_WAIT = 2,
+                DRM_LIST_PEND = 3,
+                DRM_LIST_PRIO = 4,
+                DRM_LIST_RECLAIM = 5
+        } list;                        /**< Which list we're on */
+
+        int dev_priv_size;               /**< Size of buffer private storage */
+        void *dev_private;               /**< Per-buffer private storage */
+};
+
+/** bufs is one longer than it has to be */
+struct drm_waitlist {
+        int count;                      /**< Number of possible buffers */
+        struct drm_buf **bufs;          /**< List of pointers to buffers */
+        struct drm_buf **rp;                    /**< Read pointer */
+        struct drm_buf **wp;                    /**< Write pointer */
+        struct drm_buf **end;           /**< End pointer */
+        spinlock_t read_lock;
+        spinlock_t write_lock;
+};
+
+struct drm_freelist {
+        int initialized;               /**< Freelist in use */
+        atomic_t count;                /**< Number of free buffers */
+        struct drm_buf *next;          /**< End pointer */
+
+        wait_queue_head_t waiting;     /**< Processes waiting on free bufs */
+        int low_mark;                  /**< Low water mark */
+        int high_mark;                 /**< High water mark */
+        atomic_t wfh;                  /**< If waiting for high mark */
+        spinlock_t lock;
+};
+
+typedef struct drm_dma_handle {
+        dma_addr_t busaddr;
+        void *vaddr;
+        size_t size;
+} drm_dma_handle_t;
+
+/**
+ * Buffer entry.  There is one of this for each buffer size order.
+ */
+struct drm_buf_entry {
+        int buf_size;                   /**< size */
+        int buf_count;                  /**< number of buffers */
+        struct drm_buf *buflist;                /**< buffer list */
+        int seg_count;
+        int page_order;
+        struct drm_dma_handle **seglist;
+
+        struct drm_freelist freelist;
+};
+
+/** File private data */
+struct drm_file {
+        int authenticated;
+        int master;
+        pid_t pid;
+        uid_t uid;
+        drm_magic_t magic;
+        unsigned long ioctl_count;
+        struct list_head lhead;
+        struct drm_minor *minor;
+        int remove_auth_on_close;
+        unsigned long lock_count;
+        struct file *filp;
+        void *driver_priv;
+};
+
+/** Wait queue */
+struct drm_queue {
+        atomic_t use_count;             /**< Outstanding uses (+1) */
+        atomic_t finalization;          /**< Finalization in progress */
+        atomic_t block_count;           /**< Count of processes waiting */
+        atomic_t block_read;            /**< Queue blocked for reads */
+        wait_queue_head_t read_queue;   /**< Processes waiting on block_read */
+        atomic_t block_write;           /**< Queue blocked for writes */
+        wait_queue_head_t write_queue;  /**< Processes waiting on block_write */
+        atomic_t total_queued;          /**< Total queued statistic */
+        atomic_t total_flushed;         /**< Total flushes statistic */
+        atomic_t total_locks;           /**< Total locks statistics */
+        enum drm_ctx_flags flags;       /**< Context preserving and 2D-only */
+        struct drm_waitlist waitlist;   /**< Pending buffers */
+        wait_queue_head_t flush_queue;  /**< Processes waiting until flush */
+};
+
+/**
+ * Lock data.
+ */
+struct drm_lock_data {
+        struct drm_hw_lock *hw_lock;    /**< Hardware lock */
+        /** Private of lock holder's file (NULL=kernel) */
+        struct drm_file *file_priv;
+        wait_queue_head_t lock_queue;   /**< Queue of blocked processes */
+        unsigned long lock_time;        /**< Time of last lock in jiffies */
+        spinlock_t spinlock;
+        uint32_t kernel_waiters;
+        uint32_t user_waiters;
+        int idle_has_lock;
+};
+
+/**
+ * DMA data.
+ */
+struct drm_device_dma {
+
+        struct drm_buf_entry bufs[DRM_MAX_ORDER + 1];   /**< buffers, grouped by their size order */
+        int buf_count;                  /**< total number of buffers */
+        struct drm_buf **buflist;               /**< Vector of pointers into drm_device_dma::bufs */
+        int seg_count;
+        int page_count;                 /**< number of pages */
+        unsigned long *pagelist;        /**< page list */
+        unsigned long byte_count;
+        enum {
+                _DRM_DMA_USE_AGP = 0x01,
+                _DRM_DMA_USE_SG = 0x02,
+                _DRM_DMA_USE_FB = 0x04,
+                _DRM_DMA_USE_PCI_RO = 0x08
+        } flags;
+
+};
+
+/**
+ * AGP memory entry.  Stored as a doubly linked list.
+ */
+struct drm_agp_mem {
+        unsigned long handle;           /**< handle */
+        DRM_AGP_MEM *memory;
+        unsigned long bound;            /**< address */
+        int pages;
+        struct list_head head;
+};
+
+/**
+ * AGP data.
+ *
+ * \sa drm_agp_init() and drm_device::agp.
+ */
+struct drm_agp_head {
+        DRM_AGP_KERN agp_info;          /**< AGP device information */
+        struct list_head memory;
+        unsigned long mode;             /**< AGP mode */
+        struct agp_bridge_data *bridge;
+        int enabled;                    /**< whether the AGP bus as been enabled */
+        int acquired;                   /**< whether the AGP device has been acquired */
+        unsigned long base;
+        int agp_mtrr;
+        int cant_use_aperture;
+        unsigned long page_mask;
+};
+
+/**
+ * Scatter-gather memory.
+ */
+struct drm_sg_mem {
+        unsigned long handle;
+        void *virtual;
+        int pages;
+        struct page **pagelist;
+        dma_addr_t *busaddr;
+};
+
+struct drm_sigdata {
+        int context;
+        struct drm_hw_lock *lock;
+};
+
+
+/*
+ * Generic memory manager structs
+ */
+
+struct drm_mm_node {
+        struct list_head fl_entry;
+        struct list_head ml_entry;
+        int free;
+        unsigned long start;
+        unsigned long size;
+        struct drm_mm *mm;
+        void *private;
+};
+
+struct drm_mm {
+        struct list_head fl_entry;
+        struct list_head ml_entry;
+};
+
+
+/**
+ * Mappings list
+ */
+struct drm_map_list {
+        struct list_head head;          /**< list head */
+        struct drm_hash_item hash;
+        struct drm_map *map;                    /**< mapping */
+        uint64_t user_token;
+};
+
+typedef struct drm_map drm_local_map_t;
+
+/**
+ * Context handle list
+ */
+struct drm_ctx_list {
+        struct list_head head;          /**< list head */
+        drm_context_t handle;           /**< context handle */
+        struct drm_file *tag;           /**< associated fd private data */
+};
+
+struct drm_vbl_sig {
+        struct list_head head;
+        unsigned int sequence;
+        struct siginfo info;
+        struct task_struct *task;
+};
+
+/* location of GART table */
+#define DRM_ATI_GART_MAIN 1
+#define DRM_ATI_GART_FB   2
+
+#define DRM_ATI_GART_PCI 1
+#define DRM_ATI_GART_PCIE 2
+#define DRM_ATI_GART_IGP 3
+
+struct drm_ati_pcigart_info {
+        int gart_table_location;
+        int gart_reg_if;
+        void *addr;
+        dma_addr_t bus_addr;
+        dma_addr_t table_mask;
+        struct drm_dma_handle *table_handle;
+        drm_local_map_t mapping;
+        int table_size;
+};
+
+/**
+ * DRM driver structure. This structure represent the common code for
+ * a family of cards. There will one drm_device for each card present
+ * in this family
+ */
+struct drm_driver {
+        int (*load) (struct drm_device *, unsigned long flags);
+        int (*firstopen) (struct drm_device *);
+        int (*open) (struct drm_device *, struct drm_file *);
+        void (*preclose) (struct drm_device *, struct drm_file *file_priv);
+        void (*postclose) (struct drm_device *, struct drm_file *);
+        void (*lastclose) (struct drm_device *);
+        int (*unload) (struct drm_device *);
+        int (*suspend) (struct drm_device *, pm_message_t state);
+        int (*resume) (struct drm_device *);
+        int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file *file_priv);
+        void (*dma_ready) (struct drm_device *);
+        int (*dma_quiescent) (struct drm_device *);
+        int (*context_ctor) (struct drm_device *dev, int context);
+        int (*context_dtor) (struct drm_device *dev, int context);
+        int (*kernel_context_switch) (struct drm_device *dev, int old,
+                                      int new);
+        void (*kernel_context_switch_unlock) (struct drm_device *dev);
+        int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence);
+        int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence);
+        int (*dri_library_name) (struct drm_device *dev, char *buf);
+
+        /**
+         * Called by \c drm_device_is_agp.  Typically used to determine if a
+         * card is really attached to AGP or not.
+         *
+         * \param dev  DRM device handle
+         *
+         * \returns
+         * One of three values is returned depending on whether or not the
+         * card is absolutely \b not AGP (return of 0), absolutely \b is AGP
+         * (return of 1), or may or may not be AGP (return of 2).
+         */
+        int (*device_is_agp) (struct drm_device *dev);
+
+        /* these have to be filled in */
+
+        irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
+        void (*irq_preinstall) (struct drm_device *dev);
+        void (*irq_postinstall) (struct drm_device *dev);
+        void (*irq_uninstall) (struct drm_device *dev);
+        void (*reclaim_buffers) (struct drm_device *dev,
+                                 struct drm_file * file_priv);
+        void (*reclaim_buffers_locked) (struct drm_device *dev,
+                                        struct drm_file *file_priv);
+        void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
+                                            struct drm_file *file_priv);
+        unsigned long (*get_map_ofs) (struct drm_map * map);
+        unsigned long (*get_reg_ofs) (struct drm_device *dev);
+        void (*set_version) (struct drm_device *dev,
+                             struct drm_set_version *sv);
+
+        int major;
+        int minor;
+        int patchlevel;
+        char *name;
+        char *desc;
+        char *date;
+
+        u32 driver_features;
+        int dev_priv_size;
+        struct drm_ioctl_desc *ioctls;
+        int num_ioctls;
+        struct file_operations fops;
+        struct pci_driver pci_driver;
+};
+
+#define DRM_MINOR_UNASSIGNED 0
+#define DRM_MINOR_LEGACY 1
+
+/**
+ * DRM minor structure. This structure represents a drm minor number.
+ */
+struct drm_minor {
+        int index;                      /**< Minor device number */
+        int type;                       /**< Control or render */
+        dev_t device;                   /**< Device number for mknod */
+        struct device kdev;             /**< Linux device */
+        struct drm_device *dev;
+        struct proc_dir_entry *dev_root;  /**< proc directory entry */
+};
+
+/**
+ * DRM device structure. This structure represent a complete card that
+ * may contain multiple heads.
+ */
+struct drm_device {
+        char *unique;                   /**< Unique identifier: e.g., busid */
+        int unique_len;                 /**< Length of unique field */
+        char *devname;                  /**< For /proc/interrupts */
+        int if_version;                 /**< Highest interface version set */
+
+        int blocked;                    /**< Blocked due to VC switch? */
+
+        /** \name Locks */
+        /*@{ */
+        spinlock_t count_lock;          /**< For inuse, drm_device::open_count, drm_device::buf_use */
+        struct mutex struct_mutex;      /**< For others */
+        /*@} */
+
+        /** \name Usage Counters */
+        /*@{ */
+        int open_count;                 /**< Outstanding files open */
+        atomic_t ioctl_count;           /**< Outstanding IOCTLs pending */
+        atomic_t vma_count;             /**< Outstanding vma areas open */
+        int buf_use;                    /**< Buffers in use -- cannot alloc */
+        atomic_t buf_alloc;             /**< Buffer allocation in progress */
+        /*@} */
+
+        /** \name Performance counters */
+        /*@{ */
+        unsigned long counters;
+        enum drm_stat_type types[15];
+        atomic_t counts[15];
+        /*@} */
+
+        /** \name Authentication */
+        /*@{ */
+        struct list_head filelist;
+        struct drm_open_hash magiclist; /**< magic hash table */
+        struct list_head magicfree;
+        /*@} */
+
+        /** \name Memory management */
+        /*@{ */
+        struct list_head maplist;       /**< Linked list of regions */
+        int map_count;                  /**< Number of mappable regions */
+        struct drm_open_hash map_hash;  /**< User token hash table for maps */
+
+        /** \name Context handle management */
+        /*@{ */
+        struct list_head ctxlist;       /**< Linked list of context handles */
+        int ctx_count;                  /**< Number of context handles */
+        struct mutex ctxlist_mutex;     /**< For ctxlist */
+
+        struct idr ctx_idr;
+
+        struct list_head vmalist;       /**< List of vmas (for debugging) */
+        struct drm_lock_data lock;      /**< Information on hardware lock */
+        /*@} */
+
+        /** \name DMA queues (contexts) */
+        /*@{ */
+        int queue_count;                /**< Number of active DMA queues */
+        int queue_reserved;               /**< Number of reserved DMA queues */
+        int queue_slots;                /**< Actual length of queuelist */
+        struct drm_queue **queuelist;   /**< Vector of pointers to DMA queues */
+        struct drm_device_dma *dma;             /**< Optional pointer for DMA support */
+        /*@} */
+
+        /** \name Context support */
+        /*@{ */
+        int irq;                        /**< Interrupt used by board */
+        int irq_enabled;                /**< True if irq handler is enabled */
+        __volatile__ long context_flag; /**< Context swapping flag */
+        __volatile__ long interrupt_flag; /**< Interruption handler flag */
+        __volatile__ long dma_flag;     /**< DMA dispatch flag */
+        struct timer_list timer;        /**< Timer for delaying ctx switch */
+        wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */
+        int last_checked;               /**< Last context checked for DMA */
+        int last_context;               /**< Last current context */
+        unsigned long last_switch;      /**< jiffies at last context switch */
+        /*@} */
+
+        struct work_struct work;
+        /** \name VBLANK IRQ support */
+        /*@{ */
+
+        wait_queue_head_t vbl_queue;    /**< VBLANK wait queue */
+        atomic_t vbl_received;
+        atomic_t vbl_received2;         /**< number of secondary VBLANK interrupts */
+        spinlock_t vbl_lock;
+        struct list_head vbl_sigs;              /**< signal list to send on VBLANK */
+        struct list_head vbl_sigs2;     /**< signals to send on secondary VBLANK */
+        unsigned int vbl_pending;
+        spinlock_t tasklet_lock;        /**< For drm_locked_tasklet */
+        void (*locked_tasklet_func)(struct drm_device *dev);
+
+        /*@} */
+        cycles_t ctx_start;
+        cycles_t lck_start;
+
+        struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */
+        wait_queue_head_t buf_readers;  /**< Processes waiting to read */
+        wait_queue_head_t buf_writers;  /**< Processes waiting to ctx switch */
+
+        struct drm_agp_head *agp;       /**< AGP data */
+
+        struct pci_dev *pdev;           /**< PCI device structure */
+        int pci_vendor;                 /**< PCI vendor id */
+        int pci_device;                 /**< PCI device id */
+#ifdef __alpha__
+        struct pci_controller *hose;
+#endif
+        struct drm_sg_mem *sg;  /**< Scatter gather memory */
+        void *dev_private;              /**< device private data */
+        struct drm_sigdata sigdata;        /**< For block_all_signals */
+        sigset_t sigmask;
+
+        struct drm_driver *driver;
+        drm_local_map_t *agp_buffer_map;
+        unsigned int agp_buffer_token;
+        struct drm_minor *primary;              /**< render type primary screen head */
+
+        /** \name Drawable information */
+        /*@{ */
+        spinlock_t drw_lock;
+        struct idr drw_idr;
+        /*@} */
+};
+
+static __inline__ int drm_core_check_feature(struct drm_device *dev,
+                                             int feature)
+{
+        return ((dev->driver->driver_features & feature) ? 1 : 0);
+}
+
+#ifdef __alpha__
+#define drm_get_pci_domain(dev) dev->hose->index
+#else
+#define drm_get_pci_domain(dev) 0
+#endif
+
+#if __OS_HAS_AGP
+static inline int drm_core_has_AGP(struct drm_device *dev)
+{
+        return drm_core_check_feature(dev, DRIVER_USE_AGP);
+}
+#else
+#define drm_core_has_AGP(dev) (0)
+#endif
+
+#if __OS_HAS_MTRR
+static inline int drm_core_has_MTRR(struct drm_device *dev)
+{
+        return drm_core_check_feature(dev, DRIVER_USE_MTRR);
+}
+
+#define DRM_MTRR_WC             MTRR_TYPE_WRCOMB
+
+static inline int drm_mtrr_add(unsigned long offset, unsigned long size,
+                               unsigned int flags)
+{
+        return mtrr_add(offset, size, flags, 1);
+}
+
+static inline int drm_mtrr_del(int handle, unsigned long offset,
+                               unsigned long size, unsigned int flags)
+{
+        return mtrr_del(handle, offset, size);
+}
+
+#else
+#define drm_core_has_MTRR(dev) (0)
+
+#define DRM_MTRR_WC             0
+
+static inline int drm_mtrr_add(unsigned long offset, unsigned long size,
+                               unsigned int flags)
+{
+        return 0;
+}
+
+static inline int drm_mtrr_del(int handle, unsigned long offset,
+                               unsigned long size, unsigned int flags)
+{
+        return 0;
+}
+#endif
+
+/******************************************************************/
+/** \name Internal function definitions */
+/*@{*/
+
+                                /* Driver support (drm_drv.h) */
+extern int drm_init(struct drm_driver *driver);
+extern void drm_exit(struct drm_driver *driver);
+extern int drm_ioctl(struct inode *inode, struct file *filp,
+                     unsigned int cmd, unsigned long arg);
+extern long drm_compat_ioctl(struct file *filp,
+                             unsigned int cmd, unsigned long arg);
+extern int drm_lastclose(struct drm_device *dev);
+
+                                /* Device support (drm_fops.h) */
+extern int drm_open(struct inode *inode, struct file *filp);
+extern int drm_stub_open(struct inode *inode, struct file *filp);
+extern int drm_fasync(int fd, struct file *filp, int on);
+extern int drm_release(struct inode *inode, struct file *filp);
+
+                                /* Mapping support (drm_vm.h) */
+extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
+extern unsigned long drm_core_get_map_ofs(struct drm_map * map);
+extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev);
+extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
+
+                                /* Memory management support (drm_memory.h) */
+#include "drm_memory.h"
+extern void drm_mem_init(void);
+extern int drm_mem_info(char *buf, char **start, off_t offset,
+                        int request, int *eof, void *data);
+extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
+
+extern DRM_AGP_MEM *drm_alloc_agp(struct drm_device *dev, int pages, u32 type);
+extern int drm_free_agp(DRM_AGP_MEM * handle, int pages);
+extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
+extern int drm_unbind_agp(DRM_AGP_MEM * handle);
+
+                                /* Misc. IOCTL support (drm_ioctl.h) */
+extern int drm_irq_by_busid(struct drm_device *dev, void *data,
+                            struct drm_file *file_priv);
+extern int drm_getunique(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+extern int drm_setunique(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+extern int drm_getmap(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_getclient(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+extern int drm_getstats(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_setversion(struct drm_device *dev, void *data,
+                          struct drm_file *file_priv);
+extern int drm_noop(struct drm_device *dev, void *data,
+                    struct drm_file *file_priv);
+
+                                /* Context IOCTL support (drm_context.h) */
+extern int drm_resctx(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_addctx(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_modctx(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_getctx(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_switchctx(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+extern int drm_newctx(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_rmctx(struct drm_device *dev, void *data,
+                     struct drm_file *file_priv);
+
+extern int drm_ctxbitmap_init(struct drm_device *dev);
+extern void drm_ctxbitmap_cleanup(struct drm_device *dev);
+extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
+
+extern int drm_setsareactx(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
+extern int drm_getsareactx(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
+
+                                /* Drawable IOCTL support (drm_drawable.h) */
+extern int drm_adddraw(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv);
+extern int drm_rmdraw(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_update_drawable_info(struct drm_device *dev, void *data,
+                                    struct drm_file *file_priv);
+extern struct drm_drawable_info *drm_get_drawable_info(struct drm_device *dev,
+                                                  drm_drawable_t id);
+extern void drm_drawable_free_all(struct drm_device *dev);
+
+                                /* Authentication IOCTL support (drm_auth.h) */
+extern int drm_getmagic(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_authmagic(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+
+                                /* Locking IOCTL support (drm_lock.h) */
+extern int drm_lock(struct drm_device *dev, void *data,
+                    struct drm_file *file_priv);
+extern int drm_unlock(struct drm_device *dev, void *data,
+                      struct drm_file *file_priv);
+extern int drm_lock_take(struct drm_lock_data *lock_data, unsigned int context);
+extern int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context);
+extern void drm_idlelock_take(struct drm_lock_data *lock_data);
+extern void drm_idlelock_release(struct drm_lock_data *lock_data);
+
+/*
+ * These are exported to drivers so that they can implement fencing using
+ * DMA quiscent + idle. DMA quiescent usually requires the hardware lock.
+ */
+
+extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv);
+
+                                /* Buffer management support (drm_bufs.h) */
+extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request);
+extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request);
+extern int drm_addmap(struct drm_device *dev, unsigned int offset,
+                      unsigned int size, enum drm_map_type type,
+                      enum drm_map_flags flags, drm_local_map_t ** map_ptr);
+extern int drm_addmap_ioctl(struct drm_device *dev, void *data,
+                            struct drm_file *file_priv);
+extern int drm_rmmap(struct drm_device *dev, drm_local_map_t *map);
+extern int drm_rmmap_locked(struct drm_device *dev, drm_local_map_t *map);
+extern int drm_rmmap_ioctl(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
+extern int drm_addbufs(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv);
+extern int drm_infobufs(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_markbufs(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_freebufs(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_mapbufs(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv);
+extern int drm_order(unsigned long size);
+extern unsigned long drm_get_resource_start(struct drm_device *dev,
+                                            unsigned int resource);
+extern unsigned long drm_get_resource_len(struct drm_device *dev,
+                                          unsigned int resource);
+
+                                /* DMA support (drm_dma.h) */
+extern int drm_dma_setup(struct drm_device *dev);
+extern void drm_dma_takedown(struct drm_device *dev);
+extern void drm_free_buffer(struct drm_device *dev, struct drm_buf * buf);
+extern void drm_core_reclaim_buffers(struct drm_device *dev,
+                                     struct drm_file *filp);
+
+                                /* IRQ support (drm_irq.h) */
+extern int drm_control(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv);
+extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
+extern int drm_irq_uninstall(struct drm_device *dev);
+extern void drm_driver_irq_preinstall(struct drm_device *dev);
+extern void drm_driver_irq_postinstall(struct drm_device *dev);
+extern void drm_driver_irq_uninstall(struct drm_device *dev);
+
+extern int drm_wait_vblank(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
+extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
+extern void drm_vbl_send_signals(struct drm_device *dev);
+extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
+
+                                /* AGP/GART support (drm_agpsupport.h) */
+extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
+extern int drm_agp_acquire(struct drm_device *dev);
+extern int drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
+                                 struct drm_file *file_priv);
+extern int drm_agp_release(struct drm_device *dev);
+extern int drm_agp_release_ioctl(struct drm_device *dev, void *data,
+                                 struct drm_file *file_priv);
+extern int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode);
+extern int drm_agp_enable_ioctl(struct drm_device *dev, void *data,
+                                struct drm_file *file_priv);
+extern int drm_agp_info(struct drm_device *dev, struct drm_agp_info *info);
+extern int drm_agp_info_ioctl(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request);
+extern int drm_agp_alloc_ioctl(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+extern int drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request);
+extern int drm_agp_free_ioctl(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request);
+extern int drm_agp_unbind_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *file_priv);
+extern int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request);
+extern int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type);
+extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
+extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
+extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
+
+                                /* Stub support (drm_stub.h) */
+extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
+                       struct drm_driver *driver);
+extern int drm_put_dev(struct drm_device *dev);
+extern int drm_put_minor(struct drm_minor **minor);
+extern unsigned int drm_debug;
+
+extern struct class *drm_class;
+extern struct proc_dir_entry *drm_proc_root;
+
+extern struct idr drm_minors_idr;
+
+extern drm_local_map_t *drm_getsarea(struct drm_device *dev);
+
+                                /* Proc support (drm_proc.h) */
+extern int drm_proc_init(struct drm_minor *minor, int minor_id,
+                         struct proc_dir_entry *root);
+extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root);
+
+                                /* Scatter Gather Support (drm_scatter.h) */
+extern void drm_sg_cleanup(struct drm_sg_mem * entry);
+extern int drm_sg_alloc_ioctl(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+extern int drm_sg_alloc(struct drm_device *dev, struct drm_scatter_gather * request);
+extern int drm_sg_free(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv);
+
+                               /* ATI PCIGART support (ati_pcigart.h) */
+extern int drm_ati_pcigart_init(struct drm_device *dev,
+                                struct drm_ati_pcigart_info * gart_info);
+extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
+                                   struct drm_ati_pcigart_info * gart_info);
+
+extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
+                                       size_t align, dma_addr_t maxaddr);
+extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
+extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
+
+                               /* sysfs support (drm_sysfs.c) */
+struct drm_sysfs_class;
+extern struct class *drm_sysfs_create(struct module *owner, char *name);
+extern void drm_sysfs_destroy(void);
+extern int drm_sysfs_device_add(struct drm_minor *minor);
+extern void drm_sysfs_device_remove(struct drm_minor *minor);
+
+/*
+ * Basic memory manager support (drm_mm.c)
+ */
+extern struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent,
+                                       unsigned long size,
+                                       unsigned alignment);
+extern void drm_mm_put_block(struct drm_mm_node * cur);
+extern struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, unsigned long size,
+                                         unsigned alignment, int best_match);
+extern int drm_mm_init(struct drm_mm *mm, unsigned long start, unsigned long size);
+extern void drm_mm_takedown(struct drm_mm *mm);
+extern int drm_mm_clean(struct drm_mm *mm);
+extern unsigned long drm_mm_tail_space(struct drm_mm *mm);
+extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size);
+extern int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size);
+
+extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev);
+extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev);
+extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev);
+
+static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev,
+                                                   unsigned int token)
+{
+        struct drm_map_list *_entry;
+        list_for_each_entry(_entry, &dev->maplist, head)
+            if (_entry->user_token == token)
+                return _entry->map;
+        return NULL;
+}
+
+static __inline__ int drm_device_is_agp(struct drm_device *dev)
+{
+        if (dev->driver->device_is_agp != NULL) {
+                int err = (*dev->driver->device_is_agp) (dev);
+
+                if (err != 2) {
+                        return err;
+                }
+        }
+
+        return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
+}
+
+static __inline__ int drm_device_is_pcie(struct drm_device *dev)
+{
+        return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
+}
+
+static __inline__ void drm_core_dropmap(struct drm_map *map)
+{
+}
+
+#ifndef DEBUG_MEMORY
+/** Wrapper around kmalloc() */
+static __inline__ void *drm_alloc(size_t size, int area)
+{
+        return kmalloc(size, GFP_KERNEL);
+}
+
+/** Wrapper around kfree() */
+static __inline__ void drm_free(void *pt, size_t size, int area)
+{
+        kfree(pt);
+}
+
+/** Wrapper around kcalloc() */
+static __inline__ void *drm_calloc(size_t nmemb, size_t size, int area)
+{
+        return kcalloc(nmemb, size, GFP_KERNEL);
+}
+#else
+extern void *drm_alloc(size_t size, int area);
+extern void drm_free(void *pt, size_t size, int area);
+extern void *drm_calloc(size_t nmemb, size_t size, int area);
+#endif
+
+/*@}*/
+
+#endif                          /* __KERNEL__ */
+#endif
diff --git a/include/drm/drm_core.h b/include/drm/drm_core.h
new file mode 100644
index 000000000000..316739036079
--- /dev/null
+++ b/include/drm/drm_core.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2004 Jon Smirl <jonsmirl@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#define CORE_AUTHOR             "Gareth Hughes, Leif Delgass, José Fonseca, Jon Smirl"
+
+#define CORE_NAME               "drm"
+#define CORE_DESC               "DRM shared core routines"
+#define CORE_DATE               "20060810"
+
+#define DRM_IF_MAJOR    1
+#define DRM_IF_MINOR    3
+
+#define CORE_MAJOR      1
+#define CORE_MINOR      1
+#define CORE_PATCHLEVEL 0
diff --git a/include/drm/drm_hashtab.h b/include/drm/drm_hashtab.h
new file mode 100644
index 000000000000..cd2b189e1be6
--- /dev/null
+++ b/include/drm/drm_hashtab.h
@@ -0,0 +1,67 @@
+/**************************************************************************
+ *
+ * Copyright 2006 Tungsten Graphics, Inc., Bismack, ND. USA.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ **************************************************************************/
+/*
+ * Simple open hash tab implementation.
+ *
+ * Authors:
+ * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
+ */
+
+#ifndef DRM_HASHTAB_H
+#define DRM_HASHTAB_H
+
+#define drm_hash_entry(_ptr, _type, _member) container_of(_ptr, _type, _member)
+
+struct drm_hash_item {
+        struct hlist_node head;
+        unsigned long key;
+};
+
+struct drm_open_hash {
+        unsigned int size;
+        unsigned int order;
+        unsigned int fill;
+        struct hlist_head *table;
+        int use_vmalloc;
+};
+
+
+extern int drm_ht_create(struct drm_open_hash *ht, unsigned int order);
+extern int drm_ht_insert_item(struct drm_open_hash *ht, struct drm_hash_item *item);
+extern int drm_ht_just_insert_please(struct drm_open_hash *ht, struct drm_hash_item *item,
+                                     unsigned long seed, int bits, int shift,
+                                     unsigned long add);
+extern int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key, struct drm_hash_item **item);
+
+extern void drm_ht_verbose_list(struct drm_open_hash *ht, unsigned long key);
+extern int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key);
+extern int drm_ht_remove_item(struct drm_open_hash *ht, struct drm_hash_item *item);
+extern void drm_ht_remove(struct drm_open_hash *ht);
+
+
+#endif
diff --git a/include/drm/drm_memory.h b/include/drm/drm_memory.h
new file mode 100644
index 000000000000..63e425b5ea82
--- /dev/null
+++ b/include/drm/drm_memory.h
@@ -0,0 +1,61 @@
+/**
+ * \file drm_memory.h
+ * Memory management wrappers for DRM
+ *
+ * \author Rickard E. (Rik) Faith <faith@valinux.com>
+ * \author Gareth Hughes <gareth@valinux.com>
+ */
+
+/*
+ * Created: Thu Feb  4 14:00:34 1999 by faith@valinux.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/highmem.h>
+#include <linux/vmalloc.h>
+#include "drmP.h"
+
+/**
+ * Cut down version of drm_memory_debug.h, which used to be called
+ * drm_memory.h.
+ */
+
+#if __OS_HAS_AGP
+
+#include <linux/vmalloc.h>
+
+#ifdef HAVE_PAGE_AGP
+#include <asm/agp.h>
+#else
+# ifdef __powerpc__
+#  define PAGE_AGP      __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
+# else
+#  define PAGE_AGP      PAGE_KERNEL
+# endif
+#endif
+
+#else                           /* __OS_HAS_AGP */
+
+#endif
diff --git a/include/drm/drm_memory_debug.h b/include/drm/drm_memory_debug.h
new file mode 100644
index 000000000000..6463271deea8
--- /dev/null
+++ b/include/drm/drm_memory_debug.h
@@ -0,0 +1,309 @@
+/**
+ * \file drm_memory_debug.h
+ * Memory management wrappers for DRM.
+ *
+ * \author Rickard E. (Rik) Faith <faith@valinux.com>
+ * \author Gareth Hughes <gareth@valinux.com>
+ */
+
+/*
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "drmP.h"
+
+typedef struct drm_mem_stats {
+        const char *name;
+        int succeed_count;
+        int free_count;
+        int fail_count;
+        unsigned long bytes_allocated;
+        unsigned long bytes_freed;
+} drm_mem_stats_t;
+
+static DEFINE_SPINLOCK(drm_mem_lock);
+static unsigned long drm_ram_available = 0;     /* In pages */
+static unsigned long drm_ram_used = 0;
+static drm_mem_stats_t drm_mem_stats[] =
+{
+        [DRM_MEM_DMA] = {"dmabufs"},
+        [DRM_MEM_SAREA] = {"sareas"},
+        [DRM_MEM_DRIVER] = {"driver"},
+        [DRM_MEM_MAGIC] = {"magic"},
+        [DRM_MEM_IOCTLS] = {"ioctltab"},
+        [DRM_MEM_MAPS] = {"maplist"},
+        [DRM_MEM_VMAS] = {"vmalist"},
+        [DRM_MEM_BUFS] = {"buflist"},
+        [DRM_MEM_SEGS] = {"seglist"},
+        [DRM_MEM_PAGES] = {"pagelist"},
+        [DRM_MEM_FILES] = {"files"},
+        [DRM_MEM_QUEUES] = {"queues"},
+        [DRM_MEM_CMDS] = {"commands"},
+        [DRM_MEM_MAPPINGS] = {"mappings"},
+        [DRM_MEM_BUFLISTS] = {"buflists"},
+        [DRM_MEM_AGPLISTS] = {"agplist"},
+        [DRM_MEM_SGLISTS] = {"sglist"},
+        [DRM_MEM_TOTALAGP] = {"totalagp"},
+        [DRM_MEM_BOUNDAGP] = {"boundagp"},
+        [DRM_MEM_CTXBITMAP] = {"ctxbitmap"},
+        [DRM_MEM_CTXLIST] = {"ctxlist"},
+        [DRM_MEM_STUB] = {"stub"},
+        {NULL, 0,}              /* Last entry must be null */
+};
+
+void drm_mem_init (void) {
+        drm_mem_stats_t *mem;
+        struct sysinfo si;
+
+        for (mem = drm_mem_stats; mem->name; ++mem) {
+                mem->succeed_count = 0;
+                mem->free_count = 0;
+                mem->fail_count = 0;
+                mem->bytes_allocated = 0;
+                mem->bytes_freed = 0;
+        }
+
+        si_meminfo(&si);
+        drm_ram_available = si.totalram;
+        drm_ram_used = 0;
+}
+
+/* drm_mem_info is called whenever a process reads /dev/drm/mem. */
+
+static int drm__mem_info (char *buf, char **start, off_t offset,
+                           int request, int *eof, void *data) {
+        drm_mem_stats_t *pt;
+        int len = 0;
+
+        if (offset > DRM_PROC_LIMIT) {
+                *eof = 1;
+                return 0;
+        }
+
+        *eof = 0;
+        *start = &buf[offset];
+
+        DRM_PROC_PRINT("                  total counts                  "
+                       " |    outstanding  \n");
+        DRM_PROC_PRINT("type       alloc freed fail     bytes      freed"
+                       " | allocs      bytes\n\n");
+        DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB         |\n",
+                       "system", 0, 0, 0,
+                       drm_ram_available << (PAGE_SHIFT - 10));
+        DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB         |\n",
+                       "locked", 0, 0, 0, drm_ram_used >> 10);
+        DRM_PROC_PRINT("\n");
+        for (pt = drm_mem_stats; pt->name; pt++) {
+                DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu %10lu | %6d %10ld\n",
+                               pt->name,
+                               pt->succeed_count,
+                               pt->free_count,
+                               pt->fail_count,
+                               pt->bytes_allocated,
+                               pt->bytes_freed,
+                               pt->succeed_count - pt->free_count,
+                               (long)pt->bytes_allocated
+                               - (long)pt->bytes_freed);
+        }
+
+        if (len > request + offset)
+                return request;
+        *eof = 1;
+        return len - offset;
+}
+
+int drm_mem_info (char *buf, char **start, off_t offset,
+                   int len, int *eof, void *data) {
+        int ret;
+
+        spin_lock(&drm_mem_lock);
+        ret = drm__mem_info (buf, start, offset, len, eof, data);
+        spin_unlock(&drm_mem_lock);
+        return ret;
+}
+
+void *drm_alloc (size_t size, int area) {
+        void *pt;
+
+        if (!size) {
+                DRM_MEM_ERROR(area, "Allocating 0 bytes\n");
+                return NULL;
+        }
+
+        if (!(pt = kmalloc(size, GFP_KERNEL))) {
+                spin_lock(&drm_mem_lock);
+                ++drm_mem_stats[area].fail_count;
+                spin_unlock(&drm_mem_lock);
+                return NULL;
+        }
+        spin_lock(&drm_mem_lock);
+        ++drm_mem_stats[area].succeed_count;
+        drm_mem_stats[area].bytes_allocated += size;
+        spin_unlock(&drm_mem_lock);
+        return pt;
+}
+
+void *drm_calloc (size_t nmemb, size_t size, int area) {
+        void *addr;
+
+        addr = drm_alloc (nmemb * size, area);
+        if (addr != NULL)
+                memset((void *)addr, 0, size * nmemb);
+
+        return addr;
+}
+
+void *drm_realloc (void *oldpt, size_t oldsize, size_t size, int area) {
+        void *pt;
+
+        if (!(pt = drm_alloc (size, area)))
+                return NULL;
+        if (oldpt && oldsize) {
+                memcpy(pt, oldpt, oldsize);
+                drm_free (oldpt, oldsize, area);
+        }
+        return pt;
+}
+
+void drm_free (void *pt, size_t size, int area) {
+        int alloc_count;
+        int free_count;
+
+        if (!pt)
+                DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n");
+        else
+                kfree(pt);
+        spin_lock(&drm_mem_lock);
+        drm_mem_stats[area].bytes_freed += size;
+        free_count = ++drm_mem_stats[area].free_count;
+        alloc_count = drm_mem_stats[area].succeed_count;
+        spin_unlock(&drm_mem_lock);
+        if (free_count > alloc_count) {
+                DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n",
+                              free_count, alloc_count);
+        }
+}
+
+#if __OS_HAS_AGP
+
+DRM_AGP_MEM *drm_alloc_agp (drm_device_t *dev, int pages, u32 type) {
+        DRM_AGP_MEM *handle;
+
+        if (!pages) {
+                DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n");
+                return NULL;
+        }
+
+        if ((handle = drm_agp_allocate_memory (pages, type))) {
+                spin_lock(&drm_mem_lock);
+                ++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count;
+                drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated
+                    += pages << PAGE_SHIFT;
+                spin_unlock(&drm_mem_lock);
+                return handle;
+        }
+        spin_lock(&drm_mem_lock);
+        ++drm_mem_stats[DRM_MEM_TOTALAGP].fail_count;
+        spin_unlock(&drm_mem_lock);
+        return NULL;
+}
+
+int drm_free_agp (DRM_AGP_MEM * handle, int pages) {
+        int alloc_count;
+        int free_count;
+        int retval = -EINVAL;
+
+        if (!handle) {
+                DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
+                              "Attempt to free NULL AGP handle\n");
+                return retval;
+        }
+
+        if (drm_agp_free_memory (handle)) {
+                spin_lock(&drm_mem_lock);
+                free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count;
+                alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count;
+                drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed
+                    += pages << PAGE_SHIFT;
+                spin_unlock(&drm_mem_lock);
+                if (free_count > alloc_count) {
+                        DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
+                                      "Excess frees: %d frees, %d allocs\n",
+                                      free_count, alloc_count);
+                }
+                return 0;
+        }
+        return retval;
+}
+
+int drm_bind_agp (DRM_AGP_MEM * handle, unsigned int start) {
+        int retcode = -EINVAL;
+
+        if (!handle) {
+                DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
+                              "Attempt to bind NULL AGP handle\n");
+                return retcode;
+        }
+
+        if (!(retcode = drm_agp_bind_memory (handle, start))) {
+                spin_lock(&drm_mem_lock);
+                ++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count;
+                drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated
+                    += handle->page_count << PAGE_SHIFT;
+                spin_unlock(&drm_mem_lock);
+                return retcode;
+        }
+        spin_lock(&drm_mem_lock);
+        ++drm_mem_stats[DRM_MEM_BOUNDAGP].fail_count;
+        spin_unlock(&drm_mem_lock);
+        return retcode;
+}
+
+int drm_unbind_agp (DRM_AGP_MEM * handle) {
+        int alloc_count;
+        int free_count;
+        int retcode = -EINVAL;
+
+        if (!handle) {
+                DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
+                              "Attempt to unbind NULL AGP handle\n");
+                return retcode;
+        }
+
+        if ((retcode = drm_agp_unbind_memory (handle)))
+                return retcode;
+        spin_lock(&drm_mem_lock);
+        free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count;
+        alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count;
+        drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed
+            += handle->page_count << PAGE_SHIFT;
+        spin_unlock(&drm_mem_lock);
+        if (free_count > alloc_count) {
+                DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
+                              "Excess frees: %d frees, %d allocs\n",
+                              free_count, alloc_count);
+        }
+        return retcode;
+}
+#endif
diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h
new file mode 100644
index 000000000000..8dbd2572b7c3
--- /dev/null
+++ b/include/drm/drm_os_linux.h
@@ -0,0 +1,108 @@
+/**
+ * \file drm_os_linux.h
+ * OS abstraction macros.
+ */
+
+#include <linux/interrupt.h>    /* For task queue support */
+#include <linux/delay.h>
+
+/** Current process ID */
+#define DRM_CURRENTPID                  task_pid_nr(current)
+#define DRM_SUSER(p)                    capable(CAP_SYS_ADMIN)
+#define DRM_UDELAY(d)                   udelay(d)
+/** Read a byte from a MMIO region */
+#define DRM_READ8(map, offset)          readb(((void __iomem *)(map)->handle) + (offset))
+/** Read a word from a MMIO region */
+#define DRM_READ16(map, offset)         readw(((void __iomem *)(map)->handle) + (offset))
+/** Read a dword from a MMIO region */
+#define DRM_READ32(map, offset)         readl(((void __iomem *)(map)->handle) + (offset))
+/** Write a byte into a MMIO region */
+#define DRM_WRITE8(map, offset, val)    writeb(val, ((void __iomem *)(map)->handle) + (offset))
+/** Write a word into a MMIO region */
+#define DRM_WRITE16(map, offset, val)   writew(val, ((void __iomem *)(map)->handle) + (offset))
+/** Write a dword into a MMIO region */
+#define DRM_WRITE32(map, offset, val)   writel(val, ((void __iomem *)(map)->handle) + (offset))
+/** Read memory barrier */
+#define DRM_READMEMORYBARRIER()         rmb()
+/** Write memory barrier */
+#define DRM_WRITEMEMORYBARRIER()        wmb()
+/** Read/write memory barrier */
+#define DRM_MEMORYBARRIER()             mb()
+
+/** IRQ handler arguments and return type and values */
+#define DRM_IRQ_ARGS            int irq, void *arg
+
+/** AGP types */
+#if __OS_HAS_AGP
+#define DRM_AGP_MEM             struct agp_memory
+#define DRM_AGP_KERN            struct agp_kern_info
+#else
+/* define some dummy types for non AGP supporting kernels */
+struct no_agp_kern {
+        unsigned long aper_base;
+        unsigned long aper_size;
+};
+#define DRM_AGP_MEM             int
+#define DRM_AGP_KERN            struct no_agp_kern
+#endif
+
+#if !(__OS_HAS_MTRR)
+static __inline__ int mtrr_add(unsigned long base, unsigned long size,
+                               unsigned int type, char increment)
+{
+        return -ENODEV;
+}
+
+static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size)
+{
+        return -ENODEV;
+}
+
+#define MTRR_TYPE_WRCOMB     1
+
+#endif
+
+/** Other copying of data to kernel space */
+#define DRM_COPY_FROM_USER(arg1, arg2, arg3)            \
+        copy_from_user(arg1, arg2, arg3)
+/** Other copying of data from kernel space */
+#define DRM_COPY_TO_USER(arg1, arg2, arg3)              \
+        copy_to_user(arg1, arg2, arg3)
+/* Macros for copyfrom user, but checking readability only once */
+#define DRM_VERIFYAREA_READ( uaddr, size )              \
+        (access_ok( VERIFY_READ, uaddr, size ) ? 0 : -EFAULT)
+#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3)  \
+        __copy_from_user(arg1, arg2, arg3)
+#define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3)    \
+        __copy_to_user(arg1, arg2, arg3)
+#define DRM_GET_USER_UNCHECKED(val, uaddr)              \
+        __get_user(val, uaddr)
+
+#define DRM_HZ HZ
+
+#define DRM_WAIT_ON( ret, queue, timeout, condition )           \
+do {                                                            \
+        DECLARE_WAITQUEUE(entry, current);                      \
+        unsigned long end = jiffies + (timeout);                \
+        add_wait_queue(&(queue), &entry);                       \
+                                                                \
+        for (;;) {                                              \
+                __set_current_state(TASK_INTERRUPTIBLE);        \
+                if (condition)                                  \
+                        break;                                  \
+                if (time_after_eq(jiffies, end)) {              \
+                        ret = -EBUSY;                           \
+                        break;                                  \
+                }                                               \
+                schedule_timeout((HZ/100 > 1) ? HZ/100 : 1);    \
+                if (signal_pending(current)) {                  \
+                        ret = -EINTR;                           \
+                        break;                                  \
+                }                                               \
+        }                                                       \
+        __set_current_state(TASK_RUNNING);                      \
+        remove_wait_queue(&(queue), &entry);                    \
+} while (0)
+
+#define DRM_WAKEUP( queue ) wake_up_interruptible( queue )
+#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
new file mode 100644
index 000000000000..135bd19499fc
--- /dev/null
+++ b/include/drm/drm_pciids.h
@@ -0,0 +1,415 @@
+/*
+   This file is auto-generated from the drm_pciids.txt in the DRM CVS
+   Please contact dri-devel@lists.sf.net to add new cards to this list
+*/
+#define radeon_PCI_IDS \
+        {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \
+        {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
+        {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+        {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
+        {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+        {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+        {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
+        {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
+        {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+        {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+        {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
+        {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
+        {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
+        {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
+        {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+        {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+        {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+        {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
+        {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
+        {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+        {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+        {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+        {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
+        {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+        {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+        {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+        {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+        {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+        {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+        {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
+        {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+        {0, 0, 0}
+
+#define r128_PCI_IDS \
+        {0x1002, 0x4c45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4d46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5041, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5044, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5045, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5046, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5047, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5048, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5049, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x504A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x504B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x504C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x504D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x504E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x504F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x524b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x524c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x534d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x544C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x5452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
+
+#define mga_PCI_IDS \
+        {0x102b, 0x0520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G200}, \
+        {0x102b, 0x0521, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G200}, \
+        {0x102b, 0x0525, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G400}, \
+        {0x102b, 0x2527, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G550}, \
+        {0, 0, 0}
+
+#define mach64_PCI_IDS \
+        {0x1002, 0x4749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4744, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x474c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x474f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4752, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4753, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x474d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x474e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1002, 0x4c4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
+
+#define sisdrv_PCI_IDS \
+        {0x1039, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1039, 0x5300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1039, 0x6300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1039, 0x6330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \
+        {0x1039, 0x6351, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1039, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x18CA, 0x0040, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \
+        {0x18CA, 0x0042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \
+        {0, 0, 0}
+
+#define tdfx_PCI_IDS \
+        {0x121a, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x121a, 0x0004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x121a, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x121a, 0x0007, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x121a, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x121a, 0x000b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
+
+#define viadrv_PCI_IDS \
+        {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
+        {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1106, 0x3343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
+        {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
+        {0, 0, 0}
+
+#define i810_PCI_IDS \
+        {0x8086, 0x7121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x7123, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x1132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
+
+#define i830_PCI_IDS \
+        {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
+
+#define gamma_PCI_IDS \
+        {0x3d3d, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
+
+#define savage_PCI_IDS \
+        {0x5333, 0x8a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE3D}, \
+        {0x5333, 0x8a21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE3D}, \
+        {0x5333, 0x8a22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE4}, \
+        {0x5333, 0x8a23, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE4}, \
+        {0x5333, 0x8c10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
+        {0x5333, 0x8c11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
+        {0x5333, 0x8c12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
+        {0x5333, 0x8c13, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
+        {0x5333, 0x8c22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c24, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c2a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c2b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c2c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8c2f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
+        {0x5333, 0x8a25, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGE}, \
+        {0x5333, 0x8a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGE}, \
+        {0x5333, 0x8d01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_TWISTER}, \
+        {0x5333, 0x8d02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_TWISTER}, \
+        {0x5333, 0x8d03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGEDDR}, \
+        {0x5333, 0x8d04, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGEDDR}, \
+        {0, 0, 0}
+
+#define ffb_PCI_IDS \
+        {0, 0, 0}
+
+#define i915_PCI_IDS \
+        {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0, 0, 0}
diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h
new file mode 100644
index 000000000000..480037331e4e
--- /dev/null
+++ b/include/drm/drm_sarea.h
@@ -0,0 +1,84 @@
+/**
+ * \file drm_sarea.h
+ * \brief SAREA definitions
+ *
+ * \author Michel Dänzer <michel@daenzer.net>
+ */
+
+/*
+ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DRM_SAREA_H_
+#define _DRM_SAREA_H_
+
+#include "drm.h"
+
+/* SAREA area needs to be at least a page */
+#if defined(__alpha__)
+#define SAREA_MAX                       0x2000
+#elif defined(__ia64__)
+#define SAREA_MAX                       0x10000 /* 64kB */
+#else
+/* Intel 830M driver needs at least 8k SAREA */
+#define SAREA_MAX                       0x2000
+#endif
+
+/** Maximum number of drawables in the SAREA */
+#define SAREA_MAX_DRAWABLES             256
+
+#define SAREA_DRAWABLE_CLAIMED_ENTRY    0x80000000
+
+/** SAREA drawable */
+struct drm_sarea_drawable {
+        unsigned int stamp;
+        unsigned int flags;
+};
+
+/** SAREA frame */
+struct drm_sarea_frame {
+        unsigned int x;
+        unsigned int y;
+        unsigned int width;
+        unsigned int height;
+        unsigned int fullscreen;
+};
+
+/** SAREA */
+struct drm_sarea {
+    /** first thing is always the DRM locking structure */
+        struct drm_hw_lock lock;
+    /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
+        struct drm_hw_lock drawable_lock;
+        struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES];   /**< drawables */
+        struct drm_sarea_frame frame;   /**< frame */
+        drm_context_t dummy_context;
+};
+
+#ifndef __KERNEL__
+typedef struct drm_sarea_drawable drm_sarea_drawable_t;
+typedef struct drm_sarea_frame drm_sarea_frame_t;
+typedef struct drm_sarea drm_sarea_t;
+#endif
+
+#endif                          /* _DRM_SAREA_H_ */
diff --git a/include/drm/drm_sman.h b/include/drm/drm_sman.h
new file mode 100644
index 000000000000..08ecf83ad5d4
--- /dev/null
+++ b/include/drm/drm_sman.h
@@ -0,0 +1,176 @@
+/**************************************************************************
+ *
+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ **************************************************************************/
+/*
+ * Simple memory MANager interface that keeps track on allocate regions on a
+ * per "owner" basis. All regions associated with an "owner" can be released
+ * with a simple call. Typically if the "owner" exists. The owner is any
+ * "unsigned long" identifier. Can typically be a pointer to a file private
+ * struct or a context identifier.
+ *
+ * Authors:
+ * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
+ */
+
+#ifndef DRM_SMAN_H
+#define DRM_SMAN_H
+
+#include "drmP.h"
+#include "drm_hashtab.h"
+
+/*
+ * A class that is an abstration of a simple memory allocator.
+ * The sman implementation provides a default such allocator
+ * using the drm_mm.c implementation. But the user can replace it.
+ * See the SiS implementation, which may use the SiS FB kernel module
+ * for memory management.
+ */
+
+struct drm_sman_mm {
+        /* private info. If allocated, needs to be destroyed by the destroy
+           function */
+        void *private;
+
+        /* Allocate a memory block with given size and alignment.
+           Return an opaque reference to the memory block */
+
+        void *(*allocate) (void *private, unsigned long size,
+                           unsigned alignment);
+
+        /* Free a memory block. "ref" is the opaque reference that we got from
+           the "alloc" function */
+
+        void (*free) (void *private, void *ref);
+
+        /* Free all resources associated with this allocator */
+
+        void (*destroy) (void *private);
+
+        /* Return a memory offset from the opaque reference returned from the
+           "alloc" function */
+
+        unsigned long (*offset) (void *private, void *ref);
+};
+
+struct drm_memblock_item {
+        struct list_head owner_list;
+        struct drm_hash_item user_hash;
+        void *mm_info;
+        struct drm_sman_mm *mm;
+        struct drm_sman *sman;
+};
+
+struct drm_sman {
+        struct drm_sman_mm *mm;
+        int num_managers;
+        struct drm_open_hash owner_hash_tab;
+        struct drm_open_hash user_hash_tab;
+        struct list_head owner_items;
+};
+
+/*
+ * Take down a memory manager. This function should only be called after a
+ * successful init and after a call to drm_sman_cleanup.
+ */
+
+extern void drm_sman_takedown(struct drm_sman * sman);
+
+/*
+ * Allocate structures for a manager.
+ * num_managers are the number of memory pools to manage. (VRAM, AGP, ....)
+ * user_order is the log2 of the number of buckets in the user hash table.
+ *          set this to approximately log2 of the max number of memory regions
+ *          that will be allocated for _all_ pools together.
+ * owner_order is the log2 of the number of buckets in the owner hash table.
+ *          set this to approximately log2 of
+ *          the number of client file connections that will
+ *          be using the manager.
+ *
+ */
+
+extern int drm_sman_init(struct drm_sman * sman, unsigned int num_managers,
+                         unsigned int user_order, unsigned int owner_order);
+
+/*
+ * Initialize a drm_mm.c allocator. Should be called only once for each
+ * manager unless a customized allogator is used.
+ */
+
+extern int drm_sman_set_range(struct drm_sman * sman, unsigned int manager,
+                              unsigned long start, unsigned long size);
+
+/*
+ * Initialize a customized allocator for one of the managers.
+ * (See the SiS module). The object pointed to by "allocator" is copied,
+ * so it can be destroyed after this call.
+ */
+
+extern int drm_sman_set_manager(struct drm_sman * sman, unsigned int mananger,
+                                struct drm_sman_mm * allocator);
+
+/*
+ * Allocate a memory block. Aligment is not implemented yet.
+ */
+
+extern struct drm_memblock_item *drm_sman_alloc(struct drm_sman * sman,
+                                                unsigned int manager,
+                                                unsigned long size,
+                                                unsigned alignment,
+                                                unsigned long owner);
+/*
+ * Free a memory block identified by its user hash key.
+ */
+
+extern int drm_sman_free_key(struct drm_sman * sman, unsigned int key);
+
+/*
+ * returns 1 iff there are no stale memory blocks associated with this owner.
+ * Typically called to determine if we need to idle the hardware and call
+ * drm_sman_owner_cleanup. If there are no stale memory blocks, it removes all
+ * resources associated with owner.
+ */
+
+extern int drm_sman_owner_clean(struct drm_sman * sman, unsigned long owner);
+
+/*
+ * Frees all stale memory blocks associated with this owner. Note that this
+ * requires that the hardware is finished with all blocks, so the graphics engine
+ * should be idled before this call is made. This function also frees
+ * any resources associated with "owner" and should be called when owner
+ * is not going to be referenced anymore.
+ */
+
+extern void drm_sman_owner_cleanup(struct drm_sman * sman, unsigned long owner);
+
+/*
+ * Frees all stale memory blocks associated with the memory manager.
+ * See idling above.
+ */
+
+extern void drm_sman_cleanup(struct drm_sman * sman);
+
+#endif
diff --git a/include/drm/i810_drm.h b/include/drm/i810_drm.h
new file mode 100644
index 000000000000..7a10bb6f2c0f
--- /dev/null
+++ b/include/drm/i810_drm.h
@@ -0,0 +1,281 @@
+#ifndef _I810_DRM_H_
+#define _I810_DRM_H_
+
+/* WARNING: These defines must be the same as what the Xserver uses.
+ * if you change them, you must change the defines in the Xserver.
+ */
+
+#ifndef _I810_DEFINES_
+#define _I810_DEFINES_
+
+#define I810_DMA_BUF_ORDER              12
+#define I810_DMA_BUF_SZ                 (1<<I810_DMA_BUF_ORDER)
+#define I810_DMA_BUF_NR                 256
+#define I810_NR_SAREA_CLIPRECTS         8
+
+/* Each region is a minimum of 64k, and there are at most 64 of them.
+ */
+#define I810_NR_TEX_REGIONS 64
+#define I810_LOG_MIN_TEX_REGION_SIZE 16
+#endif
+
+#define I810_UPLOAD_TEX0IMAGE  0x1      /* handled clientside */
+#define I810_UPLOAD_TEX1IMAGE  0x2      /* handled clientside */
+#define I810_UPLOAD_CTX        0x4
+#define I810_UPLOAD_BUFFERS    0x8
+#define I810_UPLOAD_TEX0       0x10
+#define I810_UPLOAD_TEX1       0x20
+#define I810_UPLOAD_CLIPRECTS  0x40
+
+/* Indices into buf.Setup where various bits of state are mirrored per
+ * context and per buffer.  These can be fired at the card as a unit,
+ * or in a piecewise fashion as required.
+ */
+
+/* Destbuffer state
+ *    - backbuffer linear offset and pitch -- invarient in the current dri
+ *    - zbuffer linear offset and pitch -- also invarient
+ *    - drawing origin in back and depth buffers.
+ *
+ * Keep the depth/back buffer state here to accommodate private buffers
+ * in the future.
+ */
+#define I810_DESTREG_DI0  0     /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
+#define I810_DESTREG_DI1  1
+#define I810_DESTREG_DV0  2     /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
+#define I810_DESTREG_DV1  3
+#define I810_DESTREG_DR0  4     /* GFX_OP_DRAWRECT_INFO (4 dwords) */
+#define I810_DESTREG_DR1  5
+#define I810_DESTREG_DR2  6
+#define I810_DESTREG_DR3  7
+#define I810_DESTREG_DR4  8
+#define I810_DEST_SETUP_SIZE 10
+
+/* Context state
+ */
+#define I810_CTXREG_CF0   0     /* GFX_OP_COLOR_FACTOR */
+#define I810_CTXREG_CF1   1
+#define I810_CTXREG_ST0   2     /* GFX_OP_STIPPLE */
+#define I810_CTXREG_ST1   3
+#define I810_CTXREG_VF    4     /* GFX_OP_VERTEX_FMT */
+#define I810_CTXREG_MT    5     /* GFX_OP_MAP_TEXELS */
+#define I810_CTXREG_MC0   6     /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
+#define I810_CTXREG_MC1   7     /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
+#define I810_CTXREG_MC2   8     /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
+#define I810_CTXREG_MA0   9     /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
+#define I810_CTXREG_MA1   10    /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
+#define I810_CTXREG_MA2   11    /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
+#define I810_CTXREG_SDM   12    /* GFX_OP_SRC_DEST_MONO */
+#define I810_CTXREG_FOG   13    /* GFX_OP_FOG_COLOR */
+#define I810_CTXREG_B1    14    /* GFX_OP_BOOL_1 */
+#define I810_CTXREG_B2    15    /* GFX_OP_BOOL_2 */
+#define I810_CTXREG_LCS   16    /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
+#define I810_CTXREG_PV    17    /* GFX_OP_PV_RULE -- Invarient! */
+#define I810_CTXREG_ZA    18    /* GFX_OP_ZBIAS_ALPHAFUNC */
+#define I810_CTXREG_AA    19    /* GFX_OP_ANTIALIAS */
+#define I810_CTX_SETUP_SIZE 20
+
+/* Texture state (per tex unit)
+ */
+#define I810_TEXREG_MI0  0      /* GFX_OP_MAP_INFO (4 dwords) */
+#define I810_TEXREG_MI1  1
+#define I810_TEXREG_MI2  2
+#define I810_TEXREG_MI3  3
+#define I810_TEXREG_MF   4      /* GFX_OP_MAP_FILTER */
+#define I810_TEXREG_MLC  5      /* GFX_OP_MAP_LOD_CTL */
+#define I810_TEXREG_MLL  6      /* GFX_OP_MAP_LOD_LIMITS */
+#define I810_TEXREG_MCS  7      /* GFX_OP_MAP_COORD_SETS ??? */
+#define I810_TEX_SETUP_SIZE 8
+
+/* Flags for clear ioctl
+ */
+#define I810_FRONT   0x1
+#define I810_BACK    0x2
+#define I810_DEPTH   0x4
+
+typedef enum _drm_i810_init_func {
+        I810_INIT_DMA = 0x01,
+        I810_CLEANUP_DMA = 0x02,
+        I810_INIT_DMA_1_4 = 0x03
+} drm_i810_init_func_t;
+
+/* This is the init structure after v1.2 */
+typedef struct _drm_i810_init {
+        drm_i810_init_func_t func;
+        unsigned int mmio_offset;
+        unsigned int buffers_offset;
+        int sarea_priv_offset;
+        unsigned int ring_start;
+        unsigned int ring_end;
+        unsigned int ring_size;
+        unsigned int front_offset;
+        unsigned int back_offset;
+        unsigned int depth_offset;
+        unsigned int overlay_offset;
+        unsigned int overlay_physical;
+        unsigned int w;
+        unsigned int h;
+        unsigned int pitch;
+        unsigned int pitch_bits;
+} drm_i810_init_t;
+
+/* This is the init structure prior to v1.2 */
+typedef struct _drm_i810_pre12_init {
+        drm_i810_init_func_t func;
+        unsigned int mmio_offset;
+        unsigned int buffers_offset;
+        int sarea_priv_offset;
+        unsigned int ring_start;
+        unsigned int ring_end;
+        unsigned int ring_size;
+        unsigned int front_offset;
+        unsigned int back_offset;
+        unsigned int depth_offset;
+        unsigned int w;
+        unsigned int h;
+        unsigned int pitch;
+        unsigned int pitch_bits;
+} drm_i810_pre12_init_t;
+
+/* Warning: If you change the SAREA structure you must change the Xserver
+ * structure as well */
+
+typedef struct _drm_i810_tex_region {
+        unsigned char next, prev;       /* indices to form a circular LRU  */
+        unsigned char in_use;   /* owned by a client, or free? */
+        int age;                /* tracked by clients to update local LRU's */
+} drm_i810_tex_region_t;
+
+typedef struct _drm_i810_sarea {
+        unsigned int ContextState[I810_CTX_SETUP_SIZE];
+        unsigned int BufferState[I810_DEST_SETUP_SIZE];
+        unsigned int TexState[2][I810_TEX_SETUP_SIZE];
+        unsigned int dirty;
+
+        unsigned int nbox;
+        struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
+
+        /* Maintain an LRU of contiguous regions of texture space.  If
+         * you think you own a region of texture memory, and it has an
+         * age different to the one you set, then you are mistaken and
+         * it has been stolen by another client.  If global texAge
+         * hasn't changed, there is no need to walk the list.
+         *
+         * These regions can be used as a proxy for the fine-grained
+         * texture information of other clients - by maintaining them
+         * in the same lru which is used to age their own textures,
+         * clients have an approximate lru for the whole of global
+         * texture space, and can make informed decisions as to which
+         * areas to kick out.  There is no need to choose whether to
+         * kick out your own texture or someone else's - simply eject
+         * them all in LRU order.
+         */
+
+        drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
+        /* Last elt is sentinal */
+        int texAge;             /* last time texture was uploaded */
+        int last_enqueue;       /* last time a buffer was enqueued */
+        int last_dispatch;      /* age of the most recently dispatched buffer */
+        int last_quiescent;     /*  */
+        int ctxOwner;           /* last context to upload state */
+
+        int vertex_prim;
+
+        int pf_enabled;         /* is pageflipping allowed? */
+        int pf_active;
+        int pf_current_page;    /* which buffer is being displayed? */
+} drm_i810_sarea_t;
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmMga.h)
+ */
+
+/* i810 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_I810_INIT           0x00
+#define DRM_I810_VERTEX         0x01
+#define DRM_I810_CLEAR          0x02
+#define DRM_I810_FLUSH          0x03
+#define DRM_I810_GETAGE         0x04
+#define DRM_I810_GETBUF         0x05
+#define DRM_I810_SWAP           0x06
+#define DRM_I810_COPY           0x07
+#define DRM_I810_DOCOPY         0x08
+#define DRM_I810_OV0INFO        0x09
+#define DRM_I810_FSTATUS        0x0a
+#define DRM_I810_OV0FLIP        0x0b
+#define DRM_I810_MC             0x0c
+#define DRM_I810_RSTATUS        0x0d
+#define DRM_I810_FLIP           0x0e
+
+#define DRM_IOCTL_I810_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX           DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR            DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH            DRM_IO(  DRM_COMMAND_BASE + DRM_I810_FLUSH)
+#define DRM_IOCTL_I810_GETAGE           DRM_IO(  DRM_COMMAND_BASE + DRM_I810_GETAGE)
+#define DRM_IOCTL_I810_GETBUF           DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP             DRM_IO(  DRM_COMMAND_BASE + DRM_I810_SWAP)
+#define DRM_IOCTL_I810_COPY             DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY           DRM_IO(  DRM_COMMAND_BASE + DRM_I810_DOCOPY)
+#define DRM_IOCTL_I810_OV0INFO          DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
+#define DRM_IOCTL_I810_FSTATUS          DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
+#define DRM_IOCTL_I810_OV0FLIP          DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
+#define DRM_IOCTL_I810_MC               DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
+#define DRM_IOCTL_I810_RSTATUS          DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
+#define DRM_IOCTL_I810_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
+
+typedef struct _drm_i810_clear {
+        int clear_color;
+        int clear_depth;
+        int flags;
+} drm_i810_clear_t;
+
+/* These may be placeholders if we have more cliprects than
+ * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
+ * false, indicating that the buffer will be dispatched again with a
+ * new set of cliprects.
+ */
+typedef struct _drm_i810_vertex {
+        int idx;                /* buffer index */
+        int used;               /* nr bytes in use */
+        int discard;            /* client is finished with the buffer? */
+} drm_i810_vertex_t;
+
+typedef struct _drm_i810_copy_t {
+        int idx;                /* buffer index */
+        int used;               /* nr bytes in use */
+        void *address;          /* Address to copy from */
+} drm_i810_copy_t;
+
+#define PR_TRIANGLES         (0x0<<18)
+#define PR_TRISTRIP_0        (0x1<<18)
+#define PR_TRISTRIP_1        (0x2<<18)
+#define PR_TRIFAN            (0x3<<18)
+#define PR_POLYGON           (0x4<<18)
+#define PR_LINES             (0x5<<18)
+#define PR_LINESTRIP         (0x6<<18)
+#define PR_RECTS             (0x7<<18)
+#define PR_MASK              (0x7<<18)
+
+typedef struct drm_i810_dma {
+        void *virtual;
+        int request_idx;
+        int request_size;
+        int granted;
+} drm_i810_dma_t;
+
+typedef struct _drm_i810_overlay_t {
+        unsigned int offset;    /* Address of the Overlay Regs */
+        unsigned int physical;
+} drm_i810_overlay_t;
+
+typedef struct _drm_i810_mc {
+        int idx;                /* buffer index */
+        int used;               /* nr bytes in use */
+        int num_blocks;         /* number of GFXBlocks */
+        int *length;            /* List of lengths for GFXBlocks (FUTURE) */
+        unsigned int last_render;       /* Last Render Request */
+} drm_i810_mc_t;
+
+#endif                          /* _I810_DRM_H_ */
diff --git a/include/drm/i830_drm.h b/include/drm/i830_drm.h
new file mode 100644
index 000000000000..4b00d2dd4f68
--- /dev/null
+++ b/include/drm/i830_drm.h
@@ -0,0 +1,342 @@
+#ifndef _I830_DRM_H_
+#define _I830_DRM_H_
+
+/* WARNING: These defines must be the same as what the Xserver uses.
+ * if you change them, you must change the defines in the Xserver.
+ *
+ * KW: Actually, you can't ever change them because doing so would
+ * break backwards compatibility.
+ */
+
+#ifndef _I830_DEFINES_
+#define _I830_DEFINES_
+
+#define I830_DMA_BUF_ORDER              12
+#define I830_DMA_BUF_SZ                 (1<<I830_DMA_BUF_ORDER)
+#define I830_DMA_BUF_NR                 256
+#define I830_NR_SAREA_CLIPRECTS         8
+
+/* Each region is a minimum of 64k, and there are at most 64 of them.
+ */
+#define I830_NR_TEX_REGIONS 64
+#define I830_LOG_MIN_TEX_REGION_SIZE 16
+
+/* KW: These aren't correct but someone set them to two and then
+ * released the module.  Now we can't change them as doing so would
+ * break backwards compatibility.
+ */
+#define I830_TEXTURE_COUNT      2
+#define I830_TEXBLEND_COUNT     I830_TEXTURE_COUNT
+
+#define I830_TEXBLEND_SIZE      12      /* (4 args + op) * 2 + COLOR_FACTOR */
+
+#define I830_UPLOAD_CTX                 0x1
+#define I830_UPLOAD_BUFFERS             0x2
+#define I830_UPLOAD_CLIPRECTS           0x4
+#define I830_UPLOAD_TEX0_IMAGE          0x100   /* handled clientside */
+#define I830_UPLOAD_TEX0_CUBE           0x200   /* handled clientside */
+#define I830_UPLOAD_TEX1_IMAGE          0x400   /* handled clientside */
+#define I830_UPLOAD_TEX1_CUBE           0x800   /* handled clientside */
+#define I830_UPLOAD_TEX2_IMAGE          0x1000  /* handled clientside */
+#define I830_UPLOAD_TEX2_CUBE           0x2000  /* handled clientside */
+#define I830_UPLOAD_TEX3_IMAGE          0x4000  /* handled clientside */
+#define I830_UPLOAD_TEX3_CUBE           0x8000  /* handled clientside */
+#define I830_UPLOAD_TEX_N_IMAGE(n)      (0x100 << (n * 2))
+#define I830_UPLOAD_TEX_N_CUBE(n)       (0x200 << (n * 2))
+#define I830_UPLOAD_TEXIMAGE_MASK       0xff00
+#define I830_UPLOAD_TEX0                        0x10000
+#define I830_UPLOAD_TEX1                        0x20000
+#define I830_UPLOAD_TEX2                        0x40000
+#define I830_UPLOAD_TEX3                        0x80000
+#define I830_UPLOAD_TEX_N(n)            (0x10000 << (n))
+#define I830_UPLOAD_TEX_MASK            0xf0000
+#define I830_UPLOAD_TEXBLEND0           0x100000
+#define I830_UPLOAD_TEXBLEND1           0x200000
+#define I830_UPLOAD_TEXBLEND2           0x400000
+#define I830_UPLOAD_TEXBLEND3           0x800000
+#define I830_UPLOAD_TEXBLEND_N(n)       (0x100000 << (n))
+#define I830_UPLOAD_TEXBLEND_MASK       0xf00000
+#define I830_UPLOAD_TEX_PALETTE_N(n)    (0x1000000 << (n))
+#define I830_UPLOAD_TEX_PALETTE_SHARED  0x4000000
+#define I830_UPLOAD_STIPPLE             0x8000000
+
+/* Indices into buf.Setup where various bits of state are mirrored per
+ * context and per buffer.  These can be fired at the card as a unit,
+ * or in a piecewise fashion as required.
+ */
+
+/* Destbuffer state
+ *    - backbuffer linear offset and pitch -- invarient in the current dri
+ *    - zbuffer linear offset and pitch -- also invarient
+ *    - drawing origin in back and depth buffers.
+ *
+ * Keep the depth/back buffer state here to accommodate private buffers
+ * in the future.
+ */
+
+#define I830_DESTREG_CBUFADDR 0
+#define I830_DESTREG_DBUFADDR 1
+#define I830_DESTREG_DV0 2
+#define I830_DESTREG_DV1 3
+#define I830_DESTREG_SENABLE 4
+#define I830_DESTREG_SR0 5
+#define I830_DESTREG_SR1 6
+#define I830_DESTREG_SR2 7
+#define I830_DESTREG_DR0 8
+#define I830_DESTREG_DR1 9
+#define I830_DESTREG_DR2 10
+#define I830_DESTREG_DR3 11
+#define I830_DESTREG_DR4 12
+#define I830_DEST_SETUP_SIZE 13
+
+/* Context state
+ */
+#define I830_CTXREG_STATE1              0
+#define I830_CTXREG_STATE2              1
+#define I830_CTXREG_STATE3              2
+#define I830_CTXREG_STATE4              3
+#define I830_CTXREG_STATE5              4
+#define I830_CTXREG_IALPHAB             5
+#define I830_CTXREG_STENCILTST          6
+#define I830_CTXREG_ENABLES_1           7
+#define I830_CTXREG_ENABLES_2           8
+#define I830_CTXREG_AA                  9
+#define I830_CTXREG_FOGCOLOR            10
+#define I830_CTXREG_BLENDCOLR0          11
+#define I830_CTXREG_BLENDCOLR           12      /* Dword 1 of 2 dword command */
+#define I830_CTXREG_VF                  13
+#define I830_CTXREG_VF2                 14
+#define I830_CTXREG_MCSB0               15
+#define I830_CTXREG_MCSB1               16
+#define I830_CTX_SETUP_SIZE             17
+
+/* 1.3: Stipple state
+ */
+#define I830_STPREG_ST0 0
+#define I830_STPREG_ST1 1
+#define I830_STP_SETUP_SIZE 2
+
+/* Texture state (per tex unit)
+ */
+
+#define I830_TEXREG_MI0 0       /* GFX_OP_MAP_INFO (6 dwords) */
+#define I830_TEXREG_MI1 1
+#define I830_TEXREG_MI2 2
+#define I830_TEXREG_MI3 3
+#define I830_TEXREG_MI4 4
+#define I830_TEXREG_MI5 5
+#define I830_TEXREG_MF  6       /* GFX_OP_MAP_FILTER */
+#define I830_TEXREG_MLC 7       /* GFX_OP_MAP_LOD_CTL */
+#define I830_TEXREG_MLL 8       /* GFX_OP_MAP_LOD_LIMITS */
+#define I830_TEXREG_MCS 9       /* GFX_OP_MAP_COORD_SETS */
+#define I830_TEX_SETUP_SIZE 10
+
+#define I830_TEXREG_TM0LI      0        /* load immediate 2 texture map n */
+#define I830_TEXREG_TM0S0      1
+#define I830_TEXREG_TM0S1      2
+#define I830_TEXREG_TM0S2      3
+#define I830_TEXREG_TM0S3      4
+#define I830_TEXREG_TM0S4      5
+#define I830_TEXREG_NOP0       6        /* noop */
+#define I830_TEXREG_NOP1       7        /* noop */
+#define I830_TEXREG_NOP2       8        /* noop */
+#define __I830_TEXREG_MCS      9        /* GFX_OP_MAP_COORD_SETS -- shared */
+#define __I830_TEX_SETUP_SIZE   10
+
+#define I830_FRONT   0x1
+#define I830_BACK    0x2
+#define I830_DEPTH   0x4
+
+#endif                          /* _I830_DEFINES_ */
+
+typedef struct _drm_i830_init {
+        enum {
+                I830_INIT_DMA = 0x01,
+                I830_CLEANUP_DMA = 0x02
+        } func;
+        unsigned int mmio_offset;
+        unsigned int buffers_offset;
+        int sarea_priv_offset;
+        unsigned int ring_start;
+        unsigned int ring_end;
+        unsigned int ring_size;
+        unsigned int front_offset;
+        unsigned int back_offset;
+        unsigned int depth_offset;
+        unsigned int w;
+        unsigned int h;
+        unsigned int pitch;
+        unsigned int pitch_bits;
+        unsigned int back_pitch;
+        unsigned int depth_pitch;
+        unsigned int cpp;
+} drm_i830_init_t;
+
+/* Warning: If you change the SAREA structure you must change the Xserver
+ * structure as well */
+
+typedef struct _drm_i830_tex_region {
+        unsigned char next, prev;       /* indices to form a circular LRU  */
+        unsigned char in_use;   /* owned by a client, or free? */
+        int age;                /* tracked by clients to update local LRU's */
+} drm_i830_tex_region_t;
+
+typedef struct _drm_i830_sarea {
+        unsigned int ContextState[I830_CTX_SETUP_SIZE];
+        unsigned int BufferState[I830_DEST_SETUP_SIZE];
+        unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
+        unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
+        unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
+        unsigned int Palette[2][256];
+        unsigned int dirty;
+
+        unsigned int nbox;
+        struct drm_clip_rect boxes[I830_NR_SAREA_CLIPRECTS];
+
+        /* Maintain an LRU of contiguous regions of texture space.  If
+         * you think you own a region of texture memory, and it has an
+         * age different to the one you set, then you are mistaken and
+         * it has been stolen by another client.  If global texAge
+         * hasn't changed, there is no need to walk the list.
+         *
+         * These regions can be used as a proxy for the fine-grained
+         * texture information of other clients - by maintaining them
+         * in the same lru which is used to age their own textures,
+         * clients have an approximate lru for the whole of global
+         * texture space, and can make informed decisions as to which
+         * areas to kick out.  There is no need to choose whether to
+         * kick out your own texture or someone else's - simply eject
+         * them all in LRU order.
+         */
+
+        drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
+        /* Last elt is sentinal */
+        int texAge;             /* last time texture was uploaded */
+        int last_enqueue;       /* last time a buffer was enqueued */
+        int last_dispatch;      /* age of the most recently dispatched buffer */
+        int last_quiescent;     /*  */
+        int ctxOwner;           /* last context to upload state */
+
+        int vertex_prim;
+
+        int pf_enabled;         /* is pageflipping allowed? */
+        int pf_active;
+        int pf_current_page;    /* which buffer is being displayed? */
+
+        int perf_boxes;         /* performance boxes to be displayed */
+
+        /* Here's the state for texunits 2,3:
+         */
+        unsigned int TexState2[I830_TEX_SETUP_SIZE];
+        unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
+        unsigned int TexBlendStateWordsUsed2;
+
+        unsigned int TexState3[I830_TEX_SETUP_SIZE];
+        unsigned int TexBlendState3[I830_TEXBLEND_SIZE];
+        unsigned int TexBlendStateWordsUsed3;
+
+        unsigned int StippleState[I830_STP_SETUP_SIZE];
+} drm_i830_sarea_t;
+
+/* Flags for perf_boxes
+ */
+#define I830_BOX_RING_EMPTY    0x1      /* populated by kernel */
+#define I830_BOX_FLIP          0x2      /* populated by kernel */
+#define I830_BOX_WAIT          0x4      /* populated by kernel & client */
+#define I830_BOX_TEXTURE_LOAD  0x8      /* populated by kernel */
+#define I830_BOX_LOST_CONTEXT  0x10     /* populated by client */
+
+/* I830 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_I830_INIT   0x00
+#define DRM_I830_VERTEX 0x01
+#define DRM_I830_CLEAR  0x02
+#define DRM_I830_FLUSH  0x03
+#define DRM_I830_GETAGE 0x04
+#define DRM_I830_GETBUF 0x05
+#define DRM_I830_SWAP   0x06
+#define DRM_I830_COPY   0x07
+#define DRM_I830_DOCOPY 0x08
+#define DRM_I830_FLIP   0x09
+#define DRM_I830_IRQ_EMIT       0x0a
+#define DRM_I830_IRQ_WAIT       0x0b
+#define DRM_I830_GETPARAM       0x0c
+#define DRM_I830_SETPARAM       0x0d
+
+#define DRM_IOCTL_I830_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t)
+#define DRM_IOCTL_I830_VERTEX           DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t)
+#define DRM_IOCTL_I830_CLEAR            DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t)
+#define DRM_IOCTL_I830_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH)
+#define DRM_IOCTL_I830_GETAGE           DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE)
+#define DRM_IOCTL_I830_GETBUF           DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t)
+#define DRM_IOCTL_I830_SWAP             DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP)
+#define DRM_IOCTL_I830_COPY             DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t)
+#define DRM_IOCTL_I830_DOCOPY           DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY)
+#define DRM_IOCTL_I830_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP)
+#define DRM_IOCTL_I830_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t)
+#define DRM_IOCTL_I830_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t)
+#define DRM_IOCTL_I830_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t)
+#define DRM_IOCTL_I830_SETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t)
+
+typedef struct _drm_i830_clear {
+        int clear_color;
+        int clear_depth;
+        int flags;
+        unsigned int clear_colormask;
+        unsigned int clear_depthmask;
+} drm_i830_clear_t;
+
+/* These may be placeholders if we have more cliprects than
+ * I830_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
+ * false, indicating that the buffer will be dispatched again with a
+ * new set of cliprects.
+ */
+typedef struct _drm_i830_vertex {
+        int idx;                /* buffer index */
+        int used;               /* nr bytes in use */
+        int discard;            /* client is finished with the buffer? */
+} drm_i830_vertex_t;
+
+typedef struct _drm_i830_copy_t {
+        int idx;                /* buffer index */
+        int used;               /* nr bytes in use */
+        void __user *address;   /* Address to copy from */
+} drm_i830_copy_t;
+
+typedef struct drm_i830_dma {
+        void __user *virtual;
+        int request_idx;
+        int request_size;
+        int granted;
+} drm_i830_dma_t;
+
+/* 1.3: Userspace can request & wait on irq's:
+ */
+typedef struct drm_i830_irq_emit {
+        int __user *irq_seq;
+} drm_i830_irq_emit_t;
+
+typedef struct drm_i830_irq_wait {
+        int irq_seq;
+} drm_i830_irq_wait_t;
+
+/* 1.3: New ioctl to query kernel params:
+ */
+#define I830_PARAM_IRQ_ACTIVE            1
+
+typedef struct drm_i830_getparam {
+        int param;
+        int __user *value;
+} drm_i830_getparam_t;
+
+/* 1.3: New ioctl to set kernel params:
+ */
+#define I830_SETPARAM_USE_MI_BATCHBUFFER_START            1
+
+typedef struct drm_i830_setparam {
+        int param;
+        int value;
+} drm_i830_setparam_t;
+
+#endif                          /* _I830_DRM_H_ */
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
new file mode 100644
index 000000000000..05c66cf03a9e
--- /dev/null
+++ b/include/drm/i915_drm.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _I915_DRM_H_
+#define _I915_DRM_H_
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ */
+
+#include "drm.h"
+
+/* Each region is a minimum of 16k, and there are at most 255 of them.
+ */
+#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
+                                 * of chars for next/prev indices */
+#define I915_LOG_MIN_TEX_REGION_SIZE 14
+
+typedef struct _drm_i915_init {
+        enum {
+                I915_INIT_DMA = 0x01,
+                I915_CLEANUP_DMA = 0x02,
+                I915_RESUME_DMA = 0x03
+        } func;
+        unsigned int mmio_offset;
+        int sarea_priv_offset;
+        unsigned int ring_start;
+        unsigned int ring_end;
+        unsigned int ring_size;
+        unsigned int front_offset;
+        unsigned int back_offset;
+        unsigned int depth_offset;
+        unsigned int w;
+        unsigned int h;
+        unsigned int pitch;
+        unsigned int pitch_bits;
+        unsigned int back_pitch;
+        unsigned int depth_pitch;
+        unsigned int cpp;
+        unsigned int chipset;
+} drm_i915_init_t;
+
+typedef struct _drm_i915_sarea {
+        struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
+        int last_upload;        /* last time texture was uploaded */
+        int last_enqueue;       /* last time a buffer was enqueued */
+        int last_dispatch;      /* age of the most recently dispatched buffer */
+        int ctxOwner;           /* last context to upload state */
+        int texAge;
+        int pf_enabled;         /* is pageflipping allowed? */
+        int pf_active;
+        int pf_current_page;    /* which buffer is being displayed? */
+        int perf_boxes;         /* performance boxes to be displayed */
+        int width, height;      /* screen size in pixels */
+
+        drm_handle_t front_handle;
+        int front_offset;
+        int front_size;
+
+        drm_handle_t back_handle;
+        int back_offset;
+        int back_size;
+
+        drm_handle_t depth_handle;
+        int depth_offset;
+        int depth_size;
+
+        drm_handle_t tex_handle;
+        int tex_offset;
+        int tex_size;
+        int log_tex_granularity;
+        int pitch;
+        int rotation;           /* 0, 90, 180 or 270 */
+        int rotated_offset;
+        int rotated_size;
+        int rotated_pitch;
+        int virtualX, virtualY;
+
+        unsigned int front_tiled;
+        unsigned int back_tiled;
+        unsigned int depth_tiled;
+        unsigned int rotated_tiled;
+        unsigned int rotated2_tiled;
+
+        int pipeA_x;
+        int pipeA_y;
+        int pipeA_w;
+        int pipeA_h;
+        int pipeB_x;
+        int pipeB_y;
+        int pipeB_w;
+        int pipeB_h;
+} drm_i915_sarea_t;
+
+/* Flags for perf_boxes
+ */
+#define I915_BOX_RING_EMPTY    0x1
+#define I915_BOX_FLIP          0x2
+#define I915_BOX_WAIT          0x4
+#define I915_BOX_TEXTURE_LOAD  0x8
+#define I915_BOX_LOST_CONTEXT  0x10
+
+/* I915 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_I915_INIT           0x00
+#define DRM_I915_FLUSH          0x01
+#define DRM_I915_FLIP           0x02
+#define DRM_I915_BATCHBUFFER    0x03
+#define DRM_I915_IRQ_EMIT       0x04
+#define DRM_I915_IRQ_WAIT       0x05
+#define DRM_I915_GETPARAM       0x06
+#define DRM_I915_SETPARAM       0x07
+#define DRM_I915_ALLOC          0x08
+#define DRM_I915_FREE           0x09
+#define DRM_I915_INIT_HEAP      0x0a
+#define DRM_I915_CMDBUFFER      0x0b
+#define DRM_I915_DESTROY_HEAP   0x0c
+#define DRM_I915_SET_VBLANK_PIPE        0x0d
+#define DRM_I915_GET_VBLANK_PIPE        0x0e
+#define DRM_I915_VBLANK_SWAP    0x0f
+#define DRM_I915_HWS_ADDR       0x11
+
+#define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
+#define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
+#define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
+#define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
+#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
+#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
+#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
+#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
+#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
+#define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
+#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
+#define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
+#define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
+#define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
+#define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
+#define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
+
+/* Allow drivers to submit batchbuffers directly to hardware, relying
+ * on the security mechanisms provided by hardware.
+ */
+typedef struct _drm_i915_batchbuffer {
+        int start;              /* agp offset */
+        int used;               /* nr bytes in use */
+        int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
+        int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
+        int num_cliprects;      /* mulitpass with multiple cliprects? */
+        struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
+} drm_i915_batchbuffer_t;
+
+/* As above, but pass a pointer to userspace buffer which can be
+ * validated by the kernel prior to sending to hardware.
+ */
+typedef struct _drm_i915_cmdbuffer {
+        char __user *buf;       /* pointer to userspace command buffer */
+        int sz;                 /* nr bytes in buf */
+        int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
+        int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
+        int num_cliprects;      /* mulitpass with multiple cliprects? */
+        struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
+} drm_i915_cmdbuffer_t;
+
+/* Userspace can request & wait on irq's:
+ */
+typedef struct drm_i915_irq_emit {
+        int __user *irq_seq;
+} drm_i915_irq_emit_t;
+
+typedef struct drm_i915_irq_wait {
+        int irq_seq;
+} drm_i915_irq_wait_t;
+
+/* Ioctl to query kernel params:
+ */
+#define I915_PARAM_IRQ_ACTIVE            1
+#define I915_PARAM_ALLOW_BATCHBUFFER     2
+#define I915_PARAM_LAST_DISPATCH         3
+
+typedef struct drm_i915_getparam {
+        int param;
+        int __user *value;
+} drm_i915_getparam_t;
+
+/* Ioctl to set kernel params:
+ */
+#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
+#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
+#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
+
+typedef struct drm_i915_setparam {
+        int param;
+        int value;
+} drm_i915_setparam_t;
+
+/* A memory manager for regions of shared memory:
+ */
+#define I915_MEM_REGION_AGP 1
+
+typedef struct drm_i915_mem_alloc {
+        int region;
+        int alignment;
+        int size;
+        int __user *region_offset;      /* offset from start of fb or agp */
+} drm_i915_mem_alloc_t;
+
+typedef struct drm_i915_mem_free {
+        int region;
+        int region_offset;
+} drm_i915_mem_free_t;
+
+typedef struct drm_i915_mem_init_heap {
+        int region;
+        int size;
+        int start;
+} drm_i915_mem_init_heap_t;
+
+/* Allow memory manager to be torn down and re-initialized (eg on
+ * rotate):
+ */
+typedef struct drm_i915_mem_destroy_heap {
+        int region;
+} drm_i915_mem_destroy_heap_t;
+
+/* Allow X server to configure which pipes to monitor for vblank signals
+ */
+#define DRM_I915_VBLANK_PIPE_A  1
+#define DRM_I915_VBLANK_PIPE_B  2
+
+typedef struct drm_i915_vblank_pipe {
+        int pipe;
+} drm_i915_vblank_pipe_t;
+
+/* Schedule buffer swap at given vertical blank:
+ */
+typedef struct drm_i915_vblank_swap {
+        drm_drawable_t drawable;
+        enum drm_vblank_seq_type seqtype;
+        unsigned int sequence;
+} drm_i915_vblank_swap_t;
+
+typedef struct drm_i915_hws_addr {
+        uint64_t addr;
+} drm_i915_hws_addr_t;
+
+#endif                          /* _I915_DRM_H_ */
diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h
new file mode 100644
index 000000000000..944b50a5ff24
--- /dev/null
+++ b/include/drm/mga_drm.h
@@ -0,0 +1,417 @@
+/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
+ * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Jeff Hartmann <jhartmann@valinux.com>
+ *    Keith Whitwell <keith@tungstengraphics.com>
+ *
+ * Rewritten by:
+ *    Gareth Hughes <gareth@valinux.com>
+ */
+
+#ifndef __MGA_DRM_H__
+#define __MGA_DRM_H__
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (mga_sarea.h)
+ */
+
+#ifndef __MGA_SAREA_DEFINES__
+#define __MGA_SAREA_DEFINES__
+
+/* WARP pipe flags
+ */
+#define MGA_F                   0x1     /* fog */
+#define MGA_A                   0x2     /* alpha */
+#define MGA_S                   0x4     /* specular */
+#define MGA_T2                  0x8     /* multitexture */
+
+#define MGA_WARP_TGZ            0
+#define MGA_WARP_TGZF           (MGA_F)
+#define MGA_WARP_TGZA           (MGA_A)
+#define MGA_WARP_TGZAF          (MGA_F|MGA_A)
+#define MGA_WARP_TGZS           (MGA_S)
+#define MGA_WARP_TGZSF          (MGA_S|MGA_F)
+#define MGA_WARP_TGZSA          (MGA_S|MGA_A)
+#define MGA_WARP_TGZSAF         (MGA_S|MGA_F|MGA_A)
+#define MGA_WARP_T2GZ           (MGA_T2)
+#define MGA_WARP_T2GZF          (MGA_T2|MGA_F)
+#define MGA_WARP_T2GZA          (MGA_T2|MGA_A)
+#define MGA_WARP_T2GZAF         (MGA_T2|MGA_A|MGA_F)
+#define MGA_WARP_T2GZS          (MGA_T2|MGA_S)
+#define MGA_WARP_T2GZSF         (MGA_T2|MGA_S|MGA_F)
+#define MGA_WARP_T2GZSA         (MGA_T2|MGA_S|MGA_A)
+#define MGA_WARP_T2GZSAF        (MGA_T2|MGA_S|MGA_F|MGA_A)
+
+#define MGA_MAX_G200_PIPES      8       /* no multitex */
+#define MGA_MAX_G400_PIPES      16
+#define MGA_MAX_WARP_PIPES      MGA_MAX_G400_PIPES
+#define MGA_WARP_UCODE_SIZE     32768   /* in bytes */
+
+#define MGA_CARD_TYPE_G200      1
+#define MGA_CARD_TYPE_G400      2
+#define MGA_CARD_TYPE_G450      3       /* not currently used */
+#define MGA_CARD_TYPE_G550      4
+
+#define MGA_FRONT               0x1
+#define MGA_BACK                0x2
+#define MGA_DEPTH               0x4
+
+/* What needs to be changed for the current vertex dma buffer?
+ */
+#define MGA_UPLOAD_CONTEXT      0x1
+#define MGA_UPLOAD_TEX0         0x2
+#define MGA_UPLOAD_TEX1         0x4
+#define MGA_UPLOAD_PIPE         0x8
+#define MGA_UPLOAD_TEX0IMAGE    0x10    /* handled client-side */
+#define MGA_UPLOAD_TEX1IMAGE    0x20    /* handled client-side */
+#define MGA_UPLOAD_2D           0x40
+#define MGA_WAIT_AGE            0x80    /* handled client-side */
+#define MGA_UPLOAD_CLIPRECTS    0x100   /* handled client-side */
+#if 0
+#define MGA_DMA_FLUSH           0x200   /* set when someone gets the lock
+                                           quiescent */
+#endif
+
+/* 32 buffers of 64k each, total 2 meg.
+ */
+#define MGA_BUFFER_SIZE         (1 << 16)
+#define MGA_NUM_BUFFERS         128
+
+/* Keep these small for testing.
+ */
+#define MGA_NR_SAREA_CLIPRECTS  8
+
+/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
+ * regions, subject to a minimum region size of (1<<16) == 64k.
+ *
+ * Clients may subdivide regions internally, but when sharing between
+ * clients, the region size is the minimum granularity.
+ */
+
+#define MGA_CARD_HEAP                   0
+#define MGA_AGP_HEAP                    1
+#define MGA_NR_TEX_HEAPS                2
+#define MGA_NR_TEX_REGIONS              16
+#define MGA_LOG_MIN_TEX_REGION_SIZE     16
+
+#define  DRM_MGA_IDLE_RETRY          2048
+
+#endif                          /* __MGA_SAREA_DEFINES__ */
+
+/* Setup registers for 3D context
+ */
+typedef struct {
+        unsigned int dstorg;
+        unsigned int maccess;
+        unsigned int plnwt;
+        unsigned int dwgctl;
+        unsigned int alphactrl;
+        unsigned int fogcolor;
+        unsigned int wflag;
+        unsigned int tdualstage0;
+        unsigned int tdualstage1;
+        unsigned int fcol;
+        unsigned int stencil;
+        unsigned int stencilctl;
+} drm_mga_context_regs_t;
+
+/* Setup registers for 2D, X server
+ */
+typedef struct {
+        unsigned int pitch;
+} drm_mga_server_regs_t;
+
+/* Setup registers for each texture unit
+ */
+typedef struct {
+        unsigned int texctl;
+        unsigned int texctl2;
+        unsigned int texfilter;
+        unsigned int texbordercol;
+        unsigned int texorg;
+        unsigned int texwidth;
+        unsigned int texheight;
+        unsigned int texorg1;
+        unsigned int texorg2;
+        unsigned int texorg3;
+        unsigned int texorg4;
+} drm_mga_texture_regs_t;
+
+/* General aging mechanism
+ */
+typedef struct {
+        unsigned int head;      /* Position of head pointer          */
+        unsigned int wrap;      /* Primary DMA wrap count            */
+} drm_mga_age_t;
+
+typedef struct _drm_mga_sarea {
+        /* The channel for communication of state information to the kernel
+         * on firing a vertex dma buffer.
+         */
+        drm_mga_context_regs_t context_state;
+        drm_mga_server_regs_t server_state;
+        drm_mga_texture_regs_t tex_state[2];
+        unsigned int warp_pipe;
+        unsigned int dirty;
+        unsigned int vertsize;
+
+        /* The current cliprects, or a subset thereof.
+         */
+        struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
+        unsigned int nbox;
+
+        /* Information about the most recently used 3d drawable.  The
+         * client fills in the req_* fields, the server fills in the
+         * exported_ fields and puts the cliprects into boxes, above.
+         *
+         * The client clears the exported_drawable field before
+         * clobbering the boxes data.
+         */
+        unsigned int req_drawable;      /* the X drawable id */
+        unsigned int req_draw_buffer;   /* MGA_FRONT or MGA_BACK */
+
+        unsigned int exported_drawable;
+        unsigned int exported_index;
+        unsigned int exported_stamp;
+        unsigned int exported_buffers;
+        unsigned int exported_nfront;
+        unsigned int exported_nback;
+        int exported_back_x, exported_front_x, exported_w;
+        int exported_back_y, exported_front_y, exported_h;
+        struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
+
+        /* Counters for aging textures and for client-side throttling.
+         */
+        unsigned int status[4];
+        unsigned int last_wrap;
+
+        drm_mga_age_t last_frame;
+        unsigned int last_enqueue;      /* last time a buffer was enqueued */
+        unsigned int last_dispatch;     /* age of the most recently dispatched buffer */
+        unsigned int last_quiescent;    /*  */
+
+        /* LRU lists for texture memory in agp space and on the card.
+         */
+        struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
+        unsigned int texAge[MGA_NR_TEX_HEAPS];
+
+        /* Mechanism to validate card state.
+         */
+        int ctxOwner;
+} drm_mga_sarea_t;
+
+/* MGA specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_MGA_INIT     0x00
+#define DRM_MGA_FLUSH    0x01
+#define DRM_MGA_RESET    0x02
+#define DRM_MGA_SWAP     0x03
+#define DRM_MGA_CLEAR    0x04
+#define DRM_MGA_VERTEX   0x05
+#define DRM_MGA_INDICES  0x06
+#define DRM_MGA_ILOAD    0x07
+#define DRM_MGA_BLIT     0x08
+#define DRM_MGA_GETPARAM 0x09
+
+/* 3.2:
+ * ioctls for operating on fences.
+ */
+#define DRM_MGA_SET_FENCE      0x0a
+#define DRM_MGA_WAIT_FENCE     0x0b
+#define DRM_MGA_DMA_BOOTSTRAP  0x0c
+
+#define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
+#define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
+#define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
+#define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
+#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
+#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
+#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
+#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
+
+typedef struct _drm_mga_warp_index {
+        int installed;
+        unsigned long phys_addr;
+        int size;
+} drm_mga_warp_index_t;
+
+typedef struct drm_mga_init {
+        enum {
+                MGA_INIT_DMA = 0x01,
+                MGA_CLEANUP_DMA = 0x02
+        } func;
+
+        unsigned long sarea_priv_offset;
+
+        int chipset;
+        int sgram;
+
+        unsigned int maccess;
+
+        unsigned int fb_cpp;
+        unsigned int front_offset, front_pitch;
+        unsigned int back_offset, back_pitch;
+
+        unsigned int depth_cpp;
+        unsigned int depth_offset, depth_pitch;
+
+        unsigned int texture_offset[MGA_NR_TEX_HEAPS];
+        unsigned int texture_size[MGA_NR_TEX_HEAPS];
+
+        unsigned long fb_offset;
+        unsigned long mmio_offset;
+        unsigned long status_offset;
+        unsigned long warp_offset;
+        unsigned long primary_offset;
+        unsigned long buffers_offset;
+} drm_mga_init_t;
+
+typedef struct drm_mga_dma_bootstrap {
+        /**
+         * \name AGP texture region
+         *
+         * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
+         * be filled in with the actual AGP texture settings.
+         *
+         * \warning
+         * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
+         * is zero, it means that PCI memory (most likely through the use of
+         * an IOMMU) is being used for "AGP" textures.
+         */
+        /*@{ */
+        unsigned long texture_handle; /**< Handle used to map AGP textures. */
+        uint32_t texture_size;        /**< Size of the AGP texture region. */
+        /*@} */
+
+        /**
+         * Requested size of the primary DMA region.
+         *
+         * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
+         * filled in with the actual AGP mode.  If AGP was not available
+         */
+        uint32_t primary_size;
+
+        /**
+         * Requested number of secondary DMA buffers.
+         *
+         * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
+         * filled in with the actual number of secondary DMA buffers
+         * allocated.  Particularly when PCI DMA is used, this may be
+         * (subtantially) less than the number requested.
+         */
+        uint32_t secondary_bin_count;
+
+        /**
+         * Requested size of each secondary DMA buffer.
+         *
+         * While the kernel \b is free to reduce
+         * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
+         * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
+         */
+        uint32_t secondary_bin_size;
+
+        /**
+         * Bit-wise mask of AGPSTAT2_* values.  Currently only \c AGPSTAT2_1X,
+         * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported.  If this value is
+         * zero, it means that PCI DMA should be used, even if AGP is
+         * possible.
+         *
+         * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
+         * filled in with the actual AGP mode.  If AGP was not available
+         * (i.e., PCI DMA was used), this value will be zero.
+         */
+        uint32_t agp_mode;
+
+        /**
+         * Desired AGP GART size, measured in megabytes.
+         */
+        uint8_t agp_size;
+} drm_mga_dma_bootstrap_t;
+
+typedef struct drm_mga_clear {
+        unsigned int flags;
+        unsigned int clear_color;
+        unsigned int clear_depth;
+        unsigned int color_mask;
+        unsigned int depth_mask;
+} drm_mga_clear_t;
+
+typedef struct drm_mga_vertex {
+        int idx;                /* buffer to queue */
+        int used;               /* bytes in use */
+        int discard;            /* client finished with buffer?  */
+} drm_mga_vertex_t;
+
+typedef struct drm_mga_indices {
+        int idx;                /* buffer to queue */
+        unsigned int start;
+        unsigned int end;
+        int discard;            /* client finished with buffer?  */
+} drm_mga_indices_t;
+
+typedef struct drm_mga_iload {
+        int idx;
+        unsigned int dstorg;
+        unsigned int length;
+} drm_mga_iload_t;
+
+typedef struct _drm_mga_blit {
+        unsigned int planemask;
+        unsigned int srcorg;
+        unsigned int dstorg;
+        int src_pitch, dst_pitch;
+        int delta_sx, delta_sy;
+        int delta_dx, delta_dy;
+        int height, ydir;       /* flip image vertically */
+        int source_pitch, dest_pitch;
+} drm_mga_blit_t;
+
+/* 3.1: An ioctl to get parameters that aren't available to the 3d
+ * client any other way.
+ */
+#define MGA_PARAM_IRQ_NR            1
+
+/* 3.2: Query the actual card type.  The DDX only distinguishes between
+ * G200 chips and non-G200 chips, which it calls G400.  It turns out that
+ * there are some very sublte differences between the G4x0 chips and the G550
+ * chips.  Using this parameter query, a client-side driver can detect the
+ * difference between a G4x0 and a G550.
+ */
+#define MGA_PARAM_CARD_TYPE         2
+
+typedef struct drm_mga_getparam {
+        int param;
+        void __user *value;
+} drm_mga_getparam_t;
+
+#endif
diff --git a/include/drm/r128_drm.h b/include/drm/r128_drm.h
new file mode 100644
index 000000000000..8d8878b55f55
--- /dev/null
+++ b/include/drm/r128_drm.h
@@ -0,0 +1,326 @@
+/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
+ * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
+ */
+/*
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Gareth Hughes <gareth@valinux.com>
+ *    Kevin E. Martin <martin@valinux.com>
+ */
+
+#ifndef __R128_DRM_H__
+#define __R128_DRM_H__
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the X server file (r128_sarea.h)
+ */
+#ifndef __R128_SAREA_DEFINES__
+#define __R128_SAREA_DEFINES__
+
+/* What needs to be changed for the current vertex buffer?
+ */
+#define R128_UPLOAD_CONTEXT             0x001
+#define R128_UPLOAD_SETUP               0x002
+#define R128_UPLOAD_TEX0                0x004
+#define R128_UPLOAD_TEX1                0x008
+#define R128_UPLOAD_TEX0IMAGES          0x010
+#define R128_UPLOAD_TEX1IMAGES          0x020
+#define R128_UPLOAD_CORE                0x040
+#define R128_UPLOAD_MASKS               0x080
+#define R128_UPLOAD_WINDOW              0x100
+#define R128_UPLOAD_CLIPRECTS           0x200   /* handled client-side */
+#define R128_REQUIRE_QUIESCENCE         0x400
+#define R128_UPLOAD_ALL                 0x7ff
+
+#define R128_FRONT                      0x1
+#define R128_BACK                       0x2
+#define R128_DEPTH                      0x4
+
+/* Primitive types
+ */
+#define R128_POINTS                     0x1
+#define R128_LINES                      0x2
+#define R128_LINE_STRIP                 0x3
+#define R128_TRIANGLES                  0x4
+#define R128_TRIANGLE_FAN               0x5
+#define R128_TRIANGLE_STRIP             0x6
+
+/* Vertex/indirect buffer size
+ */
+#define R128_BUFFER_SIZE                16384
+
+/* Byte offsets for indirect buffer data
+ */
+#define R128_INDEX_PRIM_OFFSET          20
+#define R128_HOSTDATA_BLIT_OFFSET       32
+
+/* Keep these small for testing.
+ */
+#define R128_NR_SAREA_CLIPRECTS         12
+
+/* There are 2 heaps (local/AGP).  Each region within a heap is a
+ *  minimum of 64k, and there are at most 64 of them per heap.
+ */
+#define R128_LOCAL_TEX_HEAP             0
+#define R128_AGP_TEX_HEAP               1
+#define R128_NR_TEX_HEAPS               2
+#define R128_NR_TEX_REGIONS             64
+#define R128_LOG_TEX_GRANULARITY        16
+
+#define R128_NR_CONTEXT_REGS            12
+
+#define R128_MAX_TEXTURE_LEVELS         11
+#define R128_MAX_TEXTURE_UNITS          2
+
+#endif                          /* __R128_SAREA_DEFINES__ */
+
+typedef struct {
+        /* Context state - can be written in one large chunk */
+        unsigned int dst_pitch_offset_c;
+        unsigned int dp_gui_master_cntl_c;
+        unsigned int sc_top_left_c;
+        unsigned int sc_bottom_right_c;
+        unsigned int z_offset_c;
+        unsigned int z_pitch_c;
+        unsigned int z_sten_cntl_c;
+        unsigned int tex_cntl_c;
+        unsigned int misc_3d_state_cntl_reg;
+        unsigned int texture_clr_cmp_clr_c;
+        unsigned int texture_clr_cmp_msk_c;
+        unsigned int fog_color_c;
+
+        /* Texture state */
+        unsigned int tex_size_pitch_c;
+        unsigned int constant_color_c;
+
+        /* Setup state */
+        unsigned int pm4_vc_fpu_setup;
+        unsigned int setup_cntl;
+
+        /* Mask state */
+        unsigned int dp_write_mask;
+        unsigned int sten_ref_mask_c;
+        unsigned int plane_3d_mask_c;
+
+        /* Window state */
+        unsigned int window_xy_offset;
+
+        /* Core state */
+        unsigned int scale_3d_cntl;
+} drm_r128_context_regs_t;
+
+/* Setup registers for each texture unit
+ */
+typedef struct {
+        unsigned int tex_cntl;
+        unsigned int tex_combine_cntl;
+        unsigned int tex_size_pitch;
+        unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
+        unsigned int tex_border_color;
+} drm_r128_texture_regs_t;
+
+typedef struct drm_r128_sarea {
+        /* The channel for communication of state information to the kernel
+         * on firing a vertex buffer.
+         */
+        drm_r128_context_regs_t context_state;
+        drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
+        unsigned int dirty;
+        unsigned int vertsize;
+        unsigned int vc_format;
+
+        /* The current cliprects, or a subset thereof.
+         */
+        struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
+        unsigned int nbox;
+
+        /* Counters for client-side throttling of rendering clients.
+         */
+        unsigned int last_frame;
+        unsigned int last_dispatch;
+
+        struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
+        unsigned int tex_age[R128_NR_TEX_HEAPS];
+        int ctx_owner;
+        int pfAllowPageFlip;    /* number of 3d windows (0,1,2 or more) */
+        int pfCurrentPage;      /* which buffer is being displayed? */
+} drm_r128_sarea_t;
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmR128.h)
+ */
+
+/* Rage 128 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_R128_INIT       0x00
+#define DRM_R128_CCE_START  0x01
+#define DRM_R128_CCE_STOP   0x02
+#define DRM_R128_CCE_RESET  0x03
+#define DRM_R128_CCE_IDLE   0x04
+/* 0x05 not used */
+#define DRM_R128_RESET      0x06
+#define DRM_R128_SWAP       0x07
+#define DRM_R128_CLEAR      0x08
+#define DRM_R128_VERTEX     0x09
+#define DRM_R128_INDICES    0x0a
+#define DRM_R128_BLIT       0x0b
+#define DRM_R128_DEPTH      0x0c
+#define DRM_R128_STIPPLE    0x0d
+/* 0x0e not used */
+#define DRM_R128_INDIRECT   0x0f
+#define DRM_R128_FULLSCREEN 0x10
+#define DRM_R128_CLEAR2     0x11
+#define DRM_R128_GETPARAM   0x12
+#define DRM_R128_FLIP       0x13
+
+#define DRM_IOCTL_R128_INIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_START)
+#define DRM_IOCTL_R128_CCE_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
+#define DRM_IOCTL_R128_CCE_IDLE   DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
+/* 0x05 not used */
+#define DRM_IOCTL_R128_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_R128_RESET)
+#define DRM_IOCTL_R128_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_SWAP)
+#define DRM_IOCTL_R128_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
+/* 0x0e not used */
+#define DRM_IOCTL_R128_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
+#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
+#define DRM_IOCTL_R128_GETPARAM   DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
+#define DRM_IOCTL_R128_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_FLIP)
+
+typedef struct drm_r128_init {
+        enum {
+                R128_INIT_CCE = 0x01,
+                R128_CLEANUP_CCE = 0x02
+        } func;
+        unsigned long sarea_priv_offset;
+        int is_pci;
+        int cce_mode;
+        int cce_secure;
+        int ring_size;
+        int usec_timeout;
+
+        unsigned int fb_bpp;
+        unsigned int front_offset, front_pitch;
+        unsigned int back_offset, back_pitch;
+        unsigned int depth_bpp;
+        unsigned int depth_offset, depth_pitch;
+        unsigned int span_offset;
+
+        unsigned long fb_offset;
+        unsigned long mmio_offset;
+        unsigned long ring_offset;
+        unsigned long ring_rptr_offset;
+        unsigned long buffers_offset;
+        unsigned long agp_textures_offset;
+} drm_r128_init_t;
+
+typedef struct drm_r128_cce_stop {
+        int flush;
+        int idle;
+} drm_r128_cce_stop_t;
+
+typedef struct drm_r128_clear {
+        unsigned int flags;
+        unsigned int clear_color;
+        unsigned int clear_depth;
+        unsigned int color_mask;
+        unsigned int depth_mask;
+} drm_r128_clear_t;
+
+typedef struct drm_r128_vertex {
+        int prim;
+        int idx;                /* Index of vertex buffer */
+        int count;              /* Number of vertices in buffer */
+        int discard;            /* Client finished with buffer? */
+} drm_r128_vertex_t;
+
+typedef struct drm_r128_indices {
+        int prim;
+        int idx;
+        int start;
+        int end;
+        int discard;            /* Client finished with buffer? */
+} drm_r128_indices_t;
+
+typedef struct drm_r128_blit {
+        int idx;
+        int pitch;
+        int offset;
+        int format;
+        unsigned short x, y;
+        unsigned short width, height;
+} drm_r128_blit_t;
+
+typedef struct drm_r128_depth {
+        enum {
+                R128_WRITE_SPAN = 0x01,
+                R128_WRITE_PIXELS = 0x02,
+                R128_READ_SPAN = 0x03,
+                R128_READ_PIXELS = 0x04
+        } func;
+        int n;
+        int __user *x;
+        int __user *y;
+        unsigned int __user *buffer;
+        unsigned char __user *mask;
+} drm_r128_depth_t;
+
+typedef struct drm_r128_stipple {
+        unsigned int __user *mask;
+} drm_r128_stipple_t;
+
+typedef struct drm_r128_indirect {
+        int idx;
+        int start;
+        int end;
+        int discard;
+} drm_r128_indirect_t;
+
+typedef struct drm_r128_fullscreen {
+        enum {
+                R128_INIT_FULLSCREEN = 0x01,
+                R128_CLEANUP_FULLSCREEN = 0x02
+        } func;
+} drm_r128_fullscreen_t;
+
+/* 2.3: An ioctl to get parameters that aren't available to the 3d
+ * client any other way.
+ */
+#define R128_PARAM_IRQ_NR            1
+
+typedef struct drm_r128_getparam {
+        int param;
+        void __user *value;
+} drm_r128_getparam_t;
+
+#endif
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
new file mode 100644
index 000000000000..73ff51f12311
--- /dev/null
+++ b/include/drm/radeon_drm.h
@@ -0,0 +1,749 @@
+/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Kevin E. Martin <martin@valinux.com>
+ *    Gareth Hughes <gareth@valinux.com>
+ *    Keith Whitwell <keith@tungstengraphics.com>
+ */
+
+#ifndef __RADEON_DRM_H__
+#define __RADEON_DRM_H__
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the X server file (radeon_sarea.h)
+ */
+#ifndef __RADEON_SAREA_DEFINES__
+#define __RADEON_SAREA_DEFINES__
+
+/* Old style state flags, required for sarea interface (1.1 and 1.2
+ * clears) and 1.2 drm_vertex2 ioctl.
+ */
+#define RADEON_UPLOAD_CONTEXT           0x00000001
+#define RADEON_UPLOAD_VERTFMT           0x00000002
+#define RADEON_UPLOAD_LINE              0x00000004
+#define RADEON_UPLOAD_BUMPMAP           0x00000008
+#define RADEON_UPLOAD_MASKS             0x00000010
+#define RADEON_UPLOAD_VIEWPORT          0x00000020
+#define RADEON_UPLOAD_SETUP             0x00000040
+#define RADEON_UPLOAD_TCL               0x00000080
+#define RADEON_UPLOAD_MISC              0x00000100
+#define RADEON_UPLOAD_TEX0              0x00000200
+#define RADEON_UPLOAD_TEX1              0x00000400
+#define RADEON_UPLOAD_TEX2              0x00000800
+#define RADEON_UPLOAD_TEX0IMAGES        0x00001000
+#define RADEON_UPLOAD_TEX1IMAGES        0x00002000
+#define RADEON_UPLOAD_TEX2IMAGES        0x00004000
+#define RADEON_UPLOAD_CLIPRECTS         0x00008000      /* handled client-side */
+#define RADEON_REQUIRE_QUIESCENCE       0x00010000
+#define RADEON_UPLOAD_ZBIAS             0x00020000      /* version 1.2 and newer */
+#define RADEON_UPLOAD_ALL               0x003effff
+#define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
+
+/* New style per-packet identifiers for use in cmd_buffer ioctl with
+ * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
+ * state bits and the packet size:
+ */
+#define RADEON_EMIT_PP_MISC                         0   /* context/7 */
+#define RADEON_EMIT_PP_CNTL                         1   /* context/3 */
+#define RADEON_EMIT_RB3D_COLORPITCH                 2   /* context/1 */
+#define RADEON_EMIT_RE_LINE_PATTERN                 3   /* line/2 */
+#define RADEON_EMIT_SE_LINE_WIDTH                   4   /* line/1 */
+#define RADEON_EMIT_PP_LUM_MATRIX                   5   /* bumpmap/1 */
+#define RADEON_EMIT_PP_ROT_MATRIX_0                 6   /* bumpmap/2 */
+#define RADEON_EMIT_RB3D_STENCILREFMASK             7   /* masks/3 */
+#define RADEON_EMIT_SE_VPORT_XSCALE                 8   /* viewport/6 */
+#define RADEON_EMIT_SE_CNTL                         9   /* setup/2 */
+#define RADEON_EMIT_SE_CNTL_STATUS                  10  /* setup/1 */
+#define RADEON_EMIT_RE_MISC                         11  /* misc/1 */
+#define RADEON_EMIT_PP_TXFILTER_0                   12  /* tex0/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_0               13  /* tex0/1 */
+#define RADEON_EMIT_PP_TXFILTER_1                   14  /* tex1/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_1               15  /* tex1/1 */
+#define RADEON_EMIT_PP_TXFILTER_2                   16  /* tex2/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_2               17  /* tex2/1 */
+#define RADEON_EMIT_SE_ZBIAS_FACTOR                 18  /* zbias/2 */
+#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19  /* tcl/11 */
+#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20  /* material/17 */
+#define R200_EMIT_PP_TXCBLEND_0                     21  /* tex0/4 */
+#define R200_EMIT_PP_TXCBLEND_1                     22  /* tex1/4 */
+#define R200_EMIT_PP_TXCBLEND_2                     23  /* tex2/4 */
+#define R200_EMIT_PP_TXCBLEND_3                     24  /* tex3/4 */
+#define R200_EMIT_PP_TXCBLEND_4                     25  /* tex4/4 */
+#define R200_EMIT_PP_TXCBLEND_5                     26  /* tex5/4 */
+#define R200_EMIT_PP_TXCBLEND_6                     27  /* /4 */
+#define R200_EMIT_PP_TXCBLEND_7                     28  /* /4 */
+#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29  /* tcl/7 */
+#define R200_EMIT_TFACTOR_0                         30  /* tf/7 */
+#define R200_EMIT_VTX_FMT_0                         31  /* vtx/5 */
+#define R200_EMIT_VAP_CTL                           32  /* vap/1 */
+#define R200_EMIT_MATRIX_SELECT_0                   33  /* msl/5 */
+#define R200_EMIT_TEX_PROC_CTL_2                    34  /* tcg/5 */
+#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35  /* tcl/1 */
+#define R200_EMIT_PP_TXFILTER_0                     36  /* tex0/6 */
+#define R200_EMIT_PP_TXFILTER_1                     37  /* tex1/6 */
+#define R200_EMIT_PP_TXFILTER_2                     38  /* tex2/6 */
+#define R200_EMIT_PP_TXFILTER_3                     39  /* tex3/6 */
+#define R200_EMIT_PP_TXFILTER_4                     40  /* tex4/6 */
+#define R200_EMIT_PP_TXFILTER_5                     41  /* tex5/6 */
+#define R200_EMIT_PP_TXOFFSET_0                     42  /* tex0/1 */
+#define R200_EMIT_PP_TXOFFSET_1                     43  /* tex1/1 */
+#define R200_EMIT_PP_TXOFFSET_2                     44  /* tex2/1 */
+#define R200_EMIT_PP_TXOFFSET_3                     45  /* tex3/1 */
+#define R200_EMIT_PP_TXOFFSET_4                     46  /* tex4/1 */
+#define R200_EMIT_PP_TXOFFSET_5                     47  /* tex5/1 */
+#define R200_EMIT_VTE_CNTL                          48  /* vte/1 */
+#define R200_EMIT_OUTPUT_VTX_COMP_SEL               49  /* vtx/1 */
+#define R200_EMIT_PP_TAM_DEBUG3                     50  /* tam/1 */
+#define R200_EMIT_PP_CNTL_X                         51  /* cst/1 */
+#define R200_EMIT_RB3D_DEPTHXY_OFFSET               52  /* cst/1 */
+#define R200_EMIT_RE_AUX_SCISSOR_CNTL               53  /* cst/1 */
+#define R200_EMIT_RE_SCISSOR_TL_0                   54  /* cst/2 */
+#define R200_EMIT_RE_SCISSOR_TL_1                   55  /* cst/2 */
+#define R200_EMIT_RE_SCISSOR_TL_2                   56  /* cst/2 */
+#define R200_EMIT_SE_VAP_CNTL_STATUS                57  /* cst/1 */
+#define R200_EMIT_SE_VTX_STATE_CNTL                 58  /* cst/1 */
+#define R200_EMIT_RE_POINTSIZE                      59  /* cst/1 */
+#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60  /* cst/4 */
+#define R200_EMIT_PP_CUBIC_FACES_0                  61
+#define R200_EMIT_PP_CUBIC_OFFSETS_0                62
+#define R200_EMIT_PP_CUBIC_FACES_1                  63
+#define R200_EMIT_PP_CUBIC_OFFSETS_1                64
+#define R200_EMIT_PP_CUBIC_FACES_2                  65
+#define R200_EMIT_PP_CUBIC_OFFSETS_2                66
+#define R200_EMIT_PP_CUBIC_FACES_3                  67
+#define R200_EMIT_PP_CUBIC_OFFSETS_3                68
+#define R200_EMIT_PP_CUBIC_FACES_4                  69
+#define R200_EMIT_PP_CUBIC_OFFSETS_4                70
+#define R200_EMIT_PP_CUBIC_FACES_5                  71
+#define R200_EMIT_PP_CUBIC_OFFSETS_5                72
+#define RADEON_EMIT_PP_TEX_SIZE_0                   73
+#define RADEON_EMIT_PP_TEX_SIZE_1                   74
+#define RADEON_EMIT_PP_TEX_SIZE_2                   75
+#define R200_EMIT_RB3D_BLENDCOLOR                   76
+#define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
+#define RADEON_EMIT_PP_CUBIC_FACES_0                78
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
+#define RADEON_EMIT_PP_CUBIC_FACES_1                80
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
+#define RADEON_EMIT_PP_CUBIC_FACES_2                82
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
+#define R200_EMIT_PP_TRI_PERF_CNTL                  84
+#define R200_EMIT_PP_AFS_0                          85
+#define R200_EMIT_PP_AFS_1                          86
+#define R200_EMIT_ATF_TFACTOR                       87
+#define R200_EMIT_PP_TXCTLALL_0                     88
+#define R200_EMIT_PP_TXCTLALL_1                     89
+#define R200_EMIT_PP_TXCTLALL_2                     90
+#define R200_EMIT_PP_TXCTLALL_3                     91
+#define R200_EMIT_PP_TXCTLALL_4                     92
+#define R200_EMIT_PP_TXCTLALL_5                     93
+#define R200_EMIT_VAP_PVS_CNTL                      94
+#define RADEON_MAX_STATE_PACKETS                    95
+
+/* Commands understood by cmd_buffer ioctl.  More can be added but
+ * obviously these can't be removed or changed:
+ */
+#define RADEON_CMD_PACKET      1        /* emit one of the register packets above */
+#define RADEON_CMD_SCALARS     2        /* emit scalar data */
+#define RADEON_CMD_VECTORS     3        /* emit vector data */
+#define RADEON_CMD_DMA_DISCARD 4        /* discard current dma buf */
+#define RADEON_CMD_PACKET3     5        /* emit hw packet */
+#define RADEON_CMD_PACKET3_CLIP 6       /* emit hw packet wrapped in cliprects */
+#define RADEON_CMD_SCALARS2     7       /* r200 stopgap */
+#define RADEON_CMD_WAIT         8       /* emit hw wait commands -- note:
+                                         *  doesn't make the cpu wait, just
+                                         *  the graphics hardware */
+#define RADEON_CMD_VECLINEAR    9       /* another r200 stopgap */
+
+typedef union {
+        int i;
+        struct {
+                unsigned char cmd_type, pad0, pad1, pad2;
+        } header;
+        struct {
+                unsigned char cmd_type, packet_id, pad0, pad1;
+        } packet;
+        struct {
+                unsigned char cmd_type, offset, stride, count;
+        } scalars;
+        struct {
+                unsigned char cmd_type, offset, stride, count;
+        } vectors;
+        struct {
+                unsigned char cmd_type, addr_lo, addr_hi, count;
+        } veclinear;
+        struct {
+                unsigned char cmd_type, buf_idx, pad0, pad1;
+        } dma;
+        struct {
+                unsigned char cmd_type, flags, pad0, pad1;
+        } wait;
+} drm_radeon_cmd_header_t;
+
+#define RADEON_WAIT_2D  0x1
+#define RADEON_WAIT_3D  0x2
+
+/* Allowed parameters for R300_CMD_PACKET3
+ */
+#define R300_CMD_PACKET3_CLEAR          0
+#define R300_CMD_PACKET3_RAW            1
+
+/* Commands understood by cmd_buffer ioctl for R300.
+ * The interface has not been stabilized, so some of these may be removed
+ * and eventually reordered before stabilization.
+ */
+#define R300_CMD_PACKET0                1
+#define R300_CMD_VPU                    2       /* emit vertex program upload */
+#define R300_CMD_PACKET3                3       /* emit a packet3 */
+#define R300_CMD_END3D                  4       /* emit sequence ending 3d rendering */
+#define R300_CMD_CP_DELAY               5
+#define R300_CMD_DMA_DISCARD            6
+#define R300_CMD_WAIT                   7
+#       define R300_WAIT_2D             0x1
+#       define R300_WAIT_3D             0x2
+/* these two defines are DOING IT WRONG - however
+ * we have userspace which relies on using these.
+ * The wait interface is backwards compat new 
+ * code should use the NEW_WAIT defines below
+ * THESE ARE NOT BIT FIELDS
+ */
+#       define R300_WAIT_2D_CLEAN       0x3
+#       define R300_WAIT_3D_CLEAN       0x4
+
+#       define R300_NEW_WAIT_2D_3D      0x3
+#       define R300_NEW_WAIT_2D_2D_CLEAN        0x4
+#       define R300_NEW_WAIT_3D_3D_CLEAN        0x6
+#       define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN    0x8
+
+#define R300_CMD_SCRATCH                8
+#define R300_CMD_R500FP                 9
+
+typedef union {
+        unsigned int u;
+        struct {
+                unsigned char cmd_type, pad0, pad1, pad2;
+        } header;
+        struct {
+                unsigned char cmd_type, count, reglo, reghi;
+        } packet0;
+        struct {
+                unsigned char cmd_type, count, adrlo, adrhi;
+        } vpu;
+        struct {
+                unsigned char cmd_type, packet, pad0, pad1;
+        } packet3;
+        struct {
+                unsigned char cmd_type, packet;
+                unsigned short count;   /* amount of packet2 to emit */
+        } delay;
+        struct {
+                unsigned char cmd_type, buf_idx, pad0, pad1;
+        } dma;
+        struct {
+                unsigned char cmd_type, flags, pad0, pad1;
+        } wait;
+        struct {
+                unsigned char cmd_type, reg, n_bufs, flags;
+        } scratch;
+        struct {
+                unsigned char cmd_type, count, adrlo, adrhi_flags;
+        } r500fp;
+} drm_r300_cmd_header_t;
+
+#define RADEON_FRONT                    0x1
+#define RADEON_BACK                     0x2
+#define RADEON_DEPTH                    0x4
+#define RADEON_STENCIL                  0x8
+#define RADEON_CLEAR_FASTZ              0x80000000
+#define RADEON_USE_HIERZ                0x40000000
+#define RADEON_USE_COMP_ZBUF            0x20000000
+
+#define R500FP_CONSTANT_TYPE  (1 << 1)
+#define R500FP_CONSTANT_CLAMP (1 << 2)
+
+/* Primitive types
+ */
+#define RADEON_POINTS                   0x1
+#define RADEON_LINES                    0x2
+#define RADEON_LINE_STRIP               0x3
+#define RADEON_TRIANGLES                0x4
+#define RADEON_TRIANGLE_FAN             0x5
+#define RADEON_TRIANGLE_STRIP           0x6
+
+/* Vertex/indirect buffer size
+ */
+#define RADEON_BUFFER_SIZE              65536
+
+/* Byte offsets for indirect buffer data
+ */
+#define RADEON_INDEX_PRIM_OFFSET        20
+
+#define RADEON_SCRATCH_REG_OFFSET       32
+
+#define RADEON_NR_SAREA_CLIPRECTS       12
+
+/* There are 2 heaps (local/GART).  Each region within a heap is a
+ * minimum of 64k, and there are at most 64 of them per heap.
+ */
+#define RADEON_LOCAL_TEX_HEAP           0
+#define RADEON_GART_TEX_HEAP            1
+#define RADEON_NR_TEX_HEAPS             2
+#define RADEON_NR_TEX_REGIONS           64
+#define RADEON_LOG_TEX_GRANULARITY      16
+
+#define RADEON_MAX_TEXTURE_LEVELS       12
+#define RADEON_MAX_TEXTURE_UNITS        3
+
+#define RADEON_MAX_SURFACES             8
+
+/* Blits have strict offset rules.  All blit offset must be aligned on
+ * a 1K-byte boundary.
+ */
+#define RADEON_OFFSET_SHIFT             10
+#define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
+#define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
+
+#endif                          /* __RADEON_SAREA_DEFINES__ */
+
+typedef struct {
+        unsigned int red;
+        unsigned int green;
+        unsigned int blue;
+        unsigned int alpha;
+} radeon_color_regs_t;
+
+typedef struct {
+        /* Context state */
+        unsigned int pp_misc;   /* 0x1c14 */
+        unsigned int pp_fog_color;
+        unsigned int re_solid_color;
+        unsigned int rb3d_blendcntl;
+        unsigned int rb3d_depthoffset;
+        unsigned int rb3d_depthpitch;
+        unsigned int rb3d_zstencilcntl;
+
+        unsigned int pp_cntl;   /* 0x1c38 */
+        unsigned int rb3d_cntl;
+        unsigned int rb3d_coloroffset;
+        unsigned int re_width_height;
+        unsigned int rb3d_colorpitch;
+        unsigned int se_cntl;
+
+        /* Vertex format state */
+        unsigned int se_coord_fmt;      /* 0x1c50 */
+
+        /* Line state */
+        unsigned int re_line_pattern;   /* 0x1cd0 */
+        unsigned int re_line_state;
+
+        unsigned int se_line_width;     /* 0x1db8 */
+
+        /* Bumpmap state */
+        unsigned int pp_lum_matrix;     /* 0x1d00 */
+
+        unsigned int pp_rot_matrix_0;   /* 0x1d58 */
+        unsigned int pp_rot_matrix_1;
+
+        /* Mask state */
+        unsigned int rb3d_stencilrefmask;       /* 0x1d7c */
+        unsigned int rb3d_ropcntl;
+        unsigned int rb3d_planemask;
+
+        /* Viewport state */
+        unsigned int se_vport_xscale;   /* 0x1d98 */
+        unsigned int se_vport_xoffset;
+        unsigned int se_vport_yscale;
+        unsigned int se_vport_yoffset;
+        unsigned int se_vport_zscale;
+        unsigned int se_vport_zoffset;
+
+        /* Setup state */
+        unsigned int se_cntl_status;    /* 0x2140 */
+
+        /* Misc state */
+        unsigned int re_top_left;       /* 0x26c0 */
+        unsigned int re_misc;
+} drm_radeon_context_regs_t;
+
+typedef struct {
+        /* Zbias state */
+        unsigned int se_zbias_factor;   /* 0x1dac */
+        unsigned int se_zbias_constant;
+} drm_radeon_context2_regs_t;
+
+/* Setup registers for each texture unit
+ */
+typedef struct {
+        unsigned int pp_txfilter;
+        unsigned int pp_txformat;
+        unsigned int pp_txoffset;
+        unsigned int pp_txcblend;
+        unsigned int pp_txablend;
+        unsigned int pp_tfactor;
+        unsigned int pp_border_color;
+} drm_radeon_texture_regs_t;
+
+typedef struct {
+        unsigned int start;
+        unsigned int finish;
+        unsigned int prim:8;
+        unsigned int stateidx:8;
+        unsigned int numverts:16;       /* overloaded as offset/64 for elt prims */
+        unsigned int vc_format; /* vertex format */
+} drm_radeon_prim_t;
+
+typedef struct {
+        drm_radeon_context_regs_t context;
+        drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
+        drm_radeon_context2_regs_t context2;
+        unsigned int dirty;
+} drm_radeon_state_t;
+
+typedef struct {
+        /* The channel for communication of state information to the
+         * kernel on firing a vertex buffer with either of the
+         * obsoleted vertex/index ioctls.
+         */
+        drm_radeon_context_regs_t context_state;
+        drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
+        unsigned int dirty;
+        unsigned int vertsize;
+        unsigned int vc_format;
+
+        /* The current cliprects, or a subset thereof.
+         */
+        struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
+        unsigned int nbox;
+
+        /* Counters for client-side throttling of rendering clients.
+         */
+        unsigned int last_frame;
+        unsigned int last_dispatch;
+        unsigned int last_clear;
+
+        struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
+                                                       1];
+        unsigned int tex_age[RADEON_NR_TEX_HEAPS];
+        int ctx_owner;
+        int pfState;            /* number of 3d windows (0,1,2ormore) */
+        int pfCurrentPage;      /* which buffer is being displayed? */
+        int crtc2_base;         /* CRTC2 frame offset */
+        int tiling_enabled;     /* set by drm, read by 2d + 3d clients */
+} drm_radeon_sarea_t;
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmRadeon.h)
+ *
+ * KW: actually it's illegal to change any of this (backwards compatibility).
+ */
+
+/* Radeon specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_RADEON_CP_INIT    0x00
+#define DRM_RADEON_CP_START   0x01
+#define DRM_RADEON_CP_STOP    0x02
+#define DRM_RADEON_CP_RESET   0x03
+#define DRM_RADEON_CP_IDLE    0x04
+#define DRM_RADEON_RESET      0x05
+#define DRM_RADEON_FULLSCREEN 0x06
+#define DRM_RADEON_SWAP       0x07
+#define DRM_RADEON_CLEAR      0x08
+#define DRM_RADEON_VERTEX     0x09
+#define DRM_RADEON_INDICES    0x0A
+#define DRM_RADEON_NOT_USED
+#define DRM_RADEON_STIPPLE    0x0C
+#define DRM_RADEON_INDIRECT   0x0D
+#define DRM_RADEON_TEXTURE    0x0E
+#define DRM_RADEON_VERTEX2    0x0F
+#define DRM_RADEON_CMDBUF     0x10
+#define DRM_RADEON_GETPARAM   0x11
+#define DRM_RADEON_FLIP       0x12
+#define DRM_RADEON_ALLOC      0x13
+#define DRM_RADEON_FREE       0x14
+#define DRM_RADEON_INIT_HEAP  0x15
+#define DRM_RADEON_IRQ_EMIT   0x16
+#define DRM_RADEON_IRQ_WAIT   0x17
+#define DRM_RADEON_CP_RESUME  0x18
+#define DRM_RADEON_SETPARAM   0x19
+#define DRM_RADEON_SURF_ALLOC 0x1a
+#define DRM_RADEON_SURF_FREE  0x1b
+
+#define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
+#define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
+#define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
+#define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
+#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
+#define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
+#define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
+#define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
+#define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
+#define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
+#define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
+#define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
+#define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
+#define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
+#define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
+#define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
+#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
+#define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
+
+typedef struct drm_radeon_init {
+        enum {
+                RADEON_INIT_CP = 0x01,
+                RADEON_CLEANUP_CP = 0x02,
+                RADEON_INIT_R200_CP = 0x03,
+                RADEON_INIT_R300_CP = 0x04
+        } func;
+        unsigned long sarea_priv_offset;
+        int is_pci;
+        int cp_mode;
+        int gart_size;
+        int ring_size;
+        int usec_timeout;
+
+        unsigned int fb_bpp;
+        unsigned int front_offset, front_pitch;
+        unsigned int back_offset, back_pitch;
+        unsigned int depth_bpp;
+        unsigned int depth_offset, depth_pitch;
+
+        unsigned long fb_offset;
+        unsigned long mmio_offset;
+        unsigned long ring_offset;
+        unsigned long ring_rptr_offset;
+        unsigned long buffers_offset;
+        unsigned long gart_textures_offset;
+} drm_radeon_init_t;
+
+typedef struct drm_radeon_cp_stop {
+        int flush;
+        int idle;
+} drm_radeon_cp_stop_t;
+
+typedef struct drm_radeon_fullscreen {
+        enum {
+                RADEON_INIT_FULLSCREEN = 0x01,
+                RADEON_CLEANUP_FULLSCREEN = 0x02
+        } func;
+} drm_radeon_fullscreen_t;
+
+#define CLEAR_X1        0
+#define CLEAR_Y1        1
+#define CLEAR_X2        2
+#define CLEAR_Y2        3
+#define CLEAR_DEPTH     4
+
+typedef union drm_radeon_clear_rect {
+        float f[5];
+        unsigned int ui[5];
+} drm_radeon_clear_rect_t;
+
+typedef struct drm_radeon_clear {
+        unsigned int flags;
+        unsigned int clear_color;
+        unsigned int clear_depth;
+        unsigned int color_mask;
+        unsigned int depth_mask;        /* misnamed field:  should be stencil */
+        drm_radeon_clear_rect_t __user *depth_boxes;
+} drm_radeon_clear_t;
+
+typedef struct drm_radeon_vertex {
+        int prim;
+        int idx;                /* Index of vertex buffer */
+        int count;              /* Number of vertices in buffer */
+        int discard;            /* Client finished with buffer? */
+} drm_radeon_vertex_t;
+
+typedef struct drm_radeon_indices {
+        int prim;
+        int idx;
+        int start;
+        int end;
+        int discard;            /* Client finished with buffer? */
+} drm_radeon_indices_t;
+
+/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
+ *      - allows multiple primitives and state changes in a single ioctl
+ *      - supports driver change to emit native primitives
+ */
+typedef struct drm_radeon_vertex2 {
+        int idx;                /* Index of vertex buffer */
+        int discard;            /* Client finished with buffer? */
+        int nr_states;
+        drm_radeon_state_t __user *state;
+        int nr_prims;
+        drm_radeon_prim_t __user *prim;
+} drm_radeon_vertex2_t;
+
+/* v1.3 - obsoletes drm_radeon_vertex2
+ *      - allows arbitarily large cliprect list
+ *      - allows updating of tcl packet, vector and scalar state
+ *      - allows memory-efficient description of state updates
+ *      - allows state to be emitted without a primitive
+ *           (for clears, ctx switches)
+ *      - allows more than one dma buffer to be referenced per ioctl
+ *      - supports tcl driver
+ *      - may be extended in future versions with new cmd types, packets
+ */
+typedef struct drm_radeon_cmd_buffer {
+        int bufsz;
+        char __user *buf;
+        int nbox;
+        struct drm_clip_rect __user *boxes;
+} drm_radeon_cmd_buffer_t;
+
+typedef struct drm_radeon_tex_image {
+        unsigned int x, y;      /* Blit coordinates */
+        unsigned int width, height;
+        const void __user *data;
+} drm_radeon_tex_image_t;
+
+typedef struct drm_radeon_texture {
+        unsigned int offset;
+        int pitch;
+        int format;
+        int width;              /* Texture image coordinates */
+        int height;
+        drm_radeon_tex_image_t __user *image;
+} drm_radeon_texture_t;
+
+typedef struct drm_radeon_stipple {
+        unsigned int __user *mask;
+} drm_radeon_stipple_t;
+
+typedef struct drm_radeon_indirect {
+        int idx;
+        int start;
+        int end;
+        int discard;
+} drm_radeon_indirect_t;
+
+/* enum for card type parameters */
+#define RADEON_CARD_PCI 0
+#define RADEON_CARD_AGP 1
+#define RADEON_CARD_PCIE 2
+
+/* 1.3: An ioctl to get parameters that aren't available to the 3d
+ * client any other way.
+ */
+#define RADEON_PARAM_GART_BUFFER_OFFSET    1    /* card offset of 1st GART buffer */
+#define RADEON_PARAM_LAST_FRAME            2
+#define RADEON_PARAM_LAST_DISPATCH         3
+#define RADEON_PARAM_LAST_CLEAR            4
+/* Added with DRM version 1.6. */
+#define RADEON_PARAM_IRQ_NR                5
+#define RADEON_PARAM_GART_BASE             6    /* card offset of GART base */
+/* Added with DRM version 1.8. */
+#define RADEON_PARAM_REGISTER_HANDLE       7    /* for drmMap() */
+#define RADEON_PARAM_STATUS_HANDLE         8
+#define RADEON_PARAM_SAREA_HANDLE          9
+#define RADEON_PARAM_GART_TEX_HANDLE       10
+#define RADEON_PARAM_SCRATCH_OFFSET        11
+#define RADEON_PARAM_CARD_TYPE             12
+#define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
+#define RADEON_PARAM_FB_LOCATION           14   /* FB location */
+#define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
+
+typedef struct drm_radeon_getparam {
+        int param;
+        void __user *value;
+} drm_radeon_getparam_t;
+
+/* 1.6: Set up a memory manager for regions of shared memory:
+ */
+#define RADEON_MEM_REGION_GART 1
+#define RADEON_MEM_REGION_FB   2
+
+typedef struct drm_radeon_mem_alloc {
+        int region;
+        int alignment;
+        int size;
+        int __user *region_offset;      /* offset from start of fb or GART */
+} drm_radeon_mem_alloc_t;
+
+typedef struct drm_radeon_mem_free {
+        int region;
+        int region_offset;
+} drm_radeon_mem_free_t;
+
+typedef struct drm_radeon_mem_init_heap {
+        int region;
+        int size;
+        int start;
+} drm_radeon_mem_init_heap_t;
+
+/* 1.6: Userspace can request & wait on irq's:
+ */
+typedef struct drm_radeon_irq_emit {
+        int __user *irq_seq;
+} drm_radeon_irq_emit_t;
+
+typedef struct drm_radeon_irq_wait {
+        int irq_seq;
+} drm_radeon_irq_wait_t;
+
+/* 1.10: Clients tell the DRM where they think the framebuffer is located in
+ * the card's address space, via a new generic ioctl to set parameters
+ */
+
+typedef struct drm_radeon_setparam {
+        unsigned int param;
+        int64_t value;
+} drm_radeon_setparam_t;
+
+#define RADEON_SETPARAM_FB_LOCATION    1        /* determined framebuffer location */
+#define RADEON_SETPARAM_SWITCH_TILING  2        /* enable/disable color tiling */
+#define RADEON_SETPARAM_PCIGART_LOCATION 3      /* PCI Gart Location */
+#define RADEON_SETPARAM_NEW_MEMMAP 4            /* Use new memory map */
+#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
+#define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
+/* 1.14: Clients can allocate/free a surface
+ */
+typedef struct drm_radeon_surface_alloc {
+        unsigned int address;
+        unsigned int size;
+        unsigned int flags;
+} drm_radeon_surface_alloc_t;
+
+typedef struct drm_radeon_surface_free {
+        unsigned int address;
+} drm_radeon_surface_free_t;
+
+#define DRM_RADEON_VBLANK_CRTC1         1
+#define DRM_RADEON_VBLANK_CRTC2         2
+
+#endif
diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h
new file mode 100644
index 000000000000..8a576ef01821
--- /dev/null
+++ b/include/drm/savage_drm.h
@@ -0,0 +1,210 @@
+/* savage_drm.h -- Public header for the savage driver
+ *
+ * Copyright 2004  Felix Kuehling
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __SAVAGE_DRM_H__
+#define __SAVAGE_DRM_H__
+
+#ifndef __SAVAGE_SAREA_DEFINES__
+#define __SAVAGE_SAREA_DEFINES__
+
+/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
+ * regions, subject to a minimum region size of (1<<16) == 64k.
+ *
+ * Clients may subdivide regions internally, but when sharing between
+ * clients, the region size is the minimum granularity.
+ */
+
+#define SAVAGE_CARD_HEAP                0
+#define SAVAGE_AGP_HEAP                 1
+#define SAVAGE_NR_TEX_HEAPS             2
+#define SAVAGE_NR_TEX_REGIONS           16
+#define SAVAGE_LOG_MIN_TEX_REGION_SIZE  16
+
+#endif                          /* __SAVAGE_SAREA_DEFINES__ */
+
+typedef struct _drm_savage_sarea {
+        /* LRU lists for texture memory in agp space and on the card.
+         */
+        struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
+                                                      1];
+        unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
+
+        /* Mechanism to validate card state.
+         */
+        int ctxOwner;
+} drm_savage_sarea_t, *drm_savage_sarea_ptr;
+
+/* Savage-specific ioctls
+ */
+#define DRM_SAVAGE_BCI_INIT             0x00
+#define DRM_SAVAGE_BCI_CMDBUF           0x01
+#define DRM_SAVAGE_BCI_EVENT_EMIT       0x02
+#define DRM_SAVAGE_BCI_EVENT_WAIT       0x03
+
+#define DRM_IOCTL_SAVAGE_INIT           DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
+#define DRM_IOCTL_SAVAGE_CMDBUF         DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
+#define DRM_IOCTL_SAVAGE_EVENT_EMIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
+#define DRM_IOCTL_SAVAGE_EVENT_WAIT     DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
+
+#define SAVAGE_DMA_PCI  1
+#define SAVAGE_DMA_AGP  3
+typedef struct drm_savage_init {
+        enum {
+                SAVAGE_INIT_BCI = 1,
+                SAVAGE_CLEANUP_BCI = 2
+        } func;
+        unsigned int sarea_priv_offset;
+
+        /* some parameters */
+        unsigned int cob_size;
+        unsigned int bci_threshold_lo, bci_threshold_hi;
+        unsigned int dma_type;
+
+        /* frame buffer layout */
+        unsigned int fb_bpp;
+        unsigned int front_offset, front_pitch;
+        unsigned int back_offset, back_pitch;
+        unsigned int depth_bpp;
+        unsigned int depth_offset, depth_pitch;
+
+        /* local textures */
+        unsigned int texture_offset;
+        unsigned int texture_size;
+
+        /* physical locations of non-permanent maps */
+        unsigned long status_offset;
+        unsigned long buffers_offset;
+        unsigned long agp_textures_offset;
+        unsigned long cmd_dma_offset;
+} drm_savage_init_t;
+
+typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
+typedef struct drm_savage_cmdbuf {
+        /* command buffer in client's address space */
+        drm_savage_cmd_header_t __user *cmd_addr;
+        unsigned int size;      /* size of the command buffer in 64bit units */
+
+        unsigned int dma_idx;   /* DMA buffer index to use */
+        int discard;            /* discard DMA buffer when done */
+        /* vertex buffer in client's address space */
+        unsigned int __user *vb_addr;
+        unsigned int vb_size;   /* size of client vertex buffer in bytes */
+        unsigned int vb_stride; /* stride of vertices in 32bit words */
+        /* boxes in client's address space */
+        struct drm_clip_rect __user *box_addr;
+        unsigned int nbox;      /* number of clipping boxes */
+} drm_savage_cmdbuf_t;
+
+#define SAVAGE_WAIT_2D  0x1     /* wait for 2D idle before updating event tag */
+#define SAVAGE_WAIT_3D  0x2     /* wait for 3D idle before updating event tag */
+#define SAVAGE_WAIT_IRQ 0x4     /* emit or wait for IRQ, not implemented yet */
+typedef struct drm_savage_event {
+        unsigned int count;
+        unsigned int flags;
+} drm_savage_event_emit_t, drm_savage_event_wait_t;
+
+/* Commands for the cmdbuf ioctl
+ */
+#define SAVAGE_CMD_STATE        0       /* a range of state registers */
+#define SAVAGE_CMD_DMA_PRIM     1       /* vertices from DMA buffer */
+#define SAVAGE_CMD_VB_PRIM      2       /* vertices from client vertex buffer */
+#define SAVAGE_CMD_DMA_IDX      3       /* indexed vertices from DMA buffer */
+#define SAVAGE_CMD_VB_IDX       4       /* indexed vertices client vertex buffer */
+#define SAVAGE_CMD_CLEAR        5       /* clear buffers */
+#define SAVAGE_CMD_SWAP         6       /* swap buffers */
+
+/* Primitive types
+*/
+#define SAVAGE_PRIM_TRILIST     0       /* triangle list */
+#define SAVAGE_PRIM_TRISTRIP    1       /* triangle strip */
+#define SAVAGE_PRIM_TRIFAN      2       /* triangle fan */
+#define SAVAGE_PRIM_TRILIST_201 3       /* reorder verts for correct flat
+                                         * shading on s3d */
+
+/* Skip flags (vertex format)
+ */
+#define SAVAGE_SKIP_Z           0x01
+#define SAVAGE_SKIP_W           0x02
+#define SAVAGE_SKIP_C0          0x04
+#define SAVAGE_SKIP_C1          0x08
+#define SAVAGE_SKIP_S0          0x10
+#define SAVAGE_SKIP_T0          0x20
+#define SAVAGE_SKIP_ST0         0x30
+#define SAVAGE_SKIP_S1          0x40
+#define SAVAGE_SKIP_T1          0x80
+#define SAVAGE_SKIP_ST1         0xc0
+#define SAVAGE_SKIP_ALL_S3D     0x3f
+#define SAVAGE_SKIP_ALL_S4      0xff
+
+/* Buffer names for clear command
+ */
+#define SAVAGE_FRONT            0x1
+#define SAVAGE_BACK             0x2
+#define SAVAGE_DEPTH            0x4
+
+/* 64-bit command header
+ */
+union drm_savage_cmd_header {
+        struct {
+                unsigned char cmd;      /* command */
+                unsigned char pad0;
+                unsigned short pad1;
+                unsigned short pad2;
+                unsigned short pad3;
+        } cmd;                  /* generic */
+        struct {
+                unsigned char cmd;
+                unsigned char global;   /* need idle engine? */
+                unsigned short count;   /* number of consecutive registers */
+                unsigned short start;   /* first register */
+                unsigned short pad3;
+        } state;                /* SAVAGE_CMD_STATE */
+        struct {
+                unsigned char cmd;
+                unsigned char prim;     /* primitive type */
+                unsigned short skip;    /* vertex format (skip flags) */
+                unsigned short count;   /* number of vertices */
+                unsigned short start;   /* first vertex in DMA/vertex buffer */
+        } prim;                 /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
+        struct {
+                unsigned char cmd;
+                unsigned char prim;
+                unsigned short skip;
+                unsigned short count;   /* number of indices that follow */
+                unsigned short pad3;
+        } idx;                  /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
+        struct {
+                unsigned char cmd;
+                unsigned char pad0;
+                unsigned short pad1;
+                unsigned int flags;
+        } clear0;               /* SAVAGE_CMD_CLEAR */
+        struct {
+                unsigned int mask;
+                unsigned int value;
+        } clear1;               /* SAVAGE_CMD_CLEAR data */
+};
+
+#endif
diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h
new file mode 100644
index 000000000000..30f7b3827466
--- /dev/null
+++ b/include/drm/sis_drm.h
@@ -0,0 +1,67 @@
+/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */
+/*
+ * Copyright 2005 Eric Anholt
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef __SIS_DRM_H__
+#define __SIS_DRM_H__
+
+/* SiS specific ioctls */
+#define NOT_USED_0_3
+#define DRM_SIS_FB_ALLOC        0x04
+#define DRM_SIS_FB_FREE         0x05
+#define NOT_USED_6_12
+#define DRM_SIS_AGP_INIT        0x13
+#define DRM_SIS_AGP_ALLOC       0x14
+#define DRM_SIS_AGP_FREE        0x15
+#define DRM_SIS_FB_INIT         0x16
+
+#define DRM_IOCTL_SIS_FB_ALLOC          DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t)
+#define DRM_IOCTL_SIS_FB_FREE           DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t)
+#define DRM_IOCTL_SIS_AGP_INIT          DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t)
+#define DRM_IOCTL_SIS_AGP_ALLOC         DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t)
+#define DRM_IOCTL_SIS_AGP_FREE          DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t)
+#define DRM_IOCTL_SIS_FB_INIT           DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t)
+/*
+#define DRM_IOCTL_SIS_FLIP              DRM_IOW( 0x48, drm_sis_flip_t)
+#define DRM_IOCTL_SIS_FLIP_INIT         DRM_IO(  0x49)
+#define DRM_IOCTL_SIS_FLIP_FINAL        DRM_IO(  0x50)
+*/
+
+typedef struct {
+        int context;
+        unsigned int offset;
+        unsigned int size;
+        unsigned long free;
+} drm_sis_mem_t;
+
+typedef struct {
+        unsigned int offset, size;
+} drm_sis_agp_t;
+
+typedef struct {
+        unsigned int offset, size;
+} drm_sis_fb_t;
+
+#endif                          /* __SIS_DRM_H__ */
diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h
new file mode 100644
index 000000000000..a3b5c102b067
--- /dev/null
+++ b/include/drm/via_drm.h
@@ -0,0 +1,275 @@
+/*
+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _VIA_DRM_H_
+#define _VIA_DRM_H_
+
+/* WARNING: These defines must be the same as what the Xserver uses.
+ * if you change them, you must change the defines in the Xserver.
+ */
+
+#ifndef _VIA_DEFINES_
+#define _VIA_DEFINES_
+
+#ifndef __KERNEL__
+#include "via_drmclient.h"
+#endif
+
+#define VIA_NR_SAREA_CLIPRECTS          8
+#define VIA_NR_XVMC_PORTS               10
+#define VIA_NR_XVMC_LOCKS               5
+#define VIA_MAX_CACHELINE_SIZE          64
+#define XVMCLOCKPTR(saPriv,lockNo)                                      \
+        ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
+                                      (VIA_MAX_CACHELINE_SIZE - 1)) &   \
+                                     ~(VIA_MAX_CACHELINE_SIZE - 1)) +   \
+                                    VIA_MAX_CACHELINE_SIZE*(lockNo)))
+
+/* Each region is a minimum of 64k, and there are at most 64 of them.
+ */
+#define VIA_NR_TEX_REGIONS 64
+#define VIA_LOG_MIN_TEX_REGION_SIZE 16
+#endif
+
+#define VIA_UPLOAD_TEX0IMAGE  0x1       /* handled clientside */
+#define VIA_UPLOAD_TEX1IMAGE  0x2       /* handled clientside */
+#define VIA_UPLOAD_CTX        0x4
+#define VIA_UPLOAD_BUFFERS    0x8
+#define VIA_UPLOAD_TEX0       0x10
+#define VIA_UPLOAD_TEX1       0x20
+#define VIA_UPLOAD_CLIPRECTS  0x40
+#define VIA_UPLOAD_ALL        0xff
+
+/* VIA specific ioctls */
+#define DRM_VIA_ALLOCMEM        0x00
+#define DRM_VIA_FREEMEM         0x01
+#define DRM_VIA_AGP_INIT        0x02
+#define DRM_VIA_FB_INIT         0x03
+#define DRM_VIA_MAP_INIT        0x04
+#define DRM_VIA_DEC_FUTEX       0x05
+#define NOT_USED
+#define DRM_VIA_DMA_INIT        0x07
+#define DRM_VIA_CMDBUFFER       0x08
+#define DRM_VIA_FLUSH           0x09
+#define DRM_VIA_PCICMD          0x0a
+#define DRM_VIA_CMDBUF_SIZE     0x0b
+#define NOT_USED
+#define DRM_VIA_WAIT_IRQ        0x0d
+#define DRM_VIA_DMA_BLIT        0x0e
+#define DRM_VIA_BLIT_SYNC       0x0f
+
+#define DRM_IOCTL_VIA_ALLOCMEM    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
+#define DRM_IOCTL_VIA_FREEMEM     DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
+#define DRM_IOCTL_VIA_AGP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
+#define DRM_IOCTL_VIA_FB_INIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
+#define DRM_IOCTL_VIA_MAP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
+#define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
+#define DRM_IOCTL_VIA_DMA_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
+#define DRM_IOCTL_VIA_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
+#define DRM_IOCTL_VIA_FLUSH       DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
+#define DRM_IOCTL_VIA_PCICMD      DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
+#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
+                                            drm_via_cmdbuf_size_t)
+#define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
+#define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
+#define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
+
+/* Indices into buf.Setup where various bits of state are mirrored per
+ * context and per buffer.  These can be fired at the card as a unit,
+ * or in a piecewise fashion as required.
+ */
+
+#define VIA_TEX_SETUP_SIZE 8
+
+/* Flags for clear ioctl
+ */
+#define VIA_FRONT   0x1
+#define VIA_BACK    0x2
+#define VIA_DEPTH   0x4
+#define VIA_STENCIL 0x8
+#define VIA_MEM_VIDEO   0       /* matches drm constant */
+#define VIA_MEM_AGP     1       /* matches drm constant */
+#define VIA_MEM_SYSTEM  2
+#define VIA_MEM_MIXED   3
+#define VIA_MEM_UNKNOWN 4
+
+typedef struct {
+        uint32_t offset;
+        uint32_t size;
+} drm_via_agp_t;
+
+typedef struct {
+        uint32_t offset;
+        uint32_t size;
+} drm_via_fb_t;
+
+typedef struct {
+        uint32_t context;
+        uint32_t type;
+        uint32_t size;
+        unsigned long index;
+        unsigned long offset;
+} drm_via_mem_t;
+
+typedef struct _drm_via_init {
+        enum {
+                VIA_INIT_MAP = 0x01,
+                VIA_CLEANUP_MAP = 0x02
+        } func;
+
+        unsigned long sarea_priv_offset;
+        unsigned long fb_offset;
+        unsigned long mmio_offset;
+        unsigned long agpAddr;
+} drm_via_init_t;
+
+typedef struct _drm_via_futex {
+        enum {
+                VIA_FUTEX_WAIT = 0x00,
+                VIA_FUTEX_WAKE = 0X01
+        } func;
+        uint32_t ms;
+        uint32_t lock;
+        uint32_t val;
+} drm_via_futex_t;
+
+typedef struct _drm_via_dma_init {
+        enum {
+                VIA_INIT_DMA = 0x01,
+                VIA_CLEANUP_DMA = 0x02,
+                VIA_DMA_INITIALIZED = 0x03
+        } func;
+
+        unsigned long offset;
+        unsigned long size;
+        unsigned long reg_pause_addr;
+} drm_via_dma_init_t;
+
+typedef struct _drm_via_cmdbuffer {
+        char __user *buf;
+        unsigned long size;
+} drm_via_cmdbuffer_t;
+
+/* Warning: If you change the SAREA structure you must change the Xserver
+ * structure as well */
+
+typedef struct _drm_via_tex_region {
+        unsigned char next, prev;       /* indices to form a circular LRU  */
+        unsigned char inUse;    /* owned by a client, or free? */
+        int age;                /* tracked by clients to update local LRU's */
+} drm_via_tex_region_t;
+
+typedef struct _drm_via_sarea {
+        unsigned int dirty;
+        unsigned int nbox;
+        struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
+        drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
+        int texAge;             /* last time texture was uploaded */
+        int ctxOwner;           /* last context to upload state */
+        int vertexPrim;
+
+        /*
+         * Below is for XvMC.
+         * We want the lock integers alone on, and aligned to, a cache line.
+         * Therefore this somewhat strange construct.
+         */
+
+        char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
+
+        unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
+        unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
+        unsigned int XvMCCtxNoGrabbed;  /* Last context to hold decoder */
+
+        /* Used by the 3d driver only at this point, for pageflipping:
+         */
+        unsigned int pfCurrentOffset;
+} drm_via_sarea_t;
+
+typedef struct _drm_via_cmdbuf_size {
+        enum {
+                VIA_CMDBUF_SPACE = 0x01,
+                VIA_CMDBUF_LAG = 0x02
+        } func;
+        int wait;
+        uint32_t size;
+} drm_via_cmdbuf_size_t;
+
+typedef enum {
+        VIA_IRQ_ABSOLUTE = 0x0,
+        VIA_IRQ_RELATIVE = 0x1,
+        VIA_IRQ_SIGNAL = 0x10000000,
+        VIA_IRQ_FORCE_SEQUENCE = 0x20000000
+} via_irq_seq_type_t;
+
+#define VIA_IRQ_FLAGS_MASK 0xF0000000
+
+enum drm_via_irqs {
+        drm_via_irq_hqv0 = 0,
+        drm_via_irq_hqv1,
+        drm_via_irq_dma0_dd,
+        drm_via_irq_dma0_td,
+        drm_via_irq_dma1_dd,
+        drm_via_irq_dma1_td,
+        drm_via_irq_num
+};
+
+struct drm_via_wait_irq_request {
+        unsigned irq;
+        via_irq_seq_type_t type;
+        uint32_t sequence;
+        uint32_t signal;
+};
+
+typedef union drm_via_irqwait {
+        struct drm_via_wait_irq_request request;
+        struct drm_wait_vblank_reply reply;
+} drm_via_irqwait_t;
+
+typedef struct drm_via_blitsync {
+        uint32_t sync_handle;
+        unsigned engine;
+} drm_via_blitsync_t;
+
+/* - * Below,"flags" is currently unused but will be used for possible future
+ * extensions like kernel space bounce buffers for bad alignments and
+ * blit engine busy-wait polling for better latency in the absence of
+ * interrupts.
+ */
+
+typedef struct drm_via_dmablit {
+        uint32_t num_lines;
+        uint32_t line_length;
+
+        uint32_t fb_addr;
+        uint32_t fb_stride;
+
+        unsigned char *mem_addr;
+        uint32_t mem_stride;
+
+        uint32_t flags;
+        int to_fb;
+
+        drm_via_blitsync_t sync;
+} drm_via_dmablit_t;
+
+#endif                          /* _VIA_DRM_H_ */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 0601075d09a1..a17177639376 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -235,6 +235,9 @@ int acpi_check_region(resource_size_t start, resource_size_t n,
 int acpi_check_mem_region(resource_size_t start, resource_size_t n,
                       const char *name);
 
+#ifdef CONFIG_PM_SLEEP
+void __init acpi_old_suspend_ordering(void);
+#endif /* CONFIG_PM_SLEEP */
 #else   /* CONFIG_ACPI */
 
 static inline int early_acpi_boot_init(void)
diff --git a/include/linux/adb.h b/include/linux/adb.h
index 64d8878e1444..63bca502fa55 100644
--- a/include/linux/adb.h
+++ b/include/linux/adb.h
@@ -84,7 +84,6 @@ enum adb_message {
     ADB_MSG_PRE_RESET,  /* Called before resetting the bus */
     ADB_MSG_POST_RESET  /* Called after resetting the bus (re-do init & register) */
 };
-extern struct adb_driver *adb_controller;
 extern struct blocking_notifier_head adb_client_list;
 
 int adb_request(struct adb_request *req, void (*done)(struct adb_request *),
diff --git a/include/linux/bio.h b/include/linux/bio.h
index 61c15eaf3fb3..0933a14e6414 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -64,6 +64,7 @@ struct bio_vec {
 
 struct bio_set;
 struct bio;
+struct bio_integrity_payload;
 typedef void (bio_end_io_t) (struct bio *, int);
 typedef void (bio_destructor_t) (struct bio *);
 
@@ -112,6 +113,9 @@ struct bio {
         atomic_t                bi_cnt;         /* pin count */
 
         void                    *bi_private;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+        struct bio_integrity_payload *bi_integrity;  /* data integrity */
+#endif
 
         bio_destructor_t        *bi_destructor; /* destructor */
 };
@@ -271,6 +275,29 @@ static inline void *bio_data(struct bio *bio)
  */
 #define bio_get(bio)    atomic_inc(&(bio)->bi_cnt)
 
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+/*
+ * bio integrity payload
+ */
+struct bio_integrity_payload {
+        struct bio              *bip_bio;       /* parent bio */
+        struct bio_vec          *bip_vec;       /* integrity data vector */
+
+        sector_t                bip_sector;     /* virtual start sector */
+
+        void                    *bip_buf;       /* generated integrity data */
+        bio_end_io_t            *bip_end_io;    /* saved I/O completion fn */
+
+        int                     bip_error;      /* saved I/O error */
+        unsigned int            bip_size;
+
+        unsigned short          bip_pool;       /* pool the ivec came from */
+        unsigned short          bip_vcnt;       /* # of integrity bio_vecs */
+        unsigned short          bip_idx;        /* current bip_vec index */
+
+        struct work_struct      bip_work;       /* I/O completion */
+};
+#endif /* CONFIG_BLK_DEV_INTEGRITY */
 
 /*
  * A bio_pair is used when we need to split a bio.
@@ -283,10 +310,14 @@ static inline void *bio_data(struct bio *bio)
  *   in bio2.bi_private
  */
 struct bio_pair {
-        struct bio      bio1, bio2;
-        struct bio_vec  bv1, bv2;
-        atomic_t        cnt;
-        int             error;
+        struct bio                      bio1, bio2;
+        struct bio_vec                  bv1, bv2;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+        struct bio_integrity_payload    bip1, bip2;
+        struct bio_vec                  iv1, iv2;
+#endif
+        atomic_t                        cnt;
+        int                             error;
 };
 extern struct bio_pair *bio_split(struct bio *bi, mempool_t *pool,
                                   int first_sectors);
@@ -333,6 +364,39 @@ extern struct bio *bio_copy_user_iov(struct request_queue *, struct sg_iovec *,
                                      int, int);
 extern int bio_uncopy_user(struct bio *);
 void zero_fill_bio(struct bio *bio);
+extern struct bio_vec *bvec_alloc_bs(gfp_t, int, unsigned long *, struct bio_set *);
+extern unsigned int bvec_nr_vecs(unsigned short idx);
+
+/*
+ * bio_set is used to allow other portions of the IO system to
+ * allocate their own private memory pools for bio and iovec structures.
+ * These memory pools in turn all allocate from the bio_slab
+ * and the bvec_slabs[].
+ */
+#define BIO_POOL_SIZE 2
+#define BIOVEC_NR_POOLS 6
+
+struct bio_set {
+        mempool_t *bio_pool;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+        mempool_t *bio_integrity_pool;
+#endif
+        mempool_t *bvec_pools[BIOVEC_NR_POOLS];
+};
+
+struct biovec_slab {
+        int nr_vecs;
+        char *name;
+        struct kmem_cache *slab;
+};
+
+extern struct bio_set *fs_bio_set;
+
+/*
+ * a small number of entries is fine, not going to be performance critical.
+ * basically we just need to survive
+ */
+#define BIO_SPLIT_ENTRIES 2
 
 #ifdef CONFIG_HIGHMEM
 /*
@@ -381,5 +445,63 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx,
         __bio_kmap_irq((bio), (bio)->bi_idx, (flags))
 #define bio_kunmap_irq(buf,flags)       __bio_kunmap_irq(buf, flags)
 
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+
+#define bip_vec_idx(bip, idx)   (&(bip->bip_vec[(idx)]))
+#define bip_vec(bip)            bip_vec_idx(bip, 0)
+
+#define __bip_for_each_vec(bvl, bip, i, start_idx)                      \
+        for (bvl = bip_vec_idx((bip), (start_idx)), i = (start_idx);    \
+             i < (bip)->bip_vcnt;                                       \
+             bvl++, i++)
+
+#define bip_for_each_vec(bvl, bip, i)                                   \
+        __bip_for_each_vec(bvl, bip, i, (bip)->bip_idx)
+
+static inline int bio_integrity(struct bio *bio)
+{
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+        return bio->bi_integrity != NULL;
+#else
+        return 0;
+#endif
+}
+
+extern struct bio_integrity_payload *bio_integrity_alloc_bioset(struct bio *, gfp_t, unsigned int, struct bio_set *);
+extern struct bio_integrity_payload *bio_integrity_alloc(struct bio *, gfp_t, unsigned int);
+extern void bio_integrity_free(struct bio *, struct bio_set *);
+extern int bio_integrity_add_page(struct bio *, struct page *, unsigned int, unsigned int);
+extern int bio_integrity_enabled(struct bio *bio);
+extern int bio_integrity_set_tag(struct bio *, void *, unsigned int);
+extern int bio_integrity_get_tag(struct bio *, void *, unsigned int);
+extern int bio_integrity_prep(struct bio *);
+extern void bio_integrity_endio(struct bio *, int);
+extern void bio_integrity_advance(struct bio *, unsigned int);
+extern void bio_integrity_trim(struct bio *, unsigned int, unsigned int);
+extern void bio_integrity_split(struct bio *, struct bio_pair *, int);
+extern int bio_integrity_clone(struct bio *, struct bio *, struct bio_set *);
+extern int bioset_integrity_create(struct bio_set *, int);
+extern void bioset_integrity_free(struct bio_set *);
+extern void bio_integrity_init_slab(void);
+
+#else /* CONFIG_BLK_DEV_INTEGRITY */
+
+#define bio_integrity(a)                (0)
+#define bioset_integrity_create(a, b)   (0)
+#define bio_integrity_prep(a)           (0)
+#define bio_integrity_enabled(a)        (0)
+#define bio_integrity_clone(a, b, c)    (0)
+#define bioset_integrity_free(a)        do { } while (0)
+#define bio_integrity_free(a, b)        do { } while (0)
+#define bio_integrity_endio(a, b)       do { } while (0)
+#define bio_integrity_advance(a, b)     do { } while (0)
+#define bio_integrity_trim(a, b, c)     do { } while (0)
+#define bio_integrity_split(a, b, c)    do { } while (0)
+#define bio_integrity_set_tag(a, b, c)  do { } while (0)
+#define bio_integrity_get_tag(a, b, c)  do { } while (0)
+#define bio_integrity_init_slab(a)      do { } while (0)
+
+#endif /* CONFIG_BLK_DEV_INTEGRITY */
+
 #endif /* CONFIG_BLOCK */
 #endif /* __LINUX_BIO_H */
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index d2a1b71e93c3..88d68081a0f1 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -23,7 +23,6 @@
 struct scsi_ioctl_command;
 
 struct request_queue;
-typedef struct request_queue request_queue_t __deprecated;
 struct elevator_queue;
 typedef struct elevator_queue elevator_t;
 struct request_pm_state;
@@ -34,12 +33,6 @@ struct sg_io_hdr;
 #define BLKDEV_MIN_RQ   4
 #define BLKDEV_MAX_RQ   128     /* Default maximum */
 
-int put_io_context(struct io_context *ioc);
-void exit_io_context(void);
-struct io_context *get_io_context(gfp_t gfp_flags, int node);
-struct io_context *alloc_io_context(gfp_t gfp_flags, int node);
-void copy_io_context(struct io_context **pdst, struct io_context **psrc);
-
 struct request;
 typedef void (rq_end_io_fn)(struct request *, int);
 
@@ -113,6 +106,7 @@ enum rq_flag_bits {
         __REQ_ALLOCED,          /* request came from our alloc pool */
         __REQ_RW_META,          /* metadata io request */
         __REQ_COPY_USER,        /* contains copies of user pages */
+        __REQ_INTEGRITY,        /* integrity metadata has been remapped */
         __REQ_NR_BITS,          /* stops here */
 };
 
@@ -135,6 +129,7 @@ enum rq_flag_bits {
 #define REQ_ALLOCED     (1 << __REQ_ALLOCED)
 #define REQ_RW_META     (1 << __REQ_RW_META)
 #define REQ_COPY_USER   (1 << __REQ_COPY_USER)
+#define REQ_INTEGRITY   (1 << __REQ_INTEGRITY)
 
 #define BLK_MAX_CDB     16
 
@@ -259,7 +254,14 @@ typedef int (prep_rq_fn) (struct request_queue *, struct request *);
 typedef void (unplug_fn) (struct request_queue *);
 
 struct bio_vec;
-typedef int (merge_bvec_fn) (struct request_queue *, struct bio *, struct bio_vec *);
+struct bvec_merge_data {
+        struct block_device *bi_bdev;
+        sector_t bi_sector;
+        unsigned bi_size;
+        unsigned long bi_rw;
+};
+typedef int (merge_bvec_fn) (struct request_queue *, struct bvec_merge_data *,
+                             struct bio_vec *);
 typedef void (prepare_flush_fn) (struct request_queue *, struct request *);
 typedef void (softirq_done_fn)(struct request *);
 typedef int (dma_drain_needed_fn)(struct request *);
@@ -426,6 +428,32 @@ static inline void queue_flag_set_unlocked(unsigned int flag,
         __set_bit(flag, &q->queue_flags);
 }
 
+static inline int queue_flag_test_and_clear(unsigned int flag,
+                                            struct request_queue *q)
+{
+        WARN_ON_ONCE(!queue_is_locked(q));
+
+        if (test_bit(flag, &q->queue_flags)) {
+                __clear_bit(flag, &q->queue_flags);
+                return 1;
+        }
+
+        return 0;
+}
+
+static inline int queue_flag_test_and_set(unsigned int flag,
+                                          struct request_queue *q)
+{
+        WARN_ON_ONCE(!queue_is_locked(q));
+
+        if (!test_bit(flag, &q->queue_flags)) {
+                __set_bit(flag, &q->queue_flags);
+                return 0;
+        }
+
+        return 1;
+}
+
 static inline void queue_flag_set(unsigned int flag, struct request_queue *q)
 {
         WARN_ON_ONCE(!queue_is_locked(q));
@@ -623,7 +651,6 @@ extern void generic_make_request(struct bio *bio);
 extern void blk_rq_init(struct request_queue *q, struct request *rq);
 extern void blk_put_request(struct request *);
 extern void __blk_put_request(struct request_queue *, struct request *);
-extern void blk_end_sync_rq(struct request *rq, int error);
 extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
 extern void blk_insert_request(struct request_queue *, struct request *, int, void *);
 extern void blk_requeue_request(struct request_queue *, struct request *);
@@ -676,7 +703,6 @@ extern int blk_execute_rq(struct request_queue *, struct gendisk *,
                           struct request *, int);
 extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *,
                                   struct request *, int, rq_end_io_fn *);
-extern int blk_verify_command(unsigned char *, int);
 extern void blk_unplug(struct request_queue *q);
 
 static inline struct request_queue *bdev_get_queue(struct block_device *bdev)
@@ -749,6 +775,7 @@ extern void blk_queue_max_segment_size(struct request_queue *, unsigned int);
 extern void blk_queue_hardsect_size(struct request_queue *, unsigned short);
 extern void blk_queue_stack_limits(struct request_queue *t, struct request_queue *b);
 extern void blk_queue_dma_pad(struct request_queue *, unsigned int);
+extern void blk_queue_update_dma_pad(struct request_queue *, unsigned int);
 extern int blk_queue_dma_drain(struct request_queue *q,
                                dma_drain_needed_fn *dma_drain_needed,
                                void *buf, unsigned int size);
@@ -802,6 +829,15 @@ static inline struct request *blk_map_queue_find_tag(struct blk_queue_tag *bqt,
 
 extern int blkdev_issue_flush(struct block_device *, sector_t *);
 
+/*
+* command filter functions
+*/
+extern int blk_verify_command(struct file *file, unsigned char *cmd);
+extern int blk_cmd_filter_verify_command(struct blk_scsi_cmd_filter *filter,
+                                         unsigned char *cmd, mode_t *f_mode);
+extern int blk_register_filter(struct gendisk *disk);
+extern void blk_unregister_filter(struct gendisk *disk);
+
 #define MAX_PHYS_SEGMENTS 128
 #define MAX_HW_SEGMENTS 128
 #define SAFE_MAX_SECTORS 255
@@ -865,28 +901,119 @@ void kblockd_flush_work(struct work_struct *work);
 #define MODULE_ALIAS_BLOCKDEV_MAJOR(major) \
         MODULE_ALIAS("block-major-" __stringify(major) "-*")
 
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
 
-#else /* CONFIG_BLOCK */
-/*
- * stubs for when the block layer is configured out
- */
-#define buffer_heads_over_limit 0
+#define INTEGRITY_FLAG_READ     2       /* verify data integrity on read */
+#define INTEGRITY_FLAG_WRITE    4       /* generate data integrity on write */
 
-static inline long nr_blockdev_pages(void)
+struct blk_integrity_exchg {
+        void                    *prot_buf;
+        void                    *data_buf;
+        sector_t                sector;
+        unsigned int            data_size;
+        unsigned short          sector_size;
+        const char              *disk_name;
+};
+
+typedef void (integrity_gen_fn) (struct blk_integrity_exchg *);
+typedef int (integrity_vrfy_fn) (struct blk_integrity_exchg *);
+typedef void (integrity_set_tag_fn) (void *, void *, unsigned int);
+typedef void (integrity_get_tag_fn) (void *, void *, unsigned int);
+
+struct blk_integrity {
+        integrity_gen_fn        *generate_fn;
+        integrity_vrfy_fn       *verify_fn;
+        integrity_set_tag_fn    *set_tag_fn;
+        integrity_get_tag_fn    *get_tag_fn;
+
+        unsigned short          flags;
+        unsigned short          tuple_size;
+        unsigned short          sector_size;
+        unsigned short          tag_size;
+
+        const char              *name;
+
+        struct kobject          kobj;
+};
+
+extern int blk_integrity_register(struct gendisk *, struct blk_integrity *);
+extern void blk_integrity_unregister(struct gendisk *);
+extern int blk_integrity_compare(struct block_device *, struct block_device *);
+extern int blk_rq_map_integrity_sg(struct request *, struct scatterlist *);
+extern int blk_rq_count_integrity_sg(struct request *);
+
+static inline unsigned short blk_integrity_tuple_size(struct blk_integrity *bi)
 {
+        if (bi)
+                return bi->tuple_size;
+
         return 0;
 }
 
-static inline void exit_io_context(void)
+static inline struct blk_integrity *bdev_get_integrity(struct block_device *bdev)
 {
+        return bdev->bd_disk->integrity;
 }
 
-struct io_context;
-static inline int put_io_context(struct io_context *ioc)
+static inline unsigned int bdev_get_tag_size(struct block_device *bdev)
 {
-        return 1;
+        struct blk_integrity *bi = bdev_get_integrity(bdev);
+
+        if (bi)
+                return bi->tag_size;
+
+        return 0;
+}
+
+static inline int bdev_integrity_enabled(struct block_device *bdev, int rw)
+{
+        struct blk_integrity *bi = bdev_get_integrity(bdev);
+
+        if (bi == NULL)
+                return 0;
+
+        if (rw == READ && bi->verify_fn != NULL &&
+            (bi->flags & INTEGRITY_FLAG_READ))
+                return 1;
+
+        if (rw == WRITE && bi->generate_fn != NULL &&
+            (bi->flags & INTEGRITY_FLAG_WRITE))
+                return 1;
+
+        return 0;
 }
 
+static inline int blk_integrity_rq(struct request *rq)
+{
+        if (rq->bio == NULL)
+                return 0;
+
+        return bio_integrity(rq->bio);
+}
+
+#else /* CONFIG_BLK_DEV_INTEGRITY */
+
+#define blk_integrity_rq(rq)                    (0)
+#define blk_rq_count_integrity_sg(a)            (0)
+#define blk_rq_map_integrity_sg(a, b)           (0)
+#define bdev_get_integrity(a)                   (0)
+#define bdev_get_tag_size(a)                    (0)
+#define blk_integrity_compare(a, b)             (0)
+#define blk_integrity_register(a, b)            (0)
+#define blk_integrity_unregister(a)             do { } while (0);
+
+#endif /* CONFIG_BLK_DEV_INTEGRITY */
+
+#else /* CONFIG_BLOCK */
+/*
+ * stubs for when the block layer is configured out
+ */
+#define buffer_heads_over_limit 0
+
+static inline long nr_blockdev_pages(void)
+{
+        return 0;
+}
 
 #endif /* CONFIG_BLOCK */
 
diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h
index e3ef903aae88..d084b8d227a5 100644
--- a/include/linux/blktrace_api.h
+++ b/include/linux/blktrace_api.h
@@ -129,6 +129,7 @@ struct blk_trace {
         u32 dev;
         struct dentry *dir;
         struct dentry *dropped_file;
+        struct dentry *msg_file;
         atomic_t dropped;
 };
 
diff --git a/include/linux/configfs.h b/include/linux/configfs.h
index 3ae65b1bf90f..0488f937634a 100644
--- a/include/linux/configfs.h
+++ b/include/linux/configfs.h
@@ -165,8 +165,8 @@ struct configfs_item_operations {
 };
 
 struct configfs_group_operations {
-        struct config_item *(*make_item)(struct config_group *group, const char *name);
-        struct config_group *(*make_group)(struct config_group *group, const char *name);
+        int (*make_item)(struct config_group *group, const char *name, struct config_item **new_item);
+        int (*make_group)(struct config_group *group, const char *name, struct config_group **new_group);
         int (*commit_item)(struct config_item *item);
         void (*disconnect_notify)(struct config_group *group, struct config_item *item);
         void (*drop_item)(struct config_group *group, struct config_item *item);
diff --git a/include/linux/crc-t10dif.h b/include/linux/crc-t10dif.h
new file mode 100644
index 000000000000..a9c96d865ee7
--- /dev/null
+++ b/include/linux/crc-t10dif.h
@@ -0,0 +1,8 @@
+#ifndef _LINUX_CRC_T10DIF_H
+#define _LINUX_CRC_T10DIF_H
+
+#include <linux/types.h>
+
+__u16 crc_t10dif(unsigned char const *, size_t);
+
+#endif
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 425824bd49f3..c43dc47fdf75 100644
--- a/include/linux/crypto.h
+++ b/include/linux/crypto.h
@@ -30,15 +30,17 @@
  */
 #define CRYPTO_ALG_TYPE_MASK            0x0000000f
 #define CRYPTO_ALG_TYPE_CIPHER          0x00000001
-#define CRYPTO_ALG_TYPE_DIGEST          0x00000002
-#define CRYPTO_ALG_TYPE_HASH            0x00000003
+#define CRYPTO_ALG_TYPE_COMPRESS        0x00000002
+#define CRYPTO_ALG_TYPE_AEAD            0x00000003
 #define CRYPTO_ALG_TYPE_BLKCIPHER       0x00000004
 #define CRYPTO_ALG_TYPE_ABLKCIPHER      0x00000005
 #define CRYPTO_ALG_TYPE_GIVCIPHER       0x00000006
-#define CRYPTO_ALG_TYPE_COMPRESS        0x00000008
-#define CRYPTO_ALG_TYPE_AEAD            0x00000009
+#define CRYPTO_ALG_TYPE_DIGEST          0x00000008
+#define CRYPTO_ALG_TYPE_HASH            0x00000009
+#define CRYPTO_ALG_TYPE_AHASH           0x0000000a
 
 #define CRYPTO_ALG_TYPE_HASH_MASK       0x0000000e
+#define CRYPTO_ALG_TYPE_AHASH_MASK      0x0000000c
 #define CRYPTO_ALG_TYPE_BLKCIPHER_MASK  0x0000000c
 
 #define CRYPTO_ALG_LARVAL               0x00000010
@@ -102,6 +104,7 @@ struct crypto_async_request;
 struct crypto_aead;
 struct crypto_blkcipher;
 struct crypto_hash;
+struct crypto_ahash;
 struct crypto_tfm;
 struct crypto_type;
 struct aead_givcrypt_request;
@@ -131,6 +134,16 @@ struct ablkcipher_request {
         void *__ctx[] CRYPTO_MINALIGN_ATTR;
 };
 
+struct ahash_request {
+        struct crypto_async_request base;
+
+        unsigned int nbytes;
+        struct scatterlist *src;
+        u8                 *result;
+
+        void *__ctx[] CRYPTO_MINALIGN_ATTR;
+};
+
 /**
  *      struct aead_request - AEAD request
  *      @base: Common attributes for async crypto requests
@@ -195,6 +208,17 @@ struct ablkcipher_alg {
         unsigned int ivsize;
 };
 
+struct ahash_alg {
+        int (*init)(struct ahash_request *req);
+        int (*update)(struct ahash_request *req);
+        int (*final)(struct ahash_request *req);
+        int (*digest)(struct ahash_request *req);
+        int (*setkey)(struct crypto_ahash *tfm, const u8 *key,
+                        unsigned int keylen);
+
+        unsigned int digestsize;
+};
+
 struct aead_alg {
         int (*setkey)(struct crypto_aead *tfm, const u8 *key,
                       unsigned int keylen);
@@ -272,6 +296,7 @@ struct compress_alg {
 #define cra_cipher      cra_u.cipher
 #define cra_digest      cra_u.digest
 #define cra_hash        cra_u.hash
+#define cra_ahash       cra_u.ahash
 #define cra_compress    cra_u.compress
 
 struct crypto_alg {
@@ -298,6 +323,7 @@ struct crypto_alg {
                 struct cipher_alg cipher;
                 struct digest_alg digest;
                 struct hash_alg hash;
+                struct ahash_alg ahash;
                 struct compress_alg compress;
         } cra_u;
 
@@ -383,6 +409,18 @@ struct hash_tfm {
         unsigned int digestsize;
 };
 
+struct ahash_tfm {
+        int (*init)(struct ahash_request *req);
+        int (*update)(struct ahash_request *req);
+        int (*final)(struct ahash_request *req);
+        int (*digest)(struct ahash_request *req);
+        int (*setkey)(struct crypto_ahash *tfm, const u8 *key,
+                        unsigned int keylen);
+
+        unsigned int digestsize;
+        unsigned int reqsize;
+};
+
 struct compress_tfm {
         int (*cot_compress)(struct crypto_tfm *tfm,
                             const u8 *src, unsigned int slen,
@@ -397,6 +435,7 @@ struct compress_tfm {
 #define crt_blkcipher   crt_u.blkcipher
 #define crt_cipher      crt_u.cipher
 #define crt_hash        crt_u.hash
+#define crt_ahash       crt_u.ahash
 #define crt_compress    crt_u.compress
 
 struct crypto_tfm {
@@ -409,6 +448,7 @@ struct crypto_tfm {
                 struct blkcipher_tfm blkcipher;
                 struct cipher_tfm cipher;
                 struct hash_tfm hash;
+                struct ahash_tfm ahash;
                 struct compress_tfm compress;
         } crt_u;
         
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index d982eb89c77d..98202c672fde 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -3,6 +3,7 @@
 
 #include <asm/atomic.h>
 #include <linux/list.h>
+#include <linux/rculist.h>
 #include <linux/spinlock.h>
 #include <linux/cache.h>
 #include <linux/rcupdate.h>
diff --git a/include/linux/device.h b/include/linux/device.h
index 6a2d04c011bc..f71a78d123ae 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -68,6 +68,8 @@ struct bus_type {
         int (*resume_early)(struct device *dev);
         int (*resume)(struct device *dev);
 
+        struct pm_ext_ops *pm;
+
         struct bus_type_private *p;
 };
 
@@ -131,6 +133,8 @@ struct device_driver {
         int (*resume) (struct device *dev);
         struct attribute_group **groups;
 
+        struct pm_ops *pm;
+
         struct driver_private *p;
 };
 
@@ -197,6 +201,8 @@ struct class {
 
         int (*suspend)(struct device *dev, pm_message_t state);
         int (*resume)(struct device *dev);
+
+        struct pm_ops *pm;
 };
 
 extern int __must_check class_register(struct class *class);
@@ -248,8 +254,11 @@ struct device_type {
         struct attribute_group **groups;
         int (*uevent)(struct device *dev, struct kobj_uevent_env *env);
         void (*release)(struct device *dev);
+
         int (*suspend)(struct device *dev, pm_message_t state);
         int (*resume)(struct device *dev);
+
+        struct pm_ops *pm;
 };
 
 /* interface for exporting device attributes */
diff --git a/include/linux/elf.h b/include/linux/elf.h
index ff9fbed90123..edc3dac3f02f 100644
--- a/include/linux/elf.h
+++ b/include/linux/elf.h
@@ -358,6 +358,7 @@ typedef struct elf64_shdr {
 #define NT_PRXFPREG     0x46e62b7f      /* copied from gdb5.1/include/elf/common.h */
 #define NT_PPC_VMX      0x100           /* PowerPC Altivec/VMX registers */
 #define NT_PPC_SPE      0x101           /* PowerPC SPE/EVR registers */
+#define NT_PPC_VSX      0x102           /* PowerPC VSX registers */
 #define NT_386_TLS      0x200           /* i386 TLS slots (struct user_desc) */
 
 
diff --git a/include/linux/firmware-map.h b/include/linux/firmware-map.h
new file mode 100644
index 000000000000..acbdbcc16051
--- /dev/null
+++ b/include/linux/firmware-map.h
@@ -0,0 +1,74 @@
+/*
+ * include/linux/firmware-map.h:
+ *  Copyright (C) 2008 SUSE LINUX Products GmbH
+ *  by Bernhard Walle <bwalle@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2.0 as published by
+ * the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _LINUX_FIRMWARE_MAP_H
+#define _LINUX_FIRMWARE_MAP_H
+
+#include <linux/list.h>
+#include <linux/kobject.h>
+
+/*
+ * provide a dummy interface if CONFIG_FIRMWARE_MEMMAP is disabled
+ */
+#ifdef CONFIG_FIRMWARE_MEMMAP
+
+/**
+ * Adds a firmware mapping entry. This function uses kmalloc() for memory
+ * allocation. Use firmware_map_add_early() if you want to use the bootmem
+ * allocator.
+ *
+ * That function must be called before late_initcall.
+ *
+ * @start: Start of the memory range.
+ * @end:   End of the memory range (inclusive).
+ * @type:  Type of the memory range.
+ *
+ * Returns 0 on success, or -ENOMEM if no memory could be allocated.
+ */
+int firmware_map_add(resource_size_t start, resource_size_t end,
+                     const char *type);
+
+/**
+ * Adds a firmware mapping entry. This function uses the bootmem allocator
+ * for memory allocation. Use firmware_map_add() if you want to use kmalloc().
+ *
+ * That function must be called before late_initcall.
+ *
+ * @start: Start of the memory range.
+ * @end:   End of the memory range (inclusive).
+ * @type:  Type of the memory range.
+ *
+ * Returns 0 on success, or -ENOMEM if no memory could be allocated.
+ */
+int firmware_map_add_early(resource_size_t start, resource_size_t end,
+                           const char *type);
+
+#else /* CONFIG_FIRMWARE_MEMMAP */
+
+static inline int firmware_map_add(resource_size_t start, resource_size_t end,
+                                   const char *type)
+{
+        return 0;
+}
+
+static inline int firmware_map_add_early(resource_size_t start,
+                                         resource_size_t end, const char *type)
+{
+        return 0;
+}
+
+#endif /* CONFIG_FIRMWARE_MEMMAP */
+
+#endif /* _LINUX_FIRMWARE_MAP_H */
diff --git a/include/linux/firmware.h b/include/linux/firmware.h
index 6c7eff2ebada..c8ecf5b2a207 100644
--- a/include/linux/firmware.h
+++ b/include/linux/firmware.h
@@ -1,18 +1,39 @@
 #ifndef _LINUX_FIRMWARE_H
 #define _LINUX_FIRMWARE_H
+
 #include <linux/module.h>
 #include <linux/types.h>
+#include <linux/compiler.h>
+
 #define FIRMWARE_NAME_MAX 30 
 #define FW_ACTION_NOHOTPLUG 0
 #define FW_ACTION_HOTPLUG 1
 
 struct firmware {
         size_t size;
-        u8 *data;
+        const u8 *data;
 };
 
 struct device;
 
+struct builtin_fw {
+        char *name;
+        void *data;
+        unsigned long size;
+};
+
+/* We have to play tricks here much like stringify() to get the
+   __COUNTER__ macro to be expanded as we want it */
+#define __fw_concat1(x, y) x##y
+#define __fw_concat(x, y) __fw_concat1(x, y)
+
+#define DECLARE_BUILTIN_FIRMWARE(name, blob)                                 \
+        DECLARE_BUILTIN_FIRMWARE_SIZE(name, &(blob), sizeof(blob))
+
+#define DECLARE_BUILTIN_FIRMWARE_SIZE(name, blob, size)                      \
+        static const struct builtin_fw __fw_concat(__builtin_fw,__COUNTER__) \
+        __used __section(.builtin_fw) = { name, blob, size }
+
 #if defined(CONFIG_FW_LOADER) || (defined(CONFIG_FW_LOADER_MODULE) && defined(MODULE))
 int request_firmware(const struct firmware **fw, const char *name,
                      struct device *device);
diff --git a/include/linux/freezer.h b/include/linux/freezer.h
index 08934995c7ab..deddeedf3257 100644
--- a/include/linux/freezer.h
+++ b/include/linux/freezer.h
@@ -128,6 +128,15 @@ static inline void set_freezable(void)
 }
 
 /*
+ * Tell the freezer that the current task should be frozen by it and that it
+ * should send a fake signal to the task to freeze it.
+ */
+static inline void set_freezable_with_signal(void)
+{
+        current->flags &= ~(PF_NOFREEZE | PF_FREEZER_NOSIG);
+}
+
+/*
  * Freezer-friendly wrappers around wait_event_interruptible() and
  * wait_event_interruptible_timeout(), originally defined in <linux/wait.h>
  */
@@ -174,6 +183,7 @@ static inline void freezer_do_not_count(void) {}
 static inline void freezer_count(void) {}
 static inline int freezer_should_skip(struct task_struct *p) { return 0; }
 static inline void set_freezable(void) {}
+static inline void set_freezable_with_signal(void) {}
 
 #define wait_event_freezable(wq, condition)                             \
                 wait_event_interruptible(wq, condition)
diff --git a/include/linux/fs.h b/include/linux/fs.h
index d8e2762ed14d..c6455dadb21b 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1729,6 +1729,8 @@ static inline void invalidate_remote_inode(struct inode *inode)
 extern int invalidate_inode_pages2(struct address_space *mapping);
 extern int invalidate_inode_pages2_range(struct address_space *mapping,
                                          pgoff_t start, pgoff_t end);
+extern void generic_sync_sb_inodes(struct super_block *sb,
+                                struct writeback_control *wbc);
 extern int write_inode_now(struct inode *, int);
 extern int filemap_fdatawrite(struct address_space *);
 extern int filemap_flush(struct address_space *);
@@ -1740,6 +1742,8 @@ extern int wait_on_page_writeback_range(struct address_space *mapping,
                                 pgoff_t start, pgoff_t end);
 extern int __filemap_fdatawrite_range(struct address_space *mapping,
                                 loff_t start, loff_t end, int sync_mode);
+extern int filemap_fdatawrite_range(struct address_space *mapping,
+                                loff_t start, loff_t end);
 
 extern long do_fsync(struct file *file, int datasync);
 extern void sync_supers(void);
@@ -1870,7 +1874,8 @@ extern void
 file_ra_state_init(struct file_ra_state *ra, struct address_space *mapping);
 extern loff_t no_llseek(struct file *file, loff_t offset, int origin);
 extern loff_t generic_file_llseek(struct file *file, loff_t offset, int origin);
-extern loff_t remote_llseek(struct file *file, loff_t offset, int origin);
+extern loff_t generic_file_llseek_unlocked(struct file *file, loff_t offset,
+                        int origin);
 extern int generic_file_open(struct inode * inode, struct file * filp);
 extern int nonseekable_open(struct inode * inode, struct file * filp);
 
diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
new file mode 100644
index 000000000000..f368d041e02d
--- /dev/null
+++ b/include/linux/ftrace.h
@@ -0,0 +1,144 @@
+#ifndef _LINUX_FTRACE_H
+#define _LINUX_FTRACE_H
+
+#ifdef CONFIG_FTRACE
+
+#include <linux/linkage.h>
+#include <linux/fs.h>
+
+extern int ftrace_enabled;
+extern int
+ftrace_enable_sysctl(struct ctl_table *table, int write,
+                     struct file *filp, void __user *buffer, size_t *lenp,
+                     loff_t *ppos);
+
+typedef void (*ftrace_func_t)(unsigned long ip, unsigned long parent_ip);
+
+struct ftrace_ops {
+        ftrace_func_t     func;
+        struct ftrace_ops *next;
+};
+
+/*
+ * The ftrace_ops must be a static and should also
+ * be read_mostly.  These functions do modify read_mostly variables
+ * so use them sparely. Never free an ftrace_op or modify the
+ * next pointer after it has been registered. Even after unregistering
+ * it, the next pointer may still be used internally.
+ */
+int register_ftrace_function(struct ftrace_ops *ops);
+int unregister_ftrace_function(struct ftrace_ops *ops);
+void clear_ftrace_function(void);
+
+extern void ftrace_stub(unsigned long a0, unsigned long a1);
+
+#else /* !CONFIG_FTRACE */
+# define register_ftrace_function(ops) do { } while (0)
+# define unregister_ftrace_function(ops) do { } while (0)
+# define clear_ftrace_function(ops) do { } while (0)
+#endif /* CONFIG_FTRACE */
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+# define FTRACE_HASHBITS        10
+# define FTRACE_HASHSIZE        (1<<FTRACE_HASHBITS)
+
+enum {
+        FTRACE_FL_FREE          = (1 << 0),
+        FTRACE_FL_FAILED        = (1 << 1),
+        FTRACE_FL_FILTER        = (1 << 2),
+        FTRACE_FL_ENABLED       = (1 << 3),
+        FTRACE_FL_NOTRACE       = (1 << 4),
+        FTRACE_FL_CONVERTED     = (1 << 5),
+        FTRACE_FL_FROZEN        = (1 << 6),
+};
+
+struct dyn_ftrace {
+        struct hlist_node node;
+        unsigned long     ip; /* address of mcount call-site */
+        unsigned long     flags;
+};
+
+int ftrace_force_update(void);
+void ftrace_set_filter(unsigned char *buf, int len, int reset);
+
+/* defined in arch */
+extern int ftrace_ip_converted(unsigned long ip);
+extern unsigned char *ftrace_nop_replace(void);
+extern unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr);
+extern int ftrace_dyn_arch_init(void *data);
+extern int ftrace_mcount_set(unsigned long *data);
+extern int ftrace_modify_code(unsigned long ip, unsigned char *old_code,
+                              unsigned char *new_code);
+extern int ftrace_update_ftrace_func(ftrace_func_t func);
+extern void ftrace_caller(void);
+extern void ftrace_call(void);
+extern void mcount_call(void);
+
+extern int skip_trace(unsigned long ip);
+
+void ftrace_disable_daemon(void);
+void ftrace_enable_daemon(void);
+
+#else
+# define skip_trace(ip)                         ({ 0; })
+# define ftrace_force_update()                  ({ 0; })
+# define ftrace_set_filter(buf, len, reset)     do { } while (0)
+# define ftrace_disable_daemon()                do { } while (0)
+# define ftrace_enable_daemon()                 do { } while (0)
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+/* totally disable ftrace - can not re-enable after this */
+void ftrace_kill(void);
+void ftrace_kill_atomic(void);
+
+static inline void tracer_disable(void)
+{
+#ifdef CONFIG_FTRACE
+        ftrace_enabled = 0;
+#endif
+}
+
+#ifdef CONFIG_FRAME_POINTER
+/* TODO: need to fix this for ARM */
+# define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
+# define CALLER_ADDR1 ((unsigned long)__builtin_return_address(1))
+# define CALLER_ADDR2 ((unsigned long)__builtin_return_address(2))
+# define CALLER_ADDR3 ((unsigned long)__builtin_return_address(3))
+# define CALLER_ADDR4 ((unsigned long)__builtin_return_address(4))
+# define CALLER_ADDR5 ((unsigned long)__builtin_return_address(5))
+# define CALLER_ADDR6 ((unsigned long)__builtin_return_address(6))
+#else
+# define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
+# define CALLER_ADDR1 0UL
+# define CALLER_ADDR2 0UL
+# define CALLER_ADDR3 0UL
+# define CALLER_ADDR4 0UL
+# define CALLER_ADDR5 0UL
+# define CALLER_ADDR6 0UL
+#endif
+
+#ifdef CONFIG_IRQSOFF_TRACER
+  extern void time_hardirqs_on(unsigned long a0, unsigned long a1);
+  extern void time_hardirqs_off(unsigned long a0, unsigned long a1);
+#else
+# define time_hardirqs_on(a0, a1)               do { } while (0)
+# define time_hardirqs_off(a0, a1)              do { } while (0)
+#endif
+
+#ifdef CONFIG_PREEMPT_TRACER
+  extern void trace_preempt_on(unsigned long a0, unsigned long a1);
+  extern void trace_preempt_off(unsigned long a0, unsigned long a1);
+#else
+# define trace_preempt_on(a0, a1)               do { } while (0)
+# define trace_preempt_off(a0, a1)              do { } while (0)
+#endif
+
+#ifdef CONFIG_TRACING
+extern void
+ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3);
+#else
+static inline void
+ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3) { }
+#endif
+
+#endif /* _LINUX_FTRACE_H */
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index ae7aec3cabee..e8787417f65a 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -110,6 +110,14 @@ struct hd_struct {
 #define GENHD_FL_SUPPRESS_PARTITION_INFO        32
 #define GENHD_FL_FAIL                           64
 
+#define BLK_SCSI_MAX_CMDS       (256)
+#define BLK_SCSI_CMD_PER_LONG   (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
+
+struct blk_scsi_cmd_filter {
+        unsigned long read_ok[BLK_SCSI_CMD_PER_LONG];
+        unsigned long write_ok[BLK_SCSI_CMD_PER_LONG];
+        struct kobject kobj;
+};
 
 struct gendisk {
         int major;                      /* major number of driver */
@@ -120,6 +128,7 @@ struct gendisk {
         struct hd_struct **part;        /* [indexed by minor] */
         struct block_device_operations *fops;
         struct request_queue *queue;
+        struct blk_scsi_cmd_filter cmd_filter;
         void *private_data;
         sector_t capacity;
 
@@ -141,6 +150,9 @@ struct gendisk {
         struct disk_stats dkstats;
 #endif
         struct work_struct async_notify;
+#ifdef  CONFIG_BLK_DEV_INTEGRITY
+        struct blk_integrity *integrity;
+#endif
 };
 
 /* 
diff --git a/include/linux/i2c-algo-pcf.h b/include/linux/i2c-algo-pcf.h
index 77afbb60fd11..0177d280f733 100644
--- a/include/linux/i2c-algo-pcf.h
+++ b/include/linux/i2c-algo-pcf.h
@@ -33,9 +33,11 @@ struct i2c_algo_pcf_data {
         int  (*getclock) (void *data);
         void (*waitforpin) (void);
 
-        /* local settings */
-        int udelay;
-        int timeout;
+        /* Multi-master lost arbitration back-off delay (msecs)
+         * This should be set by the bus adapter or knowledgable client
+         * if bus is multi-mastered, else zero
+         */
+        unsigned long lab_mdelay;
 };
 
 int i2c_pcf_add_bus(struct i2c_adapter *);
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 580acc93903e..ef13b7c66df3 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -91,8 +91,6 @@
 #define I2C_DRIVERID_M52790     95      /* Mitsubishi M52790SP/FP AV switch */
 #define I2C_DRIVERID_CS5345     96      /* cs5345 audio processor       */
 
-#define I2C_DRIVERID_I2CDEV     900
-
 #define I2C_DRIVERID_OV7670 1048        /* Omnivision 7670 camera */
 
 /*
@@ -111,7 +109,6 @@
 #define I2C_HW_B_RIVA           0x010010 /* Riva based graphics cards */
 #define I2C_HW_B_IOC            0x010011 /* IOC bit-wiggling */
 #define I2C_HW_B_IXP2000        0x010016 /* GPIO on IXP2000 systems */
-#define I2C_HW_B_S3VIA          0x010018 /* S3Via ProSavage adapter */
 #define I2C_HW_B_ZR36067        0x010019 /* Zoran-36057/36067 based boards */
 #define I2C_HW_B_PCILYNX        0x01001a /* TI PCILynx I2C adapter */
 #define I2C_HW_B_CX2388x        0x01001b /* connexant 2388x based tv cards */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 8dc730132192..08be0d21864c 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -35,6 +35,8 @@
 #include <linux/sched.h>        /* for completion */
 #include <linux/mutex.h>
 
+extern struct bus_type i2c_bus_type;
+
 /* --- General options ------------------------------------------------ */
 
 struct i2c_msg;
@@ -43,6 +45,7 @@ struct i2c_adapter;
 struct i2c_client;
 struct i2c_driver;
 union i2c_smbus_data;
+struct i2c_board_info;
 
 /*
  * The master routines are the ones normally used to transmit data to devices
@@ -69,9 +72,8 @@ extern s32 i2c_smbus_xfer (struct i2c_adapter * adapter, u16 addr,
                            union i2c_smbus_data * data);
 
 /* Now follow the 'nice' access routines. These also document the calling
-   conventions of smbus_access. */
+   conventions of i2c_smbus_xfer. */
 
-extern s32 i2c_smbus_write_quick(struct i2c_client * client, u8 value);
 extern s32 i2c_smbus_read_byte(struct i2c_client * client);
 extern s32 i2c_smbus_write_byte(struct i2c_client * client, u8 value);
 extern s32 i2c_smbus_read_byte_data(struct i2c_client * client, u8 command);
@@ -93,15 +95,33 @@ extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client,
                                           u8 command, u8 length,
                                           const u8 *values);
 
-/*
- * A driver is capable of handling one or more physical devices present on
- * I2C adapters. This information is used to inform the driver of adapter
- * events.
+/**
+ * struct i2c_driver - represent an I2C device driver
+ * @class: What kind of i2c device we instantiate (for detect)
+ * @detect: Callback for device detection
+ * @address_data: The I2C addresses to probe, ignore or force (for detect)
+ * @clients: List of detected clients we created (for i2c-core use only)
  *
  * The driver.owner field should be set to the module owner of this driver.
  * The driver.name field should be set to the name of this driver.
+ *
+ * For automatic device detection, both @detect and @address_data must
+ * be defined. @class should also be set, otherwise only devices forced
+ * with module parameters will be created. The detect function must
+ * fill at least the name field of the i2c_board_info structure it is
+ * handed upon successful detection, and possibly also the flags field.
+ *
+ * If @detect is missing, the driver will still work fine for enumerated
+ * devices. Detected devices simply won't be supported. This is expected
+ * for the many I2C/SMBus devices which can't be detected reliably, and
+ * the ones which can always be enumerated in practice.
+ *
+ * The i2c_client structure which is handed to the @detect callback is
+ * not a real i2c_client. It is initialized just enough so that you can
+ * call i2c_smbus_read_byte_data and friends on it. Don't do anything
+ * else with it. In particular, calling dev_dbg and friends on it is
+ * not allowed.
  */
-
 struct i2c_driver {
         int id;
         unsigned int class;
@@ -141,6 +161,11 @@ struct i2c_driver {
 
         struct device_driver driver;
         const struct i2c_device_id *id_table;
+
+        /* Device detection callback for automatic device creation */
+        int (*detect)(struct i2c_client *, int kind, struct i2c_board_info *);
+        const struct i2c_client_address_data *address_data;
+        struct list_head clients;
 };
 #define to_i2c_driver(d) container_of(d, struct i2c_driver, driver)
 
@@ -156,6 +181,7 @@ struct i2c_driver {
  * @dev: Driver model device node for the slave.
  * @irq: indicates the IRQ generated by this device (if any)
  * @list: list of active/busy clients (DEPRECATED)
+ * @detected: member of an i2c_driver.clients list
  * @released: used to synchronize client releases & detaches and references
  *
  * An i2c_client identifies a single device (i.e. chip) connected to an
@@ -173,6 +199,7 @@ struct i2c_client {
         struct device dev;              /* the device structure         */
         int irq;                        /* irq issued by device         */
         struct list_head list;          /* DEPRECATED */
+        struct list_head detected;
         struct completion released;
 };
 #define to_i2c_client(d) container_of(d, struct i2c_client, dev)
@@ -350,10 +377,11 @@ static inline void i2c_set_adapdata (struct i2c_adapter *dev, void *data)
 #define I2C_CLASS_HWMON         (1<<0)  /* lm_sensors, ... */
 #define I2C_CLASS_TV_ANALOG     (1<<1)  /* bttv + friends */
 #define I2C_CLASS_TV_DIGITAL    (1<<2)  /* dvb cards */
-#define I2C_CLASS_DDC           (1<<3)  /* i2c-matroxfb ? */
+#define I2C_CLASS_DDC           (1<<3)  /* DDC bus on graphics adapters */
 #define I2C_CLASS_CAM_ANALOG    (1<<4)  /* camera with analog CCD */
 #define I2C_CLASS_CAM_DIGITAL   (1<<5)  /* most webcams */
 #define I2C_CLASS_SOUND         (1<<6)  /* sound devices */
+#define I2C_CLASS_SPD           (1<<7)  /* SPD EEPROMs and similar */
 #define I2C_CLASS_ALL           (UINT_MAX) /* all of the above */
 
 /* i2c_client_address_data is the struct for holding default client
@@ -537,7 +565,7 @@ union i2c_smbus_data {
                                /* and one more for user-space compatibility */
 };
 
-/* smbus_access read or write markers */
+/* i2c_smbus_xfer read or write markers */
 #define I2C_SMBUS_READ  1
 #define I2C_SMBUS_WRITE 0
 
diff --git a/include/linux/i2c/at24.h b/include/linux/i2c/at24.h
new file mode 100644
index 000000000000..f6edd522a929
--- /dev/null
+++ b/include/linux/i2c/at24.h
@@ -0,0 +1,28 @@
+#ifndef _LINUX_AT24_H
+#define _LINUX_AT24_H
+
+#include <linux/types.h>
+
+/*
+ * As seen through Linux I2C, differences between the most common types of I2C
+ * memory include:
+ * - How much memory is available (usually specified in bit)?
+ * - What write page size does it support?
+ * - Special flags (16 bit addresses, read_only, world readable...)?
+ *
+ * If you set up a custom eeprom type, please double-check the parameters.
+ * Especially page_size needs extra care, as you risk data loss if your value
+ * is bigger than what the chip actually supports!
+ */
+
+struct at24_platform_data {
+        u32             byte_len;               /* size (sum of all addr) */
+        u16             page_size;              /* for writes */
+        u8              flags;
+#define AT24_FLAG_ADDR16        0x80    /* address pointer is 16 bit */
+#define AT24_FLAG_READONLY      0x40    /* sysfs-entry will be read-only */
+#define AT24_FLAG_IRUGO         0x20    /* sysfs-entry will be world-readable */
+#define AT24_FLAG_TAKE8ADDR     0x10    /* take always 8 addresses (24c00) */
+};
+
+#endif /* _LINUX_AT24_H */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index eddb6daadf4a..4726126f5a59 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -139,6 +139,12 @@ struct ide_io_ports {
 #define WAIT_MIN_SLEEP  (2*HZ/100)      /* 20msec - minimum sleep time */
 
 /*
+ * Op codes for special requests to be handled by ide_special_rq().
+ * Values should be in the range of 0x20 to 0x3f.
+ */
+#define REQ_DRIVE_RESET         0x20
+
+/*
  * Check for an interrupt and acknowledge the interrupt status
  */
 struct hwif_s;
@@ -171,7 +177,7 @@ typedef struct hw_regs_s {
         int             irq;                    /* our irq number */
         ide_ack_intr_t  *ack_intr;              /* acknowledge interrupt */
         hwif_chipset_t  chipset;
-        struct device   *dev;
+        struct device   *dev, *parent;
 } hw_regs_t;
 
 void ide_init_port_data(struct hwif_s *, unsigned int);
@@ -364,7 +370,6 @@ typedef struct ide_drive_s {
         u8      wcache;         /* status of write cache */
         u8      acoustic;       /* acoustic management */
         u8      media;          /* disk, cdrom, tape, floppy, ... */
-        u8      ctl;            /* "normal" value for Control register */
         u8      ready_stat;     /* min status value for drive ready */
         u8      mult_count;     /* current multiple sector setting */
         u8      mult_req;       /* requested multiple sector setting */
@@ -406,8 +411,8 @@ typedef struct ide_drive_s {
 struct ide_port_info;
 
 struct ide_port_ops {
-        /* host specific initialization of devices on a port */
-        void    (*port_init_devs)(struct hwif_s *);
+        /* host specific initialization of a device */
+        void    (*init_dev)(ide_drive_t *);
         /* routine to program host for PIO mode */
         void    (*set_pio_mode)(ide_drive_t *, const u8);
         /* routine to program host for DMA mode */
@@ -493,7 +498,7 @@ typedef struct hwif_s {
         void (*ide_dma_clear_irq)(ide_drive_t *drive);
 
         void (*OUTB)(u8 addr, unsigned long port);
-        void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port);
+        void (*OUTBSYNC)(struct hwif_s *hwif, u8 addr, unsigned long port);
 
         u8  (*INB)(unsigned long port);
 
@@ -532,7 +537,6 @@ typedef struct hwif_s {
         unsigned        serialized : 1; /* serialized all channel operation */
         unsigned        sharing_irq: 1; /* 1 = sharing irq with another hwif */
         unsigned        sg_mapped  : 1; /* sg_table and sg_nents are ready */
-        unsigned        mmio       : 1; /* host uses MMIO */
 
         struct device           gendev;
         struct device           *portdev;
@@ -567,8 +571,6 @@ typedef struct hwgroup_s {
         unsigned int sleeping   : 1;
                 /* BOOL: polling active & poll_timeout field valid */
         unsigned int polling    : 1;
-                /* BOOL: in a polling reset situation. Must not trigger another reset yet */
-        unsigned int resetting  : 1;
 
                 /* current drive */
         ide_drive_t *drive;
@@ -604,12 +606,13 @@ enum {
         PC_FLAG_SUPPRESS_ERROR          = (1 << 1),
         PC_FLAG_WAIT_FOR_DSC            = (1 << 2),
         PC_FLAG_DMA_OK                  = (1 << 3),
-        PC_FLAG_DMA_RECOMMENDED         = (1 << 4),
-        PC_FLAG_DMA_IN_PROGRESS         = (1 << 5),
-        PC_FLAG_DMA_ERROR               = (1 << 6),
-        PC_FLAG_WRITING                 = (1 << 7),
+        PC_FLAG_DMA_IN_PROGRESS         = (1 << 4),
+        PC_FLAG_DMA_ERROR               = (1 << 5),
+        PC_FLAG_WRITING                 = (1 << 6),
         /* command timed out */
-        PC_FLAG_TIMEDOUT                = (1 << 8),
+        PC_FLAG_TIMEDOUT                = (1 << 7),
+        PC_FLAG_ZIP_DRIVE               = (1 << 8),
+        PC_FLAG_DRQ_INTERRUPT           = (1 << 9),
 };
 
 struct ide_atapi_pc {
@@ -642,8 +645,8 @@ struct ide_atapi_pc {
          * to change/removal later.
          */
         u8 pc_buf[256];
-        void (*idefloppy_callback) (ide_drive_t *);
-        ide_startstop_t (*idetape_callback) (ide_drive_t *);
+
+        void (*callback)(ide_drive_t *);
 
         /* idetape only */
         struct idetape_bh *bh;
@@ -787,7 +790,6 @@ struct ide_driver_s {
         ide_startstop_t (*do_request)(ide_drive_t *, struct request *, sector_t);
         int             (*end_request)(ide_drive_t *, int, int);
         ide_startstop_t (*error)(ide_drive_t *, struct request *rq, u8, u8);
-        ide_startstop_t (*abort)(ide_drive_t *, struct request *rq);
         struct device_driver    gen_driver;
         int             (*probe)(ide_drive_t *);
         void            (*remove)(ide_drive_t *);
@@ -802,22 +804,6 @@ struct ide_driver_s {
 
 int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsigned, unsigned long);
 
-/*
- * ide_hwifs[] is the master data structure used to keep track
- * of just about everything in ide.c.  Whenever possible, routines
- * should be using pointers to a drive (ide_drive_t *) or
- * pointers to a hwif (ide_hwif_t *), rather than indexing this
- * structure directly (the allocation/layout may change!).
- *
- */
-#ifndef _IDE_C
-extern  ide_hwif_t      ide_hwifs[];            /* master data repository */
-#endif
-extern int ide_noacpi;
-extern int ide_acpigtf;
-extern int ide_acpionboot;
-extern int noautodma;
-
 extern int ide_vlb_clk;
 extern int ide_pci_clk;
 
@@ -845,10 +831,6 @@ ide_startstop_t __ide_error(ide_drive_t *, struct request *, u8, u8);
 
 ide_startstop_t ide_error (ide_drive_t *drive, const char *msg, byte stat);
 
-ide_startstop_t __ide_abort(ide_drive_t *, struct request *);
-
-extern ide_startstop_t ide_abort(ide_drive_t *, const char *);
-
 extern void ide_fix_driveid(struct hd_driveid *);
 
 extern void ide_fixstring(u8 *, const int, const int);
@@ -857,25 +839,12 @@ int ide_wait_stat(ide_startstop_t *, ide_drive_t *, u8, u8, unsigned long);
 
 extern ide_startstop_t ide_do_reset (ide_drive_t *);
 
-extern void ide_init_drive_cmd (struct request *rq);
-
-/*
- * "action" parameter type for ide_do_drive_cmd() below.
- */
-typedef enum {
-        ide_wait,       /* insert rq at end of list, and wait for it */
-        ide_preempt,    /* insert rq in front of current request */
-        ide_head_wait,  /* insert rq in front of current request and wait for it */
-        ide_end         /* insert rq at end of list, but don't wait for it */
-} ide_action_t;
-
-extern int ide_do_drive_cmd(ide_drive_t *, struct request *, ide_action_t);
+extern void ide_do_drive_cmd(ide_drive_t *, struct request *);
 
 extern void ide_end_drive_cmd(ide_drive_t *, u8, u8);
 
 enum {
         IDE_TFLAG_LBA48                 = (1 << 0),
-        IDE_TFLAG_NO_SELECT_MASK        = (1 << 1),
         IDE_TFLAG_FLAGGED               = (1 << 2),
         IDE_TFLAG_OUT_DATA              = (1 << 3),
         IDE_TFLAG_OUT_HOB_FEATURE       = (1 << 4),
@@ -980,11 +949,23 @@ typedef struct ide_task_s {
 void ide_tf_dump(const char *, struct ide_taskfile *);
 
 extern void SELECT_DRIVE(ide_drive_t *);
+void SELECT_MASK(ide_drive_t *, int);
 
 extern int drive_is_ready(ide_drive_t *);
 
 void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8);
 
+ide_startstop_t ide_pc_intr(ide_drive_t *drive, struct ide_atapi_pc *pc,
+        ide_handler_t *handler, unsigned int timeout, ide_expiry_t *expiry,
+        void (*update_buffers)(ide_drive_t *, struct ide_atapi_pc *),
+        void (*retry_pc)(ide_drive_t *), void (*dsc_handle)(ide_drive_t *),
+        void (*io_buffers)(ide_drive_t *, struct ide_atapi_pc *, unsigned int,
+                           int));
+ide_startstop_t ide_transfer_pc(ide_drive_t *, struct ide_atapi_pc *,
+                                ide_handler_t *, unsigned int, ide_expiry_t *);
+ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_atapi_pc *,
+                             ide_handler_t *, unsigned int, ide_expiry_t *);
+
 ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *);
 
 void task_end_request(ide_drive_t *, struct request *, u8);
@@ -996,8 +977,6 @@ int ide_taskfile_ioctl(ide_drive_t *, unsigned int, unsigned long);
 int ide_cmd_ioctl(ide_drive_t *, unsigned int, unsigned long);
 int ide_task_ioctl(ide_drive_t *, unsigned int, unsigned long);
 
-extern int system_bus_clock(void);
-
 extern int ide_driveid_update(ide_drive_t *);
 extern int ide_config_drive_speed(ide_drive_t *, u8);
 extern u8 eighty_ninty_three (ide_drive_t *);
@@ -1279,16 +1258,43 @@ static inline int ide_dev_is_sata(struct hd_driveid *id)
 u64 ide_get_lba_addr(struct ide_taskfile *, int);
 u8 ide_dump_status(ide_drive_t *, const char *, u8);
 
-typedef struct ide_pio_timings_s {
-        int     setup_time;     /* Address setup (ns) minimum */
-        int     active_time;    /* Active pulse (ns) minimum */
-        int     cycle_time;     /* Cycle time (ns) minimum = */
-                                /* active + recovery (+ setup for some chips) */
-} ide_pio_timings_t;
+struct ide_timing {
+        u8  mode;
+        u8  setup;      /* t1 */
+        u16 act8b;      /* t2 for 8-bit io */
+        u16 rec8b;      /* t2i for 8-bit io */
+        u16 cyc8b;      /* t0 for 8-bit io */
+        u16 active;     /* t2 or tD */
+        u16 recover;    /* t2i or tK */
+        u16 cycle;      /* t0 */
+        u16 udma;       /* t2CYCTYP/2 */
+};
+
+enum {
+        IDE_TIMING_SETUP        = (1 << 0),
+        IDE_TIMING_ACT8B        = (1 << 1),
+        IDE_TIMING_REC8B        = (1 << 2),
+        IDE_TIMING_CYC8B        = (1 << 3),
+        IDE_TIMING_8BIT         = IDE_TIMING_ACT8B | IDE_TIMING_REC8B |
+                                  IDE_TIMING_CYC8B,
+        IDE_TIMING_ACTIVE       = (1 << 4),
+        IDE_TIMING_RECOVER      = (1 << 5),
+        IDE_TIMING_CYCLE        = (1 << 6),
+        IDE_TIMING_UDMA         = (1 << 7),
+        IDE_TIMING_ALL          = IDE_TIMING_SETUP | IDE_TIMING_8BIT |
+                                  IDE_TIMING_ACTIVE | IDE_TIMING_RECOVER |
+                                  IDE_TIMING_CYCLE | IDE_TIMING_UDMA,
+};
+
+struct ide_timing *ide_timing_find_mode(u8);
+u16 ide_pio_cycle_time(ide_drive_t *, u8);
+void ide_timing_merge(struct ide_timing *, struct ide_timing *,
+                      struct ide_timing *, unsigned int);
+int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int);
+
+int ide_scan_pio_blacklist(char *);
 
-unsigned int ide_pio_cycle_time(ide_drive_t *, u8);
 u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8);
-extern const ide_pio_timings_t ide_pio_timings[6];
 
 int ide_set_pio_mode(ide_drive_t *, u8);
 int ide_set_dma_mode(ide_drive_t *, u8);
@@ -1349,7 +1355,8 @@ static inline void ide_set_irq(ide_drive_t *drive, int on)
 {
         ide_hwif_t *hwif = drive->hwif;
 
-        hwif->OUTB(drive->ctl | (on ? 0 : 2), hwif->io_ports.ctl_addr);
+        hwif->OUTBSYNC(hwif, ATA_DEVCTL_OBS | (on ? 0 : 2),
+                       hwif->io_ports.ctl_addr);
 }
 
 static inline u8 ide_read_status(ide_drive_t *drive)
diff --git a/include/linux/ihex.h b/include/linux/ihex.h
new file mode 100644
index 000000000000..2baace2788a7
--- /dev/null
+++ b/include/linux/ihex.h
@@ -0,0 +1,74 @@
+/*
+ * Compact binary representation of ihex records. Some devices need their
+ * firmware loaded in strange orders rather than a single big blob, but
+ * actually parsing ihex-as-text within the kernel seems silly. Thus,...
+ */
+
+#ifndef __LINUX_IHEX_H__
+#define __LINUX_IHEX_H__
+
+#include <linux/types.h>
+#include <linux/firmware.h>
+#include <linux/device.h>
+
+/* Intel HEX files actually limit the length to 256 bytes, but we have
+   drivers which would benefit from using separate records which are
+   longer than that, so we extend to 16 bits of length */
+struct ihex_binrec {
+        __be32 addr;
+        __be16 len;
+        uint8_t data[0];
+} __attribute__((aligned(4)));
+
+/* Find the next record, taking into account the 4-byte alignment */
+static inline const struct ihex_binrec *
+ihex_next_binrec(const struct ihex_binrec *rec)
+{
+        int next = ((be16_to_cpu(rec->len) + 5) & ~3) - 2;
+        rec = (void *)&rec->data[next];
+
+        return be16_to_cpu(rec->len) ? rec : NULL;
+}
+
+/* Check that ihex_next_binrec() won't take us off the end of the image... */
+static inline int ihex_validate_fw(const struct firmware *fw)
+{
+        const struct ihex_binrec *rec;
+        size_t ofs = 0;
+
+        while (ofs <= fw->size - sizeof(*rec)) {
+                rec = (void *)&fw->data[ofs];
+
+                /* Zero length marks end of records */
+                if (!be16_to_cpu(rec->len))
+                        return 0;
+
+                /* Point to next record... */
+                ofs += (sizeof(*rec) + be16_to_cpu(rec->len) + 3) & ~3;
+        }
+        return -EINVAL;
+}
+
+/* Request firmware and validate it so that we can trust we won't
+ * run off the end while reading records... */
+static inline int request_ihex_firmware(const struct firmware **fw,
+                                        const char *fw_name,
+                                        struct device *dev)
+{
+        const struct firmware *lfw;
+        int ret;
+
+        ret = request_firmware(&lfw, fw_name, dev);
+        if (ret)
+                return ret;
+        ret = ihex_validate_fw(lfw);
+        if (ret) {
+                dev_err(dev, "Firmware \"%s\" not valid IHEX records\n",
+                        fw_name);
+                release_firmware(lfw);
+                return ret;
+        }
+        *fw = lfw;
+        return 0;
+}
+#endif /* __LINUX_IHEX_H__ */
diff --git a/include/linux/inet.h b/include/linux/inet.h
index 1354080cf8cf..4cca05c9678e 100644
--- a/include/linux/inet.h
+++ b/include/linux/inet.h
@@ -44,6 +44,13 @@
 
 #include <linux/types.h>
 
+/*
+ * These mimic similar macros defined in user-space for inet_ntop(3).
+ * See /usr/include/netinet/in.h .
+ */
+#define INET_ADDRSTRLEN         (16)
+#define INET6_ADDRSTRLEN        (48)
+
 extern __be32 in_aton(const char *str);
 extern int in4_pton(const char *src, int srclen, u8 *dst, int delim, const char **end);
 extern int in6_pton(const char *src, int srclen, u8 *dst, int delim, const char **end);
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index 9927a88674a3..93c45acf249a 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -140,8 +140,8 @@ extern struct group_info init_groups;
                 .nr_cpus_allowed = NR_CPUS,                             \
         },                                                              \
         .tasks          = LIST_HEAD_INIT(tsk.tasks),                    \
-        .ptrace_children= LIST_HEAD_INIT(tsk.ptrace_children),          \
-        .ptrace_list    = LIST_HEAD_INIT(tsk.ptrace_list),              \
+        .ptraced        = LIST_HEAD_INIT(tsk.ptraced),                  \
+        .ptrace_entry   = LIST_HEAD_INIT(tsk.ptrace_entry),             \
         .real_parent    = &tsk,                                         \
         .parent         = &tsk,                                         \
         .children       = LIST_HEAD_INIT(tsk.children),                 \
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index f1fc7470d26c..62aa4f895abe 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -104,8 +104,11 @@ extern void enable_irq(unsigned int irq);
 
 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS)
 
+extern cpumask_t irq_default_affinity;
+
 extern int irq_set_affinity(unsigned int irq, cpumask_t cpumask);
 extern int irq_can_set_affinity(unsigned int irq);
+extern int irq_select_affinity(unsigned int irq);
 
 #else /* CONFIG_SMP */
 
@@ -119,6 +122,8 @@ static inline int irq_can_set_affinity(unsigned int irq)
         return 0;
 }
 
+static inline int irq_select_affinity(unsigned int irq)  { return 0; }
+
 #endif /* CONFIG_SMP && CONFIG_GENERIC_HARDIRQS */
 
 #ifdef CONFIG_GENERIC_HARDIRQS
@@ -285,12 +290,11 @@ enum
 struct softirq_action
 {
         void    (*action)(struct softirq_action *);
-        void    *data;
 };
 
 asmlinkage void do_softirq(void);
 asmlinkage void __do_softirq(void);
-extern void open_softirq(int nr, void (*action)(struct softirq_action*), void *data);
+extern void open_softirq(int nr, void (*action)(struct softirq_action *));
 extern void softirq_init(void);
 #define __raise_softirq_irqoff(nr) do { or_softirq_pending(1UL << (nr)); } while (0)
 extern void raise_softirq_irqoff(unsigned int nr);
diff --git a/include/linux/iocontext.h b/include/linux/iocontext.h
index 2b7a1187cb29..08b987bccf89 100644
--- a/include/linux/iocontext.h
+++ b/include/linux/iocontext.h
@@ -99,4 +99,22 @@ static inline struct io_context *ioc_task_link(struct io_context *ioc)
         return NULL;
 }
 
+#ifdef CONFIG_BLOCK
+int put_io_context(struct io_context *ioc);
+void exit_io_context(void);
+struct io_context *get_io_context(gfp_t gfp_flags, int node);
+struct io_context *alloc_io_context(gfp_t gfp_flags, int node);
+void copy_io_context(struct io_context **pdst, struct io_context **psrc);
+#else
+static inline void exit_io_context(void)
+{
+}
+
+struct io_context;
+static inline int put_io_context(struct io_context *ioc)
+{
+        return 1;
+}
+#endif
+
 #endif
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index c6801bffe76d..2cd07cc29687 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -59,6 +59,7 @@ struct resource_list {
 #define IORESOURCE_IRQ_HIGHLEVEL        (1<<2)
 #define IORESOURCE_IRQ_LOWLEVEL         (1<<3)
 #define IORESOURCE_IRQ_SHAREABLE        (1<<4)
+#define IORESOURCE_IRQ_OPTIONAL         (1<<5)
 
 /* PnP DMA specific bits (IORESOURCE_BITS) */
 #define IORESOURCE_DMA_TYPE_MASK        (3<<0)
@@ -88,6 +89,10 @@ struct resource_list {
 #define IORESOURCE_MEM_SHADOWABLE       (1<<5)  /* dup: IORESOURCE_SHADOWABLE */
 #define IORESOURCE_MEM_EXPANSIONROM     (1<<6)
 
+/* PnP I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IO_16BIT_ADDR        (1<<0)
+#define IORESOURCE_IO_FIXED             (1<<1)
+
 /* PCI ROM control bits (IORESOURCE_BITS) */
 #define IORESOURCE_ROM_ENABLE           (1<<0)  /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
 #define IORESOURCE_ROM_SHADOW           (1<<1)  /* ROM is copy at C000:0 */
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 552e0ec269c9..8ccb462ea42c 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -244,15 +244,6 @@ static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 }
 #endif
 
-#ifdef CONFIG_AUTO_IRQ_AFFINITY
-extern int select_smp_affinity(unsigned int irq);
-#else
-static inline int select_smp_affinity(unsigned int irq)
-{
-        return 1;
-}
-#endif
-
 extern int no_irq_affinity;
 
 static inline int irq_balancing_disabled(unsigned int irq)
diff --git a/include/linux/irqflags.h b/include/linux/irqflags.h
index e600c4e9b8c5..2b1c2e58566e 100644
--- a/include/linux/irqflags.h
+++ b/include/linux/irqflags.h
@@ -12,10 +12,10 @@
 #define _LINUX_TRACE_IRQFLAGS_H
 
 #ifdef CONFIG_TRACE_IRQFLAGS
-  extern void trace_hardirqs_on(void);
-  extern void trace_hardirqs_off(void);
   extern void trace_softirqs_on(unsigned long ip);
   extern void trace_softirqs_off(unsigned long ip);
+  extern void trace_hardirqs_on(void);
+  extern void trace_hardirqs_off(void);
 # define trace_hardirq_context(p)       ((p)->hardirq_context)
 # define trace_softirq_context(p)       ((p)->softirq_context)
 # define trace_hardirqs_enabled(p)      ((p)->hardirqs_enabled)
@@ -41,6 +41,15 @@
 # define INIT_TRACE_IRQFLAGS
 #endif
 
+#if defined(CONFIG_IRQSOFF_TRACER) || \
+        defined(CONFIG_PREEMPT_TRACER)
+ extern void stop_critical_timings(void);
+ extern void start_critical_timings(void);
+#else
+# define stop_critical_timings() do { } while (0)
+# define start_critical_timings() do { } while (0)
+#endif
+
 #ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT
 
 #include <asm/irqflags.h>
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index d147f0f90360..3dd209007098 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -168,6 +168,8 @@ struct commit_header {
         unsigned char   h_chksum_size;
         unsigned char   h_padding[2];
         __be32          h_chksum[JBD2_CHECKSUM_BYTES];
+        __be64          h_commit_sec;
+        __be32          h_commit_nsec;
 };
 
 /*
@@ -379,6 +381,38 @@ static inline void jbd_unlock_bh_journal_head(struct buffer_head *bh)
         bit_spin_unlock(BH_JournalHead, &bh->b_state);
 }
 
+/* Flags in jbd_inode->i_flags */
+#define __JI_COMMIT_RUNNING 0
+/* Commit of the inode data in progress. We use this flag to protect us from
+ * concurrent deletion of inode. We cannot use reference to inode for this
+ * since we cannot afford doing last iput() on behalf of kjournald
+ */
+#define JI_COMMIT_RUNNING (1 << __JI_COMMIT_RUNNING)
+
+/**
+ * struct jbd_inode is the structure linking inodes in ordered mode
+ *   present in a transaction so that we can sync them during commit.
+ */
+struct jbd2_inode {
+        /* Which transaction does this inode belong to? Either the running
+         * transaction or the committing one. [j_list_lock] */
+        transaction_t *i_transaction;
+
+        /* Pointer to the running transaction modifying inode's data in case
+         * there is already a committing transaction touching it. [j_list_lock] */
+        transaction_t *i_next_transaction;
+
+        /* List of inodes in the i_transaction [j_list_lock] */
+        struct list_head i_list;
+
+        /* VFS inode this inode belongs to [constant during the lifetime
+         * of the structure] */
+        struct inode *i_vfs_inode;
+
+        /* Flags of inode [j_list_lock] */
+        unsigned int i_flags;
+};
+
 struct jbd2_revoke_table_s;
 
 /**
@@ -509,24 +543,12 @@ struct transaction_s
         struct journal_head     *t_reserved_list;
 
         /*
-         * Doubly-linked circular list of all buffers under writeout during
-         * commit [j_list_lock]
-         */
-        struct journal_head     *t_locked_list;
-
-        /*
          * Doubly-linked circular list of all metadata buffers owned by this
          * transaction [j_list_lock]
          */
         struct journal_head     *t_buffers;
 
         /*
-         * Doubly-linked circular list of all data buffers still to be
-         * flushed before this transaction can be committed [j_list_lock]
-         */
-        struct journal_head     *t_sync_datalist;
-
-        /*
          * Doubly-linked circular list of all forget buffers (superseded
          * buffers which we can un-checkpoint once this transaction commits)
          * [j_list_lock]
@@ -565,6 +587,12 @@ struct transaction_s
         struct journal_head     *t_log_list;
 
         /*
+         * List of inodes whose data we've modified in data=ordered mode.
+         * [j_list_lock]
+         */
+        struct list_head        t_inode_list;
+
+        /*
          * Protects info related to handles
          */
         spinlock_t              t_handle_lock;
@@ -1004,7 +1032,6 @@ extern int	 jbd2_journal_extend (handle_t *, int nblocks);
 extern int       jbd2_journal_get_write_access(handle_t *, struct buffer_head *);
 extern int       jbd2_journal_get_create_access (handle_t *, struct buffer_head *);
 extern int       jbd2_journal_get_undo_access(handle_t *, struct buffer_head *);
-extern int       jbd2_journal_dirty_data (handle_t *, struct buffer_head *);
 extern int       jbd2_journal_dirty_metadata (handle_t *, struct buffer_head *);
 extern void      jbd2_journal_release_buffer (handle_t *, struct buffer_head *);
 extern int       jbd2_journal_forget (handle_t *, struct buffer_head *);
@@ -1044,6 +1071,10 @@ extern void	   jbd2_journal_ack_err    (journal_t *);
 extern int         jbd2_journal_clear_err  (journal_t *);
 extern int         jbd2_journal_bmap(journal_t *, unsigned long, unsigned long long *);
 extern int         jbd2_journal_force_commit(journal_t *);
+extern int         jbd2_journal_file_inode(handle_t *handle, struct jbd2_inode *inode);
+extern int         jbd2_journal_begin_ordered_truncate(struct jbd2_inode *inode, loff_t new_size);
+extern void        jbd2_journal_init_jbd_inode(struct jbd2_inode *jinode, struct inode *inode);
+extern void        jbd2_journal_release_jbd_inode(journal_t *journal, struct jbd2_inode *jinode);
 
 /*
  * journal_head management
@@ -1179,15 +1210,13 @@ static inline int jbd_space_needed(journal_t *journal)
 
 /* journaling buffer types */
 #define BJ_None         0       /* Not journaled */
-#define BJ_SyncData     1       /* Normal data: flush before commit */
-#define BJ_Metadata     2       /* Normal journaled metadata */
-#define BJ_Forget       3       /* Buffer superseded by this transaction */
-#define BJ_IO           4       /* Buffer is for temporary IO use */
-#define BJ_Shadow       5       /* Buffer contents being shadowed to the log */
-#define BJ_LogCtl       6       /* Buffer contains log descriptors */
-#define BJ_Reserved     7       /* Buffer is reserved for access by journal */
-#define BJ_Locked       8       /* Locked for I/O during commit */
-#define BJ_Types        9
+#define BJ_Metadata     1       /* Normal journaled metadata */
+#define BJ_Forget       2       /* Buffer superseded by this transaction */
+#define BJ_IO           3       /* Buffer is for temporary IO use */
+#define BJ_Shadow       4       /* Buffer contents being shadowed to the log */
+#define BJ_LogCtl       5       /* Buffer contains log descriptors */
+#define BJ_Reserved     6       /* Buffer is reserved for access by journal */
+#define BJ_Types        7
 
 extern int jbd_blocks_per_page(struct inode *inode);
 
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 2e70006c7fa8..f9cd7a513f9c 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -187,9 +187,6 @@ asmlinkage int vprintk(const char *fmt, va_list args)
         __attribute__ ((format (printf, 1, 0)));
 asmlinkage int printk(const char * fmt, ...)
         __attribute__ ((format (printf, 1, 2))) __cold;
-extern int log_buf_get_len(void);
-extern int log_buf_read(int idx);
-extern int log_buf_copy(char *dest, int idx, int len);
 
 extern int printk_ratelimit_jiffies;
 extern int printk_ratelimit_burst;
@@ -205,9 +202,6 @@ static inline int vprintk(const char *s, va_list args) { return 0; }
 static inline int printk(const char *s, ...)
         __attribute__ ((format (printf, 1, 2)));
 static inline int __cold printk(const char *s, ...) { return 0; }
-static inline int log_buf_get_len(void) { return 0; }
-static inline int log_buf_read(int idx) { return 0; }
-static inline int log_buf_copy(char *dest, int idx, int len) { return 0; }
 static inline int printk_ratelimit(void) { return 0; }
 static inline int __printk_ratelimit(int ratelimit_jiffies, \
                                      int ratelimit_burst) { return 0; }
@@ -216,7 +210,7 @@ static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \
                 { return false; }
 #endif
 
-extern void __attribute__((format(printf, 1, 2)))
+extern void asmlinkage __attribute__((format(printf, 1, 2)))
         early_printk(const char *fmt, ...);
 
 unsigned long int_sqrt(unsigned long);
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 1036631ff4fa..04a3556bdea6 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -259,6 +259,10 @@ void recycle_rp_inst(struct kretprobe_instance *ri, struct hlist_head *head);
 struct jprobe;
 struct kretprobe;
 
+static inline struct kprobe *get_kprobe(void *addr)
+{
+        return NULL;
+}
 static inline struct kprobe *kprobe_running(void)
 {
         return NULL;
diff --git a/include/linux/libata.h b/include/linux/libata.h
index e57e5d08312d..5b247b8a6b3b 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -27,6 +27,7 @@
 #define __LINUX_LIBATA_H__
 
 #include <linux/delay.h>
+#include <linux/jiffies.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/scatterlist.h>
@@ -115,7 +116,7 @@ enum {
         /* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */
         ATA_MAX_QUEUE           = 32,
         ATA_TAG_INTERNAL        = ATA_MAX_QUEUE - 1,
-        ATA_SHORT_PAUSE         = (HZ >> 6) + 1,
+        ATA_SHORT_PAUSE         = 16,
 
         ATAPI_MAX_DRAIN         = 16 << 10,
 
@@ -168,6 +169,7 @@ enum {
         ATA_LFLAG_ASSUME_CLASS  = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
         ATA_LFLAG_NO_RETRY      = (1 << 5), /* don't retry this link */
         ATA_LFLAG_DISABLED      = (1 << 6), /* link is disabled */
+        ATA_LFLAG_SW_ACTIVITY   = (1 << 7), /* keep activity stats */
 
         /* struct ata_port flags */
         ATA_FLAG_SLAVE_POSS     = (1 << 0), /* host supports slave dev */
@@ -190,6 +192,10 @@ enum {
         ATA_FLAG_AN             = (1 << 18), /* controller supports AN */
         ATA_FLAG_PMP            = (1 << 19), /* controller supports PMP */
         ATA_FLAG_IPM            = (1 << 20), /* driver can handle IPM */
+        ATA_FLAG_EM             = (1 << 21), /* driver supports enclosure
+                                              * management */
+        ATA_FLAG_SW_ACTIVITY    = (1 << 22), /* driver supports sw activity
+                                              * led */
 
         /* The following flag belongs to ap->pflags but is kept in
          * ap->flags because it's referenced in many LLDs and will be
@@ -234,17 +240,16 @@ enum {
         /* bits 24:31 of host->flags are reserved for LLD specific flags */
 
         /* various lengths of time */
-        ATA_TMOUT_BOOT          = 30 * HZ,      /* heuristic */
-        ATA_TMOUT_BOOT_QUICK    = 7 * HZ,       /* heuristic */
-        ATA_TMOUT_INTERNAL      = 30 * HZ,
-        ATA_TMOUT_INTERNAL_QUICK = 5 * HZ,
+        ATA_TMOUT_BOOT          = 30000,        /* heuristic */
+        ATA_TMOUT_BOOT_QUICK    =  7000,        /* heuristic */
+        ATA_TMOUT_INTERNAL_QUICK = 5000,
 
         /* FIXME: GoVault needs 2s but we can't afford that without
          * parallel probing.  800ms is enough for iVDR disk
          * HHD424020F7SV00.  Increase to 2secs when parallel probing
          * is in place.
          */
-        ATA_TMOUT_FF_WAIT       = 4 * HZ / 5,
+        ATA_TMOUT_FF_WAIT       =  800,
 
         /* Spec mandates to wait for ">= 2ms" before checking status
          * after reset.  We wait 150ms, because that was the magic
@@ -256,14 +261,14 @@ enum {
          *
          * Old drivers/ide uses the 2mS rule and then waits for ready.
          */
-        ATA_WAIT_AFTER_RESET_MSECS = 150,
+        ATA_WAIT_AFTER_RESET    =  150,
 
         /* If PMP is supported, we have to do follow-up SRST.  As some
          * PMPs don't send D2H Reg FIS after hardreset, LLDs are
          * advised to wait only for the following duration before
          * doing SRST.
          */
-        ATA_TMOUT_PMP_SRST_WAIT = 1 * HZ,
+        ATA_TMOUT_PMP_SRST_WAIT = 1000,
 
         /* ATA bus states */
         BUS_UNKNOWN             = 0,
@@ -340,6 +345,11 @@ enum {
 
         SATA_PMP_RW_TIMEOUT     = 3000,         /* PMP read/write timeout */
 
+        /* This should match the actual table size of
+         * ata_eh_cmd_timeout_table in libata-eh.c.
+         */
+        ATA_EH_CMD_TIMEOUT_TABLE_SIZE = 5,
+
         /* Horkage types. May be set by libata or controller on drives
            (some horkage may be drive/controller pair dependant */
 
@@ -441,6 +451,15 @@ enum link_pm {
         MEDIUM_POWER,
 };
 extern struct device_attribute dev_attr_link_power_management_policy;
+extern struct device_attribute dev_attr_em_message_type;
+extern struct device_attribute dev_attr_em_message;
+extern struct device_attribute dev_attr_sw_activity;
+
+enum sw_activity {
+        OFF,
+        BLINK_ON,
+        BLINK_OFF,
+};
 
 #ifdef CONFIG_ATA_SFF
 struct ata_ioports {
@@ -597,10 +616,14 @@ struct ata_eh_info {
 struct ata_eh_context {
         struct ata_eh_info      i;
         int                     tries[ATA_MAX_DEVICES];
+        int                     cmd_timeout_idx[ATA_MAX_DEVICES]
+                                               [ATA_EH_CMD_TIMEOUT_TABLE_SIZE];
         unsigned int            classes[ATA_MAX_DEVICES];
         unsigned int            did_probe_mask;
         unsigned int            saved_ncq_enabled;
         u8                      saved_xfer_mode[ATA_MAX_DEVICES];
+        /* timestamp for the last reset attempt or success */
+        unsigned long           last_reset;
 };
 
 struct ata_acpi_drive
@@ -692,6 +715,7 @@ struct ata_port {
         struct timer_list       fastdrain_timer;
         unsigned long           fastdrain_cnt;
 
+        int                     em_message_type;
         void                    *private_data;
 
 #ifdef CONFIG_ATA_ACPI
@@ -783,6 +807,12 @@ struct ata_port_operations {
         u8   (*bmdma_status)(struct ata_port *ap);
 #endif /* CONFIG_ATA_SFF */
 
+        ssize_t (*em_show)(struct ata_port *ap, char *buf);
+        ssize_t (*em_store)(struct ata_port *ap, const char *message,
+                            size_t size);
+        ssize_t (*sw_activity_show)(struct ata_device *dev, char *buf);
+        ssize_t (*sw_activity_store)(struct ata_device *dev,
+                                     enum sw_activity val);
         /*
          * Obsolete
          */
@@ -895,8 +925,7 @@ extern void ata_host_resume(struct ata_host *host);
 #endif
 extern int ata_ratelimit(void);
 extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
-                             unsigned long interval_msec,
-                             unsigned long timeout_msec);
+                             unsigned long interval, unsigned long timeout);
 extern int atapi_cmd_type(u8 opcode);
 extern void ata_tf_to_fis(const struct ata_taskfile *tf,
                           u8 pmp, int is_cmd, u8 *fis);
@@ -1389,6 +1418,12 @@ static inline int ata_check_ready(u8 status)
         return 0;
 }
 
+static inline unsigned long ata_deadline(unsigned long from_jiffies,
+                                         unsigned long timeout_msecs)
+{
+        return from_jiffies + msecs_to_jiffies(timeout_msecs);
+}
+
 
 /**************************************************************************
  * PMP - drivers/ata/libata-pmp.c
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 9fd1f859021b..56ba37394656 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -4,6 +4,8 @@
 #include <linux/compiler.h>
 #include <asm/linkage.h>
 
+#define notrace __attribute__((no_instrument_function))
+
 #ifdef __cplusplus
 #define CPP_ASMLINKAGE extern "C"
 #else
diff --git a/include/linux/list.h b/include/linux/list.h
index 08cf4f651889..139ec41d9c2e 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -85,65 +85,6 @@ static inline void list_add_tail(struct list_head *new, struct list_head *head)
 }
 
 /*
- * Insert a new entry between two known consecutive entries.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-static inline void __list_add_rcu(struct list_head * new,
-                struct list_head * prev, struct list_head * next)
-{
-        new->next = next;
-        new->prev = prev;
-        smp_wmb();
-        next->prev = new;
-        prev->next = new;
-}
-
-/**
- * list_add_rcu - add a new entry to rcu-protected list
- * @new: new entry to be added
- * @head: list head to add it after
- *
- * Insert a new entry after the specified head.
- * This is good for implementing stacks.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as list_add_rcu()
- * or list_del_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * list_for_each_entry_rcu().
- */
-static inline void list_add_rcu(struct list_head *new, struct list_head *head)
-{
-        __list_add_rcu(new, head, head->next);
-}
-
-/**
- * list_add_tail_rcu - add a new entry to rcu-protected list
- * @new: new entry to be added
- * @head: list head to add it before
- *
- * Insert a new entry before the specified head.
- * This is useful for implementing queues.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as list_add_tail_rcu()
- * or list_del_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * list_for_each_entry_rcu().
- */
-static inline void list_add_tail_rcu(struct list_head *new,
-                                        struct list_head *head)
-{
-        __list_add_rcu(new, head->prev, head);
-}
-
-/*
  * Delete a list entry by making the prev/next entries
  * point to each other.
  *
@@ -174,36 +115,6 @@ extern void list_del(struct list_head *entry);
 #endif
 
 /**
- * list_del_rcu - deletes entry from list without re-initialization
- * @entry: the element to delete from the list.
- *
- * Note: list_empty() on entry does not return true after this,
- * the entry is in an undefined state. It is useful for RCU based
- * lockfree traversal.
- *
- * In particular, it means that we can not poison the forward
- * pointers that may still be used for walking the list.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as list_del_rcu()
- * or list_add_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * list_for_each_entry_rcu().
- *
- * Note that the caller is not permitted to immediately free
- * the newly deleted entry.  Instead, either synchronize_rcu()
- * or call_rcu() must be used to defer freeing until an RCU
- * grace period has elapsed.
- */
-static inline void list_del_rcu(struct list_head *entry)
-{
-        __list_del(entry->prev, entry->next);
-        entry->prev = LIST_POISON2;
-}
-
-/**
  * list_replace - replace old entry by new one
  * @old : the element to be replaced
  * @new : the new element to insert
@@ -227,25 +138,6 @@ static inline void list_replace_init(struct list_head *old,
 }
 
 /**
- * list_replace_rcu - replace old entry by new one
- * @old : the element to be replaced
- * @new : the new element to insert
- *
- * The @old entry will be replaced with the @new entry atomically.
- * Note: @old should not be empty.
- */
-static inline void list_replace_rcu(struct list_head *old,
-                                struct list_head *new)
-{
-        new->next = old->next;
-        new->prev = old->prev;
-        smp_wmb();
-        new->next->prev = new;
-        new->prev->next = new;
-        old->prev = LIST_POISON2;
-}
-
-/**
  * list_del_init - deletes entry from list and reinitialize it.
  * @entry: the element to delete from the list.
  */
@@ -369,62 +261,6 @@ static inline void list_splice_init(struct list_head *list,
 }
 
 /**
- * list_splice_init_rcu - splice an RCU-protected list into an existing list.
- * @list:       the RCU-protected list to splice
- * @head:       the place in the list to splice the first list into
- * @sync:       function to sync: synchronize_rcu(), synchronize_sched(), ...
- *
- * @head can be RCU-read traversed concurrently with this function.
- *
- * Note that this function blocks.
- *
- * Important note: the caller must take whatever action is necessary to
- *      prevent any other updates to @head.  In principle, it is possible
- *      to modify the list as soon as sync() begins execution.
- *      If this sort of thing becomes necessary, an alternative version
- *      based on call_rcu() could be created.  But only if -really-
- *      needed -- there is no shortage of RCU API members.
- */
-static inline void list_splice_init_rcu(struct list_head *list,
-                                        struct list_head *head,
-                                        void (*sync)(void))
-{
-        struct list_head *first = list->next;
-        struct list_head *last = list->prev;
-        struct list_head *at = head->next;
-
-        if (list_empty(head))
-                return;
-
-        /* "first" and "last" tracking list, so initialize it. */
-
-        INIT_LIST_HEAD(list);
-
-        /*
-         * At this point, the list body still points to the source list.
-         * Wait for any readers to finish using the list before splicing
-         * the list body into the new list.  Any new readers will see
-         * an empty list.
-         */
-
-        sync();
-
-        /*
-         * Readers are finished with the source list, so perform splice.
-         * The order is important if the new list is global and accessible
-         * to concurrent RCU readers.  Note that RCU readers are not
-         * permitted to traverse the prev pointers without excluding
-         * this function.
-         */
-
-        last->next = at;
-        smp_wmb();
-        head->next = first;
-        first->prev = head;
-        at->prev = last;
-}
-
-/**
  * list_entry - get the struct for this entry
  * @ptr:        the &struct list_head pointer.
  * @type:       the type of the struct this is embedded in.
@@ -629,57 +465,6 @@ static inline void list_splice_init_rcu(struct list_head *list,
              &pos->member != (head);                                    \
              pos = n, n = list_entry(n->member.prev, typeof(*n), member))
 
-/**
- * list_for_each_rcu    -       iterate over an rcu-protected list
- * @pos:        the &struct list_head to use as a loop cursor.
- * @head:       the head for your list.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as list_add_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define list_for_each_rcu(pos, head) \
-        for (pos = rcu_dereference((head)->next); \
-                prefetch(pos->next), pos != (head); \
-                pos = rcu_dereference(pos->next))
-
-#define __list_for_each_rcu(pos, head) \
-        for (pos = rcu_dereference((head)->next); \
-                pos != (head); \
-                pos = rcu_dereference(pos->next))
-
-/**
- * list_for_each_entry_rcu      -       iterate over rcu list of given type
- * @pos:        the type * to use as a loop cursor.
- * @head:       the head for your list.
- * @member:     the name of the list_struct within the struct.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as list_add_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define list_for_each_entry_rcu(pos, head, member) \
-        for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \
-                prefetch(pos->member.next), &pos->member != (head); \
-                pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member))
-
-
-/**
- * list_for_each_continue_rcu
- * @pos:        the &struct list_head to use as a loop cursor.
- * @head:       the head for your list.
- *
- * Iterate over an rcu-protected list, continuing after current point.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as list_add_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define list_for_each_continue_rcu(pos, head) \
-        for ((pos) = rcu_dereference((pos)->next); \
-                prefetch((pos)->next), (pos) != (head); \
-                (pos) = rcu_dereference((pos)->next))
-
 /*
  * Double linked lists with a single pointer list head.
  * Mostly useful for hash tables where the two pointer list head is
@@ -730,31 +515,6 @@ static inline void hlist_del(struct hlist_node *n)
         n->pprev = LIST_POISON2;
 }
 
-/**
- * hlist_del_rcu - deletes entry from hash list without re-initialization
- * @n: the element to delete from the hash list.
- *
- * Note: list_unhashed() on entry does not return true after this,
- * the entry is in an undefined state. It is useful for RCU based
- * lockfree traversal.
- *
- * In particular, it means that we can not poison the forward
- * pointers that may still be used for walking the hash list.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as hlist_add_head_rcu()
- * or hlist_del_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * hlist_for_each_entry().
- */
-static inline void hlist_del_rcu(struct hlist_node *n)
-{
-        __hlist_del(n);
-        n->pprev = LIST_POISON2;
-}
-
 static inline void hlist_del_init(struct hlist_node *n)
 {
         if (!hlist_unhashed(n)) {
@@ -763,27 +523,6 @@ static inline void hlist_del_init(struct hlist_node *n)
         }
 }
 
-/**
- * hlist_replace_rcu - replace old entry by new one
- * @old : the element to be replaced
- * @new : the new element to insert
- *
- * The @old entry will be replaced with the @new entry atomically.
- */
-static inline void hlist_replace_rcu(struct hlist_node *old,
-                                        struct hlist_node *new)
-{
-        struct hlist_node *next = old->next;
-
-        new->next = next;
-        new->pprev = old->pprev;
-        smp_wmb();
-        if (next)
-                new->next->pprev = &new->next;
-        *new->pprev = new;
-        old->pprev = LIST_POISON2;
-}
-
 static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
 {
         struct hlist_node *first = h->first;
@@ -794,38 +533,6 @@ static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
         n->pprev = &h->first;
 }
 
-
-/**
- * hlist_add_head_rcu
- * @n: the element to add to the hash list.
- * @h: the list to add to.
- *
- * Description:
- * Adds the specified element to the specified hlist,
- * while permitting racing traversals.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as hlist_add_head_rcu()
- * or hlist_del_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * hlist_for_each_entry_rcu(), used to prevent memory-consistency
- * problems on Alpha CPUs.  Regardless of the type of CPU, the
- * list-traversal primitive must be guarded by rcu_read_lock().
- */
-static inline void hlist_add_head_rcu(struct hlist_node *n,
-                                        struct hlist_head *h)
-{
-        struct hlist_node *first = h->first;
-        n->next = first;
-        n->pprev = &h->first;
-        smp_wmb();
-        if (first)
-                first->pprev = &n->next;
-        h->first = n;
-}
-
 /* next must be != NULL */
 static inline void hlist_add_before(struct hlist_node *n,
                                         struct hlist_node *next)
@@ -847,63 +554,6 @@ static inline void hlist_add_after(struct hlist_node *n,
                 next->next->pprev  = &next->next;
 }
 
-/**
- * hlist_add_before_rcu
- * @n: the new element to add to the hash list.
- * @next: the existing element to add the new element before.
- *
- * Description:
- * Adds the specified element to the specified hlist
- * before the specified node while permitting racing traversals.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as hlist_add_head_rcu()
- * or hlist_del_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * hlist_for_each_entry_rcu(), used to prevent memory-consistency
- * problems on Alpha CPUs.
- */
-static inline void hlist_add_before_rcu(struct hlist_node *n,
-                                        struct hlist_node *next)
-{
-        n->pprev = next->pprev;
-        n->next = next;
-        smp_wmb();
-        next->pprev = &n->next;
-        *(n->pprev) = n;
-}
-
-/**
- * hlist_add_after_rcu
- * @prev: the existing element to add the new element after.
- * @n: the new element to add to the hash list.
- *
- * Description:
- * Adds the specified element to the specified hlist
- * after the specified node while permitting racing traversals.
- *
- * The caller must take whatever precautions are necessary
- * (such as holding appropriate locks) to avoid racing
- * with another list-mutation primitive, such as hlist_add_head_rcu()
- * or hlist_del_rcu(), running on this same list.
- * However, it is perfectly legal to run concurrently with
- * the _rcu list-traversal primitives, such as
- * hlist_for_each_entry_rcu(), used to prevent memory-consistency
- * problems on Alpha CPUs.
- */
-static inline void hlist_add_after_rcu(struct hlist_node *prev,
-                                       struct hlist_node *n)
-{
-        n->next = prev->next;
-        n->pprev = &prev->next;
-        smp_wmb();
-        prev->next = n;
-        if (n->next)
-                n->next->pprev = &n->next;
-}
-
 #define hlist_entry(ptr, type, member) container_of(ptr,type,member)
 
 #define hlist_for_each(pos, head) \
@@ -964,21 +614,4 @@ static inline void hlist_add_after_rcu(struct hlist_node *prev,
                 ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
              pos = n)
 
-/**
- * hlist_for_each_entry_rcu - iterate over rcu list of given type
- * @tpos:       the type * to use as a loop cursor.
- * @pos:        the &struct hlist_node to use as a loop cursor.
- * @head:       the head for your list.
- * @member:     the name of the hlist_node within the struct.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as hlist_add_head_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define hlist_for_each_entry_rcu(tpos, pos, head, member)                \
-        for (pos = rcu_dereference((head)->first);                       \
-                pos && ({ prefetch(pos->next); 1;}) &&                   \
-                ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
-             pos = rcu_dereference(pos->next))
-
 #endif
diff --git a/include/linux/lm_interface.h b/include/linux/lm_interface.h
index f274997bc283..2ed8fa1b762b 100644
--- a/include/linux/lm_interface.h
+++ b/include/linux/lm_interface.h
@@ -122,11 +122,9 @@ typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
  */
 
 #define LM_OUT_ST_MASK          0x00000003
-#define LM_OUT_CACHEABLE        0x00000004
 #define LM_OUT_CANCELED         0x00000008
 #define LM_OUT_ASYNC            0x00000080
 #define LM_OUT_ERROR            0x00000100
-#define LM_OUT_CONV_DEADLK      0x00000200
 
 /*
  * lm_callback_t types
@@ -138,9 +136,6 @@ typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
  * LM_CB_NEED_RECOVERY
  * The given journal needs to be recovered.
  *
- * LM_CB_DROPLOCKS
- * Reduce the number of cached locks.
- *
  * LM_CB_ASYNC
  * The given lock has been granted.
  */
@@ -149,7 +144,6 @@ typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
 #define LM_CB_NEED_D            258
 #define LM_CB_NEED_S            259
 #define LM_CB_NEED_RECOVERY     260
-#define LM_CB_DROPLOCKS         261
 #define LM_CB_ASYNC             262
 
 /*
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 4c4d236ded18..2486eb4edbf1 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -182,6 +182,9 @@ struct lock_list {
  * We record lock dependency chains, so that we can cache them:
  */
 struct lock_chain {
+        u8                              irq_context;
+        u8                              depth;
+        u16                             base;
         struct list_head                entry;
         u64                             chain_key;
 };
@@ -276,14 +279,6 @@ extern void lockdep_init_map(struct lockdep_map *lock, const char *name,
                                  (lock)->dep_map.key, sub)
 
 /*
- * To initialize a lockdep_map statically use this macro.
- * Note that _name must not be NULL.
- */
-#define STATIC_LOCKDEP_MAP_INIT(_name, _key) \
-        { .name = (_name), .key = (void *)(_key), }
-
-
-/*
  * Acquire a lock.
  *
  * Values for "read":
diff --git a/include/linux/marker.h b/include/linux/marker.h
index 430f6adf9762..1290653f9241 100644
--- a/include/linux/marker.h
+++ b/include/linux/marker.h
@@ -44,8 +44,8 @@ struct marker {
                                  */
         char state;             /* Marker state. */
         char ptype;             /* probe type : 0 : single, 1 : multi */
-        void (*call)(const struct marker *mdata,        /* Probe wrapper */
-                void *call_private, const char *fmt, ...);
+                                /* Probe wrapper */
+        void (*call)(const struct marker *mdata, void *call_private, ...);
         struct marker_probe_closure single;
         struct marker_probe_closure *multi;
 } __attribute__((aligned(8)));
@@ -58,8 +58,12 @@ struct marker {
  * Make sure the alignment of the structure in the __markers section will
  * not add unwanted padding between the beginning of the section and the
  * structure. Force alignment to the same alignment as the section start.
+ *
+ * The "generic" argument controls which marker enabling mechanism must be used.
+ * If generic is true, a variable read is used.
+ * If generic is false, immediate values are used.
  */
-#define __trace_mark(name, call_private, format, args...)               \
+#define __trace_mark(generic, name, call_private, format, args...)      \
         do {                                                            \
                 static const char __mstrtab_##name[]                    \
                 __attribute__((section("__markers_strings")))           \
@@ -72,15 +76,14 @@ struct marker {
                 __mark_check_format(format, ## args);                   \
                 if (unlikely(__mark_##name.state)) {                    \
                         (*__mark_##name.call)                           \
-                                (&__mark_##name, call_private,          \
-                                format, ## args);                       \
+                                (&__mark_##name, call_private, ## args);\
                 }                                                       \
         } while (0)
 
 extern void marker_update_probe_range(struct marker *begin,
         struct marker *end);
 #else /* !CONFIG_MARKERS */
-#define __trace_mark(name, call_private, format, args...) \
+#define __trace_mark(generic, name, call_private, format, args...) \
                 __mark_check_format(format, ## args)
 static inline void marker_update_probe_range(struct marker *begin,
         struct marker *end)
@@ -88,15 +91,30 @@ static inline void marker_update_probe_range(struct marker *begin,
 #endif /* CONFIG_MARKERS */
 
 /**
- * trace_mark - Marker
+ * trace_mark - Marker using code patching
  * @name: marker name, not quoted.
  * @format: format string
  * @args...: variable argument list
  *
- * Places a marker.
+ * Places a marker using optimized code patching technique (imv_read())
+ * to be enabled when immediate values are present.
  */
 #define trace_mark(name, format, args...) \
-        __trace_mark(name, NULL, format, ## args)
+        __trace_mark(0, name, NULL, format, ## args)
+
+/**
+ * _trace_mark - Marker using variable read
+ * @name: marker name, not quoted.
+ * @format: format string
+ * @args...: variable argument list
+ *
+ * Places a marker using a standard memory read (_imv_read()) to be
+ * enabled. Should be used for markers in code paths where instruction
+ * modification based enabling is not welcome. (__init and __exit functions,
+ * lockdep, some traps, printk).
+ */
+#define _trace_mark(name, format, args...) \
+        __trace_mark(1, name, NULL, format, ## args)
 
 /**
  * MARK_NOARGS - Format string for a marker with no argument.
@@ -117,9 +135,9 @@ static inline void __printf(1, 2) ___mark_check_format(const char *fmt, ...)
 extern marker_probe_func __mark_empty_function;
 
 extern void marker_probe_cb(const struct marker *mdata,
-        void *call_private, const char *fmt, ...);
+        void *call_private, ...);
 extern void marker_probe_cb_noarg(const struct marker *mdata,
-        void *call_private, const char *fmt, ...);
+        void *call_private, ...);
 
 /*
  * Connect a probe to a marker.
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index a744383d16e9..81b3dd5206e0 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -398,7 +398,8 @@ int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_waterm
 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
 
-int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
+int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
+                          int block_mcast_loopback);
 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
 
 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
diff --git a/include/linux/mm.h b/include/linux/mm.h
index cf1cd3a2ed78..2128ef7780c6 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -108,6 +108,7 @@ extern unsigned int kobjsize(const void *objp);
 
 #define VM_CAN_NONLINEAR 0x08000000     /* Has ->fault & does nonlinear pages */
 #define VM_MIXEDMAP     0x10000000      /* Can contain "struct page" and pure PFN pages */
+#define VM_SAO          0x20000000      /* Strong Access Ordering (powerpc) */
 
 #ifndef VM_STACK_DEFAULT_FLAGS          /* arch can override this */
 #define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS
diff --git a/include/linux/mman.h b/include/linux/mman.h
index dab8892e6ff1..30d1073bac3b 100644
--- a/include/linux/mman.h
+++ b/include/linux/mman.h
@@ -34,6 +34,32 @@ static inline void vm_unacct_memory(long pages)
 }
 
 /*
+ * Allow architectures to handle additional protection bits
+ */
+
+#ifndef arch_calc_vm_prot_bits
+#define arch_calc_vm_prot_bits(prot) 0
+#endif
+
+#ifndef arch_vm_get_page_prot
+#define arch_vm_get_page_prot(vm_flags) __pgprot(0)
+#endif
+
+#ifndef arch_validate_prot
+/*
+ * This is called from mprotect().  PROT_GROWSDOWN and PROT_GROWSUP have
+ * already been masked out.
+ *
+ * Returns true if the prot flags are valid
+ */
+static inline int arch_validate_prot(unsigned long prot)
+{
+        return (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM)) == 0;
+}
+#define arch_validate_prot arch_validate_prot
+#endif
+
+/*
  * Optimisation macro.  It is equivalent to:
  *      (x & bit1) ? bit2 : 0
  * but this version is faster.
@@ -51,7 +77,8 @@ calc_vm_prot_bits(unsigned long prot)
 {
         return _calc_vm_trans(prot, PROT_READ,  VM_READ ) |
                _calc_vm_trans(prot, PROT_WRITE, VM_WRITE) |
-               _calc_vm_trans(prot, PROT_EXEC,  VM_EXEC );
+               _calc_vm_trans(prot, PROT_EXEC,  VM_EXEC) |
+               arch_calc_vm_prot_bits(prot);
 }
 
 /*
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index d0c3abed74c2..143cebf0586f 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -135,6 +135,7 @@ extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
         struct mmc_command *, int);
 
 extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *);
+extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int);
 
 extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
 extern void mmc_release_host(struct mmc_host *host);
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 7ab962fa1d73..10a2080086ca 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -51,8 +51,30 @@ struct mmc_ios {
 
 struct mmc_host_ops {
         void    (*request)(struct mmc_host *host, struct mmc_request *req);
+        /*
+         * Avoid calling these three functions too often or in a "fast path",
+         * since underlaying controller might implement them in an expensive
+         * and/or slow way.
+         *
+         * Also note that these functions might sleep, so don't call them
+         * in the atomic contexts!
+         *
+         * Return values for the get_ro callback should be:
+         *   0 for a read/write card
+         *   1 for a read-only card
+         *   -ENOSYS when not supported (equal to NULL callback)
+         *   or a negative errno value when something bad happened
+         *
+         * Return values for the get_ro callback should be:
+         *   0 for a absent card
+         *   1 for a present card
+         *   -ENOSYS when not supported (equal to NULL callback)
+         *   or a negative errno value when something bad happened
+         */
         void    (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
         int     (*get_ro)(struct mmc_host *host);
+        int     (*get_cd)(struct mmc_host *host);
+
         void    (*enable_sdio_irq)(struct mmc_host *host, int enable);
 };
 
@@ -89,11 +111,11 @@ struct mmc_host {
         unsigned long           caps;           /* Host capabilities */
 
 #define MMC_CAP_4_BIT_DATA      (1 << 0)        /* Can the host do 4 bit transfers */
-#define MMC_CAP_MULTIWRITE      (1 << 1)        /* Can accurately report bytes sent to card on error */
-#define MMC_CAP_MMC_HIGHSPEED   (1 << 2)        /* Can do MMC high-speed timing */
-#define MMC_CAP_SD_HIGHSPEED    (1 << 3)        /* Can do SD high-speed timing */
-#define MMC_CAP_SDIO_IRQ        (1 << 4)        /* Can signal pending SDIO IRQs */
-#define MMC_CAP_SPI             (1 << 5)        /* Talks only SPI protocols */
+#define MMC_CAP_MMC_HIGHSPEED   (1 << 1)        /* Can do MMC high-speed timing */
+#define MMC_CAP_SD_HIGHSPEED    (1 << 2)        /* Can do SD high-speed timing */
+#define MMC_CAP_SDIO_IRQ        (1 << 3)        /* Can signal pending SDIO IRQs */
+#define MMC_CAP_SPI             (1 << 4)        /* Talks only SPI protocols */
+#define MMC_CAP_NEEDS_POLL      (1 << 5)        /* Needs polling for card-detection */
 
         /* host specific block data */
         unsigned int            max_seg_size;   /* see blk_queue_max_segment_size */
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 4236fbf0b6fb..14b81f3e5232 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -16,7 +16,6 @@
  * Based strongly on code by:
  *
  * Author: Yong-iL Joh <tolkien@mizi.com>
- * Date  : $Date: 2002/06/18 12:37:30 $
  *
  * Author:  Andrew Christian
  *          15 May 2002
diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h
index b050f4d7b41f..07bee4a0d457 100644
--- a/include/linux/mmc/sdio_func.h
+++ b/include/linux/mmc/sdio_func.h
@@ -1,7 +1,7 @@
 /*
  *  include/linux/mmc/sdio_func.h
  *
- *  Copyright 2007 Pierre Ossman
+ *  Copyright 2007-2008 Pierre Ossman
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -46,6 +46,8 @@ struct sdio_func {
         unsigned                max_blksize;    /* maximum block size */
         unsigned                cur_blksize;    /* current block size */
 
+        unsigned                enable_timeout; /* max enable timeout in msec */
+
         unsigned int            state;          /* function state */
 #define SDIO_STATE_PRESENT      (1<<0)          /* present in sysfs */
 
@@ -120,23 +122,22 @@ extern int sdio_set_block_size(struct sdio_func *func, unsigned blksz);
 extern int sdio_claim_irq(struct sdio_func *func, sdio_irq_handler_t *handler);
 extern int sdio_release_irq(struct sdio_func *func);
 
-extern unsigned char sdio_readb(struct sdio_func *func,
-        unsigned int addr, int *err_ret);
-extern unsigned short sdio_readw(struct sdio_func *func,
-        unsigned int addr, int *err_ret);
-extern unsigned long sdio_readl(struct sdio_func *func,
-        unsigned int addr, int *err_ret);
+extern unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz);
+
+extern u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret);
+extern u16 sdio_readw(struct sdio_func *func, unsigned int addr, int *err_ret);
+extern u32 sdio_readl(struct sdio_func *func, unsigned int addr, int *err_ret);
 
 extern int sdio_memcpy_fromio(struct sdio_func *func, void *dst,
         unsigned int addr, int count);
 extern int sdio_readsb(struct sdio_func *func, void *dst,
         unsigned int addr, int count);
 
-extern void sdio_writeb(struct sdio_func *func, unsigned char b,
+extern void sdio_writeb(struct sdio_func *func, u8 b,
         unsigned int addr, int *err_ret);
-extern void sdio_writew(struct sdio_func *func, unsigned short b,
+extern void sdio_writew(struct sdio_func *func, u16 b,
         unsigned int addr, int *err_ret);
-extern void sdio_writel(struct sdio_func *func, unsigned long b,
+extern void sdio_writel(struct sdio_func *func, u32 b,
         unsigned int addr, int *err_ret);
 
 extern int sdio_memcpy_toio(struct sdio_func *func, unsigned int addr,
diff --git a/include/linux/mmiotrace.h b/include/linux/mmiotrace.h
new file mode 100644
index 000000000000..61d19e1b7a0b
--- /dev/null
+++ b/include/linux/mmiotrace.h
@@ -0,0 +1,85 @@
+#ifndef MMIOTRACE_H
+#define MMIOTRACE_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+struct kmmio_probe;
+struct pt_regs;
+
+typedef void (*kmmio_pre_handler_t)(struct kmmio_probe *,
+                                struct pt_regs *, unsigned long addr);
+typedef void (*kmmio_post_handler_t)(struct kmmio_probe *,
+                                unsigned long condition, struct pt_regs *);
+
+struct kmmio_probe {
+        struct list_head list; /* kmmio internal list */
+        unsigned long addr; /* start location of the probe point */
+        unsigned long len; /* length of the probe region */
+        kmmio_pre_handler_t pre_handler; /* Called before addr is executed. */
+        kmmio_post_handler_t post_handler; /* Called after addr is executed */
+        void *private;
+};
+
+/* kmmio is active by some kmmio_probes? */
+static inline int is_kmmio_active(void)
+{
+        extern unsigned int kmmio_count;
+        return kmmio_count;
+}
+
+extern int register_kmmio_probe(struct kmmio_probe *p);
+extern void unregister_kmmio_probe(struct kmmio_probe *p);
+
+/* Called from page fault handler. */
+extern int kmmio_handler(struct pt_regs *regs, unsigned long addr);
+
+/* Called from ioremap.c */
+#ifdef CONFIG_MMIOTRACE
+extern void mmiotrace_ioremap(resource_size_t offset, unsigned long size,
+                                                        void __iomem *addr);
+extern void mmiotrace_iounmap(volatile void __iomem *addr);
+#else
+static inline void mmiotrace_ioremap(resource_size_t offset,
+                                        unsigned long size, void __iomem *addr)
+{
+}
+
+static inline void mmiotrace_iounmap(volatile void __iomem *addr)
+{
+}
+#endif /* CONFIG_MMIOTRACE_HOOKS */
+
+enum mm_io_opcode {
+        MMIO_READ = 0x1,     /* struct mmiotrace_rw */
+        MMIO_WRITE = 0x2,    /* struct mmiotrace_rw */
+        MMIO_PROBE = 0x3,    /* struct mmiotrace_map */
+        MMIO_UNPROBE = 0x4,  /* struct mmiotrace_map */
+        MMIO_MARKER = 0x5,   /* raw char data */
+        MMIO_UNKNOWN_OP = 0x6, /* struct mmiotrace_rw */
+};
+
+struct mmiotrace_rw {
+        resource_size_t phys;   /* PCI address of register */
+        unsigned long value;
+        unsigned long pc;       /* optional program counter */
+        int map_id;
+        unsigned char opcode;   /* one of MMIO_{READ,WRITE,UNKNOWN_OP} */
+        unsigned char width;    /* size of register access in bytes */
+};
+
+struct mmiotrace_map {
+        resource_size_t phys;   /* base address in PCI space */
+        unsigned long virt;     /* base virtual address */
+        unsigned long len;      /* mapping size */
+        int map_id;
+        unsigned char opcode;   /* MMIO_PROBE or MMIO_UNPROBE */
+};
+
+/* in kernel/trace/trace_mmiotrace.c */
+extern void enable_mmiotrace(void);
+extern void disable_mmiotrace(void);
+extern void mmio_trace_rw(struct mmiotrace_rw *rw);
+extern void mmio_trace_mapping(struct mmiotrace_map *map);
+
+#endif /* MMIOTRACE_H */
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 69b2342d5ebb..c4db5827963d 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -159,6 +159,15 @@ struct ap_device_id {
 
 #define AP_DEVICE_ID_MATCH_DEVICE_TYPE          0x01
 
+/* s390 css bus devices (subchannels) */
+struct css_device_id {
+        __u8 match_flags;
+        __u8 type; /* subchannel type */
+        __u16 pad2;
+        __u32 pad3;
+        kernel_ulong_t driver_data;
+};
+
 #define ACPI_ID_LEN     16 /* only 9 bytes needed here, 16 bytes are used */
                            /* to workaround crosscompile issues */
 
diff --git a/include/linux/mpage.h b/include/linux/mpage.h
index 068a0c9946af..5c42821da2d1 100644
--- a/include/linux/mpage.h
+++ b/include/linux/mpage.h
@@ -11,11 +11,21 @@
  */
 #ifdef CONFIG_BLOCK
 
+struct mpage_data {
+        struct bio *bio;
+        sector_t last_block_in_bio;
+        get_block_t *get_block;
+        unsigned use_writepage;
+};
+
 struct writeback_control;
 
+struct bio *mpage_bio_submit(int rw, struct bio *bio);
 int mpage_readpages(struct address_space *mapping, struct list_head *pages,
                                 unsigned nr_pages, get_block_t get_block);
 int mpage_readpage(struct page *page, get_block_t get_block);
+int __mpage_writepage(struct page *page, struct writeback_control *wbc,
+                      void *data);
 int mpage_writepages(struct address_space *mapping,
                 struct writeback_control *wbc, get_block_t get_block);
 int mpage_writepage(struct page *page, get_block_t *get_block,
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 27d6a8d98cef..29d261918734 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -12,9 +12,19 @@
 #include <linux/magic.h>
 
 /* Default timeout values */
+#define NFS_DEF_UDP_TIMEO       (11)
+#define NFS_DEF_UDP_RETRANS     (3)
+#define NFS_DEF_TCP_TIMEO       (600)
+#define NFS_DEF_TCP_RETRANS     (2)
+
 #define NFS_MAX_UDP_TIMEOUT     (60*HZ)
 #define NFS_MAX_TCP_TIMEOUT     (600*HZ)
 
+#define NFS_DEF_ACREGMIN        (3)
+#define NFS_DEF_ACREGMAX        (60)
+#define NFS_DEF_ACDIRMIN        (30)
+#define NFS_DEF_ACDIRMAX        (60)
+
 /*
  * When flushing a cluster of dirty pages, there can be different
  * strategies:
diff --git a/include/linux/nfs_iostat.h b/include/linux/nfs_iostat.h
new file mode 100644
index 000000000000..1cb9a3fed2b3
--- /dev/null
+++ b/include/linux/nfs_iostat.h
@@ -0,0 +1,119 @@
+/*
+ *  User-space visible declarations for NFS client per-mount
+ *  point statistics
+ *
+ *  Copyright (C) 2005, 2006 Chuck Lever <cel@netapp.com>
+ *
+ *  NFS client per-mount statistics provide information about the
+ *  health of the NFS client and the health of each NFS mount point.
+ *  Generally these are not for detailed problem diagnosis, but
+ *  simply to indicate that there is a problem.
+ *
+ *  These counters are not meant to be human-readable, but are meant
+ *  to be integrated into system monitoring tools such as "sar" and
+ *  "iostat".  As such, the counters are sampled by the tools over
+ *  time, and are never zeroed after a file system is mounted.
+ *  Moving averages can be computed by the tools by taking the
+ *  difference between two instantaneous samples  and dividing that
+ *  by the time between the samples.
+ */
+
+#ifndef _LINUX_NFS_IOSTAT
+#define _LINUX_NFS_IOSTAT
+
+#define NFS_IOSTAT_VERS         "1.0"
+
+/*
+ * NFS byte counters
+ *
+ * 1.  SERVER - the number of payload bytes read from or written
+ *     to the server by the NFS client via an NFS READ or WRITE
+ *     request.
+ *
+ * 2.  NORMAL - the number of bytes read or written by applications
+ *     via the read(2) and write(2) system call interfaces.
+ *
+ * 3.  DIRECT - the number of bytes read or written from files
+ *     opened with the O_DIRECT flag.
+ *
+ * These counters give a view of the data throughput into and out
+ * of the NFS client.  Comparing the number of bytes requested by
+ * an application with the number of bytes the client requests from
+ * the server can provide an indication of client efficiency
+ * (per-op, cache hits, etc).
+ *
+ * These counters can also help characterize which access methods
+ * are in use.  DIRECT by itself shows whether there is any O_DIRECT
+ * traffic.  NORMAL + DIRECT shows how much data is going through
+ * the system call interface.  A large amount of SERVER traffic
+ * without much NORMAL or DIRECT traffic shows that applications
+ * are using mapped files.
+ *
+ * NFS page counters
+ *
+ * These count the number of pages read or written via nfs_readpage(),
+ * nfs_readpages(), or their write equivalents.
+ *
+ * NB: When adding new byte counters, please include the measured
+ * units in the name of each byte counter to help users of this
+ * interface determine what exactly is being counted.
+ */
+enum nfs_stat_bytecounters {
+        NFSIOS_NORMALREADBYTES = 0,
+        NFSIOS_NORMALWRITTENBYTES,
+        NFSIOS_DIRECTREADBYTES,
+        NFSIOS_DIRECTWRITTENBYTES,
+        NFSIOS_SERVERREADBYTES,
+        NFSIOS_SERVERWRITTENBYTES,
+        NFSIOS_READPAGES,
+        NFSIOS_WRITEPAGES,
+        __NFSIOS_BYTESMAX,
+};
+
+/*
+ * NFS event counters
+ *
+ * These counters provide a low-overhead way of monitoring client
+ * activity without enabling NFS trace debugging.  The counters
+ * show the rate at which VFS requests are made, and how often the
+ * client invalidates its data and attribute caches.  This allows
+ * system administrators to monitor such things as how close-to-open
+ * is working, and answer questions such as "why are there so many
+ * GETATTR requests on the wire?"
+ *
+ * They also count anamolous events such as short reads and writes,
+ * silly renames due to close-after-delete, and operations that
+ * change the size of a file (such operations can often be the
+ * source of data corruption if applications aren't using file
+ * locking properly).
+ */
+enum nfs_stat_eventcounters {
+        NFSIOS_INODEREVALIDATE = 0,
+        NFSIOS_DENTRYREVALIDATE,
+        NFSIOS_DATAINVALIDATE,
+        NFSIOS_ATTRINVALIDATE,
+        NFSIOS_VFSOPEN,
+        NFSIOS_VFSLOOKUP,
+        NFSIOS_VFSACCESS,
+        NFSIOS_VFSUPDATEPAGE,
+        NFSIOS_VFSREADPAGE,
+        NFSIOS_VFSREADPAGES,
+        NFSIOS_VFSWRITEPAGE,
+        NFSIOS_VFSWRITEPAGES,
+        NFSIOS_VFSGETDENTS,
+        NFSIOS_VFSSETATTR,
+        NFSIOS_VFSFLUSH,
+        NFSIOS_VFSFSYNC,
+        NFSIOS_VFSLOCK,
+        NFSIOS_VFSRELEASE,
+        NFSIOS_CONGESTIONWAIT,
+        NFSIOS_SETATTRTRUNC,
+        NFSIOS_EXTENDWRITE,
+        NFSIOS_SILLYRENAME,
+        NFSIOS_SHORTREAD,
+        NFSIOS_SHORTWRITE,
+        NFSIOS_DELAY,
+        __NFSIOS_COUNTSMAX,
+};
+
+#endif  /* _LINUX_NFS_IOSTAT */
diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h
index a1676e19e491..3c60685d972b 100644
--- a/include/linux/nfs_page.h
+++ b/include/linux/nfs_page.h
@@ -27,9 +27,12 @@
 /*
  * Valid flags for a dirty buffer
  */
-#define PG_BUSY                 0
-#define PG_NEED_COMMIT          1
-#define PG_NEED_RESCHED         2
+enum {
+        PG_BUSY = 0,
+        PG_CLEAN,
+        PG_NEED_COMMIT,
+        PG_NEED_RESCHED,
+};
 
 struct nfs_inode;
 struct nfs_page {
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 24263bb8e0be..8c77c11224d1 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -829,9 +829,8 @@ struct nfs_rpc_ops {
         int     (*write_done)  (struct rpc_task *, struct nfs_write_data *);
         void    (*commit_setup) (struct nfs_write_data *, struct rpc_message *);
         int     (*commit_done) (struct rpc_task *, struct nfs_write_data *);
-        int     (*file_open)   (struct inode *, struct file *);
-        int     (*file_release) (struct inode *, struct file *);
         int     (*lock)(struct file *, int, struct file_lock *);
+        int     (*lock_check_bounds)(const struct file_lock *);
         void    (*clear_acl_cache)(struct inode *);
 };
 
diff --git a/include/linux/of_device.h b/include/linux/of_device.h
index afe338217d91..d3a74e00a3e1 100644
--- a/include/linux/of_device.h
+++ b/include/linux/of_device.h
@@ -24,4 +24,7 @@ static inline void of_device_free(struct of_device *dev)
         of_release_dev(&dev->dev);
 }
 
+extern ssize_t of_device_get_modalias(struct of_device *ofdev,
+                                        char *str, ssize_t len);
+
 #endif /* _LINUX_OF_DEVICE_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 6755cf5ac109..cfc2297c3e28 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -17,8 +17,7 @@
 #ifndef LINUX_PCI_H
 #define LINUX_PCI_H
 
-/* Include the pci register defines */
-#include <linux/pci_regs.h>
+#include <linux/pci_regs.h>     /* The pci register defines */
 
 /*
  * The PCI interface treats multi-function devices as independent
@@ -49,12 +48,22 @@
 #include <linux/list.h>
 #include <linux/compiler.h>
 #include <linux/errno.h>
+#include <linux/kobject.h>
 #include <asm/atomic.h>
 #include <linux/device.h>
 
 /* Include the ID list */
 #include <linux/pci_ids.h>
 
+/* pci_slot represents a physical slot */
+struct pci_slot {
+        struct pci_bus *bus;            /* The bus this slot is on */
+        struct list_head list;          /* node in list of slots on this bus */
+        struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
+        unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
+        struct kobject kobj;
+};
+
 /* File state for mmap()s on /proc/bus/pci/X/Y */
 enum pci_mmap_state {
         pci_mmap_io,
@@ -147,6 +156,7 @@ struct pci_dev {
 
         void            *sysdata;       /* hook for sys-specific extension */
         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
+        struct pci_slot *slot;          /* Physical slot this device is in */
 
         unsigned int    devfn;          /* encoded device & function index */
         unsigned short  vendor;
@@ -172,6 +182,13 @@ struct pci_dev {
         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
                                            this is D0-D3, D0 being fully functional,
                                            and D3 being off. */
+        int             pm_cap;         /* PM capability offset in the
+                                           configuration space */
+        unsigned int    pme_support:5;  /* Bitmask of states from which PME#
+                                           can be generated */
+        unsigned int    d1_support:1;   /* Low power state D1 is supported */
+        unsigned int    d2_support:1;   /* Low power state D2 is supported */
+        unsigned int    no_d1d2:1;      /* Only allow D0 and D3 */
 
 #ifdef CONFIG_PCIEASPM
         struct pcie_link_state  *link_state;    /* ASPM link state. */
@@ -196,7 +213,6 @@ struct pci_dev {
         unsigned int    is_added:1;
         unsigned int    is_busmaster:1; /* device is busmaster */
         unsigned int    no_msi:1;       /* device may not use msi */
-        unsigned int    no_d1d2:1;   /* only allow d0 or d3 */
         unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
@@ -273,6 +289,7 @@ struct pci_bus {
         struct list_head children;      /* list of child buses */
         struct list_head devices;       /* list of devices on this bus */
         struct pci_dev  *self;          /* bridge device as seen by parent */
+        struct list_head slots;         /* list of slots on this bus */
         struct resource *resource[PCI_BUS_NUM_RESOURCES];
                                         /* address space routed to this bus */
 
@@ -334,7 +351,7 @@ struct pci_bus_region {
 struct pci_dynids {
         spinlock_t lock;            /* protects list, index */
         struct list_head list;      /* for IDs added at runtime */
-        unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
+        unsigned int use_driver_data:1; /* pci_device_id->driver_data is used */
 };
 
 /* ---------------------------------------------------------------- */
@@ -396,7 +413,7 @@ struct pci_driver {
         int  (*resume_early) (struct pci_dev *dev);
         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
         void (*shutdown) (struct pci_dev *dev);
-
+        struct pm_ext_ops *pm;
         struct pci_error_handlers *err_handler;
         struct device_driver    driver;
         struct pci_dynids dynids;
@@ -495,6 +512,10 @@ struct pci_bus *pci_create_bus(struct device *parent, int bus,
                                struct pci_ops *ops, void *sysdata);
 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
                                 int busnr);
+struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
+                                 const char *name);
+void pci_destroy_slot(struct pci_slot *slot);
+void pci_update_slot_number(struct pci_slot *slot, int slot_nr);
 int pci_scan_slot(struct pci_bus *bus, int devfn);
 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
@@ -624,6 +645,8 @@ int pci_restore_state(struct pci_dev *dev);
 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
+int pci_prepare_to_sleep(struct pci_dev *dev);
+int pci_back_from_sleep(struct pci_dev *dev);
 
 /* Functions for PCI Hotplug drivers to use */
 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
@@ -845,6 +868,11 @@ static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
         return -EIO;
 }
 
+static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
+{
+        return -EIO;
+}
+
 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
                                         unsigned int size)
 {
@@ -983,9 +1011,9 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
 /* If you want to know what to call your pci_dev, ask this function.
  * Again, it's a wrapper around the generic device.
  */
-static inline char *pci_name(struct pci_dev *pdev)
+static inline const char *pci_name(struct pci_dev *pdev)
 {
-        return pdev->dev.bus_id;
+        return dev_name(&pdev->dev);
 }
 
 
@@ -1020,7 +1048,9 @@ enum pci_fixup_pass {
         pci_fixup_header,       /* After reading configuration header */
         pci_fixup_final,        /* Final phase of device fixups */
         pci_fixup_enable,       /* pci_enable_device() time */
-        pci_fixup_resume,       /* pci_enable_device() time */
+        pci_fixup_resume,       /* pci_device_resume() */
+        pci_fixup_suspend,      /* pci_device_suspend */
+        pci_fixup_resume_early, /* pci_device_resume_early() */
 };
 
 /* Anonymous variables would be nice... */
@@ -1042,6 +1072,12 @@ enum pci_fixup_pass {
 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
                         resume##vendor##device##hook, vendor, device, hook)
+#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
+        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
+                        resume_early##vendor##device##hook, vendor, device, hook)
+#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
+        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
+                        suspend##vendor##device##hook, vendor, device, hook)
 
 
 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
@@ -1066,7 +1102,10 @@ extern int pci_pci_problems;
 extern unsigned long pci_cardbus_io_size;
 extern unsigned long pci_cardbus_mem_size;
 
-extern int pcibios_add_platform_entries(struct pci_dev *dev);
+int pcibios_add_platform_entries(struct pci_dev *dev);
+void pcibios_disable_device(struct pci_dev *dev);
+int pcibios_set_pcie_reset_state(struct pci_dev *dev,
+                                 enum pcie_reset_state state);
 
 #ifdef CONFIG_PCI_MMCONFIG
 extern void __init pci_mmcfg_early_init(void);
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index 8f67e8f2a3cc..a08cd06b541a 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -95,9 +95,6 @@ struct hotplug_slot_attribute {
  * @get_adapter_status: Called to get see if an adapter is present in the slot or not.
  *      If this field is NULL, the value passed in the struct hotplug_slot_info
  *      will be used when this value is requested by a user.
- * @get_address: Called to get pci address of a slot.
- *      If this field is NULL, the value passed in the struct hotplug_slot_info
- *      will be used when this value is requested by a user.
  * @get_max_bus_speed: Called to get the max bus speed for a slot.
  *      If this field is NULL, the value passed in the struct hotplug_slot_info
  *      will be used when this value is requested by a user.
@@ -120,7 +117,6 @@ struct hotplug_slot_ops {
         int (*get_attention_status)     (struct hotplug_slot *slot, u8 *value);
         int (*get_latch_status)         (struct hotplug_slot *slot, u8 *value);
         int (*get_adapter_status)       (struct hotplug_slot *slot, u8 *value);
-        int (*get_address)              (struct hotplug_slot *slot, u32 *value);
         int (*get_max_bus_speed)        (struct hotplug_slot *slot, enum pci_bus_speed *value);
         int (*get_cur_bus_speed)        (struct hotplug_slot *slot, enum pci_bus_speed *value);
 };
@@ -140,7 +136,6 @@ struct hotplug_slot_info {
         u8      attention_status;
         u8      latch_status;
         u8      adapter_status;
-        u32     address;
         enum pci_bus_speed      max_bus_speed;
         enum pci_bus_speed      cur_bus_speed;
 };
@@ -166,15 +161,14 @@ struct hotplug_slot {
 
         /* Variables below this are for use only by the hotplug pci core. */
         struct list_head                slot_list;
-        struct kobject                  kobj;
+        struct pci_slot                 *pci_slot;
 };
 #define to_hotplug_slot(n) container_of(n, struct hotplug_slot, kobj)
 
-extern int pci_hp_register              (struct hotplug_slot *slot);
-extern int pci_hp_deregister            (struct hotplug_slot *slot);
+extern int pci_hp_register(struct hotplug_slot *, struct pci_bus *, int nr);
+extern int pci_hp_deregister(struct hotplug_slot *slot);
 extern int __must_check pci_hp_change_slot_info (struct hotplug_slot *slot,
                                                  struct hotplug_slot_info *info);
-extern struct kset *pci_hotplug_slots_kset;
 
 /* PCI Setting Record (Type 0) */
 struct hpp_type0 {
@@ -227,9 +221,9 @@ struct hotplug_params {
 #include <acpi/acpi.h>
 #include <acpi/acpi_bus.h>
 #include <acpi/actypes.h>
-extern acpi_status acpi_run_oshp(acpi_handle handle);
 extern acpi_status acpi_get_hp_params_from_firmware(struct pci_bus *bus,
                                 struct hotplug_params *hpp);
+int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags);
 int acpi_root_bridge(acpi_handle handle);
 #endif
 #endif
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 7f3f101e03c1..2b3934c735b2 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2171,6 +2171,8 @@
 #define PCI_DEVICE_ID_MPC8544           0x0033
 #define PCI_DEVICE_ID_MPC8572E          0x0040
 #define PCI_DEVICE_ID_MPC8572           0x0041
+#define PCI_DEVICE_ID_MPC8536E          0x0050
+#define PCI_DEVICE_ID_MPC8536           0x0051
 #define PCI_DEVICE_ID_MPC8641           0x7010
 #define PCI_DEVICE_ID_MPC8641D          0x7011
 #define PCI_DEVICE_ID_MPC8610           0x7018
@@ -2188,6 +2190,7 @@
 #define PCI_DEVICE_ID_JMICRON_JMB366    0x2366
 #define PCI_DEVICE_ID_JMICRON_JMB368    0x2368
 #define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381
+#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
 #define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383
 
 #define PCI_VENDOR_ID_KORENIX           0x1982
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223c9194..19958b929905 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -231,6 +231,7 @@
 #define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
 #define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
 #define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
+#define  PCI_PM_CAP_PME_SHIFT   11      /* Start of the PME Mask in PMC */
 #define PCI_PM_CTRL             4       /* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
 #define  PCI_PM_CTRL_NO_SOFT_RESET      0x0004  /* No reset for D3hot->D0 */
diff --git a/include/linux/percpu_counter.h b/include/linux/percpu_counter.h
index 9007ccdfc112..208388835357 100644
--- a/include/linux/percpu_counter.h
+++ b/include/linux/percpu_counter.h
@@ -35,7 +35,7 @@ int percpu_counter_init_irq(struct percpu_counter *fbc, s64 amount);
 void percpu_counter_destroy(struct percpu_counter *fbc);
 void percpu_counter_set(struct percpu_counter *fbc, s64 amount);
 void __percpu_counter_add(struct percpu_counter *fbc, s64 amount, s32 batch);
-s64 __percpu_counter_sum(struct percpu_counter *fbc);
+s64 __percpu_counter_sum(struct percpu_counter *fbc, int set);
 
 static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount)
 {
@@ -44,13 +44,19 @@ static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount)
 
 static inline s64 percpu_counter_sum_positive(struct percpu_counter *fbc)
 {
-        s64 ret = __percpu_counter_sum(fbc);
+        s64 ret = __percpu_counter_sum(fbc, 0);
         return ret < 0 ? 0 : ret;
 }
 
+static inline s64 percpu_counter_sum_and_set(struct percpu_counter *fbc)
+{
+        return __percpu_counter_sum(fbc, 1);
+}
+
+
 static inline s64 percpu_counter_sum(struct percpu_counter *fbc)
 {
-        return __percpu_counter_sum(fbc);
+        return __percpu_counter_sum(fbc, 0);
 }
 
 static inline s64 percpu_counter_read(struct percpu_counter *fbc)
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 3261681c82a4..95ac21ab3a09 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -53,6 +53,7 @@ struct platform_driver {
         int (*suspend_late)(struct platform_device *, pm_message_t state);
         int (*resume_early)(struct platform_device *);
         int (*resume)(struct platform_device *);
+        struct pm_ext_ops *pm;
         struct device_driver driver;
 };
 
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 39a7ee859b67..4ad9de94449a 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -112,7 +112,9 @@ typedef struct pm_message {
         int event;
 } pm_message_t;
 
-/*
+/**
+ * struct pm_ops - device PM callbacks
+ *
  * Several driver power state transitions are externally visible, affecting
  * the state of pending I/O queues and (for drivers that touch hardware)
  * interrupts, wakeups, DMA, and other hardware state.  There may also be
@@ -120,6 +122,284 @@ typedef struct pm_message {
  * to the rest of the driver stack (such as a driver that's ON gating off
  * clocks which are not in active use).
  *
+ * The externally visible transitions are handled with the help of the following
+ * callbacks included in this structure:
+ *
+ * @prepare: Prepare the device for the upcoming transition, but do NOT change
+ *      its hardware state.  Prevent new children of the device from being
+ *      registered after @prepare() returns (the driver's subsystem and
+ *      generally the rest of the kernel is supposed to prevent new calls to the
+ *      probe method from being made too once @prepare() has succeeded).  If
+ *      @prepare() detects a situation it cannot handle (e.g. registration of a
+ *      child already in progress), it may return -EAGAIN, so that the PM core
+ *      can execute it once again (e.g. after the new child has been registered)
+ *      to recover from the race condition.  This method is executed for all
+ *      kinds of suspend transitions and is followed by one of the suspend
+ *      callbacks: @suspend(), @freeze(), or @poweroff().
+ *      The PM core executes @prepare() for all devices before starting to
+ *      execute suspend callbacks for any of them, so drivers may assume all of
+ *      the other devices to be present and functional while @prepare() is being
+ *      executed.  In particular, it is safe to make GFP_KERNEL memory
+ *      allocations from within @prepare().  However, drivers may NOT assume
+ *      anything about the availability of the user space at that time and it
+ *      is not correct to request firmware from within @prepare() (it's too
+ *      late to do that).  [To work around this limitation, drivers may
+ *      register suspend and hibernation notifiers that are executed before the
+ *      freezing of tasks.]
+ *
+ * @complete: Undo the changes made by @prepare().  This method is executed for
+ *      all kinds of resume transitions, following one of the resume callbacks:
+ *      @resume(), @thaw(), @restore().  Also called if the state transition
+ *      fails before the driver's suspend callback (@suspend(), @freeze(),
+ *      @poweroff()) can be executed (e.g. if the suspend callback fails for one
+ *      of the other devices that the PM core has unsuccessfully attempted to
+ *      suspend earlier).
+ *      The PM core executes @complete() after it has executed the appropriate
+ *      resume callback for all devices.
+ *
+ * @suspend: Executed before putting the system into a sleep state in which the
+ *      contents of main memory are preserved.  Quiesce the device, put it into
+ *      a low power state appropriate for the upcoming system state (such as
+ *      PCI_D3hot), and enable wakeup events as appropriate.
+ *
+ * @resume: Executed after waking the system up from a sleep state in which the
+ *      contents of main memory were preserved.  Put the device into the
+ *      appropriate state, according to the information saved in memory by the
+ *      preceding @suspend().  The driver starts working again, responding to
+ *      hardware events and software requests.  The hardware may have gone
+ *      through a power-off reset, or it may have maintained state from the
+ *      previous suspend() which the driver may rely on while resuming.  On most
+ *      platforms, there are no restrictions on availability of resources like
+ *      clocks during @resume().
+ *
+ * @freeze: Hibernation-specific, executed before creating a hibernation image.
+ *      Quiesce operations so that a consistent image can be created, but do NOT
+ *      otherwise put the device into a low power device state and do NOT emit
+ *      system wakeup events.  Save in main memory the device settings to be
+ *      used by @restore() during the subsequent resume from hibernation or by
+ *      the subsequent @thaw(), if the creation of the image or the restoration
+ *      of main memory contents from it fails.
+ *
+ * @thaw: Hibernation-specific, executed after creating a hibernation image OR
+ *      if the creation of the image fails.  Also executed after a failing
+ *      attempt to restore the contents of main memory from such an image.
+ *      Undo the changes made by the preceding @freeze(), so the device can be
+ *      operated in the same way as immediately before the call to @freeze().
+ *
+ * @poweroff: Hibernation-specific, executed after saving a hibernation image.
+ *      Quiesce the device, put it into a low power state appropriate for the
+ *      upcoming system state (such as PCI_D3hot), and enable wakeup events as
+ *      appropriate.
+ *
+ * @restore: Hibernation-specific, executed after restoring the contents of main
+ *      memory from a hibernation image.  Driver starts working again,
+ *      responding to hardware events and software requests.  Drivers may NOT
+ *      make ANY assumptions about the hardware state right prior to @restore().
+ *      On most platforms, there are no restrictions on availability of
+ *      resources like clocks during @restore().
+ *
+ * All of the above callbacks, except for @complete(), return error codes.
+ * However, the error codes returned by the resume operations, @resume(),
+ * @thaw(), and @restore(), do not cause the PM core to abort the resume
+ * transition during which they are returned.  The error codes returned in
+ * that cases are only printed by the PM core to the system logs for debugging
+ * purposes.  Still, it is recommended that drivers only return error codes
+ * from their resume methods in case of an unrecoverable failure (i.e. when the
+ * device being handled refuses to resume and becomes unusable) to allow us to
+ * modify the PM core in the future, so that it can avoid attempting to handle
+ * devices that failed to resume and their children.
+ *
+ * It is allowed to unregister devices while the above callbacks are being
+ * executed.  However, it is not allowed to unregister a device from within any
+ * of its own callbacks.
+ */
+
+struct pm_ops {
+        int (*prepare)(struct device *dev);
+        void (*complete)(struct device *dev);
+        int (*suspend)(struct device *dev);
+        int (*resume)(struct device *dev);
+        int (*freeze)(struct device *dev);
+        int (*thaw)(struct device *dev);
+        int (*poweroff)(struct device *dev);
+        int (*restore)(struct device *dev);
+};
+
+/**
+ * struct pm_ext_ops - extended device PM callbacks
+ *
+ * Some devices require certain operations related to suspend and hibernation
+ * to be carried out with interrupts disabled.  Thus, 'struct pm_ext_ops' below
+ * is defined, adding callbacks to be executed with interrupts disabled to
+ * 'struct pm_ops'.
+ *
+ * The following callbacks included in 'struct pm_ext_ops' are executed with
+ * the nonboot CPUs switched off and with interrupts disabled on the only
+ * functional CPU.  They also are executed with the PM core list of devices
+ * locked, so they must NOT unregister any devices.
+ *
+ * @suspend_noirq: Complete the operations of ->suspend() by carrying out any
+ *      actions required for suspending the device that need interrupts to be
+ *      disabled
+ *
+ * @resume_noirq: Prepare for the execution of ->resume() by carrying out any
+ *      actions required for resuming the device that need interrupts to be
+ *      disabled
+ *
+ * @freeze_noirq: Complete the operations of ->freeze() by carrying out any
+ *      actions required for freezing the device that need interrupts to be
+ *      disabled
+ *
+ * @thaw_noirq: Prepare for the execution of ->thaw() by carrying out any
+ *      actions required for thawing the device that need interrupts to be
+ *      disabled
+ *
+ * @poweroff_noirq: Complete the operations of ->poweroff() by carrying out any
+ *      actions required for handling the device that need interrupts to be
+ *      disabled
+ *
+ * @restore_noirq: Prepare for the execution of ->restore() by carrying out any
+ *      actions required for restoring the operations of the device that need
+ *      interrupts to be disabled
+ *
+ * All of the above callbacks return error codes, but the error codes returned
+ * by the resume operations, @resume_noirq(), @thaw_noirq(), and
+ * @restore_noirq(), do not cause the PM core to abort the resume transition
+ * during which they are returned.  The error codes returned in that cases are
+ * only printed by the PM core to the system logs for debugging purposes.
+ * Still, as stated above, it is recommended that drivers only return error
+ * codes from their resume methods if the device being handled fails to resume
+ * and is not usable any more.
+ */
+
+struct pm_ext_ops {
+        struct pm_ops base;
+        int (*suspend_noirq)(struct device *dev);
+        int (*resume_noirq)(struct device *dev);
+        int (*freeze_noirq)(struct device *dev);
+        int (*thaw_noirq)(struct device *dev);
+        int (*poweroff_noirq)(struct device *dev);
+        int (*restore_noirq)(struct device *dev);
+};
+
+/**
+ * PM_EVENT_ messages
+ *
+ * The following PM_EVENT_ messages are defined for the internal use of the PM
+ * core, in order to provide a mechanism allowing the high level suspend and
+ * hibernation code to convey the necessary information to the device PM core
+ * code:
+ *
+ * ON           No transition.
+ *
+ * FREEZE       System is going to hibernate, call ->prepare() and ->freeze()
+ *              for all devices.
+ *
+ * SUSPEND      System is going to suspend, call ->prepare() and ->suspend()
+ *              for all devices.
+ *
+ * HIBERNATE    Hibernation image has been saved, call ->prepare() and
+ *              ->poweroff() for all devices.
+ *
+ * QUIESCE      Contents of main memory are going to be restored from a (loaded)
+ *              hibernation image, call ->prepare() and ->freeze() for all
+ *              devices.
+ *
+ * RESUME       System is resuming, call ->resume() and ->complete() for all
+ *              devices.
+ *
+ * THAW         Hibernation image has been created, call ->thaw() and
+ *              ->complete() for all devices.
+ *
+ * RESTORE      Contents of main memory have been restored from a hibernation
+ *              image, call ->restore() and ->complete() for all devices.
+ *
+ * RECOVER      Creation of a hibernation image or restoration of the main
+ *              memory contents from a hibernation image has failed, call
+ *              ->thaw() and ->complete() for all devices.
+ */
+
+#define PM_EVENT_ON             0x0000
+#define PM_EVENT_FREEZE         0x0001
+#define PM_EVENT_SUSPEND        0x0002
+#define PM_EVENT_HIBERNATE      0x0004
+#define PM_EVENT_QUIESCE        0x0008
+#define PM_EVENT_RESUME         0x0010
+#define PM_EVENT_THAW           0x0020
+#define PM_EVENT_RESTORE        0x0040
+#define PM_EVENT_RECOVER        0x0080
+
+#define PM_EVENT_SLEEP  (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE)
+
+#define PMSG_FREEZE     ((struct pm_message){ .event = PM_EVENT_FREEZE, })
+#define PMSG_QUIESCE    ((struct pm_message){ .event = PM_EVENT_QUIESCE, })
+#define PMSG_SUSPEND    ((struct pm_message){ .event = PM_EVENT_SUSPEND, })
+#define PMSG_HIBERNATE  ((struct pm_message){ .event = PM_EVENT_HIBERNATE, })
+#define PMSG_RESUME     ((struct pm_message){ .event = PM_EVENT_RESUME, })
+#define PMSG_THAW       ((struct pm_message){ .event = PM_EVENT_THAW, })
+#define PMSG_RESTORE    ((struct pm_message){ .event = PM_EVENT_RESTORE, })
+#define PMSG_RECOVER    ((struct pm_message){ .event = PM_EVENT_RECOVER, })
+#define PMSG_ON         ((struct pm_message){ .event = PM_EVENT_ON, })
+
+/**
+ * Device power management states
+ *
+ * These state labels are used internally by the PM core to indicate the current
+ * status of a device with respect to the PM core operations.
+ *
+ * DPM_ON               Device is regarded as operational.  Set this way
+ *                      initially and when ->complete() is about to be called.
+ *                      Also set when ->prepare() fails.
+ *
+ * DPM_PREPARING        Device is going to be prepared for a PM transition.  Set
+ *                      when ->prepare() is about to be called.
+ *
+ * DPM_RESUMING         Device is going to be resumed.  Set when ->resume(),
+ *                      ->thaw(), or ->restore() is about to be called.
+ *
+ * DPM_SUSPENDING       Device has been prepared for a power transition.  Set
+ *                      when ->prepare() has just succeeded.
+ *
+ * DPM_OFF              Device is regarded as inactive.  Set immediately after
+ *                      ->suspend(), ->freeze(), or ->poweroff() has succeeded.
+ *                      Also set when ->resume()_noirq, ->thaw_noirq(), or
+ *                      ->restore_noirq() is about to be called.
+ *
+ * DPM_OFF_IRQ          Device is in a "deep sleep".  Set immediately after
+ *                      ->suspend_noirq(), ->freeze_noirq(), or
+ *                      ->poweroff_noirq() has just succeeded.
+ */
+
+enum dpm_state {
+        DPM_INVALID,
+        DPM_ON,
+        DPM_PREPARING,
+        DPM_RESUMING,
+        DPM_SUSPENDING,
+        DPM_OFF,
+        DPM_OFF_IRQ,
+};
+
+struct dev_pm_info {
+        pm_message_t            power_state;
+        unsigned                can_wakeup:1;
+        unsigned                should_wakeup:1;
+        enum dpm_state          status;         /* Owned by the PM core */
+#ifdef  CONFIG_PM_SLEEP
+        struct list_head        entry;
+#endif
+};
+
+/*
+ * The PM_EVENT_ messages are also used by drivers implementing the legacy
+ * suspend framework, based on the ->suspend() and ->resume() callbacks common
+ * for suspend and hibernation transitions, according to the rules below.
+ */
+
+/* Necessary, because several drivers use PM_EVENT_PRETHAW */
+#define PM_EVENT_PRETHAW PM_EVENT_QUIESCE
+
+/*
  * One transition is triggered by resume(), after a suspend() call; the
  * message is implicit:
  *
@@ -164,35 +444,13 @@ typedef struct pm_message {
  * or from system low-power states such as standby or suspend-to-RAM.
  */
 
-#define PM_EVENT_ON 0
-#define PM_EVENT_FREEZE 1
-#define PM_EVENT_SUSPEND 2
-#define PM_EVENT_HIBERNATE 4
-#define PM_EVENT_PRETHAW 8
-
-#define PM_EVENT_SLEEP  (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE)
-
-#define PMSG_FREEZE     ((struct pm_message){ .event = PM_EVENT_FREEZE, })
-#define PMSG_PRETHAW    ((struct pm_message){ .event = PM_EVENT_PRETHAW, })
-#define PMSG_SUSPEND    ((struct pm_message){ .event = PM_EVENT_SUSPEND, })
-#define PMSG_HIBERNATE  ((struct pm_message){ .event = PM_EVENT_HIBERNATE, })
-#define PMSG_ON         ((struct pm_message){ .event = PM_EVENT_ON, })
-
-struct dev_pm_info {
-        pm_message_t            power_state;
-        unsigned                can_wakeup:1;
-        unsigned                should_wakeup:1;
-        bool                    sleeping:1;     /* Owned by the PM core */
-#ifdef  CONFIG_PM_SLEEP
-        struct list_head        entry;
-#endif
-};
+#ifdef CONFIG_PM_SLEEP
+extern void device_pm_lock(void);
+extern void device_power_up(pm_message_t state);
+extern void device_resume(pm_message_t state);
 
+extern void device_pm_unlock(void);
 extern int device_power_down(pm_message_t state);
-extern void device_power_up(void);
-extern void device_resume(void);
-
-#ifdef CONFIG_PM_SLEEP
 extern int device_suspend(pm_message_t state);
 extern int device_prepare_suspend(pm_message_t state);
 
diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
index f0d0b2cb8d20..0aae7776185e 100644
--- a/include/linux/pm_wakeup.h
+++ b/include/linux/pm_wakeup.h
@@ -35,6 +35,11 @@ static inline void device_init_wakeup(struct device *dev, int val)
         dev->power.can_wakeup = dev->power.should_wakeup = !!val;
 }
 
+static inline void device_set_wakeup_capable(struct device *dev, int val)
+{
+        dev->power.can_wakeup = !!val;
+}
+
 static inline int device_can_wakeup(struct device *dev)
 {
         return dev->power.can_wakeup;
@@ -47,21 +52,7 @@ static inline void device_set_wakeup_enable(struct device *dev, int val)
 
 static inline int device_may_wakeup(struct device *dev)
 {
-        return dev->power.can_wakeup & dev->power.should_wakeup;
-}
-
-/*
- * Platform hook to activate device wakeup capability, if that's not already
- * handled by enable_irq_wake() etc.
- * Returns zero on success, else negative errno
- */
-extern int (*platform_enable_wakeup)(struct device *dev, int is_on);
-
-static inline int call_platform_enable_wakeup(struct device *dev, int is_on)
-{
-        if (platform_enable_wakeup)
-                return (*platform_enable_wakeup)(dev, is_on);
-        return 0;
+        return dev->power.can_wakeup && dev->power.should_wakeup;
 }
 
 #else /* !CONFIG_PM */
@@ -72,6 +63,8 @@ static inline void device_init_wakeup(struct device *dev, int val)
         dev->power.can_wakeup = !!val;
 }
 
+static inline void device_set_wakeup_capable(struct device *dev, int val) { }
+
 static inline int device_can_wakeup(struct device *dev)
 {
         return dev->power.can_wakeup;
@@ -80,11 +73,6 @@ static inline int device_can_wakeup(struct device *dev)
 #define device_set_wakeup_enable(dev, val)      do {} while (0)
 #define device_may_wakeup(dev)                  0
 
-static inline int call_platform_enable_wakeup(struct device *dev, int is_on)
-{
-        return 0;
-}
-
 #endif /* !CONFIG_PM */
 
 #endif /* _LINUX_PM_WAKEUP_H */
diff --git a/include/linux/pnp.h b/include/linux/pnp.h
index 63b128d512fb..1ce54b63085d 100644
--- a/include/linux/pnp.h
+++ b/include/linux/pnp.h
@@ -1,6 +1,8 @@
 /*
  * Linux Plug and Play Support
  * Copyright by Adam Belay <ambx1@neo.rr.com>
+ * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
+ *      Bjorn Helgaas <bjorn.helgaas@hp.com>
  */
 
 #ifndef _LINUX_PNP_H
@@ -15,7 +17,6 @@
 
 struct pnp_protocol;
 struct pnp_dev;
-struct pnp_resource_table;
 
 /*
  * Resource Management
@@ -24,7 +25,14 @@ struct resource *pnp_get_resource(struct pnp_dev *, unsigned int, unsigned int);
 
 static inline int pnp_resource_valid(struct resource *res)
 {
-        if (res && !(res->flags & IORESOURCE_UNSET))
+        if (res)
+                return 1;
+        return 0;
+}
+
+static inline int pnp_resource_enabled(struct resource *res)
+{
+        if (res && !(res->flags & IORESOURCE_DISABLED))
                 return 1;
         return 0;
 }
@@ -40,19 +48,31 @@ static inline resource_size_t pnp_resource_len(struct resource *res)
 static inline resource_size_t pnp_port_start(struct pnp_dev *dev,
                                              unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_IO, bar)->start;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar);
+
+        if (pnp_resource_valid(res))
+                return res->start;
+        return 0;
 }
 
 static inline resource_size_t pnp_port_end(struct pnp_dev *dev,
                                            unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_IO, bar)->end;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar);
+
+        if (pnp_resource_valid(res))
+                return res->end;
+        return 0;
 }
 
 static inline unsigned long pnp_port_flags(struct pnp_dev *dev,
                                            unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_IO, bar)->flags;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar);
+
+        if (pnp_resource_valid(res))
+                return res->flags;
+        return IORESOURCE_IO | IORESOURCE_AUTO;
 }
 
 static inline int pnp_port_valid(struct pnp_dev *dev, unsigned int bar)
@@ -63,25 +83,41 @@ static inline int pnp_port_valid(struct pnp_dev *dev, unsigned int bar)
 static inline resource_size_t pnp_port_len(struct pnp_dev *dev,
                                            unsigned int bar)
 {
-        return pnp_resource_len(pnp_get_resource(dev, IORESOURCE_IO, bar));
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar);
+
+        if (pnp_resource_valid(res))
+                return pnp_resource_len(res);
+        return 0;
 }
 
 
 static inline resource_size_t pnp_mem_start(struct pnp_dev *dev,
                                             unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_MEM, bar)->start;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar);
+
+        if (pnp_resource_valid(res))
+                return res->start;
+        return 0;
 }
 
 static inline resource_size_t pnp_mem_end(struct pnp_dev *dev,
                                           unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_MEM, bar)->end;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar);
+
+        if (pnp_resource_valid(res))
+                return res->end;
+        return 0;
 }
 
 static inline unsigned long pnp_mem_flags(struct pnp_dev *dev, unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_MEM, bar)->flags;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar);
+
+        if (pnp_resource_valid(res))
+                return res->flags;
+        return IORESOURCE_MEM | IORESOURCE_AUTO;
 }
 
 static inline int pnp_mem_valid(struct pnp_dev *dev, unsigned int bar)
@@ -92,18 +128,30 @@ static inline int pnp_mem_valid(struct pnp_dev *dev, unsigned int bar)
 static inline resource_size_t pnp_mem_len(struct pnp_dev *dev,
                                           unsigned int bar)
 {
-        return pnp_resource_len(pnp_get_resource(dev, IORESOURCE_MEM, bar));
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar);
+
+        if (pnp_resource_valid(res))
+                return pnp_resource_len(res);
+        return 0;
 }
 
 
 static inline resource_size_t pnp_irq(struct pnp_dev *dev, unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_IRQ, bar)->start;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_IRQ, bar);
+
+        if (pnp_resource_valid(res))
+                return res->start;
+        return -1;
 }
 
 static inline unsigned long pnp_irq_flags(struct pnp_dev *dev, unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_IRQ, bar)->flags;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_IRQ, bar);
+
+        if (pnp_resource_valid(res))
+                return res->flags;
+        return IORESOURCE_IRQ | IORESOURCE_AUTO;
 }
 
 static inline int pnp_irq_valid(struct pnp_dev *dev, unsigned int bar)
@@ -114,12 +162,20 @@ static inline int pnp_irq_valid(struct pnp_dev *dev, unsigned int bar)
 
 static inline resource_size_t pnp_dma(struct pnp_dev *dev, unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_DMA, bar)->start;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_DMA, bar);
+
+        if (pnp_resource_valid(res))
+                return res->start;
+        return -1;
 }
 
 static inline unsigned long pnp_dma_flags(struct pnp_dev *dev, unsigned int bar)
 {
-        return pnp_get_resource(dev, IORESOURCE_DMA, bar)->flags;
+        struct resource *res = pnp_get_resource(dev, IORESOURCE_DMA, bar);
+
+        if (pnp_resource_valid(res))
+                return res->flags;
+        return IORESOURCE_DMA | IORESOURCE_AUTO;
 }
 
 static inline int pnp_dma_valid(struct pnp_dev *dev, unsigned int bar)
@@ -128,57 +184,6 @@ static inline int pnp_dma_valid(struct pnp_dev *dev, unsigned int bar)
 }
 
 
-#define PNP_PORT_FLAG_16BITADDR (1<<0)
-#define PNP_PORT_FLAG_FIXED     (1<<1)
-
-struct pnp_port {
-        unsigned short min;     /* min base number */
-        unsigned short max;     /* max base number */
-        unsigned char align;    /* align boundary */
-        unsigned char size;     /* size of range */
-        unsigned char flags;    /* port flags */
-        unsigned char pad;      /* pad */
-        struct pnp_port *next;  /* next port */
-};
-
-#define PNP_IRQ_NR 256
-struct pnp_irq {
-        DECLARE_BITMAP(map, PNP_IRQ_NR);        /* bitmask for IRQ lines */
-        unsigned char flags;    /* IRQ flags */
-        unsigned char pad;      /* pad */
-        struct pnp_irq *next;   /* next IRQ */
-};
-
-struct pnp_dma {
-        unsigned char map;      /* bitmask for DMA channels */
-        unsigned char flags;    /* DMA flags */
-        struct pnp_dma *next;   /* next port */
-};
-
-struct pnp_mem {
-        unsigned int min;       /* min base number */
-        unsigned int max;       /* max base number */
-        unsigned int align;     /* align boundary */
-        unsigned int size;      /* size of range */
-        unsigned char flags;    /* memory flags */
-        unsigned char pad;      /* pad */
-        struct pnp_mem *next;   /* next memory resource */
-};
-
-#define PNP_RES_PRIORITY_PREFERRED      0
-#define PNP_RES_PRIORITY_ACCEPTABLE     1
-#define PNP_RES_PRIORITY_FUNCTIONAL     2
-#define PNP_RES_PRIORITY_INVALID        65535
-
-struct pnp_option {
-        unsigned short priority;        /* priority */
-        struct pnp_port *port;          /* first port */
-        struct pnp_irq *irq;            /* first IRQ */
-        struct pnp_dma *dma;            /* first DMA */
-        struct pnp_mem *mem;            /* first memory resource */
-        struct pnp_option *next;        /* used to chain dependent resources */
-};
-
 /*
  * Device Management
  */
@@ -246,9 +251,9 @@ struct pnp_dev {
 
         int active;
         int capabilities;
-        struct pnp_option *independent;
-        struct pnp_option *dependent;
-        struct pnp_resource_table *res;
+        unsigned int num_dependent_sets;
+        struct list_head resources;
+        struct list_head options;
 
         char name[PNP_NAME_LEN];        /* contains a human-readable name */
         int flags;                      /* used by protocols */
@@ -425,6 +430,8 @@ void pnp_unregister_card_driver(struct pnp_card_driver *drv);
 extern struct list_head pnp_cards;
 
 /* resource management */
+int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t base,
+                        resource_size_t size);
 int pnp_auto_config_dev(struct pnp_dev *dev);
 int pnp_start_dev(struct pnp_dev *dev);
 int pnp_stop_dev(struct pnp_dev *dev);
@@ -452,6 +459,9 @@ static inline int pnp_register_card_driver(struct pnp_card_driver *drv) { return
 static inline void pnp_unregister_card_driver(struct pnp_card_driver *drv) { }
 
 /* resource management */
+static inline int pnp_possible_config(struct pnp_dev *dev, int type,
+                                      resource_size_t base,
+                                      resource_size_t size) { return 0; }
 static inline int pnp_auto_config_dev(struct pnp_dev *dev) { return -ENODEV; }
 static inline int pnp_start_dev(struct pnp_dev *dev) { return -ENODEV; }
 static inline int pnp_stop_dev(struct pnp_dev *dev) { return -ENODEV; }
diff --git a/include/linux/preempt.h b/include/linux/preempt.h
index 23f0c54175cd..72b1a10a59b6 100644
--- a/include/linux/preempt.h
+++ b/include/linux/preempt.h
@@ -10,7 +10,7 @@
 #include <linux/linkage.h>
 #include <linux/list.h>
 
-#ifdef CONFIG_DEBUG_PREEMPT
+#if defined(CONFIG_DEBUG_PREEMPT) || defined(CONFIG_PREEMPT_TRACER)
   extern void add_preempt_count(int val);
   extern void sub_preempt_count(int val);
 #else
@@ -52,6 +52,34 @@ do { \
         preempt_check_resched(); \
 } while (0)
 
+/* For debugging and tracer internals only! */
+#define add_preempt_count_notrace(val)                  \
+        do { preempt_count() += (val); } while (0)
+#define sub_preempt_count_notrace(val)                  \
+        do { preempt_count() -= (val); } while (0)
+#define inc_preempt_count_notrace() add_preempt_count_notrace(1)
+#define dec_preempt_count_notrace() sub_preempt_count_notrace(1)
+
+#define preempt_disable_notrace() \
+do { \
+        inc_preempt_count_notrace(); \
+        barrier(); \
+} while (0)
+
+#define preempt_enable_no_resched_notrace() \
+do { \
+        barrier(); \
+        dec_preempt_count_notrace(); \
+} while (0)
+
+/* preempt_check_resched is OK to trace */
+#define preempt_enable_notrace() \
+do { \
+        preempt_enable_no_resched_notrace(); \
+        barrier(); \
+        preempt_check_resched(); \
+} while (0)
+
 #else
 
 #define preempt_disable()               do { } while (0)
@@ -59,6 +87,10 @@ do { \
 #define preempt_enable()                do { } while (0)
 #define preempt_check_resched()         do { } while (0)
 
+#define preempt_disable_notrace()               do { } while (0)
+#define preempt_enable_no_resched_notrace()     do { } while (0)
+#define preempt_enable_notrace()                do { } while (0)
+
 #endif
 
 #ifdef CONFIG_PREEMPT_NOTIFIERS
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h
index f98501ba557e..c6f5f9dd0cee 100644
--- a/include/linux/ptrace.h
+++ b/include/linux/ptrace.h
@@ -95,8 +95,12 @@ extern void __ptrace_link(struct task_struct *child,
                           struct task_struct *new_parent);
 extern void __ptrace_unlink(struct task_struct *child);
 extern void ptrace_untrace(struct task_struct *child);
-extern int ptrace_may_attach(struct task_struct *task);
-extern int __ptrace_may_attach(struct task_struct *task);
+#define PTRACE_MODE_READ   1
+#define PTRACE_MODE_ATTACH 2
+/* Returns 0 on success, -errno on denial. */
+extern int __ptrace_may_access(struct task_struct *task, unsigned int mode);
+/* Returns true on success, false on denial. */
+extern bool ptrace_may_access(struct task_struct *task, unsigned int mode);
 
 static inline int ptrace_reparented(struct task_struct *child)
 {
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
new file mode 100644
index 000000000000..3945f803d514
--- /dev/null
+++ b/include/linux/pwm.h
@@ -0,0 +1,31 @@
+#ifndef __LINUX_PWM_H
+#define __LINUX_PWM_H
+
+struct pwm_device;
+
+/*
+ * pwm_request - request a PWM device
+ */
+struct pwm_device *pwm_request(int pwm_id, const char *label);
+
+/*
+ * pwm_free - free a PWM device
+ */
+void pwm_free(struct pwm_device *pwm);
+
+/*
+ * pwm_config - change a PWM device configuration
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
+
+/*
+ * pwm_enable - start a PWM output toggling
+ */
+int pwm_enable(struct pwm_device *pwm);
+
+/*
+ * pwm_disable - stop a PWM output toggling
+ */
+void pwm_disable(struct pwm_device *pwm);
+
+#endif /* __ASM_ARCH_PWM_H */
diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
new file mode 100644
index 000000000000..7a9754c96775
--- /dev/null
+++ b/include/linux/pwm_backlight.h
@@ -0,0 +1,17 @@
+/*
+ * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
+ */
+#ifndef __LINUX_PWM_BACKLIGHT_H
+#define __LINUX_PWM_BACKLIGHT_H
+
+struct platform_pwm_backlight_data {
+        int pwm_id;
+        unsigned int max_brightness;
+        unsigned int dft_brightness;
+        unsigned int pwm_period_ns;
+        int (*init)(struct device *dev);
+        int (*notify)(int brightness);
+        void (*exit)(struct device *dev);
+};
+
+#endif
diff --git a/include/linux/rcuclassic.h b/include/linux/rcuclassic.h
index b3aa05baab8a..8c774905dcfe 100644
--- a/include/linux/rcuclassic.h
+++ b/include/linux/rcuclassic.h
@@ -151,7 +151,10 @@ extern struct lockdep_map rcu_lock_map;
 
 #define __synchronize_sched() synchronize_rcu()
 
+#define call_rcu_sched(head, func) call_rcu(head, func)
+
 extern void __rcu_init(void);
+#define rcu_init_sched()        do { } while (0)
 extern void rcu_check_callbacks(int cpu, int user);
 extern void rcu_restart_cpu(int cpu);
 
diff --git a/include/linux/rculist.h b/include/linux/rculist.h
index bde4586f4382..b0f39be08b6c 100644
--- a/include/linux/rculist.h
+++ b/include/linux/rculist.h
@@ -1,6 +1,373 @@
 #ifndef _LINUX_RCULIST_H
 #define _LINUX_RCULIST_H
 
+#ifdef __KERNEL__
+
+/*
+ * RCU-protected list version
+ */
 #include <linux/list.h>
+#include <linux/rcupdate.h>
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_add_rcu(struct list_head *new,
+                struct list_head *prev, struct list_head *next)
+{
+        new->next = next;
+        new->prev = prev;
+        rcu_assign_pointer(prev->next, new);
+        next->prev = new;
+}
+
+/**
+ * list_add_rcu - add a new entry to rcu-protected list
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as list_add_rcu()
+ * or list_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * list_for_each_entry_rcu().
+ */
+static inline void list_add_rcu(struct list_head *new, struct list_head *head)
+{
+        __list_add_rcu(new, head, head->next);
+}
+
+/**
+ * list_add_tail_rcu - add a new entry to rcu-protected list
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as list_add_tail_rcu()
+ * or list_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * list_for_each_entry_rcu().
+ */
+static inline void list_add_tail_rcu(struct list_head *new,
+                                        struct list_head *head)
+{
+        __list_add_rcu(new, head->prev, head);
+}
+
+/**
+ * list_del_rcu - deletes entry from list without re-initialization
+ * @entry: the element to delete from the list.
+ *
+ * Note: list_empty() on entry does not return true after this,
+ * the entry is in an undefined state. It is useful for RCU based
+ * lockfree traversal.
+ *
+ * In particular, it means that we can not poison the forward
+ * pointers that may still be used for walking the list.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as list_del_rcu()
+ * or list_add_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * list_for_each_entry_rcu().
+ *
+ * Note that the caller is not permitted to immediately free
+ * the newly deleted entry.  Instead, either synchronize_rcu()
+ * or call_rcu() must be used to defer freeing until an RCU
+ * grace period has elapsed.
+ */
+static inline void list_del_rcu(struct list_head *entry)
+{
+        __list_del(entry->prev, entry->next);
+        entry->prev = LIST_POISON2;
+}
+
+/**
+ * list_replace_rcu - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * The @old entry will be replaced with the @new entry atomically.
+ * Note: @old should not be empty.
+ */
+static inline void list_replace_rcu(struct list_head *old,
+                                struct list_head *new)
+{
+        new->next = old->next;
+        new->prev = old->prev;
+        rcu_assign_pointer(new->prev->next, new);
+        new->next->prev = new;
+        old->prev = LIST_POISON2;
+}
+
+/**
+ * list_splice_init_rcu - splice an RCU-protected list into an existing list.
+ * @list:       the RCU-protected list to splice
+ * @head:       the place in the list to splice the first list into
+ * @sync:       function to sync: synchronize_rcu(), synchronize_sched(), ...
+ *
+ * @head can be RCU-read traversed concurrently with this function.
+ *
+ * Note that this function blocks.
+ *
+ * Important note: the caller must take whatever action is necessary to
+ *      prevent any other updates to @head.  In principle, it is possible
+ *      to modify the list as soon as sync() begins execution.
+ *      If this sort of thing becomes necessary, an alternative version
+ *      based on call_rcu() could be created.  But only if -really-
+ *      needed -- there is no shortage of RCU API members.
+ */
+static inline void list_splice_init_rcu(struct list_head *list,
+                                        struct list_head *head,
+                                        void (*sync)(void))
+{
+        struct list_head *first = list->next;
+        struct list_head *last = list->prev;
+        struct list_head *at = head->next;
+
+        if (list_empty(head))
+                return;
+
+        /* "first" and "last" tracking list, so initialize it. */
+
+        INIT_LIST_HEAD(list);
+
+        /*
+         * At this point, the list body still points to the source list.
+         * Wait for any readers to finish using the list before splicing
+         * the list body into the new list.  Any new readers will see
+         * an empty list.
+         */
+
+        sync();
+
+        /*
+         * Readers are finished with the source list, so perform splice.
+         * The order is important if the new list is global and accessible
+         * to concurrent RCU readers.  Note that RCU readers are not
+         * permitted to traverse the prev pointers without excluding
+         * this function.
+         */
+
+        last->next = at;
+        rcu_assign_pointer(head->next, first);
+        first->prev = head;
+        at->prev = last;
+}
+
+/**
+ * list_for_each_rcu    -       iterate over an rcu-protected list
+ * @pos:        the &struct list_head to use as a loop cursor.
+ * @head:       the head for your list.
+ *
+ * This list-traversal primitive may safely run concurrently with
+ * the _rcu list-mutation primitives such as list_add_rcu()
+ * as long as the traversal is guarded by rcu_read_lock().
+ */
+#define list_for_each_rcu(pos, head) \
+        for (pos = rcu_dereference((head)->next); \
+                prefetch(pos->next), pos != (head); \
+                pos = rcu_dereference(pos->next))
+
+#define __list_for_each_rcu(pos, head) \
+        for (pos = rcu_dereference((head)->next); \
+                pos != (head); \
+                pos = rcu_dereference(pos->next))
+
+/**
+ * list_for_each_entry_rcu      -       iterate over rcu list of given type
+ * @pos:        the type * to use as a loop cursor.
+ * @head:       the head for your list.
+ * @member:     the name of the list_struct within the struct.
+ *
+ * This list-traversal primitive may safely run concurrently with
+ * the _rcu list-mutation primitives such as list_add_rcu()
+ * as long as the traversal is guarded by rcu_read_lock().
+ */
+#define list_for_each_entry_rcu(pos, head, member) \
+        for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \
+                prefetch(pos->member.next), &pos->member != (head); \
+                pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member))
+
+
+/**
+ * list_for_each_continue_rcu
+ * @pos:        the &struct list_head to use as a loop cursor.
+ * @head:       the head for your list.
+ *
+ * Iterate over an rcu-protected list, continuing after current point.
+ *
+ * This list-traversal primitive may safely run concurrently with
+ * the _rcu list-mutation primitives such as list_add_rcu()
+ * as long as the traversal is guarded by rcu_read_lock().
+ */
+#define list_for_each_continue_rcu(pos, head) \
+        for ((pos) = rcu_dereference((pos)->next); \
+                prefetch((pos)->next), (pos) != (head); \
+                (pos) = rcu_dereference((pos)->next))
+
+/**
+ * hlist_del_rcu - deletes entry from hash list without re-initialization
+ * @n: the element to delete from the hash list.
+ *
+ * Note: list_unhashed() on entry does not return true after this,
+ * the entry is in an undefined state. It is useful for RCU based
+ * lockfree traversal.
+ *
+ * In particular, it means that we can not poison the forward
+ * pointers that may still be used for walking the hash list.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_add_head_rcu()
+ * or hlist_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_for_each_entry().
+ */
+static inline void hlist_del_rcu(struct hlist_node *n)
+{
+        __hlist_del(n);
+        n->pprev = LIST_POISON2;
+}
+
+/**
+ * hlist_replace_rcu - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * The @old entry will be replaced with the @new entry atomically.
+ */
+static inline void hlist_replace_rcu(struct hlist_node *old,
+                                        struct hlist_node *new)
+{
+        struct hlist_node *next = old->next;
+
+        new->next = next;
+        new->pprev = old->pprev;
+        rcu_assign_pointer(*new->pprev, new);
+        if (next)
+                new->next->pprev = &new->next;
+        old->pprev = LIST_POISON2;
+}
+
+/**
+ * hlist_add_head_rcu
+ * @n: the element to add to the hash list.
+ * @h: the list to add to.
+ *
+ * Description:
+ * Adds the specified element to the specified hlist,
+ * while permitting racing traversals.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_add_head_rcu()
+ * or hlist_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_for_each_entry_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs.  Regardless of the type of CPU, the
+ * list-traversal primitive must be guarded by rcu_read_lock().
+ */
+static inline void hlist_add_head_rcu(struct hlist_node *n,
+                                        struct hlist_head *h)
+{
+        struct hlist_node *first = h->first;
+
+        n->next = first;
+        n->pprev = &h->first;
+        rcu_assign_pointer(h->first, n);
+        if (first)
+                first->pprev = &n->next;
+}
+
+/**
+ * hlist_add_before_rcu
+ * @n: the new element to add to the hash list.
+ * @next: the existing element to add the new element before.
+ *
+ * Description:
+ * Adds the specified element to the specified hlist
+ * before the specified node while permitting racing traversals.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_add_head_rcu()
+ * or hlist_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_for_each_entry_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs.
+ */
+static inline void hlist_add_before_rcu(struct hlist_node *n,
+                                        struct hlist_node *next)
+{
+        n->pprev = next->pprev;
+        n->next = next;
+        rcu_assign_pointer(*(n->pprev), n);
+        next->pprev = &n->next;
+}
+
+/**
+ * hlist_add_after_rcu
+ * @prev: the existing element to add the new element after.
+ * @n: the new element to add to the hash list.
+ *
+ * Description:
+ * Adds the specified element to the specified hlist
+ * after the specified node while permitting racing traversals.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_add_head_rcu()
+ * or hlist_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_for_each_entry_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs.
+ */
+static inline void hlist_add_after_rcu(struct hlist_node *prev,
+                                       struct hlist_node *n)
+{
+        n->next = prev->next;
+        n->pprev = &prev->next;
+        rcu_assign_pointer(prev->next, n);
+        if (n->next)
+                n->next->pprev = &n->next;
+}
+
+/**
+ * hlist_for_each_entry_rcu - iterate over rcu list of given type
+ * @tpos:       the type * to use as a loop cursor.
+ * @pos:        the &struct hlist_node to use as a loop cursor.
+ * @head:       the head for your list.
+ * @member:     the name of the hlist_node within the struct.
+ *
+ * This list-traversal primitive may safely run concurrently with
+ * the _rcu list-mutation primitives such as hlist_add_head_rcu()
+ * as long as the traversal is guarded by rcu_read_lock().
+ */
+#define hlist_for_each_entry_rcu(tpos, pos, head, member)                \
+        for (pos = rcu_dereference((head)->first);                       \
+                pos && ({ prefetch(pos->next); 1; }) &&                  \
+                ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \
+                pos = rcu_dereference(pos->next))
 
-#endif  /* _LINUX_RCULIST_H */
+#endif  /* __KERNEL__ */
+#endif
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index d42dbec06083..e8b4039cfb2f 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -40,6 +40,7 @@
 #include <linux/cpumask.h>
 #include <linux/seqlock.h>
 #include <linux/lockdep.h>
+#include <linux/completion.h>
 
 /**
  * struct rcu_head - callback structure for use with RCU
@@ -168,6 +169,27 @@ struct rcu_head {
                 (p) = (v); \
         })
 
+/* Infrastructure to implement the synchronize_() primitives. */
+
+struct rcu_synchronize {
+        struct rcu_head head;
+        struct completion completion;
+};
+
+extern void wakeme_after_rcu(struct rcu_head  *head);
+
+#define synchronize_rcu_xxx(name, func) \
+void name(void) \
+{ \
+        struct rcu_synchronize rcu; \
+        \
+        init_completion(&rcu.completion); \
+        /* Will wake me after RCU finished. */ \
+        func(&rcu.head, wakeme_after_rcu); \
+        /* Wait for it. */ \
+        wait_for_completion(&rcu.completion); \
+}
+
 /**
  * synchronize_sched - block until all CPUs have exited any non-preemptive
  * kernel code sequences.
@@ -224,8 +246,8 @@ extern void call_rcu_bh(struct rcu_head *head,
 /* Exported common interfaces */
 extern void synchronize_rcu(void);
 extern void rcu_barrier(void);
-extern long rcu_batches_completed(void);
-extern long rcu_batches_completed_bh(void);
+extern void rcu_barrier_bh(void);
+extern void rcu_barrier_sched(void);
 
 /* Internal to kernel */
 extern void rcu_init(void);
diff --git a/include/linux/rcupreempt.h b/include/linux/rcupreempt.h
index 8a05c7e20bc4..f04b64eca636 100644
--- a/include/linux/rcupreempt.h
+++ b/include/linux/rcupreempt.h
@@ -40,10 +40,39 @@
 #include <linux/cpumask.h>
 #include <linux/seqlock.h>
 
-#define rcu_qsctr_inc(cpu)
+struct rcu_dyntick_sched {
+        int dynticks;
+        int dynticks_snap;
+        int sched_qs;
+        int sched_qs_snap;
+        int sched_dynticks_snap;
+};
+
+DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched);
+
+static inline void rcu_qsctr_inc(int cpu)
+{
+        struct rcu_dyntick_sched *rdssp = &per_cpu(rcu_dyntick_sched, cpu);
+
+        rdssp->sched_qs++;
+}
 #define rcu_bh_qsctr_inc(cpu)
 #define call_rcu_bh(head, rcu) call_rcu(head, rcu)
 
+/**
+ * call_rcu_sched - Queue RCU callback for invocation after sched grace period.
+ * @head: structure to be used for queueing the RCU updates.
+ * @func: actual update function to be invoked after the grace period
+ *
+ * The update function will be invoked some time after a full
+ * synchronize_sched()-style grace period elapses, in other words after
+ * all currently executing preempt-disabled sections of code (including
+ * hardirq handlers, NMI handlers, and local_irq_save() blocks) have
+ * completed.
+ */
+extern void call_rcu_sched(struct rcu_head *head,
+                           void (*func)(struct rcu_head *head));
+
 extern void __rcu_read_lock(void)       __acquires(RCU);
 extern void __rcu_read_unlock(void)     __releases(RCU);
 extern int rcu_pending(int cpu);
@@ -55,6 +84,7 @@ extern int rcu_needs_cpu(int cpu);
 extern void __synchronize_sched(void);
 
 extern void __rcu_init(void);
+extern void rcu_init_sched(void);
 extern void rcu_check_callbacks(int cpu, int user);
 extern void rcu_restart_cpu(int cpu);
 extern long rcu_batches_completed(void);
@@ -81,20 +111,20 @@ extern struct rcupreempt_trace *rcupreempt_trace_cpu(int cpu);
 struct softirq_action;
 
 #ifdef CONFIG_NO_HZ
-DECLARE_PER_CPU(long, dynticks_progress_counter);
+DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched);
 
 static inline void rcu_enter_nohz(void)
 {
         smp_mb(); /* CPUs seeing ++ must see prior RCU read-side crit sects */
-        __get_cpu_var(dynticks_progress_counter)++;
-        WARN_ON(__get_cpu_var(dynticks_progress_counter) & 0x1);
+        __get_cpu_var(rcu_dyntick_sched).dynticks++;
+        WARN_ON(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1);
 }
 
 static inline void rcu_exit_nohz(void)
 {
-        __get_cpu_var(dynticks_progress_counter)++;
         smp_mb(); /* CPUs seeing ++ must see later RCU read-side crit sects */
-        WARN_ON(!(__get_cpu_var(dynticks_progress_counter) & 0x1));
+        __get_cpu_var(rcu_dyntick_sched).dynticks++;
+        WARN_ON(!(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1));
 }
 
 #else /* CONFIG_NO_HZ */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index c5d3f847ca8d..1941d8b5cf11 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -134,7 +134,6 @@ extern unsigned long nr_running(void);
 extern unsigned long nr_uninterruptible(void);
 extern unsigned long nr_active(void);
 extern unsigned long nr_iowait(void);
-extern unsigned long weighted_cpuload(const int cpu);
 
 struct seq_file;
 struct cfs_rq;
@@ -246,6 +245,8 @@ extern asmlinkage void schedule_tail(struct task_struct *prev);
 extern void init_idle(struct task_struct *idle, int cpu);
 extern void init_idle_bootup_task(struct task_struct *idle);
 
+extern int runqueue_is_locked(void);
+
 extern cpumask_t nohz_cpu_mask;
 #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ)
 extern int select_nohz_load_balancer(int cpu);
@@ -784,6 +785,8 @@ struct sched_domain {
         unsigned int balance_interval;  /* initialise to 1. units in ms. */
         unsigned int nr_balance_failed; /* initialise to 0 */
 
+        u64 last_update;
+
 #ifdef CONFIG_SCHEDSTATS
         /* load_balance() stats */
         unsigned int lb_count[CPU_MAX_IDLE_TYPES];
@@ -823,23 +826,6 @@ extern int arch_reinit_sched_domains(void);
 
 #endif  /* CONFIG_SMP */
 
-/*
- * A runqueue laden with a single nice 0 task scores a weighted_cpuload of
- * SCHED_LOAD_SCALE. This function returns 1 if any cpu is laden with a
- * task of nice 0 or enough lower priority tasks to bring up the
- * weighted_cpuload
- */
-static inline int above_background_load(void)
-{
-        unsigned long cpu;
-
-        for_each_online_cpu(cpu) {
-                if (weighted_cpuload(cpu) >= SCHED_LOAD_SCALE)
-                        return 1;
-        }
-        return 0;
-}
-
 struct io_context;                      /* See blkdev.h */
 #define NGROUPS_SMALL           32
 #define NGROUPS_PER_BLOCK       ((unsigned int)(PAGE_SIZE / sizeof(gid_t)))
@@ -921,8 +907,8 @@ struct sched_class {
         void (*set_cpus_allowed)(struct task_struct *p,
                                  const cpumask_t *newmask);
 
-        void (*join_domain)(struct rq *rq);
-        void (*leave_domain)(struct rq *rq);
+        void (*rq_online)(struct rq *rq);
+        void (*rq_offline)(struct rq *rq);
 
         void (*switched_from) (struct rq *this_rq, struct task_struct *task,
                                int running);
@@ -1039,6 +1025,7 @@ struct task_struct {
 #endif
 
         int prio, static_prio, normal_prio;
+        unsigned int rt_priority;
         const struct sched_class *sched_class;
         struct sched_entity se;
         struct sched_rt_entity rt;
@@ -1075,12 +1062,6 @@ struct task_struct {
 #endif
 
         struct list_head tasks;
-        /*
-         * ptrace_list/ptrace_children forms the list of my children
-         * that were stolen by a ptracer.
-         */
-        struct list_head ptrace_children;
-        struct list_head ptrace_list;
 
         struct mm_struct *mm, *active_mm;
 
@@ -1102,18 +1083,25 @@ struct task_struct {
         /* 
          * pointers to (original) parent process, youngest child, younger sibling,
          * older sibling, respectively.  (p->father can be replaced with 
-         * p->parent->pid)
+         * p->real_parent->pid)
          */
-        struct task_struct *real_parent; /* real parent process (when being debugged) */
-        struct task_struct *parent;     /* parent process */
+        struct task_struct *real_parent; /* real parent process */
+        struct task_struct *parent; /* recipient of SIGCHLD, wait4() reports */
         /*
-         * children/sibling forms the list of my children plus the
-         * tasks I'm ptracing.
+         * children/sibling forms the list of my natural children
          */
         struct list_head children;      /* list of my children */
         struct list_head sibling;       /* linkage in my parent's children list */
         struct task_struct *group_leader;       /* threadgroup leader */
 
+        /*
+         * ptraced is the list of tasks this task is using ptrace on.
+         * This includes both natural children and PTRACE_ATTACH targets.
+         * p->ptrace_entry is p's link on the p->parent->ptraced list.
+         */
+        struct list_head ptraced;
+        struct list_head ptrace_entry;
+
         /* PID/PID hash table linkage. */
         struct pid_link pids[PIDTYPE_MAX];
         struct list_head thread_group;
@@ -1122,7 +1110,6 @@ struct task_struct {
         int __user *set_child_tid;              /* CLONE_CHILD_SETTID */
         int __user *clear_child_tid;            /* CLONE_CHILD_CLEARTID */
 
-        unsigned int rt_priority;
         cputime_t utime, stime, utimescaled, stimescaled;
         cputime_t gtime;
         cputime_t prev_utime, prev_stime;
@@ -1141,12 +1128,12 @@ struct task_struct {
         gid_t gid,egid,sgid,fsgid;
         struct group_info *group_info;
         kernel_cap_t   cap_effective, cap_inheritable, cap_permitted, cap_bset;
-        unsigned securebits;
         struct user_struct *user;
+        unsigned securebits;
 #ifdef CONFIG_KEYS
+        unsigned char jit_keyring;      /* default keyring to attach requested keys to */
         struct key *request_key_auth;   /* assumed request_key authority */
         struct key *thread_keyring;     /* keyring private to this thread */
-        unsigned char jit_keyring;      /* default keyring to attach requested keys to */
 #endif
         char comm[TASK_COMM_LEN]; /* executable name excluding path
                                      - access with [gs]et_task_comm (which lock
@@ -1233,8 +1220,8 @@ struct task_struct {
 # define MAX_LOCK_DEPTH 48UL
         u64 curr_chain_key;
         int lockdep_depth;
-        struct held_lock held_locks[MAX_LOCK_DEPTH];
         unsigned int lockdep_recursion;
+        struct held_lock held_locks[MAX_LOCK_DEPTH];
 #endif
 
 /* journalling filesystem info */
@@ -1262,10 +1249,6 @@ struct task_struct {
         u64 acct_vm_mem1;       /* accumulated virtual memory usage */
         cputime_t acct_stimexpd;/* stime since last update */
 #endif
-#ifdef CONFIG_NUMA
-        struct mempolicy *mempolicy;
-        short il_next;
-#endif
 #ifdef CONFIG_CPUSETS
         nodemask_t mems_allowed;
         int cpuset_mems_generation;
@@ -1285,6 +1268,10 @@ struct task_struct {
         struct list_head pi_state_list;
         struct futex_pi_state *pi_state_cache;
 #endif
+#ifdef CONFIG_NUMA
+        struct mempolicy *mempolicy;
+        short il_next;
+#endif
         atomic_t fs_excl;       /* holding fs exclusive resources */
         struct rcu_head rcu;
 
@@ -1504,9 +1491,11 @@ static inline void put_task_struct(struct task_struct *t)
 #define PF_SWAPWRITE    0x00800000      /* Allowed to write to swap */
 #define PF_SPREAD_PAGE  0x01000000      /* Spread page cache over cpuset */
 #define PF_SPREAD_SLAB  0x02000000      /* Spread some slab caches over cpuset */
+#define PF_THREAD_BOUND 0x04000000      /* Thread bound to specific cpu */
 #define PF_MEMPOLICY    0x10000000      /* Non-default NUMA mempolicy */
 #define PF_MUTEX_TESTER 0x20000000      /* Thread belongs to the rt mutex tester */
 #define PF_FREEZER_SKIP 0x40000000      /* Freezer should not count it as freezeable */
+#define PF_FREEZER_NOSIG 0x80000000     /* Freezer won't send signals to it */
 
 /*
  * Only the _current_ task can read/write to tsk->flags, but other
@@ -1573,13 +1562,28 @@ static inline void sched_clock_idle_sleep_event(void)
 static inline void sched_clock_idle_wakeup_event(u64 delta_ns)
 {
 }
-#else
+
+#ifdef CONFIG_NO_HZ
+static inline void sched_clock_tick_stop(int cpu)
+{
+}
+
+static inline void sched_clock_tick_start(int cpu)
+{
+}
+#endif
+
+#else /* CONFIG_HAVE_UNSTABLE_SCHED_CLOCK */
 extern void sched_clock_init(void);
 extern u64 sched_clock_cpu(int cpu);
 extern void sched_clock_tick(void);
 extern void sched_clock_idle_sleep_event(void);
 extern void sched_clock_idle_wakeup_event(u64 delta_ns);
+#ifdef CONFIG_NO_HZ
+extern void sched_clock_tick_stop(int cpu);
+extern void sched_clock_tick_start(int cpu);
 #endif
+#endif /* CONFIG_HAVE_UNSTABLE_SCHED_CLOCK */
 
 /*
  * For kernel-internal use: high-speed (but slightly incorrect) per-cpu
@@ -1622,6 +1626,7 @@ extern unsigned int sysctl_sched_child_runs_first;
 extern unsigned int sysctl_sched_features;
 extern unsigned int sysctl_sched_migration_cost;
 extern unsigned int sysctl_sched_nr_migrate;
+extern unsigned int sysctl_sched_shares_ratelimit;
 
 int sched_nr_latency_handler(struct ctl_table *table, int write,
                 struct file *file, void __user *buffer, size_t *length,
@@ -1655,6 +1660,8 @@ extern int can_nice(const struct task_struct *p, const int nice);
 extern int task_curr(const struct task_struct *p);
 extern int idle_cpu(int cpu);
 extern int sched_setscheduler(struct task_struct *, int, struct sched_param *);
+extern int sched_setscheduler_nocheck(struct task_struct *, int,
+                                      struct sched_param *);
 extern struct task_struct *idle_task(int cpu);
 extern struct task_struct *curr_task(int cpu);
 extern void set_curr_task(int cpu, struct task_struct *p);
@@ -1870,9 +1877,6 @@ extern void wait_task_inactive(struct task_struct * p);
 #define wait_task_inactive(p)   do { } while (0)
 #endif
 
-#define remove_parent(p)        list_del_init(&(p)->sibling)
-#define add_parent(p)           list_add_tail(&(p)->sibling,&(p)->parent->children)
-
 #define next_task(p)    list_entry(rcu_dereference((p)->tasks.next), struct task_struct, tasks)
 
 #define for_each_process(p) \
@@ -2131,6 +2135,18 @@ static inline void arch_pick_mmap_layout(struct mm_struct *mm)
 }
 #endif
 
+#ifdef CONFIG_TRACING
+extern void
+__trace_special(void *__tr, void *__data,
+                unsigned long arg1, unsigned long arg2, unsigned long arg3);
+#else
+static inline void
+__trace_special(void *__tr, void *__data,
+                unsigned long arg1, unsigned long arg2, unsigned long arg3)
+{
+}
+#endif
+
 extern long sched_setaffinity(pid_t pid, const cpumask_t *new_mask);
 extern long sched_getaffinity(pid_t pid, cpumask_t *mask);
 
@@ -2225,6 +2241,8 @@ static inline void mm_init_owner(struct mm_struct *mm, struct task_struct *p)
 }
 #endif /* CONFIG_MM_OWNER */
 
+#define TASK_STATE_TO_CHAR_STR "RSDTtZX"
+
 #endif /* __KERNEL__ */
 
 #endif
diff --git a/include/linux/security.h b/include/linux/security.h
index 50737c70e78e..31c8851ec5d0 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -46,7 +46,8 @@ struct audit_krule;
  */
 extern int cap_capable(struct task_struct *tsk, int cap);
 extern int cap_settime(struct timespec *ts, struct timezone *tz);
-extern int cap_ptrace(struct task_struct *parent, struct task_struct *child);
+extern int cap_ptrace(struct task_struct *parent, struct task_struct *child,
+                      unsigned int mode);
 extern int cap_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
 extern int cap_capset_check(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
 extern void cap_capset_set(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
@@ -79,6 +80,7 @@ struct xfrm_selector;
 struct xfrm_policy;
 struct xfrm_state;
 struct xfrm_user_sec_ctx;
+struct seq_file;
 
 extern int cap_netlink_send(struct sock *sk, struct sk_buff *skb);
 extern int cap_netlink_recv(struct sk_buff *skb, int cap);
@@ -289,10 +291,6 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *      Update module state after a successful pivot.
  *      @old_path contains the path for the old root.
  *      @new_path contains the path for the new root.
- * @sb_get_mnt_opts:
- *      Get the security relevant mount options used for a superblock
- *      @sb the superblock to get security mount options from
- *      @opts binary data structure containing all lsm mount data
  * @sb_set_mnt_opts:
  *      Set the security relevant mount options used for a superblock
  *      @sb the superblock to set security mount options for
@@ -1170,6 +1168,7 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *      attributes would be changed by the execve.
  *      @parent contains the task_struct structure for parent process.
  *      @child contains the task_struct structure for child process.
+ *      @mode contains the PTRACE_MODE flags indicating the form of access.
  *      Return 0 if permission is granted.
  * @capget:
  *      Get the @effective, @inheritable, and @permitted capability sets for
@@ -1240,11 +1239,6 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *      @pages contains the number of pages.
  *      Return 0 if permission is granted.
  *
- * @register_security:
- *      allow module stacking.
- *      @name contains the name of the security module being stacked.
- *      @ops contains a pointer to the struct security_operations of the module to stack.
- *
  * @secid_to_secctx:
  *      Convert secid to security context.
  *      @secid contains the security ID.
@@ -1295,7 +1289,8 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
 struct security_operations {
         char name[SECURITY_NAME_MAX + 1];
 
-        int (*ptrace) (struct task_struct *parent, struct task_struct *child);
+        int (*ptrace) (struct task_struct *parent, struct task_struct *child,
+                       unsigned int mode);
         int (*capget) (struct task_struct *target,
                        kernel_cap_t *effective,
                        kernel_cap_t *inheritable, kernel_cap_t *permitted);
@@ -1328,6 +1323,7 @@ struct security_operations {
         void (*sb_free_security) (struct super_block *sb);
         int (*sb_copy_data) (char *orig, char *copy);
         int (*sb_kern_mount) (struct super_block *sb, void *data);
+        int (*sb_show_options) (struct seq_file *m, struct super_block *sb);
         int (*sb_statfs) (struct dentry *dentry);
         int (*sb_mount) (char *dev_name, struct path *path,
                          char *type, unsigned long flags, void *data);
@@ -1343,8 +1339,6 @@ struct security_operations {
                              struct path *new_path);
         void (*sb_post_pivotroot) (struct path *old_path,
                                    struct path *new_path);
-        int (*sb_get_mnt_opts) (const struct super_block *sb,
-                                struct security_mnt_opts *opts);
         int (*sb_set_mnt_opts) (struct super_block *sb,
                                 struct security_mnt_opts *opts);
         void (*sb_clone_mnt_opts) (const struct super_block *oldsb,
@@ -1472,10 +1466,6 @@ struct security_operations {
         int (*netlink_send) (struct sock *sk, struct sk_buff *skb);
         int (*netlink_recv) (struct sk_buff *skb, int cap);
 
-        /* allow module stacking */
-        int (*register_security) (const char *name,
-                                  struct security_operations *ops);
-
         void (*d_instantiate) (struct dentry *dentry, struct inode *inode);
 
         int (*getprocattr) (struct task_struct *p, char *name, char **value);
@@ -1565,7 +1555,6 @@ struct security_operations {
 extern int security_init(void);
 extern int security_module_enable(struct security_operations *ops);
 extern int register_security(struct security_operations *ops);
-extern int mod_reg_security(const char *name, struct security_operations *ops);
 extern struct dentry *securityfs_create_file(const char *name, mode_t mode,
                                              struct dentry *parent, void *data,
                                              const struct file_operations *fops);
@@ -1573,7 +1562,8 @@ extern struct dentry *securityfs_create_dir(const char *name, struct dentry *par
 extern void securityfs_remove(struct dentry *dentry);
 
 /* Security operations */
-int security_ptrace(struct task_struct *parent, struct task_struct *child);
+int security_ptrace(struct task_struct *parent, struct task_struct *child,
+                    unsigned int mode);
 int security_capget(struct task_struct *target,
                     kernel_cap_t *effective,
                     kernel_cap_t *inheritable,
@@ -1606,6 +1596,7 @@ int security_sb_alloc(struct super_block *sb);
 void security_sb_free(struct super_block *sb);
 int security_sb_copy_data(char *orig, char *copy);
 int security_sb_kern_mount(struct super_block *sb, void *data);
+int security_sb_show_options(struct seq_file *m, struct super_block *sb);
 int security_sb_statfs(struct dentry *dentry);
 int security_sb_mount(char *dev_name, struct path *path,
                       char *type, unsigned long flags, void *data);
@@ -1617,8 +1608,6 @@ void security_sb_post_remount(struct vfsmount *mnt, unsigned long flags, void *d
 void security_sb_post_addmount(struct vfsmount *mnt, struct path *mountpoint);
 int security_sb_pivotroot(struct path *old_path, struct path *new_path);
 void security_sb_post_pivotroot(struct path *old_path, struct path *new_path);
-int security_sb_get_mnt_opts(const struct super_block *sb,
-                                struct security_mnt_opts *opts);
 int security_sb_set_mnt_opts(struct super_block *sb, struct security_mnt_opts *opts);
 void security_sb_clone_mnt_opts(const struct super_block *oldsb,
                                 struct super_block *newsb);
@@ -1755,9 +1744,11 @@ static inline int security_init(void)
         return 0;
 }
 
-static inline int security_ptrace(struct task_struct *parent, struct task_struct *child)
+static inline int security_ptrace(struct task_struct *parent,
+                                  struct task_struct *child,
+                                  unsigned int mode)
 {
-        return cap_ptrace(parent, child);
+        return cap_ptrace(parent, child, mode);
 }
 
 static inline int security_capget(struct task_struct *target,
@@ -1881,6 +1872,12 @@ static inline int security_sb_kern_mount(struct super_block *sb, void *data)
         return 0;
 }
 
+static inline int security_sb_show_options(struct seq_file *m,
+                                           struct super_block *sb)
+{
+        return 0;
+}
+
 static inline int security_sb_statfs(struct dentry *dentry)
 {
         return 0;
@@ -1927,12 +1924,6 @@ static inline int security_sb_pivotroot(struct path *old_path,
 static inline void security_sb_post_pivotroot(struct path *old_path,
                                               struct path *new_path)
 { }
-static inline int security_sb_get_mnt_opts(const struct super_block *sb,
-                                           struct security_mnt_opts *opts)
-{
-        security_init_mnt_opts(opts);
-        return 0;
-}
 
 static inline int security_sb_set_mnt_opts(struct super_block *sb,
                                            struct security_mnt_opts *opts)
diff --git a/include/linux/smp.h b/include/linux/smp.h
index 55232ccf9cfd..48262f86c969 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -7,9 +7,18 @@
  */
 
 #include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/cpumask.h>
 
 extern void cpu_idle(void);
 
+struct call_single_data {
+        struct list_head list;
+        void (*func) (void *info);
+        void *info;
+        unsigned int flags;
+};
+
 #ifdef CONFIG_SMP
 
 #include <linux/preempt.h>
@@ -52,15 +61,34 @@ extern void smp_cpus_done(unsigned int max_cpus);
 /*
  * Call a function on all other processors
  */
-int smp_call_function(void(*func)(void *info), void *info, int retry, int wait);
-
+int smp_call_function(void(*func)(void *info), void *info, int wait);
+int smp_call_function_mask(cpumask_t mask, void(*func)(void *info), void *info,
+                                int wait);
 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
-                                int retry, int wait);
+                                int wait);
+void __smp_call_function_single(int cpuid, struct call_single_data *data);
+
+/*
+ * Generic and arch helpers
+ */
+#ifdef CONFIG_USE_GENERIC_SMP_HELPERS
+void generic_smp_call_function_single_interrupt(void);
+void generic_smp_call_function_interrupt(void);
+void init_call_single_data(void);
+void ipi_call_lock(void);
+void ipi_call_unlock(void);
+void ipi_call_lock_irq(void);
+void ipi_call_unlock_irq(void);
+#else
+static inline void init_call_single_data(void)
+{
+}
+#endif
 
 /*
  * Call a function on all processors
  */
-int on_each_cpu(void (*func) (void *info), void *info, int retry, int wait);
+int on_each_cpu(void (*func) (void *info), void *info, int wait);
 
 #define MSG_ALL_BUT_SELF        0x8000  /* Assume <32768 CPU's */
 #define MSG_ALL                 0x8001
@@ -90,9 +118,9 @@ static inline int up_smp_call_function(void (*func)(void *), void *info)
 {
         return 0;
 }
-#define smp_call_function(func, info, retry, wait) \
+#define smp_call_function(func, info, wait) \
                         (up_smp_call_function(func, info))
-#define on_each_cpu(func,info,retry,wait)       \
+#define on_each_cpu(func,info,wait)             \
         ({                                      \
                 local_irq_disable();            \
                 func(info);                     \
@@ -102,7 +130,7 @@ static inline int up_smp_call_function(void (*func)(void *), void *info)
 static inline void smp_send_reschedule(int cpu) { }
 #define num_booting_cpus()                      1
 #define smp_prepare_boot_cpu()                  do {} while (0)
-#define smp_call_function_single(cpuid, func, info, retry, wait) \
+#define smp_call_function_single(cpuid, func, info, wait) \
 ({ \
         WARN_ON(cpuid != 0);    \
         local_irq_disable();    \
@@ -112,7 +140,9 @@ static inline void smp_send_reschedule(int cpu) { }
 })
 #define smp_call_function_mask(mask, func, info, wait) \
                         (up_smp_call_function(func, info))
-
+static inline void init_call_single_data(void)
+{
+}
 #endif /* !SMP */
 
 /*
diff --git a/include/linux/smp_lock.h b/include/linux/smp_lock.h
index aab3a4cff4e1..813be59bf345 100644
--- a/include/linux/smp_lock.h
+++ b/include/linux/smp_lock.h
@@ -27,11 +27,24 @@ static inline int reacquire_kernel_lock(struct task_struct *task)
 extern void __lockfunc lock_kernel(void)        __acquires(kernel_lock);
 extern void __lockfunc unlock_kernel(void)      __releases(kernel_lock);
 
+/*
+ * Various legacy drivers don't really need the BKL in a specific
+ * function, but they *do* need to know that the BKL became available.
+ * This function just avoids wrapping a bunch of lock/unlock pairs
+ * around code which doesn't really need it.
+ */
+static inline void cycle_kernel_lock(void)
+{
+        lock_kernel();
+        unlock_kernel();
+}
+
 #else
 
 #define lock_kernel()                           do { } while(0)
 #define unlock_kernel()                         do { } while(0)
 #define release_kernel_lock(task)               do { } while(0)
+#define cycle_kernel_lock()                     do { } while(0)
 #define reacquire_kernel_lock(task)             0
 #define kernel_locked()                         1
 
diff --git a/include/linux/spi/mmc_spi.h b/include/linux/spi/mmc_spi.h
index d5ca78b93a3b..a3626aedaec9 100644
--- a/include/linux/spi/mmc_spi.h
+++ b/include/linux/spi/mmc_spi.h
@@ -23,6 +23,15 @@ struct mmc_spi_platform_data {
         /* sense switch on sd cards */
         int (*get_ro)(struct device *);
 
+        /*
+         * If board does not use CD interrupts, driver can optimize polling
+         * using this function.
+         */
+        int (*get_cd)(struct device *);
+
+        /* Capabilities to pass into mmc core (e.g. MMC_CAP_NEEDS_POLL). */
+        unsigned long caps;
+
         /* how long to debounce card detect, in msecs */
         u16 detect_delay;
 
diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h
index 6fff7f82ef12..e5bfe01ee305 100644
--- a/include/linux/sunrpc/clnt.h
+++ b/include/linux/sunrpc/clnt.h
@@ -42,7 +42,8 @@ struct rpc_clnt {
 
         unsigned int            cl_softrtry : 1,/* soft timeouts */
                                 cl_discrtry : 1,/* disconnect before retry */
-                                cl_autobind : 1;/* use getport() */
+                                cl_autobind : 1,/* use getport() */
+                                cl_chatty   : 1;/* be verbose */
 
         struct rpc_rtt *        cl_rtt;         /* RTO estimator data */
         const struct rpc_timeout *cl_timeout;   /* Timeout strategy */
@@ -114,6 +115,7 @@ struct rpc_create_args {
 #define RPC_CLNT_CREATE_NONPRIVPORT     (1UL << 3)
 #define RPC_CLNT_CREATE_NOPING          (1UL << 4)
 #define RPC_CLNT_CREATE_DISCRTRY        (1UL << 5)
+#define RPC_CLNT_CREATE_QUIET           (1UL << 6)
 
 struct rpc_clnt *rpc_create(struct rpc_create_args *args);
 struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *,
@@ -123,6 +125,9 @@ void		rpc_shutdown_client(struct rpc_clnt *);
 void            rpc_release_client(struct rpc_clnt *);
 
 int             rpcb_register(u32, u32, int, unsigned short, int *);
+int             rpcb_v4_register(const u32 program, const u32 version,
+                                 const struct sockaddr *address,
+                                 const char *netid, int *result);
 int             rpcb_getport_sync(struct sockaddr_in *, u32, u32, int);
 void            rpcb_getport_async(struct rpc_task *);
 
diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h
index d1a5c8c1a0f1..64981a2f1cae 100644
--- a/include/linux/sunrpc/sched.h
+++ b/include/linux/sunrpc/sched.h
@@ -135,7 +135,6 @@ struct rpc_task_setup {
 #define RPC_IS_SWAPPER(t)       ((t)->tk_flags & RPC_TASK_SWAPPER)
 #define RPC_DO_ROOTOVERRIDE(t)  ((t)->tk_flags & RPC_TASK_ROOTCREDS)
 #define RPC_ASSASSINATED(t)     ((t)->tk_flags & RPC_TASK_KILLED)
-#define RPC_DO_CALLBACK(t)      ((t)->tk_callback != NULL)
 #define RPC_IS_SOFT(t)          ((t)->tk_flags & RPC_TASK_SOFT)
 
 #define RPC_TASK_RUNNING        0
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index a6977423baf7..e8e69159af71 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -86,6 +86,11 @@ typedef int __bitwise suspend_state_t;
  *      that implement @begin(), but platforms implementing @begin() should
  *      also provide a @end() which cleans up transitions aborted before
  *      @enter().
+ *
+ * @recover: Recover the platform from a suspend failure.
+ *      Called by the PM core if the suspending of devices fails.
+ *      This callback is optional and should only be implemented by platforms
+ *      which require special recovery actions in that situation.
  */
 struct platform_suspend_ops {
         int (*valid)(suspend_state_t state);
@@ -94,6 +99,7 @@ struct platform_suspend_ops {
         int (*enter)(suspend_state_t state);
         void (*finish)(void);
         void (*end)(void);
+        void (*recover)(void);
 };
 
 #ifdef CONFIG_SUSPEND
@@ -149,7 +155,7 @@ extern void mark_free_pages(struct zone *zone);
  * The methods in this structure allow a platform to carry out special
  * operations required by it during a hibernation transition.
  *
- * All the methods below must be implemented.
+ * All the methods below, except for @recover(), must be implemented.
  *
  * @begin: Tell the platform driver that we're starting hibernation.
  *      Called right after shrinking memory and before freezing devices.
@@ -189,6 +195,11 @@ extern void mark_free_pages(struct zone *zone);
  * @restore_cleanup: Clean up after a failing image restoration.
  *      Called right after the nonboot CPUs have been enabled and before
  *      thawing devices (runs with IRQs on).
+ *
+ * @recover: Recover the platform from a failure to suspend devices.
+ *      Called by the PM core if the suspending of devices during hibernation
+ *      fails.  This callback is optional and should only be implemented by
+ *      platforms which require special recovery actions in that situation.
  */
 struct platform_hibernation_ops {
         int (*begin)(void);
@@ -200,6 +211,7 @@ struct platform_hibernation_ops {
         void (*leave)(void);
         int (*pre_restore)(void);
         void (*restore_cleanup)(void);
+        void (*recover)(void);
 };
 
 #ifdef CONFIG_HIBERNATION
diff --git a/include/linux/topology.h b/include/linux/topology.h
index 24f3d2282e11..2158fc0d5a56 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -179,4 +179,17 @@ void arch_update_cpu_topology(void);
 #endif
 #endif /* CONFIG_NUMA */
 
+#ifndef topology_physical_package_id
+#define topology_physical_package_id(cpu)       ((void)(cpu), -1)
+#endif
+#ifndef topology_core_id
+#define topology_core_id(cpu)                   ((void)(cpu), 0)
+#endif
+#ifndef topology_thread_siblings
+#define topology_thread_siblings(cpu)           cpumask_of_cpu(cpu)
+#endif
+#ifndef topology_core_siblings
+#define topology_core_siblings(cpu)             cpumask_of_cpu(cpu)
+#endif
+
 #endif /* _LINUX_TOPOLOGY_H */
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index f462439cc288..12b15c561a1f 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -63,6 +63,7 @@ struct writeback_control {
         unsigned for_writepages:1;      /* This is a writepages() call */
         unsigned range_cyclic:1;        /* range_start is cyclic */
         unsigned more_io:1;             /* more io to be dispatched */
+        unsigned range_cont:1;
 };
 
 /*
@@ -105,6 +106,8 @@ extern int vm_highmem_is_dirtyable;
 extern int block_dump;
 extern int laptop_mode;
 
+extern unsigned long determine_dirtyable_memory(void);
+
 extern int dirty_ratio_handler(struct ctl_table *table, int write,
                 struct file *filp, void __user *buffer, size_t *lenp,
                 loff_t *ppos);
diff --git a/include/pcmcia/bulkmem.h b/include/pcmcia/bulkmem.h
deleted file mode 100644
index 6bc7472293b2..000000000000
--- a/include/pcmcia/bulkmem.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * bulkmem.h -- Definitions for bulk memory services
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
- *
- * (C) 1999             David A. Hinds
- */
-
-#ifndef _LINUX_BULKMEM_H
-#define _LINUX_BULKMEM_H
-
-/* For GetFirstRegion and GetNextRegion */
-typedef struct region_info_t {
-    u_int               Attributes;
-    u_int               CardOffset;
-    u_int               RegionSize;
-    u_int               AccessSpeed;
-    u_int               BlockSize;
-    u_int               PartMultiple;
-    u_char              JedecMfr, JedecInfo;
-    memory_handle_t     next;
-} region_info_t;
-
-#define REGION_TYPE             0x0001
-#define REGION_TYPE_CM          0x0000
-#define REGION_TYPE_AM          0x0001
-#define REGION_PREFETCH         0x0008
-#define REGION_CACHEABLE        0x0010
-#define REGION_BAR_MASK         0xe000
-#define REGION_BAR_SHIFT        13
-
-int pcmcia_get_first_region(struct pcmcia_device *handle, region_info_t *rgn);
-int pcmcia_get_next_region(struct pcmcia_device *handle, region_info_t *rgn);
-
-#endif /* _LINUX_BULKMEM_H */
diff --git a/include/pcmcia/cistpl.h b/include/pcmcia/cistpl.h
index d3bbb19caf81..e2e10c1e9a06 100644
--- a/include/pcmcia/cistpl.h
+++ b/include/pcmcia/cistpl.h
@@ -595,7 +595,7 @@ int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function, tuple
 int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple);
 int pccard_parse_tuple(tuple_t *tuple, cisparse_t *parse);
 
-int pccard_validate_cis(struct pcmcia_socket *s, unsigned int function, cisinfo_t *info);
+int pccard_validate_cis(struct pcmcia_socket *s, unsigned int function, unsigned int *count);
 
 /* ... but use these wrappers instead */
 #define pcmcia_get_first_tuple(p_dev, tuple) \
diff --git a/include/pcmcia/cs.h b/include/pcmcia/cs.h
index 87a260e3699e..45d84b275789 100644
--- a/include/pcmcia/cs.h
+++ b/include/pcmcia/cs.h
@@ -373,9 +373,6 @@ struct pcmcia_socket;
 
 int pcmcia_access_configuration_register(struct pcmcia_device *p_dev, conf_reg_t *reg);
 int pcmcia_get_configuration_info(struct pcmcia_device *p_dev, config_info_t *config);
-int pcmcia_get_first_window(window_handle_t *win, win_req_t *req);
-int pcmcia_get_next_window(window_handle_t *win, win_req_t *req);
-int pcmcia_get_status(struct pcmcia_device *p_dev, cs_status_t *status);
 int pcmcia_get_mem_page(window_handle_t win, memreq_t *req);
 int pcmcia_map_mem_page(window_handle_t win, memreq_t *req);
 int pcmcia_modify_configuration(struct pcmcia_device *p_dev, modconf_t *mod);
diff --git a/include/pcmcia/cs_types.h b/include/pcmcia/cs_types.h
index 9a6bcc4952f0..f402a0f435b4 100644
--- a/include/pcmcia/cs_types.h
+++ b/include/pcmcia/cs_types.h
@@ -21,7 +21,8 @@
 #include <sys/types.h>
 #endif
 
-#if defined(__arm__) || defined(__mips__) || defined(__avr32__)
+#if defined(__arm__) || defined(__mips__) || defined(__avr32__) || \
+        defined(__bfin__)
 /* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */
 typedef u_int   ioaddr_t;
 #else
@@ -33,9 +34,6 @@ typedef u_int	event_t;
 typedef u_char  cisdata_t;
 typedef u_short page_t;
 
-struct pcmcia_device;
-typedef struct pcmcia_device *client_handle_t;
-
 struct window_t;
 typedef struct window_t *window_handle_t;
 
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index f047a1fd64f8..b316027c853d 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -20,7 +20,6 @@
 #include <linux/mod_devicetable.h>
 #endif
 
-#include <pcmcia/bulkmem.h>
 #include <pcmcia/cs_types.h>
 #include <pcmcia/device_id.h>
 
@@ -51,6 +50,24 @@ typedef struct mtd_info_t {
     u_int               CardOffset;
 } mtd_info_t;
 
+typedef struct region_info_t {
+    u_int               Attributes;
+    u_int               CardOffset;
+    u_int               RegionSize;
+    u_int               AccessSpeed;
+    u_int               BlockSize;
+    u_int               PartMultiple;
+    u_char              JedecMfr, JedecInfo;
+    memory_handle_t     next;
+} region_info_t;
+#define REGION_TYPE             0x0001
+#define REGION_TYPE_CM          0x0000
+#define REGION_TYPE_AM          0x0001
+#define REGION_PREFETCH         0x0008
+#define REGION_CACHEABLE        0x0010
+#define REGION_BAR_MASK         0xe000
+#define REGION_BAR_SHIFT        13
+
 typedef union ds_ioctl_arg_t {
     adjust_t            adjust;
     config_info_t       config;
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index f95dca077c1c..ed919dd9bb5c 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -21,7 +21,6 @@
 
 #include <pcmcia/cs_types.h>
 #include <pcmcia/cs.h>
-#include <pcmcia/bulkmem.h>
 #ifdef CONFIG_CARDBUS
 #include <linux/pci.h>
 #endif
@@ -136,8 +135,14 @@ struct pccard_resource_ops {
         struct resource* (*find_mem)    (unsigned long base, unsigned long num,
                                          unsigned long align, int low,
                                          struct pcmcia_socket *s);
-        int     (*adjust_resource)      (struct pcmcia_socket *s,
-                                         adjust_t *adj);
+        int     (*add_io)               (struct pcmcia_socket *s,
+                                         unsigned int action,
+                                         unsigned long r_start,
+                                         unsigned long r_end);
+        int     (*add_mem)              (struct pcmcia_socket *s,
+                                         unsigned int action,
+                                         unsigned long r_start,
+                                         unsigned long r_end);
         int     (*init)                 (struct pcmcia_socket *s);
         void    (*exit)                 (struct pcmcia_socket *s);
 };
@@ -245,7 +250,6 @@ struct pcmcia_socket {
 
         struct task_struct              *thread;
         struct completion               thread_done;
-        wait_queue_head_t               thread_wait;
         spinlock_t                      thread_lock;    /* protects thread_events */
         unsigned int                    thread_events;
 
diff --git a/include/pcmcia/version.h b/include/pcmcia/version.h
deleted file mode 100644
index 5ad9c5e198b6..000000000000
--- a/include/pcmcia/version.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* version.h 1.94 2000/10/03 17:55:48 (David Hinds) */
-
-/* This file will be removed, please don't include it */
diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h
index c36750ff6ae8..483057b2f4b4 100644
--- a/include/rdma/ib_addr.h
+++ b/include/rdma/ib_addr.h
@@ -2,29 +2,33 @@
  * Copyright (c) 2005 Voltaire Inc.  All rights reserved.
  * Copyright (c) 2005 Intel Corporation.  All rights reserved.
  *
- * This Software is licensed under one of the following licenses:
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
  *
- * 1) under the terms of the "Common Public License 1.0" a copy of which is
- *    available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/cpl.php.
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
  *
- * 2) under the terms of the "The BSD License" a copy of which is
- *    available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/bsd-license.php.
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
  *
- * 3) under the terms of the "GNU General Public License (GPL) Version 2" a
- *    copy of which is available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/gpl-license.php.
- *
- * Licensee has the right to choose one of the above licenses.
- *
- * Redistributions of source code must retain the above copyright
- * notice and one of the license notices.
- *
- * Redistributions in binary form must reproduce both the above copyright
- * notice, one of the license notices in the documentation
- * and/or other materials provided with the distribution.
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
  *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
  */
 
 #if !defined(IB_ADDR_H)
@@ -57,6 +61,7 @@ struct rdma_dev_addr {
         unsigned char dst_dev_addr[MAX_ADDR_LEN];
         unsigned char broadcast[MAX_ADDR_LEN];
         enum rdma_node_type dev_type;
+        struct net_device *src_dev;
 };
 
 /**
diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h
index f179d233ffc3..00a2b8ec327f 100644
--- a/include/rdma/ib_cache.h
+++ b/include/rdma/ib_cache.h
@@ -30,8 +30,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_cache.h 1349 2004-12-16 21:09:43Z roland $
  */
 
 #ifndef _IB_CACHE_H
diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h
index a627c8682d2f..ec7c6d99ed3f 100644
--- a/include/rdma/ib_cm.h
+++ b/include/rdma/ib_cm.h
@@ -31,8 +31,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_cm.h 4311 2005-12-05 18:42:01Z sean.hefty $
  */
 #if !defined(IB_CM_H)
 #define IB_CM_H
diff --git a/include/rdma/ib_fmr_pool.h b/include/rdma/ib_fmr_pool.h
index 00dadbf94e1d..f62b842e6596 100644
--- a/include/rdma/ib_fmr_pool.h
+++ b/include/rdma/ib_fmr_pool.h
@@ -29,8 +29,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $
  */
 
 #if !defined(IB_FMR_POOL_H)
@@ -61,7 +59,7 @@ struct ib_fmr_pool_param {
         int                     pool_size;
         int                     dirty_watermark;
         void                  (*flush_function)(struct ib_fmr_pool *pool,
-                                                void *              arg);
+                                                void               *arg);
         void                   *flush_arg;
         unsigned                cache:1;
 };
diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h
index 7228c056b9e9..5f6c40fffcf4 100644
--- a/include/rdma/ib_mad.h
+++ b/include/rdma/ib_mad.h
@@ -32,11 +32,9 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_mad.h 5596 2006-03-03 01:00:07Z sean.hefty $
  */
 
-#if !defined( IB_MAD_H )
+#if !defined(IB_MAD_H)
 #define IB_MAD_H
 
 #include <linux/list.h>
@@ -194,8 +192,7 @@ struct ib_vendor_mad {
         u8                      data[IB_MGMT_VENDOR_DATA];
 };
 
-struct ib_class_port_info
-{
+struct ib_class_port_info {
         u8                      base_version;
         u8                      class_version;
         __be16                  capability_mask;
@@ -614,11 +611,11 @@ int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
  * any class specific header, and MAD data area.
  * If @rmpp_active is set, the RMPP header will be initialized for sending.
  */
-struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent,
-                                            u32 remote_qpn, u16 pkey_index,
-                                            int rmpp_active,
-                                            int hdr_len, int data_len,
-                                            gfp_t gfp_mask);
+struct ib_mad_send_buf *ib_create_send_mad(struct ib_mad_agent *mad_agent,
+                                           u32 remote_qpn, u16 pkey_index,
+                                           int rmpp_active,
+                                           int hdr_len, int data_len,
+                                           gfp_t gfp_mask);
 
 /**
  * ib_is_mad_class_rmpp - returns whether given management class
diff --git a/include/rdma/ib_pack.h b/include/rdma/ib_pack.h
index f926020d6331..d7fc45c4eba9 100644
--- a/include/rdma/ib_pack.h
+++ b/include/rdma/ib_pack.h
@@ -28,8 +28,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_pack.h 1349 2004-12-16 21:09:43Z roland $
  */
 
 #ifndef IB_PACK_H
diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h
index 942692b0b92e..3841c1aff692 100644
--- a/include/rdma/ib_sa.h
+++ b/include/rdma/ib_sa.h
@@ -30,8 +30,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $
  */
 
 #ifndef IB_SA_H
diff --git a/include/rdma/ib_smi.h b/include/rdma/ib_smi.h
index f29af135ba83..aaca0878668f 100644
--- a/include/rdma/ib_smi.h
+++ b/include/rdma/ib_smi.h
@@ -32,11 +32,9 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_smi.h 1389 2004-12-27 22:56:47Z roland $
  */
 
-#if !defined( IB_SMI_H )
+#if !defined(IB_SMI_H)
 #define IB_SMI_H
 
 #include <rdma/ib_mad.h>
diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h
index 37650afb982c..bd3d380781e0 100644
--- a/include/rdma/ib_user_cm.h
+++ b/include/rdma/ib_user_cm.h
@@ -29,8 +29,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_user_cm.h 4019 2005-11-11 00:33:09Z sean.hefty $
  */
 
 #ifndef IB_USER_CM_H
diff --git a/include/rdma/ib_user_mad.h b/include/rdma/ib_user_mad.h
index 29d2c7205a90..d6fce1cbdb90 100644
--- a/include/rdma/ib_user_mad.h
+++ b/include/rdma/ib_user_mad.h
@@ -29,8 +29,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $
  */
 
 #ifndef IB_USER_MAD_H
diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h
index 8d65bf0a625b..a17f77106149 100644
--- a/include/rdma/ib_user_verbs.h
+++ b/include/rdma/ib_user_verbs.h
@@ -31,8 +31,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_user_verbs.h 4019 2005-11-11 00:33:09Z sean.hefty $
  */
 
 #ifndef IB_USER_VERBS_H
@@ -291,7 +289,10 @@ struct ib_uverbs_wc {
         __u32 opcode;
         __u32 vendor_err;
         __u32 byte_len;
-        __u32 imm_data;
+        union {
+                __u32 imm_data;
+                __u32 invalidate_rkey;
+        } ex;
         __u32 qp_num;
         __u32 src_qp;
         __u32 wc_flags;
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index 31d30b1852e8..90b529f7a154 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -34,8 +34,6 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- *
- * $Id: ib_verbs.h 1349 2004-12-16 21:09:43Z roland $
  */
 
 #if !defined(IB_VERBS_H)
@@ -93,7 +91,7 @@ enum ib_device_cap_flags {
         IB_DEVICE_RC_RNR_NAK_GEN        = (1<<12),
         IB_DEVICE_SRQ_RESIZE            = (1<<13),
         IB_DEVICE_N_NOTIFY_CQ           = (1<<14),
-        IB_DEVICE_ZERO_STAG             = (1<<15),
+        IB_DEVICE_LOCAL_DMA_LKEY        = (1<<15),
         IB_DEVICE_RESERVED              = (1<<16), /* old SEND_W_INV */
         IB_DEVICE_MEM_WINDOW            = (1<<17),
         /*
@@ -105,6 +103,8 @@ enum ib_device_cap_flags {
          */
         IB_DEVICE_UD_IP_CSUM            = (1<<18),
         IB_DEVICE_UD_TSO                = (1<<19),
+        IB_DEVICE_MEM_MGT_EXTENSIONS    = (1<<21),
+        IB_DEVICE_BLOCK_MULTICAST_LOOPBACK = (1<<22),
 };
 
 enum ib_atomic_cap {
@@ -150,6 +150,7 @@ struct ib_device_attr {
         int                     max_srq;
         int                     max_srq_wr;
         int                     max_srq_sge;
+        unsigned int            max_fast_reg_page_list_len;
         u16                     max_pkeys;
         u8                      local_ca_ack_delay;
 };
@@ -226,6 +227,57 @@ static inline int ib_width_enum_to_int(enum ib_port_width width)
         }
 }
 
+struct ib_protocol_stats {
+        /* TBD... */
+};
+
+struct iw_protocol_stats {
+        u64     ipInReceives;
+        u64     ipInHdrErrors;
+        u64     ipInTooBigErrors;
+        u64     ipInNoRoutes;
+        u64     ipInAddrErrors;
+        u64     ipInUnknownProtos;
+        u64     ipInTruncatedPkts;
+        u64     ipInDiscards;
+        u64     ipInDelivers;
+        u64     ipOutForwDatagrams;
+        u64     ipOutRequests;
+        u64     ipOutDiscards;
+        u64     ipOutNoRoutes;
+        u64     ipReasmTimeout;
+        u64     ipReasmReqds;
+        u64     ipReasmOKs;
+        u64     ipReasmFails;
+        u64     ipFragOKs;
+        u64     ipFragFails;
+        u64     ipFragCreates;
+        u64     ipInMcastPkts;
+        u64     ipOutMcastPkts;
+        u64     ipInBcastPkts;
+        u64     ipOutBcastPkts;
+
+        u64     tcpRtoAlgorithm;
+        u64     tcpRtoMin;
+        u64     tcpRtoMax;
+        u64     tcpMaxConn;
+        u64     tcpActiveOpens;
+        u64     tcpPassiveOpens;
+        u64     tcpAttemptFails;
+        u64     tcpEstabResets;
+        u64     tcpCurrEstab;
+        u64     tcpInSegs;
+        u64     tcpOutSegs;
+        u64     tcpRetransSegs;
+        u64     tcpInErrs;
+        u64     tcpOutRsts;
+};
+
+union rdma_protocol_stats {
+        struct ib_protocol_stats        ib;
+        struct iw_protocol_stats        iw;
+};
+
 struct ib_port_attr {
         enum ib_port_state      state;
         enum ib_mtu             max_mtu;
@@ -413,6 +465,8 @@ enum ib_wc_opcode {
         IB_WC_FETCH_ADD,
         IB_WC_BIND_MW,
         IB_WC_LSO,
+        IB_WC_LOCAL_INV,
+        IB_WC_FAST_REG_MR,
 /*
  * Set value of IB_WC_RECV so consumers can test if a completion is a
  * receive by testing (opcode & IB_WC_RECV).
@@ -423,7 +477,8 @@ enum ib_wc_opcode {
 
 enum ib_wc_flags {
         IB_WC_GRH               = 1,
-        IB_WC_WITH_IMM          = (1<<1)
+        IB_WC_WITH_IMM          = (1<<1),
+        IB_WC_WITH_INVALIDATE   = (1<<2),
 };
 
 struct ib_wc {
@@ -433,7 +488,10 @@ struct ib_wc {
         u32                     vendor_err;
         u32                     byte_len;
         struct ib_qp           *qp;
-        __be32                  imm_data;
+        union {
+                __be32          imm_data;
+                u32             invalidate_rkey;
+        } ex;
         u32                     src_qp;
         int                     wc_flags;
         u16                     pkey_index;
@@ -498,7 +556,8 @@ enum ib_qp_type {
 };
 
 enum ib_qp_create_flags {
-        IB_QP_CREATE_IPOIB_UD_LSO       = 1 << 0,
+        IB_QP_CREATE_IPOIB_UD_LSO               = 1 << 0,
+        IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK   = 1 << 1,
 };
 
 struct ib_qp_init_attr {
@@ -627,6 +686,9 @@ enum ib_wr_opcode {
         IB_WR_ATOMIC_FETCH_AND_ADD,
         IB_WR_LSO,
         IB_WR_SEND_WITH_INV,
+        IB_WR_RDMA_READ_WITH_INV,
+        IB_WR_LOCAL_INV,
+        IB_WR_FAST_REG_MR,
 };
 
 enum ib_send_flags {
@@ -643,6 +705,12 @@ struct ib_sge {
         u32     lkey;
 };
 
+struct ib_fast_reg_page_list {
+        struct ib_device       *device;
+        u64                    *page_list;
+        unsigned int            max_page_list_len;
+};
+
 struct ib_send_wr {
         struct ib_send_wr      *next;
         u64                     wr_id;
@@ -675,6 +743,15 @@ struct ib_send_wr {
                         u16     pkey_index; /* valid for GSI only */
                         u8      port_num;   /* valid for DR SMPs on switch only */
                 } ud;
+                struct {
+                        u64                             iova_start;
+                        struct ib_fast_reg_page_list   *page_list;
+                        unsigned int                    page_shift;
+                        unsigned int                    page_list_len;
+                        u32                             length;
+                        int                             access_flags;
+                        u32                             rkey;
+                } fast_reg;
         } wr;
 };
 
@@ -777,7 +854,7 @@ struct ib_cq {
         struct ib_uobject      *uobject;
         ib_comp_handler         comp_handler;
         void                  (*event_handler)(struct ib_event *, void *);
-        void *                  cq_context;
+        void                   *cq_context;
         int                     cqe;
         atomic_t                usecnt; /* count number of work queues */
 };
@@ -883,7 +960,7 @@ struct ib_dma_mapping_ops {
         void            (*sync_single_for_cpu)(struct ib_device *dev,
                                                u64 dma_handle,
                                                size_t size,
-                                               enum dma_data_direction dir);
+                                               enum dma_data_direction dir);
         void            (*sync_single_for_device)(struct ib_device *dev,
                                                   u64 dma_handle,
                                                   size_t size,
@@ -919,6 +996,8 @@ struct ib_device {
 
         struct iw_cm_verbs           *iwcm;
 
+        int                        (*get_protocol_stats)(struct ib_device *device,
+                                                         union rdma_protocol_stats *stats);
         int                        (*query_device)(struct ib_device *device,
                                                    struct ib_device_attr *device_attr);
         int                        (*query_port)(struct ib_device *device,
@@ -1013,6 +1092,11 @@ struct ib_device {
         int                        (*query_mr)(struct ib_mr *mr,
                                                struct ib_mr_attr *mr_attr);
         int                        (*dereg_mr)(struct ib_mr *mr);
+        struct ib_mr *             (*alloc_fast_reg_mr)(struct ib_pd *pd,
+                                               int max_page_list_len);
+        struct ib_fast_reg_page_list * (*alloc_fast_reg_page_list)(struct ib_device *device,
+                                                                   int page_list_len);
+        void                       (*free_fast_reg_page_list)(struct ib_fast_reg_page_list *page_list);
         int                        (*rereg_phys_mr)(struct ib_mr *mr,
                                                     int mr_rereg_mask,
                                                     struct ib_pd *pd,
@@ -1065,6 +1149,7 @@ struct ib_device {
 
         char                         node_desc[64];
         __be64                       node_guid;
+        u32                          local_dma_lkey;
         u8                           node_type;
         u8                           phys_port_cnt;
 };
@@ -1807,6 +1892,54 @@ int ib_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr);
 int ib_dereg_mr(struct ib_mr *mr);
 
 /**
+ * ib_alloc_fast_reg_mr - Allocates memory region usable with the
+ *   IB_WR_FAST_REG_MR send work request.
+ * @pd: The protection domain associated with the region.
+ * @max_page_list_len: requested max physical buffer list length to be
+ *   used with fast register work requests for this MR.
+ */
+struct ib_mr *ib_alloc_fast_reg_mr(struct ib_pd *pd, int max_page_list_len);
+
+/**
+ * ib_alloc_fast_reg_page_list - Allocates a page list array
+ * @device - ib device pointer.
+ * @page_list_len - size of the page list array to be allocated.
+ *
+ * This allocates and returns a struct ib_fast_reg_page_list * and a
+ * page_list array that is at least page_list_len in size.  The actual
+ * size is returned in max_page_list_len.  The caller is responsible
+ * for initializing the contents of the page_list array before posting
+ * a send work request with the IB_WC_FAST_REG_MR opcode.
+ *
+ * The page_list array entries must be translated using one of the
+ * ib_dma_*() functions just like the addresses passed to
+ * ib_map_phys_fmr().  Once the ib_post_send() is issued, the struct
+ * ib_fast_reg_page_list must not be modified by the caller until the
+ * IB_WC_FAST_REG_MR work request completes.
+ */
+struct ib_fast_reg_page_list *ib_alloc_fast_reg_page_list(
+                                struct ib_device *device, int page_list_len);
+
+/**
+ * ib_free_fast_reg_page_list - Deallocates a previously allocated
+ *   page list array.
+ * @page_list - struct ib_fast_reg_page_list pointer to be deallocated.
+ */
+void ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
+
+/**
+ * ib_update_fast_reg_key - updates the key portion of the fast_reg MR
+ *   R_Key and L_Key.
+ * @mr - struct ib_mr pointer to be updated.
+ * @newkey - new key to be used.
+ */
+static inline void ib_update_fast_reg_key(struct ib_mr *mr, u8 newkey)
+{
+        mr->lkey = (mr->lkey & 0xffffff00) | newkey;
+        mr->rkey = (mr->rkey & 0xffffff00) | newkey;
+}
+
+/**
  * ib_alloc_mw - Allocates a memory window.
  * @pd: The protection domain associated with the memory window.
  */
diff --git a/include/rdma/iw_cm.h b/include/rdma/iw_cm.h
index aeefa9b740dc..cbb822e8d791 100644
--- a/include/rdma/iw_cm.h
+++ b/include/rdma/iw_cm.h
@@ -62,7 +62,7 @@ struct iw_cm_event {
         struct sockaddr_in remote_addr;
         void *private_data;
         u8 private_data_len;
-        void* provider_data;
+        void *provider_data;
 };
 
 /**
diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h
index 010f876f41d8..22bb2e7bab1a 100644
--- a/include/rdma/rdma_cm.h
+++ b/include/rdma/rdma_cm.h
@@ -2,29 +2,33 @@
  * Copyright (c) 2005 Voltaire Inc.  All rights reserved.
  * Copyright (c) 2005 Intel Corporation.  All rights reserved.
  *
- * This Software is licensed under one of the following licenses:
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
  *
- * 1) under the terms of the "Common Public License 1.0" a copy of which is
- *    available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/cpl.php.
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
  *
- * 2) under the terms of the "The BSD License" a copy of which is
- *    available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/bsd-license.php.
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
  *
- * 3) under the terms of the "GNU General Public License (GPL) Version 2" a
- *    copy of which is available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/gpl-license.php.
- *
- * Licensee has the right to choose one of the above licenses.
- *
- * Redistributions of source code must retain the above copyright
- * notice and one of the license notices.
- *
- * Redistributions in binary form must reproduce both the above copyright
- * notice, one of the license notices in the documentation
- * and/or other materials provided with the distribution.
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
  *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
  */
 
 #if !defined(RDMA_CM_H)
@@ -57,11 +61,11 @@ enum rdma_cm_event_type {
 };
 
 enum rdma_port_space {
-        RDMA_PS_SDP  = 0x0001,
-        RDMA_PS_IPOIB= 0x0002,
-        RDMA_PS_TCP  = 0x0106,
-        RDMA_PS_UDP  = 0x0111,
-        RDMA_PS_SCTP = 0x0183
+        RDMA_PS_SDP   = 0x0001,
+        RDMA_PS_IPOIB = 0x0002,
+        RDMA_PS_TCP   = 0x0106,
+        RDMA_PS_UDP   = 0x0111,
+        RDMA_PS_SCTP  = 0x0183
 };
 
 struct rdma_addr {
diff --git a/include/rdma/rdma_cm_ib.h b/include/rdma/rdma_cm_ib.h
index 950424b38f16..2389c3b45404 100644
--- a/include/rdma/rdma_cm_ib.h
+++ b/include/rdma/rdma_cm_ib.h
@@ -1,29 +1,33 @@
 /*
  * Copyright (c) 2006 Intel Corporation.  All rights reserved.
  *
- * This Software is licensed under one of the following licenses:
- *
- * 1) under the terms of the "Common Public License 1.0" a copy of which is
- *    available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/cpl.php.
- *
- * 2) under the terms of the "The BSD License" a copy of which is
- *    available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/bsd-license.php.
- *
- * 3) under the terms of the "GNU General Public License (GPL) Version 2" a
- *    copy of which is available from the Open Source Initiative, see
- *    http://www.opensource.org/licenses/gpl-license.php.
- *
- * Licensee has the right to choose one of the above licenses.
- *
- * Redistributions of source code must retain the above copyright
- * notice and one of the license notices.
- *
- * Redistributions in binary form must reproduce both the above copyright
- * notice, one of the license notices in the documentation
- * and/or other materials provided with the distribution.
- *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
  */
 
 #if !defined(RDMA_CM_IB_H)
diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h
index e19e58423166..16be12f1cbe8 100644
--- a/include/scsi/iscsi_if.h
+++ b/include/scsi/iscsi_if.h
@@ -50,6 +50,7 @@ enum iscsi_uevent_e {
         ISCSI_UEVENT_TGT_DSCVR          = UEVENT_BASE + 15,
         ISCSI_UEVENT_SET_HOST_PARAM     = UEVENT_BASE + 16,
         ISCSI_UEVENT_UNBIND_SESSION     = UEVENT_BASE + 17,
+        ISCSI_UEVENT_CREATE_BOUND_SESSION       = UEVENT_BASE + 18,
 
         /* up events */
         ISCSI_KEVENT_RECV_PDU           = KEVENT_BASE + 1,
@@ -78,6 +79,12 @@ struct iscsi_uevent {
                         uint16_t        cmds_max;
                         uint16_t        queue_depth;
                 } c_session;
+                struct msg_create_bound_session {
+                        uint64_t        ep_handle;
+                        uint32_t        initial_cmdsn;
+                        uint16_t        cmds_max;
+                        uint16_t        queue_depth;
+                } c_bound_session;
                 struct msg_destroy_session {
                         uint32_t        sid;
                 } d_session;
@@ -250,42 +257,49 @@ enum iscsi_param {
 
         ISCSI_PARAM_PING_TMO,
         ISCSI_PARAM_RECV_TMO,
+
+        ISCSI_PARAM_IFACE_NAME,
+        ISCSI_PARAM_ISID,
+        ISCSI_PARAM_INITIATOR_NAME,
         /* must always be last */
         ISCSI_PARAM_MAX,
 };
 
-#define ISCSI_MAX_RECV_DLENGTH          (1 << ISCSI_PARAM_MAX_RECV_DLENGTH)
-#define ISCSI_MAX_XMIT_DLENGTH          (1 << ISCSI_PARAM_MAX_XMIT_DLENGTH)
-#define ISCSI_HDRDGST_EN                (1 << ISCSI_PARAM_HDRDGST_EN)
-#define ISCSI_DATADGST_EN               (1 << ISCSI_PARAM_DATADGST_EN)
-#define ISCSI_INITIAL_R2T_EN            (1 << ISCSI_PARAM_INITIAL_R2T_EN)
-#define ISCSI_MAX_R2T                   (1 << ISCSI_PARAM_MAX_R2T)
-#define ISCSI_IMM_DATA_EN               (1 << ISCSI_PARAM_IMM_DATA_EN)
-#define ISCSI_FIRST_BURST               (1 << ISCSI_PARAM_FIRST_BURST)
-#define ISCSI_MAX_BURST                 (1 << ISCSI_PARAM_MAX_BURST)
-#define ISCSI_PDU_INORDER_EN            (1 << ISCSI_PARAM_PDU_INORDER_EN)
-#define ISCSI_DATASEQ_INORDER_EN        (1 << ISCSI_PARAM_DATASEQ_INORDER_EN)
-#define ISCSI_ERL                       (1 << ISCSI_PARAM_ERL)
-#define ISCSI_IFMARKER_EN               (1 << ISCSI_PARAM_IFMARKER_EN)
-#define ISCSI_OFMARKER_EN               (1 << ISCSI_PARAM_OFMARKER_EN)
-#define ISCSI_EXP_STATSN                (1 << ISCSI_PARAM_EXP_STATSN)
-#define ISCSI_TARGET_NAME               (1 << ISCSI_PARAM_TARGET_NAME)
-#define ISCSI_TPGT                      (1 << ISCSI_PARAM_TPGT)
-#define ISCSI_PERSISTENT_ADDRESS        (1 << ISCSI_PARAM_PERSISTENT_ADDRESS)
-#define ISCSI_PERSISTENT_PORT           (1 << ISCSI_PARAM_PERSISTENT_PORT)
-#define ISCSI_SESS_RECOVERY_TMO         (1 << ISCSI_PARAM_SESS_RECOVERY_TMO)
-#define ISCSI_CONN_PORT                 (1 << ISCSI_PARAM_CONN_PORT)
-#define ISCSI_CONN_ADDRESS              (1 << ISCSI_PARAM_CONN_ADDRESS)
-#define ISCSI_USERNAME                  (1 << ISCSI_PARAM_USERNAME)
-#define ISCSI_USERNAME_IN               (1 << ISCSI_PARAM_USERNAME_IN)
-#define ISCSI_PASSWORD                  (1 << ISCSI_PARAM_PASSWORD)
-#define ISCSI_PASSWORD_IN               (1 << ISCSI_PARAM_PASSWORD_IN)
-#define ISCSI_FAST_ABORT                (1 << ISCSI_PARAM_FAST_ABORT)
-#define ISCSI_ABORT_TMO                 (1 << ISCSI_PARAM_ABORT_TMO)
-#define ISCSI_LU_RESET_TMO              (1 << ISCSI_PARAM_LU_RESET_TMO)
-#define ISCSI_HOST_RESET_TMO            (1 << ISCSI_PARAM_HOST_RESET_TMO)
-#define ISCSI_PING_TMO                  (1 << ISCSI_PARAM_PING_TMO)
-#define ISCSI_RECV_TMO                  (1 << ISCSI_PARAM_RECV_TMO)
+#define ISCSI_MAX_RECV_DLENGTH          (1ULL << ISCSI_PARAM_MAX_RECV_DLENGTH)
+#define ISCSI_MAX_XMIT_DLENGTH          (1ULL << ISCSI_PARAM_MAX_XMIT_DLENGTH)
+#define ISCSI_HDRDGST_EN                (1ULL << ISCSI_PARAM_HDRDGST_EN)
+#define ISCSI_DATADGST_EN               (1ULL << ISCSI_PARAM_DATADGST_EN)
+#define ISCSI_INITIAL_R2T_EN            (1ULL << ISCSI_PARAM_INITIAL_R2T_EN)
+#define ISCSI_MAX_R2T                   (1ULL << ISCSI_PARAM_MAX_R2T)
+#define ISCSI_IMM_DATA_EN               (1ULL << ISCSI_PARAM_IMM_DATA_EN)
+#define ISCSI_FIRST_BURST               (1ULL << ISCSI_PARAM_FIRST_BURST)
+#define ISCSI_MAX_BURST                 (1ULL << ISCSI_PARAM_MAX_BURST)
+#define ISCSI_PDU_INORDER_EN            (1ULL << ISCSI_PARAM_PDU_INORDER_EN)
+#define ISCSI_DATASEQ_INORDER_EN        (1ULL << ISCSI_PARAM_DATASEQ_INORDER_EN)
+#define ISCSI_ERL                       (1ULL << ISCSI_PARAM_ERL)
+#define ISCSI_IFMARKER_EN               (1ULL << ISCSI_PARAM_IFMARKER_EN)
+#define ISCSI_OFMARKER_EN               (1ULL << ISCSI_PARAM_OFMARKER_EN)
+#define ISCSI_EXP_STATSN                (1ULL << ISCSI_PARAM_EXP_STATSN)
+#define ISCSI_TARGET_NAME               (1ULL << ISCSI_PARAM_TARGET_NAME)
+#define ISCSI_TPGT                      (1ULL << ISCSI_PARAM_TPGT)
+#define ISCSI_PERSISTENT_ADDRESS        (1ULL << ISCSI_PARAM_PERSISTENT_ADDRESS)
+#define ISCSI_PERSISTENT_PORT           (1ULL << ISCSI_PARAM_PERSISTENT_PORT)
+#define ISCSI_SESS_RECOVERY_TMO         (1ULL << ISCSI_PARAM_SESS_RECOVERY_TMO)
+#define ISCSI_CONN_PORT                 (1ULL << ISCSI_PARAM_CONN_PORT)
+#define ISCSI_CONN_ADDRESS              (1ULL << ISCSI_PARAM_CONN_ADDRESS)
+#define ISCSI_USERNAME                  (1ULL << ISCSI_PARAM_USERNAME)
+#define ISCSI_USERNAME_IN               (1ULL << ISCSI_PARAM_USERNAME_IN)
+#define ISCSI_PASSWORD                  (1ULL << ISCSI_PARAM_PASSWORD)
+#define ISCSI_PASSWORD_IN               (1ULL << ISCSI_PARAM_PASSWORD_IN)
+#define ISCSI_FAST_ABORT                (1ULL << ISCSI_PARAM_FAST_ABORT)
+#define ISCSI_ABORT_TMO                 (1ULL << ISCSI_PARAM_ABORT_TMO)
+#define ISCSI_LU_RESET_TMO              (1ULL << ISCSI_PARAM_LU_RESET_TMO)
+#define ISCSI_HOST_RESET_TMO            (1ULL << ISCSI_PARAM_HOST_RESET_TMO)
+#define ISCSI_PING_TMO                  (1ULL << ISCSI_PARAM_PING_TMO)
+#define ISCSI_RECV_TMO                  (1ULL << ISCSI_PARAM_RECV_TMO)
+#define ISCSI_IFACE_NAME                (1ULL << ISCSI_PARAM_IFACE_NAME)
+#define ISCSI_ISID                      (1ULL << ISCSI_PARAM_ISID)
+#define ISCSI_INITIATOR_NAME            (1ULL << ISCSI_PARAM_INITIATOR_NAME)
 
 /* iSCSI HBA params */
 enum iscsi_host_param {
@@ -296,20 +310,13 @@ enum iscsi_host_param {
         ISCSI_HOST_PARAM_MAX,
 };
 
-#define ISCSI_HOST_HWADDRESS            (1 << ISCSI_HOST_PARAM_HWADDRESS)
-#define ISCSI_HOST_INITIATOR_NAME       (1 << ISCSI_HOST_PARAM_INITIATOR_NAME)
-#define ISCSI_HOST_NETDEV_NAME          (1 << ISCSI_HOST_PARAM_NETDEV_NAME)
-#define ISCSI_HOST_IPADDRESS            (1 << ISCSI_HOST_PARAM_IPADDRESS)
+#define ISCSI_HOST_HWADDRESS            (1ULL << ISCSI_HOST_PARAM_HWADDRESS)
+#define ISCSI_HOST_INITIATOR_NAME       (1ULL << ISCSI_HOST_PARAM_INITIATOR_NAME)
+#define ISCSI_HOST_NETDEV_NAME          (1ULL << ISCSI_HOST_PARAM_NETDEV_NAME)
+#define ISCSI_HOST_IPADDRESS            (1ULL << ISCSI_HOST_PARAM_IPADDRESS)
 
 #define iscsi_ptr(_handle) ((void*)(unsigned long)_handle)
 #define iscsi_handle(_ptr) ((uint64_t)(unsigned long)_ptr)
-#define hostdata_session(_hostdata) (iscsi_ptr(*(unsigned long *)_hostdata))
-
-/**
- * iscsi_hostdata - get LLD hostdata from scsi_host
- * @_hostdata: pointer to scsi host's hostdata
- **/
-#define iscsi_hostdata(_hostdata) ((void*)_hostdata + sizeof(unsigned long))
 
 /*
  * These flags presents iSCSI Data-Path capabilities.
diff --git a/include/scsi/iscsi_proto.h b/include/scsi/iscsi_proto.h
index e0593bfae622..f2a2c1169486 100644
--- a/include/scsi/iscsi_proto.h
+++ b/include/scsi/iscsi_proto.h
@@ -22,6 +22,7 @@
 #define ISCSI_PROTO_H
 
 #include <linux/types.h>
+#include <scsi/scsi.h>
 
 #define ISCSI_DRAFT20_VERSION   0x00
 
@@ -156,7 +157,7 @@ struct iscsi_ecdb_ahdr {
         uint8_t ahstype;
         uint8_t reserved;
         /* 4-byte aligned extended CDB spillover */
-        uint8_t ecdb[260 - ISCSI_CDB_SIZE];
+        uint8_t ecdb[SCSI_MAX_VARLEN_CDB_SIZE - ISCSI_CDB_SIZE];
 };
 
 /* SCSI Response Header */
diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
index cd3ca63d4fb1..5e75bb7f311c 100644
--- a/include/scsi/libiscsi.h
+++ b/include/scsi/libiscsi.h
@@ -24,6 +24,7 @@
 #define LIBISCSI_H
 
 #include <linux/types.h>
+#include <linux/wait.h>
 #include <linux/mutex.h>
 #include <linux/timer.h>
 #include <linux/workqueue.h>
@@ -31,6 +32,7 @@
 #include <scsi/iscsi_if.h>
 
 struct scsi_transport_template;
+struct scsi_host_template;
 struct scsi_device;
 struct Scsi_Host;
 struct scsi_cmnd;
@@ -40,6 +42,7 @@ struct iscsi_cls_session;
 struct iscsi_cls_conn;
 struct iscsi_session;
 struct iscsi_nopin;
+struct device;
 
 /* #define DEBUG_SCSI */
 #ifdef DEBUG_SCSI
@@ -49,9 +52,7 @@ struct iscsi_nopin;
 #endif
 
 #define ISCSI_DEF_XMIT_CMDS_MAX 128     /* must be power of 2 */
-#define ISCSI_MGMT_CMDS_MAX     16      /* must be power of 2 */
-
-#define ISCSI_MGMT_ITT_OFFSET   0xa00
+#define ISCSI_MGMT_CMDS_MAX     15
 
 #define ISCSI_DEF_CMD_PER_LUN           32
 #define ISCSI_MAX_CMD_PER_LUN           128
@@ -69,7 +70,10 @@ enum {
 /* Connection suspend "bit" */
 #define ISCSI_SUSPEND_BIT               1
 
-#define ISCSI_ITT_MASK                  (0xfff)
+#define ISCSI_ITT_MASK                  (0x1fff)
+#define ISCSI_TOTAL_CMDS_MAX            4096
+/* this must be a power of two greater than ISCSI_MGMT_CMDS_MAX */
+#define ISCSI_TOTAL_CMDS_MIN            16
 #define ISCSI_AGE_SHIFT                 28
 #define ISCSI_AGE_MASK                  (0xf << ISCSI_AGE_SHIFT)
 
@@ -82,18 +86,6 @@ enum {
         ISCSI_DIGEST_SIZE = sizeof(__u32),
 };
 
-struct iscsi_mgmt_task {
-        /*
-         * Becuae LLDs allocate their hdr differently, this is a pointer to
-         * that storage. It must be setup at session creation time.
-         */
-        struct iscsi_hdr        *hdr;
-        char                    *data;          /* mgmt payload */
-        unsigned                data_count;     /* counts data to be sent */
-        uint32_t                itt;            /* this ITT */
-        void                    *dd_data;       /* driver/transport data */
-        struct list_head        running;
-};
 
 enum {
         ISCSI_TASK_COMPLETED,
@@ -101,7 +93,7 @@ enum {
         ISCSI_TASK_RUNNING,
 };
 
-struct iscsi_cmd_task {
+struct iscsi_task {
         /*
          * Because LLDs allocate their hdr differently, this is a pointer
          * and length to that storage. It must be setup at session
@@ -118,6 +110,7 @@ struct iscsi_cmd_task {
         /* offset in unsolicited stream (bytes); */
         unsigned                unsol_offset;
         unsigned                data_count;     /* remaining Data-Out */
+        char                    *data;          /* mgmt payload */
         struct scsi_cmnd        *sc;            /* associated SCSI cmd*/
         struct iscsi_conn       *conn;          /* used connection    */
 
@@ -128,9 +121,9 @@ struct iscsi_cmd_task {
         void                    *dd_data;       /* driver/transport data */
 };
 
-static inline void* iscsi_next_hdr(struct iscsi_cmd_task *ctask)
+static inline void* iscsi_next_hdr(struct iscsi_task *task)
 {
-        return (void*)ctask->hdr + ctask->hdr_len;
+        return (void*)task->hdr + task->hdr_len;
 }
 
 /* Connection's states */
@@ -146,11 +139,6 @@ struct iscsi_conn {
         void                    *dd_data;       /* iscsi_transport data */
         struct iscsi_session    *session;       /* parent session */
         /*
-         * LLDs should set this lock. It protects the transport recv
-         * code
-         */
-        rwlock_t                *recv_lock;
-        /*
          * conn_stop() flag: stop to recover, stop to terminate
          */
         int                     stop_stage;
@@ -159,7 +147,7 @@ struct iscsi_conn {
         unsigned long           last_ping;
         int                     ping_timeout;
         int                     recv_timeout;
-        struct iscsi_mgmt_task  *ping_mtask;
+        struct iscsi_task       *ping_task;
 
         /* iSCSI connection-wide sequencing */
         uint32_t                exp_statsn;
@@ -175,9 +163,8 @@ struct iscsi_conn {
          * should always fit in this buffer
          */
         char                    *data;
-        struct iscsi_mgmt_task  *login_mtask;   /* mtask used for login/text */
-        struct iscsi_mgmt_task  *mtask;         /* xmit mtask in progress */
-        struct iscsi_cmd_task   *ctask;         /* xmit ctask in progress */
+        struct iscsi_task       *login_task;    /* mtask used for login/text */
+        struct iscsi_task       *task;          /* xmit task in progress */
 
         /* xmit */
         struct list_head        mgmtqueue;      /* mgmt (control) xmit queue */
@@ -208,9 +195,6 @@ struct iscsi_conn {
         /* remote portal currently connected to */
         int                     portal_port;
         char                    portal_address[ISCSI_ADDRESS_BUF_LEN];
-        /* local address */
-        int                     local_port;
-        char                    local_address[ISCSI_ADDRESS_BUF_LEN];
 
         /* MIB-statistics */
         uint64_t                txdata_octets;
@@ -246,6 +230,7 @@ enum {
 };
 
 struct iscsi_session {
+        struct iscsi_cls_session *cls_session;
         /*
          * Syncs up the scsi eh thread with the iscsi eh thread when sending
          * task management functions. This must be taken before the session
@@ -281,10 +266,8 @@ struct iscsi_session {
         char                    *password;
         char                    *password_in;
         char                    *targetname;
+        char                    *ifacename;
         char                    *initiatorname;
-        /* hw address or netdev iscsi connection is bound to */
-        char                    *hwaddress;
-        char                    *netdev;
         /* control data */
         struct iscsi_transport  *tt;
         struct Scsi_Host        *host;
@@ -298,12 +281,20 @@ struct iscsi_session {
         int                     state;          /* session state           */
         int                     age;            /* counts session re-opens */
 
+        int                     scsi_cmds_max;  /* max scsi commands */
         int                     cmds_max;       /* size of cmds array */
-        struct iscsi_cmd_task   **cmds;         /* Original Cmds arr */
+        struct iscsi_task       **cmds;         /* Original Cmds arr */
         struct iscsi_pool       cmdpool;        /* PDU's pool */
-        int                     mgmtpool_max;   /* size of mgmt array */
-        struct iscsi_mgmt_task  **mgmt_cmds;    /* Original mgmt arr */
-        struct iscsi_pool       mgmtpool;       /* Mgmt PDU's pool */
+};
+
+struct iscsi_host {
+        char                    *initiatorname;
+        /* hw address or netdev iscsi connection is bound to */
+        char                    *hwaddress;
+        char                    *netdev;
+        /* local address */
+        int                     local_port;
+        char                    local_address[ISCSI_ADDRESS_BUF_LEN];
 };
 
 /*
@@ -316,42 +307,44 @@ extern int iscsi_eh_device_reset(struct scsi_cmnd *sc);
 extern int iscsi_queuecommand(struct scsi_cmnd *sc,
                               void (*done)(struct scsi_cmnd *));
 
-
 /*
  * iSCSI host helpers.
  */
+#define iscsi_host_priv(_shost) \
+        (shost_priv(_shost) + sizeof(struct iscsi_host))
+
 extern int iscsi_host_set_param(struct Scsi_Host *shost,
                                 enum iscsi_host_param param, char *buf,
                                 int buflen);
 extern int iscsi_host_get_param(struct Scsi_Host *shost,
                                 enum iscsi_host_param param, char *buf);
+extern int iscsi_host_add(struct Scsi_Host *shost, struct device *pdev);
+extern struct Scsi_Host *iscsi_host_alloc(struct scsi_host_template *sht,
+                                          int dd_data_size, uint16_t qdepth);
+extern void iscsi_host_remove(struct Scsi_Host *shost);
+extern void iscsi_host_free(struct Scsi_Host *shost);
 
 /*
  * session management
  */
 extern struct iscsi_cls_session *
-iscsi_session_setup(struct iscsi_transport *, struct scsi_transport_template *,
-                    uint16_t, uint16_t, int, int, uint32_t, uint32_t *);
+iscsi_session_setup(struct iscsi_transport *, struct Scsi_Host *shost,
+                    uint16_t, int, uint32_t, unsigned int);
 extern void iscsi_session_teardown(struct iscsi_cls_session *);
-extern struct iscsi_session *class_to_transport_session(struct iscsi_cls_session *);
 extern void iscsi_session_recovery_timedout(struct iscsi_cls_session *);
 extern int iscsi_set_param(struct iscsi_cls_conn *cls_conn,
                            enum iscsi_param param, char *buf, int buflen);
 extern int iscsi_session_get_param(struct iscsi_cls_session *cls_session,
                                    enum iscsi_param param, char *buf);
 
-#define session_to_cls(_sess) \
-        hostdata_session(_sess->host->hostdata)
-
 #define iscsi_session_printk(prefix, _sess, fmt, a...)  \
-        iscsi_cls_session_printk(prefix,                \
-                (struct iscsi_cls_session *)session_to_cls(_sess), fmt, ##a)
+        iscsi_cls_session_printk(prefix, _sess->cls_session, fmt, ##a)
 
 /*
  * connection management
  */
 extern struct iscsi_cls_conn *iscsi_conn_setup(struct iscsi_cls_session *,
-                                               uint32_t);
+                                               int, uint32_t);
 extern void iscsi_conn_teardown(struct iscsi_cls_conn *);
 extern int iscsi_conn_start(struct iscsi_cls_conn *);
 extern void iscsi_conn_stop(struct iscsi_cls_conn *, int);
@@ -360,25 +353,29 @@ extern int iscsi_conn_bind(struct iscsi_cls_session *, struct iscsi_cls_conn *,
 extern void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err);
 extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn,
                                 enum iscsi_param param, char *buf);
+extern void iscsi_suspend_tx(struct iscsi_conn *conn);
 
 #define iscsi_conn_printk(prefix, _c, fmt, a...) \
-        iscsi_cls_conn_printk(prefix, _c->cls_conn, fmt, ##a)
+        iscsi_cls_conn_printk(prefix, ((struct iscsi_conn *)_c)->cls_conn, \
+                              fmt, ##a)
 
 /*
  * pdu and task processing
  */
 extern void iscsi_update_cmdsn(struct iscsi_session *, struct iscsi_nopin *);
-extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_cmd_task *,
+extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_task *,
                                         struct iscsi_data *hdr);
 extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *,
                                 char *, uint32_t);
 extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *,
                               char *, int);
-extern int iscsi_verify_itt(struct iscsi_conn *, struct iscsi_hdr *,
-                            uint32_t *);
-extern void iscsi_requeue_ctask(struct iscsi_cmd_task *ctask);
-extern void iscsi_free_mgmt_task(struct iscsi_conn *conn,
-                                 struct iscsi_mgmt_task *mtask);
+extern int __iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *,
+                                char *, int);
+extern int iscsi_verify_itt(struct iscsi_conn *, itt_t);
+extern struct iscsi_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t);
+extern void iscsi_requeue_task(struct iscsi_task *task);
+extern void iscsi_put_task(struct iscsi_task *task);
+extern void __iscsi_get_task(struct iscsi_task *task);
 
 /*
  * generic helpers
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index 32742c4563de..00137a7769ee 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -9,6 +9,7 @@
 #define _SCSI_SCSI_H
 
 #include <linux/types.h>
+#include <scsi/scsi_cmnd.h>
 
 /*
  * The maximum number of SG segments that we will put inside a
@@ -400,6 +401,7 @@ struct scsi_lun {
 #define SOFT_ERROR      0x2005
 #define ADD_TO_MLQUEUE  0x2006
 #define TIMEOUT_ERROR   0x2007
+#define SCSI_RETURN_NOT_HANDLED   0x2008
 
 /*
  * Midlevel queue return values.
@@ -424,6 +426,22 @@ struct scsi_lun {
 #define driver_byte(result) (((result) >> 24) & 0xff)
 #define suggestion(result)  (driver_byte(result) & SUGGEST_MASK)
 
+static inline void set_msg_byte(struct scsi_cmnd *cmd, char status)
+{
+        cmd->result |= status << 8;
+}
+
+static inline void set_host_byte(struct scsi_cmnd *cmd, char status)
+{
+        cmd->result |= status << 16;
+}
+
+static inline void set_driver_byte(struct scsi_cmnd *cmd, char status)
+{
+        cmd->result |= status << 24;
+}
+
+
 #define sense_class(sense)  (((sense) >> 4) & 0x7)
 #define sense_error(sense)  ((sense) & 0xf)
 #define sense_valid(sense)  ((sense) & 0x80);
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index 3e46dfae8194..66c944849d6b 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -7,7 +7,6 @@
 #include <linux/types.h>
 #include <linux/timer.h>
 #include <linux/scatterlist.h>
-#include <linux/blkdev.h>
 
 struct Scsi_Host;
 struct scsi_device;
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index f6a9fe0ef09c..6467f78b191f 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -134,6 +134,7 @@ struct scsi_device {
         unsigned no_start_on_add:1;     /* do not issue start on add */
         unsigned allow_restart:1; /* issue START_UNIT in error handler */
         unsigned manage_start_stop:1;   /* Let HLD (sd) manage start/stop */
+        unsigned start_stop_pwr_cond:1; /* Set power cond. in START_STOP_UNIT */
         unsigned no_uld_attach:1; /* disable connecting to upper level drivers */
         unsigned select_no_atn:1;
         unsigned fix_capacity:1;        /* READ_CAPACITY is too high by 1 */
@@ -161,9 +162,29 @@ struct scsi_device {
 
         struct execute_work     ew; /* used to get process context on put */
 
+        struct scsi_dh_data     *scsi_dh_data;
         enum scsi_device_state sdev_state;
         unsigned long           sdev_data[0];
 } __attribute__((aligned(sizeof(unsigned long))));
+
+struct scsi_device_handler {
+        /* Used by the infrastructure */
+        struct list_head list; /* list of scsi_device_handlers */
+        struct notifier_block nb;
+
+        /* Filled by the hardware handler */
+        struct module *module;
+        const char *name;
+        int (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);
+        int (*activate)(struct scsi_device *);
+        int (*prep_fn)(struct scsi_device *, struct request *);
+};
+
+struct scsi_dh_data {
+        struct scsi_device_handler *scsi_dh;
+        char buf[0];
+};
+
 #define to_scsi_device(d)       \
         container_of(d, struct scsi_device, sdev_gendev)
 #define class_to_sdev(d)        \
@@ -230,7 +251,9 @@ extern struct scsi_device *__scsi_add_device(struct Scsi_Host *,
                 uint, uint, uint, void *hostdata);
 extern int scsi_add_device(struct Scsi_Host *host, uint channel,
                            uint target, uint lun);
+extern int scsi_register_device_handler(struct scsi_device_handler *scsi_dh);
 extern void scsi_remove_device(struct scsi_device *);
+extern int scsi_unregister_device_handler(struct scsi_device_handler *scsi_dh);
 
 extern int scsi_device_get(struct scsi_device *);
 extern void scsi_device_put(struct scsi_device *);
diff --git a/include/scsi/scsi_dh.h b/include/scsi/scsi_dh.h
new file mode 100644
index 000000000000..3ad2303d1a16
--- /dev/null
+++ b/include/scsi/scsi_dh.h
@@ -0,0 +1,69 @@
+/*
+ * Header file for SCSI device handler infrastruture.
+ *
+ * Modified version of patches posted by Mike Christie <michaelc@cs.wisc.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright IBM Corporation, 2007
+ *      Authors:
+ *               Chandra Seetharaman <sekharan@us.ibm.com>
+ *               Mike Anderson <andmike@linux.vnet.ibm.com>
+ */
+
+#include <scsi/scsi_device.h>
+
+enum {
+        SCSI_DH_OK = 0,
+        /*
+         * device errors
+         */
+        SCSI_DH_DEV_FAILED,     /* generic device error */
+        SCSI_DH_DEV_TEMP_BUSY,
+        SCSI_DH_DEVICE_MAX,     /* max device blkerr definition */
+
+        /*
+         * transport errors
+         */
+        SCSI_DH_NOTCONN = SCSI_DH_DEVICE_MAX + 1,
+        SCSI_DH_CONN_FAILURE,
+        SCSI_DH_TRANSPORT_MAX,  /* max transport blkerr definition */
+
+        /*
+         * driver and generic errors
+         */
+        SCSI_DH_IO = SCSI_DH_TRANSPORT_MAX + 1, /* generic error */
+        SCSI_DH_INVALID_IO,
+        SCSI_DH_RETRY,          /* retry the req, but not immediately */
+        SCSI_DH_IMM_RETRY,      /* immediately retry the req */
+        SCSI_DH_TIMED_OUT,
+        SCSI_DH_RES_TEMP_UNAVAIL,
+        SCSI_DH_DEV_OFFLINED,
+        SCSI_DH_NOSYS,
+        SCSI_DH_DRIVER_MAX,
+};
+#if defined(CONFIG_SCSI_DH) || defined(CONFIG_SCSI_DH_MODULE)
+extern int scsi_dh_activate(struct request_queue *);
+extern int scsi_dh_handler_exist(const char *);
+#else
+static inline int scsi_dh_activate(struct request_queue *req)
+{
+        return 0;
+}
+static inline int scsi_dh_handler_exist(const char *name)
+{
+        return 0;
+}
+#endif
diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h
index aab1eae2ec4c..f5444e033cc9 100644
--- a/include/scsi/scsi_transport_iscsi.h
+++ b/include/scsi/scsi_transport_iscsi.h
@@ -30,11 +30,11 @@
 
 struct scsi_transport_template;
 struct iscsi_transport;
+struct iscsi_endpoint;
 struct Scsi_Host;
 struct iscsi_cls_conn;
 struct iscsi_conn;
-struct iscsi_cmd_task;
-struct iscsi_mgmt_task;
+struct iscsi_task;
 struct sockaddr;
 
 /**
@@ -58,19 +58,22 @@ struct sockaddr;
  * @stop_conn:          suspend/recover/terminate connection
  * @send_pdu:           send iSCSI PDU, Login, Logout, NOP-Out, Reject, Text.
  * @session_recovery_timedout: notify LLD a block during recovery timed out
- * @init_cmd_task:      Initialize a iscsi_cmd_task and any internal structs.
- *                      Called from queuecommand with session lock held.
- * @init_mgmt_task:     Initialize a iscsi_mgmt_task and any internal structs.
- *                      Called from iscsi_conn_send_generic with xmitmutex.
- * @xmit_cmd_task:      Requests LLD to transfer cmd task. Returns 0 or the
+ * @init_task:          Initialize a iscsi_task and any internal structs.
+ *                      When offloading the data path, this is called from
+ *                      queuecommand with the session lock, or from the
+ *                      iscsi_conn_send_pdu context with the session lock.
+ *                      When not offloading the data path, this is called
+ *                      from the scsi work queue without the session lock.
+ * @xmit_task           Requests LLD to transfer cmd task. Returns 0 or the
  *                      the number of bytes transferred on success, and -Exyz
- *                      value on error.
- * @xmit_mgmt_task:     Requests LLD to transfer mgmt task. Returns 0 or the
- *                      the number of bytes transferred on success, and -Exyz
- *                      value on error.
- * @cleanup_cmd_task:   requests LLD to fail cmd task. Called with xmitmutex
- *                      and session->lock after the connection has been
- *                      suspended and terminated during recovery. If called
+ *                      value on error. When offloading the data path, this
+ *                      is called from queuecommand with the session lock, or
+ *                      from the iscsi_conn_send_pdu context with the session
+ *                      lock. When not offloading the data path, this is called
+ *                      from the scsi work queue without the session lock.
+ * @cleanup_task:       requests LLD to fail task. Called with session lock
+ *                      and after the connection has been suspended and
+ *                      terminated during recovery. If called
  *                      from abort task then connection is not suspended
  *                      or terminated but sk_callback_lock is held
  *
@@ -83,17 +86,9 @@ struct iscsi_transport {
         /* LLD sets this to indicate what values it can export to sysfs */
         uint64_t param_mask;
         uint64_t host_param_mask;
-        struct scsi_host_template *host_template;
-        /* LLD connection data size */
-        int conndata_size;
-        /* LLD session data size */
-        int sessiondata_size;
-        int max_lun;
-        unsigned int max_conn;
-        unsigned int max_cmd_len;
-        struct iscsi_cls_session *(*create_session) (struct iscsi_transport *it,
-                struct scsi_transport_template *t, uint16_t, uint16_t,
-                uint32_t sn, uint32_t *hn);
+        struct iscsi_cls_session *(*create_session) (struct iscsi_endpoint *ep,
+                                        uint16_t cmds_max, uint16_t qdepth,
+                                        uint32_t sn, uint32_t *hn);
         void (*destroy_session) (struct iscsi_cls_session *session);
         struct iscsi_cls_conn *(*create_conn) (struct iscsi_cls_session *sess,
                                 uint32_t cid);
@@ -118,20 +113,15 @@ struct iscsi_transport {
                          char *data, uint32_t data_size);
         void (*get_stats) (struct iscsi_cls_conn *conn,
                            struct iscsi_stats *stats);
-        int (*init_cmd_task) (struct iscsi_cmd_task *ctask);
-        void (*init_mgmt_task) (struct iscsi_conn *conn,
-                                struct iscsi_mgmt_task *mtask);
-        int (*xmit_cmd_task) (struct iscsi_conn *conn,
-                              struct iscsi_cmd_task *ctask);
-        void (*cleanup_cmd_task) (struct iscsi_conn *conn,
-                                  struct iscsi_cmd_task *ctask);
-        int (*xmit_mgmt_task) (struct iscsi_conn *conn,
-                               struct iscsi_mgmt_task *mtask);
+        int (*init_task) (struct iscsi_task *task);
+        int (*xmit_task) (struct iscsi_task *task);
+        void (*cleanup_task) (struct iscsi_conn *conn,
+                                  struct iscsi_task *task);
         void (*session_recovery_timedout) (struct iscsi_cls_session *session);
-        int (*ep_connect) (struct sockaddr *dst_addr, int non_blocking,
-                           uint64_t *ep_handle);
-        int (*ep_poll) (uint64_t ep_handle, int timeout_ms);
-        void (*ep_disconnect) (uint64_t ep_handle);
+        struct iscsi_endpoint *(*ep_connect) (struct sockaddr *dst_addr,
+                                              int non_blocking);
+        int (*ep_poll) (struct iscsi_endpoint *ep, int timeout_ms);
+        void (*ep_disconnect) (struct iscsi_endpoint *ep);
         int (*tgt_dscvr) (struct Scsi_Host *shost, enum iscsi_tgt_dscvr type,
                           uint32_t enable, struct sockaddr *dst_addr);
 };
@@ -172,9 +162,10 @@ enum {
         ISCSI_SESSION_FREE,
 };
 
+#define ISCSI_MAX_TARGET -1
+
 struct iscsi_cls_session {
         struct list_head sess_list;             /* item in session_list */
-        struct list_head host_list;
         struct iscsi_transport *transport;
         spinlock_t lock;
         struct work_struct block_work;
@@ -186,7 +177,7 @@ struct iscsi_cls_session {
         int recovery_tmo;
         struct delayed_work recovery_work;
 
-        int target_id;
+        unsigned int target_id;
 
         int state;
         int sid;                                /* session id */
@@ -203,14 +194,22 @@ struct iscsi_cls_session {
 #define starget_to_session(_stgt) \
         iscsi_dev_to_session(_stgt->dev.parent)
 
-struct iscsi_host {
-        struct list_head sessions;
+struct iscsi_cls_host {
         atomic_t nr_scans;
         struct mutex mutex;
         struct workqueue_struct *scan_workq;
         char scan_workq_name[KOBJ_NAME_LEN];
 };
 
+extern void iscsi_host_for_each_session(struct Scsi_Host *shost,
+                                void (*fn)(struct iscsi_cls_session *));
+
+struct iscsi_endpoint {
+        void *dd_data;                  /* LLD private data */
+        struct device dev;
+        unsigned int id;
+};
+
 /*
  * session and connection functions that can be used by HW iSCSI LLDs
  */
@@ -222,22 +221,26 @@ struct iscsi_host {
 
 extern int iscsi_session_chkready(struct iscsi_cls_session *session);
 extern struct iscsi_cls_session *iscsi_alloc_session(struct Scsi_Host *shost,
-                                        struct iscsi_transport *transport);
+                                struct iscsi_transport *transport, int dd_size);
 extern int iscsi_add_session(struct iscsi_cls_session *session,
                              unsigned int target_id);
 extern int iscsi_session_event(struct iscsi_cls_session *session,
                                enum iscsi_uevent_e event);
 extern struct iscsi_cls_session *iscsi_create_session(struct Scsi_Host *shost,
                                                 struct iscsi_transport *t,
+                                                int dd_size,
                                                 unsigned int target_id);
 extern void iscsi_remove_session(struct iscsi_cls_session *session);
 extern void iscsi_free_session(struct iscsi_cls_session *session);
 extern int iscsi_destroy_session(struct iscsi_cls_session *session);
 extern struct iscsi_cls_conn *iscsi_create_conn(struct iscsi_cls_session *sess,
-                                            uint32_t cid);
+                                                int dd_size, uint32_t cid);
 extern int iscsi_destroy_conn(struct iscsi_cls_conn *conn);
 extern void iscsi_unblock_session(struct iscsi_cls_session *session);
 extern void iscsi_block_session(struct iscsi_cls_session *session);
 extern int iscsi_scan_finished(struct Scsi_Host *shost, unsigned long time);
+extern struct iscsi_endpoint *iscsi_create_endpoint(int dd_size);
+extern void iscsi_destroy_endpoint(struct iscsi_endpoint *ep);
+extern struct iscsi_endpoint *iscsi_lookup_endpoint(u64 handle);
 
 #endif
diff --git a/include/scsi/sd.h b/include/scsi/sd.h
deleted file mode 100644
index 4f032d48cb6e..000000000000
--- a/include/scsi/sd.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef _SCSI_DISK_H
-#define _SCSI_DISK_H
-
-/*
- * More than enough for everybody ;)  The huge number of majors
- * is a leftover from 16bit dev_t days, we don't really need that
- * much numberspace.
- */
-#define SD_MAJORS       16
-
-/*
- * This is limited by the naming scheme enforced in sd_probe,
- * add another character to it if you really need more disks.
- */
-#define SD_MAX_DISKS    (((26 * 26) + 26 + 1) * 26)
-
-/*
- * Time out in seconds for disks and Magneto-opticals (which are slower).
- */
-#define SD_TIMEOUT              (30 * HZ)
-#define SD_MOD_TIMEOUT          (75 * HZ)
-
-/*
- * Number of allowed retries
- */
-#define SD_MAX_RETRIES          5
-#define SD_PASSTHROUGH_RETRIES  1
-
-/*
- * Size of the initial data buffer for mode and read capacity data
- */
-#define SD_BUF_SIZE             512
-
-struct scsi_disk {
-        struct scsi_driver *driver;     /* always &sd_template */
-        struct scsi_device *device;
-        struct device   dev;
-        struct gendisk  *disk;
-        unsigned int    openers;        /* protected by BKL for now, yuck */
-        sector_t        capacity;       /* size in 512-byte sectors */
-        u32             index;
-        u8              media_present;
-        u8              write_prot;
-        unsigned        previous_state : 1;
-        unsigned        WCE : 1;        /* state of disk WCE bit */
-        unsigned        RCD : 1;        /* state of disk RCD bit, unused */
-        unsigned        DPOFUA : 1;     /* state of disk DPOFUA bit */
-};
-#define to_scsi_disk(obj) container_of(obj,struct scsi_disk,dev)
-
-#define sd_printk(prefix, sdsk, fmt, a...)                              \
-        (sdsk)->disk ?                                                  \
-        sdev_printk(prefix, (sdsk)->device, "[%s] " fmt,                \
-                    (sdsk)->disk->disk_name, ##a) :                     \
-        sdev_printk(prefix, (sdsk)->device, fmt, ##a)
-
-#endif /* _SCSI_DISK_H */
diff --git a/include/scsi/sg.h b/include/scsi/sg.h
index 519c49a0fc11..934ae389671d 100644
--- a/include/scsi/sg.h
+++ b/include/scsi/sg.h
@@ -206,6 +206,7 @@ typedef struct sg_req_info { /* used by SG_GET_REQUEST_TABLE ioctl() */
 #define         SG_SCSI_RESET_DEVICE    1
 #define         SG_SCSI_RESET_BUS       2
 #define         SG_SCSI_RESET_HOST      3
+#define         SG_SCSI_RESET_TARGET    4
 
 /* synchronous SCSI command ioctl, (only in version 3 interface) */
 #define SG_IO 0x2285   /* similar effect as write() followed by read() */
diff --git a/include/sound/ad1843.h b/include/sound/ad1843.h
new file mode 100644
index 000000000000..b236a9d1d6e4
--- /dev/null
+++ b/include/sound/ad1843.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
+ * Copyright 2008 Thomas Bogendoerfer <tsbogend@franken.de>
+ */
+
+#ifndef __SOUND_AD1843_H
+#define __SOUND_AD1843_H
+
+struct snd_ad1843 {
+        void *chip;
+        int (*read)(void *chip, int reg);
+        int (*write)(void *chip, int reg, int val);
+};
+
+#define AD1843_GAIN_RECLEV 0
+#define AD1843_GAIN_LINE   1
+#define AD1843_GAIN_LINE_2 2
+#define AD1843_GAIN_MIC    3
+#define AD1843_GAIN_PCM_0  4
+#define AD1843_GAIN_PCM_1  5
+#define AD1843_GAIN_SIZE   (AD1843_GAIN_PCM_1+1)
+
+int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id);
+int ad1843_get_gain(struct snd_ad1843 *ad1843, int id);
+int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval);
+int ad1843_get_recsrc(struct snd_ad1843 *ad1843);
+int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc);
+void ad1843_setup_dac(struct snd_ad1843 *ad1843,
+                      unsigned int id,
+                      unsigned int framerate,
+                      snd_pcm_format_t fmt,
+                      unsigned int channels);
+void ad1843_shutdown_dac(struct snd_ad1843 *ad1843,
+                         unsigned int id);
+void ad1843_setup_adc(struct snd_ad1843 *ad1843,
+                      unsigned int framerate,
+                      snd_pcm_format_t fmt,
+                      unsigned int channels);
+void ad1843_shutdown_adc(struct snd_ad1843 *ad1843);
+int ad1843_init(struct snd_ad1843 *ad1843);
+
+#endif /* __SOUND_AD1843_H */
diff --git a/include/sound/control.h b/include/sound/control.h
index 3dc1291f52db..4721b4bba053 100644
--- a/include/sound/control.h
+++ b/include/sound/control.h
@@ -129,9 +129,6 @@ int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn);
 #define snd_ctl_unregister_ioctl_compat(fcn)
 #endif
 
-int snd_ctl_elem_read(struct snd_card *card, struct snd_ctl_elem_value *control);
-int snd_ctl_elem_write(struct snd_card *card, struct snd_ctl_file *file, struct snd_ctl_elem_value *control);
-
 static inline unsigned int snd_ctl_get_ioffnum(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id)
 {
         return id->numid - kctl->id.numid;
diff --git a/include/sound/core.h b/include/sound/core.h
index 695ee53488a3..558b96284bd2 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -412,13 +412,13 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
 
 #endif /* CONFIG_SND_DEBUG */
 
-#ifdef CONFIG_SND_DEBUG_DETECT
+#ifdef CONFIG_SND_DEBUG_VERBOSE
 /**
  * snd_printdd - debug printk
  * @format: format string
  *
  * Works like snd_printk() for debugging purposes.
- * Ignored when CONFIG_SND_DEBUG_DETECT is not set.
+ * Ignored when CONFIG_SND_DEBUG_VERBOSE is not set.
  */
 #define snd_printdd(format, args...) snd_printk(format, ##args)
 #else
@@ -442,7 +442,7 @@ struct snd_pci_quirk {
         unsigned short subvendor;       /* PCI subvendor ID */
         unsigned short subdevice;       /* PCI subdevice ID */
         int value;                      /* value */
-#ifdef CONFIG_SND_DEBUG_DETECT
+#ifdef CONFIG_SND_DEBUG_VERBOSE
         const char *name;               /* name of the device (optional) */
 #endif
 };
@@ -450,7 +450,7 @@ struct snd_pci_quirk {
 #define _SND_PCI_QUIRK_ID(vend,dev) \
         .subvendor = (vend), .subdevice = (dev)
 #define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)}
-#ifdef CONFIG_SND_DEBUG_DETECT
+#ifdef CONFIG_SND_DEBUG_VERBOSE
 #define SND_PCI_QUIRK(vend,dev,xname,val) \
         {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)}
 #else
diff --git a/include/sound/cs4231-regs.h b/include/sound/cs4231-regs.h
index e8d1f3e31f9e..92647532c454 100644
--- a/include/sound/cs4231-regs.h
+++ b/include/sound/cs4231-regs.h
@@ -177,4 +177,12 @@
 #define CS4236_RIGHT_WAVE       0x1c    /* right wavetable serial port volume */
 #define CS4236_VERSION          0x9c    /* chip version and ID */
 
+/* definitions for extended registers - OPTI93X */
+#define OPTi931_AUX_LEFT_INPUT  0x10
+#define OPTi931_AUX_RIGHT_INPUT 0x11
+#define OPTi93X_MIC_LEFT_INPUT  0x14
+#define OPTi93X_MIC_RIGHT_INPUT 0x15
+#define OPTi93X_OUT_LEFT        0x16
+#define OPTi93X_OUT_RIGHT       0x17
+
 #endif /* __SOUND_CS4231_REGS_H */
diff --git a/include/sound/cs4231.h b/include/sound/cs4231.h
index 66055d702aa3..f0785f9f4ae4 100644
--- a/include/sound/cs4231.h
+++ b/include/sound/cs4231.h
@@ -58,6 +58,7 @@
 /* compatible, but clones */
 #define CS4231_HW_INTERWAVE     0x1000  /* InterWave chip */
 #define CS4231_HW_OPL3SA2       0x1101  /* OPL3-SA2 chip, similar to cs4231 */
+#define CS4231_HW_OPTI93X       0x1102  /* Opti 930/931/933 */
 
 /* defines for codec.hwshare */
 #define CS4231_HWSHARE_IRQ      (1<<0)
@@ -120,6 +121,8 @@ unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg);
 void snd_cs4231_mce_up(struct snd_cs4231 *chip);
 void snd_cs4231_mce_down(struct snd_cs4231 *chip);
 
+void snd_cs4231_overrange(struct snd_cs4231 *chip);
+
 irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id);
 
 const char *snd_cs4231_chip_id(struct snd_cs4231 *chip);
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 7b7b9b13b4dd..10ee28eac018 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -1670,6 +1670,7 @@ struct snd_emu_chip_details {
         unsigned char spi_dac;      /* SPI interface for DAC */
         unsigned char i2c_adc;      /* I2C interface for ADC */
         unsigned char adc_1361t;    /* Use Philips 1361T ADC */
+        unsigned char invert_shared_spdif; /* analog/digital switch inverted */
         const char *driver;
         const char *name;
         const char *id;         /* for backward compatibility - can be NULL if not needed */
diff --git a/include/sound/seq_kernel.h b/include/sound/seq_kernel.h
index f023c1b97f8c..3d9afb6a8c9c 100644
--- a/include/sound/seq_kernel.h
+++ b/include/sound/seq_kernel.h
@@ -105,7 +105,7 @@ int snd_seq_event_port_attach(int client, struct snd_seq_port_callback *pcbp,
                               int cap, int type, int midi_channels, int midi_voices, char *portname);
 int snd_seq_event_port_detach(int client, int port);
 
-#ifdef CONFIG_KMOD
+#ifdef CONFIG_MODULES
 void snd_seq_autoload_lock(void);
 void snd_seq_autoload_unlock(void);
 #else
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index a105b01e06d5..3030fdc6981d 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -130,6 +130,13 @@
 {       .id = snd_soc_dapm_adc, .name = wname, .sname = stname, .reg = wreg, \
         .shift = wshift, .invert = winvert}
 
+/* generic register modifier widget */
+#define SND_SOC_DAPM_REG(wid, wname, wreg, wshift, wmask, won_val, woff_val) \
+{       .id = wid, .name = wname, .kcontrols = NULL, .num_kcontrols = 0, \
+        .reg = -((wreg) + 1), .shift = wshift, .mask = wmask, \
+        .on_val = won_val, .off_val = woff_val, .event = dapm_reg_event, \
+        .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD}
+
 /* dapm kcontrol types */
 #define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
@@ -193,6 +200,7 @@ struct snd_soc_dapm_widget;
 enum snd_soc_dapm_type;
 struct snd_soc_dapm_path;
 struct snd_soc_dapm_pin;
+struct snd_soc_dapm_route;
 
 /* dapm controls */
 int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
@@ -205,25 +213,32 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
         struct snd_ctl_elem_value *ucontrol);
 int snd_soc_dapm_new_control(struct snd_soc_codec *codec,
         const struct snd_soc_dapm_widget *widget);
+int snd_soc_dapm_new_controls(struct snd_soc_codec *codec,
+        const struct snd_soc_dapm_widget *widget,
+        int num);
 
 /* dapm path setup */
-int snd_soc_dapm_connect_input(struct snd_soc_codec *codec,
+int  __deprecated snd_soc_dapm_connect_input(struct snd_soc_codec *codec,
         const char *sink_name, const char *control_name, const char *src_name);
 int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec);
 void snd_soc_dapm_free(struct snd_soc_device *socdev);
+int snd_soc_dapm_add_routes(struct snd_soc_codec *codec,
+                            const struct snd_soc_dapm_route *route, int num);
 
 /* dapm events */
 int snd_soc_dapm_stream_event(struct snd_soc_codec *codec, char *stream,
         int event);
-int snd_soc_dapm_device_event(struct snd_soc_device *socdev, int event);
+int snd_soc_dapm_set_bias_level(struct snd_soc_device *socdev,
+        enum snd_soc_bias_level level);
 
 /* dapm sys fs - used by the core */
 int snd_soc_dapm_sys_add(struct device *dev);
 
-/* dapm audio endpoint control */
-int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
-        char *pin, int status);
-int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec);
+/* dapm audio pin control and status */
+int snd_soc_dapm_enable_pin(struct snd_soc_codec *codec, char *pin);
+int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, char *pin);
+int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin);
+int snd_soc_dapm_sync(struct snd_soc_codec *codec);
 
 /* dapm widget types */
 enum snd_soc_dapm_type {
@@ -245,6 +260,18 @@ enum snd_soc_dapm_type {
         snd_soc_dapm_post,                      /* machine specific post widget - exec last */
 };
 
+/*
+ * DAPM audio route definition.
+ *
+ * Defines an audio route originating at source via control and finishing
+ * at sink.
+ */
+struct snd_soc_dapm_route {
+        const char *sink;
+        const char *control;
+        const char *source;
+};
+
 /* dapm audio path between two widgets */
 struct snd_soc_dapm_path {
         char *name;
@@ -277,6 +304,9 @@ struct snd_soc_dapm_widget {
         unsigned char shift;                    /* bits to shift */
         unsigned int saved_value;               /* widget saved value */
         unsigned int value;                             /* widget current value */
+        unsigned int mask;                      /* non-shifted mask */
+        unsigned int on_val;                    /* on state value */
+        unsigned int off_val;                   /* off state value */
         unsigned char power:1;                  /* block power status */
         unsigned char invert:1;                 /* invert the power bit */
         unsigned char active:1;                 /* active stream on DAC, ADC's */
diff --git a/include/sound/soc.h b/include/sound/soc.h
index d3c8c033dff8..1890d87c5204 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -73,6 +73,15 @@
         .get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \
         .private_value = (reg_left) | ((shift) << 8)  | \
                 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
+#define SOC_DOUBLE_S8_TLV(xname, reg, min, max, tlv_array) \
+{       .iface  = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
+                  SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+        .tlv.p  = (tlv_array), \
+        .info   = snd_soc_info_volsw_s8, .get = snd_soc_get_volsw_s8, \
+        .put    = snd_soc_put_volsw_s8, \
+        .private_value = (reg) | (((signed char)max) << 16) | \
+                         (((signed char)min) << 24) }
 #define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xtexts) \
 {       .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \
         .mask = xmask, .texts = xtexts }
@@ -91,6 +100,15 @@
         .info = snd_soc_info_volsw, \
         .get = xhandler_get, .put = xhandler_put, \
         .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) }
+#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmask, xinvert,\
+         xhandler_get, xhandler_put, tlv_array) \
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+                 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .tlv.p = (tlv_array), \
+        .info = snd_soc_info_volsw, \
+        .get = xhandler_get, .put = xhandler_put, \
+        .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) }
 #define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
         .info = snd_soc_info_bool_ext, \
@@ -103,6 +121,24 @@
         .private_value = (unsigned long)&xenum }
 
 /*
+ * Bias levels
+ *
+ * @ON:      Bias is fully on for audio playback and capture operations.
+ * @PREPARE: Prepare for audio operations. Called before DAPM switching for
+ *           stream start and stop operations.
+ * @STANDBY: Low power standby state when no playback/capture operations are
+ *           in progress. NOTE: The transition time between STANDBY and ON
+ *           should be as fast as possible and no longer than 10ms.
+ * @OFF:     Power Off. No restrictions on transition times.
+ */
+enum snd_soc_bias_level {
+        SND_SOC_BIAS_ON,
+        SND_SOC_BIAS_PREPARE,
+        SND_SOC_BIAS_STANDBY,
+        SND_SOC_BIAS_OFF,
+};
+
+/*
  * Digital Audio Interface (DAI) types
  */
 #define SND_SOC_DAI_AC97        0x1
@@ -185,8 +221,7 @@ struct snd_soc_pcm_stream;
 struct snd_soc_ops;
 struct snd_soc_dai_mode;
 struct snd_soc_pcm_runtime;
-struct snd_soc_codec_dai;
-struct snd_soc_cpu_dai;
+struct snd_soc_dai;
 struct snd_soc_codec;
 struct snd_soc_machine_config;
 struct soc_enum;
@@ -221,6 +256,27 @@ int snd_soc_new_ac97_codec(struct snd_soc_codec *codec,
         struct snd_ac97_bus_ops *ops, int num);
 void snd_soc_free_ac97_codec(struct snd_soc_codec *codec);
 
+/* Digital Audio Interface clocking API.*/
+int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+        unsigned int freq, int dir);
+
+int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai,
+        int div_id, int div);
+
+int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
+        int pll_id, unsigned int freq_in, unsigned int freq_out);
+
+/* Digital Audio interface formatting */
+int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
+
+int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai,
+        unsigned int mask, int slots);
+
+int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate);
+
+/* Digital Audio Interface mute */
+int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute);
+
 /*
  *Controls
  */
@@ -249,6 +305,12 @@ int snd_soc_get_volsw_2r(struct snd_kcontrol *kcontrol,
         struct snd_ctl_elem_value *ucontrol);
 int snd_soc_put_volsw_2r(struct snd_kcontrol *kcontrol,
         struct snd_ctl_elem_value *ucontrol);
+int snd_soc_info_volsw_s8(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_info *uinfo);
+int snd_soc_get_volsw_s8(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol);
+int snd_soc_put_volsw_s8(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol);
 
 /* SoC PCM stream information */
 struct snd_soc_pcm_stream {
@@ -272,87 +334,45 @@ struct snd_soc_ops {
         int (*trigger)(struct snd_pcm_substream *, int);
 };
 
-/* ASoC codec DAI ops */
-struct snd_soc_codec_ops {
-        /* codec DAI clocking configuration */
-        int (*set_sysclk)(struct snd_soc_codec_dai *codec_dai,
+/* ASoC DAI ops */
+struct snd_soc_dai_ops {
+        /* DAI clocking configuration */
+        int (*set_sysclk)(struct snd_soc_dai *dai,
                 int clk_id, unsigned int freq, int dir);
-        int (*set_pll)(struct snd_soc_codec_dai *codec_dai,
+        int (*set_pll)(struct snd_soc_dai *dai,
                 int pll_id, unsigned int freq_in, unsigned int freq_out);
-        int (*set_clkdiv)(struct snd_soc_codec_dai *codec_dai,
-                int div_id, int div);
+        int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div);
 
-        /* CPU DAI format configuration */
-        int (*set_fmt)(struct snd_soc_codec_dai *codec_dai,
-                unsigned int fmt);
-        int (*set_tdm_slot)(struct snd_soc_codec_dai *codec_dai,
+        /* DAI format configuration */
+        int (*set_fmt)(struct snd_soc_dai *dai, unsigned int fmt);
+        int (*set_tdm_slot)(struct snd_soc_dai *dai,
                 unsigned int mask, int slots);
-        int (*set_tristate)(struct snd_soc_codec_dai *, int tristate);
+        int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
 
         /* digital mute */
-        int (*digital_mute)(struct snd_soc_codec_dai *, int mute);
-};
-
-/* ASoC cpu DAI ops */
-struct snd_soc_cpu_ops {
-        /* CPU DAI clocking configuration */
-        int (*set_sysclk)(struct snd_soc_cpu_dai *cpu_dai,
-                int clk_id, unsigned int freq, int dir);
-        int (*set_clkdiv)(struct snd_soc_cpu_dai *cpu_dai,
-                int div_id, int div);
-        int (*set_pll)(struct snd_soc_cpu_dai *cpu_dai,
-                int pll_id, unsigned int freq_in, unsigned int freq_out);
-
-        /* CPU DAI format configuration */
-        int (*set_fmt)(struct snd_soc_cpu_dai *cpu_dai,
-                unsigned int fmt);
-        int (*set_tdm_slot)(struct snd_soc_cpu_dai *cpu_dai,
-                unsigned int mask, int slots);
-        int (*set_tristate)(struct snd_soc_cpu_dai *, int tristate);
-};
-
-/* SoC Codec DAI */
-struct snd_soc_codec_dai {
-        char *name;
-        int id;
-        unsigned char type;
-
-        /* DAI capabilities */
-        struct snd_soc_pcm_stream playback;
-        struct snd_soc_pcm_stream capture;
-
-        /* DAI runtime info */
-        struct snd_soc_codec *codec;
-        unsigned int active;
-        unsigned char pop_wait:1;
-
-        /* ops */
-        struct snd_soc_ops ops;
-        struct snd_soc_codec_ops dai_ops;
-
-        /* DAI private data */
-        void *private_data;
+        int (*digital_mute)(struct snd_soc_dai *dai, int mute);
 };
 
-/* SoC CPU DAI */
-struct snd_soc_cpu_dai {
-
+/* SoC  DAI (Digital Audio Interface) */
+struct snd_soc_dai {
         /* DAI description */
         char *name;
         unsigned int id;
         unsigned char type;
 
         /* DAI callbacks */
-        int (*probe)(struct platform_device *pdev);
-        void (*remove)(struct platform_device *pdev);
+        int (*probe)(struct platform_device *pdev,
+                     struct snd_soc_dai *dai);
+        void (*remove)(struct platform_device *pdev,
+                       struct snd_soc_dai *dai);
         int (*suspend)(struct platform_device *pdev,
-                struct snd_soc_cpu_dai *cpu_dai);
+                struct snd_soc_dai *dai);
         int (*resume)(struct platform_device *pdev,
-                struct snd_soc_cpu_dai *cpu_dai);
+                struct snd_soc_dai *dai);
 
         /* ops */
         struct snd_soc_ops ops;
-        struct snd_soc_cpu_ops dai_ops;
+        struct snd_soc_dai_ops dai_ops;
 
         /* DAI capabilities */
         struct snd_soc_pcm_stream capture;
@@ -360,7 +380,9 @@ struct snd_soc_cpu_dai {
 
         /* DAI runtime info */
         struct snd_pcm_runtime *runtime;
-        unsigned char active:1;
+        struct snd_soc_codec *codec;
+        unsigned int active;
+        unsigned char pop_wait:1;
         void *dma_data;
 
         /* DAI private data */
@@ -374,7 +396,8 @@ struct snd_soc_codec {
         struct mutex mutex;
 
         /* callbacks */
-        int (*dapm_event)(struct snd_soc_codec *codec, int event);
+        int (*set_bias_level)(struct snd_soc_codec *,
+                              enum snd_soc_bias_level level);
 
         /* runtime */
         struct snd_card *card;
@@ -396,12 +419,12 @@ struct snd_soc_codec {
         /* dapm */
         struct list_head dapm_widgets;
         struct list_head dapm_paths;
-        unsigned int dapm_state;
-        unsigned int suspend_dapm_state;
+        enum snd_soc_bias_level bias_level;
+        enum snd_soc_bias_level suspend_bias_level;
         struct delayed_work delayed_work;
 
         /* codec DAI's */
-        struct snd_soc_codec_dai *dai;
+        struct snd_soc_dai *dai;
         unsigned int num_dai;
 };
 
@@ -420,12 +443,12 @@ struct snd_soc_platform {
         int (*probe)(struct platform_device *pdev);
         int (*remove)(struct platform_device *pdev);
         int (*suspend)(struct platform_device *pdev,
-                struct snd_soc_cpu_dai *cpu_dai);
+                struct snd_soc_dai *dai);
         int (*resume)(struct platform_device *pdev,
-                struct snd_soc_cpu_dai *cpu_dai);
+                struct snd_soc_dai *dai);
 
         /* pcm creation and destruction */
-        int (*pcm_new)(struct snd_card *, struct snd_soc_codec_dai *,
+        int (*pcm_new)(struct snd_card *, struct snd_soc_dai *,
                 struct snd_pcm *);
         void (*pcm_free)(struct snd_pcm *);
 
@@ -439,8 +462,8 @@ struct snd_soc_dai_link  {
         char *stream_name;              /* Stream name */
 
         /* DAI */
-        struct snd_soc_codec_dai *codec_dai;
-        struct snd_soc_cpu_dai *cpu_dai;
+        struct snd_soc_dai *codec_dai;
+        struct snd_soc_dai *cpu_dai;
 
         /* machine stream operations */
         struct snd_soc_ops *ops;
@@ -467,7 +490,8 @@ struct snd_soc_machine {
         int (*resume_post)(struct platform_device *pdev);
 
         /* callbacks */
-        int (*dapm_event)(struct snd_soc_machine *, int event);
+        int (*set_bias_level)(struct snd_soc_machine *,
+                              enum snd_soc_bias_level level);
 
         /* CPU <--> Codec DAI links  */
         struct snd_soc_dai_link *dai_link;
@@ -482,6 +506,7 @@ struct snd_soc_device {
         struct snd_soc_codec *codec;
         struct snd_soc_codec_device *codec_dev;
         struct delayed_work delayed_work;
+        struct work_struct deferred_resume_work;
         void *codec_data;
 };
 
diff --git a/include/sound/uda1341.h b/include/sound/uda1341.h
index 2e564bfb37fe..110d5dc3a2be 100644
--- a/include/sound/uda1341.h
+++ b/include/sound/uda1341.h
@@ -15,8 +15,6 @@
  *                           features support
  */
 
-/* $Id: uda1341.h,v 1.8 2005/11/17 14:17:21 tiwai Exp $ */
-
 #define UDA1341_ALSA_NAME "snd-uda1341"
 
 /*
diff --git a/include/sound/version.h b/include/sound/version.h
index ed6fb2eb1eac..6b78aff273a8 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
-/* include/version.h.  Generated by alsa/ksync script.  */
-#define CONFIG_SND_VERSION "1.0.16"
+/* include/version.h */
+#define CONFIG_SND_VERSION "1.0.17"
 #define CONFIG_SND_DATE ""