diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-15 19:37:40 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-15 19:37:40 -0500 |
commit | db0b2d01163cc3050eb52a979541e0d16553be48 (patch) | |
tree | 2a4370fc568e444c98913100b2a520035cc99930 /include | |
parent | 16cd9d1c0f149ee0c8073de037e7c57886234aa0 (diff) | |
parent | 90b128ed1557c2f523995a379a53e5105891ecf8 (diff) |
Merge tag 'mfd-3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-next
Pull MFD updates from Samuel Ortiz:
"For the 3.13 merge window we have a couple of new drivers for the AMS
AS3722 PMIC and for STMicroelectronics STw481x PMIC.
Although this is a smaller update than usual, we also have:
- Device tree support for the max77693 driver
- linux/of.h inclusion for all DT compatible MFD drivers, to avoid
build breakage in the future
- Support for Intel Wildcat Point-LP PCH through the lpc_ich driver
- A small arizona update for new wm5110 DSP registers and a few fixes
- A small palmas update as well, including an of_device table
addition and a few minor fixes
- Two small mfd-core changes, one including a memory leak fix for
when mfd_add_device() fails
- Our usual round of minor cleanups and janitorial fixes"
* tag 'mfd-3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-next: (63 commits)
Documentation: mfd: Update s2mps11.txt
mfd: pm8921: Potential NULL dereference in pm8921_remove()
mfd: Fix memory leak in mfd_add_devices()
mfd: Stop setting refcounting pointers in original mfd_cell arrays
mfd: wm5110: Enable micd clamp functionality
mfd: lpc_ich: Add Device IDs for Intel Wildcat Point-LP PCH
mfd: max77693: Fix up bug of wrong interrupt number
mfd: as3722: Don't export the regmap config
mfd: twl6040: Remove obsolete cleanup for i2c clientdata
mfd: tps65910: Remove warning during dt node parsing
mfd: lpc_sch: Ignore resource conflicts when adding mfd cells
mfd: ti_am335x_tscadc: Avoid possible deadlock of reg_lock
mfd: syscon: Return -ENOSYS if CONFIG_MFD_SYSCON is not enabled
mfd: Add support for ams AS3722 PMIC
mfd: max77693: Include linux/of.h header
mfd: tc3589x: Detect the precise version
mfd: omap-usb: prepare/unprepare clock while enable/disable
mfd: max77686: Include linux/of.h header
mfd: max8907: Include linux/of.h header
mfd: max8997: Include linux/of.h header
...
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/mfd/as3722.h | 52 | ||||
-rw-r--r-- | include/linux/mfd/arizona/registers.h | 2 | ||||
-rw-r--r-- | include/linux/mfd/as3722.h | 423 | ||||
-rw-r--r-- | include/linux/mfd/core.h | 2 | ||||
-rw-r--r-- | include/linux/mfd/da9052/da9052.h | 20 | ||||
-rw-r--r-- | include/linux/mfd/max77693-private.h | 1 | ||||
-rw-r--r-- | include/linux/mfd/max77693.h | 2 | ||||
-rw-r--r-- | include/linux/mfd/rtsx_pci.h | 53 | ||||
-rw-r--r-- | include/linux/mfd/stw481x.h | 56 | ||||
-rw-r--r-- | include/linux/mfd/syscon.h | 25 | ||||
-rw-r--r-- | include/linux/mfd/ti_am335x_tscadc.h | 20 | ||||
-rw-r--r-- | include/linux/mfd/wm8994/core.h | 47 |
12 files changed, 674 insertions, 29 deletions
diff --git a/include/dt-bindings/mfd/as3722.h b/include/dt-bindings/mfd/as3722.h new file mode 100644 index 000000000000..0e692562d77b --- /dev/null +++ b/include/dt-bindings/mfd/as3722.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * This header provides macros for ams AS3722 device bindings. | ||
3 | * | ||
4 | * Copyright (c) 2013, NVIDIA Corporation. | ||
5 | * | ||
6 | * Author: Laxman Dewangan <ldewangan@nvidia.com> | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #ifndef __DT_BINDINGS_AS3722_H__ | ||
11 | #define __DT_BINDINGS_AS3722_H__ | ||
12 | |||
13 | /* External control pins */ | ||
14 | #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 | ||
15 | #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 | ||
16 | #define AS3722_EXT_CONTROL_PIN_ENABLE2 3 | ||
17 | |||
18 | /* Interrupt numbers for AS3722 */ | ||
19 | #define AS3722_IRQ_LID 0 | ||
20 | #define AS3722_IRQ_ACOK 1 | ||
21 | #define AS3722_IRQ_ENABLE1 2 | ||
22 | #define AS3722_IRQ_OCCUR_ALARM_SD0 3 | ||
23 | #define AS3722_IRQ_ONKEY_LONG_PRESS 4 | ||
24 | #define AS3722_IRQ_ONKEY 5 | ||
25 | #define AS3722_IRQ_OVTMP 6 | ||
26 | #define AS3722_IRQ_LOWBAT 7 | ||
27 | #define AS3722_IRQ_SD0_LV 8 | ||
28 | #define AS3722_IRQ_SD1_LV 9 | ||
29 | #define AS3722_IRQ_SD2_LV 10 | ||
30 | #define AS3722_IRQ_PWM1_OV_PROT 11 | ||
31 | #define AS3722_IRQ_PWM2_OV_PROT 12 | ||
32 | #define AS3722_IRQ_ENABLE2 13 | ||
33 | #define AS3722_IRQ_SD6_LV 14 | ||
34 | #define AS3722_IRQ_RTC_REP 15 | ||
35 | #define AS3722_IRQ_RTC_ALARM 16 | ||
36 | #define AS3722_IRQ_GPIO1 17 | ||
37 | #define AS3722_IRQ_GPIO2 18 | ||
38 | #define AS3722_IRQ_GPIO3 19 | ||
39 | #define AS3722_IRQ_GPIO4 20 | ||
40 | #define AS3722_IRQ_GPIO5 21 | ||
41 | #define AS3722_IRQ_WATCHDOG 22 | ||
42 | #define AS3722_IRQ_ENABLE3 23 | ||
43 | #define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 | ||
44 | #define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 | ||
45 | #define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 | ||
46 | #define AS3722_IRQ_TEMP_SD0_ALARM 27 | ||
47 | #define AS3722_IRQ_TEMP_SD1_ALARM 28 | ||
48 | #define AS3722_IRQ_TEMP_SD6_ALARM 29 | ||
49 | #define AS3722_IRQ_OCCUR_ALARM_SD6 30 | ||
50 | #define AS3722_IRQ_ADC 31 | ||
51 | |||
52 | #endif /* __DT_BINDINGS_AS3722_H__ */ | ||
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index 4706d3d46e56..cb49417f8ba9 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h | |||
@@ -1908,7 +1908,7 @@ | |||
1908 | #define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */ | 1908 | #define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */ |
1909 | #define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */ | 1909 | #define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */ |
1910 | #define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */ | 1910 | #define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */ |
1911 | #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */ | 1911 | #define ARIZONA_FLL2_SYNC_BW 0x0001 /* FLL2_SYNC_BW */ |
1912 | #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */ | 1912 | #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */ |
1913 | #define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */ | 1913 | #define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */ |
1914 | #define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */ | 1914 | #define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */ |
diff --git a/include/linux/mfd/as3722.h b/include/linux/mfd/as3722.h new file mode 100644 index 000000000000..16bf8a0dcd97 --- /dev/null +++ b/include/linux/mfd/as3722.h | |||
@@ -0,0 +1,423 @@ | |||
1 | /* | ||
2 | * as3722 definitions | ||
3 | * | ||
4 | * Copyright (C) 2013 ams | ||
5 | * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. | ||
6 | * | ||
7 | * Author: Florian Lobmaier <florian.lobmaier@ams.com> | ||
8 | * Author: Laxman Dewangan <ldewangan@nvidia.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #ifndef __LINUX_MFD_AS3722_H__ | ||
27 | #define __LINUX_MFD_AS3722_H__ | ||
28 | |||
29 | #include <linux/regmap.h> | ||
30 | |||
31 | /* AS3722 registers */ | ||
32 | #define AS3722_SD0_VOLTAGE_REG 0x00 | ||
33 | #define AS3722_SD1_VOLTAGE_REG 0x01 | ||
34 | #define AS3722_SD2_VOLTAGE_REG 0x02 | ||
35 | #define AS3722_SD3_VOLTAGE_REG 0x03 | ||
36 | #define AS3722_SD4_VOLTAGE_REG 0x04 | ||
37 | #define AS3722_SD5_VOLTAGE_REG 0x05 | ||
38 | #define AS3722_SD6_VOLTAGE_REG 0x06 | ||
39 | #define AS3722_GPIO0_CONTROL_REG 0x08 | ||
40 | #define AS3722_GPIO1_CONTROL_REG 0x09 | ||
41 | #define AS3722_GPIO2_CONTROL_REG 0x0A | ||
42 | #define AS3722_GPIO3_CONTROL_REG 0x0B | ||
43 | #define AS3722_GPIO4_CONTROL_REG 0x0C | ||
44 | #define AS3722_GPIO5_CONTROL_REG 0x0D | ||
45 | #define AS3722_GPIO6_CONTROL_REG 0x0E | ||
46 | #define AS3722_GPIO7_CONTROL_REG 0x0F | ||
47 | #define AS3722_LDO0_VOLTAGE_REG 0x10 | ||
48 | #define AS3722_LDO1_VOLTAGE_REG 0x11 | ||
49 | #define AS3722_LDO2_VOLTAGE_REG 0x12 | ||
50 | #define AS3722_LDO3_VOLTAGE_REG 0x13 | ||
51 | #define AS3722_LDO4_VOLTAGE_REG 0x14 | ||
52 | #define AS3722_LDO5_VOLTAGE_REG 0x15 | ||
53 | #define AS3722_LDO6_VOLTAGE_REG 0x16 | ||
54 | #define AS3722_LDO7_VOLTAGE_REG 0x17 | ||
55 | #define AS3722_LDO9_VOLTAGE_REG 0x19 | ||
56 | #define AS3722_LDO10_VOLTAGE_REG 0x1A | ||
57 | #define AS3722_LDO11_VOLTAGE_REG 0x1B | ||
58 | #define AS3722_GPIO_DEB1_REG 0x1E | ||
59 | #define AS3722_GPIO_DEB2_REG 0x1F | ||
60 | #define AS3722_GPIO_SIGNAL_OUT_REG 0x20 | ||
61 | #define AS3722_GPIO_SIGNAL_IN_REG 0x21 | ||
62 | #define AS3722_REG_SEQU_MOD1_REG 0x22 | ||
63 | #define AS3722_REG_SEQU_MOD2_REG 0x23 | ||
64 | #define AS3722_REG_SEQU_MOD3_REG 0x24 | ||
65 | #define AS3722_SD_PHSW_CTRL_REG 0x27 | ||
66 | #define AS3722_SD_PHSW_STATUS 0x28 | ||
67 | #define AS3722_SD0_CONTROL_REG 0x29 | ||
68 | #define AS3722_SD1_CONTROL_REG 0x2A | ||
69 | #define AS3722_SDmph_CONTROL_REG 0x2B | ||
70 | #define AS3722_SD23_CONTROL_REG 0x2C | ||
71 | #define AS3722_SD4_CONTROL_REG 0x2D | ||
72 | #define AS3722_SD5_CONTROL_REG 0x2E | ||
73 | #define AS3722_SD6_CONTROL_REG 0x2F | ||
74 | #define AS3722_SD_DVM_REG 0x30 | ||
75 | #define AS3722_RESET_REASON_REG 0x31 | ||
76 | #define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32 | ||
77 | #define AS3722_STARTUP_CONTROL_REG 0x33 | ||
78 | #define AS3722_RESET_TIMER_REG 0x34 | ||
79 | #define AS3722_REFERENCE_CONTROL_REG 0x35 | ||
80 | #define AS3722_RESET_CONTROL_REG 0x36 | ||
81 | #define AS3722_OVER_TEMP_CONTROL_REG 0x37 | ||
82 | #define AS3722_WATCHDOG_CONTROL_REG 0x38 | ||
83 | #define AS3722_REG_STANDBY_MOD1_REG 0x39 | ||
84 | #define AS3722_REG_STANDBY_MOD2_REG 0x3A | ||
85 | #define AS3722_REG_STANDBY_MOD3_REG 0x3B | ||
86 | #define AS3722_ENABLE_CTRL1_REG 0x3C | ||
87 | #define AS3722_ENABLE_CTRL2_REG 0x3D | ||
88 | #define AS3722_ENABLE_CTRL3_REG 0x3E | ||
89 | #define AS3722_ENABLE_CTRL4_REG 0x3F | ||
90 | #define AS3722_ENABLE_CTRL5_REG 0x40 | ||
91 | #define AS3722_PWM_CONTROL_L_REG 0x41 | ||
92 | #define AS3722_PWM_CONTROL_H_REG 0x42 | ||
93 | #define AS3722_WATCHDOG_TIMER_REG 0x46 | ||
94 | #define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48 | ||
95 | #define AS3722_IOVOLTAGE_REG 0x49 | ||
96 | #define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A | ||
97 | #define AS3722_SD_CONTROL_REG 0x4D | ||
98 | #define AS3722_LDOCONTROL0_REG 0x4E | ||
99 | #define AS3722_LDOCONTROL1_REG 0x4F | ||
100 | #define AS3722_SD0_PROTECT_REG 0x50 | ||
101 | #define AS3722_SD6_PROTECT_REG 0x51 | ||
102 | #define AS3722_PWM_VCONTROL1_REG 0x52 | ||
103 | #define AS3722_PWM_VCONTROL2_REG 0x53 | ||
104 | #define AS3722_PWM_VCONTROL3_REG 0x54 | ||
105 | #define AS3722_PWM_VCONTROL4_REG 0x55 | ||
106 | #define AS3722_BB_CHARGER_REG 0x57 | ||
107 | #define AS3722_CTRL_SEQU1_REG 0x58 | ||
108 | #define AS3722_CTRL_SEQU2_REG 0x59 | ||
109 | #define AS3722_OVCURRENT_REG 0x5A | ||
110 | #define AS3722_OVCURRENT_DEB_REG 0x5B | ||
111 | #define AS3722_SDLV_DEB_REG 0x5C | ||
112 | #define AS3722_OC_PG_CTRL_REG 0x5D | ||
113 | #define AS3722_OC_PG_CTRL2_REG 0x5E | ||
114 | #define AS3722_CTRL_STATUS 0x5F | ||
115 | #define AS3722_RTC_CONTROL_REG 0x60 | ||
116 | #define AS3722_RTC_SECOND_REG 0x61 | ||
117 | #define AS3722_RTC_MINUTE_REG 0x62 | ||
118 | #define AS3722_RTC_HOUR_REG 0x63 | ||
119 | #define AS3722_RTC_DAY_REG 0x64 | ||
120 | #define AS3722_RTC_MONTH_REG 0x65 | ||
121 | #define AS3722_RTC_YEAR_REG 0x66 | ||
122 | #define AS3722_RTC_ALARM_SECOND_REG 0x67 | ||
123 | #define AS3722_RTC_ALARM_MINUTE_REG 0x68 | ||
124 | #define AS3722_RTC_ALARM_HOUR_REG 0x69 | ||
125 | #define AS3722_RTC_ALARM_DAY_REG 0x6A | ||
126 | #define AS3722_RTC_ALARM_MONTH_REG 0x6B | ||
127 | #define AS3722_RTC_ALARM_YEAR_REG 0x6C | ||
128 | #define AS3722_SRAM_REG 0x6D | ||
129 | #define AS3722_RTC_ACCESS_REG 0x6F | ||
130 | #define AS3722_RTC_STATUS_REG 0x73 | ||
131 | #define AS3722_INTERRUPT_MASK1_REG 0x74 | ||
132 | #define AS3722_INTERRUPT_MASK2_REG 0x75 | ||
133 | #define AS3722_INTERRUPT_MASK3_REG 0x76 | ||
134 | #define AS3722_INTERRUPT_MASK4_REG 0x77 | ||
135 | #define AS3722_INTERRUPT_STATUS1_REG 0x78 | ||
136 | #define AS3722_INTERRUPT_STATUS2_REG 0x79 | ||
137 | #define AS3722_INTERRUPT_STATUS3_REG 0x7A | ||
138 | #define AS3722_INTERRUPT_STATUS4_REG 0x7B | ||
139 | #define AS3722_TEMP_STATUS_REG 0x7D | ||
140 | #define AS3722_ADC0_CONTROL_REG 0x80 | ||
141 | #define AS3722_ADC1_CONTROL_REG 0x81 | ||
142 | #define AS3722_ADC0_MSB_RESULT_REG 0x82 | ||
143 | #define AS3722_ADC0_LSB_RESULT_REG 0x83 | ||
144 | #define AS3722_ADC1_MSB_RESULT_REG 0x84 | ||
145 | #define AS3722_ADC1_LSB_RESULT_REG 0x85 | ||
146 | #define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86 | ||
147 | #define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87 | ||
148 | #define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88 | ||
149 | #define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89 | ||
150 | #define AS3722_ADC_CONFIGURATION_REG 0x8A | ||
151 | #define AS3722_ASIC_ID1_REG 0x90 | ||
152 | #define AS3722_ASIC_ID2_REG 0x91 | ||
153 | #define AS3722_LOCK_REG 0x9E | ||
154 | #define AS3722_MAX_REGISTER 0xF4 | ||
155 | |||
156 | #define AS3722_SD0_EXT_ENABLE_MASK 0x03 | ||
157 | #define AS3722_SD1_EXT_ENABLE_MASK 0x0C | ||
158 | #define AS3722_SD2_EXT_ENABLE_MASK 0x30 | ||
159 | #define AS3722_SD3_EXT_ENABLE_MASK 0xC0 | ||
160 | #define AS3722_SD4_EXT_ENABLE_MASK 0x03 | ||
161 | #define AS3722_SD5_EXT_ENABLE_MASK 0x0C | ||
162 | #define AS3722_SD6_EXT_ENABLE_MASK 0x30 | ||
163 | #define AS3722_LDO0_EXT_ENABLE_MASK 0x03 | ||
164 | #define AS3722_LDO1_EXT_ENABLE_MASK 0x0C | ||
165 | #define AS3722_LDO2_EXT_ENABLE_MASK 0x30 | ||
166 | #define AS3722_LDO3_EXT_ENABLE_MASK 0xC0 | ||
167 | #define AS3722_LDO4_EXT_ENABLE_MASK 0x03 | ||
168 | #define AS3722_LDO5_EXT_ENABLE_MASK 0x0C | ||
169 | #define AS3722_LDO6_EXT_ENABLE_MASK 0x30 | ||
170 | #define AS3722_LDO7_EXT_ENABLE_MASK 0xC0 | ||
171 | #define AS3722_LDO9_EXT_ENABLE_MASK 0x0C | ||
172 | #define AS3722_LDO10_EXT_ENABLE_MASK 0x30 | ||
173 | #define AS3722_LDO11_EXT_ENABLE_MASK 0xC0 | ||
174 | |||
175 | #define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07 | ||
176 | #define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01 | ||
177 | #define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18 | ||
178 | #define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03 | ||
179 | #define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60 | ||
180 | #define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05 | ||
181 | |||
182 | #define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07 | ||
183 | #define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01 | ||
184 | #define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18 | ||
185 | #define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03 | ||
186 | |||
187 | /* AS3722 register bits and bit masks */ | ||
188 | #define AS3722_LDO_ILIMIT_MASK BIT(7) | ||
189 | #define AS3722_LDO_ILIMIT_BIT BIT(7) | ||
190 | #define AS3722_LDO0_VSEL_MASK 0x1F | ||
191 | #define AS3722_LDO0_VSEL_MIN 0x01 | ||
192 | #define AS3722_LDO0_VSEL_MAX 0x12 | ||
193 | #define AS3722_LDO0_NUM_VOLT 0x12 | ||
194 | #define AS3722_LDO3_VSEL_MASK 0x3F | ||
195 | #define AS3722_LDO3_VSEL_MIN 0x01 | ||
196 | #define AS3722_LDO3_VSEL_MAX 0x2D | ||
197 | #define AS3722_LDO3_NUM_VOLT 0x2D | ||
198 | #define AS3722_LDO_VSEL_MASK 0x7F | ||
199 | #define AS3722_LDO_VSEL_MIN 0x01 | ||
200 | #define AS3722_LDO_VSEL_MAX 0x7F | ||
201 | #define AS3722_LDO_VSEL_DNU_MIN 0x25 | ||
202 | #define AS3722_LDO_VSEL_DNU_MAX 0x3F | ||
203 | #define AS3722_LDO_NUM_VOLT 0x80 | ||
204 | |||
205 | #define AS3722_LDO0_CTRL BIT(0) | ||
206 | #define AS3722_LDO1_CTRL BIT(1) | ||
207 | #define AS3722_LDO2_CTRL BIT(2) | ||
208 | #define AS3722_LDO3_CTRL BIT(3) | ||
209 | #define AS3722_LDO4_CTRL BIT(4) | ||
210 | #define AS3722_LDO5_CTRL BIT(5) | ||
211 | #define AS3722_LDO6_CTRL BIT(6) | ||
212 | #define AS3722_LDO7_CTRL BIT(7) | ||
213 | #define AS3722_LDO9_CTRL BIT(1) | ||
214 | #define AS3722_LDO10_CTRL BIT(2) | ||
215 | #define AS3722_LDO11_CTRL BIT(3) | ||
216 | |||
217 | #define AS3722_LDO3_MODE_MASK (3 << 6) | ||
218 | #define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6) | ||
219 | #define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0) | ||
220 | #define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1) | ||
221 | #define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2) | ||
222 | #define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3) | ||
223 | |||
224 | #define AS3722_SD_VSEL_MASK 0x7F | ||
225 | #define AS3722_SD0_VSEL_MIN 0x01 | ||
226 | #define AS3722_SD0_VSEL_MAX 0x5A | ||
227 | #define AS3722_SD2_VSEL_MIN 0x01 | ||
228 | #define AS3722_SD2_VSEL_MAX 0x7F | ||
229 | |||
230 | #define AS3722_SDn_CTRL(n) BIT(n) | ||
231 | |||
232 | #define AS3722_SD0_MODE_FAST BIT(4) | ||
233 | #define AS3722_SD1_MODE_FAST BIT(4) | ||
234 | #define AS3722_SD2_MODE_FAST BIT(2) | ||
235 | #define AS3722_SD3_MODE_FAST BIT(6) | ||
236 | #define AS3722_SD4_MODE_FAST BIT(2) | ||
237 | #define AS3722_SD5_MODE_FAST BIT(2) | ||
238 | #define AS3722_SD6_MODE_FAST BIT(4) | ||
239 | |||
240 | #define AS3722_POWER_OFF BIT(1) | ||
241 | |||
242 | #define AS3722_INTERRUPT_MASK1_LID BIT(0) | ||
243 | #define AS3722_INTERRUPT_MASK1_ACOK BIT(1) | ||
244 | #define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2) | ||
245 | #define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3) | ||
246 | #define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4) | ||
247 | #define AS3722_INTERRUPT_MASK1_ONKEY BIT(5) | ||
248 | #define AS3722_INTERRUPT_MASK1_OVTMP BIT(6) | ||
249 | #define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7) | ||
250 | |||
251 | #define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0) | ||
252 | #define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1) | ||
253 | #define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2) | ||
254 | #define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3) | ||
255 | #define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4) | ||
256 | #define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5) | ||
257 | #define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6) | ||
258 | #define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7) | ||
259 | |||
260 | #define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0) | ||
261 | #define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1) | ||
262 | #define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2) | ||
263 | #define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3) | ||
264 | #define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4) | ||
265 | #define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5) | ||
266 | #define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6) | ||
267 | #define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7) | ||
268 | |||
269 | #define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0) | ||
270 | #define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1) | ||
271 | #define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2) | ||
272 | #define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3) | ||
273 | #define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4) | ||
274 | #define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5) | ||
275 | #define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6) | ||
276 | #define AS3722_INTERRUPT_MASK4_ADC BIT(7) | ||
277 | |||
278 | #define AS3722_ADC1_INTERVAL_TIME BIT(0) | ||
279 | #define AS3722_ADC1_INT_MODE_ON BIT(1) | ||
280 | #define AS3722_ADC_BUF_ON BIT(2) | ||
281 | #define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5) | ||
282 | #define AS3722_ADC1_INTEVAL_SCAN BIT(6) | ||
283 | #define AS3722_ADC1_INT_MASK BIT(7) | ||
284 | |||
285 | #define AS3722_ADC_MSB_VAL_MASK 0x7F | ||
286 | #define AS3722_ADC_LSB_VAL_MASK 0x07 | ||
287 | |||
288 | #define AS3722_ADC0_CONV_START BIT(7) | ||
289 | #define AS3722_ADC0_CONV_NOTREADY BIT(7) | ||
290 | #define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F | ||
291 | |||
292 | #define AS3722_ADC1_CONV_START BIT(7) | ||
293 | #define AS3722_ADC1_CONV_NOTREADY BIT(7) | ||
294 | #define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F | ||
295 | |||
296 | /* GPIO modes */ | ||
297 | #define AS3722_GPIO_MODE_MASK 0x07 | ||
298 | #define AS3722_GPIO_MODE_INPUT 0x00 | ||
299 | #define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01 | ||
300 | #define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02 | ||
301 | #define AS3722_GPIO_MODE_ADC_IN 0x03 | ||
302 | #define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04 | ||
303 | #define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05 | ||
304 | #define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06 | ||
305 | #define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07 | ||
306 | #define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK) | ||
307 | |||
308 | #define AS3722_GPIO_INV BIT(7) | ||
309 | #define AS3722_GPIO_IOSF_MASK 0x78 | ||
310 | #define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3) | ||
311 | #define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0) | ||
312 | #define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1) | ||
313 | #define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2) | ||
314 | #define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3) | ||
315 | #define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4) | ||
316 | #define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5) | ||
317 | #define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7) | ||
318 | #define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8) | ||
319 | #define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9) | ||
320 | #define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11) | ||
321 | #define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12) | ||
322 | #define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13) | ||
323 | #define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14) | ||
324 | |||
325 | #define AS3722_GPIOn_SIGNAL(n) BIT(n) | ||
326 | #define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n) | ||
327 | #define AS3722_I2C_PULL_UP BIT(4) | ||
328 | #define AS3722_INT_PULL_UP BIT(5) | ||
329 | |||
330 | #define AS3722_RTC_REP_WAKEUP_EN BIT(0) | ||
331 | #define AS3722_RTC_ALARM_WAKEUP_EN BIT(1) | ||
332 | #define AS3722_RTC_ON BIT(2) | ||
333 | #define AS3722_RTC_IRQMODE BIT(3) | ||
334 | #define AS3722_RTC_CLK32K_OUT_EN BIT(5) | ||
335 | |||
336 | #define AS3722_WATCHDOG_TIMER_MAX 0x7F | ||
337 | #define AS3722_WATCHDOG_ON BIT(0) | ||
338 | #define AS3722_WATCHDOG_SW_SIG BIT(0) | ||
339 | |||
340 | #define AS3722_EXT_CONTROL_ENABLE1 0x1 | ||
341 | #define AS3722_EXT_CONTROL_ENABLE2 0x2 | ||
342 | #define AS3722_EXT_CONTROL_ENABLE3 0x3 | ||
343 | |||
344 | /* Interrupt IDs */ | ||
345 | enum as3722_irq { | ||
346 | AS3722_IRQ_LID, | ||
347 | AS3722_IRQ_ACOK, | ||
348 | AS3722_IRQ_ENABLE1, | ||
349 | AS3722_IRQ_OCCUR_ALARM_SD0, | ||
350 | AS3722_IRQ_ONKEY_LONG_PRESS, | ||
351 | AS3722_IRQ_ONKEY, | ||
352 | AS3722_IRQ_OVTMP, | ||
353 | AS3722_IRQ_LOWBAT, | ||
354 | AS3722_IRQ_SD0_LV, | ||
355 | AS3722_IRQ_SD1_LV, | ||
356 | AS3722_IRQ_SD2_LV, | ||
357 | AS3722_IRQ_PWM1_OV_PROT, | ||
358 | AS3722_IRQ_PWM2_OV_PROT, | ||
359 | AS3722_IRQ_ENABLE2, | ||
360 | AS3722_IRQ_SD6_LV, | ||
361 | AS3722_IRQ_RTC_REP, | ||
362 | AS3722_IRQ_RTC_ALARM, | ||
363 | AS3722_IRQ_GPIO1, | ||
364 | AS3722_IRQ_GPIO2, | ||
365 | AS3722_IRQ_GPIO3, | ||
366 | AS3722_IRQ_GPIO4, | ||
367 | AS3722_IRQ_GPIO5, | ||
368 | AS3722_IRQ_WATCHDOG, | ||
369 | AS3722_IRQ_ENABLE3, | ||
370 | AS3722_IRQ_TEMP_SD0_SHUTDOWN, | ||
371 | AS3722_IRQ_TEMP_SD1_SHUTDOWN, | ||
372 | AS3722_IRQ_TEMP_SD2_SHUTDOWN, | ||
373 | AS3722_IRQ_TEMP_SD0_ALARM, | ||
374 | AS3722_IRQ_TEMP_SD1_ALARM, | ||
375 | AS3722_IRQ_TEMP_SD6_ALARM, | ||
376 | AS3722_IRQ_OCCUR_ALARM_SD6, | ||
377 | AS3722_IRQ_ADC, | ||
378 | AS3722_IRQ_MAX, | ||
379 | }; | ||
380 | |||
381 | struct as3722 { | ||
382 | struct device *dev; | ||
383 | struct regmap *regmap; | ||
384 | int chip_irq; | ||
385 | unsigned long irq_flags; | ||
386 | bool en_intern_int_pullup; | ||
387 | bool en_intern_i2c_pullup; | ||
388 | struct regmap_irq_chip_data *irq_data; | ||
389 | }; | ||
390 | |||
391 | static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest) | ||
392 | { | ||
393 | return regmap_read(as3722->regmap, reg, dest); | ||
394 | } | ||
395 | |||
396 | static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value) | ||
397 | { | ||
398 | return regmap_write(as3722->regmap, reg, value); | ||
399 | } | ||
400 | |||
401 | static inline int as3722_block_read(struct as3722 *as3722, u32 reg, | ||
402 | int count, u8 *buf) | ||
403 | { | ||
404 | return regmap_bulk_read(as3722->regmap, reg, buf, count); | ||
405 | } | ||
406 | |||
407 | static inline int as3722_block_write(struct as3722 *as3722, u32 reg, | ||
408 | int count, u8 *data) | ||
409 | { | ||
410 | return regmap_bulk_write(as3722->regmap, reg, data, count); | ||
411 | } | ||
412 | |||
413 | static inline int as3722_update_bits(struct as3722 *as3722, u32 reg, | ||
414 | u32 mask, u8 val) | ||
415 | { | ||
416 | return regmap_update_bits(as3722->regmap, reg, mask, val); | ||
417 | } | ||
418 | |||
419 | static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq) | ||
420 | { | ||
421 | return regmap_irq_get_virq(as3722->irq_data, irq); | ||
422 | } | ||
423 | #endif /* __LINUX_MFD_AS3722_H__ */ | ||
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index 7314fc4e6d25..bdba8c61207b 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h | |||
@@ -104,7 +104,7 @@ static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev) | |||
104 | } | 104 | } |
105 | 105 | ||
106 | extern int mfd_add_devices(struct device *parent, int id, | 106 | extern int mfd_add_devices(struct device *parent, int id, |
107 | struct mfd_cell *cells, int n_devs, | 107 | const struct mfd_cell *cells, int n_devs, |
108 | struct resource *mem_base, | 108 | struct resource *mem_base, |
109 | int irq_base, struct irq_domain *irq_domain); | 109 | int irq_base, struct irq_domain *irq_domain); |
110 | 110 | ||
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h index 786d02eb79d2..21e21b81cc75 100644 --- a/include/linux/mfd/da9052/da9052.h +++ b/include/linux/mfd/da9052/da9052.h | |||
@@ -148,10 +148,15 @@ static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg, | |||
148 | unsigned reg_cnt, unsigned char *val) | 148 | unsigned reg_cnt, unsigned char *val) |
149 | { | 149 | { |
150 | int ret; | 150 | int ret; |
151 | unsigned int tmp; | ||
152 | int i; | ||
151 | 153 | ||
152 | ret = regmap_bulk_read(da9052->regmap, reg, val, reg_cnt); | 154 | for (i = 0; i < reg_cnt; i++) { |
153 | if (ret < 0) | 155 | ret = regmap_read(da9052->regmap, reg + i, &tmp); |
154 | return ret; | 156 | val[i] = (unsigned char)tmp; |
157 | if (ret < 0) | ||
158 | return ret; | ||
159 | } | ||
155 | 160 | ||
156 | if (da9052->fix_io) { | 161 | if (da9052->fix_io) { |
157 | ret = da9052->fix_io(da9052, reg); | 162 | ret = da9052->fix_io(da9052, reg); |
@@ -166,10 +171,13 @@ static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg, | |||
166 | unsigned reg_cnt, unsigned char *val) | 171 | unsigned reg_cnt, unsigned char *val) |
167 | { | 172 | { |
168 | int ret; | 173 | int ret; |
174 | int i; | ||
169 | 175 | ||
170 | ret = regmap_raw_write(da9052->regmap, reg, val, reg_cnt); | 176 | for (i = 0; i < reg_cnt; i++) { |
171 | if (ret < 0) | 177 | ret = regmap_write(da9052->regmap, reg + i, val[i]); |
172 | return ret; | 178 | if (ret < 0) |
179 | return ret; | ||
180 | } | ||
173 | 181 | ||
174 | if (da9052->fix_io) { | 182 | if (da9052->fix_io) { |
175 | ret = da9052->fix_io(da9052, reg); | 183 | ret = da9052->fix_io(da9052, reg); |
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h index 244fb0d51589..3e050b933dd0 100644 --- a/include/linux/mfd/max77693-private.h +++ b/include/linux/mfd/max77693-private.h | |||
@@ -323,7 +323,6 @@ struct max77693_dev { | |||
323 | 323 | ||
324 | int irq; | 324 | int irq; |
325 | int irq_gpio; | 325 | int irq_gpio; |
326 | bool wakeup; | ||
327 | struct mutex irqlock; | 326 | struct mutex irqlock; |
328 | int irq_masks_cur[MAX77693_IRQ_GROUP_NR]; | 327 | int irq_masks_cur[MAX77693_IRQ_GROUP_NR]; |
329 | int irq_masks_cache[MAX77693_IRQ_GROUP_NR]; | 328 | int irq_masks_cache[MAX77693_IRQ_GROUP_NR]; |
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h index 676f0f388992..3f3dc45f93ee 100644 --- a/include/linux/mfd/max77693.h +++ b/include/linux/mfd/max77693.h | |||
@@ -64,8 +64,6 @@ struct max77693_muic_platform_data { | |||
64 | }; | 64 | }; |
65 | 65 | ||
66 | struct max77693_platform_data { | 66 | struct max77693_platform_data { |
67 | int wakeup; | ||
68 | |||
69 | /* regulator data */ | 67 | /* regulator data */ |
70 | struct max77693_regulator_data *regulators; | 68 | struct max77693_regulator_data *regulators; |
71 | int num_regulators; | 69 | int num_regulators; |
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index d1382dfbeff0..0ce772105508 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h | |||
@@ -756,6 +756,59 @@ | |||
756 | #define PCR_SETTING_REG2 0x814 | 756 | #define PCR_SETTING_REG2 0x814 |
757 | #define PCR_SETTING_REG3 0x747 | 757 | #define PCR_SETTING_REG3 0x747 |
758 | 758 | ||
759 | /* Phy bits */ | ||
760 | #define PHY_PCR_FORCE_CODE 0xB000 | ||
761 | #define PHY_PCR_OOBS_CALI_50 0x0800 | ||
762 | #define PHY_PCR_OOBS_VCM_08 0x0200 | ||
763 | #define PHY_PCR_OOBS_SEN_90 0x0040 | ||
764 | #define PHY_PCR_RSSI_EN 0x0002 | ||
765 | |||
766 | #define PHY_RCR1_ADP_TIME 0x0100 | ||
767 | #define PHY_RCR1_VCO_COARSE 0x001F | ||
768 | |||
769 | #define PHY_RCR2_EMPHASE_EN 0x8000 | ||
770 | #define PHY_RCR2_NADJR 0x4000 | ||
771 | #define PHY_RCR2_CDR_CP_10 0x0400 | ||
772 | #define PHY_RCR2_CDR_SR_2 0x0100 | ||
773 | #define PHY_RCR2_FREQSEL_12 0x0040 | ||
774 | #define PHY_RCR2_CPADJEN 0x0020 | ||
775 | #define PHY_RCR2_CDR_SC_8 0x0008 | ||
776 | #define PHY_RCR2_CALIB_LATE 0x0002 | ||
777 | |||
778 | #define PHY_RDR_RXDSEL_1_9 0x4000 | ||
779 | |||
780 | #define PHY_TUNE_TUNEREF_1_0 0x4000 | ||
781 | #define PHY_TUNE_VBGSEL_1252 0x0C00 | ||
782 | #define PHY_TUNE_SDBUS_33 0x0200 | ||
783 | #define PHY_TUNE_TUNED18 0x01C0 | ||
784 | #define PHY_TUNE_TUNED12 0X0020 | ||
785 | |||
786 | #define PHY_BPCR_IBRXSEL 0x0400 | ||
787 | #define PHY_BPCR_IBTXSEL 0x0100 | ||
788 | #define PHY_BPCR_IB_FILTER 0x0080 | ||
789 | #define PHY_BPCR_CMIRROR_EN 0x0040 | ||
790 | |||
791 | #define PHY_REG_REV_RESV 0xE000 | ||
792 | #define PHY_REG_REV_RXIDLE_LATCHED 0x1000 | ||
793 | #define PHY_REG_REV_P1_EN 0x0800 | ||
794 | #define PHY_REG_REV_RXIDLE_EN 0x0400 | ||
795 | #define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 0x0040 | ||
796 | #define PHY_REG_REV_STOP_CLKRD 0x0020 | ||
797 | #define PHY_REG_REV_RX_PWST 0x0008 | ||
798 | #define PHY_REG_REV_STOP_CLKWR 0x0004 | ||
799 | |||
800 | #define PHY_FLD3_TIMER_4 0x7800 | ||
801 | #define PHY_FLD3_TIMER_6 0x00E0 | ||
802 | #define PHY_FLD3_RXDELINK 0x0004 | ||
803 | |||
804 | #define PHY_FLD4_FLDEN_SEL 0x4000 | ||
805 | #define PHY_FLD4_REQ_REF 0x2000 | ||
806 | #define PHY_FLD4_RXAMP_OFF 0x1000 | ||
807 | #define PHY_FLD4_REQ_ADDA 0x0800 | ||
808 | #define PHY_FLD4_BER_COUNT 0x00E0 | ||
809 | #define PHY_FLD4_BER_TIMER 0x000A | ||
810 | #define PHY_FLD4_BER_CHK_EN 0x0001 | ||
811 | |||
759 | #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) | 812 | #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) |
760 | 813 | ||
761 | struct rtsx_pcr; | 814 | struct rtsx_pcr; |
diff --git a/include/linux/mfd/stw481x.h b/include/linux/mfd/stw481x.h new file mode 100644 index 000000000000..eda121556e5d --- /dev/null +++ b/include/linux/mfd/stw481x.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 ST-Ericsson SA | ||
3 | * Written on behalf of Linaro for ST-Ericsson | ||
4 | * | ||
5 | * Author: Linus Walleij <linus.walleij@linaro.org> | ||
6 | * | ||
7 | * License terms: GNU General Public License (GPL) version 2 | ||
8 | */ | ||
9 | #ifndef MFD_STW481X_H | ||
10 | #define MFD_STW481X_H | ||
11 | |||
12 | #include <linux/i2c.h> | ||
13 | #include <linux/regulator/machine.h> | ||
14 | #include <linux/regmap.h> | ||
15 | #include <linux/bitops.h> | ||
16 | |||
17 | /* These registers are accessed from more than one driver */ | ||
18 | #define STW_CONF1 0x11U | ||
19 | #define STW_CONF1_PDN_VMMC 0x01U | ||
20 | #define STW_CONF1_VMMC_MASK 0x0eU | ||
21 | #define STW_CONF1_VMMC_1_8V 0x02U | ||
22 | #define STW_CONF1_VMMC_2_85V 0x04U | ||
23 | #define STW_CONF1_VMMC_3V 0x06U | ||
24 | #define STW_CONF1_VMMC_1_85V 0x08U | ||
25 | #define STW_CONF1_VMMC_2_6V 0x0aU | ||
26 | #define STW_CONF1_VMMC_2_7V 0x0cU | ||
27 | #define STW_CONF1_VMMC_3_3V 0x0eU | ||
28 | #define STW_CONF1_MMC_LS_STATUS 0x10U | ||
29 | #define STW_PCTL_REG_LO 0x1eU | ||
30 | #define STW_PCTL_REG_HI 0x1fU | ||
31 | #define STW_CONF1_V_MONITORING 0x20U | ||
32 | #define STW_CONF1_IT_WARN 0x40U | ||
33 | #define STW_CONF1_PDN_VAUX 0x80U | ||
34 | #define STW_CONF2 0x20U | ||
35 | #define STW_CONF2_MASK_TWARN 0x01U | ||
36 | #define STW_CONF2_VMMC_EXT 0x02U | ||
37 | #define STW_CONF2_MASK_IT_WAKE_UP 0x04U | ||
38 | #define STW_CONF2_GPO1 0x08U | ||
39 | #define STW_CONF2_GPO2 0x10U | ||
40 | #define STW_VCORE_SLEEP 0x21U | ||
41 | |||
42 | /** | ||
43 | * struct stw481x - state holder for the Stw481x drivers | ||
44 | * @mutex: mutex to serialize I2C accesses | ||
45 | * @i2c_client: corresponding I2C client | ||
46 | * @regulator: regulator device for regulator children | ||
47 | * @map: regmap handle to access device registers | ||
48 | */ | ||
49 | struct stw481x { | ||
50 | struct mutex lock; | ||
51 | struct i2c_client *client; | ||
52 | struct regulator_dev *vmmc_regulator; | ||
53 | struct regmap *map; | ||
54 | }; | ||
55 | |||
56 | #endif | ||
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h index b473577f36db..8789fa3c7fd9 100644 --- a/include/linux/mfd/syscon.h +++ b/include/linux/mfd/syscon.h | |||
@@ -17,10 +17,35 @@ | |||
17 | 17 | ||
18 | struct device_node; | 18 | struct device_node; |
19 | 19 | ||
20 | #ifdef CONFIG_MFD_SYSCON | ||
20 | extern struct regmap *syscon_node_to_regmap(struct device_node *np); | 21 | extern struct regmap *syscon_node_to_regmap(struct device_node *np); |
21 | extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s); | 22 | extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s); |
22 | extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s); | 23 | extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s); |
23 | extern struct regmap *syscon_regmap_lookup_by_phandle( | 24 | extern struct regmap *syscon_regmap_lookup_by_phandle( |
24 | struct device_node *np, | 25 | struct device_node *np, |
25 | const char *property); | 26 | const char *property); |
27 | #else | ||
28 | static inline struct regmap *syscon_node_to_regmap(struct device_node *np) | ||
29 | { | ||
30 | return ERR_PTR(-ENOSYS); | ||
31 | } | ||
32 | |||
33 | static inline struct regmap *syscon_regmap_lookup_by_compatible(const char *s) | ||
34 | { | ||
35 | return ERR_PTR(-ENOSYS); | ||
36 | } | ||
37 | |||
38 | static inline struct regmap *syscon_regmap_lookup_by_pdevname(const char *s) | ||
39 | { | ||
40 | return ERR_PTR(-ENOSYS); | ||
41 | } | ||
42 | |||
43 | static inline struct regmap *syscon_regmap_lookup_by_phandle( | ||
44 | struct device_node *np, | ||
45 | const char *property) | ||
46 | { | ||
47 | return ERR_PTR(-ENOSYS); | ||
48 | } | ||
49 | #endif | ||
50 | |||
26 | #endif /* __LINUX_MFD_SYSCON_H__ */ | 51 | #endif /* __LINUX_MFD_SYSCON_H__ */ |
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index 08cce7f96ab9..d498d98f0c2c 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h | |||
@@ -134,13 +134,18 @@ | |||
134 | #define FIFO1_THRESHOLD 19 | 134 | #define FIFO1_THRESHOLD 19 |
135 | 135 | ||
136 | /* | 136 | /* |
137 | * ADC runs at 3MHz, and it takes | 137 | * time in us for processing a single channel, calculated as follows: |
138 | * 15 cycles to latch one data output. | 138 | * |
139 | * Hence the idle time for ADC to | 139 | * num cycles = open delay + (sample delay + conv time) * averaging |
140 | * process one sample data would be | 140 | * |
141 | * around 5 micro seconds. | 141 | * num cycles: 152 + (1 + 13) * 16 = 376 |
142 | */ | 142 | * |
143 | #define IDLE_TIMEOUT 5 /* microsec */ | 143 | * clock frequency: 26MHz / 8 = 3.25MHz |
144 | * clock period: 1 / 3.25MHz = 308ns | ||
145 | * | ||
146 | * processing time: 376 * 308ns = 116us | ||
147 | */ | ||
148 | #define IDLE_TIMEOUT 116 /* microsec */ | ||
144 | 149 | ||
145 | #define TSCADC_CELLS 2 | 150 | #define TSCADC_CELLS 2 |
146 | 151 | ||
@@ -155,6 +160,7 @@ struct ti_tscadc_dev { | |||
155 | struct mfd_cell cells[TSCADC_CELLS]; | 160 | struct mfd_cell cells[TSCADC_CELLS]; |
156 | u32 reg_se_cache; | 161 | u32 reg_se_cache; |
157 | spinlock_t reg_lock; | 162 | spinlock_t reg_lock; |
163 | unsigned int clk_div; | ||
158 | 164 | ||
159 | /* tsc device */ | 165 | /* tsc device */ |
160 | struct titsc *tsc; | 166 | struct titsc *tsc; |
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h index 40854ac0ba3d..eefafa62d304 100644 --- a/include/linux/mfd/wm8994/core.h +++ b/include/linux/mfd/wm8994/core.h | |||
@@ -56,8 +56,6 @@ struct irq_domain; | |||
56 | #define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN) | 56 | #define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN) |
57 | 57 | ||
58 | struct wm8994 { | 58 | struct wm8994 { |
59 | struct mutex irq_lock; | ||
60 | |||
61 | struct wm8994_pdata pdata; | 59 | struct wm8994_pdata pdata; |
62 | 60 | ||
63 | enum wm8994_type type; | 61 | enum wm8994_type type; |
@@ -85,16 +83,43 @@ struct wm8994 { | |||
85 | }; | 83 | }; |
86 | 84 | ||
87 | /* Device I/O API */ | 85 | /* Device I/O API */ |
88 | int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg); | ||
89 | int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg, | ||
90 | unsigned short val); | ||
91 | int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg, | ||
92 | unsigned short mask, unsigned short val); | ||
93 | int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, | ||
94 | int count, u16 *buf); | ||
95 | int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg, | ||
96 | int count, const u16 *buf); | ||
97 | 86 | ||
87 | static inline int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg) | ||
88 | { | ||
89 | unsigned int val; | ||
90 | int ret; | ||
91 | |||
92 | ret = regmap_read(wm8994->regmap, reg, &val); | ||
93 | |||
94 | if (ret < 0) | ||
95 | return ret; | ||
96 | else | ||
97 | return val; | ||
98 | } | ||
99 | |||
100 | static inline int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg, | ||
101 | unsigned short val) | ||
102 | { | ||
103 | return regmap_write(wm8994->regmap, reg, val); | ||
104 | } | ||
105 | |||
106 | static inline int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, | ||
107 | int count, u16 *buf) | ||
108 | { | ||
109 | return regmap_bulk_read(wm8994->regmap, reg, buf, count); | ||
110 | } | ||
111 | |||
112 | static inline int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg, | ||
113 | int count, const u16 *buf) | ||
114 | { | ||
115 | return regmap_raw_write(wm8994->regmap, reg, buf, count * sizeof(u16)); | ||
116 | } | ||
117 | |||
118 | static inline int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg, | ||
119 | unsigned short mask, unsigned short val) | ||
120 | { | ||
121 | return regmap_update_bits(wm8994->regmap, reg, mask, val); | ||
122 | } | ||
98 | 123 | ||
99 | /* Helper to save on boilerplate */ | 124 | /* Helper to save on boilerplate */ |
100 | static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq, | 125 | static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq, |