aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2008-02-29 00:53:20 -0500
committerDavid S. Miller <davem@davemloft.net>2008-02-29 00:53:20 -0500
commit7729d74ed5099021f79ee8ecfa676829b5bac796 (patch)
tree969a2a5e2b0de1d812f8856e9f60fdf0c471a922 /include
parentc8edc89d24546c834d7f595663afd14602855c02 (diff)
[SPARC]: Add reboot_command[] extern decl to asm/system.h
Kill off some sparse warnings. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r--include/asm-sparc/system.h2
-rw-r--r--include/asm-sparc64/system.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
index 45e47c159a6e..4e08210cd4c2 100644
--- a/include/asm-sparc/system.h
+++ b/include/asm-sparc/system.h
@@ -44,6 +44,8 @@ extern enum sparc_cpu sparc_cpu_model;
44 44
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */ 45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46 46
47extern char reboot_command[];
48
47extern struct thread_info *current_set[NR_CPUS]; 49extern struct thread_info *current_set[NR_CPUS];
48 50
49extern unsigned long empty_bad_page; 51extern unsigned long empty_bad_page;
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index ed91a5d8d4f0..53eae091a171 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -30,6 +30,8 @@ enum sparc_cpu {
30#define ARCH_SUN4C_SUN4 0 30#define ARCH_SUN4C_SUN4 0
31#define ARCH_SUN4 0 31#define ARCH_SUN4 0
32 32
33extern char reboot_command[];
34
33/* These are here in an effort to more fully work around Spitfire Errata 35/* These are here in an effort to more fully work around Spitfire Errata
34 * #51. Essentially, if a memory barrier occurs soon after a mispredicted 36 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
35 * branch, the chip can stop executing instructions until a trap occurs. 37 * branch, the chip can stop executing instructions until a trap occurs.