diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2005-11-09 10:04:22 -0500 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-11-09 10:04:22 -0500 |
commit | 59d1ff3bfb56d9b8cf3ec864857e6a4dfd9d2dba (patch) | |
tree | e70623b924a8859182dc3326b6d5f7a5b9271504 /include | |
parent | be6eb9b79f99e652a0827a475c4daa02ecef221f (diff) |
[ARM] Clean up save_and_disable_irqs macro and allow use of ARMv6 CPSID
save_and_disable_irqs does not need to use mov + msr (which was
introduced to work around a documentation bug which was propagated
into binutils.) Use msr with an immediate constant, and if we're
building for ARMv6 or later, use the new CPSID instruction.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-arm/assembler.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index 69a28f96bee2..f31ac92b6c7f 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h | |||
@@ -83,10 +83,13 @@ | |||
83 | * Save the current IRQ state and disable IRQs. Note that this macro | 83 | * Save the current IRQ state and disable IRQs. Note that this macro |
84 | * assumes FIQs are enabled, and that the processor is in SVC mode. | 84 | * assumes FIQs are enabled, and that the processor is in SVC mode. |
85 | */ | 85 | */ |
86 | .macro save_and_disable_irqs, oldcpsr, temp | 86 | .macro save_and_disable_irqs, oldcpsr |
87 | mrs \oldcpsr, cpsr | 87 | mrs \oldcpsr, cpsr |
88 | mov \temp, #PSR_I_BIT | MODE_SVC | 88 | #if __LINUX_ARM_ARCH__ >= 6 |
89 | msr cpsr_c, \temp | 89 | cpsid i |
90 | #else | ||
91 | msr cpsr_c, #PSR_I_BIT | MODE_SVC | ||
92 | #endif | ||
90 | .endm | 93 | .endm |
91 | 94 | ||
92 | /* | 95 | /* |