diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2008-02-06 14:16:11 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2008-02-06 14:16:11 -0500 |
commit | 3d4d4582e5b3f67a68f2cf32fd5b70d8d80f119d (patch) | |
tree | 18d270847537d1a9d1a396d03e585654130630db /include | |
parent | 8f1bfa4c5c093e97154be4ec969bdf7190aeff6a (diff) | |
parent | 47437b2c9a64315efeb3d84e97ffefd6c3c67ef1 (diff) |
Merge branch 'async-tx-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop into fix
* 'async-tx-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop:
async_tx: allow architecture specific async_tx_find_channel implementations
async_tx: replace 'int_en' with operation preparation flags
async_tx: kill tx_set_src and tx_set_dest methods
async_tx: kill ASYNC_TX_ASSUME_COHERENT
iop-adma: use LIST_HEAD instead of LIST_HEAD_INIT
async_tx: use LIST_HEAD instead of LIST_HEAD_INIT
async_tx: fix compile breakage, mark do_async_xor __always_inline
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-arm/arch-iop13xx/adma.h | 18 | ||||
-rw-r--r-- | include/asm-arm/hardware/iop3xx-adma.h | 30 | ||||
-rw-r--r-- | include/linux/async_tx.h | 13 | ||||
-rw-r--r-- | include/linux/dmaengine.h | 29 |
4 files changed, 53 insertions, 37 deletions
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h index 04006c1c5fd7..efd9a5eb1008 100644 --- a/include/asm-arm/arch-iop13xx/adma.h +++ b/include/asm-arm/arch-iop13xx/adma.h | |||
@@ -247,7 +247,7 @@ static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, | |||
247 | } | 247 | } |
248 | 248 | ||
249 | static inline void | 249 | static inline void |
250 | iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) | 250 | iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) |
251 | { | 251 | { |
252 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | 252 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; |
253 | union { | 253 | union { |
@@ -257,13 +257,13 @@ iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) | |||
257 | 257 | ||
258 | u_desc_ctrl.value = 0; | 258 | u_desc_ctrl.value = 0; |
259 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | 259 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ |
260 | u_desc_ctrl.field.int_en = int_en; | 260 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
261 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 261 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
262 | hw_desc->crc_addr = 0; | 262 | hw_desc->crc_addr = 0; |
263 | } | 263 | } |
264 | 264 | ||
265 | static inline void | 265 | static inline void |
266 | iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) | 266 | iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) |
267 | { | 267 | { |
268 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | 268 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; |
269 | union { | 269 | union { |
@@ -274,14 +274,15 @@ iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) | |||
274 | u_desc_ctrl.value = 0; | 274 | u_desc_ctrl.value = 0; |
275 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | 275 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ |
276 | u_desc_ctrl.field.block_fill_en = 1; | 276 | u_desc_ctrl.field.block_fill_en = 1; |
277 | u_desc_ctrl.field.int_en = int_en; | 277 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
278 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 278 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
279 | hw_desc->crc_addr = 0; | 279 | hw_desc->crc_addr = 0; |
280 | } | 280 | } |
281 | 281 | ||
282 | /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ | 282 | /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ |
283 | static inline void | 283 | static inline void |
284 | iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | 284 | iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, |
285 | unsigned long flags) | ||
285 | { | 286 | { |
286 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | 287 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; |
287 | union { | 288 | union { |
@@ -292,7 +293,7 @@ iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | |||
292 | u_desc_ctrl.value = 0; | 293 | u_desc_ctrl.value = 0; |
293 | u_desc_ctrl.field.src_select = src_cnt - 1; | 294 | u_desc_ctrl.field.src_select = src_cnt - 1; |
294 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | 295 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ |
295 | u_desc_ctrl.field.int_en = int_en; | 296 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
296 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 297 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
297 | hw_desc->crc_addr = 0; | 298 | hw_desc->crc_addr = 0; |
298 | 299 | ||
@@ -301,7 +302,8 @@ iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | |||
301 | 302 | ||
302 | /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ | 303 | /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ |
303 | static inline int | 304 | static inline int |
304 | iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | 305 | iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, |
306 | unsigned long flags) | ||
305 | { | 307 | { |
306 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | 308 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; |
307 | union { | 309 | union { |
@@ -314,7 +316,7 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | |||
314 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | 316 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ |
315 | u_desc_ctrl.field.zero_result = 1; | 317 | u_desc_ctrl.field.zero_result = 1; |
316 | u_desc_ctrl.field.status_write_back_en = 1; | 318 | u_desc_ctrl.field.status_write_back_en = 1; |
317 | u_desc_ctrl.field.int_en = int_en; | 319 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
318 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 320 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
319 | hw_desc->crc_addr = 0; | 321 | hw_desc->crc_addr = 0; |
320 | 322 | ||
diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h index 10834b54f681..5c529e6a5e3b 100644 --- a/include/asm-arm/hardware/iop3xx-adma.h +++ b/include/asm-arm/hardware/iop3xx-adma.h | |||
@@ -414,7 +414,7 @@ static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, | |||
414 | } | 414 | } |
415 | 415 | ||
416 | static inline void | 416 | static inline void |
417 | iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) | 417 | iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) |
418 | { | 418 | { |
419 | struct iop3xx_desc_dma *hw_desc = desc->hw_desc; | 419 | struct iop3xx_desc_dma *hw_desc = desc->hw_desc; |
420 | union { | 420 | union { |
@@ -425,14 +425,14 @@ iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) | |||
425 | u_desc_ctrl.value = 0; | 425 | u_desc_ctrl.value = 0; |
426 | u_desc_ctrl.field.mem_to_mem_en = 1; | 426 | u_desc_ctrl.field.mem_to_mem_en = 1; |
427 | u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ | 427 | u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ |
428 | u_desc_ctrl.field.int_en = int_en; | 428 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
429 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 429 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
430 | hw_desc->upper_pci_src_addr = 0; | 430 | hw_desc->upper_pci_src_addr = 0; |
431 | hw_desc->crc_addr = 0; | 431 | hw_desc->crc_addr = 0; |
432 | } | 432 | } |
433 | 433 | ||
434 | static inline void | 434 | static inline void |
435 | iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) | 435 | iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) |
436 | { | 436 | { |
437 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; | 437 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; |
438 | union { | 438 | union { |
@@ -443,12 +443,13 @@ iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) | |||
443 | u_desc_ctrl.value = 0; | 443 | u_desc_ctrl.value = 0; |
444 | u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ | 444 | u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ |
445 | u_desc_ctrl.field.dest_write_en = 1; | 445 | u_desc_ctrl.field.dest_write_en = 1; |
446 | u_desc_ctrl.field.int_en = int_en; | 446 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
447 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 447 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
448 | } | 448 | } |
449 | 449 | ||
450 | static inline u32 | 450 | static inline u32 |
451 | iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en) | 451 | iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, |
452 | unsigned long flags) | ||
452 | { | 453 | { |
453 | int i, shift; | 454 | int i, shift; |
454 | u32 edcr; | 455 | u32 edcr; |
@@ -509,21 +510,23 @@ iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en) | |||
509 | 510 | ||
510 | u_desc_ctrl.field.dest_write_en = 1; | 511 | u_desc_ctrl.field.dest_write_en = 1; |
511 | u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ | 512 | u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ |
512 | u_desc_ctrl.field.int_en = int_en; | 513 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
513 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 514 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
514 | 515 | ||
515 | return u_desc_ctrl.value; | 516 | return u_desc_ctrl.value; |
516 | } | 517 | } |
517 | 518 | ||
518 | static inline void | 519 | static inline void |
519 | iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | 520 | iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, |
521 | unsigned long flags) | ||
520 | { | 522 | { |
521 | iop3xx_desc_init_xor(desc->hw_desc, src_cnt, int_en); | 523 | iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags); |
522 | } | 524 | } |
523 | 525 | ||
524 | /* return the number of operations */ | 526 | /* return the number of operations */ |
525 | static inline int | 527 | static inline int |
526 | iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | 528 | iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, |
529 | unsigned long flags) | ||
527 | { | 530 | { |
528 | int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; | 531 | int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; |
529 | struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; | 532 | struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; |
@@ -538,10 +541,10 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | |||
538 | for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; | 541 | for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; |
539 | i += slots_per_op, j++) { | 542 | i += slots_per_op, j++) { |
540 | iter = iop_hw_desc_slot_idx(hw_desc, i); | 543 | iter = iop_hw_desc_slot_idx(hw_desc, i); |
541 | u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, int_en); | 544 | u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags); |
542 | u_desc_ctrl.field.dest_write_en = 0; | 545 | u_desc_ctrl.field.dest_write_en = 0; |
543 | u_desc_ctrl.field.zero_result_en = 1; | 546 | u_desc_ctrl.field.zero_result_en = 1; |
544 | u_desc_ctrl.field.int_en = int_en; | 547 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
545 | iter->desc_ctrl = u_desc_ctrl.value; | 548 | iter->desc_ctrl = u_desc_ctrl.value; |
546 | 549 | ||
547 | /* for the subsequent descriptors preserve the store queue | 550 | /* for the subsequent descriptors preserve the store queue |
@@ -559,7 +562,8 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | |||
559 | } | 562 | } |
560 | 563 | ||
561 | static inline void | 564 | static inline void |
562 | iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | 565 | iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, |
566 | unsigned long flags) | ||
563 | { | 567 | { |
564 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; | 568 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; |
565 | union { | 569 | union { |
@@ -591,7 +595,7 @@ iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) | |||
591 | } | 595 | } |
592 | 596 | ||
593 | u_desc_ctrl.field.dest_write_en = 0; | 597 | u_desc_ctrl.field.dest_write_en = 0; |
594 | u_desc_ctrl.field.int_en = int_en; | 598 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; |
595 | hw_desc->desc_ctrl = u_desc_ctrl.value; | 599 | hw_desc->desc_ctrl = u_desc_ctrl.value; |
596 | } | 600 | } |
597 | 601 | ||
diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index bdca3f1b3213..eb640f0acfac 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h | |||
@@ -47,7 +47,6 @@ struct dma_chan_ref { | |||
47 | * address is an implied source, whereas the asynchronous case it must be listed | 47 | * address is an implied source, whereas the asynchronous case it must be listed |
48 | * as a source. The destination address must be the first address in the source | 48 | * as a source. The destination address must be the first address in the source |
49 | * array. | 49 | * array. |
50 | * @ASYNC_TX_ASSUME_COHERENT: skip cache maintenance operations | ||
51 | * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a | 50 | * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a |
52 | * dependency chain | 51 | * dependency chain |
53 | * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. | 52 | * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. |
@@ -55,7 +54,6 @@ struct dma_chan_ref { | |||
55 | enum async_tx_flags { | 54 | enum async_tx_flags { |
56 | ASYNC_TX_XOR_ZERO_DST = (1 << 0), | 55 | ASYNC_TX_XOR_ZERO_DST = (1 << 0), |
57 | ASYNC_TX_XOR_DROP_DST = (1 << 1), | 56 | ASYNC_TX_XOR_DROP_DST = (1 << 1), |
58 | ASYNC_TX_ASSUME_COHERENT = (1 << 2), | ||
59 | ASYNC_TX_ACK = (1 << 3), | 57 | ASYNC_TX_ACK = (1 << 3), |
60 | ASYNC_TX_DEP_ACK = (1 << 4), | 58 | ASYNC_TX_DEP_ACK = (1 << 4), |
61 | }; | 59 | }; |
@@ -64,9 +62,15 @@ enum async_tx_flags { | |||
64 | void async_tx_issue_pending_all(void); | 62 | void async_tx_issue_pending_all(void); |
65 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | 63 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
66 | void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx); | 64 | void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx); |
65 | #ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL | ||
66 | #include <asm/async_tx.h> | ||
67 | #else | ||
68 | #define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ | ||
69 | __async_tx_find_channel(dep, type) | ||
67 | struct dma_chan * | 70 | struct dma_chan * |
68 | async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, | 71 | __async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, |
69 | enum dma_transaction_type tx_type); | 72 | enum dma_transaction_type tx_type); |
73 | #endif /* CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL */ | ||
70 | #else | 74 | #else |
71 | static inline void async_tx_issue_pending_all(void) | 75 | static inline void async_tx_issue_pending_all(void) |
72 | { | 76 | { |
@@ -88,7 +92,8 @@ async_tx_run_dependencies(struct dma_async_tx_descriptor *tx, | |||
88 | 92 | ||
89 | static inline struct dma_chan * | 93 | static inline struct dma_chan * |
90 | async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, | 94 | async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, |
91 | enum dma_transaction_type tx_type) | 95 | enum dma_transaction_type tx_type, struct page **dst, int dst_count, |
96 | struct page **src, int src_count, size_t len) | ||
92 | { | 97 | { |
93 | return NULL; | 98 | return NULL; |
94 | } | 99 | } |
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 5c84bf897593..acbb364674ff 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
@@ -95,6 +95,15 @@ enum dma_transaction_type { | |||
95 | #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1) | 95 | #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1) |
96 | 96 | ||
97 | /** | 97 | /** |
98 | * enum dma_prep_flags - DMA flags to augment operation preparation | ||
99 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of | ||
100 | * this transaction | ||
101 | */ | ||
102 | enum dma_prep_flags { | ||
103 | DMA_PREP_INTERRUPT = (1 << 0), | ||
104 | }; | ||
105 | |||
106 | /** | ||
98 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | 107 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. |
99 | * See linux/cpumask.h | 108 | * See linux/cpumask.h |
100 | */ | 109 | */ |
@@ -209,8 +218,6 @@ typedef void (*dma_async_tx_callback)(void *dma_async_param); | |||
209 | * descriptors | 218 | * descriptors |
210 | * @chan: target channel for this operation | 219 | * @chan: target channel for this operation |
211 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | 220 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine |
212 | * @tx_set_dest: set a destination address in a hardware descriptor | ||
213 | * @tx_set_src: set a source address in a hardware descriptor | ||
214 | * @callback: routine to call after this operation is complete | 221 | * @callback: routine to call after this operation is complete |
215 | * @callback_param: general parameter to pass to the callback routine | 222 | * @callback_param: general parameter to pass to the callback routine |
216 | * ---async_tx api specific fields--- | 223 | * ---async_tx api specific fields--- |
@@ -227,10 +234,6 @@ struct dma_async_tx_descriptor { | |||
227 | struct list_head tx_list; | 234 | struct list_head tx_list; |
228 | struct dma_chan *chan; | 235 | struct dma_chan *chan; |
229 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | 236 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); |
230 | void (*tx_set_dest)(dma_addr_t addr, | ||
231 | struct dma_async_tx_descriptor *tx, int index); | ||
232 | void (*tx_set_src)(dma_addr_t addr, | ||
233 | struct dma_async_tx_descriptor *tx, int index); | ||
234 | dma_async_tx_callback callback; | 237 | dma_async_tx_callback callback; |
235 | void *callback_param; | 238 | void *callback_param; |
236 | struct list_head depend_list; | 239 | struct list_head depend_list; |
@@ -279,15 +282,17 @@ struct dma_device { | |||
279 | void (*device_free_chan_resources)(struct dma_chan *chan); | 282 | void (*device_free_chan_resources)(struct dma_chan *chan); |
280 | 283 | ||
281 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | 284 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( |
282 | struct dma_chan *chan, size_t len, int int_en); | 285 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
286 | size_t len, unsigned long flags); | ||
283 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( | 287 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
284 | struct dma_chan *chan, unsigned int src_cnt, size_t len, | 288 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
285 | int int_en); | 289 | unsigned int src_cnt, size_t len, unsigned long flags); |
286 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( | 290 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( |
287 | struct dma_chan *chan, unsigned int src_cnt, size_t len, | 291 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
288 | u32 *result, int int_en); | 292 | size_t len, u32 *result, unsigned long flags); |
289 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( | 293 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
290 | struct dma_chan *chan, int value, size_t len, int int_en); | 294 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
295 | unsigned long flags); | ||
291 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( | 296 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
292 | struct dma_chan *chan); | 297 | struct dma_chan *chan); |
293 | 298 | ||