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authorLinus Torvalds <torvalds@g5.osdl.org>2005-11-10 13:17:11 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-10 13:17:11 -0500
commita46699c9a32505cb5bbfd16f76e7d4a2c84a7705 (patch)
tree5c0bc91dd1c07ab95769f5749b3b58235c758d50 /include
parent7ed0175a462c4c30f6df6fac1cccac058f997739 (diff)
parentb216c01829d0b73a468204e2e763c0a818b77a46 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-ixp4xx/hardware.h1
-rw-r--r--include/asm-arm/arch-ixp4xx/irqs.h7
-rw-r--r--include/asm-arm/arch-ixp4xx/nslu2.h96
-rw-r--r--include/asm-arm/arch-omap/board-h4.h6
-rw-r--r--include/asm-arm/arch-omap/board-innovator.h4
-rw-r--r--include/asm-arm/arch-omap/clock.h91
-rw-r--r--include/asm-arm/arch-omap/common.h2
-rw-r--r--include/asm-arm/arch-omap/cpu.h82
-rw-r--r--include/asm-arm/arch-omap/dma.h261
-rw-r--r--include/asm-arm/arch-omap/entry-macro.S14
-rw-r--r--include/asm-arm/arch-omap/fpga.h4
-rw-r--r--include/asm-arm/arch-omap/gpio.h2
-rw-r--r--include/asm-arm/arch-omap/hardware.h8
-rw-r--r--include/asm-arm/arch-omap/io.h32
-rw-r--r--include/asm-arm/arch-omap/irqs.h13
-rw-r--r--include/asm-arm/arch-omap/memory.h4
-rw-r--r--include/asm-arm/arch-omap/menelaus.h22
-rw-r--r--include/asm-arm/arch-omap/mux.h327
-rw-r--r--include/asm-arm/arch-omap/omap1510.h6
-rw-r--r--include/asm-arm/arch-omap/omap24xx.h17
-rw-r--r--include/asm-arm/arch-omap/omapfb.h281
-rw-r--r--include/asm-arm/arch-omap/pm.h40
-rw-r--r--include/asm-arm/arch-omap/prcm.h429
-rw-r--r--include/asm-arm/arch-omap/sram.h38
-rw-r--r--include/asm-arm/arch-omap/system.h35
-rw-r--r--include/asm-arm/arch-omap/timex.h8
-rw-r--r--include/asm-arm/arch-omap/uncompress.h6
-rw-r--r--include/asm-arm/arch-pxa/sharpsl.h8
-rw-r--r--include/asm-arm/arch-pxa/ssp.h8
29 files changed, 1490 insertions, 362 deletions
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 55d85eea8c1a..cfb413c845f7 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -44,5 +44,6 @@ extern unsigned int processor_id;
44#include "ixdp425.h" 44#include "ixdp425.h"
45#include "coyote.h" 45#include "coyote.h"
46#include "prpmc1100.h" 46#include "prpmc1100.h"
47#include "nslu2.h"
47 48
48#endif /* _ASM_ARCH_HARDWARE_H */ 49#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index ca808281c7f9..2cf4930372bc 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -93,4 +93,11 @@
93#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 93#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
94#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 94#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
95 95
96/*
97 * NSLU2 board IRQs
98 */
99#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11
100#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
101#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
102
96#endif 103#endif
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
new file mode 100644
index 000000000000..b8b347a559c7
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -0,0 +1,96 @@
1/*
2 * include/asm-arm/arch-ixp4xx/nslu2.h
3 *
4 * NSLU2 platform specific definitions
5 *
6 * Author: Mark Rakes <mrakes AT mac.com>
7 * Maintainers: http://www.nslu2-linux.org
8 *
9 * based on ixdp425.h:
10 * Copyright 2004 (c) MontaVista, Software, Inc.
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H__
18#error "Do not include this directly, instead #include <asm/hardware.h>"
19#endif
20
21#define NSLU2_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
22#define NSLU2_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
23
24#define NSLU2_SDA_PIN 7
25#define NSLU2_SCL_PIN 6
26
27/*
28 * NSLU2 PCI IRQs
29 */
30#define NSLU2_PCI_MAX_DEV 3
31#define NSLU2_PCI_IRQ_LINES 3
32
33
34/* PCI controller GPIO to IRQ pin mappings */
35#define NSLU2_PCI_INTA_PIN 11
36#define NSLU2_PCI_INTB_PIN 10
37#define NSLU2_PCI_INTC_PIN 9
38#define NSLU2_PCI_INTD_PIN 8
39
40
41/* NSLU2 Timer */
42#define NSLU2_FREQ 66000000
43#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
44#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
45
46/* GPIO */
47
48#define NSLU2_GPIO0 0
49#define NSLU2_GPIO1 1
50#define NSLU2_GPIO2 2
51#define NSLU2_GPIO3 3
52#define NSLU2_GPIO4 4
53#define NSLU2_GPIO5 5
54#define NSLU2_GPIO6 6
55#define NSLU2_GPIO7 7
56#define NSLU2_GPIO8 8
57#define NSLU2_GPIO9 9
58#define NSLU2_GPIO10 10
59#define NSLU2_GPIO11 11
60#define NSLU2_GPIO12 12
61#define NSLU2_GPIO13 13
62#define NSLU2_GPIO14 14
63#define NSLU2_GPIO15 15
64
65/* Buttons */
66
67#define NSLU2_PB_GPIO NSLU2_GPIO5
68#define NSLU2_PO_GPIO NSLU2_GPIO8 /* power off */
69#define NSLU2_RB_GPIO NSLU2_GPIO12
70
71#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5
72#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12
73
74#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO)
75#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO)
76#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO)
77
78/* Buzzer */
79
80#define NSLU2_GPIO_BUZZ 4
81#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
82/* LEDs */
83
84#define NSLU2_LED_RED NSLU2_GPIO0
85#define NSLU2_LED_GRN NSLU2_GPIO1
86
87#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED)
88#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN)
89
90#define NSLU2_LED_DISK1 NSLU2_GPIO2
91#define NSLU2_LED_DISK2 NSLU2_GPIO3
92
93#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2)
94#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3)
95
96
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
index d64ee9211eed..33ea29a41654 100644
--- a/include/asm-arm/arch-omap/board-h4.h
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -34,5 +34,11 @@
34#define OMAP24XX_ETHR_START 0x08000300 34#define OMAP24XX_ETHR_START 0x08000300
35#define OMAP24XX_ETHR_GPIO_IRQ 92 35#define OMAP24XX_ETHR_GPIO_IRQ 92
36 36
37#define H4_CS0_BASE 0x04000000
38
39#define H4_CS0_BASE 0x04000000
40
41#define H4_CS0_BASE 0x04000000
42
37#endif /* __ASM_ARCH_OMAP_H4_H */ 43#endif /* __ASM_ARCH_OMAP_H4_H */
38 44
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 79574e0ed13d..b3cf33441f6e 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -26,7 +26,7 @@
26#ifndef __ASM_ARCH_OMAP_INNOVATOR_H 26#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
27#define __ASM_ARCH_OMAP_INNOVATOR_H 27#define __ASM_ARCH_OMAP_INNOVATOR_H
28 28
29#if defined (CONFIG_ARCH_OMAP1510) 29#if defined (CONFIG_ARCH_OMAP15XX)
30 30
31#ifndef OMAP_SDRAM_DEVICE 31#ifndef OMAP_SDRAM_DEVICE
32#define OMAP_SDRAM_DEVICE D256M_1X16_4B 32#define OMAP_SDRAM_DEVICE D256M_1X16_4B
@@ -44,7 +44,7 @@ void fpga_write(unsigned char val, int reg);
44unsigned char fpga_read(int reg); 44unsigned char fpga_read(int reg);
45#endif 45#endif
46 46
47#endif /* CONFIG_ARCH_OMAP1510 */ 47#endif /* CONFIG_ARCH_OMAP15XX */
48 48
49#if defined (CONFIG_ARCH_OMAP16XX) 49#if defined (CONFIG_ARCH_OMAP16XX)
50 50
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
new file mode 100644
index 000000000000..740c297eb11c
--- /dev/null
+++ b/include/asm-arm/arch-omap/clock.h
@@ -0,0 +1,91 @@
1/*
2 * linux/include/asm-arm/arch-omap/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H
15
16struct module;
17
18struct clk {
19 struct list_head node;
20 struct module *owner;
21 const char *name;
22 struct clk *parent;
23 unsigned long rate;
24 __u32 flags;
25 void __iomem *enable_reg;
26 __u8 enable_bit;
27 __u8 rate_offset;
28 __u8 src_offset;
29 __s8 usecount;
30 void (*recalc)(struct clk *);
31 int (*set_rate)(struct clk *, unsigned long);
32 long (*round_rate)(struct clk *, unsigned long);
33 void (*init)(struct clk *);
34 int (*enable)(struct clk *);
35 void (*disable)(struct clk *);
36};
37
38struct clk_functions {
39 int (*clk_enable)(struct clk *clk);
40 void (*clk_disable)(struct clk *clk);
41 int (*clk_use)(struct clk *clk);
42 void (*clk_unuse)(struct clk *clk);
43 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
44 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
45 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
46 struct clk * (*clk_get_parent)(struct clk *clk);
47 void (*clk_allow_idle)(struct clk *clk);
48 void (*clk_deny_idle)(struct clk *clk);
49};
50
51extern unsigned int mpurate;
52extern struct list_head clocks;
53extern spinlock_t clockfw_lock;
54
55extern int clk_init(struct clk_functions * custom_clocks);
56extern int clk_register(struct clk *clk);
57extern void clk_unregister(struct clk *clk);
58extern void propagate_rate(struct clk *clk);
59extern void followparent_recalc(struct clk * clk);
60extern void clk_allow_idle(struct clk *clk);
61extern void clk_deny_idle(struct clk *clk);
62
63/* Clock flags */
64#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
65#define RATE_FIXED (1 << 1) /* Fixed clock rate */
66#define RATE_PROPAGATES (1 << 2) /* Program children too */
67#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
68#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
69#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
70#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
71#define CLOCK_IDLE_CONTROL (1 << 7)
72#define CLOCK_NO_IDLE_PARENT (1 << 8)
73#define DELAYED_APP (1 << 9) /* Delay application of clock */
74#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
75#define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */
76#define CM_DSP_SEL1 (1 << 12)
77#define CM_GFX_SEL1 (1 << 13)
78#define CM_MODEM_SEL1 (1 << 14)
79#define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */
80#define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */
81#define CM_WKUP_SEL1 (1 << 17)
82#define CM_PLL_SEL1 (1 << 18)
83#define CM_PLL_SEL2 (1 << 19)
84#define CM_SYSCLKOUT_SEL1 (1 << 20)
85#define CLOCK_IN_OMAP730 (1 << 21)
86#define CLOCK_IN_OMAP1510 (1 << 22)
87#define CLOCK_IN_OMAP16XX (1 << 23)
88#define CLOCK_IN_OMAP242X (1 << 24)
89#define CLOCK_IN_OMAP243X (1 << 25)
90
91#endif
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 2a676b4f13b5..08d58abd8218 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -31,6 +31,6 @@ struct sys_timer;
31 31
32extern void omap_map_common_io(void); 32extern void omap_map_common_io(void);
33extern struct sys_timer omap_timer; 33extern struct sys_timer omap_timer;
34extern void omap_serial_init(int ports[]); 34extern void omap_serial_init(void);
35 35
36#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 36#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index 1119e2b53e72..ec7eb675d922 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -28,12 +28,7 @@
28 28
29extern unsigned int system_rev; 29extern unsigned int system_rev;
30 30
31#define OMAP_DIE_ID_0 0xfffe1800 31#define omap2_cpu_rev() ((system_rev >> 8) & 0x0f)
32#define OMAP_DIE_ID_1 0xfffe1804
33#define OMAP_PRODUCTION_ID_0 0xfffe2000
34#define OMAP_PRODUCTION_ID_1 0xfffe2004
35#define OMAP32_ID_0 0xfffed400
36#define OMAP32_ID_1 0xfffed404
37 32
38/* 33/*
39 * Test if multicore OMAP support is needed 34 * Test if multicore OMAP support is needed
@@ -50,7 +45,7 @@ extern unsigned int system_rev;
50# define OMAP_NAME omap730 45# define OMAP_NAME omap730
51# endif 46# endif
52#endif 47#endif
53#ifdef CONFIG_ARCH_OMAP1510 48#ifdef CONFIG_ARCH_OMAP15XX
54# ifdef OMAP_NAME 49# ifdef OMAP_NAME
55# undef MULTI_OMAP1 50# undef MULTI_OMAP1
56# define MULTI_OMAP1 51# define MULTI_OMAP1
@@ -79,9 +74,11 @@ extern unsigned int system_rev;
79 * Macros to group OMAP into cpu classes. 74 * Macros to group OMAP into cpu classes.
80 * These can be used in most places. 75 * These can be used in most places.
81 * cpu_is_omap7xx(): True for OMAP730 76 * cpu_is_omap7xx(): True for OMAP730
82 * cpu_is_omap15xx(): True for OMAP1510 and OMAP5910 77 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
83 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 78 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
84 * cpu_is_omap24xx(): True for OMAP2420 79 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
80 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
81 * cpu_is_omap243x(): True for OMAP2430
85 */ 82 */
86#define GET_OMAP_CLASS (system_rev & 0xff) 83#define GET_OMAP_CLASS (system_rev & 0xff)
87 84
@@ -91,22 +88,35 @@ static inline int is_omap ##class (void) \
91 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ 88 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
92} 89}
93 90
91#define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff)
92
93#define IS_OMAP_SUBCLASS(subclass, id) \
94static inline int is_omap ##subclass (void) \
95{ \
96 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
97}
98
94IS_OMAP_CLASS(7xx, 0x07) 99IS_OMAP_CLASS(7xx, 0x07)
95IS_OMAP_CLASS(15xx, 0x15) 100IS_OMAP_CLASS(15xx, 0x15)
96IS_OMAP_CLASS(16xx, 0x16) 101IS_OMAP_CLASS(16xx, 0x16)
97IS_OMAP_CLASS(24xx, 0x24) 102IS_OMAP_CLASS(24xx, 0x24)
98 103
104IS_OMAP_SUBCLASS(242x, 0x242)
105IS_OMAP_SUBCLASS(243x, 0x243)
106
99#define cpu_is_omap7xx() 0 107#define cpu_is_omap7xx() 0
100#define cpu_is_omap15xx() 0 108#define cpu_is_omap15xx() 0
101#define cpu_is_omap16xx() 0 109#define cpu_is_omap16xx() 0
102#define cpu_is_omap24xx() 0 110#define cpu_is_omap24xx() 0
111#define cpu_is_omap242x() 0
112#define cpu_is_omap243x() 0
103 113
104#if defined(MULTI_OMAP1) 114#if defined(MULTI_OMAP1)
105# if defined(CONFIG_ARCH_OMAP730) 115# if defined(CONFIG_ARCH_OMAP730)
106# undef cpu_is_omap7xx 116# undef cpu_is_omap7xx
107# define cpu_is_omap7xx() is_omap7xx() 117# define cpu_is_omap7xx() is_omap7xx()
108# endif 118# endif
109# if defined(CONFIG_ARCH_OMAP1510) 119# if defined(CONFIG_ARCH_OMAP15XX)
110# undef cpu_is_omap15xx 120# undef cpu_is_omap15xx
111# define cpu_is_omap15xx() is_omap15xx() 121# define cpu_is_omap15xx() is_omap15xx()
112# endif 122# endif
@@ -119,7 +129,7 @@ IS_OMAP_CLASS(24xx, 0x24)
119# undef cpu_is_omap7xx 129# undef cpu_is_omap7xx
120# define cpu_is_omap7xx() 1 130# define cpu_is_omap7xx() 1
121# endif 131# endif
122# if defined(CONFIG_ARCH_OMAP1510) 132# if defined(CONFIG_ARCH_OMAP15XX)
123# undef cpu_is_omap15xx 133# undef cpu_is_omap15xx
124# define cpu_is_omap15xx() 1 134# define cpu_is_omap15xx() 1
125# endif 135# endif
@@ -129,13 +139,18 @@ IS_OMAP_CLASS(24xx, 0x24)
129# endif 139# endif
130# if defined(CONFIG_ARCH_OMAP24XX) 140# if defined(CONFIG_ARCH_OMAP24XX)
131# undef cpu_is_omap24xx 141# undef cpu_is_omap24xx
142# undef cpu_is_omap242x
143# undef cpu_is_omap243x
132# define cpu_is_omap24xx() 1 144# define cpu_is_omap24xx() 1
145# define cpu_is_omap242x() is_omap242x()
146# define cpu_is_omap243x() is_omap243x()
133# endif 147# endif
134#endif 148#endif
135 149
136/* 150/*
137 * Macros to detect individual cpu types. 151 * Macros to detect individual cpu types.
138 * These are only rarely needed. 152 * These are only rarely needed.
153 * cpu_is_omap330(): True for OMAP330
139 * cpu_is_omap730(): True for OMAP730 154 * cpu_is_omap730(): True for OMAP730
140 * cpu_is_omap1510(): True for OMAP1510 155 * cpu_is_omap1510(): True for OMAP1510
141 * cpu_is_omap1610(): True for OMAP1610 156 * cpu_is_omap1610(): True for OMAP1610
@@ -144,6 +159,9 @@ IS_OMAP_CLASS(24xx, 0x24)
144 * cpu_is_omap1621(): True for OMAP1621 159 * cpu_is_omap1621(): True for OMAP1621
145 * cpu_is_omap1710(): True for OMAP1710 160 * cpu_is_omap1710(): True for OMAP1710
146 * cpu_is_omap2420(): True for OMAP2420 161 * cpu_is_omap2420(): True for OMAP2420
162 * cpu_is_omap2422(): True for OMAP2422
163 * cpu_is_omap2423(): True for OMAP2423
164 * cpu_is_omap2430(): True for OMAP2430
147 */ 165 */
148#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) 166#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff)
149 167
@@ -153,6 +171,7 @@ static inline int is_omap ##type (void) \
153 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ 171 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
154} 172}
155 173
174IS_OMAP_TYPE(310, 0x0310)
156IS_OMAP_TYPE(730, 0x0730) 175IS_OMAP_TYPE(730, 0x0730)
157IS_OMAP_TYPE(1510, 0x1510) 176IS_OMAP_TYPE(1510, 0x1510)
158IS_OMAP_TYPE(1610, 0x1610) 177IS_OMAP_TYPE(1610, 0x1610)
@@ -161,7 +180,11 @@ IS_OMAP_TYPE(5912, 0x1611)
161IS_OMAP_TYPE(1621, 0x1621) 180IS_OMAP_TYPE(1621, 0x1621)
162IS_OMAP_TYPE(1710, 0x1710) 181IS_OMAP_TYPE(1710, 0x1710)
163IS_OMAP_TYPE(2420, 0x2420) 182IS_OMAP_TYPE(2420, 0x2420)
183IS_OMAP_TYPE(2422, 0x2422)
184IS_OMAP_TYPE(2423, 0x2423)
185IS_OMAP_TYPE(2430, 0x2430)
164 186
187#define cpu_is_omap310() 0
165#define cpu_is_omap730() 0 188#define cpu_is_omap730() 0
166#define cpu_is_omap1510() 0 189#define cpu_is_omap1510() 0
167#define cpu_is_omap1610() 0 190#define cpu_is_omap1610() 0
@@ -170,31 +193,33 @@ IS_OMAP_TYPE(2420, 0x2420)
170#define cpu_is_omap1621() 0 193#define cpu_is_omap1621() 0
171#define cpu_is_omap1710() 0 194#define cpu_is_omap1710() 0
172#define cpu_is_omap2420() 0 195#define cpu_is_omap2420() 0
196#define cpu_is_omap2422() 0
197#define cpu_is_omap2423() 0
198#define cpu_is_omap2430() 0
173 199
174#if defined(MULTI_OMAP1) 200#if defined(MULTI_OMAP1)
175# if defined(CONFIG_ARCH_OMAP730) 201# if defined(CONFIG_ARCH_OMAP730)
176# undef cpu_is_omap730 202# undef cpu_is_omap730
177# define cpu_is_omap730() is_omap730() 203# define cpu_is_omap730() is_omap730()
178# endif 204# endif
179# if defined(CONFIG_ARCH_OMAP1510)
180# undef cpu_is_omap1510
181# define cpu_is_omap1510() is_omap1510()
182# endif
183#else 205#else
184# if defined(CONFIG_ARCH_OMAP730) 206# if defined(CONFIG_ARCH_OMAP730)
185# undef cpu_is_omap730 207# undef cpu_is_omap730
186# define cpu_is_omap730() 1 208# define cpu_is_omap730() 1
187# endif 209# endif
188# if defined(CONFIG_ARCH_OMAP1510)
189# undef cpu_is_omap1510
190# define cpu_is_omap1510() 1
191# endif
192#endif 210#endif
193 211
194/* 212/*
195 * Whether we have MULTI_OMAP1 or not, we still need to distinguish 213 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
196 * between 1611B/5912 and 1710. 214 * between 330 vs. 1510 and 1611B/5912 vs. 1710.
197 */ 215 */
216#if defined(CONFIG_ARCH_OMAP15XX)
217# undef cpu_is_omap310
218# undef cpu_is_omap1510
219# define cpu_is_omap310() is_omap310()
220# define cpu_is_omap1510() is_omap1510()
221#endif
222
198#if defined(CONFIG_ARCH_OMAP16XX) 223#if defined(CONFIG_ARCH_OMAP16XX)
199# undef cpu_is_omap1610 224# undef cpu_is_omap1610
200# undef cpu_is_omap1611 225# undef cpu_is_omap1611
@@ -208,9 +233,20 @@ IS_OMAP_TYPE(2420, 0x2420)
208# define cpu_is_omap1710() is_omap1710() 233# define cpu_is_omap1710() is_omap1710()
209#endif 234#endif
210 235
211#if defined(CONFIG_ARCH_OMAP2420) 236#if defined(CONFIG_ARCH_OMAP24XX)
212# undef cpu_is_omap2420 237# undef cpu_is_omap2420
213# define cpu_is_omap2420() 1 238# undef cpu_is_omap2422
239# undef cpu_is_omap2423
240# undef cpu_is_omap2430
241# define cpu_is_omap2420() is_omap2420()
242# define cpu_is_omap2422() is_omap2422()
243# define cpu_is_omap2423() is_omap2423()
244# define cpu_is_omap2430() is_omap2430()
214#endif 245#endif
215 246
247/* Macros to detect if we have OMAP1 or OMAP2 */
248#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \
249 cpu_is_omap16xx())
250#define cpu_class_is_omap2() cpu_is_omap24xx()
251
216#endif 252#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 04ebef5c6e95..ccbcb580a5c1 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,9 +22,109 @@
22#define __ASM_ARCH_DMA_H 22#define __ASM_ARCH_DMA_H
23 23
24#define MAX_DMA_ADDRESS 0xffffffff 24#define MAX_DMA_ADDRESS 0xffffffff
25#define MAX_DMA_CHANNELS 0
26
27/* Hardware registers for omap1 */
28#define OMAP_DMA_BASE (0xfffed800)
29#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
30#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
31#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
32#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
33#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
34#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
35#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
36#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
37#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
38#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
39#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
40#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
41#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
42#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
43#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
44#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
45#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
46#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
47#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
48#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
49
50/* Hardware registers for omap2 */
51#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
52#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
53#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
54#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
55#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
56#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
57#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
58#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
59#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
60#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
61#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
62#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
63#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
64#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
65#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
66#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
67
68#ifdef CONFIG_ARCH_OMAP1
25 69
26#define OMAP_LOGICAL_DMA_CH_COUNT 17 70#define OMAP_LOGICAL_DMA_CH_COUNT 17
27 71
72/* Common channel specific registers for omap1 */
73#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
74#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
75#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
76#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
77#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
78#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
79#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
80#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
81#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
82#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
83#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
84#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
85#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
86
87#else
88
89#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
90
91/* Common channel specific registers for omap2 */
92#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
93#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
94#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
95#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
96#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
97#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
98#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
99#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
100#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
101#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
102#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
103#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
104#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
105
106#endif
107
108/* Channel specific registers only on omap1 */
109#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
110#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
111#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
112#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
113#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
114#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
115#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
116#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
117
118/* Channel specific registers only on omap2 */
119#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
120#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
121#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
122#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
123#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
124
125/*----------------------------------------------------------------------------*/
126
127/* DMA channels for omap1 */
28#define OMAP_DMA_NO_DEVICE 0 128#define OMAP_DMA_NO_DEVICE 0
29#define OMAP_DMA_MCSI1_TX 1 129#define OMAP_DMA_MCSI1_TX 1
30#define OMAP_DMA_MCSI1_RX 2 130#define OMAP_DMA_MCSI1_RX 2
@@ -85,29 +185,72 @@
85#define OMAP_DMA_MMC2_RX 55 185#define OMAP_DMA_MMC2_RX 55
86#define OMAP_DMA_CRYPTO_DES_OUT 56 186#define OMAP_DMA_CRYPTO_DES_OUT 56
87 187
188/* DMA channels for 24xx */
189#define OMAP24XX_DMA_NO_DEVICE 0
190#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
191#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */
192#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */
193#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
194#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
195#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
196#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */
197#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
198#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
199#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
200#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
201#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
202#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
88 203
89#define OMAP_DMA_BASE (0xfffed800) 204#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
90#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) 205#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
91#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) 206#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
92#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) 207#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
93#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) 208#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
94#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) 209#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
95#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) 210#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
96#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) 211#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
97#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) 212#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
98#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) 213#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
99#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) 214#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
100#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) 215#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
101#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) 216#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
102#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) 217#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
103#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) 218#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */
104#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) 219#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */
105#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) 220#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */
106#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) 221#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */
107#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) 222#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */
108#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) 223#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */
109#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 224#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */
225#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */
226#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */
227#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */
228#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */
229#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */
230#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */
231#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */
232#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */
233#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */
110 234
235#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */
236#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */
237#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */
238#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */
239#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */
240#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */
241#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */
242#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */
243#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */
244#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */
245#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */
246#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */
247#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
248#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
249#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
250
251/*----------------------------------------------------------------------------*/
252
253/* Hardware registers for LCD DMA */
111#define OMAP1510_DMA_LCD_BASE (0xfffedb00) 254#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
112#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) 255#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
113#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) 256#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
@@ -116,7 +259,7 @@
116#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) 259#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
117 260
118#define OMAP1610_DMA_LCD_BASE (0xfffee300) 261#define OMAP1610_DMA_LCD_BASE (0xfffee300)
119#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) 262#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
120#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) 263#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
121#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) 264#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
122#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) 265#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
@@ -134,37 +277,18 @@
134#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) 277#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
135#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) 278#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
136 279
137 280#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */
138/* Every LCh has its own set of the registers below */
139#define OMAP_DMA_CSDP(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
140#define OMAP_DMA_CCR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
141#define OMAP_DMA_CICR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
142#define OMAP_DMA_CSR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
143#define OMAP_DMA_CSSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
144#define OMAP_DMA_CSSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
145#define OMAP_DMA_CDSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
146#define OMAP_DMA_CDSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
147#define OMAP_DMA_CEN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
148#define OMAP_DMA_CFN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
149#define OMAP_DMA_CSFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
150#define OMAP_DMA_CSEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
151#define OMAP_DMA_CSAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
152#define OMAP_DMA_CDAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
153#define OMAP_DMA_CDEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
154#define OMAP_DMA_CDFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
155#define OMAP_DMA_COLOR_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
156#define OMAP_DMA_COLOR_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
157#define OMAP_DMA_CCR2(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
158#define OMAP_DMA_CLNK_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
159#define OMAP_DMA_LCH_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
160
161#define OMAP_DMA_TOUT_IRQ (1 << 0)
162#define OMAP_DMA_DROP_IRQ (1 << 1) 281#define OMAP_DMA_DROP_IRQ (1 << 1)
163#define OMAP_DMA_HALF_IRQ (1 << 2) 282#define OMAP_DMA_HALF_IRQ (1 << 2)
164#define OMAP_DMA_FRAME_IRQ (1 << 3) 283#define OMAP_DMA_FRAME_IRQ (1 << 3)
165#define OMAP_DMA_LAST_IRQ (1 << 4) 284#define OMAP_DMA_LAST_IRQ (1 << 4)
166#define OMAP_DMA_BLOCK_IRQ (1 << 5) 285#define OMAP_DMA_BLOCK_IRQ (1 << 5)
167#define OMAP_DMA_SYNC_IRQ (1 << 6) 286#define OMAP1_DMA_SYNC_IRQ (1 << 6)
287#define OMAP2_DMA_PKT_IRQ (1 << 7)
288#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
289#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
290#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
291#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
168 292
169#define OMAP_DMA_DATA_TYPE_S8 0x00 293#define OMAP_DMA_DATA_TYPE_S8 0x00
170#define OMAP_DMA_DATA_TYPE_S16 0x01 294#define OMAP_DMA_DATA_TYPE_S16 0x01
@@ -194,6 +318,7 @@ enum {
194 OMAP_LCD_DMA_B2_BOTTOM 318 OMAP_LCD_DMA_B2_BOTTOM
195}; 319};
196 320
321/* REVISIT: Check if BURST_4 is really 1 (or 2) */
197enum omap_dma_burst_mode { 322enum omap_dma_burst_mode {
198 OMAP_DMA_DATA_BURST_DIS = 0, 323 OMAP_DMA_DATA_BURST_DIS = 0,
199 OMAP_DMA_DATA_BURST_4, 324 OMAP_DMA_DATA_BURST_4,
@@ -206,6 +331,31 @@ enum omap_dma_color_mode {
206 OMAP_DMA_TRANSPARENT_COPY 331 OMAP_DMA_TRANSPARENT_COPY
207}; 332};
208 333
334struct omap_dma_channel_params {
335 int data_type; /* data type 8,16,32 */
336 int elem_count; /* number of elements in a frame */
337 int frame_count; /* number of frames in a element */
338
339 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
340 int src_amode; /* constant , post increment, indexed , double indexed */
341 int src_start; /* source address : physical */
342 int src_ei; /* source element index */
343 int src_fi; /* source frame index */
344
345 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
346 int dst_amode; /* constant , post increment, indexed , double indexed */
347 int dst_start; /* source address : physical */
348 int dst_ei; /* source element index */
349 int dst_fi; /* source frame index */
350
351 int trigger; /* trigger attached if the channel is synchronized */
352 int sync_mode; /* sycn on element, frame , block or packet */
353 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
354
355 int ie; /* interrupt enabled */
356};
357
358
209extern void omap_set_dma_priority(int dst_port, int priority); 359extern void omap_set_dma_priority(int dst_port, int priority);
210extern int omap_request_dma(int dev_id, const char *dev_name, 360extern int omap_request_dma(int dev_id, const char *dev_name,
211 void (* callback)(int lch, u16 ch_status, void *data), 361 void (* callback)(int lch, u16 ch_status, void *data),
@@ -217,24 +367,30 @@ extern void omap_start_dma(int lch);
217extern void omap_stop_dma(int lch); 367extern void omap_stop_dma(int lch);
218extern void omap_set_dma_transfer_params(int lch, int data_type, 368extern void omap_set_dma_transfer_params(int lch, int data_type,
219 int elem_count, int frame_count, 369 int elem_count, int frame_count,
220 int sync_mode); 370 int sync_mode,
371 int dma_trigger, int src_or_dst_synch);
221extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, 372extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
222 u32 color); 373 u32 color);
223 374
224extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 375extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
225 unsigned long src_start); 376 unsigned long src_start,
377 int src_ei, int src_fi);
226extern void omap_set_dma_src_index(int lch, int eidx, int fidx); 378extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
227extern void omap_set_dma_src_data_pack(int lch, int enable); 379extern void omap_set_dma_src_data_pack(int lch, int enable);
228extern void omap_set_dma_src_burst_mode(int lch, 380extern void omap_set_dma_src_burst_mode(int lch,
229 enum omap_dma_burst_mode burst_mode); 381 enum omap_dma_burst_mode burst_mode);
230 382
231extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 383extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
232 unsigned long dest_start); 384 unsigned long dest_start,
385 int dst_ei, int dst_fi);
233extern void omap_set_dma_dest_index(int lch, int eidx, int fidx); 386extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
234extern void omap_set_dma_dest_data_pack(int lch, int enable); 387extern void omap_set_dma_dest_data_pack(int lch, int enable);
235extern void omap_set_dma_dest_burst_mode(int lch, 388extern void omap_set_dma_dest_burst_mode(int lch,
236 enum omap_dma_burst_mode burst_mode); 389 enum omap_dma_burst_mode burst_mode);
237 390
391extern void omap_set_dma_params(int lch,
392 struct omap_dma_channel_params * params);
393
238extern void omap_dma_link_lch (int lch_head, int lch_queue); 394extern void omap_dma_link_lch (int lch_head, int lch_queue);
239extern void omap_dma_unlink_lch (int lch_head, int lch_queue); 395extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
240 396
@@ -244,9 +400,6 @@ extern int omap_get_dma_src_addr_counter(int lch);
244extern void omap_clear_dma(int lch); 400extern void omap_clear_dma(int lch);
245extern int omap_dma_running(void); 401extern int omap_dma_running(void);
246 402
247/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
248extern int omap_dma_in_1510_mode(void);
249
250/* LCD DMA functions */ 403/* LCD DMA functions */
251extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 404extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
252 void *data); 405 void *data);
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index 0d29b9c56a95..f8814a84910e 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -10,6 +10,20 @@
10 10
11#if defined(CONFIG_ARCH_OMAP1) 11#if defined(CONFIG_ARCH_OMAP1)
12 12
13#if defined(CONFIG_ARCH_OMAP730) && \
14 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
15#error "FIXME: OMAP730 doesn't support multiple-OMAP"
16#elif defined(CONFIG_ARCH_OMAP730)
17#define INT_IH2_IRQ INT_730_IH2_IRQ
18#elif defined(CONFIG_ARCH_OMAP15XX)
19#define INT_IH2_IRQ INT_1510_IH2_IRQ
20#elif defined(CONFIG_ARCH_OMAP16XX)
21#define INT_IH2_IRQ INT_1610_IH2_IRQ
22#else
23#warning "IH2 IRQ defaulted"
24#define INT_IH2_IRQ INT_1510_IH2_IRQ
25#endif
26
13 .macro disable_fiq 27 .macro disable_fiq
14 .endm 28 .endm
15 29
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 676807dc50e1..6a883e0bdbb8 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -19,7 +19,7 @@
19#ifndef __ASM_ARCH_OMAP_FPGA_H 19#ifndef __ASM_ARCH_OMAP_FPGA_H
20#define __ASM_ARCH_OMAP_FPGA_H 20#define __ASM_ARCH_OMAP_FPGA_H
21 21
22#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510) 22#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
23extern void omap1510_fpga_init_irq(void); 23extern void omap1510_fpga_init_irq(void);
24#else 24#else
25#define omap1510_fpga_init_irq() (0) 25#define omap1510_fpga_init_irq() (0)
@@ -77,6 +77,8 @@ struct h2p2_dbg_fpga {
77#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 77#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
78#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) 78#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
79 79
80#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
81#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
80 82
81/* 83/*
82 * --------------------------------------------------------------------------- 84 * ---------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 74cb2b93b700..1b3885741ac1 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -67,7 +67,7 @@
67 67
68#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \ 68#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
69 IH_MPUIO_BASE + ((nr) & 0x0f) : \ 69 IH_MPUIO_BASE + ((nr) & 0x0f) : \
70 IH_GPIO_BASE + ((nr) & 0x3f)) 70 IH_GPIO_BASE + (nr))
71 71
72extern int omap_gpio_init(void); /* Call from board init only */ 72extern int omap_gpio_init(void); /* Call from board init only */
73extern int omap_request_gpio(int gpio); 73extern int omap_request_gpio(int gpio);
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 60201e1dd6ad..5406b875c422 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -267,8 +267,6 @@
267#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) 267#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
268#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) 268#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
269 269
270#ifndef __ASSEMBLER__
271
272/* 270/*
273 * --------------------------------------------------------------------------- 271 * ---------------------------------------------------------------------------
274 * Processor specific defines 272 * Processor specific defines
@@ -277,13 +275,11 @@
277 275
278#include "omap730.h" 276#include "omap730.h"
279#include "omap1510.h" 277#include "omap1510.h"
280
281#ifdef CONFIG_ARCH_OMAP24XX
282#include "omap24xx.h" 278#include "omap24xx.h"
283#endif
284
285#include "omap16xx.h" 279#include "omap16xx.h"
286 280
281#ifndef __ASSEMBLER__
282
287/* 283/*
288 * --------------------------------------------------------------------------- 284 * ---------------------------------------------------------------------------
289 * Board specific defines 285 * Board specific defines
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 3d5bcd545082..f5bcc9a1aed6 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -52,23 +52,33 @@
52 * ---------------------------------------------------------------------------- 52 * ----------------------------------------------------------------------------
53 */ 53 */
54 54
55#define PCIO_BASE 0
56
55#if defined(CONFIG_ARCH_OMAP1) 57#if defined(CONFIG_ARCH_OMAP1)
58
56#define IO_PHYS 0xFFFB0000 59#define IO_PHYS 0xFFFB0000
57#define IO_OFFSET -0x01000000 /* Virtual IO = 0xfefb0000 */ 60#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
58#define IO_SIZE 0x40000 61#define IO_SIZE 0x40000
62#define IO_VIRT (IO_PHYS - IO_OFFSET)
63#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define io_p2v(pa) ((pa) - IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
59 66
60#elif defined(CONFIG_ARCH_OMAP2) 67#elif defined(CONFIG_ARCH_OMAP2)
61#define IO_PHYS 0x48000000 /* L4 peripherals; other stuff has to be mapped *
62 * manually. */
63#define IO_OFFSET 0x90000000 /* Virtual IO = 0xd8000000 */
64#define IO_SIZE 0x08000000
65#endif
66 68
67#define IO_VIRT (IO_PHYS + IO_OFFSET) 69/* We map both L3 and L4 on OMAP2 */
68#define IO_ADDRESS(x) ((x) + IO_OFFSET) 70#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
69#define PCIO_BASE 0 71#define L3_24XX_VIRT 0xf8000000
70#define io_p2v(x) ((x) + IO_OFFSET) 72#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
71#define io_v2p(x) ((x) - IO_OFFSET) 73#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
74#define L4_24XX_VIRT 0xd8000000
75#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
76#define IO_OFFSET 0x90000000
77#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
78#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
79#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
80
81#endif
72 82
73#ifndef __ASSEMBLER__ 83#ifndef __ASSEMBLER__
74 84
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 74e108ccac16..9779686bdceb 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -22,8 +22,8 @@
22 * are different. 22 * are different.
23 */ 23 */
24 24
25#ifndef __ASM_ARCH_OMAP1510_IRQS_H 25#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
26#define __ASM_ARCH_OMAP1510_IRQS_H 26#define __ASM_ARCH_OMAP15XX_IRQS_H
27 27
28/* 28/*
29 * IRQ numbers for interrupt handler 1 29 * IRQ numbers for interrupt handler 1
@@ -31,7 +31,6 @@
31 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 31 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
32 * 32 *
33 */ 33 */
34#define INT_IH2_IRQ 0
35#define INT_CAMERA 1 34#define INT_CAMERA 1
36#define INT_FIQ 3 35#define INT_FIQ 3
37#define INT_RTDX 6 36#define INT_RTDX 6
@@ -60,6 +59,7 @@
60/* 59/*
61 * OMAP-1510 specific IRQ numbers for interrupt handler 1 60 * OMAP-1510 specific IRQ numbers for interrupt handler 1
62 */ 61 */
62#define INT_1510_IH2_IRQ 0
63#define INT_1510_RES2 2 63#define INT_1510_RES2 2
64#define INT_1510_SPI_TX 4 64#define INT_1510_SPI_TX 4
65#define INT_1510_SPI_RX 5 65#define INT_1510_SPI_RX 5
@@ -71,6 +71,7 @@
71/* 71/*
72 * OMAP-1610 specific IRQ numbers for interrupt handler 1 72 * OMAP-1610 specific IRQ numbers for interrupt handler 1
73 */ 73 */
74#define INT_1610_IH2_IRQ 0
74#define INT_1610_IH2_FIQ 2 75#define INT_1610_IH2_FIQ 2
75#define INT_1610_McBSP2_TX 4 76#define INT_1610_McBSP2_TX 4
76#define INT_1610_McBSP2_RX 5 77#define INT_1610_McBSP2_RX 5
@@ -231,6 +232,12 @@
231#define INT_730_DMA_CH15 (62 + IH2_BASE) 232#define INT_730_DMA_CH15 (62 + IH2_BASE)
232#define INT_730_NAND (63 + IH2_BASE) 233#define INT_730_NAND (63 + IH2_BASE)
233 234
235#define INT_24XX_SYS_NIRQ 7
236#define INT_24XX_SDMA_IRQ0 12
237#define INT_24XX_SDMA_IRQ1 13
238#define INT_24XX_SDMA_IRQ2 14
239#define INT_24XX_SDMA_IRQ3 15
240#define INT_24XX_DSS_IRQ 25
234#define INT_24XX_GPIO_BANK1 29 241#define INT_24XX_GPIO_BANK1 29
235#define INT_24XX_GPIO_BANK2 30 242#define INT_24XX_GPIO_BANK2 30
236#define INT_24XX_GPIO_BANK3 31 243#define INT_24XX_GPIO_BANK3 31
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index bf545b6e0a26..df50dd53e1dd 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -61,7 +61,7 @@
61 * Note that the is_lbus_device() test is not very efficient on 1510 61 * Note that the is_lbus_device() test is not very efficient on 1510
62 * because of the strncmp(). 62 * because of the strncmp().
63 */ 63 */
64#ifdef CONFIG_ARCH_OMAP1510 64#ifdef CONFIG_ARCH_OMAP15XX
65 65
66/* 66/*
67 * OMAP-1510 Local Bus address offset 67 * OMAP-1510 Local Bus address offset
@@ -84,7 +84,7 @@
84 virt_to_lbus(addr) : \ 84 virt_to_lbus(addr) : \
85 __virt_to_bus(addr);}) 85 __virt_to_bus(addr);})
86 86
87#endif /* CONFIG_ARCH_OMAP1510 */ 87#endif /* CONFIG_ARCH_OMAP15XX */
88 88
89#endif 89#endif
90 90
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
new file mode 100644
index 000000000000..46be8b8d6346
--- /dev/null
+++ b/include/asm-arm/arch-omap/menelaus.h
@@ -0,0 +1,22 @@
1/*
2 * linux/include/asm-arm/arch-omap/menelaus.h
3 *
4 * Functions to access Menelaus power management chip
5 */
6
7#ifndef __ASM_ARCH_MENELAUS_H
8#define __ASM_ARCH_MENELAUS_H
9
10extern void menelaus_mmc_register(void (*callback)(u8 card_mask),
11 unsigned long data);
12extern void menelaus_mmc_remove(void);
13extern void menelaus_mmc_opendrain(int enable);
14
15#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
16#define omap_has_menelaus() 1
17#else
18#define omap_has_menelaus() 0
19#endif
20
21#endif
22
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 1b1ad4105349..13415a9aab06 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -4,7 +4,7 @@
4 * Table of the Omap register configurations for the FUNC_MUX and 4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations. 5 * PULL_DWN combinations.
6 * 6 *
7 * Copyright (C) 2003 Nokia Corporation 7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 * 8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com> 9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 * 10 *
@@ -58,6 +58,16 @@
58 .pu_pd_reg = PU_PD_SEL_##reg, \ 58 .pu_pd_reg = PU_PD_SEL_##reg, \
59 .pu_pd_val = status, 59 .pu_pd_val = status,
60 60
61#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
62 .mux_reg = OMAP730_IO_CONF_##reg, \
63 .mask_offset = mode_offset, \
64 .mask = mode,
65
66#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
67 .pull_reg = OMAP730_IO_CONF_##reg, \
68 .pull_bit = bit, \
69 .pull_val = status,
70
61#else 71#else
62 72
63#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ 73#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
@@ -71,6 +81,15 @@
71#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ 81#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
72 .pu_pd_val = status, 82 .pu_pd_val = status,
73 83
84#define MUX_REG_730(reg, mode_offset, mode) \
85 .mux_reg = OMAP730_IO_CONF_##reg, \
86 .mask_offset = mode_offset, \
87 .mask = mode,
88
89#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
90 .pull_bit = bit, \
91 .pull_val = status,
92
74#endif /* CONFIG_OMAP_MUX_DEBUG */ 93#endif /* CONFIG_OMAP_MUX_DEBUG */
75 94
76#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ 95#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
@@ -84,13 +103,44 @@
84 PU_PD_REG(pu_pd_reg, pu_pd_status) \ 103 PU_PD_REG(pu_pd_reg, pu_pd_status) \
85}, 104},
86 105
106
107/*
108 * OMAP730 has a slightly different config for the pin mux.
109 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
110 * not the FUNC_MUX_CTRL_x regs from hardware.h
111 * - for pull-up/down, only has one enable bit which is is in the same register
112 * as mux config
113 */
114#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
115 pull_reg, pull_bit, pull_status, \
116 pu_pd_reg, pu_pd_status, debug_status)\
117{ \
118 .name = desc, \
119 .debug = debug_status, \
120 MUX_REG_730(mux_reg, mode_offset, mode) \
121 PULL_REG_730(mux_reg, pull_bit, pull_status) \
122 PU_PD_REG(pu_pd_reg, pu_pd_status) \
123},
124
125#define MUX_CFG_24XX(desc, reg_offset, mode, \
126 pull_en, pull_mode, dbg) \
127{ \
128 .name = desc, \
129 .debug = dbg, \
130 .mux_reg = reg_offset, \
131 .mask = mode, \
132 .pull_val = pull_en, \
133 .pu_pd_val = pull_mode, \
134},
135
136
87#define PULL_DISABLED 0 137#define PULL_DISABLED 0
88#define PULL_ENABLED 1 138#define PULL_ENABLED 1
89 139
90#define PULL_DOWN 0 140#define PULL_DOWN 0
91#define PULL_UP 1 141#define PULL_UP 1
92 142
93typedef struct { 143struct pin_config {
94 char *name; 144 char *name;
95 unsigned char busy; 145 unsigned char busy;
96 unsigned char debug; 146 unsigned char debug;
@@ -108,13 +158,23 @@ typedef struct {
108 const char *pu_pd_name; 158 const char *pu_pd_name;
109 const unsigned int pu_pd_reg; 159 const unsigned int pu_pd_reg;
110 const unsigned char pu_pd_val; 160 const unsigned char pu_pd_val;
111} reg_cfg_set; 161};
112 162
113/* 163enum omap730_index {
114 * Lookup table for FUNC_MUX and PULL_DWN register combinations for each 164 /* OMAP 730 keyboard */
115 * device. See also reg_cfg_table below for the register values. 165 E2_730_KBR0,
116 */ 166 J7_730_KBR1,
117typedef enum { 167 E1_730_KBR2,
168 F3_730_KBR3,
169 D2_730_KBR4,
170 C2_730_KBC0,
171 D3_730_KBC1,
172 E4_730_KBC2,
173 F4_730_KBC3,
174 E3_730_KBC4,
175};
176
177enum omap1xxx_index {
118 /* UART1 (BT_UART_GATING)*/ 178 /* UART1 (BT_UART_GATING)*/
119 UART1_TX = 0, 179 UART1_TX = 0,
120 UART1_RTS, 180 UART1_RTS,
@@ -331,245 +391,34 @@ typedef enum {
331 V10_1610_CF_IREQ, 391 V10_1610_CF_IREQ,
332 W10_1610_CF_RESET, 392 W10_1610_CF_RESET,
333 W11_1610_CF_CD1, 393 W11_1610_CF_CD1,
334} reg_cfg_t; 394};
335 395
336#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX) 396enum omap24xx_index {
397 /* 24xx I2C */
398 M19_24XX_I2C1_SCL,
399 L15_24XX_I2C1_SDA,
400 J15_24XX_I2C2_SCL,
401 H19_24XX_I2C2_SDA,
337 402
338/* 403 /* 24xx Menelaus interrupt */
339 * Table of various FUNC_MUX and PULL_DWN combinations for each device. 404 W19_24XX_SYS_NIRQ,
340 * See also reg_cfg_t above for the lookup table.
341 */
342static const reg_cfg_set __initdata_or_module
343reg_cfg_table[] = {
344/*
345 * description mux mode mux pull pull pull pu_pd pu dbg
346 * reg offset mode reg bit ena reg
347 */
348MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
349MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
350
351/* UART2 (COM_UART_GATING), conflicts with USB2 */
352MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
353MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
354MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
355MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
356
357/* UART3 (GIGA_UART_GATING) */
358MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
359MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
360MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
361MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
362MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
363MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
364MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
365
366/* PWT & PWL, conflicts with UART3 */
367MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
368MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
369
370/* USB internal master generic */
371MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
372MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
373/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
374MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
375MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
376MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
377MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
378
379/* USB1 master */
380MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
381MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
382MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
383MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
384MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
385MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
386MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
387MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
388MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
389MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
390MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
391
392/* USB2 master */
393MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
394MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
395MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
396MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
397MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
398MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
399MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
400
401/* OMAP-1510 GPIO */
402MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
403MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
404MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
405
406/* OMAP1610 GPIO */
407MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
408MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
409
410/* OMAP-1710 GPIO */
411MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
412MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
413MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
414MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
415
416/* MPUIO */
417MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
418MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
419MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
420MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
421
422MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
423MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
424MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
425MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
426MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
427MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
428MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
429MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
430MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
431
432/* MCBSP2 */
433MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
434MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
435MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
436MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
437MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
438MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
439
440/* MCBSP3 NOTE: Mode must 1 for clock */
441MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
442
443/* Misc ballouts */
444MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
445MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
446
447/* OMAP-1610 MMC2 */
448MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
449MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
450MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
451MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
452MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
453MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
454MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
455MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
456MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
457MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
458
459/* OMAP-1610 External Trace Interface */
460MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
461MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
462MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
463MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
464MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
465MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
466
467/* OMAP16XX GPIO */
468MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
469MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
470MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
471MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
472MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
473MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
474MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
475MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
476MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
477MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
478MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
479MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
480MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
481
482/* OMAP-1610 uWire */
483MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
484MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
485MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
486MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
487MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
488MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
489
490/* OMAP-1610 Flash */
491MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
492MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
493
494/* First MMC interface, same on 1510, 1610 and 1710 */
495MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
496MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
497MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
498MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
499MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
500MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
501MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
502MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
503MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
504
505/* OMAP-1610 USB0 alternate configuration */
506MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
507MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
508MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
509MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
510MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
511MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
512MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
513MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
514
515/* USB2 interface */
516MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
517MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
518MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
519MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
520MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
521MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
522
523/* 16XX UART */
524MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
525MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
526MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
527MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
528MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
529MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
530
531/* I2C interface */
532MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
533MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
534
535/* Keypad */
536MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
537MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
538MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
539MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
540MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
541MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
542MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
543MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
544MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
545MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
546MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
547
548/* Power management */
549MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
550
551/* MCLK Settings */
552MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
553MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
554MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
555MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
556
557/* CompactFlash controller, conflicts with MMC1 */
558MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
559MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
560MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
561MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
562MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
563};
564 405
565#endif /* __MUX_C__ */ 406 /* 24xx GPIO */
407 Y20_24XX_GPIO60,
408 M15_24XX_GPIO92,
409};
566 410
567#ifdef CONFIG_OMAP_MUX 411#ifdef CONFIG_OMAP_MUX
568/* setup pin muxing in Linux */ 412/* setup pin muxing in Linux */
569extern int omap_cfg_reg(reg_cfg_t reg_cfg); 413extern int omap1_mux_init(void);
414extern int omap2_mux_init(void);
415extern int omap_mux_register(struct pin_config * pins, unsigned long size);
416extern int omap_cfg_reg(unsigned long reg_cfg);
570#else 417#else
571/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ 418/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
572static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; } 419static inline int omap1_mux_init(void) { return 0; }
420static inline int omap2_mux_init(void) { return 0; }
421static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
573#endif 422#endif
574 423
575#endif 424#endif
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
index f086a3933906..c575d354850f 100644
--- a/include/asm-arm/arch-omap/omap1510.h
+++ b/include/asm-arm/arch-omap/omap1510.h
@@ -25,8 +25,8 @@
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27 27
28#ifndef __ASM_ARCH_OMAP1510_H 28#ifndef __ASM_ARCH_OMAP15XX_H
29#define __ASM_ARCH_OMAP1510_H 29#define __ASM_ARCH_OMAP15XX_H
30 30
31/* 31/*
32 * ---------------------------------------------------------------------------- 32 * ----------------------------------------------------------------------------
@@ -44,5 +44,5 @@
44#define OMAP1510_DSPREG_SIZE SZ_128K 44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000 45#define OMAP1510_DSPREG_START 0xE1000000
46 46
47#endif /* __ASM_ARCH_OMAP1510_H */ 47#endif /* __ASM_ARCH_OMAP15XX_H */
48 48
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index a9105466a417..6e59805fa654 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -1,15 +1,24 @@
1#ifndef __ASM_ARCH_OMAP24XX_H 1#ifndef __ASM_ARCH_OMAP24XX_H
2#define __ASM_ARCH_OMAP24XX_H 2#define __ASM_ARCH_OMAP24XX_H
3 3
4#define OMAP24XX_L4_IO_BASE 0x48000000 4/*
5 * Please place only base defines here and put the rest in device
6 * specific headers. Note also that some of these defines are needed
7 * for omap1 to compile without adding ifdefs.
8 */
9
10#define L4_24XX_BASE 0x48000000
11#define L3_24XX_BASE 0x68000000
5 12
6/* interrupt controller */ 13/* interrupt controller */
7#define OMAP24XX_IC_BASE (OMAP24XX_L4_IO_BASE + 0xfe000) 14#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
8#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) 15#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
9
10#define OMAP24XX_IVA_INTC_BASE 0x40000000 16#define OMAP24XX_IVA_INTC_BASE 0x40000000
11
12#define IRQ_SIR_IRQ 0x0040 17#define IRQ_SIR_IRQ 0x0040
13 18
19#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
20#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
21#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
22
14#endif /* __ASM_ARCH_OMAP24XX_H */ 23#endif /* __ASM_ARCH_OMAP24XX_H */
15 24
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h
new file mode 100644
index 000000000000..4ba2622cc142
--- /dev/null
+++ b/include/asm-arm/arch-omap/omapfb.h
@@ -0,0 +1,281 @@
1/*
2 * File: include/asm-arm/arch-omap/omapfb.h
3 *
4 * Framebuffer driver for TI OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __OMAPFB_H
25#define __OMAPFB_H
26
27/* IOCTL commands. */
28
29#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
30#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
31#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
32#define OMAP_IO(num) _IO('O', num)
33
34#define OMAPFB_MIRROR OMAP_IOW(31, int)
35#define OMAPFB_SYNC_GFX OMAP_IO(37)
36#define OMAPFB_VSYNC OMAP_IO(38)
37#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, enum omapfb_update_mode)
38#define OMAPFB_GET_CAPS OMAP_IOR(42, unsigned long)
39#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, enum omapfb_update_mode)
40#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
41#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
42#define OMAPFB_UPDATE_WINDOW OMAP_IOW(47, struct omapfb_update_window)
43#define OMAPFB_SETUP_PLANE OMAP_IOW(48, struct omapfb_setup_plane)
44#define OMAPFB_ENABLE_PLANE OMAP_IOW(49, struct omapfb_enable_plane)
45#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
46
47#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
48#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
49#define OMAPFB_CAPS_PANEL_MASK 0xff000000
50
51#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
52#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
53
54/* Values from DSP must map to lower 16-bits */
55#define OMAPFB_FORMAT_MASK 0x00ff
56#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
57
58enum omapfb_color_format {
59 OMAPFB_COLOR_RGB565 = 0,
60 OMAPFB_COLOR_YUV422,
61 OMAPFB_COLOR_YUV420,
62 OMAPFB_COLOR_CLUT_8BPP,
63 OMAPFB_COLOR_CLUT_4BPP,
64 OMAPFB_COLOR_CLUT_2BPP,
65 OMAPFB_COLOR_CLUT_1BPP,
66};
67
68struct omapfb_update_window {
69 u32 x, y;
70 u32 width, height;
71 u32 format;
72};
73
74enum omapfb_plane {
75 OMAPFB_PLANE_GFX = 0,
76 OMAPFB_PLANE_VID1,
77 OMAPFB_PLANE_VID2,
78};
79
80enum omapfb_channel_out {
81 OMAPFB_CHANNEL_OUT_LCD = 0,
82 OMAPFB_CHANNEL_OUT_DIGIT,
83};
84
85struct omapfb_setup_plane {
86 u8 plane;
87 u8 channel_out;
88 u32 offset;
89 u32 pos_x, pos_y;
90 u32 width, height;
91 u32 color_mode;
92};
93
94struct omapfb_enable_plane {
95 u8 plane;
96 u8 enable;
97};
98
99enum omapfb_color_key_type {
100 OMAPFB_COLOR_KEY_DISABLED = 0,
101 OMAPFB_COLOR_KEY_GFX_DST,
102 OMAPFB_COLOR_KEY_VID_SRC,
103};
104
105struct omapfb_color_key {
106 u8 channel_out;
107 u32 background;
108 u32 trans_key;
109 u8 key_type;
110};
111
112enum omapfb_update_mode {
113 OMAPFB_UPDATE_DISABLED = 0,
114 OMAPFB_AUTO_UPDATE,
115 OMAPFB_MANUAL_UPDATE
116};
117
118#ifdef __KERNEL__
119
120#include <linux/completion.h>
121#include <linux/interrupt.h>
122#include <linux/fb.h>
123
124#define OMAP_LCDC_INV_VSYNC 0x0001
125#define OMAP_LCDC_INV_HSYNC 0x0002
126#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
127#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
128#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
129#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
130
131#define OMAP_LCDC_SIGNAL_MASK 0x003f
132
133#define OMAP_LCDC_PANEL_TFT 0x0100
134
135#ifdef CONFIG_ARCH_OMAP1
136#define OMAPFB_PLANE_NUM 1
137#else
138#define OMAPFB_PLANE_NUM 3
139#endif
140
141struct omapfb_device;
142
143struct lcd_panel {
144 const char *name;
145 int config; /* TFT/STN, signal inversion */
146 int bpp; /* Pixel format in fb mem */
147 int data_lines; /* Lines on LCD HW interface */
148
149 int x_res, y_res;
150 int pixel_clock; /* In kHz */
151 int hsw; /* Horizontal synchronization
152 pulse width */
153 int hfp; /* Horizontal front porch */
154 int hbp; /* Horizontal back porch */
155 int vsw; /* Vertical synchronization
156 pulse width */
157 int vfp; /* Vertical front porch */
158 int vbp; /* Vertical back porch */
159 int acb; /* ac-bias pin frequency */
160 int pcd; /* pixel clock divider.
161 Obsolete use pixel_clock instead */
162
163 int (*init) (struct omapfb_device *fbdev);
164 void (*cleanup) (void);
165 int (*enable) (void);
166 void (*disable) (void);
167 unsigned long (*get_caps) (void);
168 int (*set_bklight_level)(unsigned int level);
169 unsigned int (*get_bklight_level)(void);
170 unsigned int (*get_bklight_max) (void);
171 int (*run_test) (int test_num);
172};
173
174struct omapfb_device;
175
176struct extif_timings {
177 int cs_on_time;
178 int cs_off_time;
179 int we_on_time;
180 int we_off_time;
181 int re_on_time;
182 int re_off_time;
183 int we_cycle_time;
184 int re_cycle_time;
185 int cs_pulse_width;
186 int access_time;
187};
188
189struct lcd_ctrl_extif {
190 int (*init) (void);
191 void (*cleanup) (void);
192 void (*set_timings) (const struct extif_timings *timings);
193 void (*write_command) (u32 cmd);
194 u32 (*read_data) (void);
195 void (*write_data) (u32 data);
196 void (*transfer_area) (int width, int height,
197 void (callback)(void * data), void *data);
198};
199
200struct lcd_ctrl {
201 const char *name;
202 void *data;
203
204 int (*init) (struct omapfb_device *fbdev,
205 int ext_mode, int req_vram_size);
206 void (*cleanup) (void);
207 void (*get_vram_layout)(unsigned long *size,
208 void **virt_base,
209 dma_addr_t *phys_base);
210 unsigned long (*get_caps) (void);
211 int (*set_update_mode)(enum omapfb_update_mode mode);
212 enum omapfb_update_mode (*get_update_mode)(void);
213 int (*setup_plane) (int plane, int channel_out,
214 unsigned long offset,
215 int screen_width,
216 int pos_x, int pos_y, int width,
217 int height, int color_mode);
218 int (*enable_plane) (int plane, int enable);
219 int (*update_window) (struct omapfb_update_window *win,
220 void (*callback)(void *),
221 void *callback_data);
222 void (*sync) (void);
223 void (*suspend) (void);
224 void (*resume) (void);
225 int (*run_test) (int test_num);
226 int (*setcolreg) (u_int regno, u16 red, u16 green,
227 u16 blue, u16 transp,
228 int update_hw_mem);
229 int (*set_color_key) (struct omapfb_color_key *ck);
230
231};
232
233enum omapfb_state {
234 OMAPFB_DISABLED = 0,
235 OMAPFB_SUSPENDED= 99,
236 OMAPFB_ACTIVE = 100
237};
238
239struct omapfb_device {
240 int state;
241 int ext_lcdc; /* Using external
242 LCD controller */
243 struct semaphore rqueue_sema;
244
245 void *vram_virt_base;
246 dma_addr_t vram_phys_base;
247 unsigned long vram_size;
248
249 int color_mode;
250 int palette_size;
251 int mirror;
252 u32 pseudo_palette[17];
253
254 struct lcd_panel *panel; /* LCD panel */
255 struct lcd_ctrl *ctrl; /* LCD controller */
256 struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
257 struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
258 interface */
259 struct fb_info *fb_info;
260
261 struct device *dev;
262};
263
264extern struct lcd_panel h3_panel;
265extern struct lcd_panel h2_panel;
266extern struct lcd_panel p2_panel;
267extern struct lcd_panel osk_panel;
268extern struct lcd_panel innovator1610_panel;
269extern struct lcd_panel innovator1510_panel;
270
271#ifdef CONFIG_ARCH_OMAP1
272extern struct lcd_ctrl omap1_lcd_ctrl;
273#else
274extern struct lcd_ctrl omap2_disp_ctrl;
275#endif
276
277extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
278
279#endif /* __KERNEL__ */
280
281#endif /* __OMAPFB_H */
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
index fbd742d0c499..7c790425e363 100644
--- a/include/asm-arm/arch-omap/pm.h
+++ b/include/asm-arm/arch-omap/pm.h
@@ -98,7 +98,14 @@
98#define OMAP1610_IDLECT3 0xfffece24 98#define OMAP1610_IDLECT3 0xfffece24
99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400 99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
100 100
101#if !defined(CONFIG_ARCH_OMAP1510) && \ 101#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
102#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
103#define OMAP730_IDLECT3_VAL 0x3f
104#define OMAP730_IDLECT3 0xfffece24
105#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
106
107#if !defined(CONFIG_ARCH_OMAP730) && \
108 !defined(CONFIG_ARCH_OMAP15XX) && \
102 !defined(CONFIG_ARCH_OMAP16XX) && \ 109 !defined(CONFIG_ARCH_OMAP16XX) && \
103 !defined(CONFIG_ARCH_OMAP24XX) 110 !defined(CONFIG_ARCH_OMAP24XX)
104#error "Power management for this processor not implemented yet" 111#error "Power management for this processor not implemented yet"
@@ -107,8 +114,10 @@
107#ifndef __ASSEMBLER__ 114#ifndef __ASSEMBLER__
108extern void omap_pm_idle(void); 115extern void omap_pm_idle(void);
109extern void omap_pm_suspend(void); 116extern void omap_pm_suspend(void);
117extern void omap730_cpu_suspend(unsigned short, unsigned short);
110extern void omap1510_cpu_suspend(unsigned short, unsigned short); 118extern void omap1510_cpu_suspend(unsigned short, unsigned short);
111extern void omap1610_cpu_suspend(unsigned short, unsigned short); 119extern void omap1610_cpu_suspend(unsigned short, unsigned short);
120extern void omap730_idle_loop_suspend(void);
112extern void omap1510_idle_loop_suspend(void); 121extern void omap1510_idle_loop_suspend(void);
113extern void omap1610_idle_loop_suspend(void); 122extern void omap1610_idle_loop_suspend(void);
114 123
@@ -118,6 +127,8 @@ extern void omap_serial_wake_trigger(int enable);
118#define omap_serial_wake_trigger(x) {} 127#define omap_serial_wake_trigger(x) {}
119#endif /* CONFIG_OMAP_SERIAL_WAKE */ 128#endif /* CONFIG_OMAP_SERIAL_WAKE */
120 129
130extern unsigned int omap730_cpu_suspend_sz;
131extern unsigned int omap730_idle_loop_suspend_sz;
121extern unsigned int omap1510_cpu_suspend_sz; 132extern unsigned int omap1510_cpu_suspend_sz;
122extern unsigned int omap1510_idle_loop_suspend_sz; 133extern unsigned int omap1510_idle_loop_suspend_sz;
123extern unsigned int omap1610_cpu_suspend_sz; 134extern unsigned int omap1610_cpu_suspend_sz;
@@ -131,6 +142,10 @@ extern unsigned int omap1610_idle_loop_suspend_sz;
131#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) 142#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
132#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] 143#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
133 144
145#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
146#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
147#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
148
134#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) 149#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
135#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) 150#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
136#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] 151#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
@@ -188,13 +203,34 @@ enum mpui1510_save_state {
188 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, 203 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
189 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, 204 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
190 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, 205 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
191#if defined(CONFIG_ARCH_OMAP1510) 206#if defined(CONFIG_ARCH_OMAP15XX)
192 MPUI1510_SLEEP_SAVE_SIZE 207 MPUI1510_SLEEP_SAVE_SIZE
193#else 208#else
194 MPUI1510_SLEEP_SAVE_SIZE = 0 209 MPUI1510_SLEEP_SAVE_SIZE = 0
195#endif 210#endif
196}; 211};
197 212
213enum mpui730_save_state {
214 MPUI730_SLEEP_SAVE_START = 0,
215 /*
216 * MPUI registers 32 bits
217 */
218 MPUI730_SLEEP_SAVE_MPUI_CTRL,
219 MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
220 MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
221 MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
222 MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
223 MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
224 MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
225 MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
226 MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
227#if defined(CONFIG_ARCH_OMAP730)
228 MPUI730_SLEEP_SAVE_SIZE
229#else
230 MPUI730_SLEEP_SAVE_SIZE = 0
231#endif
232};
233
198enum mpui1610_save_state { 234enum mpui1610_save_state {
199 MPUI1610_SLEEP_SAVE_START = 0, 235 MPUI1610_SLEEP_SAVE_START = 0,
200 /* 236 /*
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h
new file mode 100644
index 000000000000..7b48a5cbb15f
--- /dev/null
+++ b/include/asm-arm/arch-omap/prcm.h
@@ -0,0 +1,429 @@
1/*
2 * prcm.h - Access definations for use in OMAP24XX clock and power management
3 *
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
22#define __ASM_ARM_ARCH_DPM_PRCM_H
23
24/* SET_PERFORMANCE_LEVEL PARAMETERS */
25#define PRCM_HALF_SPEED 1
26#define PRCM_FULL_SPEED 2
27
28#ifndef __ASSEMBLER__
29
30#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
31
32#define PRCM_REVISION PRCM_REG32(0x000)
33#define PRCM_SYSCONFIG PRCM_REG32(0x010)
34#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
35#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
36#define PRCM_VOLTCTRL PRCM_REG32(0x050)
37#define PRCM_VOLTST PRCM_REG32(0x054)
38#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
39#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
40#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
41#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
42#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
43#define PRCM_VOLTSETUP PRCM_REG32(0x090)
44#define PRCM_CLKSSETUP PRCM_REG32(0x094)
45#define PRCM_POLCTRL PRCM_REG32(0x098)
46
47/* GENERAL PURPOSE */
48#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
49#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
50#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
51#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
52#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
53#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
54#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
55#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
56#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
57#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
58#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
59#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
60#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
61#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
62#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
63#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
64#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
65#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
66#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
67#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
68
69/* MPU */
70#define CM_CLKSEL_MPU PRCM_REG32(0x140)
71#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
72#define RM_RSTST_MPU PRCM_REG32(0x158)
73#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
74#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
75#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
76#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
77#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
78#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
79
80/* CORE */
81#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
82#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
83#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
84#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
85#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
86#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
87#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
88#define CM_IDLEST1_CORE PRCM_REG32(0x220)
89#define CM_IDLEST2_CORE PRCM_REG32(0x224)
90#define CM_IDLEST3_CORE PRCM_REG32(0x228)
91#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
92#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
93#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
94#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
95#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
96#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
97#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
98#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
99#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
100#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
101#define PM_WKST1_CORE PRCM_REG32(0x2B0)
102#define PM_WKST2_CORE PRCM_REG32(0x2B4)
103#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
104#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
105#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
106
107/* GFX */
108#define CM_FCLKEN_GFX PRCM_REG32(0x300)
109#define CM_ICLKEN_GFX PRCM_REG32(0x310)
110#define CM_IDLEST_GFX PRCM_REG32(0x320)
111#define CM_CLKSEL_GFX PRCM_REG32(0x340)
112#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
113#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
114#define RM_RSTST_GFX PRCM_REG32(0x358)
115#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
116#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
117#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
118
119/* WAKE-UP */
120#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
121#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
122#define CM_IDLEST_WKUP PRCM_REG32(0x420)
123#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
124#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
125#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
126#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
127#define RM_RSTST_WKUP PRCM_REG32(0x458)
128#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
129#define PM_WKST_WKUP PRCM_REG32(0x4B0)
130
131/* CLOCKS */
132#define CM_CLKEN_PLL PRCM_REG32(0x500)
133#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
134#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
135#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
136#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
137
138/* DSP */
139#define CM_FCLKEN_DSP PRCM_REG32(0x800)
140#define CM_ICLKEN_DSP PRCM_REG32(0x810)
141#define CM_IDLEST_DSP PRCM_REG32(0x820)
142#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
143#define CM_CLKSEL_DSP PRCM_REG32(0x840)
144#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
145#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
146#define RM_RSTST_DSP PRCM_REG32(0x858)
147#define PM_WKEN_DSP PRCM_REG32(0x8A0)
148#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
149#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
150#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
151#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
152#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
153
154/* IVA */
155#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
156#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
157
158/* Modem on 2430 */
159#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
160#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
161#define CM_IDLEST_MDM PRCM_REG32(0xC20)
162#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
163
164/* FIXME: Move to header for 2430 */
165#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)
166#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
167
168#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
169#define GPMC_BASE (OMAP24XX_GPMC_BASE)
170#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))
171
172#define GPT1_BASE (OMAP24XX_GPT1)
173#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
174
175/* Misc sysconfig */
176#define DISPC_SYSCONFIG DISP_REG32(0x410)
177#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)
178#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
179#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)
180
181//#define DSP_MMU_SYSCONFIG 0x5A000010
182#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)
183//#define IVA_MMU_SYSCONFIG 0x5D000010
184//#define DSP_DMA_SYSCONFIG 0x00FCC02C
185#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
186#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
187#define GPMC_SYSCONFIG GPMC_REG32(0x010)
188#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)
189#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
190#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
191#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
192//#define IVA_SYSCONFIG 0x5C060010
193#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)
194#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)
195#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)
196//#define VLYNQ_SYSCONFIG 0x67FFFE10
197
198/* rkw - good cannidates for PM_ to start what nm was trying */
199#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
200#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
201#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
202#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
203#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
204#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
205#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
206#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
207#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
208#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
209#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
210
211#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
212#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
213#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
214#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
215#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
216#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
217#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
218#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
219#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
220#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
221#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
222#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
223
224#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
225
226#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10))
227#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10))
228#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10))
229#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
230
231/* GP TIMER 1 */
232#define GPTIMER1_TISTAT GPT1_REG32(0x014)
233#define GPTIMER1_TISR GPT1_REG32(0x018)
234#define GPTIMER1_TIER GPT1_REG32(0x01C)
235#define GPTIMER1_TWER GPT1_REG32(0x020)
236#define GPTIMER1_TCLR GPT1_REG32(0x024)
237#define GPTIMER1_TCRR GPT1_REG32(0x028)
238#define GPTIMER1_TLDR GPT1_REG32(0x02C)
239#define GPTIMER1_TTGR GPT1_REG32(0x030)
240#define GPTIMER1_TWPS GPT1_REG32(0x034)
241#define GPTIMER1_TMAR GPT1_REG32(0x038)
242#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
243#define GPTIMER1_TSICR GPT1_REG32(0x040)
244#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
245
246/* rkw -- base fix up please... */
247#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018)
248
249/* SDRC */
250#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060)
251#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064)
252#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068)
253#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C)
254#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070)
255#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084)
256
257/* GPIO 1 */
258#define GPIO1_BASE GPIOX_BASE(1)
259#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
260#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
261#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
262#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
263#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
264#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
265#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
266#define GPIO1_DATAIN GPIO1_REG32(0x038)
267#define GPIO1_OE GPIO1_REG32(0x034)
268#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
269
270/* GPIO2 */
271#define GPIO2_BASE GPIOX_BASE(2)
272#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
273#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
274#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
275#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
276#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
277#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
278#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
279#define GPIO2_DATAIN GPIO2_REG32(0x038)
280#define GPIO2_OE GPIO2_REG32(0x034)
281#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
282
283/* GPIO 3 */
284#define GPIO3_BASE GPIOX_BASE(3)
285#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
286#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
287#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
288#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
289#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
290#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
291#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
292#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
293#define GPIO3_DATAIN GPIO3_REG32(0x038)
294#define GPIO3_OE GPIO3_REG32(0x034)
295#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
296#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
297#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
298
299/* GPIO 4 */
300#define GPIO4_BASE GPIOX_BASE(4)
301#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
302#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
303#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
304#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
305#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
306#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
307#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
308#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
309#define GPIO4_DATAIN GPIO4_REG32(0x038)
310#define GPIO4_OE GPIO4_REG32(0x034)
311#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
312#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
313#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
314
315
316/* IO CONFIG */
317#define CONTROL_BASE (OMAP24XX_CTRL_BASE)
318#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset))
319
320#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
321#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
322#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
323#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
324#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
325#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
326#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC)
327#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
328#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
329
330/* CONTROL */
331#define CONTROL_DEVCONF CONTROL_REG32(0x274)
332
333/* INTERRUPT CONTROLLER */
334#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)
335#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
336
337#define INTC1_U_BASE INTC_REG32(0x000)
338#define INTC_MIR0 INTC_REG32(0x084)
339#define INTC_MIR_SET0 INTC_REG32(0x08C)
340#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
341#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
342#define INTC_MIR1 INTC_REG32(0x0A4)
343#define INTC_MIR_SET1 INTC_REG32(0x0AC)
344#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
345#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
346#define INTC_MIR2 INTC_REG32(0x0C4)
347#define INTC_MIR_SET2 INTC_REG32(0x0CC)
348#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
349#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
350#define INTC_SIR_IRQ INTC_REG32(0x040)
351#define INTC_CONTROL INTC_REG32(0x048)
352#define INTC_ILR11 INTC_REG32(0x12C)
353#define INTC_ILR32 INTC_REG32(0x180)
354#define INTC_ILR37 INTC_REG32(0x194)
355#define INTC_SYSCONFIG INTC_REG32(0x010)
356
357/* RAM FIREWALL */
358#define RAMFW_BASE (0x68005000)
359#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
360
361#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
362#define RAMFW_READPERM0 RAMFW_REG32(0x050)
363#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
364
365/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
366//#define DEBUG_BOARD_LED_REGISTER 0x04000014
367
368/* GPMC CS0 */
369#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
370#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
371#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
372#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
373#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
374#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
375#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
376
377/* GPMC CS1 */
378#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
379#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
380#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
381#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
382#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
383#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
384#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
385
386/* DSS */
387#define DSS_CONTROL DISP_REG32(0x040)
388#define DISPC_CONTROL DISP_REG32(0x440)
389#define DISPC_SYSSTATUS DISP_REG32(0x414)
390#define DISPC_IRQSTATUS DISP_REG32(0x418)
391#define DISPC_IRQENABLE DISP_REG32(0x41C)
392#define DISPC_CONFIG DISP_REG32(0x444)
393#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
394#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
395#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
396#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
397#define DISPC_LINE_NUMBER DISP_REG32(0x460)
398#define DISPC_TIMING_H DISP_REG32(0x464)
399#define DISPC_TIMING_V DISP_REG32(0x468)
400#define DISPC_POL_FREQ DISP_REG32(0x46C)
401#define DISPC_DIVISOR DISP_REG32(0x470)
402#define DISPC_SIZE_DIG DISP_REG32(0x478)
403#define DISPC_SIZE_LCD DISP_REG32(0x47C)
404#define DISPC_GFX_BA0 DISP_REG32(0x480)
405#define DISPC_GFX_BA1 DISP_REG32(0x484)
406#define DISPC_GFX_POSITION DISP_REG32(0x488)
407#define DISPC_GFX_SIZE DISP_REG32(0x48C)
408#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
409#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
410#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
411#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
412#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
413#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
414#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
415#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
416#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
417
418/* Wake up define for board */
419#define GPIO97 (1 << 1)
420#define GPIO88 (1 << 24)
421
422#endif /* __ASSEMBLER__ */
423
424#endif
425
426
427
428
429
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
new file mode 100644
index 000000000000..e72ccbf0fe06
--- /dev/null
+++ b/include/asm-arm/arch-omap/sram.h
@@ -0,0 +1,38 @@
1/*
2 * linux/include/asm-arm/arch-omap/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H
13
14extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16
17extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
18 u32 base_cs, u32 force_unlock);
19extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
20 u32 mem_type);
21extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
22
23
24/* Do not use these */
25extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
26extern unsigned long sram_reprogram_clock_sz;
27
28extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
29 u32 base_cs, u32 force_unlock);
30extern unsigned long sram_ddr_init_sz;
31
32extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
33extern unsigned long sram_set_prcm_sz;
34
35extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type);
36extern unsigned long sram_reprogram_sdrc_sz;
37
38#endif
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index ff37bc27e603..b43cdd2a3874 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -6,18 +6,21 @@
6#define __ASM_ARCH_SYSTEM_H 6#define __ASM_ARCH_SYSTEM_H
7#include <linux/config.h> 7#include <linux/config.h>
8#include <asm/mach-types.h> 8#include <asm/mach-types.h>
9#include <asm/hardware/clock.h>
9#include <asm/arch/hardware.h> 10#include <asm/arch/hardware.h>
10#include <asm/mach-types.h> 11#include <asm/arch/prcm.h>
12
13#ifndef CONFIG_MACH_VOICEBLUE
14#define voiceblue_reset() do {} while (0)
15#endif
11 16
12static inline void arch_idle(void) 17static inline void arch_idle(void)
13{ 18{
14 cpu_do_idle(); 19 cpu_do_idle();
15} 20}
16 21
17static inline void arch_reset(char mode) 22static inline void omap1_arch_reset(char mode)
18{ 23{
19
20#ifdef CONFIG_ARCH_OMAP16XX
21 /* 24 /*
22 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 25 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
23 * "Global Software Reset Affects Traffic Controller Frequency". 26 * "Global Software Reset Affects Traffic Controller Frequency".
@@ -27,13 +30,31 @@ static inline void arch_reset(char mode)
27 DPLL_CTL); 30 DPLL_CTL);
28 omap_writew(0x8, ARM_RSTCT1); 31 omap_writew(0x8, ARM_RSTCT1);
29 } 32 }
30#endif 33
31#ifdef CONFIG_MACH_VOICEBLUE
32 if (machine_is_voiceblue()) 34 if (machine_is_voiceblue())
33 voiceblue_reset(); 35 voiceblue_reset();
34 else 36 else
35#endif
36 omap_writew(1, ARM_RSTCT1); 37 omap_writew(1, ARM_RSTCT1);
37} 38}
38 39
40static inline void omap2_arch_reset(char mode)
41{
42 u32 rate;
43 struct clk *vclk, *sclk;
44
45 vclk = clk_get(NULL, "virt_prcm_set");
46 sclk = clk_get(NULL, "sys_ck");
47 rate = clk_get_rate(sclk);
48 clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
49 RM_RSTCTRL_WKUP |= 2;
50}
51
52static inline void arch_reset(char mode)
53{
54 if (!cpu_is_omap24xx())
55 omap1_arch_reset(mode);
56 else
57 omap2_arch_reset(mode);
58}
59
39#endif 60#endif
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
index b61ddb491e83..21f2e367185a 100644
--- a/include/asm-arm/arch-omap/timex.h
+++ b/include/asm-arm/arch-omap/timex.h
@@ -28,6 +28,14 @@
28#if !defined(__ASM_ARCH_OMAP_TIMEX_H) 28#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
29#define __ASM_ARCH_OMAP_TIMEX_H 29#define __ASM_ARCH_OMAP_TIMEX_H
30 30
31/*
32 * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
33 * and that's why the CLOCK_TICK_RATE is not 32768.
34 */
35#ifdef CONFIG_OMAP_32K_TIMER
36#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
37#else
31#define CLOCK_TICK_RATE (HZ * 100000UL) 38#define CLOCK_TICK_RATE (HZ * 100000UL)
39#endif
32 40
33#endif /* __ASM_ARCH_OMAP_TIMEX_H */ 41#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index 3545c86859cc..c718264affbd 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -36,10 +36,14 @@ putstr(const char *s)
36 volatile u8 * uart = 0; 36 volatile u8 * uart = 0;
37 int shift = 2; 37 int shift = 2;
38 38
39#ifdef CONFIG_MACH_OMAP_PALMTE
40 return;
41#endif
42
39#ifdef CONFIG_ARCH_OMAP 43#ifdef CONFIG_ARCH_OMAP
40#ifdef CONFIG_OMAP_LL_DEBUG_UART3 44#ifdef CONFIG_OMAP_LL_DEBUG_UART3
41 uart = (volatile u8 *)(OMAP_UART3_BASE); 45 uart = (volatile u8 *)(OMAP_UART3_BASE);
42#elif CONFIG_OMAP_LL_DEBUG_UART2 46#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
43 uart = (volatile u8 *)(OMAP_UART2_BASE); 47 uart = (volatile u8 *)(OMAP_UART2_BASE);
44#else 48#else
45 uart = (volatile u8 *)(OMAP_UART1_BASE); 49 uart = (volatile u8 *)(OMAP_UART1_BASE);
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
index 311f2bb5386a..0b43495d24b4 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/include/asm-arm/arch-pxa/sharpsl.h
@@ -21,12 +21,18 @@ struct corgits_machinfo {
21 void (*wait_hsync)(void); 21 void (*wait_hsync)(void);
22}; 22};
23 23
24
24/* 25/*
25 * SharpSL Backlight 26 * SharpSL Backlight
26 */ 27 */
27
28struct corgibl_machinfo { 28struct corgibl_machinfo {
29 int max_intensity; 29 int max_intensity;
30 void (*set_bl_intensity)(int intensity); 30 void (*set_bl_intensity)(int intensity);
31}; 31};
32extern void corgibl_limit_intensity(int limit);
33
32 34
35/*
36 * SharpSL Battery/PM Driver
37 */
38extern void sharpsl_battery_kick(void);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
index 6ec67b018c09..949878c0d908 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -18,6 +18,11 @@
18#ifndef SSP_H 18#ifndef SSP_H
19#define SSP_H 19#define SSP_H
20 20
21/*
22 * SSP initialisation flags
23 */
24#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */
25
21struct ssp_state { 26struct ssp_state {
22 u32 cr0; 27 u32 cr0;
23 u32 cr1; 28 u32 cr1;
@@ -31,6 +36,7 @@ struct ssp_dev {
31 u32 flags; 36 u32 flags;
32 u32 psp_flags; 37 u32 psp_flags;
33 u32 speed; 38 u32 speed;
39 int irq;
34}; 40};
35 41
36int ssp_write_word(struct ssp_dev *dev, u32 data); 42int ssp_write_word(struct ssp_dev *dev, u32 data);
@@ -40,7 +46,7 @@ void ssp_enable(struct ssp_dev *dev);
40void ssp_disable(struct ssp_dev *dev); 46void ssp_disable(struct ssp_dev *dev);
41void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp); 47void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
42void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); 48void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
43int ssp_init(struct ssp_dev *dev, u32 port); 49int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
44int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); 50int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
45void ssp_exit(struct ssp_dev *dev); 51void ssp_exit(struct ssp_dev *dev);
46 52
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 03:43:30 -0500