[SPARC64]: SUN4U PCI-E controller support.

Some minor refactoring in the generic code was necessary for
this:

1) This controller requires 8-byte access to the interrupt map
   and clear register.  They are 64-bits on all the other
   SBUS and PCI controllers anyways, so this was easy to cure.

2) The IMAP register has a different layout and some bits that we
   need to preserve, so use a read/modify/write when making
   changes to the IMAP register in generic code.

3) Flushing the entire IOMMU TLB is best done with a single write
   to a register on this PCI controller, add a iommu->iommu_flushinv
   for this.

Still lacks MSI support, that will come later.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
index e199594a1e9b..0b1813f41045 100644
--- a/include/asm-sparc64/iommu.h
+++ b/include/asm-sparc64/iommu.h
@@ -32,6 +32,7 @@ struct iommu {
         unsigned long           iommu_control;
         unsigned long           iommu_tsbbase;
         unsigned long           iommu_flush;
+        unsigned long           iommu_flushinv;
         unsigned long           iommu_ctxflush;
         unsigned long           write_complete_reg;
         unsigned long           dummy_page;