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authorKumar Gala <galak@kernel.crashing.org>2007-08-20 09:50:28 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-08-22 23:43:29 -0400
commit33d71d26ba982f99b8cb76b86b2e1e0a0964a8ac (patch)
tree20826dc9252a265438c23f6e755a285d6c2508ba /include
parented16c20da6f500bc2dfad933078d2987636a7b60 (diff)
[POWERPC] Copy over headers from arch/ppc to arch/powerpc that we need
To build arch/powerpc without including asm-ppc/ we need these files in asm-powerpc/ Moved some headers under arch/powerpc/platforms if they were only used by platform or driver files and fixed up the source file includes to match the new locations Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/8xx_immap.h564
-rw-r--r--include/asm-powerpc/commproc.h692
-rw-r--r--include/asm-powerpc/cpm2.h1248
-rw-r--r--include/asm-powerpc/highmem.h135
-rw-r--r--include/asm-powerpc/hydra.h102
-rw-r--r--include/asm-powerpc/immap_cpm2.h648
-rw-r--r--include/asm-powerpc/kgdb.h57
-rw-r--r--include/asm-powerpc/mpc52xx_psc.h191
-rw-r--r--include/asm-ppc/ans-lcd.h11
9 files changed, 3637 insertions, 11 deletions
diff --git a/include/asm-powerpc/8xx_immap.h b/include/asm-powerpc/8xx_immap.h
new file mode 100644
index 000000000000..1311cefdfd30
--- /dev/null
+++ b/include/asm-powerpc/8xx_immap.h
@@ -0,0 +1,564 @@
1/*
2 * MPC8xx Internal Memory Map
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * The I/O on the MPC860 is comprised of blocks of special registers
6 * and the dual port ram for the Communication Processor Module.
7 * Within this space are functional units such as the SIU, memory
8 * controller, system timers, and other control functions. It is
9 * a combination that I found difficult to separate into logical
10 * functional files.....but anyone else is welcome to try. -- Dan
11 */
12#ifdef __KERNEL__
13#ifndef __IMMAP_8XX__
14#define __IMMAP_8XX__
15
16/* System configuration registers.
17*/
18typedef struct sys_conf {
19 uint sc_siumcr;
20 uint sc_sypcr;
21 uint sc_swt;
22 char res1[2];
23 ushort sc_swsr;
24 uint sc_sipend;
25 uint sc_simask;
26 uint sc_siel;
27 uint sc_sivec;
28 uint sc_tesr;
29 char res2[0xc];
30 uint sc_sdcr;
31 char res3[0x4c];
32} sysconf8xx_t;
33
34/* PCMCIA configuration registers.
35*/
36typedef struct pcmcia_conf {
37 uint pcmc_pbr0;
38 uint pcmc_por0;
39 uint pcmc_pbr1;
40 uint pcmc_por1;
41 uint pcmc_pbr2;
42 uint pcmc_por2;
43 uint pcmc_pbr3;
44 uint pcmc_por3;
45 uint pcmc_pbr4;
46 uint pcmc_por4;
47 uint pcmc_pbr5;
48 uint pcmc_por5;
49 uint pcmc_pbr6;
50 uint pcmc_por6;
51 uint pcmc_pbr7;
52 uint pcmc_por7;
53 char res1[0x20];
54 uint pcmc_pgcra;
55 uint pcmc_pgcrb;
56 uint pcmc_pscr;
57 char res2[4];
58 uint pcmc_pipr;
59 char res3[4];
60 uint pcmc_per;
61 char res4[4];
62} pcmconf8xx_t;
63
64/* Memory controller registers.
65*/
66typedef struct mem_ctlr {
67 uint memc_br0;
68 uint memc_or0;
69 uint memc_br1;
70 uint memc_or1;
71 uint memc_br2;
72 uint memc_or2;
73 uint memc_br3;
74 uint memc_or3;
75 uint memc_br4;
76 uint memc_or4;
77 uint memc_br5;
78 uint memc_or5;
79 uint memc_br6;
80 uint memc_or6;
81 uint memc_br7;
82 uint memc_or7;
83 char res1[0x24];
84 uint memc_mar;
85 uint memc_mcr;
86 char res2[4];
87 uint memc_mamr;
88 uint memc_mbmr;
89 ushort memc_mstat;
90 ushort memc_mptpr;
91 uint memc_mdr;
92 char res3[0x80];
93} memctl8xx_t;
94
95/*-----------------------------------------------------------------------
96 * BR - Memory Controler: Base Register 16-9
97 */
98#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99#define BR_AT_MSK 0x00007000 /* Address Type Mask */
100#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101#define BR_PS_32 0x00000000 /* 32 bit port size */
102#define BR_PS_16 0x00000800 /* 16 bit port size */
103#define BR_PS_8 0x00000400 /* 8 bit port size */
104#define BR_PARE 0x00000200 /* Parity Enable */
105#define BR_WP 0x00000100 /* Write Protect */
106#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
107#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
110#define BR_V 0x00000001 /* Bank Valid */
111
112/*-----------------------------------------------------------------------
113 * OR - Memory Controler: Option Register 16-11
114 */
115#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
116#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
117#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
118 /* Address Multiplex */
119#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
120#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
121#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
122#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
143#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
144#define OR_TRLX 0x00000004 /* Timing Relaxed */
145#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
146
147/* System Integration Timers.
148*/
149typedef struct sys_int_timers {
150 ushort sit_tbscr;
151 char res0[0x02];
152 uint sit_tbreff0;
153 uint sit_tbreff1;
154 char res1[0x14];
155 ushort sit_rtcsc;
156 char res2[0x02];
157 uint sit_rtc;
158 uint sit_rtsec;
159 uint sit_rtcal;
160 char res3[0x10];
161 ushort sit_piscr;
162 char res4[2];
163 uint sit_pitc;
164 uint sit_pitr;
165 char res5[0x34];
166} sit8xx_t;
167
168#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
169#define TBSCR_REFA ((ushort)0x0080)
170#define TBSCR_REFB ((ushort)0x0040)
171#define TBSCR_REFAE ((ushort)0x0008)
172#define TBSCR_REFBE ((ushort)0x0004)
173#define TBSCR_TBF ((ushort)0x0002)
174#define TBSCR_TBE ((ushort)0x0001)
175
176#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
177#define RTCSC_SEC ((ushort)0x0080)
178#define RTCSC_ALR ((ushort)0x0040)
179#define RTCSC_38K ((ushort)0x0010)
180#define RTCSC_SIE ((ushort)0x0008)
181#define RTCSC_ALE ((ushort)0x0004)
182#define RTCSC_RTF ((ushort)0x0002)
183#define RTCSC_RTE ((ushort)0x0001)
184
185#define PISCR_PIRQ_MASK ((ushort)0xff00)
186#define PISCR_PS ((ushort)0x0080)
187#define PISCR_PIE ((ushort)0x0004)
188#define PISCR_PTF ((ushort)0x0002)
189#define PISCR_PTE ((ushort)0x0001)
190
191/* Clocks and Reset.
192*/
193typedef struct clk_and_reset {
194 uint car_sccr;
195 uint car_plprcr;
196 uint car_rsr;
197 char res[0x74]; /* Reserved area */
198} car8xx_t;
199
200/* System Integration Timers keys.
201*/
202typedef struct sitk {
203 uint sitk_tbscrk;
204 uint sitk_tbreff0k;
205 uint sitk_tbreff1k;
206 uint sitk_tbk;
207 char res1[0x10];
208 uint sitk_rtcsck;
209 uint sitk_rtck;
210 uint sitk_rtseck;
211 uint sitk_rtcalk;
212 char res2[0x10];
213 uint sitk_piscrk;
214 uint sitk_pitck;
215 char res3[0x38];
216} sitk8xx_t;
217
218/* Clocks and reset keys.
219*/
220typedef struct cark {
221 uint cark_sccrk;
222 uint cark_plprcrk;
223 uint cark_rsrk;
224 char res[0x474];
225} cark8xx_t;
226
227/* The key to unlock registers maintained by keep-alive power.
228*/
229#define KAPWR_KEY ((unsigned int)0x55ccaa33)
230
231/* Video interface. MPC823 Only.
232*/
233typedef struct vid823 {
234 ushort vid_vccr;
235 ushort res1;
236 u_char vid_vsr;
237 u_char res2;
238 u_char vid_vcmr;
239 u_char res3;
240 uint vid_vbcb;
241 uint res4;
242 uint vid_vfcr0;
243 uint vid_vfaa0;
244 uint vid_vfba0;
245 uint vid_vfcr1;
246 uint vid_vfaa1;
247 uint vid_vfba1;
248 u_char res5[0x18];
249} vid823_t;
250
251/* LCD interface. 823 Only.
252*/
253typedef struct lcd {
254 uint lcd_lccr;
255 uint lcd_lchcr;
256 uint lcd_lcvcr;
257 char res1[4];
258 uint lcd_lcfaa;
259 uint lcd_lcfba;
260 char lcd_lcsr;
261 char res2[0x7];
262} lcd823_t;
263
264/* I2C
265*/
266typedef struct i2c {
267 u_char i2c_i2mod;
268 char res1[3];
269 u_char i2c_i2add;
270 char res2[3];
271 u_char i2c_i2brg;
272 char res3[3];
273 u_char i2c_i2com;
274 char res4[3];
275 u_char i2c_i2cer;
276 char res5[3];
277 u_char i2c_i2cmr;
278 char res6[0x8b];
279} i2c8xx_t;
280
281/* DMA control/status registers.
282*/
283typedef struct sdma_csr {
284 char res1[4];
285 uint sdma_sdar;
286 u_char sdma_sdsr;
287 char res3[3];
288 u_char sdma_sdmr;
289 char res4[3];
290 u_char sdma_idsr1;
291 char res5[3];
292 u_char sdma_idmr1;
293 char res6[3];
294 u_char sdma_idsr2;
295 char res7[3];
296 u_char sdma_idmr2;
297 char res8[0x13];
298} sdma8xx_t;
299
300/* Communication Processor Module Interrupt Controller.
301*/
302typedef struct cpm_ic {
303 ushort cpic_civr;
304 char res[0xe];
305 uint cpic_cicr;
306 uint cpic_cipr;
307 uint cpic_cimr;
308 uint cpic_cisr;
309} cpic8xx_t;
310
311/* Input/Output Port control/status registers.
312*/
313typedef struct io_port {
314 ushort iop_padir;
315 ushort iop_papar;
316 ushort iop_paodr;
317 ushort iop_padat;
318 char res1[8];
319 ushort iop_pcdir;
320 ushort iop_pcpar;
321 ushort iop_pcso;
322 ushort iop_pcdat;
323 ushort iop_pcint;
324 char res2[6];
325 ushort iop_pddir;
326 ushort iop_pdpar;
327 char res3[2];
328 ushort iop_pddat;
329 uint utmode;
330 char res4[4];
331} iop8xx_t;
332
333/* Communication Processor Module Timers
334*/
335typedef struct cpm_timers {
336 ushort cpmt_tgcr;
337 char res1[0xe];
338 ushort cpmt_tmr1;
339 ushort cpmt_tmr2;
340 ushort cpmt_trr1;
341 ushort cpmt_trr2;
342 ushort cpmt_tcr1;
343 ushort cpmt_tcr2;
344 ushort cpmt_tcn1;
345 ushort cpmt_tcn2;
346 ushort cpmt_tmr3;
347 ushort cpmt_tmr4;
348 ushort cpmt_trr3;
349 ushort cpmt_trr4;
350 ushort cpmt_tcr3;
351 ushort cpmt_tcr4;
352 ushort cpmt_tcn3;
353 ushort cpmt_tcn4;
354 ushort cpmt_ter1;
355 ushort cpmt_ter2;
356 ushort cpmt_ter3;
357 ushort cpmt_ter4;
358 char res2[8];
359} cpmtimer8xx_t;
360
361/* Finally, the Communication Processor stuff.....
362*/
363typedef struct scc { /* Serial communication channels */
364 uint scc_gsmrl;
365 uint scc_gsmrh;
366 ushort scc_psmr;
367 char res1[2];
368 ushort scc_todr;
369 ushort scc_dsr;
370 ushort scc_scce;
371 char res2[2];
372 ushort scc_sccm;
373 char res3;
374 u_char scc_sccs;
375 char res4[8];
376} scc_t;
377
378typedef struct smc { /* Serial management channels */
379 char res1[2];
380 ushort smc_smcmr;
381 char res2[2];
382 u_char smc_smce;
383 char res3[3];
384 u_char smc_smcm;
385 char res4[5];
386} smc_t;
387
388/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
389 * it fits within the address space.
390 */
391
392typedef struct fec {
393 uint fec_addr_low; /* lower 32 bits of station address */
394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */
396 uint fec_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */
401 uint res2[9]; /* reserved */
402 uint fec_ecntrl; /* ethernet control register */
403 uint fec_ievent; /* interrupt event register */
404 uint fec_imask; /* interrupt mask register */
405 uint fec_ivec; /* interrupt level and vector status */
406 uint fec_r_des_active; /* Rx ring updated flag */
407 uint fec_x_des_active; /* Tx ring updated flag */
408 uint res3[10]; /* reserved */
409 uint fec_mii_data; /* MII data register */
410 uint fec_mii_speed; /* MII speed control register */
411 uint res4[17]; /* reserved */
412 uint fec_r_bound; /* end of RAM (read-only) */
413 uint fec_r_fstart; /* Rx FIFO start address */
414 uint res5[6]; /* reserved */
415 uint fec_x_fstart; /* Tx FIFO start address */
416 uint res6[17]; /* reserved */
417 uint fec_fun_code; /* fec SDMA function code */
418 uint res7[3]; /* reserved */
419 uint fec_r_cntrl; /* Rx control register */
420 uint fec_r_hash; /* Rx hash register */
421 uint res8[14]; /* reserved */
422 uint fec_x_cntrl; /* Tx control register */
423 uint res9[0x1e]; /* reserved */
424} fec_t;
425
426/* The FEC and LCD color map share the same address space....
427 * I guess we will never see an 823T :-).
428 */
429union fec_lcd {
430 fec_t fl_un_fec;
431 u_char fl_un_cmap[0x200];
432};
433
434typedef struct comm_proc {
435 /* General control and status registers.
436 */
437 ushort cp_cpcr;
438 u_char res1[2];
439 ushort cp_rccr;
440 u_char res2;
441 u_char cp_rmds;
442 u_char res3[4];
443 ushort cp_cpmcr1;
444 ushort cp_cpmcr2;
445 ushort cp_cpmcr3;
446 ushort cp_cpmcr4;
447 u_char res4[2];
448 ushort cp_rter;
449 u_char res5[2];
450 ushort cp_rtmr;
451 u_char res6[0x14];
452
453 /* Baud rate generators.
454 */
455 uint cp_brgc1;
456 uint cp_brgc2;
457 uint cp_brgc3;
458 uint cp_brgc4;
459
460 /* Serial Communication Channels.
461 */
462 scc_t cp_scc[4];
463
464 /* Serial Management Channels.
465 */
466 smc_t cp_smc[2];
467
468 /* Serial Peripheral Interface.
469 */
470 ushort cp_spmode;
471 u_char res7[4];
472 u_char cp_spie;
473 u_char res8[3];
474 u_char cp_spim;
475 u_char res9[2];
476 u_char cp_spcom;
477 u_char res10[2];
478
479 /* Parallel Interface Port.
480 */
481 u_char res11[2];
482 ushort cp_pipc;
483 u_char res12[2];
484 ushort cp_ptpr;
485 uint cp_pbdir;
486 uint cp_pbpar;
487 u_char res13[2];
488 ushort cp_pbodr;
489 uint cp_pbdat;
490
491 /* Port E - MPC87x/88x only.
492 */
493 uint cp_pedir;
494 uint cp_pepar;
495 uint cp_peso;
496 uint cp_peodr;
497 uint cp_pedat;
498
499 /* Communications Processor Timing Register -
500 Contains RMII Timing for the FECs on MPC87x/88x only.
501 */
502 uint cp_cptr;
503
504 /* Serial Interface and Time Slot Assignment.
505 */
506 uint cp_simode;
507 u_char cp_sigmr;
508 u_char res15;
509 u_char cp_sistr;
510 u_char cp_sicmr;
511 u_char res16[4];
512 uint cp_sicr;
513 uint cp_sirp;
514 u_char res17[0xc];
515
516 /* 256 bytes of MPC823 video controller RAM array.
517 */
518 u_char cp_vcram[0x100];
519 u_char cp_siram[0x200];
520
521 /* The fast ethernet controller is not really part of the CPM,
522 * but it resides in the address space.
523 * The LCD color map is also here.
524 */
525 union fec_lcd fl_un;
526#define cp_fec fl_un.fl_un_fec
527#define lcd_cmap fl_un.fl_un_cmap
528 char res18[0xE00];
529
530 /* The DUET family has a second FEC here */
531 fec_t cp_fec2;
532#define cp_fec1 cp_fec /* consistency macro */
533
534 /* Dual Ported RAM follows.
535 * There are many different formats for this memory area
536 * depending upon the devices used and options chosen.
537 * Some processors don't have all of it populated.
538 */
539 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
540 u_char cp_dparam[0x400]; /* Parameter RAM */
541} cpm8xx_t;
542
543/* Internal memory map.
544*/
545typedef struct immap {
546 sysconf8xx_t im_siu_conf; /* SIU Configuration */
547 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
548 memctl8xx_t im_memctl; /* Memory Controller */
549 sit8xx_t im_sit; /* System integration timers */
550 car8xx_t im_clkrst; /* Clocks and reset */
551 sitk8xx_t im_sitk; /* Sys int timer keys */
552 cark8xx_t im_clkrstk; /* Clocks and reset keys */
553 vid823_t im_vid; /* Video (823 only) */
554 lcd823_t im_lcd; /* LCD (823 only) */
555 i2c8xx_t im_i2c; /* I2C control/status */
556 sdma8xx_t im_sdma; /* SDMA control/status */
557 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
558 iop8xx_t im_ioport; /* IO Port control/status */
559 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
560 cpm8xx_t im_cpm; /* Communication processor */
561} immap_t;
562
563#endif /* __IMMAP_8XX__ */
564#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/commproc.h
new file mode 100644
index 000000000000..397248705e0e
--- /dev/null
+++ b/include/asm-powerpc/commproc.h
@@ -0,0 +1,692 @@
1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
10 * are needed. -- Dan
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM_8XX__
18#define __CPM_8XX__
19
20#include <asm/8xx_immap.h>
21#include <asm/ptrace.h>
22
23/* CPM Command register.
24*/
25#define CPM_CR_RST ((ushort)0x8000)
26#define CPM_CR_OPCODE ((ushort)0x0f00)
27#define CPM_CR_CHAN ((ushort)0x00f0)
28#define CPM_CR_FLG ((ushort)0x0001)
29
30/* Some commands (there are more...later)
31*/
32#define CPM_CR_INIT_TRX ((ushort)0x0000)
33#define CPM_CR_INIT_RX ((ushort)0x0001)
34#define CPM_CR_INIT_TX ((ushort)0x0002)
35#define CPM_CR_HUNT_MODE ((ushort)0x0003)
36#define CPM_CR_STOP_TX ((ushort)0x0004)
37#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
38#define CPM_CR_RESTART_TX ((ushort)0x0006)
39#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
40#define CPM_CR_SET_GADDR ((ushort)0x0008)
41#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
42
43/* Channel numbers.
44*/
45#define CPM_CR_CH_SCC1 ((ushort)0x0000)
46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
47#define CPM_CR_CH_SCC2 ((ushort)0x0004)
48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
49#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
50#define CPM_CR_CH_SCC3 ((ushort)0x0008)
51#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
52#define CPM_CR_CH_SCC4 ((ushort)0x000c)
53#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
54
55#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
56
57/* The dual ported RAM is multi-functional. Some areas can be (and are
58 * being) used for microcode. There is an area that can only be used
59 * as data ram for buffer descriptors, which is all we use right now.
60 * Currently the first 512 and last 256 bytes are used for microcode.
61 */
62#define CPM_DATAONLY_BASE ((uint)0x0800)
63#define CPM_DATAONLY_SIZE ((uint)0x0700)
64#define CPM_DP_NOSPACE ((uint)0x7fffffff)
65
66/* Export the base address of the communication processor registers
67 * and dual port ram.
68 */
69extern cpm8xx_t *cpmp; /* Pointer to comm processor */
70extern unsigned long cpm_dpalloc(uint size, uint align);
71extern int cpm_dpfree(unsigned long offset);
72extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
73extern void cpm_dpdump(void);
74extern void *cpm_dpram_addr(unsigned long offset);
75extern uint cpm_dpram_phys(u8* addr);
76extern void cpm_setbrg(uint brg, uint rate);
77
78extern uint m8xx_cpm_hostalloc(uint size);
79extern int m8xx_cpm_hostfree(uint start);
80extern void m8xx_cpm_hostdump(void);
81
82extern void cpm_load_patch(volatile immap_t *immr);
83
84/* Buffer descriptors used by many of the CPM protocols.
85*/
86typedef struct cpm_buf_desc {
87 ushort cbd_sc; /* Status and Control */
88 ushort cbd_datlen; /* Data length in buffer */
89 uint cbd_bufaddr; /* Buffer address in host memory */
90} cbd_t;
91
92#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
93#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
94#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
95#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
96#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
97#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
98#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
99#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
100#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
101#define BD_SC_BR ((ushort)0x0020) /* Break received */
102#define BD_SC_FR ((ushort)0x0010) /* Framing error */
103#define BD_SC_PR ((ushort)0x0008) /* Parity error */
104#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
105#define BD_SC_OV ((ushort)0x0002) /* Overrun */
106#define BD_SC_UN ((ushort)0x0002) /* Underrun */
107#define BD_SC_CD ((ushort)0x0001) /* ?? */
108#define BD_SC_CL ((ushort)0x0001) /* Collision */
109
110/* Parameter RAM offsets.
111*/
112#define PROFF_SCC1 ((uint)0x0000)
113#define PROFF_IIC ((uint)0x0080)
114#define PROFF_SCC2 ((uint)0x0100)
115#define PROFF_SPI ((uint)0x0180)
116#define PROFF_SCC3 ((uint)0x0200)
117#define PROFF_SMC1 ((uint)0x0280)
118#define PROFF_SCC4 ((uint)0x0300)
119#define PROFF_SMC2 ((uint)0x0380)
120
121/* Define enough so I can at least use the serial port as a UART.
122 * The MBX uses SMC1 as the host serial port.
123 */
124typedef struct smc_uart {
125 ushort smc_rbase; /* Rx Buffer descriptor base address */
126 ushort smc_tbase; /* Tx Buffer descriptor base address */
127 u_char smc_rfcr; /* Rx function code */
128 u_char smc_tfcr; /* Tx function code */
129 ushort smc_mrblr; /* Max receive buffer length */
130 uint smc_rstate; /* Internal */
131 uint smc_idp; /* Internal */
132 ushort smc_rbptr; /* Internal */
133 ushort smc_ibc; /* Internal */
134 uint smc_rxtmp; /* Internal */
135 uint smc_tstate; /* Internal */
136 uint smc_tdp; /* Internal */
137 ushort smc_tbptr; /* Internal */
138 ushort smc_tbc; /* Internal */
139 uint smc_txtmp; /* Internal */
140 ushort smc_maxidl; /* Maximum idle characters */
141 ushort smc_tmpidl; /* Temporary idle counter */
142 ushort smc_brklen; /* Last received break length */
143 ushort smc_brkec; /* rcv'd break condition counter */
144 ushort smc_brkcr; /* xmt break count register */
145 ushort smc_rmask; /* Temporary bit mask */
146 char res1[8]; /* Reserved */
147 ushort smc_rpbase; /* Relocation pointer */
148} smc_uart_t;
149
150/* Function code bits.
151*/
152#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
153
154/* SMC uart mode register.
155*/
156#define SMCMR_REN ((ushort)0x0001)
157#define SMCMR_TEN ((ushort)0x0002)
158#define SMCMR_DM ((ushort)0x000c)
159#define SMCMR_SM_GCI ((ushort)0x0000)
160#define SMCMR_SM_UART ((ushort)0x0020)
161#define SMCMR_SM_TRANS ((ushort)0x0030)
162#define SMCMR_SM_MASK ((ushort)0x0030)
163#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
164#define SMCMR_REVD SMCMR_PM_EVEN
165#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
166#define SMCMR_BS SMCMR_PEN
167#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
168#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
169#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
170
171/* SMC2 as Centronics parallel printer. It is half duplex, in that
172 * it can only receive or transmit. The parameter ram values for
173 * each direction are either unique or properly overlap, so we can
174 * include them in one structure.
175 */
176typedef struct smc_centronics {
177 ushort scent_rbase;
178 ushort scent_tbase;
179 u_char scent_cfcr;
180 u_char scent_smask;
181 ushort scent_mrblr;
182 uint scent_rstate;
183 uint scent_r_ptr;
184 ushort scent_rbptr;
185 ushort scent_r_cnt;
186 uint scent_rtemp;
187 uint scent_tstate;
188 uint scent_t_ptr;
189 ushort scent_tbptr;
190 ushort scent_t_cnt;
191 uint scent_ttemp;
192 ushort scent_max_sl;
193 ushort scent_sl_cnt;
194 ushort scent_character1;
195 ushort scent_character2;
196 ushort scent_character3;
197 ushort scent_character4;
198 ushort scent_character5;
199 ushort scent_character6;
200 ushort scent_character7;
201 ushort scent_character8;
202 ushort scent_rccm;
203 ushort scent_rccr;
204} smc_cent_t;
205
206/* Centronics Status Mask Register.
207*/
208#define SMC_CENT_F ((u_char)0x08)
209#define SMC_CENT_PE ((u_char)0x04)
210#define SMC_CENT_S ((u_char)0x02)
211
212/* SMC Event and Mask register.
213*/
214#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
215#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
216#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
217#define SMCM_BSY ((unsigned char)0x04)
218#define SMCM_TX ((unsigned char)0x02)
219#define SMCM_RX ((unsigned char)0x01)
220
221/* Baud rate generators.
222*/
223#define CPM_BRG_RST ((uint)0x00020000)
224#define CPM_BRG_EN ((uint)0x00010000)
225#define CPM_BRG_EXTC_INT ((uint)0x00000000)
226#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
227#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
228#define CPM_BRG_ATB ((uint)0x00002000)
229#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
230#define CPM_BRG_DIV16 ((uint)0x00000001)
231
232/* SI Clock Route Register
233*/
234#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
235#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
236#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
237#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
238#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
239#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
240#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
241#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
242
243/* SCCs.
244*/
245#define SCC_GSMRH_IRP ((uint)0x00040000)
246#define SCC_GSMRH_GDE ((uint)0x00010000)
247#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
248#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
249#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
250#define SCC_GSMRH_REVD ((uint)0x00002000)
251#define SCC_GSMRH_TRX ((uint)0x00001000)
252#define SCC_GSMRH_TTX ((uint)0x00000800)
253#define SCC_GSMRH_CDP ((uint)0x00000400)
254#define SCC_GSMRH_CTSP ((uint)0x00000200)
255#define SCC_GSMRH_CDS ((uint)0x00000100)
256#define SCC_GSMRH_CTSS ((uint)0x00000080)
257#define SCC_GSMRH_TFL ((uint)0x00000040)
258#define SCC_GSMRH_RFW ((uint)0x00000020)
259#define SCC_GSMRH_TXSY ((uint)0x00000010)
260#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
261#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
262#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
263#define SCC_GSMRH_RTSM ((uint)0x00000002)
264#define SCC_GSMRH_RSYN ((uint)0x00000001)
265
266#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
267#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
268#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
269#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
270#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
271#define SCC_GSMRL_TCI ((uint)0x10000000)
272#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
273#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
274#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
275#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
276#define SCC_GSMRL_RINV ((uint)0x02000000)
277#define SCC_GSMRL_TINV ((uint)0x01000000)
278#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
279#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
280#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
281#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
282#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
283#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
284#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
285#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
286#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
287#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
288#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
289#define SCC_GSMRL_TEND ((uint)0x00040000)
290#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
291#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
292#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
293#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
294#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
295#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
296#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
297#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
298#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
299#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
300#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
301#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
302#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
303#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
304#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
305#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
306#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
307#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
308#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
309#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
310#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
311#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
312#define SCC_GSMRL_ENR ((uint)0x00000020)
313#define SCC_GSMRL_ENT ((uint)0x00000010)
314#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
315#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
316#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
317#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
318#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
319#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
320#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
321#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
322#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
323#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
324#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
325
326#define SCC_TODR_TOD ((ushort)0x8000)
327
328/* SCC Event and Mask register.
329*/
330#define SCCM_TXE ((unsigned char)0x10)
331#define SCCM_BSY ((unsigned char)0x04)
332#define SCCM_TX ((unsigned char)0x02)
333#define SCCM_RX ((unsigned char)0x01)
334
335typedef struct scc_param {
336 ushort scc_rbase; /* Rx Buffer descriptor base address */
337 ushort scc_tbase; /* Tx Buffer descriptor base address */
338 u_char scc_rfcr; /* Rx function code */
339 u_char scc_tfcr; /* Tx function code */
340 ushort scc_mrblr; /* Max receive buffer length */
341 uint scc_rstate; /* Internal */
342 uint scc_idp; /* Internal */
343 ushort scc_rbptr; /* Internal */
344 ushort scc_ibc; /* Internal */
345 uint scc_rxtmp; /* Internal */
346 uint scc_tstate; /* Internal */
347 uint scc_tdp; /* Internal */
348 ushort scc_tbptr; /* Internal */
349 ushort scc_tbc; /* Internal */
350 uint scc_txtmp; /* Internal */
351 uint scc_rcrc; /* Internal */
352 uint scc_tcrc; /* Internal */
353} sccp_t;
354
355/* Function code bits.
356*/
357#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
358
359/* CPM Ethernet through SCCx.
360 */
361typedef struct scc_enet {
362 sccp_t sen_genscc;
363 uint sen_cpres; /* Preset CRC */
364 uint sen_cmask; /* Constant mask for CRC */
365 uint sen_crcec; /* CRC Error counter */
366 uint sen_alec; /* alignment error counter */
367 uint sen_disfc; /* discard frame counter */
368 ushort sen_pads; /* Tx short frame pad character */
369 ushort sen_retlim; /* Retry limit threshold */
370 ushort sen_retcnt; /* Retry limit counter */
371 ushort sen_maxflr; /* maximum frame length register */
372 ushort sen_minflr; /* minimum frame length register */
373 ushort sen_maxd1; /* maximum DMA1 length */
374 ushort sen_maxd2; /* maximum DMA2 length */
375 ushort sen_maxd; /* Rx max DMA */
376 ushort sen_dmacnt; /* Rx DMA counter */
377 ushort sen_maxb; /* Max BD byte count */
378 ushort sen_gaddr1; /* Group address filter */
379 ushort sen_gaddr2;
380 ushort sen_gaddr3;
381 ushort sen_gaddr4;
382 uint sen_tbuf0data0; /* Save area 0 - current frame */
383 uint sen_tbuf0data1; /* Save area 1 - current frame */
384 uint sen_tbuf0rba; /* Internal */
385 uint sen_tbuf0crc; /* Internal */
386 ushort sen_tbuf0bcnt; /* Internal */
387 ushort sen_paddrh; /* physical address (MSB) */
388 ushort sen_paddrm;
389 ushort sen_paddrl; /* physical address (LSB) */
390 ushort sen_pper; /* persistence */
391 ushort sen_rfbdptr; /* Rx first BD pointer */
392 ushort sen_tfbdptr; /* Tx first BD pointer */
393 ushort sen_tlbdptr; /* Tx last BD pointer */
394 uint sen_tbuf1data0; /* Save area 0 - current frame */
395 uint sen_tbuf1data1; /* Save area 1 - current frame */
396 uint sen_tbuf1rba; /* Internal */
397 uint sen_tbuf1crc; /* Internal */
398 ushort sen_tbuf1bcnt; /* Internal */
399 ushort sen_txlen; /* Tx Frame length counter */
400 ushort sen_iaddr1; /* Individual address filter */
401 ushort sen_iaddr2;
402 ushort sen_iaddr3;
403 ushort sen_iaddr4;
404 ushort sen_boffcnt; /* Backoff counter */
405
406 /* NOTE: Some versions of the manual have the following items
407 * incorrectly documented. Below is the proper order.
408 */
409 ushort sen_taddrh; /* temp address (MSB) */
410 ushort sen_taddrm;
411 ushort sen_taddrl; /* temp address (LSB) */
412} scc_enet_t;
413
414/* SCC Event register as used by Ethernet.
415*/
416#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
417#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
418#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
419#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
420#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
421#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
422
423/* SCC Mode Register (PMSR) as used by Ethernet.
424*/
425#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
426#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
427#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
428#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
429#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
430#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
431#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
432#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
433#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
434#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
435#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
436#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
437#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
438
439/* Buffer descriptor control/status used by Ethernet receive.
440*/
441#define BD_ENET_RX_EMPTY ((ushort)0x8000)
442#define BD_ENET_RX_WRAP ((ushort)0x2000)
443#define BD_ENET_RX_INTR ((ushort)0x1000)
444#define BD_ENET_RX_LAST ((ushort)0x0800)
445#define BD_ENET_RX_FIRST ((ushort)0x0400)
446#define BD_ENET_RX_MISS ((ushort)0x0100)
447#define BD_ENET_RX_LG ((ushort)0x0020)
448#define BD_ENET_RX_NO ((ushort)0x0010)
449#define BD_ENET_RX_SH ((ushort)0x0008)
450#define BD_ENET_RX_CR ((ushort)0x0004)
451#define BD_ENET_RX_OV ((ushort)0x0002)
452#define BD_ENET_RX_CL ((ushort)0x0001)
453#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
454#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
455#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
456
457/* Buffer descriptor control/status used by Ethernet transmit.
458*/
459#define BD_ENET_TX_READY ((ushort)0x8000)
460#define BD_ENET_TX_PAD ((ushort)0x4000)
461#define BD_ENET_TX_WRAP ((ushort)0x2000)
462#define BD_ENET_TX_INTR ((ushort)0x1000)
463#define BD_ENET_TX_LAST ((ushort)0x0800)
464#define BD_ENET_TX_TC ((ushort)0x0400)
465#define BD_ENET_TX_DEF ((ushort)0x0200)
466#define BD_ENET_TX_HB ((ushort)0x0100)
467#define BD_ENET_TX_LC ((ushort)0x0080)
468#define BD_ENET_TX_RL ((ushort)0x0040)
469#define BD_ENET_TX_RCMASK ((ushort)0x003c)
470#define BD_ENET_TX_UN ((ushort)0x0002)
471#define BD_ENET_TX_CSL ((ushort)0x0001)
472#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
473
474/* SCC as UART
475*/
476typedef struct scc_uart {
477 sccp_t scc_genscc;
478 char res1[8]; /* Reserved */
479 ushort scc_maxidl; /* Maximum idle chars */
480 ushort scc_idlc; /* temp idle counter */
481 ushort scc_brkcr; /* Break count register */
482 ushort scc_parec; /* receive parity error counter */
483 ushort scc_frmec; /* receive framing error counter */
484 ushort scc_nosec; /* receive noise counter */
485 ushort scc_brkec; /* receive break condition counter */
486 ushort scc_brkln; /* last received break length */
487 ushort scc_uaddr1; /* UART address character 1 */
488 ushort scc_uaddr2; /* UART address character 2 */
489 ushort scc_rtemp; /* Temp storage */
490 ushort scc_toseq; /* Transmit out of sequence char */
491 ushort scc_char1; /* control character 1 */
492 ushort scc_char2; /* control character 2 */
493 ushort scc_char3; /* control character 3 */
494 ushort scc_char4; /* control character 4 */
495 ushort scc_char5; /* control character 5 */
496 ushort scc_char6; /* control character 6 */
497 ushort scc_char7; /* control character 7 */
498 ushort scc_char8; /* control character 8 */
499 ushort scc_rccm; /* receive control character mask */
500 ushort scc_rccr; /* receive control character register */
501 ushort scc_rlbc; /* receive last break character */
502} scc_uart_t;
503
504/* SCC Event and Mask registers when it is used as a UART.
505*/
506#define UART_SCCM_GLR ((ushort)0x1000)
507#define UART_SCCM_GLT ((ushort)0x0800)
508#define UART_SCCM_AB ((ushort)0x0200)
509#define UART_SCCM_IDL ((ushort)0x0100)
510#define UART_SCCM_GRA ((ushort)0x0080)
511#define UART_SCCM_BRKE ((ushort)0x0040)
512#define UART_SCCM_BRKS ((ushort)0x0020)
513#define UART_SCCM_CCR ((ushort)0x0008)
514#define UART_SCCM_BSY ((ushort)0x0004)
515#define UART_SCCM_TX ((ushort)0x0002)
516#define UART_SCCM_RX ((ushort)0x0001)
517
518/* The SCC PMSR when used as a UART.
519*/
520#define SCU_PSMR_FLC ((ushort)0x8000)
521#define SCU_PSMR_SL ((ushort)0x4000)
522#define SCU_PSMR_CL ((ushort)0x3000)
523#define SCU_PSMR_UM ((ushort)0x0c00)
524#define SCU_PSMR_FRZ ((ushort)0x0200)
525#define SCU_PSMR_RZS ((ushort)0x0100)
526#define SCU_PSMR_SYN ((ushort)0x0080)
527#define SCU_PSMR_DRT ((ushort)0x0040)
528#define SCU_PSMR_PEN ((ushort)0x0010)
529#define SCU_PSMR_RPM ((ushort)0x000c)
530#define SCU_PSMR_REVP ((ushort)0x0008)
531#define SCU_PSMR_TPM ((ushort)0x0003)
532#define SCU_PSMR_TEVP ((ushort)0x0002)
533
534/* CPM Transparent mode SCC.
535 */
536typedef struct scc_trans {
537 sccp_t st_genscc;
538 uint st_cpres; /* Preset CRC */
539 uint st_cmask; /* Constant mask for CRC */
540} scc_trans_t;
541
542#define BD_SCC_TX_LAST ((ushort)0x0800)
543
544/* IIC parameter RAM.
545*/
546typedef struct iic {
547 ushort iic_rbase; /* Rx Buffer descriptor base address */
548 ushort iic_tbase; /* Tx Buffer descriptor base address */
549 u_char iic_rfcr; /* Rx function code */
550 u_char iic_tfcr; /* Tx function code */
551 ushort iic_mrblr; /* Max receive buffer length */
552 uint iic_rstate; /* Internal */
553 uint iic_rdp; /* Internal */
554 ushort iic_rbptr; /* Internal */
555 ushort iic_rbc; /* Internal */
556 uint iic_rxtmp; /* Internal */
557 uint iic_tstate; /* Internal */
558 uint iic_tdp; /* Internal */
559 ushort iic_tbptr; /* Internal */
560 ushort iic_tbc; /* Internal */
561 uint iic_txtmp; /* Internal */
562 char res1[4]; /* Reserved */
563 ushort iic_rpbase; /* Relocation pointer */
564 char res2[2]; /* Reserved */
565} iic_t;
566
567#define BD_IIC_START ((ushort)0x0400)
568
569/* SPI parameter RAM.
570*/
571typedef struct spi {
572 ushort spi_rbase; /* Rx Buffer descriptor base address */
573 ushort spi_tbase; /* Tx Buffer descriptor base address */
574 u_char spi_rfcr; /* Rx function code */
575 u_char spi_tfcr; /* Tx function code */
576 ushort spi_mrblr; /* Max receive buffer length */
577 uint spi_rstate; /* Internal */
578 uint spi_rdp; /* Internal */
579 ushort spi_rbptr; /* Internal */
580 ushort spi_rbc; /* Internal */
581 uint spi_rxtmp; /* Internal */
582 uint spi_tstate; /* Internal */
583 uint spi_tdp; /* Internal */
584 ushort spi_tbptr; /* Internal */
585 ushort spi_tbc; /* Internal */
586 uint spi_txtmp; /* Internal */
587 uint spi_res;
588 ushort spi_rpbase; /* Relocation pointer */
589 ushort spi_res2;
590} spi_t;
591
592/* SPI Mode register.
593*/
594#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
595#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
596#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
597#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
598#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
599#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
600#define SPMODE_EN ((ushort)0x0100) /* Enable */
601#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
602#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
603#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
604#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
605#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
606
607/* SPIE fields */
608#define SPIE_MME 0x20
609#define SPIE_TXE 0x10
610#define SPIE_BSY 0x04
611#define SPIE_TXB 0x02
612#define SPIE_RXB 0x01
613
614/*
615 * RISC Controller Configuration Register definitons
616 */
617#define RCCR_TIME 0x8000 /* RISC Timer Enable */
618#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
619#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
620
621/* RISC Timer Parameter RAM offset */
622#define PROFF_RTMR ((uint)0x01B0)
623
624typedef struct risc_timer_pram {
625 unsigned short tm_base; /* RISC Timer Table Base Address */
626 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
627 unsigned short r_tmr; /* RISC Timer Mode Register */
628 unsigned short r_tmv; /* RISC Timer Valid Register */
629 unsigned long tm_cmd; /* RISC Timer Command Register */
630 unsigned long tm_cnt; /* RISC Timer Internal Count */
631} rt_pram_t;
632
633/* Bits in RISC Timer Command Register */
634#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
635#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
636#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
637#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
638#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
639
640/* CPM interrupts. There are nearly 32 interrupts generated by CPM
641 * channels or devices. All of these are presented to the PPC core
642 * as a single interrupt. The CPM interrupt handler dispatches its
643 * own handlers, in a similar fashion to the PPC core handler. We
644 * use the table as defined in the manuals (i.e. no special high
645 * priority and SCC1 == SCCa, etc...).
646 */
647#define CPMVEC_NR 32
648#define CPMVEC_PIO_PC15 ((ushort)0x1f)
649#define CPMVEC_SCC1 ((ushort)0x1e)
650#define CPMVEC_SCC2 ((ushort)0x1d)
651#define CPMVEC_SCC3 ((ushort)0x1c)
652#define CPMVEC_SCC4 ((ushort)0x1b)
653#define CPMVEC_PIO_PC14 ((ushort)0x1a)
654#define CPMVEC_TIMER1 ((ushort)0x19)
655#define CPMVEC_PIO_PC13 ((ushort)0x18)
656#define CPMVEC_PIO_PC12 ((ushort)0x17)
657#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
658#define CPMVEC_IDMA1 ((ushort)0x15)
659#define CPMVEC_IDMA2 ((ushort)0x14)
660#define CPMVEC_TIMER2 ((ushort)0x12)
661#define CPMVEC_RISCTIMER ((ushort)0x11)
662#define CPMVEC_I2C ((ushort)0x10)
663#define CPMVEC_PIO_PC11 ((ushort)0x0f)
664#define CPMVEC_PIO_PC10 ((ushort)0x0e)
665#define CPMVEC_TIMER3 ((ushort)0x0c)
666#define CPMVEC_PIO_PC9 ((ushort)0x0b)
667#define CPMVEC_PIO_PC8 ((ushort)0x0a)
668#define CPMVEC_PIO_PC7 ((ushort)0x09)
669#define CPMVEC_TIMER4 ((ushort)0x07)
670#define CPMVEC_PIO_PC6 ((ushort)0x06)
671#define CPMVEC_SPI ((ushort)0x05)
672#define CPMVEC_SMC1 ((ushort)0x04)
673#define CPMVEC_SMC2 ((ushort)0x03)
674#define CPMVEC_PIO_PC5 ((ushort)0x02)
675#define CPMVEC_PIO_PC4 ((ushort)0x01)
676#define CPMVEC_ERROR ((ushort)0x00)
677
678/* CPM interrupt configuration vector.
679*/
680#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
681#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
682#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
683#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
684#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
685#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
686#define CICR_IEN ((uint)0x00000080) /* Int. enable */
687#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
688
689extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
690extern void cpm_free_handler(int vec);
691
692#endif /* __CPM_8XX__ */
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
new file mode 100644
index 000000000000..12a2860f9a9c
--- /dev/null
+++ b/include/asm-powerpc/cpm2.h
@@ -0,0 +1,1248 @@
1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
14
15/* CPM Command register.
16*/
17#define CPM_CR_RST ((uint)0x80000000)
18#define CPM_CR_PAGE ((uint)0x7c000000)
19#define CPM_CR_SBLOCK ((uint)0x03e00000)
20#define CPM_CR_FLG ((uint)0x00010000)
21#define CPM_CR_MCN ((uint)0x00003fc0)
22#define CPM_CR_OPCODE ((uint)0x0000000f)
23
24/* Device sub-block and page codes.
25*/
26#define CPM_CR_SCC1_SBLOCK (0x04)
27#define CPM_CR_SCC2_SBLOCK (0x05)
28#define CPM_CR_SCC3_SBLOCK (0x06)
29#define CPM_CR_SCC4_SBLOCK (0x07)
30#define CPM_CR_SMC1_SBLOCK (0x08)
31#define CPM_CR_SMC2_SBLOCK (0x09)
32#define CPM_CR_SPI_SBLOCK (0x0a)
33#define CPM_CR_I2C_SBLOCK (0x0b)
34#define CPM_CR_TIMER_SBLOCK (0x0f)
35#define CPM_CR_RAND_SBLOCK (0x0e)
36#define CPM_CR_FCC1_SBLOCK (0x10)
37#define CPM_CR_FCC2_SBLOCK (0x11)
38#define CPM_CR_FCC3_SBLOCK (0x12)
39#define CPM_CR_IDMA1_SBLOCK (0x14)
40#define CPM_CR_IDMA2_SBLOCK (0x15)
41#define CPM_CR_IDMA3_SBLOCK (0x16)
42#define CPM_CR_IDMA4_SBLOCK (0x17)
43#define CPM_CR_MCC1_SBLOCK (0x1c)
44
45#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
46
47#define CPM_CR_SCC1_PAGE (0x00)
48#define CPM_CR_SCC2_PAGE (0x01)
49#define CPM_CR_SCC3_PAGE (0x02)
50#define CPM_CR_SCC4_PAGE (0x03)
51#define CPM_CR_SMC1_PAGE (0x07)
52#define CPM_CR_SMC2_PAGE (0x08)
53#define CPM_CR_SPI_PAGE (0x09)
54#define CPM_CR_I2C_PAGE (0x0a)
55#define CPM_CR_TIMER_PAGE (0x0a)
56#define CPM_CR_RAND_PAGE (0x0a)
57#define CPM_CR_FCC1_PAGE (0x04)
58#define CPM_CR_FCC2_PAGE (0x05)
59#define CPM_CR_FCC3_PAGE (0x06)
60#define CPM_CR_IDMA1_PAGE (0x07)
61#define CPM_CR_IDMA2_PAGE (0x08)
62#define CPM_CR_IDMA3_PAGE (0x09)
63#define CPM_CR_IDMA4_PAGE (0x0a)
64#define CPM_CR_MCC1_PAGE (0x07)
65#define CPM_CR_MCC2_PAGE (0x08)
66
67#define CPM_CR_FCC_PAGE(x) (x + 0x04)
68
69/* Some opcodes (there are more...later)
70*/
71#define CPM_CR_INIT_TRX ((ushort)0x0000)
72#define CPM_CR_INIT_RX ((ushort)0x0001)
73#define CPM_CR_INIT_TX ((ushort)0x0002)
74#define CPM_CR_HUNT_MODE ((ushort)0x0003)
75#define CPM_CR_STOP_TX ((ushort)0x0004)
76#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
77#define CPM_CR_RESTART_TX ((ushort)0x0006)
78#define CPM_CR_SET_GADDR ((ushort)0x0008)
79#define CPM_CR_START_IDMA ((ushort)0x0009)
80#define CPM_CR_STOP_IDMA ((ushort)0x000b)
81
82#define mk_cr_cmd(PG, SBC, MCN, OP) \
83 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
84
85/* Dual Port RAM addresses. The first 16K is available for almost
86 * any CPM use, so we put the BDs there. The first 128 bytes are
87 * used for SMC1 and SMC2 parameter RAM, so we start allocating
88 * BDs above that. All of this must change when we start
89 * downloading RAM microcode.
90 */
91#define CPM_DATAONLY_BASE ((uint)128)
92#define CPM_DP_NOSPACE ((uint)0x7fffffff)
93#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
94#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
95#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
96#else
97#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
98#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
99#endif
100
101/* The number of pages of host memory we allocate for CPM. This is
102 * done early in kernel initialization to get physically contiguous
103 * pages.
104 */
105#define NUM_CPM_HOST_PAGES 2
106
107/* Export the base address of the communication processor registers
108 * and dual port ram.
109 */
110extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */
111
112extern unsigned long cpm_dpalloc(uint size, uint align);
113extern int cpm_dpfree(unsigned long offset);
114extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
115extern void cpm_dpdump(void);
116extern void *cpm_dpram_addr(unsigned long offset);
117extern void cpm_setbrg(uint brg, uint rate);
118extern void cpm2_fastbrg(uint brg, uint rate, int div16);
119extern void cpm2_reset(void);
120
121
122/* Buffer descriptors used by many of the CPM protocols.
123*/
124typedef struct cpm_buf_desc {
125 ushort cbd_sc; /* Status and Control */
126 ushort cbd_datlen; /* Data length in buffer */
127 uint cbd_bufaddr; /* Buffer address in host memory */
128} cbd_t;
129
130#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
131#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
132#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
133#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
134#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
135#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
136#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
137#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
138#define BD_SC_BR ((ushort)0x0020) /* Break received */
139#define BD_SC_FR ((ushort)0x0010) /* Framing error */
140#define BD_SC_PR ((ushort)0x0008) /* Parity error */
141#define BD_SC_OV ((ushort)0x0002) /* Overrun */
142#define BD_SC_CD ((ushort)0x0001) /* ?? */
143
144/* Function code bits, usually generic to devices.
145*/
146#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
147#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
148#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
149#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
150#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
151
152/* Parameter RAM offsets from the base.
153*/
154#define PROFF_SCC1 ((uint)0x8000)
155#define PROFF_SCC2 ((uint)0x8100)
156#define PROFF_SCC3 ((uint)0x8200)
157#define PROFF_SCC4 ((uint)0x8300)
158#define PROFF_FCC1 ((uint)0x8400)
159#define PROFF_FCC2 ((uint)0x8500)
160#define PROFF_FCC3 ((uint)0x8600)
161#define PROFF_MCC1 ((uint)0x8700)
162#define PROFF_SMC1_BASE ((uint)0x87fc)
163#define PROFF_IDMA1_BASE ((uint)0x87fe)
164#define PROFF_MCC2 ((uint)0x8800)
165#define PROFF_SMC2_BASE ((uint)0x88fc)
166#define PROFF_IDMA2_BASE ((uint)0x88fe)
167#define PROFF_SPI_BASE ((uint)0x89fc)
168#define PROFF_IDMA3_BASE ((uint)0x89fe)
169#define PROFF_TIMERS ((uint)0x8ae0)
170#define PROFF_REVNUM ((uint)0x8af0)
171#define PROFF_RAND ((uint)0x8af8)
172#define PROFF_I2C_BASE ((uint)0x8afc)
173#define PROFF_IDMA4_BASE ((uint)0x8afe)
174
175#define PROFF_SCC_SIZE ((uint)0x100)
176#define PROFF_FCC_SIZE ((uint)0x100)
177#define PROFF_SMC_SIZE ((uint)64)
178
179/* The SMCs are relocated to any of the first eight DPRAM pages.
180 * We will fix these at the first locations of DPRAM, until we
181 * get some microcode patches :-).
182 * The parameter ram space for the SMCs is fifty-some bytes, and
183 * they are required to start on a 64 byte boundary.
184 */
185#define PROFF_SMC1 (0)
186#define PROFF_SMC2 (64)
187
188
189/* Define enough so I can at least use the serial port as a UART.
190 */
191typedef struct smc_uart {
192 ushort smc_rbase; /* Rx Buffer descriptor base address */
193 ushort smc_tbase; /* Tx Buffer descriptor base address */
194 u_char smc_rfcr; /* Rx function code */
195 u_char smc_tfcr; /* Tx function code */
196 ushort smc_mrblr; /* Max receive buffer length */
197 uint smc_rstate; /* Internal */
198 uint smc_idp; /* Internal */
199 ushort smc_rbptr; /* Internal */
200 ushort smc_ibc; /* Internal */
201 uint smc_rxtmp; /* Internal */
202 uint smc_tstate; /* Internal */
203 uint smc_tdp; /* Internal */
204 ushort smc_tbptr; /* Internal */
205 ushort smc_tbc; /* Internal */
206 uint smc_txtmp; /* Internal */
207 ushort smc_maxidl; /* Maximum idle characters */
208 ushort smc_tmpidl; /* Temporary idle counter */
209 ushort smc_brklen; /* Last received break length */
210 ushort smc_brkec; /* rcv'd break condition counter */
211 ushort smc_brkcr; /* xmt break count register */
212 ushort smc_rmask; /* Temporary bit mask */
213 uint smc_stmp; /* SDMA Temp */
214} smc_uart_t;
215
216/* SMC uart mode register (Internal memory map).
217*/
218#define SMCMR_REN ((ushort)0x0001)
219#define SMCMR_TEN ((ushort)0x0002)
220#define SMCMR_DM ((ushort)0x000c)
221#define SMCMR_SM_GCI ((ushort)0x0000)
222#define SMCMR_SM_UART ((ushort)0x0020)
223#define SMCMR_SM_TRANS ((ushort)0x0030)
224#define SMCMR_SM_MASK ((ushort)0x0030)
225#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
226#define SMCMR_REVD SMCMR_PM_EVEN
227#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
228#define SMCMR_BS SMCMR_PEN
229#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
230#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
231#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
232
233/* SMC Event and Mask register.
234*/
235#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
236#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
237#define SMCM_TXE ((unsigned char)0x10)
238#define SMCM_BSY ((unsigned char)0x04)
239#define SMCM_TX ((unsigned char)0x02)
240#define SMCM_RX ((unsigned char)0x01)
241
242/* Baud rate generators.
243*/
244#define CPM_BRG_RST ((uint)0x00020000)
245#define CPM_BRG_EN ((uint)0x00010000)
246#define CPM_BRG_EXTC_INT ((uint)0x00000000)
247#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
248#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
249#define CPM_BRG_ATB ((uint)0x00002000)
250#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
251#define CPM_BRG_DIV16 ((uint)0x00000001)
252
253/* SCCs.
254*/
255#define SCC_GSMRH_IRP ((uint)0x00040000)
256#define SCC_GSMRH_GDE ((uint)0x00010000)
257#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
258#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
259#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
260#define SCC_GSMRH_REVD ((uint)0x00002000)
261#define SCC_GSMRH_TRX ((uint)0x00001000)
262#define SCC_GSMRH_TTX ((uint)0x00000800)
263#define SCC_GSMRH_CDP ((uint)0x00000400)
264#define SCC_GSMRH_CTSP ((uint)0x00000200)
265#define SCC_GSMRH_CDS ((uint)0x00000100)
266#define SCC_GSMRH_CTSS ((uint)0x00000080)
267#define SCC_GSMRH_TFL ((uint)0x00000040)
268#define SCC_GSMRH_RFW ((uint)0x00000020)
269#define SCC_GSMRH_TXSY ((uint)0x00000010)
270#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
271#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
272#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
273#define SCC_GSMRH_RTSM ((uint)0x00000002)
274#define SCC_GSMRH_RSYN ((uint)0x00000001)
275
276#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
277#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
278#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
279#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
280#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
281#define SCC_GSMRL_TCI ((uint)0x10000000)
282#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
283#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
284#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
285#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
286#define SCC_GSMRL_RINV ((uint)0x02000000)
287#define SCC_GSMRL_TINV ((uint)0x01000000)
288#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
289#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
290#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
291#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
292#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
293#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
294#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
295#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
296#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
297#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
298#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
299#define SCC_GSMRL_TEND ((uint)0x00040000)
300#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
301#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
302#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
303#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
304#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
305#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
306#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
307#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
308#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
309#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
310#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
311#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
312#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
313#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
314#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
315#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
316#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
317#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
318#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
319#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
320#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
321#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
322#define SCC_GSMRL_ENR ((uint)0x00000020)
323#define SCC_GSMRL_ENT ((uint)0x00000010)
324#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
325#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
326#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
327#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
328#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
329#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
330#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
331#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
332#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
333#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
334
335#define SCC_TODR_TOD ((ushort)0x8000)
336
337/* SCC Event and Mask register.
338*/
339#define SCCM_TXE ((unsigned char)0x10)
340#define SCCM_BSY ((unsigned char)0x04)
341#define SCCM_TX ((unsigned char)0x02)
342#define SCCM_RX ((unsigned char)0x01)
343
344typedef struct scc_param {
345 ushort scc_rbase; /* Rx Buffer descriptor base address */
346 ushort scc_tbase; /* Tx Buffer descriptor base address */
347 u_char scc_rfcr; /* Rx function code */
348 u_char scc_tfcr; /* Tx function code */
349 ushort scc_mrblr; /* Max receive buffer length */
350 uint scc_rstate; /* Internal */
351 uint scc_idp; /* Internal */
352 ushort scc_rbptr; /* Internal */
353 ushort scc_ibc; /* Internal */
354 uint scc_rxtmp; /* Internal */
355 uint scc_tstate; /* Internal */
356 uint scc_tdp; /* Internal */
357 ushort scc_tbptr; /* Internal */
358 ushort scc_tbc; /* Internal */
359 uint scc_txtmp; /* Internal */
360 uint scc_rcrc; /* Internal */
361 uint scc_tcrc; /* Internal */
362} sccp_t;
363
364/* CPM Ethernet through SCC1.
365 */
366typedef struct scc_enet {
367 sccp_t sen_genscc;
368 uint sen_cpres; /* Preset CRC */
369 uint sen_cmask; /* Constant mask for CRC */
370 uint sen_crcec; /* CRC Error counter */
371 uint sen_alec; /* alignment error counter */
372 uint sen_disfc; /* discard frame counter */
373 ushort sen_pads; /* Tx short frame pad character */
374 ushort sen_retlim; /* Retry limit threshold */
375 ushort sen_retcnt; /* Retry limit counter */
376 ushort sen_maxflr; /* maximum frame length register */
377 ushort sen_minflr; /* minimum frame length register */
378 ushort sen_maxd1; /* maximum DMA1 length */
379 ushort sen_maxd2; /* maximum DMA2 length */
380 ushort sen_maxd; /* Rx max DMA */
381 ushort sen_dmacnt; /* Rx DMA counter */
382 ushort sen_maxb; /* Max BD byte count */
383 ushort sen_gaddr1; /* Group address filter */
384 ushort sen_gaddr2;
385 ushort sen_gaddr3;
386 ushort sen_gaddr4;
387 uint sen_tbuf0data0; /* Save area 0 - current frame */
388 uint sen_tbuf0data1; /* Save area 1 - current frame */
389 uint sen_tbuf0rba; /* Internal */
390 uint sen_tbuf0crc; /* Internal */
391 ushort sen_tbuf0bcnt; /* Internal */
392 ushort sen_paddrh; /* physical address (MSB) */
393 ushort sen_paddrm;
394 ushort sen_paddrl; /* physical address (LSB) */
395 ushort sen_pper; /* persistence */
396 ushort sen_rfbdptr; /* Rx first BD pointer */
397 ushort sen_tfbdptr; /* Tx first BD pointer */
398 ushort sen_tlbdptr; /* Tx last BD pointer */
399 uint sen_tbuf1data0; /* Save area 0 - current frame */
400 uint sen_tbuf1data1; /* Save area 1 - current frame */
401 uint sen_tbuf1rba; /* Internal */
402 uint sen_tbuf1crc; /* Internal */
403 ushort sen_tbuf1bcnt; /* Internal */
404 ushort sen_txlen; /* Tx Frame length counter */
405 ushort sen_iaddr1; /* Individual address filter */
406 ushort sen_iaddr2;
407 ushort sen_iaddr3;
408 ushort sen_iaddr4;
409 ushort sen_boffcnt; /* Backoff counter */
410
411 /* NOTE: Some versions of the manual have the following items
412 * incorrectly documented. Below is the proper order.
413 */
414 ushort sen_taddrh; /* temp address (MSB) */
415 ushort sen_taddrm;
416 ushort sen_taddrl; /* temp address (LSB) */
417} scc_enet_t;
418
419
420/* SCC Event register as used by Ethernet.
421*/
422#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
423#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
424#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
425#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
426#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
427#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
428
429/* SCC Mode Register (PSMR) as used by Ethernet.
430*/
431#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
432#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
433#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
434#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
435#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
436#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
437#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
438#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
439#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
440#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
441#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
442#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
443#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
444
445/* Buffer descriptor control/status used by Ethernet receive.
446 * Common to SCC and FCC.
447 */
448#define BD_ENET_RX_EMPTY ((ushort)0x8000)
449#define BD_ENET_RX_WRAP ((ushort)0x2000)
450#define BD_ENET_RX_INTR ((ushort)0x1000)
451#define BD_ENET_RX_LAST ((ushort)0x0800)
452#define BD_ENET_RX_FIRST ((ushort)0x0400)
453#define BD_ENET_RX_MISS ((ushort)0x0100)
454#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
455#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
456#define BD_ENET_RX_LG ((ushort)0x0020)
457#define BD_ENET_RX_NO ((ushort)0x0010)
458#define BD_ENET_RX_SH ((ushort)0x0008)
459#define BD_ENET_RX_CR ((ushort)0x0004)
460#define BD_ENET_RX_OV ((ushort)0x0002)
461#define BD_ENET_RX_CL ((ushort)0x0001)
462#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
463
464/* Buffer descriptor control/status used by Ethernet transmit.
465 * Common to SCC and FCC.
466 */
467#define BD_ENET_TX_READY ((ushort)0x8000)
468#define BD_ENET_TX_PAD ((ushort)0x4000)
469#define BD_ENET_TX_WRAP ((ushort)0x2000)
470#define BD_ENET_TX_INTR ((ushort)0x1000)
471#define BD_ENET_TX_LAST ((ushort)0x0800)
472#define BD_ENET_TX_TC ((ushort)0x0400)
473#define BD_ENET_TX_DEF ((ushort)0x0200)
474#define BD_ENET_TX_HB ((ushort)0x0100)
475#define BD_ENET_TX_LC ((ushort)0x0080)
476#define BD_ENET_TX_RL ((ushort)0x0040)
477#define BD_ENET_TX_RCMASK ((ushort)0x003c)
478#define BD_ENET_TX_UN ((ushort)0x0002)
479#define BD_ENET_TX_CSL ((ushort)0x0001)
480#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
481
482/* SCC as UART
483*/
484typedef struct scc_uart {
485 sccp_t scc_genscc;
486 uint scc_res1; /* Reserved */
487 uint scc_res2; /* Reserved */
488 ushort scc_maxidl; /* Maximum idle chars */
489 ushort scc_idlc; /* temp idle counter */
490 ushort scc_brkcr; /* Break count register */
491 ushort scc_parec; /* receive parity error counter */
492 ushort scc_frmec; /* receive framing error counter */
493 ushort scc_nosec; /* receive noise counter */
494 ushort scc_brkec; /* receive break condition counter */
495 ushort scc_brkln; /* last received break length */
496 ushort scc_uaddr1; /* UART address character 1 */
497 ushort scc_uaddr2; /* UART address character 2 */
498 ushort scc_rtemp; /* Temp storage */
499 ushort scc_toseq; /* Transmit out of sequence char */
500 ushort scc_char1; /* control character 1 */
501 ushort scc_char2; /* control character 2 */
502 ushort scc_char3; /* control character 3 */
503 ushort scc_char4; /* control character 4 */
504 ushort scc_char5; /* control character 5 */
505 ushort scc_char6; /* control character 6 */
506 ushort scc_char7; /* control character 7 */
507 ushort scc_char8; /* control character 8 */
508 ushort scc_rccm; /* receive control character mask */
509 ushort scc_rccr; /* receive control character register */
510 ushort scc_rlbc; /* receive last break character */
511} scc_uart_t;
512
513/* SCC Event and Mask registers when it is used as a UART.
514*/
515#define UART_SCCM_GLR ((ushort)0x1000)
516#define UART_SCCM_GLT ((ushort)0x0800)
517#define UART_SCCM_AB ((ushort)0x0200)
518#define UART_SCCM_IDL ((ushort)0x0100)
519#define UART_SCCM_GRA ((ushort)0x0080)
520#define UART_SCCM_BRKE ((ushort)0x0040)
521#define UART_SCCM_BRKS ((ushort)0x0020)
522#define UART_SCCM_CCR ((ushort)0x0008)
523#define UART_SCCM_BSY ((ushort)0x0004)
524#define UART_SCCM_TX ((ushort)0x0002)
525#define UART_SCCM_RX ((ushort)0x0001)
526
527/* The SCC PSMR when used as a UART.
528*/
529#define SCU_PSMR_FLC ((ushort)0x8000)
530#define SCU_PSMR_SL ((ushort)0x4000)
531#define SCU_PSMR_CL ((ushort)0x3000)
532#define SCU_PSMR_UM ((ushort)0x0c00)
533#define SCU_PSMR_FRZ ((ushort)0x0200)
534#define SCU_PSMR_RZS ((ushort)0x0100)
535#define SCU_PSMR_SYN ((ushort)0x0080)
536#define SCU_PSMR_DRT ((ushort)0x0040)
537#define SCU_PSMR_PEN ((ushort)0x0010)
538#define SCU_PSMR_RPM ((ushort)0x000c)
539#define SCU_PSMR_REVP ((ushort)0x0008)
540#define SCU_PSMR_TPM ((ushort)0x0003)
541#define SCU_PSMR_TEVP ((ushort)0x0002)
542
543/* CPM Transparent mode SCC.
544 */
545typedef struct scc_trans {
546 sccp_t st_genscc;
547 uint st_cpres; /* Preset CRC */
548 uint st_cmask; /* Constant mask for CRC */
549} scc_trans_t;
550
551#define BD_SCC_TX_LAST ((ushort)0x0800)
552
553/* How about some FCCs.....
554*/
555#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
556#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
557#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
558#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
559#define FCC_GFMR_TCI ((uint)0x20000000)
560#define FCC_GFMR_TRX ((uint)0x10000000)
561#define FCC_GFMR_TTX ((uint)0x08000000)
562#define FCC_GFMR_TTX ((uint)0x08000000)
563#define FCC_GFMR_CDP ((uint)0x04000000)
564#define FCC_GFMR_CTSP ((uint)0x02000000)
565#define FCC_GFMR_CDS ((uint)0x01000000)
566#define FCC_GFMR_CTSS ((uint)0x00800000)
567#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
568#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
569#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
570#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
571#define FCC_GFMR_RTSM ((uint)0x00002000)
572#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
573#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
574#define FCC_GFMR_REVD ((uint)0x00000400)
575#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
576#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
577#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
578#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
579#define FCC_GFMR_ENR ((uint)0x00000020)
580#define FCC_GFMR_ENT ((uint)0x00000010)
581#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
582#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
583#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
584
585/* Generic FCC parameter ram.
586*/
587typedef struct fcc_param {
588 ushort fcc_riptr; /* Rx Internal temp pointer */
589 ushort fcc_tiptr; /* Tx Internal temp pointer */
590 ushort fcc_res1;
591 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
592 uint fcc_rstate; /* Upper byte is Func code, must be set */
593 uint fcc_rbase; /* Receive BD base */
594 ushort fcc_rbdstat; /* RxBD status */
595 ushort fcc_rbdlen; /* RxBD down counter */
596 uint fcc_rdptr; /* RxBD internal data pointer */
597 uint fcc_tstate; /* Upper byte is Func code, must be set */
598 uint fcc_tbase; /* Transmit BD base */
599 ushort fcc_tbdstat; /* TxBD status */
600 ushort fcc_tbdlen; /* TxBD down counter */
601 uint fcc_tdptr; /* TxBD internal data pointer */
602 uint fcc_rbptr; /* Rx BD Internal buf pointer */
603 uint fcc_tbptr; /* Tx BD Internal buf pointer */
604 uint fcc_rcrc; /* Rx temp CRC */
605 uint fcc_res2;
606 uint fcc_tcrc; /* Tx temp CRC */
607} fccp_t;
608
609
610/* Ethernet controller through FCC.
611*/
612typedef struct fcc_enet {
613 fccp_t fen_genfcc;
614 uint fen_statbuf; /* Internal status buffer */
615 uint fen_camptr; /* CAM address */
616 uint fen_cmask; /* Constant mask for CRC */
617 uint fen_cpres; /* Preset CRC */
618 uint fen_crcec; /* CRC Error counter */
619 uint fen_alec; /* alignment error counter */
620 uint fen_disfc; /* discard frame counter */
621 ushort fen_retlim; /* Retry limit */
622 ushort fen_retcnt; /* Retry counter */
623 ushort fen_pper; /* Persistence */
624 ushort fen_boffcnt; /* backoff counter */
625 uint fen_gaddrh; /* Group address filter, high 32-bits */
626 uint fen_gaddrl; /* Group address filter, low 32-bits */
627 ushort fen_tfcstat; /* out of sequence TxBD */
628 ushort fen_tfclen;
629 uint fen_tfcptr;
630 ushort fen_mflr; /* Maximum frame length (1518) */
631 ushort fen_paddrh; /* MAC address */
632 ushort fen_paddrm;
633 ushort fen_paddrl;
634 ushort fen_ibdcount; /* Internal BD counter */
635 ushort fen_ibdstart; /* Internal BD start pointer */
636 ushort fen_ibdend; /* Internal BD end pointer */
637 ushort fen_txlen; /* Internal Tx frame length counter */
638 uint fen_ibdbase[8]; /* Internal use */
639 uint fen_iaddrh; /* Individual address filter */
640 uint fen_iaddrl;
641 ushort fen_minflr; /* Minimum frame length (64) */
642 ushort fen_taddrh; /* Filter transfer MAC address */
643 ushort fen_taddrm;
644 ushort fen_taddrl;
645 ushort fen_padptr; /* Pointer to pad byte buffer */
646 ushort fen_cftype; /* control frame type */
647 ushort fen_cfrange; /* control frame range */
648 ushort fen_maxb; /* maximum BD count */
649 ushort fen_maxd1; /* Max DMA1 length (1520) */
650 ushort fen_maxd2; /* Max DMA2 length (1520) */
651 ushort fen_maxd; /* internal max DMA count */
652 ushort fen_dmacnt; /* internal DMA counter */
653 uint fen_octc; /* Total octect counter */
654 uint fen_colc; /* Total collision counter */
655 uint fen_broc; /* Total broadcast packet counter */
656 uint fen_mulc; /* Total multicast packet count */
657 uint fen_uspc; /* Total packets < 64 bytes */
658 uint fen_frgc; /* Total packets < 64 bytes with errors */
659 uint fen_ospc; /* Total packets > 1518 */
660 uint fen_jbrc; /* Total packets > 1518 with errors */
661 uint fen_p64c; /* Total packets == 64 bytes */
662 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
663 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
664 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
665 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
666 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
667 uint fen_cambuf; /* Internal CAM buffer poiner */
668 ushort fen_rfthr; /* Received frames threshold */
669 ushort fen_rfcnt; /* Received frames count */
670} fcc_enet_t;
671
672/* FCC Event/Mask register as used by Ethernet.
673*/
674#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
675#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
676#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
677#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
678#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
679#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
680#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
681#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
682
683/* FCC Mode Register (FPSMR) as used by Ethernet.
684*/
685#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
686#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
687#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
688#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
689#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
690#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
691#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
692#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
693#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
694#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
695#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
696#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
697#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
698
699/* IIC parameter RAM.
700*/
701typedef struct iic {
702 ushort iic_rbase; /* Rx Buffer descriptor base address */
703 ushort iic_tbase; /* Tx Buffer descriptor base address */
704 u_char iic_rfcr; /* Rx function code */
705 u_char iic_tfcr; /* Tx function code */
706 ushort iic_mrblr; /* Max receive buffer length */
707 uint iic_rstate; /* Internal */
708 uint iic_rdp; /* Internal */
709 ushort iic_rbptr; /* Internal */
710 ushort iic_rbc; /* Internal */
711 uint iic_rxtmp; /* Internal */
712 uint iic_tstate; /* Internal */
713 uint iic_tdp; /* Internal */
714 ushort iic_tbptr; /* Internal */
715 ushort iic_tbc; /* Internal */
716 uint iic_txtmp; /* Internal */
717} iic_t;
718
719/* SPI parameter RAM.
720*/
721typedef struct spi {
722 ushort spi_rbase; /* Rx Buffer descriptor base address */
723 ushort spi_tbase; /* Tx Buffer descriptor base address */
724 u_char spi_rfcr; /* Rx function code */
725 u_char spi_tfcr; /* Tx function code */
726 ushort spi_mrblr; /* Max receive buffer length */
727 uint spi_rstate; /* Internal */
728 uint spi_rdp; /* Internal */
729 ushort spi_rbptr; /* Internal */
730 ushort spi_rbc; /* Internal */
731 uint spi_rxtmp; /* Internal */
732 uint spi_tstate; /* Internal */
733 uint spi_tdp; /* Internal */
734 ushort spi_tbptr; /* Internal */
735 ushort spi_tbc; /* Internal */
736 uint spi_txtmp; /* Internal */
737 uint spi_res; /* Tx temp. */
738 uint spi_res1[4]; /* SDMA temp. */
739} spi_t;
740
741/* SPI Mode register.
742*/
743#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
744#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
745#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
746#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
747#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
748#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
749#define SPMODE_EN ((ushort)0x0100) /* Enable */
750#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
751#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
752
753#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
754#define SPMODE_PM(x) ((x) &0xF)
755
756#define SPI_EB ((u_char)0x10) /* big endian byte order */
757
758#define BD_IIC_START ((ushort)0x0400)
759
760/* IDMA parameter RAM
761*/
762typedef struct idma {
763 ushort ibase; /* IDMA buffer descriptor table base address */
764 ushort dcm; /* DMA channel mode */
765 ushort ibdptr; /* IDMA current buffer descriptor pointer */
766 ushort dpr_buf; /* IDMA transfer buffer base address */
767 ushort buf_inv; /* internal buffer inventory */
768 ushort ss_max; /* steady-state maximum transfer size */
769 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
770 ushort sts; /* source transfer size */
771 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
772 ushort seob; /* source end of burst */
773 ushort deob; /* destination end of burst */
774 ushort dts; /* destination transfer size */
775 ushort ret_add; /* return address when working in ERM=1 mode */
776 ushort res0; /* reserved */
777 uint bd_cnt; /* internal byte count */
778 uint s_ptr; /* source internal data pointer */
779 uint d_ptr; /* destination internal data pointer */
780 uint istate; /* internal state */
781 u_char res1[20]; /* pad to 64-byte length */
782} idma_t;
783
784/* DMA channel mode bit fields
785*/
786#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
787#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
788#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
789#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
790#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
791#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
792#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
793#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
794#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
795#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
796#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
797#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
798#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
799#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
800#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
801#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
802#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
803#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
804
805/* IDMA Buffer Descriptors
806*/
807typedef struct idma_bd {
808 uint flags;
809 uint len; /* data length */
810 uint src; /* source data buffer pointer */
811 uint dst; /* destination data buffer pointer */
812} idma_bd_t;
813
814/* IDMA buffer descriptor flag bit fields
815*/
816#define IDMA_BD_V ((uint)0x80000000) /* valid */
817#define IDMA_BD_W ((uint)0x20000000) /* wrap */
818#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
819#define IDMA_BD_L ((uint)0x08000000) /* last */
820#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
821#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
822#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
823#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
824#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
825#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
826#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
827#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
828#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
829#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
830#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
831
832/* per-channel IDMA registers
833*/
834typedef struct im_idma {
835 u_char idsr; /* IDMAn event status register */
836 u_char res0[3];
837 u_char idmr; /* IDMAn event mask register */
838 u_char res1[3];
839} im_idma_t;
840
841/* IDMA event register bit fields
842*/
843#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
844#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
845#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
846#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
847
848/* RISC Controller Configuration Register (RCCR) bit fields
849*/
850#define RCCR_TIME ((uint)0x80000000) /* timer enable */
851#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
852#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
853#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
854#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
855#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
856#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
857#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
858#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
859#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
860#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
861#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
862#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
863#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
864#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
865#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
866#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
867#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
868#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
869#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
870#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
871#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
872#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
873#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
874#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
875#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
876#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
877#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
878#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
879#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
880#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
881#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
882#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
883#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
884#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
885#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
886#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
887#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
888
889/*-----------------------------------------------------------------------
890 * CMXFCR - CMX FCC Clock Route Register
891 */
892#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
893#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
894#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
895#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
896#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
897#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
898#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
899#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
900#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
901
902#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
903#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
904#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
905#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
906#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
907#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
908#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
909#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
910
911#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
912#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
913#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
914#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
915#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
916#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
917#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
918#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
919
920#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
921#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
922#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
923#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
924#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
925#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
926#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
927#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
928
929#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
930#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
931#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
932#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
933#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
934#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
935#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
936#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
937
938#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
939#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
940#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
941#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
942#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
943#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
944#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
945#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
946
947#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
948#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
949#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
950#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
951#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
952#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
953#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
954#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
955
956/*-----------------------------------------------------------------------
957 * CMXSCR - CMX SCC Clock Route Register
958 */
959#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
960#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
961#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
962#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
963#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
964#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
965#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
966#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
967#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
968#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
969#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
970#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
971#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
972#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
973#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
974#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
975
976#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
977#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
978#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
979#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
980#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
981#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
982#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
983#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
984
985#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
986#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
987#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
988#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
989#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
990#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
991#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
992#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
993
994#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
995#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
996#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
997#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
998#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
999#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
1000#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
1001#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
1002
1003#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
1004#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
1005#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
1006#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
1007#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
1008#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
1009#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
1010#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
1011
1012#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
1013#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
1014#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
1015#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
1016#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
1017#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
1018#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
1019#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
1020
1021#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
1022#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
1023#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
1024#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
1025#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
1026#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
1027#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
1028#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
1029
1030#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
1031#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
1032#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
1033#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
1034#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
1035#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
1036#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
1037#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
1038
1039#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
1040#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
1041#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
1042#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
1043#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
1044#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
1045#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
1046#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
1047
1048/*-----------------------------------------------------------------------
1049 * SIUMCR - SIU Module Configuration Register 4-31
1050 */
1051#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
1052#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
1053#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
1054#define SIUMCR_CDIS 0x10000000 /* Core Disable */
1055#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
1056#define SIUMCR_DPPC01 0x04000000 /* - " - */
1057#define SIUMCR_DPPC10 0x08000000 /* - " - */
1058#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1059#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1060#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1061#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1062#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1063#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1064#define SIUMCR_LBPC01 0x00400000 /* - " - */
1065#define SIUMCR_LBPC10 0x00800000 /* - " - */
1066#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1067#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1068#define SIUMCR_APPC01 0x00100000 /* - " - */
1069#define SIUMCR_APPC10 0x00200000 /* - " - */
1070#define SIUMCR_APPC11 0x00300000 /* - " - */
1071#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1072#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1073#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1074#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1075#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1076#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1077#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1078#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1079#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1080#define SIUMCR_MMR01 0x00004000 /* - " - */
1081#define SIUMCR_MMR10 0x00008000 /* - " - */
1082#define SIUMCR_MMR11 0x0000c000 /* - " - */
1083#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1084
1085/*-----------------------------------------------------------------------
1086 * SCCR - System Clock Control Register 9-8
1087*/
1088#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1089#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1090#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1091#define SCCR_PCIDF_SHIFT 3
1092
1093#ifndef CPM_IMMR_OFFSET
1094#define CPM_IMMR_OFFSET 0x101a8
1095#endif
1096
1097#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1098
1099/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1100 * in order to use clock-computing stuff below for the FCC x
1101 */
1102
1103/* Automatically generates register configurations */
1104#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1105
1106#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1107#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1108#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1109#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1110#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1111#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1112
1113#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1114#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1115#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1116#define CMX1_CLK_MASK ((uint)0xff000000)
1117
1118#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1119#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1120#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1121#define CMX2_CLK_MASK ((uint)0x00ff0000)
1122
1123#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1124#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1125#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1126#define CMX3_CLK_MASK ((uint)0x0000ff00)
1127
1128#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1129#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1130
1131#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1132
1133/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1134 * but there is little variation among the choices.
1135 */
1136#define PA1_COL 0x00000001U
1137#define PA1_CRS 0x00000002U
1138#define PA1_TXER 0x00000004U
1139#define PA1_TXEN 0x00000008U
1140#define PA1_RXDV 0x00000010U
1141#define PA1_RXER 0x00000020U
1142#define PA1_TXDAT 0x00003c00U
1143#define PA1_RXDAT 0x0003c000U
1144#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1145#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1146 PA1_RXDV | PA1_RXER)
1147#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1148#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1149
1150
1151/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1152 * but there is little variation among the choices.
1153 */
1154#define PB2_TXER 0x00000001U
1155#define PB2_RXDV 0x00000002U
1156#define PB2_TXEN 0x00000004U
1157#define PB2_RXER 0x00000008U
1158#define PB2_COL 0x00000010U
1159#define PB2_CRS 0x00000020U
1160#define PB2_TXDAT 0x000003c0U
1161#define PB2_RXDAT 0x00003c00U
1162#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1163 PB2_RXER | PB2_RXDV | PB2_TXER)
1164#define PB2_PSORB1 (PB2_TXEN)
1165#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1166#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1167
1168
1169/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1170 * but there is little variation among the choices.
1171 */
1172#define PB3_RXDV 0x00004000U
1173#define PB3_RXER 0x00008000U
1174#define PB3_TXER 0x00010000U
1175#define PB3_TXEN 0x00020000U
1176#define PB3_COL 0x00040000U
1177#define PB3_CRS 0x00080000U
1178#define PB3_TXDAT 0x0f000000U
1179#define PC3_TXDAT 0x00000010U
1180#define PB3_RXDAT 0x00f00000U
1181#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1182 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1183#define PB3_PSORB1 0
1184#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1185#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1186#define PC3_DIRC1 (PC3_TXDAT)
1187
1188/* Handy macro to specify mem for FCCs*/
1189#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1190#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1191#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1192#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1193
1194/* Clocks and GRG's */
1195
1196enum cpm_clk_dir {
1197 CPM_CLK_RX,
1198 CPM_CLK_TX,
1199 CPM_CLK_RTX
1200};
1201
1202enum cpm_clk_target {
1203 CPM_CLK_SCC1,
1204 CPM_CLK_SCC2,
1205 CPM_CLK_SCC3,
1206 CPM_CLK_SCC4,
1207 CPM_CLK_FCC1,
1208 CPM_CLK_FCC2,
1209 CPM_CLK_FCC3
1210};
1211
1212enum cpm_clk {
1213 CPM_CLK_NONE = 0,
1214 CPM_BRG1, /* Baud Rate Generator 1 */
1215 CPM_BRG2, /* Baud Rate Generator 2 */
1216 CPM_BRG3, /* Baud Rate Generator 3 */
1217 CPM_BRG4, /* Baud Rate Generator 4 */
1218 CPM_BRG5, /* Baud Rate Generator 5 */
1219 CPM_BRG6, /* Baud Rate Generator 6 */
1220 CPM_BRG7, /* Baud Rate Generator 7 */
1221 CPM_BRG8, /* Baud Rate Generator 8 */
1222 CPM_CLK1, /* Clock 1 */
1223 CPM_CLK2, /* Clock 2 */
1224 CPM_CLK3, /* Clock 3 */
1225 CPM_CLK4, /* Clock 4 */
1226 CPM_CLK5, /* Clock 5 */
1227 CPM_CLK6, /* Clock 6 */
1228 CPM_CLK7, /* Clock 7 */
1229 CPM_CLK8, /* Clock 8 */
1230 CPM_CLK9, /* Clock 9 */
1231 CPM_CLK10, /* Clock 10 */
1232 CPM_CLK11, /* Clock 11 */
1233 CPM_CLK12, /* Clock 12 */
1234 CPM_CLK13, /* Clock 13 */
1235 CPM_CLK14, /* Clock 14 */
1236 CPM_CLK15, /* Clock 15 */
1237 CPM_CLK16, /* Clock 16 */
1238 CPM_CLK17, /* Clock 17 */
1239 CPM_CLK18, /* Clock 18 */
1240 CPM_CLK19, /* Clock 19 */
1241 CPM_CLK20, /* Clock 20 */
1242 CPM_CLK_DUMMY
1243};
1244
1245extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1246
1247#endif /* __CPM2__ */
1248#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/highmem.h b/include/asm-powerpc/highmem.h
new file mode 100644
index 000000000000..f7b21ee302b4
--- /dev/null
+++ b/include/asm-powerpc/highmem.h
@@ -0,0 +1,135 @@
1/*
2 * highmem.h: virtual kernel memory mappings for high memory
3 *
4 * PowerPC version, stolen from the i386 version.
5 *
6 * Used in CONFIG_HIGHMEM systems for memory pages which
7 * are not addressable by direct kernel virtual addresses.
8 *
9 * Copyright (C) 1999 Gerhard Wichert, Siemens AG
10 * Gerhard.Wichert@pdb.siemens.de
11 *
12 *
13 * Redesigned the x86 32-bit VM architecture to deal with
14 * up to 16 Terrabyte physical memory. With current x86 CPUs
15 * we now support up to 64 Gigabytes physical RAM.
16 *
17 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
18 */
19
20#ifndef _ASM_HIGHMEM_H
21#define _ASM_HIGHMEM_H
22
23#ifdef __KERNEL__
24
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <asm/kmap_types.h>
28#include <asm/tlbflush.h>
29#include <asm/page.h>
30
31/* undef for production */
32#define HIGHMEM_DEBUG 1
33
34extern pte_t *kmap_pte;
35extern pgprot_t kmap_prot;
36extern pte_t *pkmap_page_table;
37
38/*
39 * Right now we initialize only a single pte table. It can be extended
40 * easily, subsequent pte tables have to be allocated in one physical
41 * chunk of RAM.
42 */
43#define PKMAP_BASE CONFIG_HIGHMEM_START
44#define LAST_PKMAP (1 << PTE_SHIFT)
45#define LAST_PKMAP_MASK (LAST_PKMAP-1)
46#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
47#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
48
49#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL)
50
51extern void *kmap_high(struct page *page);
52extern void kunmap_high(struct page *page);
53
54static inline void *kmap(struct page *page)
55{
56 might_sleep();
57 if (!PageHighMem(page))
58 return page_address(page);
59 return kmap_high(page);
60}
61
62static inline void kunmap(struct page *page)
63{
64 BUG_ON(in_interrupt());
65 if (!PageHighMem(page))
66 return;
67 kunmap_high(page);
68}
69
70/*
71 * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
72 * gives a more generic (and caching) interface. But kmap_atomic can
73 * be used in IRQ contexts, so in some (very limited) cases we need
74 * it.
75 */
76static inline void *kmap_atomic(struct page *page, enum km_type type)
77{
78 unsigned int idx;
79 unsigned long vaddr;
80
81 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
82 pagefault_disable();
83 if (!PageHighMem(page))
84 return page_address(page);
85
86 idx = type + KM_TYPE_NR*smp_processor_id();
87 vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
88#ifdef HIGHMEM_DEBUG
89 BUG_ON(!pte_none(*(kmap_pte+idx)));
90#endif
91 set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
92 flush_tlb_page(NULL, vaddr);
93
94 return (void*) vaddr;
95}
96
97static inline void kunmap_atomic(void *kvaddr, enum km_type type)
98{
99#ifdef HIGHMEM_DEBUG
100 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
101 unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
102
103 if (vaddr < KMAP_FIX_BEGIN) { // FIXME
104 pagefault_enable();
105 return;
106 }
107
108 BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
109
110 /*
111 * force other mappings to Oops if they'll try to access
112 * this pte without first remap it
113 */
114 pte_clear(&init_mm, vaddr, kmap_pte+idx);
115 flush_tlb_page(NULL, vaddr);
116#endif
117 pagefault_enable();
118}
119
120static inline struct page *kmap_atomic_to_page(void *ptr)
121{
122 unsigned long idx, vaddr = (unsigned long) ptr;
123
124 if (vaddr < KMAP_FIX_BEGIN)
125 return virt_to_page(ptr);
126
127 idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
128 return pte_page(kmap_pte[idx]);
129}
130
131#define flush_cache_kmaps() flush_cache_all()
132
133#endif /* __KERNEL__ */
134
135#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-powerpc/hydra.h b/include/asm-powerpc/hydra.h
new file mode 100644
index 000000000000..1ad4eed07fbe
--- /dev/null
+++ b/include/asm-powerpc/hydra.h
@@ -0,0 +1,102 @@
1/*
2 * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
3 *
4 * Copyright (C) 1997 Geert Uytterhoeven
5 *
6 * This file is based on the following documentation:
7 *
8 * Macintosh Technology in the Common Hardware Reference Platform
9 * Apple Computer, Inc.
10 *
11 * © Copyright 1995 Apple Computer, Inc. All rights reserved.
12 *
13 * It's available online from http://chrp.apple.com/MacTech.pdf.
14 * You can obtain paper copies of this book from computer bookstores or by
15 * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
16 * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file COPYING in the main directory of this archive
20 * for more details.
21 */
22
23#ifndef _ASMPPC_HYDRA_H
24#define _ASMPPC_HYDRA_H
25
26#ifdef __KERNEL__
27
28struct Hydra {
29 /* DBDMA Controller Register Space */
30 char Pad1[0x30];
31 u_int CachePD;
32 u_int IDs;
33 u_int Feature_Control;
34 char Pad2[0x7fc4];
35 /* DBDMA Channel Register Space */
36 char SCSI_DMA[0x100];
37 char Pad3[0x300];
38 char SCCA_Tx_DMA[0x100];
39 char SCCA_Rx_DMA[0x100];
40 char SCCB_Tx_DMA[0x100];
41 char SCCB_Rx_DMA[0x100];
42 char Pad4[0x7800];
43 /* Device Register Space */
44 char SCSI[0x1000];
45 char ADB[0x1000];
46 char SCC_Legacy[0x1000];
47 char SCC[0x1000];
48 char Pad9[0x2000];
49 char VIA[0x2000];
50 char Pad10[0x28000];
51 char OpenPIC[0x40000];
52};
53
54extern volatile struct Hydra __iomem *Hydra;
55
56
57 /*
58 * Feature Control Register
59 */
60
61#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
62#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
63#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
64#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
65#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
66#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
67#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
68#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
69#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
70
71
72 /*
73 * OpenPIC Interrupt Sources
74 */
75
76#define HYDRA_INT_SIO 0
77#define HYDRA_INT_SCSI_DMA 1
78#define HYDRA_INT_SCCA_TX_DMA 2
79#define HYDRA_INT_SCCA_RX_DMA 3
80#define HYDRA_INT_SCCB_TX_DMA 4
81#define HYDRA_INT_SCCB_RX_DMA 5
82#define HYDRA_INT_SCSI 6
83#define HYDRA_INT_SCCA 7
84#define HYDRA_INT_SCCB 8
85#define HYDRA_INT_VIA 9
86#define HYDRA_INT_ADB 10
87#define HYDRA_INT_ADB_NMI 11
88#define HYDRA_INT_EXT1 12 /* PCI IRQW */
89#define HYDRA_INT_EXT2 13 /* PCI IRQX */
90#define HYDRA_INT_EXT3 14 /* PCI IRQY */
91#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
92#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
93#define HYDRA_INT_EXT6 17 /* IDE Secondary */
94#define HYDRA_INT_EXT7 18 /* Power Off Request */
95#define HYDRA_INT_SPARE 19
96
97extern int hydra_init(void);
98extern void macio_adb_init(void);
99
100#endif /* __KERNEL__ */
101
102#endif /* _ASMPPC_HYDRA_H */
diff --git a/include/asm-powerpc/immap_cpm2.h b/include/asm-powerpc/immap_cpm2.h
new file mode 100644
index 000000000000..f316a91c628a
--- /dev/null
+++ b/include/asm-powerpc/immap_cpm2.h
@@ -0,0 +1,648 @@
1/*
2 * CPM2 Internal Memory Map
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
4 *
5 * The Internal Memory Map for devices with CPM2 on them. This
6 * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
7 * 8560).
8 */
9#ifdef __KERNEL__
10#ifndef __IMMAP_CPM2__
11#define __IMMAP_CPM2__
12
13/* System configuration registers.
14*/
15typedef struct sys_82xx_conf {
16 u32 sc_siumcr;
17 u32 sc_sypcr;
18 u8 res1[6];
19 u16 sc_swsr;
20 u8 res2[20];
21 u32 sc_bcr;
22 u8 sc_ppc_acr;
23 u8 res3[3];
24 u32 sc_ppc_alrh;
25 u32 sc_ppc_alrl;
26 u8 sc_lcl_acr;
27 u8 res4[3];
28 u32 sc_lcl_alrh;
29 u32 sc_lcl_alrl;
30 u32 sc_tescr1;
31 u32 sc_tescr2;
32 u32 sc_ltescr1;
33 u32 sc_ltescr2;
34 u32 sc_pdtea;
35 u8 sc_pdtem;
36 u8 res5[3];
37 u32 sc_ldtea;
38 u8 sc_ldtem;
39 u8 res6[163];
40} sysconf_82xx_cpm2_t;
41
42typedef struct sys_85xx_conf {
43 u32 sc_cear;
44 u16 sc_ceer;
45 u16 sc_cemr;
46 u8 res1[70];
47 u32 sc_smaer;
48 u8 res2[4];
49 u32 sc_smevr;
50 u32 sc_smctr;
51 u32 sc_lmaer;
52 u8 res3[4];
53 u32 sc_lmevr;
54 u32 sc_lmctr;
55 u8 res4[144];
56} sysconf_85xx_cpm2_t;
57
58typedef union sys_conf {
59 sysconf_82xx_cpm2_t siu_82xx;
60 sysconf_85xx_cpm2_t siu_85xx;
61} sysconf_cpm2_t;
62
63
64
65/* Memory controller registers.
66*/
67typedef struct mem_ctlr {
68 u32 memc_br0;
69 u32 memc_or0;
70 u32 memc_br1;
71 u32 memc_or1;
72 u32 memc_br2;
73 u32 memc_or2;
74 u32 memc_br3;
75 u32 memc_or3;
76 u32 memc_br4;
77 u32 memc_or4;
78 u32 memc_br5;
79 u32 memc_or5;
80 u32 memc_br6;
81 u32 memc_or6;
82 u32 memc_br7;
83 u32 memc_or7;
84 u32 memc_br8;
85 u32 memc_or8;
86 u32 memc_br9;
87 u32 memc_or9;
88 u32 memc_br10;
89 u32 memc_or10;
90 u32 memc_br11;
91 u32 memc_or11;
92 u8 res1[8];
93 u32 memc_mar;
94 u8 res2[4];
95 u32 memc_mamr;
96 u32 memc_mbmr;
97 u32 memc_mcmr;
98 u8 res3[8];
99 u16 memc_mptpr;
100 u8 res4[2];
101 u32 memc_mdr;
102 u8 res5[4];
103 u32 memc_psdmr;
104 u32 memc_lsdmr;
105 u8 memc_purt;
106 u8 res6[3];
107 u8 memc_psrt;
108 u8 res7[3];
109 u8 memc_lurt;
110 u8 res8[3];
111 u8 memc_lsrt;
112 u8 res9[3];
113 u32 memc_immr;
114 u32 memc_pcibr0;
115 u32 memc_pcibr1;
116 u8 res10[16];
117 u32 memc_pcimsk0;
118 u32 memc_pcimsk1;
119 u8 res11[52];
120} memctl_cpm2_t;
121
122/* System Integration Timers.
123*/
124typedef struct sys_int_timers {
125 u8 res1[32];
126 u16 sit_tmcntsc;
127 u8 res2[2];
128 u32 sit_tmcnt;
129 u8 res3[4];
130 u32 sit_tmcntal;
131 u8 res4[16];
132 u16 sit_piscr;
133 u8 res5[2];
134 u32 sit_pitc;
135 u32 sit_pitr;
136 u8 res6[94];
137 u8 res7[390];
138} sit_cpm2_t;
139
140#define PISCR_PIRQ_MASK ((u16)0xff00)
141#define PISCR_PS ((u16)0x0080)
142#define PISCR_PIE ((u16)0x0004)
143#define PISCR_PTF ((u16)0x0002)
144#define PISCR_PTE ((u16)0x0001)
145
146/* PCI Controller.
147*/
148typedef struct pci_ctlr {
149 u32 pci_omisr;
150 u32 pci_omimr;
151 u8 res1[8];
152 u32 pci_ifqpr;
153 u32 pci_ofqpr;
154 u8 res2[8];
155 u32 pci_imr0;
156 u32 pci_imr1;
157 u32 pci_omr0;
158 u32 pci_omr1;
159 u32 pci_odr;
160 u8 res3[4];
161 u32 pci_idr;
162 u8 res4[20];
163 u32 pci_imisr;
164 u32 pci_imimr;
165 u8 res5[24];
166 u32 pci_ifhpr;
167 u8 res6[4];
168 u32 pci_iftpr;
169 u8 res7[4];
170 u32 pci_iphpr;
171 u8 res8[4];
172 u32 pci_iptpr;
173 u8 res9[4];
174 u32 pci_ofhpr;
175 u8 res10[4];
176 u32 pci_oftpr;
177 u8 res11[4];
178 u32 pci_ophpr;
179 u8 res12[4];
180 u32 pci_optpr;
181 u8 res13[8];
182 u32 pci_mucr;
183 u8 res14[8];
184 u32 pci_qbar;
185 u8 res15[12];
186 u32 pci_dmamr0;
187 u32 pci_dmasr0;
188 u32 pci_dmacdar0;
189 u8 res16[4];
190 u32 pci_dmasar0;
191 u8 res17[4];
192 u32 pci_dmadar0;
193 u8 res18[4];
194 u32 pci_dmabcr0;
195 u32 pci_dmandar0;
196 u8 res19[86];
197 u32 pci_dmamr1;
198 u32 pci_dmasr1;
199 u32 pci_dmacdar1;
200 u8 res20[4];
201 u32 pci_dmasar1;
202 u8 res21[4];
203 u32 pci_dmadar1;
204 u8 res22[4];
205 u32 pci_dmabcr1;
206 u32 pci_dmandar1;
207 u8 res23[88];
208 u32 pci_dmamr2;
209 u32 pci_dmasr2;
210 u32 pci_dmacdar2;
211 u8 res24[4];
212 u32 pci_dmasar2;
213 u8 res25[4];
214 u32 pci_dmadar2;
215 u8 res26[4];
216 u32 pci_dmabcr2;
217 u32 pci_dmandar2;
218 u8 res27[88];
219 u32 pci_dmamr3;
220 u32 pci_dmasr3;
221 u32 pci_dmacdar3;
222 u8 res28[4];
223 u32 pci_dmasar3;
224 u8 res29[4];
225 u32 pci_dmadar3;
226 u8 res30[4];
227 u32 pci_dmabcr3;
228 u32 pci_dmandar3;
229 u8 res31[344];
230 u32 pci_potar0;
231 u8 res32[4];
232 u32 pci_pobar0;
233 u8 res33[4];
234 u32 pci_pocmr0;
235 u8 res34[4];
236 u32 pci_potar1;
237 u8 res35[4];
238 u32 pci_pobar1;
239 u8 res36[4];
240 u32 pci_pocmr1;
241 u8 res37[4];
242 u32 pci_potar2;
243 u8 res38[4];
244 u32 pci_pobar2;
245 u8 res39[4];
246 u32 pci_pocmr2;
247 u8 res40[50];
248 u32 pci_ptcr;
249 u32 pci_gpcr;
250 u32 pci_gcr;
251 u32 pci_esr;
252 u32 pci_emr;
253 u32 pci_ecr;
254 u32 pci_eacr;
255 u8 res41[4];
256 u32 pci_edcr;
257 u8 res42[4];
258 u32 pci_eccr;
259 u8 res43[44];
260 u32 pci_pitar1;
261 u8 res44[4];
262 u32 pci_pibar1;
263 u8 res45[4];
264 u32 pci_picmr1;
265 u8 res46[4];
266 u32 pci_pitar0;
267 u8 res47[4];
268 u32 pci_pibar0;
269 u8 res48[4];
270 u32 pci_picmr0;
271 u8 res49[4];
272 u32 pci_cfg_addr;
273 u32 pci_cfg_data;
274 u32 pci_int_ack;
275 u8 res50[756];
276} pci_cpm2_t;
277
278/* Interrupt Controller.
279*/
280typedef struct interrupt_controller {
281 u16 ic_sicr;
282 u8 res1[2];
283 u32 ic_sivec;
284 u32 ic_sipnrh;
285 u32 ic_sipnrl;
286 u32 ic_siprr;
287 u32 ic_scprrh;
288 u32 ic_scprrl;
289 u32 ic_simrh;
290 u32 ic_simrl;
291 u32 ic_siexr;
292 u8 res2[88];
293} intctl_cpm2_t;
294
295/* Clocks and Reset.
296*/
297typedef struct clk_and_reset {
298 u32 car_sccr;
299 u8 res1[4];
300 u32 car_scmr;
301 u8 res2[4];
302 u32 car_rsr;
303 u32 car_rmr;
304 u8 res[104];
305} car_cpm2_t;
306
307/* Input/Output Port control/status registers.
308 * Names consistent with processor manual, although they are different
309 * from the original 8xx names.......
310 */
311typedef struct io_port {
312 u32 iop_pdira;
313 u32 iop_ppara;
314 u32 iop_psora;
315 u32 iop_podra;
316 u32 iop_pdata;
317 u8 res1[12];
318 u32 iop_pdirb;
319 u32 iop_pparb;
320 u32 iop_psorb;
321 u32 iop_podrb;
322 u32 iop_pdatb;
323 u8 res2[12];
324 u32 iop_pdirc;
325 u32 iop_pparc;
326 u32 iop_psorc;
327 u32 iop_podrc;
328 u32 iop_pdatc;
329 u8 res3[12];
330 u32 iop_pdird;
331 u32 iop_ppard;
332 u32 iop_psord;
333 u32 iop_podrd;
334 u32 iop_pdatd;
335 u8 res4[12];
336} iop_cpm2_t;
337
338/* Communication Processor Module Timers
339*/
340typedef struct cpm_timers {
341 u8 cpmt_tgcr1;
342 u8 res1[3];
343 u8 cpmt_tgcr2;
344 u8 res2[11];
345 u16 cpmt_tmr1;
346 u16 cpmt_tmr2;
347 u16 cpmt_trr1;
348 u16 cpmt_trr2;
349 u16 cpmt_tcr1;
350 u16 cpmt_tcr2;
351 u16 cpmt_tcn1;
352 u16 cpmt_tcn2;
353 u16 cpmt_tmr3;
354 u16 cpmt_tmr4;
355 u16 cpmt_trr3;
356 u16 cpmt_trr4;
357 u16 cpmt_tcr3;
358 u16 cpmt_tcr4;
359 u16 cpmt_tcn3;
360 u16 cpmt_tcn4;
361 u16 cpmt_ter1;
362 u16 cpmt_ter2;
363 u16 cpmt_ter3;
364 u16 cpmt_ter4;
365 u8 res3[584];
366} cpmtimer_cpm2_t;
367
368/* DMA control/status registers.
369*/
370typedef struct sdma_csr {
371 u8 res0[24];
372 u8 sdma_sdsr;
373 u8 res1[3];
374 u8 sdma_sdmr;
375 u8 res2[3];
376 u8 sdma_idsr1;
377 u8 res3[3];
378 u8 sdma_idmr1;
379 u8 res4[3];
380 u8 sdma_idsr2;
381 u8 res5[3];
382 u8 sdma_idmr2;
383 u8 res6[3];
384 u8 sdma_idsr3;
385 u8 res7[3];
386 u8 sdma_idmr3;
387 u8 res8[3];
388 u8 sdma_idsr4;
389 u8 res9[3];
390 u8 sdma_idmr4;
391 u8 res10[707];
392} sdma_cpm2_t;
393
394/* Fast controllers
395*/
396typedef struct fcc {
397 u32 fcc_gfmr;
398 u32 fcc_fpsmr;
399 u16 fcc_ftodr;
400 u8 res1[2];
401 u16 fcc_fdsr;
402 u8 res2[2];
403 u16 fcc_fcce;
404 u8 res3[2];
405 u16 fcc_fccm;
406 u8 res4[2];
407 u8 fcc_fccs;
408 u8 res5[3];
409 u8 fcc_ftirr_phy[4];
410} fcc_t;
411
412/* Fast controllers continued
413 */
414typedef struct fcc_c {
415 u32 fcc_firper;
416 u32 fcc_firer;
417 u32 fcc_firsr_hi;
418 u32 fcc_firsr_lo;
419 u8 fcc_gfemr;
420 u8 res1[15];
421} fcc_c_t;
422
423/* TC Layer
424 */
425typedef struct tclayer {
426 u16 tc_tcmode;
427 u16 tc_cdsmr;
428 u16 tc_tcer;
429 u16 tc_rcc;
430 u16 tc_tcmr;
431 u16 tc_fcc;
432 u16 tc_ccc;
433 u16 tc_icc;
434 u16 tc_tcc;
435 u16 tc_ecc;
436 u8 res1[12];
437} tclayer_t;
438
439
440/* I2C
441*/
442typedef struct i2c {
443 u8 i2c_i2mod;
444 u8 res1[3];
445 u8 i2c_i2add;
446 u8 res2[3];
447 u8 i2c_i2brg;
448 u8 res3[3];
449 u8 i2c_i2com;
450 u8 res4[3];
451 u8 i2c_i2cer;
452 u8 res5[3];
453 u8 i2c_i2cmr;
454 u8 res6[331];
455} i2c_cpm2_t;
456
457typedef struct scc { /* Serial communication channels */
458 u32 scc_gsmrl;
459 u32 scc_gsmrh;
460 u16 scc_psmr;
461 u8 res1[2];
462 u16 scc_todr;
463 u16 scc_dsr;
464 u16 scc_scce;
465 u8 res2[2];
466 u16 scc_sccm;
467 u8 res3;
468 u8 scc_sccs;
469 u8 res4[8];
470} scc_t;
471
472typedef struct smc { /* Serial management channels */
473 u8 res1[2];
474 u16 smc_smcmr;
475 u8 res2[2];
476 u8 smc_smce;
477 u8 res3[3];
478 u8 smc_smcm;
479 u8 res4[5];
480} smc_t;
481
482/* Serial Peripheral Interface.
483*/
484typedef struct spi_ctrl {
485 u16 spi_spmode;
486 u8 res1[4];
487 u8 spi_spie;
488 u8 res2[3];
489 u8 spi_spim;
490 u8 res3[2];
491 u8 spi_spcom;
492 u8 res4[82];
493} spictl_cpm2_t;
494
495/* CPM Mux.
496*/
497typedef struct cpmux {
498 u8 cmx_si1cr;
499 u8 res1;
500 u8 cmx_si2cr;
501 u8 res2;
502 u32 cmx_fcr;
503 u32 cmx_scr;
504 u8 cmx_smr;
505 u8 res3;
506 u16 cmx_uar;
507 u8 res4[16];
508} cpmux_t;
509
510/* SIRAM control
511*/
512typedef struct siram {
513 u16 si_amr;
514 u16 si_bmr;
515 u16 si_cmr;
516 u16 si_dmr;
517 u8 si_gmr;
518 u8 res1;
519 u8 si_cmdr;
520 u8 res2;
521 u8 si_str;
522 u8 res3;
523 u16 si_rsr;
524} siramctl_t;
525
526typedef struct mcc {
527 u16 mcc_mcce;
528 u8 res1[2];
529 u16 mcc_mccm;
530 u8 res2[2];
531 u8 mcc_mccf;
532 u8 res3[7];
533} mcc_t;
534
535typedef struct comm_proc {
536 u32 cp_cpcr;
537 u32 cp_rccr;
538 u8 res1[14];
539 u16 cp_rter;
540 u8 res2[2];
541 u16 cp_rtmr;
542 u16 cp_rtscr;
543 u8 res3[2];
544 u32 cp_rtsr;
545 u8 res4[12];
546} cpm_cpm2_t;
547
548/* USB Controller.
549*/
550typedef struct usb_ctlr {
551 u8 usb_usmod;
552 u8 usb_usadr;
553 u8 usb_uscom;
554 u8 res1[1];
555 u16 usb_usep1;
556 u16 usb_usep2;
557 u16 usb_usep3;
558 u16 usb_usep4;
559 u8 res2[4];
560 u16 usb_usber;
561 u8 res3[2];
562 u16 usb_usbmr;
563 u8 usb_usbs;
564 u8 res4[7];
565} usb_cpm2_t;
566
567/* ...and the whole thing wrapped up....
568*/
569
570typedef struct immap {
571 /* Some references are into the unique and known dpram spaces,
572 * others are from the generic base.
573 */
574#define im_dprambase im_dpram1
575 u8 im_dpram1[16*1024];
576 u8 res1[16*1024];
577 u8 im_dpram2[4*1024];
578 u8 res2[8*1024];
579 u8 im_dpram3[4*1024];
580 u8 res3[16*1024];
581
582 sysconf_cpm2_t im_siu_conf; /* SIU Configuration */
583 memctl_cpm2_t im_memctl; /* Memory Controller */
584 sit_cpm2_t im_sit; /* System Integration Timers */
585 pci_cpm2_t im_pci; /* PCI Controller */
586 intctl_cpm2_t im_intctl; /* Interrupt Controller */
587 car_cpm2_t im_clkrst; /* Clocks and reset */
588 iop_cpm2_t im_ioport; /* IO Port control/status */
589 cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */
590 sdma_cpm2_t im_sdma; /* SDMA control/status */
591
592 fcc_t im_fcc[3]; /* Three FCCs */
593 u8 res4z[32];
594 fcc_c_t im_fcc_c[3]; /* Continued FCCs */
595
596 u8 res4[32];
597
598 tclayer_t im_tclayer[8]; /* Eight TCLayers */
599 u16 tc_tcgsr;
600 u16 tc_tcger;
601
602 /* First set of baud rate generators.
603 */
604 u8 res[236];
605 u32 im_brgc5;
606 u32 im_brgc6;
607 u32 im_brgc7;
608 u32 im_brgc8;
609
610 u8 res5[608];
611
612 i2c_cpm2_t im_i2c; /* I2C control/status */
613 cpm_cpm2_t im_cpm; /* Communication processor */
614
615 /* Second set of baud rate generators.
616 */
617 u32 im_brgc1;
618 u32 im_brgc2;
619 u32 im_brgc3;
620 u32 im_brgc4;
621
622 scc_t im_scc[4]; /* Four SCCs */
623 smc_t im_smc[2]; /* Couple of SMCs */
624 spictl_cpm2_t im_spi; /* A SPI */
625 cpmux_t im_cpmux; /* CPM clock route mux */
626 siramctl_t im_siramctl1; /* First SI RAM Control */
627 mcc_t im_mcc1; /* First MCC */
628 siramctl_t im_siramctl2; /* Second SI RAM Control */
629 mcc_t im_mcc2; /* Second MCC */
630 usb_cpm2_t im_usb; /* USB Controller */
631
632 u8 res6[1153];
633
634 u16 im_si1txram[256];
635 u8 res7[512];
636 u16 im_si1rxram[256];
637 u8 res8[512];
638 u16 im_si2txram[256];
639 u8 res9[512];
640 u16 im_si2rxram[256];
641 u8 res10[512];
642 u8 res11[4096];
643} cpm2_map_t;
644
645extern cpm2_map_t *cpm2_immr;
646
647#endif /* __IMMAP_CPM2__ */
648#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/kgdb.h b/include/asm-powerpc/kgdb.h
new file mode 100644
index 000000000000..b617dac82969
--- /dev/null
+++ b/include/asm-powerpc/kgdb.h
@@ -0,0 +1,57 @@
1/*
2 * kgdb.h: Defines and declarations for serial line source level
3 * remote debugging of the Linux kernel using gdb.
4 *
5 * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9#ifdef __KERNEL__
10#ifndef _PPC_KGDB_H
11#define _PPC_KGDB_H
12
13#ifndef __ASSEMBLY__
14
15/* Things specific to the gen550 backend. */
16struct uart_port;
17
18extern void gen550_progress(char *, unsigned short);
19extern void gen550_kgdb_map_scc(void);
20extern void gen550_init(int, struct uart_port *);
21
22/* Things specific to the pmac backend. */
23extern void zs_kgdb_hook(int tty_num);
24
25/* To init the kgdb engine. (called by serial hook)*/
26extern void set_debug_traps(void);
27
28/* To enter the debugger explicitly. */
29extern void breakpoint(void);
30
31/* For taking exceptions
32 * these are defined in traps.c
33 */
34extern int (*debugger)(struct pt_regs *regs);
35extern int (*debugger_bpt)(struct pt_regs *regs);
36extern int (*debugger_sstep)(struct pt_regs *regs);
37extern int (*debugger_iabr_match)(struct pt_regs *regs);
38extern int (*debugger_dabr_match)(struct pt_regs *regs);
39extern void (*debugger_fault_handler)(struct pt_regs *regs);
40
41/* What we bring to the party */
42int kgdb_bpt(struct pt_regs *regs);
43int kgdb_sstep(struct pt_regs *regs);
44void kgdb(struct pt_regs *regs);
45int kgdb_iabr_match(struct pt_regs *regs);
46int kgdb_dabr_match(struct pt_regs *regs);
47
48/*
49 * external low-level support routines (ie macserial.c)
50 */
51extern void kgdb_interruptible(int); /* control interrupts from serial */
52extern void putDebugChar(char); /* write a single character */
53extern char getDebugChar(void); /* read and return a single char */
54
55#endif /* !(__ASSEMBLY__) */
56#endif /* !(_PPC_KGDB_H) */
57#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h
new file mode 100644
index 000000000000..26690d2b32f5
--- /dev/null
+++ b/include/asm-powerpc/mpc52xx_psc.h
@@ -0,0 +1,191 @@
1/*
2 * include/asm-ppc/mpc52xx_psc.h
3 *
4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5 * PSCs. Theses are shared between multiple drivers since a PSC can be
6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7 *
8 *
9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10 *
11 * Based/Extracted from some header of the 2.4 originally written by
12 * Dale Farnsworth <dfarnsworth@mvista.com>
13 *
14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright (C) 2003 MontaVista, Software, Inc.
16 *
17 * This file is licensed under the terms of the GNU General Public License
18 * version 2. This program is licensed "as is" without any warranty of any
19 * kind, whether express or implied.
20 */
21
22#ifndef __ASM_MPC52xx_PSC_H__
23#define __ASM_MPC52xx_PSC_H__
24
25#include <asm/types.h>
26
27/* Max number of PSCs */
28#define MPC52xx_PSC_MAXNUM 6
29
30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_CDE 0x0080
32#define MPC52xx_PSC_SR_RXRDY 0x0100
33#define MPC52xx_PSC_SR_RXFULL 0x0200
34#define MPC52xx_PSC_SR_TXRDY 0x0400
35#define MPC52xx_PSC_SR_TXEMP 0x0800
36#define MPC52xx_PSC_SR_OE 0x1000
37#define MPC52xx_PSC_SR_PE 0x2000
38#define MPC52xx_PSC_SR_FE 0x4000
39#define MPC52xx_PSC_SR_RB 0x8000
40
41/* PSC Command values */
42#define MPC52xx_PSC_RX_ENABLE 0x0001
43#define MPC52xx_PSC_RX_DISABLE 0x0002
44#define MPC52xx_PSC_TX_ENABLE 0x0004
45#define MPC52xx_PSC_TX_DISABLE 0x0008
46#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
47#define MPC52xx_PSC_RST_RX 0x0020
48#define MPC52xx_PSC_RST_TX 0x0030
49#define MPC52xx_PSC_RST_ERR_STAT 0x0040
50#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
51#define MPC52xx_PSC_START_BRK 0x0060
52#define MPC52xx_PSC_STOP_BRK 0x0070
53
54/* PSC TxRx FIFO status bits */
55#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
56#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
57#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
58#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
59#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
60#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
61#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
62
63/* PSC interrupt mask bits */
64#define MPC52xx_PSC_IMR_TXRDY 0x0100
65#define MPC52xx_PSC_IMR_RXRDY 0x0200
66#define MPC52xx_PSC_IMR_DB 0x0400
67#define MPC52xx_PSC_IMR_IPC 0x8000
68
69/* PSC input port change bit */
70#define MPC52xx_PSC_CTS 0x01
71#define MPC52xx_PSC_DCD 0x02
72#define MPC52xx_PSC_D_CTS 0x10
73#define MPC52xx_PSC_D_DCD 0x20
74
75/* PSC mode fields */
76#define MPC52xx_PSC_MODE_5_BITS 0x00
77#define MPC52xx_PSC_MODE_6_BITS 0x01
78#define MPC52xx_PSC_MODE_7_BITS 0x02
79#define MPC52xx_PSC_MODE_8_BITS 0x03
80#define MPC52xx_PSC_MODE_BITS_MASK 0x03
81#define MPC52xx_PSC_MODE_PAREVEN 0x00
82#define MPC52xx_PSC_MODE_PARODD 0x04
83#define MPC52xx_PSC_MODE_PARFORCE 0x08
84#define MPC52xx_PSC_MODE_PARNONE 0x10
85#define MPC52xx_PSC_MODE_ERR 0x20
86#define MPC52xx_PSC_MODE_FFULL 0x40
87#define MPC52xx_PSC_MODE_RXRTS 0x80
88
89#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
90#define MPC52xx_PSC_MODE_ONE_STOP 0x07
91#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
92
93#define MPC52xx_PSC_RFNUM_MASK 0x01ff
94
95
96/* Structure of the hardware registers */
97struct mpc52xx_psc {
98 u8 mode; /* PSC + 0x00 */
99 u8 reserved0[3];
100 union { /* PSC + 0x04 */
101 u16 status;
102 u16 clock_select;
103 } sr_csr;
104#define mpc52xx_psc_status sr_csr.status
105#define mpc52xx_psc_clock_select sr_csr.clock_select
106 u16 reserved1;
107 u8 command; /* PSC + 0x08 */
108 u8 reserved2[3];
109 union { /* PSC + 0x0c */
110 u8 buffer_8;
111 u16 buffer_16;
112 u32 buffer_32;
113 } buffer;
114#define mpc52xx_psc_buffer_8 buffer.buffer_8
115#define mpc52xx_psc_buffer_16 buffer.buffer_16
116#define mpc52xx_psc_buffer_32 buffer.buffer_32
117 union { /* PSC + 0x10 */
118 u8 ipcr;
119 u8 acr;
120 } ipcr_acr;
121#define mpc52xx_psc_ipcr ipcr_acr.ipcr
122#define mpc52xx_psc_acr ipcr_acr.acr
123 u8 reserved3[3];
124 union { /* PSC + 0x14 */
125 u16 isr;
126 u16 imr;
127 } isr_imr;
128#define mpc52xx_psc_isr isr_imr.isr
129#define mpc52xx_psc_imr isr_imr.imr
130 u16 reserved4;
131 u8 ctur; /* PSC + 0x18 */
132 u8 reserved5[3];
133 u8 ctlr; /* PSC + 0x1c */
134 u8 reserved6[3];
135 u16 ccr; /* PSC + 0x20 */
136 u8 reserved7[14];
137 u8 ivr; /* PSC + 0x30 */
138 u8 reserved8[3];
139 u8 ip; /* PSC + 0x34 */
140 u8 reserved9[3];
141 u8 op1; /* PSC + 0x38 */
142 u8 reserved10[3];
143 u8 op0; /* PSC + 0x3c */
144 u8 reserved11[3];
145 u32 sicr; /* PSC + 0x40 */
146 u8 ircr1; /* PSC + 0x44 */
147 u8 reserved13[3];
148 u8 ircr2; /* PSC + 0x44 */
149 u8 reserved14[3];
150 u8 irsdr; /* PSC + 0x4c */
151 u8 reserved15[3];
152 u8 irmdr; /* PSC + 0x50 */
153 u8 reserved16[3];
154 u8 irfdr; /* PSC + 0x54 */
155 u8 reserved17[3];
156 u16 rfnum; /* PSC + 0x58 */
157 u16 reserved18;
158 u16 tfnum; /* PSC + 0x5c */
159 u16 reserved19;
160 u32 rfdata; /* PSC + 0x60 */
161 u16 rfstat; /* PSC + 0x64 */
162 u16 reserved20;
163 u8 rfcntl; /* PSC + 0x68 */
164 u8 reserved21[5];
165 u16 rfalarm; /* PSC + 0x6e */
166 u16 reserved22;
167 u16 rfrptr; /* PSC + 0x72 */
168 u16 reserved23;
169 u16 rfwptr; /* PSC + 0x76 */
170 u16 reserved24;
171 u16 rflrfptr; /* PSC + 0x7a */
172 u16 reserved25;
173 u16 rflwfptr; /* PSC + 0x7e */
174 u32 tfdata; /* PSC + 0x80 */
175 u16 tfstat; /* PSC + 0x84 */
176 u16 reserved26;
177 u8 tfcntl; /* PSC + 0x88 */
178 u8 reserved27[5];
179 u16 tfalarm; /* PSC + 0x8e */
180 u16 reserved28;
181 u16 tfrptr; /* PSC + 0x92 */
182 u16 reserved29;
183 u16 tfwptr; /* PSC + 0x96 */
184 u16 reserved30;
185 u16 tflrfptr; /* PSC + 0x9a */
186 u16 reserved31;
187 u16 tflwfptr; /* PSC + 0x9e */
188};
189
190
191#endif /* __ASM_MPC52xx_PSC_H__ */
diff --git a/include/asm-ppc/ans-lcd.h b/include/asm-ppc/ans-lcd.h
deleted file mode 100644
index d795b9fd2db6..000000000000
--- a/include/asm-ppc/ans-lcd.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _PPC_ANS_LCD_H
2#define _PPC_ANS_LCD_H
3
4#define ANSLCD_MINOR 156
5
6#define ANSLCD_CLEAR 0x01
7#define ANSLCD_SENDCTRL 0x02
8#define ANSLCD_SETSHORTDELAY 0x03
9#define ANSLCD_SETLONGDELAY 0x04
10
11#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 04:29:29 -0500