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authorJohn Rigby <jrigby@freescale.com>2008-01-28 12:28:56 -0500
committerGrant Likely <grant.likely@secretlab.ca>2008-02-06 16:05:40 -0500
commit25ae3a0739c69425a911925b43213895a9802b98 (patch)
tree250695da67fc1414080f96e55cd68b4d92d6da43 /include
parent599f030cc596cd41a0f966afd4cee2e2fc48ee86 (diff)
[POWERPC] mpc512x: Add MPC512x PSC support to MPC52xx psc driver
Add 512x support using the psc_ops framework established with the previous patch. All 512x PSCs share the same interrupt so add IRQF_SHARED to irq flags. Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/mpc52xx_psc.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h
index bea42b95390f..710c5d36efaa 100644
--- a/include/asm-powerpc/mpc52xx_psc.h
+++ b/include/asm-powerpc/mpc52xx_psc.h
@@ -190,5 +190,53 @@ struct mpc52xx_psc_fifo {
190 u16 tflwfptr; /* PSC + 0x9e */ 190 u16 tflwfptr; /* PSC + 0x9e */
191}; 191};
192 192
193#define MPC512x_PSC_FIFO_RESET_SLICE 0x80
194#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
195#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
196
197#define MPC512x_PSC_FIFO_EMPTY 0x1
198#define MPC512x_PSC_FIFO_FULL 0x2
199#define MPC512x_PSC_FIFO_ALARM 0x4
200#define MPC512x_PSC_FIFO_URERR 0x8
201#define MPC512x_PSC_FIFO_ORERR 0x01
202#define MPC512x_PSC_FIFO_MEMERROR 0x02
203
204struct mpc512x_psc_fifo {
205 u32 reserved1[10];
206 u32 txcmd; /* PSC + 0x80 */
207 u32 txalarm; /* PSC + 0x84 */
208 u32 txsr; /* PSC + 0x88 */
209 u32 txisr; /* PSC + 0x8c */
210 u32 tximr; /* PSC + 0x90 */
211 u32 txcnt; /* PSC + 0x94 */
212 u32 txptr; /* PSC + 0x98 */
213 u32 txsz; /* PSC + 0x9c */
214 u32 reserved2[7];
215 union {
216 u8 txdata_8;
217 u16 txdata_16;
218 u32 txdata_32;
219 } txdata; /* PSC + 0xbc */
220#define txdata_8 txdata.txdata_8
221#define txdata_16 txdata.txdata_16
222#define txdata_32 txdata.txdata_32
223 u32 rxcmd; /* PSC + 0xc0 */
224 u32 rxalarm; /* PSC + 0xc4 */
225 u32 rxsr; /* PSC + 0xc8 */
226 u32 rxisr; /* PSC + 0xcc */
227 u32 rximr; /* PSC + 0xd0 */
228 u32 rxcnt; /* PSC + 0xd4 */
229 u32 rxptr; /* PSC + 0xd8 */
230 u32 rxsz; /* PSC + 0xdc */
231 u32 reserved3[7];
232 union {
233 u8 rxdata_8;
234 u16 rxdata_16;
235 u32 rxdata_32;
236 } rxdata; /* PSC + 0xfc */
237#define rxdata_8 rxdata.rxdata_8
238#define rxdata_16 rxdata.rxdata_16
239#define rxdata_32 rxdata.rxdata_32
240};
193 241
194#endif /* __ASM_MPC52xx_PSC_H__ */ 242#endif /* __ASM_MPC52xx_PSC_H__ */