diff options
author | Joe Perches <joe@perches.com> | 2008-02-03 09:50:59 -0500 |
---|---|---|
committer | Adrian Bunk <bunk@kernel.org> | 2008-02-03 09:50:59 -0500 |
commit | 84c079239db04ee189c658926db06daee4e72267 (patch) | |
tree | df752d29abf36b12f367d461a6518f2275216df3 /include | |
parent | 87b9bcd5aba2916edc0f6ec8814b628160ee7b64 (diff) |
include/asm-arm/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 34 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 34 | ||||
-rw-r--r-- | include/asm-arm/hardware/it8152.h | 2 | ||||
-rw-r--r-- | include/asm-arm/mach/udc_pxa2xx.h | 2 |
4 files changed, 36 insertions, 36 deletions
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 5d949d763a91..1205c28a2078 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | |||
@@ -587,23 +587,23 @@ | |||
587 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | 587 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ |
588 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | 588 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ |
589 | 589 | ||
590 | #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ | 590 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ |
591 | #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ | 591 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ |
592 | #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ | 592 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ |
593 | #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ | 593 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ |
594 | #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ | 594 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ |
595 | #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ | 595 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ |
596 | #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ | 596 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ |
597 | #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ | 597 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ |
598 | 598 | ||
599 | #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ | 599 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ |
600 | #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ | 600 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ |
601 | #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ | 601 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ |
602 | #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ | 602 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ |
603 | #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ | 603 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ |
604 | #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ | 604 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ |
605 | #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ | 605 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ |
606 | #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ | 606 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ |
607 | 607 | ||
608 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | 608 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
609 | 609 | ||
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 442494d71f12..16ed24dbda4e 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
@@ -737,25 +737,25 @@ | |||
737 | 737 | ||
738 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | 738 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ |
739 | 739 | ||
740 | #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ | 740 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ |
741 | #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ | 741 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ |
742 | #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ | 742 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ |
743 | #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ | 743 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ |
744 | #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ | 744 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ |
745 | #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ | 745 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ |
746 | #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ | 746 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ |
747 | #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ | 747 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ |
748 | 748 | ||
749 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | 749 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ |
750 | 750 | ||
751 | #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ | 751 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ |
752 | #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ | 752 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ |
753 | #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ | 753 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ |
754 | #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ | 754 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ |
755 | #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ | 755 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ |
756 | #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ | 756 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ |
757 | #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ | 757 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ |
758 | #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ | 758 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ |
759 | 759 | ||
760 | #elif defined(CONFIG_PXA27x) | 760 | #elif defined(CONFIG_PXA27x) |
761 | 761 | ||
@@ -1020,7 +1020,7 @@ | |||
1020 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ | 1020 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ |
1021 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ | 1021 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ |
1022 | 1022 | ||
1023 | #define ICCR0_AME (1 << 7) /* Adress match enable */ | 1023 | #define ICCR0_AME (1 << 7) /* Address match enable */ |
1024 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ | 1024 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ |
1025 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ | 1025 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ |
1026 | #define ICCR0_RXE (1 << 4) /* Receive enable */ | 1026 | #define ICCR0_RXE (1 << 4) /* Receive enable */ |
diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h index aaebb61aca48..74b5fff7f575 100644 --- a/include/asm-arm/hardware/it8152.h +++ b/include/asm-arm/hardware/it8152.h | |||
@@ -42,7 +42,7 @@ extern unsigned long it8152_base_address; | |||
42 | #define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) | 42 | #define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) |
43 | 43 | ||
44 | /* | 44 | /* |
45 | Interrup contoler per register summary: | 45 | Interrupt controller per register summary: |
46 | --------------------------------------- | 46 | --------------------------------------- |
47 | LCDNIRR: | 47 | LCDNIRR: |
48 | IT8152_LD_IRQ(8) PCICLK stop | 48 | IT8152_LD_IRQ(8) PCICLK stop |
diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h index f191e147ea90..f9f3606986c2 100644 --- a/include/asm-arm/mach/udc_pxa2xx.h +++ b/include/asm-arm/mach/udc_pxa2xx.h | |||
@@ -16,7 +16,7 @@ struct pxa2xx_udc_mach_info { | |||
16 | #define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ | 16 | #define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ |
17 | 17 | ||
18 | /* Boards following the design guidelines in the developer's manual, | 18 | /* Boards following the design guidelines in the developer's manual, |
19 | * with on-chip GPIOs not Lubbock's wierd hardware, can have a sane | 19 | * with on-chip GPIOs not Lubbock's weird hardware, can have a sane |
20 | * VBUS IRQ and omit the methods above. Store the GPIO number | 20 | * VBUS IRQ and omit the methods above. Store the GPIO number |
21 | * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits. | 21 | * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits. |
22 | * Note that sometimes the signals go through inverters... | 22 | * Note that sometimes the signals go through inverters... |