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authorColin Ngam <cngam@sgi.com>2005-04-25 16:07:00 -0400
committerTony Luck <tony.luck@intel.com>2005-04-25 16:07:00 -0400
commit658b32cad9ae087bd34f35a925fd75b76d663d4e (patch)
treeb742c5e1e756912fe6f6a81ebb4a9db814c641e7 /include
parentbe539c73b54dcc9f54fb2c2b70e204c93b616c9b (diff)
[IA64-SGI] support variable length nasids in shub2
This patch enables our TIO IO chipset to support variable length nasids in Shub2 chipset. Signed-off-by: Colin Ngam <cngam@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ia64/sn/addrs.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index c916bd22767a..ae0bc99d573e 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -154,8 +154,9 @@
154 * the chiplet id is zero. If we implement TIO-TIO dma, we might need 154 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
155 * to insert a chiplet id into this macro. However, it is our belief 155 * to insert a chiplet id into this macro. However, it is our belief
156 * right now that this chiplet id will be ICE, which is also zero. 156 * right now that this chiplet id will be ICE, which is also zero.
157 * Nasid starts on bit 40.
157 */ 158 */
158#define PHYS_TO_TIODMA(x) ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x)) 159#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
159#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) 160#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
160 161
161 162