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authorTimur Tabi <timur@freescale.com>2007-10-02 17:27:13 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-10-08 09:38:50 -0400
commit090fe850f9520eaedf6de50877e0c5b95349f225 (patch)
treeab691648b15b2ea965133f7e5a29429c005831ec /include
parente1c1575f831ab2165732037e6d664010a0149730 (diff)
[POWERPC] 86xx: update immap_86xx.h for the 8610
Update the definition of the global utilities structure (ccsr_guts) in immap_86xx.h and add some related macros for the Freescale 8610 SOC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/immap_86xx.h86
1 files changed, 78 insertions, 8 deletions
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
index c83d7ad16606..0ad4e653d464 100644
--- a/include/asm-powerpc/immap_86xx.h
+++ b/include/asm-powerpc/immap_86xx.h
@@ -38,7 +38,8 @@ struct ccsr_guts {
38 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ 38 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
39 u8 res6[0x70 - 0x64]; 39 u8 res6[0x70 - 0x64];
40 __be32 devdisr; /* 0x.0070 - Device Disable Control */ 40 __be32 devdisr; /* 0x.0070 - Device Disable Control */
41 u8 res7[0x80 - 0x74]; 41 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
42 u8 res7[0x80 - 0x78];
42 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ 43 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
43 u8 res8[0x90 - 0x84]; 44 u8 res8[0x90 - 0x84];
44 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 45 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
@@ -48,18 +49,87 @@ struct ccsr_guts {
48 __be32 svr; /* 0x.00a4 - System Version Register */ 49 __be32 svr; /* 0x.00a4 - System Version Register */
49 u8 res10[0xB0 - 0xA8]; 50 u8 res10[0xB0 - 0xA8];
50 __be32 rstcr; /* 0x.00b0 - Reset Control Register */ 51 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
51 u8 res11[0xB20 - 0xB4]; 52 u8 res11[0xC0 - 0xB4];
52 __be32 ddr1clkdr; /* 0x.0b20 - DDRC1 Clock Disable Register */ 53 __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
53 __be32 ddr2clkdr; /* 0x.0b24 - DDRC2 Clock Disable Register */ 54 u8 res12[0x800 - 0xC4];
54 u8 res12[0xE00 - 0xB28]; 55 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
56 u8 res13[0x900 - 0x804];
57 __be32 ircr; /* 0x.0900 - Infrared Control Register */
58 u8 res14[0x908 - 0x904];
59 __be32 dmacr; /* 0x.0908 - DMA Control Register */
60 u8 res15[0x914 - 0x90C];
61 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
62 u8 res16[0xB20 - 0x918];
63 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
64 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
65 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
66 u8 res17[0xE00 - 0xB2C];
55 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 67 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
56 u8 res13[0xF04 - 0xE04]; 68 u8 res18[0xE10 - 0xE04];
69 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
70 u8 res19[0xE20 - 0xE14];
71 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
72 u8 res20[0xF04 - 0xE24];
57 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 73 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
58 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 74 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
59 u8 res14[0xF40 - 0xF0C]; 75 u8 res21[0xF40 - 0xF0C];
60 __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ 76 __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */
61 __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ 77 __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */
62}; 78} __attribute__ ((packed));
79
80#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
81#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
82
83/*
84 * Set the DMACR register in the GUTS
85 *
86 * The DMACR register determines the source of initiated transfers for each
87 * channel on each DMA controller. Rather than have a bunch of repetitive
88 * macros for the bit patterns, we just have a function that calculates
89 * them.
90 *
91 * guts: Pointer to GUTS structure
92 * co: The DMA controller (1 or 2)
93 * ch: The channel on the DMA controller (0, 1, 2, or 3)
94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
95 */
96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device)
98{
99 unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch));
100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102}
103
104#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
105#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
106#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
107#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
108#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
109#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
110#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
111#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
112#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
113#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
114#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
115#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
116#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
117#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
120
121#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
122#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
123#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
124#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
125#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
126#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
127 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
128#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
129#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
130#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
131#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
132#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
63 133
64#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ 134#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
65#endif /* __KERNEL__ */ 135#endif /* __KERNEL__ */