manual update from upstream:

Applied Al's change 06a544971fad0992fe8b92c5647538d573089dd4
to new location of swiotlb.c

Signed-off-by: Tony Luck <tony.luck@intel.com>

649 files changed, 18553 insertions, 9561 deletions

diff --git a/include/asm-alpha/atomic.h b/include/asm-alpha/atomic.h
index 1b383e3cb68c..20ac3d95ecd9 100644
--- a/include/asm-alpha/atomic.h
+++ b/include/asm-alpha/atomic.h
@@ -1,6 +1,8 @@
 #ifndef _ALPHA_ATOMIC_H
 #define _ALPHA_ATOMIC_H
 
+#include <asm/barrier.h>
+
 /*
  * Atomic operations that C can't guarantee us.  Useful for
  * resource counting etc...
@@ -100,18 +102,19 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
 static __inline__ long atomic_add_return(int i, atomic_t * v)
 {
         long temp, result;
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldl_l %0,%1\n"
         "       addl %0,%3,%2\n"
         "       addl %0,%3,%0\n"
         "       stl_c %0,%1\n"
         "       beq %0,2f\n"
-        "       mb\n"
         ".subsection 2\n"
         "2:     br 1b\n"
         ".previous"
         :"=&r" (temp), "=m" (v->counter), "=&r" (result)
         :"Ir" (i), "m" (v->counter) : "memory");
+        smp_mb();
         return result;
 }
 
@@ -120,54 +123,57 @@ static __inline__ long atomic_add_return(int i, atomic_t * v)
 static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 {
         long temp, result;
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldq_l %0,%1\n"
         "       addq %0,%3,%2\n"
         "       addq %0,%3,%0\n"
         "       stq_c %0,%1\n"
         "       beq %0,2f\n"
-        "       mb\n"
         ".subsection 2\n"
         "2:     br 1b\n"
         ".previous"
         :"=&r" (temp), "=m" (v->counter), "=&r" (result)
         :"Ir" (i), "m" (v->counter) : "memory");
+        smp_mb();
         return result;
 }
 
 static __inline__ long atomic_sub_return(int i, atomic_t * v)
 {
         long temp, result;
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldl_l %0,%1\n"
         "       subl %0,%3,%2\n"
         "       subl %0,%3,%0\n"
         "       stl_c %0,%1\n"
         "       beq %0,2f\n"
-        "       mb\n"
         ".subsection 2\n"
         "2:     br 1b\n"
         ".previous"
         :"=&r" (temp), "=m" (v->counter), "=&r" (result)
         :"Ir" (i), "m" (v->counter) : "memory");
+        smp_mb();
         return result;
 }
 
 static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 {
         long temp, result;
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldq_l %0,%1\n"
         "       subq %0,%3,%2\n"
         "       subq %0,%3,%0\n"
         "       stq_c %0,%1\n"
         "       beq %0,2f\n"
-        "       mb\n"
         ".subsection 2\n"
         "2:     br 1b\n"
         ".previous"
         :"=&r" (temp), "=m" (v->counter), "=&r" (result)
         :"Ir" (i), "m" (v->counter) : "memory");
+        smp_mb();
         return result;
 }
 
diff --git a/include/asm-alpha/barrier.h b/include/asm-alpha/barrier.h
new file mode 100644
index 000000000000..681ff581afa5
--- /dev/null
+++ b/include/asm-alpha/barrier.h
@@ -0,0 +1,36 @@
+#ifndef __BARRIER_H
+#define __BARRIER_H
+
+#include <asm/compiler.h>
+
+#define mb() \
+__asm__ __volatile__("mb": : :"memory")
+
+#define rmb() \
+__asm__ __volatile__("mb": : :"memory")
+
+#define wmb() \
+__asm__ __volatile__("wmb": : :"memory")
+
+#define read_barrier_depends() \
+__asm__ __volatile__("mb": : :"memory")
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      barrier()
+#endif
+
+#define set_mb(var, value) \
+do { var = value; mb(); } while (0)
+
+#define set_wmb(var, value) \
+do { var = value; wmb(); } while (0)
+
+#endif          /* __BARRIER_H */
diff --git a/include/asm-alpha/dma-mapping.h b/include/asm-alpha/dma-mapping.h
index c675f282d6ad..680f7ecbb28f 100644
--- a/include/asm-alpha/dma-mapping.h
+++ b/include/asm-alpha/dma-mapping.h
@@ -31,7 +31,7 @@
 #else   /* no PCI - no IOMMU. */
 
 void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, int gfp);
+                         dma_addr_t *dma_handle, gfp_t gfp);
 int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
                enum dma_data_direction direction);
 
diff --git a/include/asm-alpha/rwsem.h b/include/asm-alpha/rwsem.h
index 8e058a67c9a4..fafdd4f7010a 100644
--- a/include/asm-alpha/rwsem.h
+++ b/include/asm-alpha/rwsem.h
@@ -262,5 +262,10 @@ static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem)
 #endif
 }
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* __KERNEL__ */
 #endif /* _ALPHA_RWSEM_H */
diff --git a/include/asm-alpha/semaphore.h b/include/asm-alpha/semaphore.h
index eb2cbd97d404..1a6295f2c2d4 100644
--- a/include/asm-alpha/semaphore.h
+++ b/include/asm-alpha/semaphore.h
@@ -26,9 +26,6 @@ struct semaphore {
         .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
 
-#define __MUTEX_INITIALIZER(name)                       \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count)         \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h
index bdb4d66418f1..050e86d12891 100644
--- a/include/asm-alpha/system.h
+++ b/include/asm-alpha/system.h
@@ -4,6 +4,7 @@
 #include <linux/config.h>
 #include <asm/pal.h>
 #include <asm/page.h>
+#include <asm/barrier.h>
 
 /*
  * System defines.. Note that this is included both from .c and .S
@@ -139,36 +140,6 @@ extern void halt(void) __attribute__((noreturn));
 struct task_struct;
 extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*);
 
-#define mb() \
-__asm__ __volatile__("mb": : :"memory")
-
-#define rmb() \
-__asm__ __volatile__("mb": : :"memory")
-
-#define wmb() \
-__asm__ __volatile__("wmb": : :"memory")
-
-#define read_barrier_depends() \
-__asm__ __volatile__("mb": : :"memory")
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      barrier()
-#endif
-
-#define set_mb(var, value) \
-do { var = value; mb(); } while (0)
-
-#define set_wmb(var, value) \
-do { var = value; wmb(); } while (0)
-
 #define imb() \
 __asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
 
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
index 0e9b7e18af05..002227924b9f 100644
--- a/include/asm-arm/arch-aaec2000/aaec2000.h
+++ b/include/asm-arm/arch-aaec2000/aaec2000.h
@@ -17,6 +17,16 @@
 #error You must include hardware.h not this file
 #endif /* __ASM_ARCH_HARDWARE_H */
 
+/* Chip selects */
+#define AAEC_CS0        0x00000000
+#define AAEC_CS1        0x10000000
+#define AAEC_CS2        0x20000000
+#define AAEC_CS3        0x30000000
+
+/* Flash */
+#define AAEC_FLASH_BASE AAEC_CS0
+#define AAEC_FLASH_SIZE SZ_64M
+
 /* Interrupt controller */
 #define IRQ_BASE        __REG(0x80000500)
 #define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
@@ -148,4 +158,50 @@
 #define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
 #define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
 
+/* GPIO Registers */
+#define AAEC_GPIO_PHYS  0x80000e00
+
+#define AAEC_GPIO_PADR          __REG(AAEC_GPIO_PHYS + 0x00)
+#define AAEC_GPIO_PBDR          __REG(AAEC_GPIO_PHYS + 0x04)
+#define AAEC_GPIO_PCDR          __REG(AAEC_GPIO_PHYS + 0x08)
+#define AAEC_GPIO_PDDR          __REG(AAEC_GPIO_PHYS + 0x0c)
+#define AAEC_GPIO_PADDR         __REG(AAEC_GPIO_PHYS + 0x10)
+#define AAEC_GPIO_PBDDR         __REG(AAEC_GPIO_PHYS + 0x14)
+#define AAEC_GPIO_PCDDR         __REG(AAEC_GPIO_PHYS + 0x18)
+#define AAEC_GPIO_PDDDR         __REG(AAEC_GPIO_PHYS + 0x1c)
+#define AAEC_GPIO_PEDR          __REG(AAEC_GPIO_PHYS + 0x20)
+#define AAEC_GPIO_PEDDR         __REG(AAEC_GPIO_PHYS + 0x24)
+#define AAEC_GPIO_KSCAN         __REG(AAEC_GPIO_PHYS + 0x28)
+#define AAEC_GPIO_PINMUX        __REG(AAEC_GPIO_PHYS + 0x2c)
+#define AAEC_GPIO_PFDR          __REG(AAEC_GPIO_PHYS + 0x30)
+#define AAEC_GPIO_PFDDR         __REG(AAEC_GPIO_PHYS + 0x34)
+#define AAEC_GPIO_PGDR          __REG(AAEC_GPIO_PHYS + 0x38)
+#define AAEC_GPIO_PGDDR         __REG(AAEC_GPIO_PHYS + 0x3c)
+#define AAEC_GPIO_PHDR          __REG(AAEC_GPIO_PHYS + 0x40)
+#define AAEC_GPIO_PHDDR         __REG(AAEC_GPIO_PHYS + 0x44)
+#define AAEC_GPIO_RAZ           __REG(AAEC_GPIO_PHYS + 0x48)
+#define AAEC_GPIO_INTTYPE1      __REG(AAEC_GPIO_PHYS + 0x4c)
+#define AAEC_GPIO_INTTYPE2      __REG(AAEC_GPIO_PHYS + 0x50)
+#define AAEC_GPIO_FEOI          __REG(AAEC_GPIO_PHYS + 0x54)
+#define AAEC_GPIO_INTEN         __REG(AAEC_GPIO_PHYS + 0x58)
+#define AAEC_GPIO_INTSTATUS     __REG(AAEC_GPIO_PHYS + 0x5c)
+#define AAEC_GPIO_RAWINTSTATUS  __REG(AAEC_GPIO_PHYS + 0x60)
+#define AAEC_GPIO_DB            __REG(AAEC_GPIO_PHYS + 0x64)
+#define AAEC_GPIO_PAPINDR       __REG(AAEC_GPIO_PHYS + 0x68)
+#define AAEC_GPIO_PBPINDR       __REG(AAEC_GPIO_PHYS + 0x6c)
+#define AAEC_GPIO_PCPINDR       __REG(AAEC_GPIO_PHYS + 0x70)
+#define AAEC_GPIO_PDPINDR       __REG(AAEC_GPIO_PHYS + 0x74)
+#define AAEC_GPIO_PEPINDR       __REG(AAEC_GPIO_PHYS + 0x78)
+#define AAEC_GPIO_PFPINDR       __REG(AAEC_GPIO_PHYS + 0x7c)
+#define AAEC_GPIO_PGPINDR       __REG(AAEC_GPIO_PHYS + 0x80)
+#define AAEC_GPIO_PHPINDR       __REG(AAEC_GPIO_PHYS + 0x84)
+
+#define AAEC_GPIO_PINMUX_PE0CON         (1 << 0)
+#define AAEC_GPIO_PINMUX_PD0CON         (1 << 1)
+#define AAEC_GPIO_PINMUX_CODECON        (1 << 2)
+#define AAEC_GPIO_PINMUX_UART3CON       (1 << 3)
+
+/* LCD Controller */
+#define AAEC_CLCD_PHYS  0x80003000
+
 #endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/include/asm-arm/arch-aaec2000/aaed2000.h b/include/asm-arm/arch-aaec2000/aaed2000.h
new file mode 100644
index 000000000000..bc76d2badb91
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/aaed2000.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/aaed2000.h
+ *
+ *  AAED-2000 specific bits definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_AAED2000_H
+#define __ASM_ARCH_AAED2000_H
+
+/* External GPIOs. */
+
+#define EXT_GPIO_PBASE  AAEC_CS3
+#define EXT_GPIO_VBASE  0xf8100000
+#define EXT_GPIO_LENGTH 0x00001000
+
+#define __ext_gpio_p2v(x)       ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
+#define __ext_gpio_v2p(x)       ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
+
+#define __EXT_GPIO_REG(x)       (*((volatile u32 *)__ext_gpio_p2v(x)))
+#define __EXT_GPIO_PREG(x)      (__ext_gpio_v2p((u32)&(x)))
+
+#define AAED_EXT_GPIO   __EXT_GPIO_REG(EXT_GPIO_PBASE)
+
+#define AAED_EGPIO_KBD_SCAN     0x00003fff /* Keyboard scan data */
+#define AAED_EGPIO_PWR_INT      0x00008fff /* Smart battery charger interrupt */
+#define AAED_EGPIO_SWITCHED     0x000f0000 /* DIP Switches */
+#define AAED_EGPIO_USB_VBUS     0x00400000 /* USB Vbus sense */
+#define AAED_EGPIO_LCD_PWR_EN   0x02000000 /* LCD and backlight PWR enable */
+#define AAED_EGPIO_nLED0        0x20000000 /* LED 0 */
+#define AAED_EGPIO_nLED1        0x20000000 /* LED 1 */
+#define AAED_EGPIO_nLED2        0x20000000 /* LED 2 */
+
+
+#endif /* __ARM_ARCH_AAED2000_H */
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h
index 4c37219e030e..153506fd06ed 100644
--- a/include/asm-arm/arch-aaec2000/hardware.h
+++ b/include/asm-arm/arch-aaec2000/hardware.h
@@ -11,7 +11,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <linux/config.h>
+#include <asm/sizes.h>
+#include <asm/arch/aaec2000.h>
 
 /* The kernel is loaded at physical address 0xf8000000.
  * We map the IO space a bit after
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
index c58a8d10425a..8d67907fd4f0 100644
--- a/include/asm-arm/arch-aaec2000/io.h
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 79c90813bc3e..d8209f8911d6 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -13,7 +13,7 @@
 
 #include <linux/config.h>
 
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
diff --git a/include/asm-arm/arch-cl7500/io.h b/include/asm-arm/arch-cl7500/io.h
index f0113bc75630..89a33287f4fe 100644
--- a/include/asm-arm/arch-cl7500/io.h
+++ b/include/asm-arm/arch-cl7500/io.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h
index 9776bba8e585..34f40a6cec30 100644
--- a/include/asm-arm/arch-cl7500/memory.h
+++ b/include/asm-arm/arch-cl7500/memory.h
@@ -17,7 +17,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 
 /*
  * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
index 1386871e1a5a..f864c367c934 100644
--- a/include/asm-arm/arch-clps711x/hardware.h
+++ b/include/asm-arm/arch-clps711x/hardware.h
@@ -235,4 +235,121 @@
 #define CEIVA_PB0_BLK_BTN       (1<<0)
 #endif // #if defined (CONFIG_ARCH_CEIVA)
 
+#if defined (CONFIG_MACH_MP1000)
+/* NOR FLASH */
+#define MP1000_NIO_BASE         0xf9000000      /* virtual */
+#define MP1000_NIO_START        CS0_PHYS_BASE   /* physical */
+#define MP1000_NIO_SIZE         0x00400000
+
+/* DSP Interface */
+#define MP1000_DSP_BASE         0xfa000000      /* virtual */
+#define MP1000_DSP_START        CS1_PHYS_BASE   /* physical */
+#define MP1000_DSP_SIZE         0x00100000
+
+/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
+#define MP1000_LIO_BASE         0xfb000000      /* virtual */
+#define MP1000_LIO_START        CS2_PHYS_BASE   /* physical */
+#define MP1000_LIO_SIZE         0x00100000
+
+/* NAND FLASH */
+#define MP1000_FIO_BASE         0xfc000000      /* virtual */
+#define MP1000_FIO_START        CS3_PHYS_BASE   /* physical */
+#define MP1000_FIO_SIZE         0x00800000
+
+/* Ethernet */
+#define MP1000_EIO_BASE         0xfd000000      /* virtual      */
+#define MP1000_EIO_START        CS4_PHYS_BASE   /* physical     */
+#define MP1000_EIO_SIZE         0x00100000
+
+#define MP1000_LCD_OFFSET       0x00000000      /* LCD offset in CS2 */
+#define MP1000_DDD_OFFSET       0x00001000      /* DAA/DAI/DSP sft reset offst*/
+#define MP1000_RTC_OFFSET       0x00002000      /* RTC offset in CS2 */
+#define MP1000_DAA_OFFSET       0x00003000      /* DAA RW reg offset in CS2 */
+
+/* IDE */
+#define MP1000_IDE_BASE         0xfe000000      /* virtual */
+#define MP1000_IDE_START        CS5_PHYS_BASE      /* physical */
+#define MP1000_IDE_SIZE         0x00100000      /* actually it's only 0x1000 */
+
+#define IRQ_HARDDISK IRQ_EINT2
+
+/*
+ * IDE registers definition
+ */
+
+#define IDE_CONTROL_BASE                (MP1000_IDE_BASE + 0x1000)
+#define IDE_BASE_OFF                    (MP1000_IDE_BASE)
+
+#define IDE_WRITE_DEVICE_DATA           (IDE_BASE_OFF + 0x0)
+#define IDE_FEATURES_REGISTER           (IDE_BASE_OFF + 0x2)
+#define IDE_SECTOR_COUNT_REGISTER       (IDE_BASE_OFF + 0x4)
+#define IDE_SECTOR_NUMBER_REGISTER      (IDE_BASE_OFF + 0x6)
+#define IDE_CYLINDER_LOW_REGISTER       (IDE_BASE_OFF + 0x8)
+#define IDE_CYLINDER_HIGH_REGISTER      (IDE_BASE_OFF + 0xa)
+#define IDE_DEVICE_HEAD_REGISTER        (IDE_BASE_OFF + 0xc)
+#define IDE_COMMAND_DATA_REGISTER       (IDE_BASE_OFF + 0xe)
+#define IDE_DEVICE_CONTROL_REGISTER     (IDE_CONTROL_BASE + 0xc)
+
+#define IDE_IRQ                      IRQ_EINT2
+
+
+#define RTC_PORT(x)     (MP1000_LIO_BASE+0x2000 + (x*2))
+#define RTC_ALWAYS_BCD  0
+
+/*
+// Definitions of the bit fields in the HwPortA register for the
+// MP1000 board.
+*/
+#define HwPortAKeyboardRow1                     0x00000001
+#define HwPortAKeyboardRow2                     0x00000002
+#define HwPortAKeyboardRow3                     0x00000004
+#define HwPortAKeyboardRow4                     0x00000008
+#define HwPortAKeyboardRow5                     0x00000010
+#define HwPortAKeyboardRow6                     0x00000020
+#define HwPortALCDEnable                        0x00000040
+#define HwPortAOffhook                          0x00000080
+
+/*
+// Definitions of the bit fields in the HwPortB register for the
+// MP1000 board.
+*/
+#define HwPortBL3Mode                           0x00000001
+#define HwPortBL3Clk                            0x00000002
+#define HwPortBSClk                             0x00000001
+#define HwPortBSData                            0x00000002
+#define HwPortBL3Data                           0x00000004
+#define HwPortBMute                             0x00000008
+#define HwPortBQD0                              0x00000010
+#define HwPortBQD1                              0x00000020
+#define HwPortBQD2                              0x00000040
+#define HwPortBQD3                              0x00000080
+
+/*
+// Definitions of the bit fields in the HwPortD register for the
+// MP1000 board.
+*/
+#define HwPortDLED1                             0x00000001
+#define HwPortDLED2                             0x00000002
+#define HwPortDLED3                             0x00000004
+#define HwPortDLED4                             0x00000008
+#define HwPortDLED5                             0x00000010
+#define HwPortDEECS                             0x00000020
+#define HwPortBRTS                              0x00000040
+#define HwPortBRI                               0x00000080
+
+
+/*
+// Definitions of the bit fields in the HwPortE register for the
+// MP1000 board.
+*/
+
+#define HwPortECLE                              0x00000001
+#define HwPortESepromDOut                       0x00000001
+#define HwPortEALE                              0x00000002
+#define HwPortESepromDIn                        0x00000002
+#define HwPortENANDCS                           0x00000004
+#define HwPortESepromCLK                        0x00000004
+
+#endif // #if defined (CONFIG_MACH_MP1000)
+
 #endif
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
index 14d7e8da5453..62613b0e2d96 100644
--- a/include/asm-arm/arch-clps711x/io.h
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 #define __io(a)                 ((void __iomem *)(a))
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index bd978947db42..61d8717406ce 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -25,7 +25,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-clps711x/mp1000-seprom.h b/include/asm-arm/arch-clps711x/mp1000-seprom.h
new file mode 100644
index 000000000000..3e5566cf9666
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/mp1000-seprom.h
@@ -0,0 +1,77 @@
+#ifndef MP1000_SEPROM_H
+#define MP1000_SEPROM_H
+
+/*
+ * mp1000-seprom.h
+ *
+ *
+ *  This file contains the Serial EEPROM definitions for the MP1000 board
+ *
+ *  Copyright (C) 2005 Comdial Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#define COMMAND_ERASE           (0x1C0)
+#define COMMAND_ERASE_ALL       (0x120)
+#define COMMAND_WRITE_DISABLE   (0x100)
+#define COMMAND_WRITE_ENABLE    (0x130)
+#define COMMAND_READ            (0x180)
+#define COMMAND_WRITE           (0x140)
+#define COMMAND_WRITE_ALL       (0x110)
+
+//
+// Serial EEPROM data format
+//
+
+#define PACKED __attribute__ ((packed))
+
+typedef struct _EEPROM {
+        union {
+                unsigned char eprom_byte_data[128];
+                unsigned short eprom_short_data[64];
+                struct {
+                        unsigned char version PACKED;   // EEPROM Version "1" for now
+                        unsigned char box_id PACKED;    // Box ID (Standalone, SOHO, embedded, etc)
+                        unsigned char major_hw_version PACKED;  // Major Hardware version (Hex)
+                        unsigned char minor_hw_version PACKED;  // Minor Hardware Version (Hex)
+                        unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
+                        unsigned char mfg_serial_number[10] PACKED;     // Manufacturer Serial number
+                        unsigned char mfg_date[3] PACKED;       // Date of Mfg (Formatted YY:MM:DD)
+                        unsigned char country PACKED;   // Country of deployment
+                        unsigned char mac_Address[6] PACKED;    // MAC Address
+                        unsigned char oem_string[20] PACKED;    // OEM ID string
+                        unsigned short feature_bits1 PACKED;    // Feature Bits 1
+                        unsigned short feature_bits2 PACKED;    // Feature Bits 2
+                        unsigned char filler[75] PACKED;                // Unused/Undefined     “0” initialized
+                        unsigned short checksum PACKED;         // byte accumulated short checksum
+                } eprom_struct;
+        } variant;
+}  eeprom_struct;
+
+/* These settings must be mutually exclusive */
+#define FEATURE_BITS1_DRAMSIZE_16MEG    0x0001  /* 0 signifies 4 MEG system */
+#define FEATURE_BITS1_DRAMSIZE_8MEG     0x0002  /* 1 in bit 1 = 8MEG system */
+#define FEATURE_BITS1_DRAMSIZE_64MEG    0x0004  /* 1 in bit 2 = 64MEG system */
+
+#define FEATURE_BITS1_CPUIS90MEG     0x0010
+
+extern void seprom_init(void);
+extern eeprom_struct* get_seprom_ptr(void);
+extern unsigned char* get_eeprom_mac_address(void);
+
+#endif /* MP1000_SEPROM_H */
+
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h
index 5a9493e12275..02f144520c10 100644
--- a/include/asm-arm/arch-ebsa110/memory.h
+++ b/include/asm-arm/arch-ebsa110/memory.h
@@ -19,7 +19,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 
 /*
  * We keep this 1:1 so that we don't interfere
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
index 70576b17f922..776f9d377057 100644
--- a/include/asm-arm/arch-ebsa285/io.h
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffff
 
 /*
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index d0466f9987d3..09e335cd687d 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -46,14 +46,14 @@ extern unsigned long __bus_to_virt(unsigned long);
 #if defined(CONFIG_ARCH_FOOTBRIDGE)
 
 /* Task size and page offset at 3GB */
-#define TASK_SIZE               (0xbf000000UL)
-#define PAGE_OFFSET             (0xc0000000UL)
+#define TASK_SIZE               UL(0xbf000000)
+#define PAGE_OFFSET             UL(0xc0000000)
 
 #elif defined(CONFIG_ARCH_CO285)
 
 /* Task size and page offset at 1.5GB */
-#define TASK_SIZE               (0x5f000000UL)
-#define PAGE_OFFSET             (0x60000000UL)
+#define TASK_SIZE               UL(0x5f000000)
+#define PAGE_OFFSET             UL(0x60000000)
 
 #else
 
@@ -64,7 +64,7 @@ extern unsigned long __bus_to_virt(unsigned long);
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET             (0x00000000UL)
+#define PHYS_OFFSET             UL(0x00000000)
 
 /*
  * This decides where the kernel will search for a free chunk of vm
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
index 1f0afa257621..9fe100c9d6be 100644
--- a/include/asm-arm/arch-epxa10db/io.h
+++ b/include/asm-arm/arch-epxa10db/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffff
 
 
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h
index 3f86bf7f67f0..999541b6a9f5 100644
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ b/include/asm-arm/arch-epxa10db/memory.h
@@ -23,7 +23,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-h720x/io.h b/include/asm-arm/arch-h720x/io.h
index 68814828c9a7..d3ccfd8172b7 100644
--- a/include/asm-arm/arch-h720x/io.h
+++ b/include/asm-arm/arch-h720x/io.h
@@ -14,7 +14,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 
 #define IO_SPACE_LIMIT 0xffffffff
 
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h
index 5633447af268..4a1bfd78a0fe 100644
--- a/include/asm-arm/arch-h720x/memory.h
+++ b/include/asm-arm/arch-h720x/memory.h
@@ -11,7 +11,7 @@
  * Page offset:
  *    ( 0xc0000000UL )
  */
-#define PHYS_OFFSET     (0x40000000UL)
+#define PHYS_OFFSET     UL(0x40000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h
index 28a4cca6a4cb..b191cdd05576 100644
--- a/include/asm-arm/arch-imx/io.h
+++ b/include/asm-arm/arch-imx/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 #define __io(a)         ((void __iomem *)(a))
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
index 116a91fa14f1..d09ae32cd2f4 100644
--- a/include/asm-arm/arch-imx/memory.h
+++ b/include/asm-arm/arch-imx/memory.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_MMU_H
 #define __ASM_ARCH_MMU_H
 
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h
index be2716eeaa02..6f0947bc500d 100644
--- a/include/asm-arm/arch-integrator/hardware.h
+++ b/include/asm-arm/arch-integrator/hardware.h
@@ -33,15 +33,6 @@
 #define IO_SIZE                 0x0B000000                 // How much?
 #define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
 
-/*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-
 #define PCIO_BASE               PCI_IO_VADDR
 #define PCIMEM_BASE             PCI_MEMORY_VADDR
 
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
index fbea8be67d26..31f2deab51b0 100644
--- a/include/asm-arm/arch-integrator/io.h
+++ b/include/asm-arm/arch-integrator/io.h
@@ -22,6 +22,14 @@
 
 #define IO_SPACE_LIMIT 0xffff
 
+/*
+ * WARNING: this has to mirror definitions in platform.h
+ */
+#define PCI_MEMORY_VADDR        0xe8000000
+#define PCI_CONFIG_VADDR        0xec000000
+#define PCI_V3_VADDR            0xed000000
+#define PCI_IO_VADDR            0xee000000
+
 #define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            ((a) + PCI_MEMORY_VADDR)
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
index 2087ea7d28a9..1ab56d783e7c 100644
--- a/include/asm-arm/arch-integrator/memory.h
+++ b/include/asm-arm/arch-integrator/memory.h
@@ -23,8 +23,8 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x00000000UL)
-#define BUS_OFFSET      (0x80000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
+#define BUS_OFFSET      UL(0x80000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
index 2761dfd8694d..f39046a6ab14 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 #define __io(p)                 ((void __iomem *)(p))
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
index 45351f5cd904..bc62f4b13235 100644
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -12,9 +12,9 @@
  * Physical DRAM offset.
  */
 #ifndef CONFIG_ARCH_IOP331
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 #else
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #endif
 
 /*
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 3241cd6f0778..7fbcdf9931ee 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT          0xffffffff
 #define __mem_pci(a)            (a)
 
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b768009c3a51..c6d51426e98f 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -22,7 +22,7 @@
 #define IXDP2X01_CPLD_REGION_SIZE       0x00100000
 
 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
-#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
 
 #define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
 #define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 32aece069869..def089d693d2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -392,4 +392,47 @@
 #define WDT_RESET_ENABLE                0x01000000
 
 
+/*
+ * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
+ * units, but the registers that differ between the two don't overlap,
+ * so we can have one register list for both.
+ */
+#define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
+#define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
+#define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
+#define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
+#define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
+#define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
+#define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
+#define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
+#define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
+#define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
+#define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
+#define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
+#define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
+#define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
+#define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
+#define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
+#define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
+#define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
+#define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
+#define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
+#define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
+#define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
+#define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
+#define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
+#define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
+#define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
+#define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
+#define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
+#define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
+#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
+
+
 #endif                          /* _IXP2000_H_ */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
index d0f415c6dae9..21e1de51e3f6 100644
--- a/include/asm-arm/arch-ixp2000/memory.h
+++ b/include/asm-arm/arch-ixp2000/memory.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index abdcf51bd283..a66317ab2071 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -15,40 +15,40 @@
 
 #ifndef __ASSEMBLY__
 
+static inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+
+static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
+
 /*
- * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
- * to on-chip I/O register to not complete fully. What this means is
- * that if you have a write to on-chip I/O followed by a back-to-back
- * read or write, the first write will happen twice. OR...if it's
- * not a back-to-back transaction, the read or write will generate
- * incorrect data.
- *
- * The official work around for this is to set the on-chip I/O regions
- * as XCB=101 and then force a read-back from the register.
+ * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
+ * XCB=101 instead, but that makes all I/O accesses bufferable.  This
+ * is not a problem in general, but we do have to be slightly more
+ * careful because I/O writes are no longer automatically flushed out
+ * of the write buffer.
  *
+ * In cases where we want to make sure that a write has been flushed
+ * out of the write buffer before we proceed, for example when masking
+ * a device interrupt before re-enabling IRQs in CPSR, we can use this
+ * function, ixp2000_reg_wrb, which performs a write, a readback, and
+ * issues a dummy instruction dependent on the value of the readback
+ * (mov rX, rX) to make sure that the readback has completed before we
+ * continue.
  */
-#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
-
-#include <asm/system.h>         /* Pickup local_irq_ functions */
-
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
 {
         unsigned long dummy;
-        unsigned long flags;
 
-        local_irq_save(flags);
         *((volatile unsigned long *)reg) = val;
-        barrier();
+
         dummy = *((volatile unsigned long *)reg);
-        local_irq_restore(flags);
-}
-#else
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
+        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
 }
-#endif  /* IXDP2400 || IXDP2401 */
-#define ixp2000_reg_read(reg)   (*((volatile unsigned long *)reg))
 
 /*
  * Boards may multiplex different devices on the 2nd channel of 
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index e350dcb544e8..80d05ecad2f0 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -113,7 +113,7 @@ __ixp4xx_writeb(u8 value, u32 addr)
 }
 
 static inline void
-__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
+__ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count)
 {
         while (count--)
                 writeb(*vaddr++, bus_addr);
@@ -136,7 +136,7 @@ __ixp4xx_writew(u16 value, u32 addr)
 }
 
 static inline void
-__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
+__ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count)
 {
         while (count--)
                 writew(*vaddr++, bus_addr);
@@ -154,7 +154,7 @@ __ixp4xx_writel(u32 value, u32 addr)
 }
 
 static inline void
-__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
+__ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count)
 {
         while (count--)
                 writel(*vaddr++, bus_addr);
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 004696a95bdb..2b149ed59149 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -36,11 +36,11 @@
  *
  * 0x6000000    0x00004000      ioremap'd       QMgr
  *
- * 0xC0000000   0x00001000      0xffbfe000      PCI CFG 
+ * 0xC0000000   0x00001000      0xffbff000      PCI CFG
  *
- * 0xC4000000   0x00001000      0xffbfd000      EXP CFG 
+ * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
  *
- * 0xC8000000   0x0000C000      0xffbf2000      On-Chip Peripherals
+ * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
  */
 
 /*
@@ -52,22 +52,22 @@
  * Expansion BUS Configuration registers
  */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFD000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 
 /*
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 
 /*
  * Peripheral space
  */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
-#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 
 /*
  * Debug UART
@@ -115,25 +115,48 @@
 /*
  * Peripheral Space Register Region Base Addresses
  */
-#define IXP4XX_UART1_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP4XX_UART2_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP4XX_PMU_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP4XX_INTC_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP4XX_GPIO_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP4XX_TIMER_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP4XX_EthA_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP4XX_EthB_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP4XX_USB_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
-
-#define IXP4XX_UART1_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
-#define IXP4XX_UART2_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
-#define IXP4XX_PMU_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
-#define IXP4XX_INTC_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
-#define IXP4XX_GPIO_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
-#define IXP4XX_TIMER_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
-#define IXP4XX_EthA_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
-#define IXP4XX_EthB_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
-#define IXP4XX_USB_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+#define IXP4XX_UART1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP4XX_UART2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP4XX_PMU_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP4XX_INTC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP4XX_GPIO_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP4XX_TIMER_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP4XX_NPEA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP4XX_NPEB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP4XX_NPEC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP4XX_EthC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP4XX_USB_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
+#define IXP4XX_EthB1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
+#define IXP4XX_EthB2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
+#define IXP4XX_EthB3_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_PHYS       (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
+#define IXP4XX_I2C_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
+#define IXP4XX_SSP_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+
+
+#define IXP4XX_UART1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_UART2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_PMU_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
+#define IXP4XX_EthB1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
+#define IXP4XX_EthB2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
+#define IXP4XX_EthB3_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_VIRT       (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
+#define IXP4XX_I2C_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
+#define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
 
 /*
  * Constants to make it easy to access  Interrupt Controller registers
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
index d348548b592b..e024d0a1a669 100644
--- a/include/asm-arm/arch-ixp4xx/memory.h
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -12,7 +12,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 
 #ifndef __ASSEMBLY__
 
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index fc012a39e2cb..cab8ad0adf09 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 
 #define IO_SPACE_LIMIT 0xffffffff
 
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
index c5b9608cb137..9e50a171f78a 100644
--- a/include/asm-arm/arch-l7200/memory.h
+++ b/include/asm-arm/arch-l7200/memory.h
@@ -15,7 +15,7 @@
 /*
  * Physical DRAM offset on the L7200 SDB.
  */
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
index c13bdd9add92..bbcd4335f441 100644
--- a/include/asm-arm/arch-lh7a40x/io.h
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /* No ISA or PCI bus on this machine. */
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index c650e6feb9d5..c92bcb837629 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -17,7 +17,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 11fbf629bf75..3d5bcd545082 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -34,6 +34,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index ef32d61eec7a..bf545b6e0a26 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -37,9 +37,9 @@
  * Physical DRAM offset.
  */
 #if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             (0x10000000UL)
+#define PHYS_OFFSET             UL(0x10000000)
 #elif defined(CONFIG_ARCH_OMAP2)
-#define PHYS_OFFSET             (0x80000000UL)
+#define PHYS_OFFSET             UL(0x80000000)
 #endif
 
 /*
@@ -66,7 +66,7 @@
 /*
  * OMAP-1510 Local Bus address offset
  */
-#define OMAP1510_LB_OFFSET      (0x30000000UL)
+#define OMAP1510_LB_OFFSET      UL(0x30000000)
 
 #define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index cf35721cfa45..3e70bd95472c 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,12 +44,12 @@
 
 #ifndef __ASSEMBLY__
 
-# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
 
 /* With indexed regs we don't want to feed the index through io_p2v()
    especially if it is a variable, otherwise horrible code will result. */
 # define __REG2(x,y)    \
-        (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
+        (*(volatile u32 *)((u32)&__REG(x) + (y)))
 
 # define __PREG(x)      (io_v2p((u32)&(x)))
 
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
index c3bdbe44e21f..eb2dd58d397f 100644
--- a/include/asm-arm/arch-pxa/io.h
+++ b/include/asm-arm/arch-pxa/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
new file mode 100644
index 000000000000..748406f384c2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_ARCH_IRDA_H
+#define ASMARM_ARCH_IRDA_H
+
+/* board specific transceiver capabilities */
+
+#define IR_OFF          1
+#define IR_SIRMODE      2
+#define IR_FIRMODE      4
+
+struct pxaficp_platform_data {
+        int transceiver_cap;
+        void (*transceiver_mode)(struct device *dev, int mode);
+};
+
+extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
+
+#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index 58bad9748b5c..eaf6d43939e9 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -15,7 +15,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 3af7165ab0d7..a75a2470f4f5 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -326,6 +326,25 @@
 #define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 #define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 
+/* Hardware UART (HWUART) */
+#define HWUART          HWRBR
+#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
+#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
+#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
+#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
+#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
+#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
+#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
+#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
+#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
+#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
+#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
+#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
+#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
+#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
+#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
 #define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
 #define IER_UUE         (1 << 6)        /* UART Unit Enable */
 #define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
@@ -1013,14 +1032,12 @@
 #define ICCR0_LBM       (1 << 1)        /* Loopback mode */
 #define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
 
-#ifdef CONFIG_PXA27x
 #define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
 #define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
 #define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
 #define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
 #define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
 #define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
-#endif
 
 #ifdef CONFIG_PXA27x
 #define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
@@ -1250,9 +1267,13 @@
 #define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
 #define GPIO41_FFRTS            41      /* FFUART request to send */
 #define GPIO42_BTRXD            42      /* BTUART receive data */
+#define GPIO42_HWRXD            42      /* HWUART receive data */
 #define GPIO43_BTTXD            43      /* BTUART transmit data */
+#define GPIO43_HWTXD            43      /* HWUART transmit data */
 #define GPIO44_BTCTS            44      /* BTUART clear to send */
+#define GPIO44_HWCTS            44      /* HWUART clear to send */
 #define GPIO45_BTRTS            45      /* BTUART request to send */
+#define GPIO45_HWRTS            45      /* HWUART request to send */
 #define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
 #define GPIO46_ICPRXD           46      /* ICP receive data */
 #define GPIO46_STRXD            46      /* STD_UART receive data */
@@ -1378,17 +1399,26 @@
 #define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
 #define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
 #define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
 #define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
 #define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
 #define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
 #define GPIO45_SYSCLK_AC97_MD           (45 | GPIO_ALT_FN_1_OUT)
 #define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
 #define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
 #define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
 #define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
 #define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
 #define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
 #define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
 #define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
 #define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
 #define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
@@ -1763,6 +1793,7 @@
 #define CKEN7_BTUART    (1 << 7)        /* BTUART Unit Clock Enable */
 #define CKEN6_FFUART    (1 << 6)        /* FFUART Unit Clock Enable */
 #define CKEN5_STUART    (1 << 5)        /* STUART Unit Clock Enable */
+#define CKEN4_HWUART    (1 << 4)        /* HWUART Unit Clock Enable */
 #define CKEN4_SSP3      (1 << 4)        /* SSP3 Unit Clock Enable */
 #define CKEN3_SSP       (1 << 3)        /* SSP Unit Clock Enable */
 #define CKEN3_SSP2      (1 << 3)        /* SSP2 Unit Clock Enable */
@@ -2282,4 +2313,11 @@
 
 #endif
 
+/* PWRMODE register M field values */
+
+#define PWRMODE_IDLE            0x1
+#define PWRMODE_STANDBY         0x2
+#define PWRMODE_SLEEP           0x3
+#define PWRMODE_DEEPSLEEP       0x7
+
 #endif
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 4428d3eb7432..fe38090444e0 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -12,6 +12,7 @@
 #define FFUART          ((volatile unsigned long *)0x40100000)
 #define BTUART          ((volatile unsigned long *)0x40200000)
 #define STUART          ((volatile unsigned long *)0x40700000)
+#define HWUART          ((volatile unsigned long *)0x41600000)
 
 #define UART            FFUART
 
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index 24453c405a87..b4da08d7a336 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h
index 33fc75cdead0..0592cb3f0c74 100644
--- a/include/asm-arm/arch-rpc/memory.h
+++ b/include/asm-arm/arch-rpc/memory.h
@@ -21,7 +21,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 
 /*
  * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
index ac57bc887d82..4790491ba9d0 100644
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -13,6 +13,7 @@
  *      07-Sep-2004     RTP     Created file
  *      03-Nov-2004     BJD     Updated and minor cleanups
  *      03-Aug-2005     RTP     Renamed to fb.h
+ *      26-Oct-2005     BJD     Changed name of platdata init
 */
 
 #ifndef __ASM_ARM_FB_H
@@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
         unsigned long   lpcsel;
 };
 
-void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
+extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
 
 #endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
index 4bf272ed9add..16fbc8afffd9 100644
--- a/include/asm-arm/arch-s3c2410/io.h
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 3380ab1d0749..6ab834a14c8e 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -28,9 +28,9 @@
  * and at 0x0C000000 for S3C2400
  */
 #ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET     (0x0C000000UL)
+#define PHYS_OFFSET     UL(0x0C000000)
 #else
-#define PHYS_OFFSET     (0x30000000UL)
+#define PHYS_OFFSET     UL(0x30000000)
 #endif
 
 /*
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 16f4c3cc1388..34360706e016 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -18,7 +18,9 @@
  *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
  *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
  *    27-Aug-2005 Ben Dooks         Add clock-slow info
- */
+ *    20-Oct-2005 Ben Dooks         Fixed overflow in PLL (Guillaume Gourat)
+ *    20-Oct-2005 Ben Dooks         Add masks for DCLK (Guillaume Gourat)
+*/
 
 #ifndef __ASM_ARM_REGS_CLOCK
 #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
@@ -66,11 +68,16 @@
 #define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
 #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
+#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
+#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
 
 #define S3C2410_DCLKCON_DCLK1EN      (1<<16)
 #define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
 #define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
 #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
+#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
+#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
+#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
 
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
@@ -83,10 +90,13 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/div64.h>
+
 static inline unsigned int
-s3c2410_get_pll(int pllval, int baseclk)
+s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 {
-        int mdiv, pdiv, sdiv;
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
 
         mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
         pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk)
         pdiv &= S3C2410_PLLCON_PDIVMASK;
         sdiv &= S3C2410_PLLCON_SDIVMASK;
 
-        return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
+        fvco = (uint64_t)baseclk * (mdiv + 8);
+        do_div(fvco, (pdiv + 2) << sdiv);
+
+        return (unsigned int)fvco;
 }
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 2053cbacffc3..cb33d57c146c 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -20,6 +20,7 @@
  *    18-11-2004     BJD     Added S3C2440 AC97 controls
  *    10-Mar-2005    LCVR    Changed S3C2410_VA to S3C24XX_VA
  *    28-Mar-2005    LCVR    Fixed definition of GPB10
+ *    26-Oct-2005    BJD     Added generic configuration types
 */
 
 
@@ -43,6 +44,11 @@
 /* general configuration options */
 
 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
+#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)
+#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
+#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
+#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* not available on A */
+#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
 
 /* configure GPIO ports A..G */
 
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 19c3b1e186bb..28711aaa4968 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -22,13 +22,6 @@
 
 
 /*
- * We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for 
- * in*()/out*() macros to be usable for all cases.
- */
-#define PCIO_BASE               0
-
-
-/*
  * SA1100 internal I/O mappings
  *
  * We have the following mapping:
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
index 7d969ffbd3bb..9d4fe6cf205b 100644
--- a/include/asm-arm/arch-sa1100/io.h
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -10,13 +10,19 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many 
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
 
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 8743ff5c1b23..0fc555b4c912 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -13,7 +13,7 @@
 /*
  * Physical DRAM offset is 0xc0000000 on the SA1100
  */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 
 #ifndef __ASSEMBLY__
 
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h
index 6f52118ba1a4..0f0612f79b2b 100644
--- a/include/asm-arm/arch-sa1100/system.h
+++ b/include/asm-arm/arch-sa1100/system.h
@@ -4,6 +4,7 @@
  * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
  */
 #include <linux/config.h>
+#include <asm/hardware.h>
 
 static inline void arch_idle(void)
 {
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index 5e6ed0038b2b..87ffa27f2962 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <asm/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h
index 8ff956d25463..95a29b4bc5d0 100644
--- a/include/asm-arm/arch-shark/memory.h
+++ b/include/asm-arm/arch-shark/memory.h
@@ -15,7 +15,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 
 #ifndef __ASSEMBLY__
 
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h
index 7b8b7cc422fa..a9370976cc5e 100644
--- a/include/asm-arm/arch-versatile/memory.h
+++ b/include/asm-arm/arch-versatile/memory.h
@@ -23,7 +23,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index aad7aad026b3..e007dd990da5 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -347,7 +347,6 @@ static inline unsigned long __ffs(unsigned long word)
  * the clz instruction for much better code efficiency.
  */
 
-static __inline__ int generic_fls(int x);
 #define fls(x) \
         ( __builtin_constant_p(x) ? generic_fls(x) : \
           ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index d62ade4e4cbb..e3e8541ee63b 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -70,7 +70,7 @@ static inline int dma_mapping_error(dma_addr_t dma_addr)
  * device-viewed address.
  */
 extern void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
+dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
 
 /**
  * dma_free_coherent - free memory allocated by dma_alloc_coherent
@@ -117,7 +117,7 @@ int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
  * device-viewed address.
  */
 extern void *
-dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
+dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
 
 #define dma_free_writecombine(dev,size,cpu_addr,handle) \
         dma_free_coherent(dev,size,cpu_addr,handle)
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 5c4ae8f5dbb0..2e6799632f12 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -26,7 +26,6 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
 
 /*
  * ISA I/O bus memory addresses are 1:1 with the physical address.
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 4fa95084a8c0..eb262e078c46 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -48,10 +48,11 @@ struct machine_desc {
  * Set of macros to define architecture features.  This is built into
  * a table by the linker.
  */
-#define MACHINE_START(_type,_name)              \
-const struct machine_desc __mach_desc_##_type   \
+#define MACHINE_START(_type,_name)                      \
+static const struct machine_desc __mach_desc_##_type    \
+ __attribute_used__                                     \
  __attribute__((__section__(".arch.info.init"))) = {    \
-        .nr             = MACH_TYPE_##_type,    \
+        .nr             = MACH_TYPE_##_type,            \
         .name           = _name,
 
 #define MACHINE_END                             \
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
index a92887d4b2cb..cd57436d9874 100644
--- a/include/asm-arm/mach/flash.h
+++ b/include/asm-arm/mach/flash.h
@@ -14,6 +14,7 @@ struct mtd_partition;
 
 /*
  * map_name:    the map probe function name
+ * name:        flash device name (eg, as used with mtdparts=)
  * width:       width of mapped device
  * init:        method called at driver/device initialisation
  * exit:        method called at driver/device removal
@@ -23,6 +24,7 @@ struct mtd_partition;
  */
 struct flash_platform_data {
         const char      *map_name;
+        const char      *name;
         unsigned int    width;
         int             (*init)(void);
         void            (*exit)(void);
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index 9ac47cf8d2e4..b338936bde4f 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -11,7 +11,7 @@
  */
 struct map_desc {
         unsigned long virtual;
-        unsigned long physical;
+        unsigned long pfn;
         unsigned long length;
         unsigned int type;
 };
@@ -27,6 +27,9 @@ struct meminfo;
 #define MT_ROM                  6
 #define MT_IXP2000_DEVICE       7
 
+#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
+#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
+
 extern void create_memmap_holes(struct meminfo *);
 extern void memtable_init(struct meminfo *);
 extern void iotable_init(struct map_desc *, int);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index a8a933a775db..a547ee598c6c 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -12,6 +12,16 @@
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
 
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#ifndef __ASSEMBLY__
+#define UL(x) (x##UL)
+#else
+#define UL(x) (x)
+#endif
+
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
@@ -21,20 +31,20 @@
  * TASK_SIZE - the maximum size of a user space task.
  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
  */
-#define TASK_SIZE               (0xbf000000UL)
-#define TASK_UNMAPPED_BASE      (0x40000000UL)
+#define TASK_SIZE               UL(0xbf000000)
+#define TASK_UNMAPPED_BASE      UL(0x40000000)
 #endif
 
 /*
  * The maximum size of a 26-bit user space task.
  */
-#define TASK_SIZE_26            (0x04000000UL)
+#define TASK_SIZE_26            UL(0x04000000)
 
 /*
  * Page offset: 3GB
  */
 #ifndef PAGE_OFFSET
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #endif
 
 /*
@@ -58,6 +68,13 @@
 #error Top of user space clashes with start of module space
 #endif
 
+/*
+ * The XIP kernel gets mapped at the bottom of the module vm area.
+ * Since we use sections to map it, this macro replaces the physical address
+ * with its virtual address while keeping offset from the base section.
+ */
+#define XIP_VIRT_ADDR(physaddr)  (MODULE_START + ((physaddr) & 0x000fffff))
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 366bafbdfbb1..5a0d19b466b0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -397,9 +397,6 @@ static inline pte_t *pmd_page_kernel(pmd_t pmd)
 #define pgd_clear(pgdp)         do { } while (0)
 #define set_pgd(pgd,pgdp)       do { } while (0)
 
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)          mk_pte(page, __pgprot(0))
-
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
 
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h
index 60f33e6eb800..71ca7d412687 100644
--- a/include/asm-arm/semaphore.h
+++ b/include/asm-arm/semaphore.h
@@ -24,8 +24,6 @@ struct semaphore {
         .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
 
-#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INIT(name,count)
 
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index 9bb325c54645..f49bfb78c221 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -27,11 +27,7 @@
  */
 struct mmu_gather {
         struct mm_struct        *mm;
-        unsigned int            freed;
         unsigned int            fullmm;
-
-        unsigned int            flushes;
-        unsigned int            avoided_flushes;
 };
 
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -39,11 +35,9 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        int cpu = smp_processor_id();
-        struct mmu_gather *tlb = &per_cpu(mmu_gathers, cpu);
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
 
         tlb->mm = mm;
-        tlb->freed = 0;
         tlb->fullmm = full_mm_flush;
 
         return tlb;
@@ -52,24 +46,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = tlb->mm;
-        unsigned long freed = tlb->freed;
-        int rss = get_mm_counter(mm, rss);
-
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
-
         if (tlb->fullmm)
-                flush_tlb_mm(mm);
+                flush_tlb_mm(tlb->mm);
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-}
 
-static inline unsigned int tlb_is_full_mm(struct mmu_gather *tlb)
-{
-        return tlb->fullmm;
+        put_cpu_var(mmu_gathers);
 }
 
 #define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index c49df635a80f..d626e70faded 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -544,7 +544,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_fork(struct pt_regs *regs);
 asmlinkage int sys_vfork(struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-arm26/pgtable.h b/include/asm-arm26/pgtable.h
index f602cf572411..a590250277f8 100644
--- a/include/asm-arm26/pgtable.h
+++ b/include/asm-arm26/pgtable.h
@@ -98,8 +98,6 @@ extern struct page *empty_zero_page;
 #define pfn_pte(pfn,prot)       (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 #define pages_to_mb(x)          ((x) >> (20 - PAGE_SHIFT))
 #define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)          mk_pte(page, __pgprot(0))
 
 /*
  * Terminology: PGD = Page Directory, PMD = Page Middle Directory,
diff --git a/include/asm-arm26/semaphore.h b/include/asm-arm26/semaphore.h
index c1b6a1edad92..ccf15e704109 100644
--- a/include/asm-arm26/semaphore.h
+++ b/include/asm-arm26/semaphore.h
@@ -25,9 +25,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INIT(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INIT(name,count)
 
diff --git a/include/asm-arm26/tlb.h b/include/asm-arm26/tlb.h
index 1316352a58f3..08ddd85b8d35 100644
--- a/include/asm-arm26/tlb.h
+++ b/include/asm-arm26/tlb.h
@@ -10,24 +10,20 @@
  */
 struct mmu_gather {
         struct mm_struct        *mm;
-        unsigned int            freed;
-        unsigned int            fullmm;
-
-        unsigned int            flushes;
-        unsigned int            avoided_flushes;
+        unsigned int            need_flush;
+        unsigned int            fullmm;
 };
 
-extern struct mmu_gather mmu_gathers[NR_CPUS];
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        int cpu = smp_processor_id();
-        struct mmu_gather *tlb = &mmu_gathers[cpu];
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
 
         tlb->mm = mm;
-        tlb->freed = 0;
-        tlb->fullmm = full_mm_flush;
+        tlb->need_flush = 0;
+        tlb->fullmm = full_mm_flush;
 
         return tlb;
 }
@@ -35,30 +31,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = tlb->mm;
-        unsigned long freed = tlb->freed;
-        int rss = get_mm_counter(mm, rss);
-
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
-
-        if (freed) {
-                flush_tlb_mm(mm);
-                tlb->flushes++;
-        } else {
-                tlb->avoided_flushes++;
-        }
+        if (tlb->need_flush)
+                flush_tlb_mm(tlb->mm);
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-}
-
 
-static inline unsigned int
-tlb_is_full_mm(struct mmu_gather *tlb)
-{
-     return tlb->fullmm;
+        put_cpu_var(mmu_gathers);
 }
 
 #define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
@@ -71,7 +50,13 @@ tlb_is_full_mm(struct mmu_gather *tlb)
         } while (0)
 #define tlb_end_vma(tlb,vma)                    do { } while (0)
 
-#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
+static inline void
+tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        tlb->need_flush = 1;
+        free_page_and_swap_cache(page);
+}
+
 #define pte_free_tlb(tlb,ptep)          pte_free(ptep)
 #define pmd_free_tlb(tlb,pmdp)          pmd_free(pmdp)
 
diff --git a/include/asm-arm26/unistd.h b/include/asm-arm26/unistd.h
index dfa0b0c30aa3..be4c2fb9c049 100644
--- a/include/asm-arm26/unistd.h
+++ b/include/asm-arm26/unistd.h
@@ -480,7 +480,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_fork(struct pt_regs *regs);
 asmlinkage int sys_vfork(struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index 0b5c3fdaefe1..8eff51349ae7 100644
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -15,14 +15,14 @@
 
 #ifdef CONFIG_PCI
 void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, int flag);
+                           dma_addr_t *dma_handle, gfp_t flag);
 
 void dma_free_coherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t dma_handle);
 #else
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   int flag)
+                   gfp_t flag)
 {
         BUG();
         return NULL;
diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h
index 8ed7636ab311..39faf69bcf76 100644
--- a/include/asm-cris/semaphore.h
+++ b/include/asm-cris/semaphore.h
@@ -33,9 +33,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h
index 28232ad2ff34..156a34bfc583 100644
--- a/include/asm-cris/unistd.h
+++ b/include/asm-cris/unistd.h
@@ -367,7 +367,6 @@ asmlinkage int sys_fork(long r10, long r11, long r12, long r13,
 asmlinkage int sys_vfork(long r10, long r11, long r12, long r13,
                         long mof, long srp, struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long __user *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-frv/dma-mapping.h b/include/asm-frv/dma-mapping.h
index 0206ab35eae0..5003e017fd1e 100644
--- a/include/asm-frv/dma-mapping.h
+++ b/include/asm-frv/dma-mapping.h
@@ -13,7 +13,7 @@
 extern unsigned long __nongprelbss dma_coherent_mem_start;
 extern unsigned long __nongprelbss dma_coherent_mem_end;
 
-void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, int gfp);
+void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp);
 void dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle);
 
 /*
diff --git a/include/asm-frv/pci.h b/include/asm-frv/pci.h
index b4efe5e3591a..1168451c275f 100644
--- a/include/asm-frv/pci.h
+++ b/include/asm-frv/pci.h
@@ -32,7 +32,7 @@ extern void pcibios_set_master(struct pci_dev *dev);
 extern void pcibios_penalize_isa_irq(int irq);
 
 #ifdef CONFIG_MMU
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle);
+extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
 extern void consistent_free(void *vaddr);
 extern void consistent_sync(void *vaddr, size_t size, int direction);
 extern void consistent_sync_page(struct page *page, unsigned long offset,
diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h
index 473fb4bb6329..b247e99dff49 100644
--- a/include/asm-frv/pgtable.h
+++ b/include/asm-frv/pgtable.h
@@ -436,8 +436,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
         return pte;
 }
 
-#define page_pte(page)  page_pte_prot((page), __pgprot(0))
-
 /* to find an entry in a page-table-directory. */
 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 #define pgd_index_k(addr) pgd_index(addr)
diff --git a/include/asm-frv/semaphore.h b/include/asm-frv/semaphore.h
index 393545630806..b18396288df1 100644
--- a/include/asm-frv/semaphore.h
+++ b/include/asm-frv/semaphore.h
@@ -47,9 +47,6 @@ struct semaphore {
 #define __SEMAPHORE_INITIALIZER(name,count) \
 { count, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) __SEM_DEBUG_INIT(name) }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-generic/4level-fixup.h b/include/asm-generic/4level-fixup.h
index c20ec257ecc0..68c6fea994d9 100644
--- a/include/asm-generic/4level-fixup.h
+++ b/include/asm-generic/4level-fixup.h
@@ -10,14 +10,9 @@
 
 #define pud_t                           pgd_t
 
-#define pmd_alloc(mm, pud, address)                     \
-({      pmd_t *ret;                                     \
-        if (pgd_none(*pud))                             \
-                ret = __pmd_alloc(mm, pud, address);    \
-        else                                            \
-                ret = pmd_offset(pud, address);         \
-        ret;                                            \
-})
+#define pmd_alloc(mm, pud, address) \
+        ((unlikely(pgd_none(*(pud))) && __pmd_alloc(mm, pud, address))? \
+                NULL: pmd_offset(pud, address))
 
 #define pud_alloc(mm, pgd, address)     (pgd)
 #define pud_offset(pgd, start)          (pgd)
diff --git a/include/asm-generic/dma-mapping-broken.h b/include/asm-generic/dma-mapping-broken.h
index fd9de9502dff..a7f1a55ce6b0 100644
--- a/include/asm-generic/dma-mapping-broken.h
+++ b/include/asm-generic/dma-mapping-broken.h
@@ -6,7 +6,7 @@
 
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   int flag)
+                   gfp_t flag)
 {
         BUG();
         return NULL;
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index ff28c8b31f58..7dca30a26c53 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -8,7 +8,7 @@
  *  - update the page tables
  *  - inform the TLB about the new one
  *
- * We hold the mm semaphore for reading and vma->vm_mm->page_table_lock.
+ * We hold the mm semaphore for reading, and the pte lock.
  *
  * Note: the old pte is known to not be writable, so we don't need to
  * worry about dirty bits etc getting lost.
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index 7d0298347ee7..cdd4145243cd 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -35,16 +35,13 @@
 #endif
 
 /* struct mmu_gather is an opaque type used by the mm code for passing around
- * any data needed by arch specific code for tlb_remove_page.  This structure
- * can be per-CPU or per-MM as the page table lock is held for the duration of
- * TLB shootdown.
+ * any data needed by arch specific code for tlb_remove_page.
  */
 struct mmu_gather {
         struct mm_struct        *mm;
         unsigned int            nr;     /* set to ~0U means fast mode */
         unsigned int            need_flush;/* Really unmapped some ptes? */
         unsigned int            fullmm; /* non-zero means full mm flush */
-        unsigned long           freed;
         struct page *           pages[FREE_PTE_NR];
 };
 
@@ -57,7 +54,7 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &per_cpu(mmu_gathers, smp_processor_id());
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
 
         tlb->mm = mm;
 
@@ -65,7 +62,6 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
         tlb->nr = num_online_cpus() > 1 ? 0U : ~0U;
 
         tlb->fullmm = full_mm_flush;
-        tlb->freed = 0;
 
         return tlb;
 }
@@ -85,28 +81,17 @@ tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 
 /* tlb_finish_mmu
  *      Called at the end of the shootdown operation to free up any resources
- *      that were required.  The page table lock is still held at this point.
+ *      that were required.
  */
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        int freed = tlb->freed;
-        struct mm_struct *mm = tlb->mm;
-        int rss = get_mm_counter(mm, rss);
-
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
         tlb_flush_mmu(tlb, start, end);
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-}
 
-static inline unsigned int
-tlb_is_full_mm(struct mmu_gather *tlb)
-{
-        return tlb->fullmm;
+        put_cpu_var(mmu_gathers);
 }
 
 /* tlb_remove_page
diff --git a/include/asm-h8300/semaphore.h b/include/asm-h8300/semaphore.h
index fe6ef3774297..81bae2a99192 100644
--- a/include/asm-h8300/semaphore.h
+++ b/include/asm-h8300/semaphore.h
@@ -35,9 +35,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-h8300/unistd.h b/include/asm-h8300/unistd.h
index 56a6401886fa..56a4a5686c88 100644
--- a/include/asm-h8300/unistd.h
+++ b/include/asm-h8300/unistd.h
@@ -528,7 +528,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
 asmlinkage int sys_execve(char *name, char **argv, char **envp,
                         int dummy, ...);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h
index 8c454aa58ac6..a515e2aed829 100644
--- a/include/asm-i386/apic.h
+++ b/include/asm-i386/apic.h
@@ -118,7 +118,8 @@ extern void release_lapic_nmi(void);
 extern void disable_timer_nmi_watchdog(void);
 extern void enable_timer_nmi_watchdog(void);
 extern void nmi_watchdog_tick (struct pt_regs * regs);
-extern int APIC_init_uniprocessor (void);
+extern int APIC_init(void);
+extern void APIC_late_time_init(void);
 extern void disable_APIC_timer(void);
 extern void enable_APIC_timer(void);
 
diff --git a/include/asm-i386/desc.h b/include/asm-i386/desc.h
index 6df1a53c190e..29b851a18c6e 100644
--- a/include/asm-i386/desc.h
+++ b/include/asm-i386/desc.h
@@ -17,6 +17,8 @@
 extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
 DECLARE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
 
+#define get_cpu_gdt_table(_cpu) (per_cpu(cpu_gdt_table,_cpu))
+
 DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
 
 struct Xgt_desc_struct {
@@ -60,7 +62,7 @@ __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
 
 static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr)
 {
-        _set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[entry], (int)addr,
+        _set_tssldt_desc(&get_cpu_gdt_table(cpu)[entry], (int)addr,
                 offsetof(struct tss_struct, __cacheline_filler) - 1, 0x89);
 }
 
@@ -68,7 +70,7 @@ static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *ad
 
 static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size)
 {
-        _set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
+        _set_tssldt_desc(&get_cpu_gdt_table(cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
 }
 
 #define LDT_entry_a(info) \
@@ -109,7 +111,7 @@ static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 en
 
 static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
 {
-#define C(i) per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
+#define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
         C(0); C(1); C(2);
 #undef C
 }
diff --git a/include/asm-i386/hw_irq.h b/include/asm-i386/hw_irq.h
index 622815bf3243..9139b89497a1 100644
--- a/include/asm-i386/hw_irq.h
+++ b/include/asm-i386/hw_irq.h
@@ -55,6 +55,7 @@ void init_8259A(int aeoi);
 void FASTCALL(send_IPI_self(int vector));
 void init_VISWS_APIC_irqs(void);
 void setup_IO_APIC(void);
+void IO_APIC_late_time_init(void);
 void disable_IO_APIC(void);
 void print_IO_APIC(void);
 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
diff --git a/include/asm-i386/mach-default/smpboot_hooks.h b/include/asm-i386/mach-default/smpboot_hooks.h
index 7f45f6311059..d7c70c144f9f 100644
--- a/include/asm-i386/mach-default/smpboot_hooks.h
+++ b/include/asm-i386/mach-default/smpboot_hooks.h
@@ -1,11 +1,6 @@
 /* two abstractions specific to kernel/smpboot.c, mainly to cater to visws
  * which needs to alter them. */
 
-static inline void smpboot_clear_io_apic_irqs(void)
-{
-        io_apic_irqs = 0;
-}
-
 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
 {
         CMOS_WRITE(0xa, 0xf);
@@ -32,13 +27,3 @@ static inline void smpboot_restore_warm_reset_vector(void)
 
         *((volatile long *) phys_to_virt(0x467)) = 0;
 }
-
-static inline void smpboot_setup_io_apic(void)
-{
-        /*
-         * Here we can be sure that there is an IO-APIC in the system. Let's
-         * go and set it up:
-         */
-        if (!skip_ioapic_setup && nr_ioapics)
-                setup_IO_APIC();
-}
diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h
index 28a84f6185a7..4a0637a3e208 100644
--- a/include/asm-i386/mach-es7000/mach_mpparse.h
+++ b/include/asm-i386/mach-es7000/mach_mpparse.h
@@ -16,7 +16,7 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
 
 extern int parse_unisys_oem (char *oemptr);
 extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
-extern void setup_unisys();
+extern void setup_unisys(void);
 
 static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                 char *productid)
diff --git a/include/asm-i386/mach-summit/mach_mpparse.h b/include/asm-i386/mach-summit/mach_mpparse.h
index 2b9e6d55bef1..1cce2b924a80 100644
--- a/include/asm-i386/mach-summit/mach_mpparse.h
+++ b/include/asm-i386/mach-summit/mach_mpparse.h
@@ -22,7 +22,6 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
 {
 }
 
-extern int usb_early_handoff;
 static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 
                 char *productid)
 {
@@ -32,7 +31,6 @@ static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                          || !strncmp(productid, "RUTHLESS SMP", 12))){
                 use_cyclone = 1; /*enable cyclone-timer*/
                 setup_summit();
-                usb_early_handoff = 1;
                 return 1;
         }
         return 0;
@@ -46,7 +44,6 @@ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
              || !strncmp(oem_table_id, "EXA", 3))){
                 use_cyclone = 1; /*enable cyclone-timer*/
                 setup_summit();
-                usb_early_handoff = 1;
                 return 1;
         }
         return 0;
diff --git a/include/asm-i386/mach-visws/smpboot_hooks.h b/include/asm-i386/mach-visws/smpboot_hooks.h
index d926471fa359..14d8e0375f7a 100644
--- a/include/asm-i386/mach-visws/smpboot_hooks.h
+++ b/include/asm-i386/mach-visws/smpboot_hooks.h
@@ -11,14 +11,7 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
 
 /* for visws do nothing for any of these */
 
-static inline void smpboot_clear_io_apic_irqs(void)
-{
-}
-
 static inline void smpboot_restore_warm_reset_vector(void)
 {
 }
 
-static inline void smpboot_setup_io_apic(void)
-{
-}
diff --git a/include/asm-i386/mmzone.h b/include/asm-i386/mmzone.h
index 348fe3a4879d..620a90641ea8 100644
--- a/include/asm-i386/mmzone.h
+++ b/include/asm-i386/mmzone.h
@@ -88,12 +88,6 @@ static inline int pfn_to_nid(unsigned long pfn)
         __pgdat->node_start_pfn + __pgdat->node_spanned_pages;          \
 })
 
-#define local_mapnr(kvaddr)                                             \
-({                                                                      \
-        unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT;               \
-        (__pfn - node_start_pfn(pfn_to_nid(__pfn)));                    \
-})
-
 /* XXX: FIXME -- wli */
 #define kern_addr_valid(kaddr)  (0)
 
diff --git a/include/asm-i386/pgtable-2level.h b/include/asm-i386/pgtable-2level.h
index fa07bd6c7529..74ef721b534d 100644
--- a/include/asm-i386/pgtable-2level.h
+++ b/include/asm-i386/pgtable-2level.h
@@ -26,11 +26,6 @@
 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-
-#define pmd_page_kernel(pmd) \
-((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
 /*
  * All present user pages are user-executable:
  */
diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h
index 2e3f4a344a2d..f1a8b454920a 100644
--- a/include/asm-i386/pgtable-3level.h
+++ b/include/asm-i386/pgtable-3level.h
@@ -74,11 +74,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
  */
 static inline void pud_clear (pud_t * pud) { }
 
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-
-#define pmd_page_kernel(pmd) \
-((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
 #define pud_page(pud) \
 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
 
diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h
index d101ac414f07..03f3c8ac6383 100644
--- a/include/asm-i386/pgtable.h
+++ b/include/asm-i386/pgtable.h
@@ -203,7 +203,8 @@ extern unsigned long pg0[];
 #define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
 #define pte_clear(mm,addr,xp)   do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
 
-#define pmd_none(x)     (!pmd_val(x))
+/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
+#define pmd_none(x)     (!(unsigned long)pmd_val(x))
 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 #define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
@@ -322,8 +323,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
         return pte;
 }
 
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
-
 #define pmd_large(pmd) \
 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
 
@@ -368,6 +367,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pte_offset_kernel(dir, address) \
         ((pte_t *) pmd_page_kernel(*(dir)) +  pte_index(address))
 
+#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
+
+#define pmd_page_kernel(pmd) \
+                ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+
 /*
  * Helper function that returns the kernel pagetable entry controlling
  * the virtual address 'address'. NULL means no pagetable entry present.
diff --git a/include/asm-i386/rwsem.h b/include/asm-i386/rwsem.h
index 7625a675852f..be4ab859238e 100644
--- a/include/asm-i386/rwsem.h
+++ b/include/asm-i386/rwsem.h
@@ -284,5 +284,10 @@ LOCK_PREFIX	"xadd %0,(%2)"
         return tmp+delta;
 }
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* __KERNEL__ */
 #endif /* _I386_RWSEM_H */
diff --git a/include/asm-i386/semaphore.h b/include/asm-i386/semaphore.h
index ea563da63e24..6a42b2142fd6 100644
--- a/include/asm-i386/semaphore.h
+++ b/include/asm-i386/semaphore.h
@@ -55,9 +55,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index acd5c26b69ba..97d52ac49e46 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -167,6 +167,8 @@ struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) ((struct __xchg_dummy *)(x))
 
 
+#ifdef CONFIG_X86_CMPXCHG64
+
 /*
  * The semantics of XCHGCMP8B are a bit strange, this is why
  * there is a loop and the loading of %%eax and %%edx has to
@@ -221,6 +223,8 @@ static inline void __set_64bit_var (unsigned long long *ptr,
  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 
+#endif
+
 /*
  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
  * Note 2: xchg has side effect, so that attribute volatile is necessary,
@@ -259,7 +263,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 #ifdef CONFIG_X86_CMPXCHG
 #define __HAVE_ARCH_CMPXCHG 1
-#endif
 
 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
                                       unsigned long new, int size)
@@ -275,13 +278,13 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
         case 2:
                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
                                      : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
                                      : "memory");
                 return prev;
         case 4:
                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
                                      : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
                                      : "memory");
                 return prev;
         }
@@ -291,6 +294,30 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 #define cmpxchg(ptr,o,n)\
         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
                                         (unsigned long)(n),sizeof(*(ptr))))
+
+#endif
+
+#ifdef CONFIG_X86_CMPXCHG64
+
+static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
+                                      unsigned long long new)
+{
+        unsigned long long prev;
+        __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
+                             : "=A"(prev)
+                             : "b"((unsigned long)new),
+                               "c"((unsigned long)(new >> 32)),
+                               "m"(*__xg(ptr)),
+                               "0"(old)
+                             : "memory");
+        return prev;
+}
+
+#define cmpxchg64(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
+                                        (unsigned long long)(n)))
+
+#endif
     
 #ifdef __KERNEL__
 struct alt_instr { 
diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h
index fbaf90a3968c..0f92e78dfea1 100644
--- a/include/asm-i386/unistd.h
+++ b/include/asm-i386/unistd.h
@@ -448,7 +448,6 @@ asmlinkage int sys_clone(struct pt_regs regs);
 asmlinkage int sys_fork(struct pt_regs regs);
 asmlinkage int sys_vfork(struct pt_regs regs);
 asmlinkage int sys_pipe(unsigned long __user *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 asmlinkage long sys_iopl(unsigned long unused);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 79e89a7db566..ca5ea994d688 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -26,7 +26,7 @@ typedef void ia64_mv_cpu_init_t (void);
 typedef void ia64_mv_irq_init_t (void);
 typedef void ia64_mv_send_ipi_t (int, int, int, int);
 typedef void ia64_mv_timer_interrupt_t (int, void *, struct pt_regs *);
-typedef void ia64_mv_global_tlb_purge_t (unsigned long, unsigned long, unsigned long);
+typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
 typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *);
 typedef unsigned int ia64_mv_local_vector_to_irq (u8);
 typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
@@ -37,7 +37,7 @@ typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
 
 /* DMA-mapping interface: */
 typedef void ia64_mv_dma_init (void);
-typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, int);
+typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, gfp_t);
 typedef void ia64_mv_dma_free_coherent (struct device *, size_t, void *, dma_addr_t);
 typedef dma_addr_t ia64_mv_dma_map_single (struct device *, void *, size_t, int);
 typedef void ia64_mv_dma_unmap_single (struct device *, dma_addr_t, size_t, int);
diff --git a/include/asm-ia64/meminit.h b/include/asm-ia64/meminit.h
index 1590dc65b30b..46501b01a5c5 100644
--- a/include/asm-ia64/meminit.h
+++ b/include/asm-ia64/meminit.h
@@ -16,10 +16,11 @@
  *      - initrd (optional)
  *      - command line string
  *      - kernel code & data
+ *      - Kernel memory map built from EFI memory map
  *
  * More could be added if necessary
  */
-#define IA64_MAX_RSVD_REGIONS 5
+#define IA64_MAX_RSVD_REGIONS 6
 
 struct rsvd_region {
         unsigned long start;    /* virtual address of beginning of element */
@@ -33,6 +34,7 @@ extern void find_memory (void);
 extern void reserve_memory (void);
 extern void find_initrd (void);
 extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg);
+extern void efi_memmap_init(unsigned long *, unsigned long *);
 
 /*
  * For rounding an address to the next IA64_GRANULE_SIZE or order
@@ -41,7 +43,7 @@ extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg
 #define GRANULEROUNDUP(n)       (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1))
 #define ORDERROUNDDOWN(n)       ((n) & ~((PAGE_SIZE<<MAX_ORDER)-1))
 
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
   extern void call_pernode_memory (unsigned long start, unsigned long len, void *func);
 #else
 # define call_pernode_memory(start, len, func)  (*func)(start, len, 0)
diff --git a/include/asm-ia64/mmzone.h b/include/asm-ia64/mmzone.h
index d32f51e3d6c2..34efe88eb849 100644
--- a/include/asm-ia64/mmzone.h
+++ b/include/asm-ia64/mmzone.h
@@ -15,7 +15,7 @@
 #include <asm/page.h>
 #include <asm/meminit.h>
 
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
 
 static inline int pfn_to_nid(unsigned long pfn)
 {
@@ -31,6 +31,10 @@ static inline int pfn_to_nid(unsigned long pfn)
 #endif
 }
 
+#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
+extern int early_pfn_to_nid(unsigned long pfn);
+#endif
+
 #ifdef CONFIG_IA64_DIG /* DIG systems are small */
 # define MAX_PHYSNODE_ID        8
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 8)
@@ -39,8 +43,8 @@ static inline int pfn_to_nid(unsigned long pfn)
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 4)
 #endif
 
-#else /* CONFIG_DISCONTIGMEM */
+#else /* CONFIG_NUMA */
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 4)
-#endif /* CONFIG_DISCONTIGMEM */
+#endif /* CONFIG_NUMA */
 
 #endif /* _ASM_IA64_MMZONE_H */
diff --git a/include/asm-ia64/nodedata.h b/include/asm-ia64/nodedata.h
index 6b0f3ed89b7e..9978c7ce7549 100644
--- a/include/asm-ia64/nodedata.h
+++ b/include/asm-ia64/nodedata.h
@@ -17,7 +17,7 @@
 #include <asm/percpu.h>
 #include <asm/mmzone.h>
 
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
 
 /*
  * Node Data. One of these structures is located on each node of a NUMA system.
@@ -47,6 +47,6 @@ struct ia64_node_data {
  */
 #define NODE_DATA(nid)          (local_node_data->pg_data_ptrs[nid])
 
-#endif /* CONFIG_DISCONTIGMEM */
+#endif /* CONFIG_NUMA */
 
 #endif /* _ASM_IA64_NODEDATA_H */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 9edffad8c28b..ef436b9d06ad 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -102,15 +102,15 @@ do {						\
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
 extern int ia64_pfn_valid (unsigned long pfn);
-#else
+#elif defined(CONFIG_FLATMEM)
 # define ia64_pfn_valid(pfn) 1
 #endif
 
-#ifndef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_FLATMEM
 # define pfn_valid(pfn)         (((pfn) < max_mapnr) && ia64_pfn_valid(pfn))
 # define page_to_pfn(page)      ((unsigned long) (page - mem_map))
 # define pfn_to_page(pfn)       (mem_map + (pfn))
-#else
+#elif defined(CONFIG_DISCONTIGMEM)
 extern struct page *vmem_map;
 extern unsigned long max_low_pfn;
 # define pfn_valid(pfn)         (((pfn) < max_low_pfn) && ia64_pfn_valid(pfn))
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index 3339c7b55a6f..21e32a06bc82 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -236,9 +236,6 @@ ia64_phys_addr_valid (unsigned long addr)
 #define pte_modify(_pte, newprot) \
         (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
 
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)                  page_pte_prot(page, __pgprot(0))
-
 #define pte_none(pte)                   (!pte_val(pte))
 #define pte_present(pte)                (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
 #define pte_clear(mm,addr,pte)          (pte_val(*(pte)) = 0UL)
diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h
index e18b5ab0cb75..1327c91ea39c 100644
--- a/include/asm-ia64/rwsem.h
+++ b/include/asm-ia64/rwsem.h
@@ -186,4 +186,9 @@ __downgrade_write (struct rw_semaphore *sem)
 #define rwsem_atomic_add(delta, sem)    atomic64_add(delta, (atomic64_t *)(&(sem)->count))
 #define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* _ASM_IA64_RWSEM_H */
diff --git a/include/asm-ia64/semaphore.h b/include/asm-ia64/semaphore.h
index 3a2f0f3f78f3..bb8906285fab 100644
--- a/include/asm-ia64/semaphore.h
+++ b/include/asm-ia64/semaphore.h
@@ -24,8 +24,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name)       __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count)                                 \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name, count)
 
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
index ab827d298569..1a3831c04af6 100644
--- a/include/asm-ia64/sn/arch.h
+++ b/include/asm-ia64/sn/arch.h
@@ -18,6 +18,32 @@
 #include <asm/sn/sn_cpuid.h>
 
 /*
+ * This is the maximum number of NUMALINK nodes that can be part of a single
+ * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
+ * remote partitions are NOT included in this number.
+ * The number of compact nodes cannot exceed size of a coherency domain.
+ * The purpose of this define is to specify a node count that includes
+ * all C/M/TIO nodes in an SSI system.
+ *
+ * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
+ *
+ *      Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
+ *      to ACPI3.0, this limit will be removed. The notion of "compact nodes"
+ *      should be deleted and TIOs should be included in MAX_NUMNODES.
+ */
+#define MAX_COMPACT_NODES       512
+
+/*
+ * Maximum number of nodes in all partitions and in all coherency domains.
+ * This is the total number of nodes accessible in the numalink fabric. It
+ * includes all C & M bricks, plus all TIOs.
+ *
+ * This value is also the value of the maximum number of NASIDs in the numalink
+ * fabric.
+ */
+#define MAX_NUMALINK_NODES      16384
+
+/*
  * The following defines attributes of the HUB chip. These attributes are
  * frequently referenced. They are kept in the per-cpu data areas of each cpu.
  * They are kept together in a struct to minimize cache misses.
@@ -41,15 +67,6 @@ DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
 
 
 /*
- * This is the maximum number of nodes that can be part of a kernel.
- * Effectively, it's the maximum number of compact node ids (cnodeid_t).
- * This is not necessarily the same as MAX_NASIDS.
- */
-#define MAX_COMPACT_NODES       2048
-#define CPUS_PER_NODE           4
-
-
-/*
  * Compact node ID to nasid mappings kept in the per-cpu data areas of each
  * cpu.
  */
@@ -57,7 +74,6 @@ DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]);
 #define sn_cnodeid_to_nasid     (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
 
 
-
 extern u8 sn_partition_id;
 extern u8 sn_system_size;
 extern u8 sn_sharing_domain_size;
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
index 42209733f6b1..41c73a735628 100644
--- a/include/asm-ia64/sn/io.h
+++ b/include/asm-ia64/sn/io.h
@@ -14,7 +14,7 @@
 extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
 extern void __sn_mmiowb(void); /* Forward definition */
 
-extern int numionodes;
+extern int num_cnodes;
 
 #define __sn_mf_a()   ia64_mfa()
 
@@ -36,6 +36,15 @@ extern void sn_dma_flush(unsigned long);
 #define __sn_readq_relaxed ___sn_readq_relaxed
 
 /*
+ * Convenience macros for setting/clearing bits using the above accessors
+ */
+
+#define __sn_setq_relaxed(addr, val) \
+        writeq((__sn_readq_relaxed(addr) | (val)), (addr))
+#define __sn_clrq_relaxed(addr, val) \
+        writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
+
+/*
  * The following routines are SN Platform specific, called when
  * a reference is made to inX/outX set macros.  SN Platform
  * inX set of macros ensures that Posted DMA writes on the
diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
index 9f920c70a62a..bcbf209d63be 100644
--- a/include/asm-ia64/sn/klconfig.h
+++ b/include/asm-ia64/sn/klconfig.h
@@ -208,19 +208,6 @@ typedef struct lboard_s {
         klconf_off_t    brd_next_same;    /* Next BOARD with same nasid */
 } lboard_t;
 
-#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
-#define NODE_OFFSET_TO_KLINFO(n,off)    ((klinfo_t*) TO_NODE_CAC(n,off))
-#define KLCF_NEXT(_brd)         \
-        ((_brd)->brd_next_same ?     \
-         (NODE_OFFSET_TO_LBOARD((_brd)->brd_next_same_host, (_brd)->brd_next_same)): NULL)
-#define KLCF_NEXT_ANY(_brd)         \
-        ((_brd)->brd_next_any ?     \
-         (NODE_OFFSET_TO_LBOARD(NASID_GET(_brd), (_brd)->brd_next_any)): NULL)
-#define KLCF_COMP(_brd, _ndx)   \
-                ((((_brd)->brd_compts[(_ndx)]) == 0) ? 0 : \
-                        (NODE_OFFSET_TO_KLINFO(NASID_GET(_brd), (_brd)->brd_compts[(_ndx)])))
-
-
 /*
  * Generic info structure. This stores common info about a 
  * component.
@@ -249,24 +236,11 @@ typedef struct klinfo_s {                  /* Generic info */
 } klinfo_t ;
 
 
-static inline lboard_t *find_lboard_any(lboard_t * start, unsigned char brd_type)
+static inline lboard_t *find_lboard_next(lboard_t * brd)
 {
-        /* Search all boards stored on this node. */
-
-        while (start) {
-                if (start->brd_type == brd_type)
-                        return start;
-                start = KLCF_NEXT_ANY(start);
-        }
-        /* Didn't find it. */
-        return (lboard_t *) NULL;
+        if (brd && brd->brd_next_any)
+                return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
+        return NULL;
 }
 
-
-/* external declarations of Linux kernel functions. */
-
-extern lboard_t *root_lboard[];
-extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
-extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
-
 #endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 2e5f0aa38889..e3b819110d47 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -35,4 +35,16 @@
 #define L1_BRICKTYPE_ATHENA     0x2b            /* + */
 #define L1_BRICKTYPE_DAYTONA    0x7a            /* z */
 
+/* board type response codes */
+#define L1_BOARDTYPE_IP69       0x0100          /* CA */
+#define L1_BOARDTYPE_IP63       0x0200          /* CB */
+#define L1_BOARDTYPE_BASEIO     0x0300          /* IB */
+#define L1_BOARDTYPE_PCIE2SLOT  0x0400          /* IC */
+#define L1_BOARDTYPE_PCIX3SLOT  0x0500          /* ID */
+#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600       /* IE */
+#define L1_BOARDTYPE_ABACUS     0x0700          /* AB */
+#define L1_BOARDTYPE_DAYTONA    0x0800          /* AD */
+#define L1_BOARDTYPE_INVAL      (-1)            /* invalid brick type */
+
+
 #endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 47bb8100fd00..6f6d69e39ff5 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -55,7 +55,6 @@ struct nodepda_s {
          */
         struct phys_cpuid       phys_cpuid[NR_CPUS];
         spinlock_t              ptc_lock ____cacheline_aligned_in_smp;
-        spinlock_t              bist_lock;
 };
 
 typedef struct nodepda_s nodepda_t;
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
index d2c1d34dcce4..749deb2ca6c1 100644
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -105,7 +105,6 @@ extern short physical_node_map[];	/* indexed by nasid to get cnode */
 #define cpuid_to_nasid(cpuid)           (sn_nodepda->phys_cpuid[cpuid].nasid)
 #define cpuid_to_subnode(cpuid)         (sn_nodepda->phys_cpuid[cpuid].subnode)
 #define cpuid_to_slice(cpuid)           (sn_nodepda->phys_cpuid[cpuid].slice)
-#define cpuid_to_cnodeid(cpuid)         (physical_node_map[cpuid_to_nasid(cpuid)])
 
 
 /*
@@ -113,8 +112,6 @@ extern short physical_node_map[];	/* indexed by nasid to get cnode */
  * of potentially large tables.
  */
 extern int nasid_slice_to_cpuid(int, int);
-#define nasid_slice_to_cpu_physical_id(nasid, slice)                    \
-        cpu_physical_id(nasid_slice_to_cpuid(nasid, slice))
 
 /*
  * cnodeid_to_nasid - convert a cnodeid to a NASID
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index fea35b33d4e4..3f7564dc0aa9 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -47,6 +47,7 @@
 #define  SN_SAL_CONSOLE_PUTB                       0x02000028
 #define  SN_SAL_CONSOLE_XMIT_CHARS                 0x0200002a
 #define  SN_SAL_CONSOLE_READC                      0x0200002b
+#define  SN_SAL_SYSCTL_OP                          0x02000030
 #define  SN_SAL_SYSCTL_MODID_GET                   0x02000031
 #define  SN_SAL_SYSCTL_GET                         0x02000032
 #define  SN_SAL_SYSCTL_IOBRICK_MODULE_GET          0x02000033
@@ -67,7 +68,7 @@
 #define  SN_SAL_IOIF_INTERRUPT                     0x0200004a
 #define  SN_SAL_HWPERF_OP                          0x02000050   // lock
 #define  SN_SAL_IOIF_ERROR_INTERRUPT               0x02000051
-
+#define  SN_SAL_IOIF_PCI_SAFE                      0x02000052
 #define  SN_SAL_IOIF_SLOT_ENABLE                   0x02000053
 #define  SN_SAL_IOIF_SLOT_DISABLE                  0x02000054
 #define  SN_SAL_IOIF_GET_HUBDEV_INFO               0x02000055
@@ -101,6 +102,13 @@
 #define SAL_INTR_FREE           2
 
 /*
+ * operations available on the generic SN_SAL_SYSCTL_OP
+ * runtime service
+ */
+#define SAL_SYSCTL_OP_IOBOARD           0x0001  /*  retrieve board type */
+#define SAL_SYSCTL_OP_TIO_JLCK_RST      0x0002  /* issue TIO clock reset */
+
+/*
  * IRouter (i.e. generalized system controller) operations
  */
 #define SAL_IROUTER_OPEN        0       /* open a subchannel */
@@ -198,26 +206,16 @@ ia64_sn_get_master_baseio_nasid(void)
         return ret_stuff.v0;
 }
 
-static inline char *
+static inline void *
 ia64_sn_get_klconfig_addr(nasid_t nasid)
 {
         struct ia64_sal_retval ret_stuff;
-        int cnodeid;
 
-        cnodeid = nasid_to_cnodeid(nasid);
         ret_stuff.status = 0;
         ret_stuff.v0 = 0;
         ret_stuff.v1 = 0;
         ret_stuff.v2 = 0;
         SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
-
-        /*
-         * We should panic if a valid cnode nasid does not produce
-         * a klconfig address.
-         */
-        if (ret_stuff.status != 0) {
-                panic("ia64_sn_get_klconfig_addr: Returned error %lx\n", ret_stuff.status);
-        }
         return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
 }
 
@@ -694,12 +692,10 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
         unsigned long irq_flags;
 
         cnodeid = nasid_to_cnodeid(get_node_number(paddr));
-        // spin_lock(&NODEPDA(cnodeid)->bist_lock);
         local_irq_save(irq_flags);
         ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
                                 (u64)nasid_array, perms, 0, 0, 0);
         local_irq_restore(irq_flags);
-        // spin_unlock(&NODEPDA(cnodeid)->bist_lock);
         return ret_stuff.status;
 }
 #define SN_MEMPROT_ACCESS_CLASS_0               0x14a080
@@ -873,6 +869,41 @@ ia64_sn_sysctl_event_init(nasid_t nasid)
         return (int) rv.v0;
 }
 
+/*
+ * Ask the system controller on the specified nasid to reset
+ * the CX corelet clock.  Only valid on TIO nodes.
+ */
+static inline int
+ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
+                        nasid, 0, 0, 0, 0, 0);
+        if (rv.status != 0)
+                return (int)rv.status;
+        if (rv.v0 != 0)
+                return (int)rv.v0;
+
+        return 0;
+}
+
+/*
+ * Get the associated ioboard type for a given nasid.
+ */
+static inline int
+ia64_sn_sysctl_ioboard_get(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
+                        nasid, 0, 0, 0, 0, 0);
+        if (rv.v0 != 0)
+                return (int)rv.v0;
+        if (rv.v1 != 0)
+                return (int)rv.v1;
+
+        return 0;
+}
+
 /**
  * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
  * @nasid: NASID of node to read
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index 5ccec608d325..b532ef6148ed 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -182,11 +182,11 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
                          * touch every CL aligned GART entry.
                          */
 
-                        ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
-                        ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
-                        ca_base->ca_control2 |=
-                            (0x2ull << CA_GART_MEM_PARAM_SHFT);
-                        tmp = ca_base->ca_control2;
+                        __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
+                        __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
+                        __sn_setq_relaxed(&ca_base->ca_control2,
+                            (0x2ull << CA_GART_MEM_PARAM_SHFT));
+                        tmp = __sn_readq_relaxed(&ca_base->ca_control2);
                 }
 
                 return;
@@ -196,8 +196,8 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
          * Gart in uncached mode ... need an explicit flush.
          */
 
-        ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
-        tmp = ca_base->ca_control2;
+        __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
+        tmp = __sn_readq_relaxed(&ca_base->ca_control2);
 }
 
 extern uint32_t tioca_gart_found;
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
index c5447a504509..5699e75e5024 100644
--- a/include/asm-ia64/sn/tiocx.h
+++ b/include/asm-ia64/sn/tiocx.h
@@ -19,6 +19,7 @@ struct cx_id_s {
 
 struct cx_dev {
         struct cx_id_s cx_id;
+        int bt;                         /* board/blade type */
         void *soft;                     /* driver specific */
         struct hubdev_info *hubdev;
         struct device dev;
@@ -59,7 +60,7 @@ struct cx_drv {
 extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
 extern void tiocx_irq_free(struct sn_irq_info *);
 extern int cx_device_unregister(struct cx_dev *);
-extern int cx_device_register(nasid_t, int, int, struct hubdev_info *);
+extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
 extern int cx_driver_unregister(struct cx_drv *);
 extern int cx_driver_register(struct cx_drv *);
 extern uint64_t tiocx_dma_addr(uint64_t addr);
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h
index 1df1c9f61a65..49faf8f26430 100644
--- a/include/asm-ia64/sn/xp.h
+++ b/include/asm-ia64/sn/xp.h
@@ -49,7 +49,7 @@
  * C-brick nasids, thus the need for bitmaps which don't account for
  * odd-numbered (non C-brick) nasids.
  */
-#define XP_MAX_PHYSNODE_ID      (MAX_PHYSNODE_ID / 2)
+#define XP_MAX_PHYSNODE_ID      (MAX_NUMALINK_NODES / 2)
 #define XP_NASID_MASK_BYTES     ((XP_MAX_PHYSNODE_ID + 7) / 8)
 #define XP_NASID_MASK_WORDS     ((XP_MAX_PHYSNODE_ID + 63) / 64)
 
@@ -217,7 +217,17 @@ enum xpc_retval {
         xpcInvalidPartid,       /* 42: invalid partition ID */
         xpcLocalPartid,         /* 43: local partition ID */
 
-        xpcUnknownReason        /* 44: unknown reason -- must be last in list */
+        xpcOtherGoingDown,      /* 44: other side going down, reason unknown */
+        xpcSystemGoingDown,     /* 45: system is going down, reason unknown */
+        xpcSystemHalt,          /* 46: system is being halted */
+        xpcSystemReboot,        /* 47: system is being rebooted */
+        xpcSystemPoweroff,      /* 48: system is being powered off */
+
+        xpcDisconnecting,       /* 49: channel disconnecting (closing) */
+
+        xpcOpenCloseError,      /* 50: channel open/close protocol error */
+
+        xpcUnknownReason        /* 51: unknown reason -- must be last in list */
 };
 
 
@@ -342,7 +352,7 @@ typedef void (*xpc_notify_func)(enum xpc_retval reason, partid_t partid,
  *
  * The 'func' field points to the function to call when aynchronous
  * notification is required for such events as: a connection established/lost,
- * or an incomming message received, or an error condition encountered. A
+ * or an incoming message received, or an error condition encountered. A
  * non-NULL 'func' field indicates that there is an active registration for
  * the channel.
  */
diff --git a/include/asm-ia64/sparsemem.h b/include/asm-ia64/sparsemem.h
new file mode 100644
index 000000000000..67a7c40ec27f
--- /dev/null
+++ b/include/asm-ia64/sparsemem.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_IA64_SPARSEMEM_H
+#define _ASM_IA64_SPARSEMEM_H
+
+#ifdef CONFIG_SPARSEMEM
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+
+#define SECTION_SIZE_BITS       (30)
+#define MAX_PHYSMEM_BITS        (50)
+#ifdef CONFIG_FORCE_MAX_ZONEORDER
+#if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS)
+#undef SECTION_SIZE_BITS
+#define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT)
+#endif
+#endif
+
+#endif /* CONFIG_SPARSEMEM */
+#endif /* _ASM_IA64_SPARSEMEM_H */
diff --git a/include/asm-ia64/tlb.h b/include/asm-ia64/tlb.h
index 3a9a6d1be75c..834370b9dea1 100644
--- a/include/asm-ia64/tlb.h
+++ b/include/asm-ia64/tlb.h
@@ -60,7 +60,6 @@ struct mmu_gather {
         unsigned int            nr;             /* == ~0U => fast mode */
         unsigned char           fullmm;         /* non-zero means full mm flush */
         unsigned char           need_flush;     /* really unmapped some PTEs? */
-        unsigned long           freed;          /* number of pages freed */
         unsigned long           start_addr;
         unsigned long           end_addr;
         struct page             *pages[FREE_PTE_NR];
@@ -129,7 +128,7 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e
 static inline struct mmu_gather *
 tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &__get_cpu_var(mmu_gathers);
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
 
         tlb->mm = mm;
         /*
@@ -147,25 +146,17 @@ tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
          */
         tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
         tlb->fullmm = full_mm_flush;
-        tlb->freed = 0;
         tlb->start_addr = ~0UL;
         return tlb;
 }
 
 /*
  * Called at the end of the shootdown operation to free up any resources that were
- * collected.  The page table lock is still held at this point.
+ * collected.
  */
 static inline void
 tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        unsigned long freed = tlb->freed;
-        struct mm_struct *mm = tlb->mm;
-        unsigned long rss = get_mm_counter(mm, rss);
-
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
         /*
          * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
          * tlb->end_addr.
@@ -174,12 +165,8 @@ tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-}
 
-static inline unsigned int
-tlb_is_full_mm(struct mmu_gather *tlb)
-{
-     return tlb->fullmm;
+        put_cpu_var(mmu_gathers);
 }
 
 /*
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index 3a0c69524656..6d96a67439be 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -383,8 +383,6 @@ struct sigaction;
 long sys_execve(char __user *filename, char __user * __user *argv,
                            char __user * __user *envp, struct pt_regs *regs);
 asmlinkage long sys_pipe(void);
-asmlinkage long sys_ptrace(long request, pid_t pid,
-                           unsigned long addr, unsigned long data);
 asmlinkage long sys_rt_sigaction(int sig,
                                  const struct sigaction __user *act,
                                  struct sigaction __user *oact,
diff --git a/include/asm-m32r/dma-mapping.h b/include/asm-m32r/dma-mapping.h
index 3a2db28834b6..a7fa0302bda7 100644
--- a/include/asm-m32r/dma-mapping.h
+++ b/include/asm-m32r/dma-mapping.h
@@ -8,7 +8,7 @@
 
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   int flag)
+                   gfp_t flag)
 {
         return (void *)NULL;
 }
diff --git a/include/asm-m32r/mmzone.h b/include/asm-m32r/mmzone.h
index d58878ec899e..adc7970a77ec 100644
--- a/include/asm-m32r/mmzone.h
+++ b/include/asm-m32r/mmzone.h
@@ -21,12 +21,6 @@ extern struct pglist_data *node_data[];
         __pgdat->node_start_pfn + __pgdat->node_spanned_pages - 1;      \
 })
 
-#define local_mapnr(kvaddr)                                             \
-({                                                                      \
-        unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT;               \
-        (__pfn - node_start_pfn(pfn_to_nid(__pfn)));                    \
-})
-
 #define pfn_to_page(pfn)                                                \
 ({                                                                      \
         unsigned long __pfn = pfn;                                      \
diff --git a/include/asm-m32r/pgtable.h b/include/asm-m32r/pgtable.h
index 388e5ee9fa27..1cd5fd4a5b2c 100644
--- a/include/asm-m32r/pgtable.h
+++ b/include/asm-m32r/pgtable.h
@@ -324,8 +324,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
         return pte;
 }
 
-#define page_pte(page)  page_pte_prot(page, __pgprot(0))
-
 /*
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
diff --git a/include/asm-m32r/semaphore.h b/include/asm-m32r/semaphore.h
index 53e3c60f21ec..bf447c52a0a1 100644
--- a/include/asm-m32r/semaphore.h
+++ b/include/asm-m32r/semaphore.h
@@ -32,9 +32,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-m32r/thread_info.h b/include/asm-m32r/thread_info.h
index 7a6be7727a92..0f589363f619 100644
--- a/include/asm-m32r/thread_info.h
+++ b/include/asm-m32r/thread_info.h
@@ -95,7 +95,7 @@ static inline struct thread_info *current_thread_info(void)
 }
 
 /* thread information allocation */
-#if CONFIG_DEBUG_STACK_USAGE
+#ifdef CONFIG_DEBUG_STACK_USAGE
 #define alloc_thread_info(tsk)                                  \
         ({                                                      \
                 struct thread_info *ret;                        \
diff --git a/include/asm-m32r/unistd.h b/include/asm-m32r/unistd.h
index 8552d8f45ab1..ac399e1f7bc0 100644
--- a/include/asm-m32r/unistd.h
+++ b/include/asm-m32r/unistd.h
@@ -452,7 +452,6 @@ asmlinkage int sys_clone(struct pt_regs regs);
 asmlinkage int sys_fork(struct pt_regs regs);
 asmlinkage int sys_vfork(struct pt_regs regs);
 asmlinkage int sys_pipe(unsigned long __user *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                  const struct sigaction __user *act,
diff --git a/include/asm-m68k/semaphore.h b/include/asm-m68k/semaphore.h
index ab94cf3ed447..fd4c7cc3d3be 100644
--- a/include/asm-m68k/semaphore.h
+++ b/include/asm-m68k/semaphore.h
@@ -36,9 +36,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-m68k/sun3xflop.h b/include/asm-m68k/sun3xflop.h
index 1ed3b787ee05..fda1eccf10aa 100644
--- a/include/asm-m68k/sun3xflop.h
+++ b/include/asm-m68k/sun3xflop.h
@@ -27,10 +27,8 @@
 
 /* We don't need no stinkin' I/O port allocation crap. */
 #undef release_region
-#undef check_region
 #undef request_region
 #define release_region(X, Y)    do { } while(0)
-#define check_region(X, Y)      (0)
 #define request_region(X, Y, Z) (1)
 
 struct sun3xflop_private {
diff --git a/include/asm-m68k/unistd.h b/include/asm-m68k/unistd.h
index cbabde4f8a45..c2554bcd1747 100644
--- a/include/asm-m68k/unistd.h
+++ b/include/asm-m68k/unistd.h
@@ -444,7 +444,6 @@ asmlinkage long sys_mmap2(
                         unsigned long fd, unsigned long pgoff);
 asmlinkage int sys_execve(char *name, char **argv, char **envp);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct pt_regs;
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
diff --git a/include/asm-m68knommu/ide.h b/include/asm-m68knommu/ide.h
index b1cbf8bb9232..836f0721ecf9 100644
--- a/include/asm-m68knommu/ide.h
+++ b/include/asm-m68knommu/ide.h
@@ -163,13 +163,6 @@ ide_free_irq(unsigned int irq, void *dev_id)
 }
 
 
-static IDE_INLINE int
-ide_check_region(ide_ioreg_t from, unsigned int extent)
-{
-        return 0;
-}
-
-
 static IDE_INLINE void
 ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
 {
diff --git a/include/asm-m68knommu/semaphore.h b/include/asm-m68knommu/semaphore.h
index febe85add509..17aee15906a6 100644
--- a/include/asm-m68knommu/semaphore.h
+++ b/include/asm-m68knommu/semaphore.h
@@ -35,9 +35,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-m68knommu/unistd.h b/include/asm-m68knommu/unistd.h
index 84b6fa14459f..5373988a7e51 100644
--- a/include/asm-m68knommu/unistd.h
+++ b/include/asm-m68knommu/unistd.h
@@ -504,7 +504,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
                         unsigned long fd, unsigned long pgoff);
 asmlinkage int sys_execve(char *name, char **argv, char **envp);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct pt_regs;
 int sys_request_irq(unsigned int,
                         irqreturn_t (*)(int, void *, struct pt_regs *),
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h
new file mode 100644
index 000000000000..2e7e651c3e3f
--- /dev/null
+++ b/include/asm-mips/abi.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle
+ * Copyright (C) 2005 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_ABI_H
+#define _ASM_ABI_H
+
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+
+struct mips_abi {
+        int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs);
+        int (* const setup_frame)(struct k_sigaction * ka,
+                                  struct pt_regs *regs, int signr,
+                                  sigset_t *set);
+        int (* const setup_rt_frame)(struct k_sigaction * ka,
+                               struct pt_regs *regs, int signr,
+                               sigset_t *set, siginfo_t *info);
+};
+
+#endif /* _ASM_ABI_H */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 7dc2619f5006..42520cc84b0f 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -20,10 +20,12 @@
 #define _ATYPE_
 #define _ATYPE32_
 #define _ATYPE64_
+#define _LLCONST_(x)    x
 #else
 #define _ATYPE_         __PTRDIFF_TYPE__
 #define _ATYPE32_       int
 #define _ATYPE64_       long long
+#define _LLCONST_(x)    x ## LL
 #endif
 
 /*
@@ -45,8 +47,9 @@
 /*
  * Returns the physical address of a CKSEGx / XKPHYS address
  */
-#define CPHYSADDR(a)            ((_ACAST32_ (a)) & 0x1fffffff)
-#define XPHYSADDR(a)            ((_ACAST64_ (a)) & 0x000000ffffffffff)
+#define CPHYSADDR(a)            ((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)            ((_ACAST64_(a)) &                       \
+                                 _LLCONST_(0x000000ffffffffff))
 
 #ifdef CONFIG_64BIT
 
@@ -55,14 +58,14 @@
  * The compatibility segments use the full 64-bit sign extended value.  Note
  * the R8000 doesn't have them so don't reference these in generic MIPS code.
  */
-#define XKUSEG                  0x0000000000000000
-#define XKSSEG                  0x4000000000000000
-#define XKPHYS                  0x8000000000000000
-#define XKSEG                   0xc000000000000000
-#define CKSEG0                  0xffffffff80000000
-#define CKSEG1                  0xffffffffa0000000
-#define CKSSEG                  0xffffffffc0000000
-#define CKSEG3                  0xffffffffe0000000
+#define XKUSEG                  _LLCONST_(0x0000000000000000)
+#define XKSSEG                  _LLCONST_(0x4000000000000000)
+#define XKPHYS                  _LLCONST_(0x8000000000000000)
+#define XKSEG                   _LLCONST_(0xc000000000000000)
+#define CKSEG0                  _LLCONST_(0xffffffff80000000)
+#define CKSEG1                  _LLCONST_(0xffffffffa0000000)
+#define CKSSEG                  _LLCONST_(0xffffffffc0000000)
+#define CKSEG3                  _LLCONST_(0xffffffffe0000000)
 
 #define CKSEG0ADDR(a)           (CPHYSADDR(a) | CKSEG0)
 #define CKSEG1ADDR(a)           (CPHYSADDR(a) | CKSEG1)
@@ -120,7 +123,8 @@
 #define PHYS_TO_XKSEG_UNCACHED(p)       PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
 #define PHYS_TO_XKSEG_CACHED(p)         PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
 #define XKPHYS_TO_PHYS(p)               ((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm,a)            (0x8000000000000000 | ((cm)<<59) | (a))
+#define PHYS_TO_XKPHYS(cm,a)            (_LLCONST_(0x8000000000000000) | \
+                                         ((cm)<<59) | (a))
 
 #if defined (CONFIG_CPU_R4300)                                          \
     || defined (CONFIG_CPU_R4X00)                                       \
@@ -128,46 +132,56 @@
     || defined (CONFIG_CPU_NEVADA)                                      \
     || defined (CONFIG_CPU_TX49XX)                                      \
     || defined (CONFIG_CPU_MIPS64)
-#define KUSIZE                  0x0000010000000000      /* 2^^40 */
-#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
-#define K0SIZE                  0x0000001000000000      /* 2^^36 */
-#define K1SIZE                  0x0000001000000000      /* 2^^36 */
-#define K2SIZE                  0x000000ff80000000
-#define KSEGSIZE                0x000000ff80000000      /* max syssegsz */
-#define TO_PHYS_MASK            0x0000000fffffffff      /* 2^^36 - 1 */
+#define KUSIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define KUSIZE_64       _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K0SIZE          _LLCONST_(0x0000001000000000)   /* 2^^36 */
+#define K1SIZE          _LLCONST_(0x0000001000000000)   /* 2^^36 */
+#define K2SIZE          _LLCONST_(0x000000ff80000000)
+#define KSEGSIZE        _LLCONST_(0x000000ff80000000)   /* max syssegsz */
+#define TO_PHYS_MASK    _LLCONST_(0x0000000fffffffff)   /* 2^^36 - 1 */
 #endif
 
 #if defined (CONFIG_CPU_R8000)
 /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
-#define KUSIZE                  0x0000010000000000      /* 2^^40 */
-#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
-#define K0SIZE                  0x0000010000000000      /* 2^^40 */
-#define K1SIZE                  0x0000010000000000      /* 2^^40 */
-#define K2SIZE                  0x0001000000000000
-#define KSEGSIZE                0x0000010000000000      /* max syssegsz */
-#define TO_PHYS_MASK            0x000000ffffffffff      /* 2^^40 - 1 */
+#define KUSIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define KUSIZE_64       _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K0SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K1SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K2SIZE          _LLCONST_(0x0001000000000000)
+#define KSEGSIZE        _LLCONST_(0x0000010000000000)   /* max syssegsz */
+#define TO_PHYS_MASK    _LLCONST_(0x000000ffffffffff)   /* 2^^40 - 1 */
 #endif
 
 #if defined (CONFIG_CPU_R10000)
-#define KUSIZE                  0x0000010000000000      /* 2^^40 */
-#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
-#define K0SIZE                  0x0000010000000000      /* 2^^40 */
-#define K1SIZE                  0x0000010000000000      /* 2^^40 */
-#define K2SIZE                  0x00000fff80000000
-#define KSEGSIZE                0x00000fff80000000      /* max syssegsz */
-#define TO_PHYS_MASK            0x000000ffffffffff      /* 2^^40 - 1 */
+#define KUSIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define KUSIZE_64       _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K0SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K1SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
+#define K2SIZE          _LLCONST_(0x00000fff80000000)
+#define KSEGSIZE        _LLCONST_(0x00000fff80000000)   /* max syssegsz */
+#define TO_PHYS_MASK    _LLCONST_(0x000000ffffffffff)   /* 2^^40 - 1 */
+#endif
+
+#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
+#define KUSIZE          _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define KUSIZE_64       _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define K0SIZE          _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define K1SIZE          _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define K2SIZE          _LLCONST_(0x0000ffff80000000)
+#define KSEGSIZE        _LLCONST_(0x0000ffff80000000)   /* max syssegsz */
+#define TO_PHYS_MASK    _LLCONST_(0x00000fffffffffff)   /* 2^^44 - 1 */
 #endif
 
 /*
  * Further names for SGI source compatibility.  These are stolen from
  * IRIX's <sys/mips_addrspace.h>.
  */
-#define KUBASE                  0
-#define KUSIZE_32               0x0000000080000000      /* KUSIZE
+#define KUBASE          _LLCONST_(0)
+#define KUSIZE_32       _LLCONST_(0x0000000080000000)   /* KUSIZE
                                                            for a 32 bit proc */
-#define K0BASE_EXL_WR           0xa800000000000000      /* exclusive on write */
-#define K0BASE_NONCOH           0x9800000000000000      /* noncoherent */
-#define K0BASE_EXL              0xa000000000000000      /* exclusive */
+#define K0BASE_EXL_WR   _LLCONST_(0xa800000000000000)   /* exclusive on write */
+#define K0BASE_NONCOH   _LLCONST_(0x9800000000000000)   /* noncoherent */
+#define K0BASE_EXL      _LLCONST_(0xa000000000000000)   /* exclusive */
 
 #ifndef CONFIG_CPU_R8000
 
@@ -176,7 +190,7 @@
  * in order to catch bugs in the source code.
  */
 
-#define COMPAT_K1BASE32         0xffffffffa0000000
+#define COMPAT_K1BASE32         _LLCONST_(0xffffffffa0000000)
 #define PHYS_TO_COMPATK1(x)     ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
 
 #endif
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index f53237772985..4b090f3142e0 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -107,6 +107,7 @@ symbol		=	value
 /*
  * Print formatted string
  */
+#ifdef CONFIG_PRINTK
 #define PRINT(string)                                   \
                 .set    push;                           \
                 .set    reorder;                        \
@@ -114,6 +115,9 @@ symbol		=	value
                 jal     printk;                         \
                 .set    pop;                            \
                 TEXT(string)
+#else
+#define PRINT(string)
+#endif
 
 #define TEXT(msg)                                       \
                 .pushsection .data;                     \
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index c0bd8d014e14..6202eb8a14b7 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -62,20 +62,24 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %1          # atomic_add            \n"
                 "       addu    %0, %2                                  \n"
                 "       sc      %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else if (cpu_has_llsc) {
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %1          # atomic_add            \n"
                 "       addu    %0, %2                                  \n"
                 "       sc      %0, %1                                  \n"
                 "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else {
@@ -100,20 +104,24 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %1          # atomic_sub            \n"
                 "       subu    %0, %2                                  \n"
                 "       sc      %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else if (cpu_has_llsc) {
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %1          # atomic_sub            \n"
                 "       subu    %0, %2                                  \n"
                 "       sc      %0, %1                                  \n"
                 "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else {
@@ -136,12 +144,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %1, %2          # atomic_add_return     \n"
                 "       addu    %0, %1, %3                              \n"
                 "       sc      %0, %2                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       addu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -149,12 +159,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %1, %2          # atomic_add_return     \n"
                 "       addu    %0, %1, %3                              \n"
                 "       sc      %0, %2                                  \n"
                 "       beqz    %0, 1b                                  \n"
                 "       addu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -179,12 +191,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %1, %2          # atomic_sub_return     \n"
                 "       subu    %0, %1, %3                              \n"
                 "       sc      %0, %2                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       subu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -192,12 +206,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %1, %2          # atomic_sub_return     \n"
                 "       subu    %0, %1, %3                              \n"
                 "       sc      %0, %2                                  \n"
                 "       beqz    %0, 1b                                  \n"
                 "       subu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -229,6 +245,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %1, %2          # atomic_sub_if_positive\n"
                 "       subu    %0, %1, %3                              \n"
                 "       bltz    %0, 1f                                  \n"
@@ -236,6 +253,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       beqzl   %0, 1b                                  \n"
                 "       sync                                            \n"
                 "1:                                                     \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -243,6 +261,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %1, %2          # atomic_sub_if_positive\n"
                 "       subu    %0, %1, %3                              \n"
                 "       bltz    %0, 1f                                  \n"
@@ -250,6 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       beqz    %0, 1b                                  \n"
                 "       sync                                            \n"
                 "1:                                                     \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -367,20 +387,24 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %1          # atomic64_add          \n"
                 "       addu    %0, %2                                  \n"
                 "       scd     %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else if (cpu_has_llsc) {
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %1          # atomic64_add          \n"
                 "       addu    %0, %2                                  \n"
                 "       scd     %0, %1                                  \n"
                 "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else {
@@ -405,20 +429,24 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %1          # atomic64_sub          \n"
                 "       subu    %0, %2                                  \n"
                 "       scd     %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else if (cpu_has_llsc) {
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %1          # atomic64_sub          \n"
                 "       subu    %0, %2                                  \n"
                 "       scd     %0, %1                                  \n"
                 "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter));
         } else {
@@ -441,12 +469,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %1, %2          # atomic64_add_return   \n"
                 "       addu    %0, %1, %3                              \n"
                 "       scd     %0, %2                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       addu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -454,12 +484,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %1, %2          # atomic64_add_return   \n"
                 "       addu    %0, %1, %3                              \n"
                 "       scd     %0, %2                                  \n"
                 "       beqz    %0, 1b                                  \n"
                 "       addu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -484,12 +516,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %1, %2          # atomic64_sub_return   \n"
                 "       subu    %0, %1, %3                              \n"
                 "       scd     %0, %2                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       subu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -497,12 +531,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %1, %2          # atomic64_sub_return   \n"
                 "       subu    %0, %1, %3                              \n"
                 "       scd     %0, %2                                  \n"
                 "       beqz    %0, 1b                                  \n"
                 "       subu    %0, %1, %3                              \n"
                 "       sync                                            \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -534,6 +570,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
                 "       dsubu   %0, %1, %3                              \n"
                 "       bltz    %0, 1f                                  \n"
@@ -541,6 +578,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 "       beqzl   %0, 1b                                  \n"
                 "       sync                                            \n"
                 "1:                                                     \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
@@ -548,6 +586,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
                 "       dsubu   %0, %1, %3                              \n"
                 "       bltz    %0, 1f                                  \n"
@@ -555,6 +594,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 "       beqz    %0, 1b                                  \n"
                 "       sync                                            \n"
                 "1:                                                     \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index eb8d79dba11c..5496f9064a6a 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -12,20 +12,21 @@
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <asm/bug.h>
 #include <asm/byteorder.h>              /* sigh ... */
 #include <asm/cpu-features.h>
 
 #if (_MIPS_SZLONG == 32)
 #define SZLONG_LOG 5
 #define SZLONG_MASK 31UL
-#define __LL    "ll     "
-#define __SC    "sc     "
+#define __LL            "ll     "
+#define __SC            "sc     "
 #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
-#define __LL    "lld    "
-#define __SC    "scd    "
+#define __LL            "lld    "
+#define __SC            "scd    "
 #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
 #endif
 
@@ -72,18 +73,22 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     " __LL "%0, %1                  # set_bit       \n"
                 "       or      %0, %2                                  \n"
-                "       "__SC   "%0, %1                                 \n"
+                "       " __SC  "%0, %1                                 \n"
                 "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     " __LL "%0, %1                  # set_bit       \n"
                 "       or      %0, %2                                  \n"
-                "       "__SC   "%0, %1                                 \n"
+                "       " __SC  "%0, %1                                 \n"
                 "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
         } else {
@@ -132,18 +137,22 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     " __LL "%0, %1                  # clear_bit     \n"
                 "       and     %0, %2                                  \n"
                 "       " __SC "%0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     " __LL "%0, %1                  # clear_bit     \n"
                 "       and     %0, %2                                  \n"
                 "       " __SC "%0, %1                                  \n"
                 "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
         } else {
@@ -191,10 +200,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                           \n"
                 "1:     " __LL "%0, %1          # change_bit    \n"
                 "       xor     %0, %2                          \n"
-                "       "__SC   "%0, %1                         \n"
+                "       " __SC  "%0, %1                         \n"
                 "       beqzl   %0, 1b                          \n"
+                "       .set    mips0                           \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
         } else if (cpu_has_llsc) {
@@ -202,10 +213,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                 unsigned long temp;
 
                 __asm__ __volatile__(
+                "       .set    mips3                           \n"
                 "1:     " __LL "%0, %1          # change_bit    \n"
                 "       xor     %0, %2                          \n"
-                "       "__SC   "%0, %1                         \n"
+                "       " __SC  "%0, %1                         \n"
                 "       beqz    %0, 1b                          \n"
+                "       .set    mips0                           \n"
                 : "=&r" (temp), "=m" (*m)
                 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
         } else {
@@ -253,14 +266,16 @@ static inline int test_and_set_bit(unsigned long nr,
                 unsigned long temp, res;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     " __LL "%0, %1          # test_and_set_bit      \n"
                 "       or      %2, %0, %3                              \n"
                 "       " __SC  "%2, %1                                 \n"
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
-                "sync                                                   \n"
+                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
                 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                 : "memory");
@@ -271,16 +286,18 @@ static inline int test_and_set_bit(unsigned long nr,
                 unsigned long temp, res;
 
                 __asm__ __volatile__(
-                "       .set    noreorder       # test_and_set_bit      \n"
-                "1:     " __LL "%0, %1                                  \n"
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
                 "       or      %2, %0, %3                              \n"
                 "       " __SC  "%2, %1                                 \n"
                 "       beqz    %2, 1b                                  \n"
                 "        and    %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
-                "sync                                                   \n"
+                "       sync                                            \n"
 #endif
-                ".set\treorder"
+                "       .set    pop                                     \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
                 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                 : "memory");
@@ -343,15 +360,17 @@ static inline int test_and_clear_bit(unsigned long nr,
                 unsigned long temp, res;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                 "       or      %2, %0, %3                              \n"
                 "       xor     %2, %3                                  \n"
-                        __SC    "%2, %1                                 \n"
+                "       " __SC  "%2, %1                                 \n"
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
                 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                 : "memory");
@@ -362,17 +381,19 @@ static inline int test_and_clear_bit(unsigned long nr,
                 unsigned long temp, res;
 
                 __asm__ __volatile__(
-                "       .set    noreorder       # test_and_clear_bit    \n"
-                "1:     " __LL  "%0, %1                                 \n"
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                 "       or      %2, %0, %3                              \n"
                 "       xor     %2, %3                                  \n"
-                        __SC    "%2, %1                                 \n"
+                "       " __SC  "%2, %1                                 \n"
                 "       beqz    %2, 1b                                  \n"
                 "        and    %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
-                "       .set    reorder                                 \n"
+                "       .set    pop                                     \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
                 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                 : "memory");
@@ -435,14 +456,16 @@ static inline int test_and_change_bit(unsigned long nr,
                 unsigned long temp, res;
 
                 __asm__ __volatile__(
-                "1:     " __LL  " %0, %1        # test_and_change_bit   \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
                 "       xor     %2, %0, %3                              \n"
-                "       "__SC   "%2, %1                                 \n"
+                "       " __SC  "%2, %1                                 \n"
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
                 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                 : "memory");
@@ -453,16 +476,18 @@ static inline int test_and_change_bit(unsigned long nr,
                 unsigned long temp, res;
 
                 __asm__ __volatile__(
-                "       .set    noreorder       # test_and_change_bit   \n"
-                "1:     " __LL  " %0, %1                                \n"
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
                 "       xor     %2, %0, %3                              \n"
-                "       "__SC   "\t%2, %1                               \n"
+                "       " __SC  "\t%2, %1                               \n"
                 "       beqz    %2, 1b                                  \n"
                 "        and    %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
-                "       .set    reorder                                 \n"
+                "       .set    pop                                     \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
                 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                 : "memory");
@@ -523,22 +548,60 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
 }
 
 /*
- * ffz - find first zero in word.
+ * Return the bit position (0..63) of the most significant 1 bit in a word
+ * Returns -1 if no 1 bit exists
+ */
+static inline int __ilog2(unsigned long x)
+{
+        int lz;
+
+        if (sizeof(x) == 4) {
+                __asm__ (
+                "       .set    push                                    \n"
+                "       .set    mips32                                  \n"
+                "       clz     %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (lz)
+                : "r" (x));
+
+                return 31 - lz;
+        }
+
+        BUG_ON(sizeof(x) != 8);
+
+        __asm__ (
+        "       .set    push                                            \n"
+        "       .set    mips64                                          \n"
+        "       dclz    %0, %1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (lz)
+        : "r" (x));
+
+        return 63 - lz;
+}
+
+/*
+ * __ffs - find first bit in word.
  * @word: The word to search
  *
- * Undefined if no zero exists, so code should check against ~0UL first.
+ * Returns 0..SZLONG-1
+ * Undefined if no bit exists, so code should check against 0 first.
  */
-static inline unsigned long ffz(unsigned long word)
+static inline unsigned long __ffs(unsigned long word)
 {
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+        return __ilog2(word & -word);
+#else
         int b = 0, s;
 
-        word = ~word;
 #ifdef CONFIG_32BIT
         s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
         s =  8; if (word << 24 != 0) s = 0; b += s; word >>= s;
         s =  4; if (word << 28 != 0) s = 0; b += s; word >>= s;
         s =  2; if (word << 30 != 0) s = 0; b += s; word >>= s;
         s =  1; if (word << 31 != 0) s = 0; b += s;
+
+        return b;
 #endif
 #ifdef CONFIG_64BIT
         s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
@@ -547,27 +610,92 @@ static inline unsigned long ffz(unsigned long word)
         s =  4; if (word << 60 != 0) s = 0; b += s; word >>= s;
         s =  2; if (word << 62 != 0) s = 0; b += s; word >>= s;
         s =  1; if (word << 63 != 0) s = 0; b += s;
-#endif
 
         return b;
+#endif
+#endif
 }
 
 /*
- * __ffs - find first bit in word.
+ * ffs - find first bit set.
  * @word: The word to search
  *
- * Undefined if no bit exists, so code should check against 0 first.
+ * Returns 1..SZLONG
+ * Returns 0 if no bit exists
  */
-static inline unsigned long __ffs(unsigned long word)
+
+static inline unsigned long ffs(unsigned long word)
 {
-        return ffz(~word);
+        if (!word)
+                return 0;
+
+        return __ffs(word) + 1;
 }
 
 /*
- * fls: find last bit set.
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        return __ffs (~word);
+}
+
+/*
+ * flz - find last zero in word.
+ * @word: The word to search
+ *
+ * Returns 0..SZLONG-1
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long flz(unsigned long word)
+{
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+        return __ilog2(~word);
+#else
+#ifdef CONFIG_32BIT
+        int r = 31, s;
+        word = ~word;
+        s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s;
+        s = 8;  if ((word & 0xff000000)) s = 0; r -= s; word <<= s;
+        s = 4;  if ((word & 0xf0000000)) s = 0; r -= s; word <<= s;
+        s = 2;  if ((word & 0xc0000000)) s = 0; r -= s; word <<= s;
+        s = 1;  if ((word & 0x80000000)) s = 0; r -= s;
+
+        return r;
+#endif
+#ifdef CONFIG_64BIT
+        int r = 63, s;
+        word = ~word;
+        s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s;
+        s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 8;  if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 4;  if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 2;  if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 1;  if ((word & 0x8000000000000000UL)) s = 0; r -= s;
+
+        return r;
+#endif
+#endif
+}
+
+/*
+ * fls - find last bit set.
+ * @word: The word to search
+ *
+ * Returns 1..SZLONG
+ * Returns 0 if no bit exists
  */
+static inline unsigned long fls(unsigned long word)
+{
+        if (word == 0)
+                return 0;
+
+        return flz(~word) + 1;
+}
 
-#define fls(x) generic_fls(x)
 
 /*
  * find_next_zero_bit - find the first zero bit in a memory region
@@ -704,17 +832,6 @@ static inline int sched_find_first_bit(const unsigned long *b)
 }
 
 /*
- * ffs - find first bit set
- * @x: the word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-
-#define ffs(x) generic_ffs(x)
-
-/*
  * hweightN - returns the hamming weight of a N-bit word
  * @x: the word to weigh
  *
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b1e57d783604..14fc88f27226 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -77,6 +77,7 @@
 #define  MACH_SGI_IP27          1       /* Origin 200, Origin 2000, Onyx 2 */
 #define  MACH_SGI_IP28          2       /* Indigo2 Impact               */
 #define  MACH_SGI_IP32          3       /* O2                           */
+#define  MACH_SGI_IP30          4       /* Octane, Octane2              */
 
 /*
  * Valid machtype for group COBALT
@@ -136,6 +137,7 @@
 #define MACH_GROUP_PHILIPS     14
 #define  MACH_PHILIPS_NINO      0       /* Nino */
 #define  MACH_PHILIPS_VELO      1       /* Velo */
+#define  MACH_PHILIPS_JBS       2       /* JBS */
 
 /*
  * Valid machtype for group Globespan
@@ -159,6 +161,7 @@
 #define  MACH_TOSHIBA_JMR3927   3       /* JMR-TX3927 CPU/IO board */
 #define  MACH_TOSHIBA_RBTX4927  4
 #define  MACH_TOSHIBA_RBTX4937  5
+#define  MACH_TOSHIBA_RBTX4938  6
 
 #define GROUP_TOSHIBA_NAMES     { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
                                   "RBTX4927", "RBTX4937" }
@@ -177,6 +180,8 @@
 #define  MACH_MTX1              7       /* 4G MTX-1 Au1500-based board */
 #define  MACH_PB1550            8       /* Au1550-based eval board */
 #define  MACH_DB1550            9       /* Au1550-based eval board */
+#define  MACH_PB1200            10       /* Au1200-based eval board */
+#define  MACH_DB1200            11       /* Au1200-based eval board */
 
 /*
  * Valid machtype for group NEC_VR41XX
diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h
index 2e6de788f207..25b980c91e7e 100644
--- a/include/asm-mips/break.h
+++ b/include/asm-mips/break.h
@@ -28,6 +28,7 @@
 #define BRK_NORLD       10      /* No rld found - not used by Linux/MIPS */
 #define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
 #define BRK_BUG         512     /* Used by BUG() */
+#define BRK_KDB         513     /* Used in KDB_ENTER() */
 #define BRK_MULOVF      1023    /* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
index 3f594b440abc..87d49a5bdc63 100644
--- a/include/asm-mips/bug.h
+++ b/include/asm-mips/bug.h
@@ -1,16 +1,21 @@
 #ifndef __ASM_BUG_H
 #define __ASM_BUG_H
 
-#include <asm/break.h>
+#include <linux/config.h>
 
 #ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
+
+#include <asm/break.h>
+
 #define BUG()                                                           \
 do {                                                                    \
         __asm__ __volatile__("break %0" : : "i" (BRK_BUG));             \
 } while (0)
+
+#define HAVE_ARCH_BUG
+
 #endif
 
 #include <asm-generic/bug.h>
 
-#endif
+#endif /* __ASM_BUG_H */
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index b14b961c2100..cb2ea7c15c7a 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -8,12 +8,18 @@
 #define _ASM_BUGS_H
 
 #include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
 
 extern void check_bugs32(void);
 extern void check_bugs64(void);
 
 static inline void check_bugs(void)
 {
+        unsigned int cpu = smp_processor_id();
+
+        cpu_data[cpu].udelay_val = loops_per_jiffy;
         check_bugs32();
 #ifdef CONFIG_64BIT
         check_bugs64();
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
index 4517bdf20953..1a5d1a669db3 100644
--- a/include/asm-mips/cache.h
+++ b/include/asm-mips/cache.h
@@ -10,6 +10,7 @@
 #define _ASM_CACHE_H
 
 #include <linux/config.h>
+#include <kmalloc.h>
 
 #define L1_CACHE_SHIFT          CONFIG_MIPS_L1_CACHE_SHIFT
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
@@ -18,6 +19,4 @@
 #define SMP_CACHE_SHIFT         L1_CACHE_SHIFT
 #define SMP_CACHE_BYTES         L1_CACHE_BYTES
 
-#define ARCH_KMALLOC_MINALIGN   8
-
 #endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 635f1bfb403e..a18ba2edc0b6 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -49,17 +49,29 @@ static inline void flush_dcache_page(struct page *page)
 
 extern void (*flush_icache_page)(struct vm_area_struct *vma,
         struct page *page);
-extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*flush_icache_range)(unsigned long __user start,
+        unsigned long __user end);
 #define flush_cache_vmap(start, end)            flush_cache_all()
 #define flush_cache_vunmap(start, end)          flush_cache_all()
 
-#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
-do {                                                                    \
-        memcpy(dst, (void *) src, len);                                 \
-        flush_icache_page(vma, page);                                   \
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
-        memcpy(dst, src, len)
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len)
+{
+        if (cpu_has_dc_aliases)
+                flush_cache_page(vma, vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+        flush_icache_page(vma, page);
+}
+
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len)
+{
+        if (cpu_has_dc_aliases)
+                flush_cache_page(vma, vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+}
 
 extern void (*flush_cache_sigtramp)(unsigned long addr);
 extern void (*flush_icache_all)(void);
@@ -78,4 +90,7 @@ extern void (*flush_data_cache_page)(unsigned long addr);
 #define ClearPageDcacheDirty(page)      \
         clear_bit(PG_dcache_dirty, &(page)->flags)
 
+/* Run kernel code uncached, useful for cache probing functions. */
+unsigned long __init run_uncached(void *func);
+
 #endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
index c1ea5a8714f3..b09f8971e95d 100644
--- a/include/asm-mips/checksum.h
+++ b/include/asm-mips/checksum.h
@@ -34,8 +34,9 @@ unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
  * this is a new version of the above that records errors it finds in *errp,
  * but continues and zeros the rest of the buffer.
  */
-unsigned int csum_partial_copy_from_user(const unsigned char *src, unsigned char *dst, int len,
-                                         unsigned int sum, int *errp);
+unsigned int csum_partial_copy_from_user(const unsigned char __user *src,
+                                         unsigned char *dst, int len,
+                                         unsigned int sum, int *errp);
 
 /*
  * Copy and checksum to user
@@ -70,14 +71,15 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *
 static inline unsigned short int csum_fold(unsigned int sum)
 {
         __asm__(
-        ".set\tnoat\t\t\t# csum_fold\n\t"
-        "sll\t$1,%0,16\n\t"
-        "addu\t%0,$1\n\t"
-        "sltu\t$1,%0,$1\n\t"
-        "srl\t%0,%0,16\n\t"
-        "addu\t%0,$1\n\t"
-        "xori\t%0,0xffff\n\t"
-        ".set\tat"
+        "       .set    push            # csum_fold\n"
+        "       .set    noat            \n"
+        "       sll     $1, %0, 16      \n"
+        "       addu    %0, $1          \n"
+        "       sltu    $1, %0, $1      \n"
+        "       srl     %0, %0, 16      \n"
+        "       addu    %0, $1          \n"
+        "       xori    %0, 0xffff      \n"
+        "       .set    pop"
         : "=r" (sum)
         : "0" (sum));
 
@@ -127,29 +129,30 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
         unsigned int sum)
 {
         __asm__(
-        ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
+        "       .set    push            # csum_tcpudp_nofold\n"
+        "       .set    noat            \n"
 #ifdef CONFIG_32BIT
-        "addu\t%0, %2\n\t"
-        "sltu\t$1, %0, %2\n\t"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, %2          \n"
+        "       sltu    $1, %0, %2      \n"
+        "       addu    %0, $1          \n"
 
-        "addu\t%0, %3\n\t"
-        "sltu\t$1, %0, %3\n\t"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, %3          \n"
+        "       sltu    $1, %0, %3      \n"
+        "       addu    %0, $1          \n"
 
-        "addu\t%0, %4\n\t"
-        "sltu\t$1, %0, %4\n\t"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, %4          \n"
+        "       sltu    $1, %0, %4      \n"
+        "       addu    %0, $1          \n"
 #endif
 #ifdef CONFIG_64BIT
-        "daddu\t%0, %2\n\t"
-        "daddu\t%0, %3\n\t"
-        "daddu\t%0, %4\n\t"
-        "dsll32\t$1, %0, 0\n\t"
-        "daddu\t%0, $1\n\t"
-        "dsrl32\t%0, %0, 0\n\t"
+        "       daddu   %0, %2          \n"
+        "       daddu   %0, %3          \n"
+        "       daddu   %0, %4          \n"
+        "       dsll32  $1, %0, 0       \n"
+        "       daddu   %0, $1          \n"
+        "       dsra32  %0, %0, 0       \n"
 #endif
-        ".set\tat"
+        "       .set    pop"
         : "=r" (sum)
         : "0" (daddr), "r"(saddr),
 #ifdef __MIPSEL__
@@ -192,57 +195,57 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
                                                      unsigned int sum)
 {
         __asm__(
-        ".set\tpush\t\t\t# csum_ipv6_magic\n\t"
-        ".set\tnoreorder\n\t"
-        ".set\tnoat\n\t"
-        "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t"
-        "sltu\t$1, %0, %5\n\t"
-        "addu\t%0, $1\n\t"
-
-        "addu\t%0, %6\t\t\t# csum\n\t"
-        "sltu\t$1, %0, %6\n\t"
-        "lw\t%1, 0(%2)\t\t\t# four words source address\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 4(%2)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 8(%2)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 12(%2)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 0(%3)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 4(%3)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 8(%3)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "lw\t%1, 12(%3)\n\t"
-        "addu\t%0, $1\n\t"
-        "addu\t%0, %1\n\t"
-        "sltu\t$1, %0, %1\n\t"
-
-        "addu\t%0, $1\t\t\t# Add final carry\n\t"
-        ".set\tpop"
+        "       .set    push            # csum_ipv6_magic\n"
+        "       .set    noreorder       \n"
+        "       .set    noat            \n"
+        "       addu    %0, %5          # proto (long in network byte order)\n"
+        "       sltu    $1, %0, %5      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %6          # csum\n"
+        "       sltu    $1, %0, %6      \n"
+        "       lw      %1, 0(%2)       # four words source address\n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 4(%2)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 8(%2)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 12(%2)      \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 0(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 4(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 8(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 12(%3)      \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       addu    %0, $1          # Add final carry\n"
+        "       .set    pop"
         : "=r" (sum), "=r" (proto)
         : "r" (saddr), "r" (daddr),
           "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h
index ca1fbc0579fe..78e1df2095fb 100644
--- a/include/asm-mips/cobalt/cobalt.h
+++ b/include/asm-mips/cobalt/cobalt.h
@@ -19,18 +19,23 @@
  *     9  - PCI
  *    14  - IDE0
  *    15  - IDE1
- *
+ */
+#define COBALT_QUBE_SLOT_IRQ    9
+
+/*
  * CPU IRQs  are 16 ... 23
  */
-#define COBALT_TIMER_IRQ        18
-#define COBALT_SCC_IRQ          19              /* pre-production has 85C30 */
-#define COBALT_RAQ_SCSI_IRQ     19
-#define COBALT_ETH0_IRQ         19
-#define COBALT_ETH1_IRQ         20
-#define COBALT_SERIAL_IRQ       21
-#define COBALT_SCSI_IRQ         21
-#define COBALT_VIA_IRQ          22              /* Chained to VIA ISA bridge */
-#define COBALT_QUBE_SLOT_IRQ    23
+#define COBALT_CPU_IRQ          16
+
+#define COBALT_GALILEO_IRQ      (COBALT_CPU_IRQ + 2)
+#define COBALT_SCC_IRQ          (COBALT_CPU_IRQ + 3)    /* pre-production has 85C30 */
+#define COBALT_RAQ_SCSI_IRQ     (COBALT_CPU_IRQ + 3)
+#define COBALT_ETH0_IRQ         (COBALT_CPU_IRQ + 3)
+#define COBALT_QUBE1_ETH0_IRQ   (COBALT_CPU_IRQ + 4)
+#define COBALT_ETH1_IRQ         (COBALT_CPU_IRQ + 4)
+#define COBALT_SERIAL_IRQ       (COBALT_CPU_IRQ + 5)
+#define COBALT_SCSI_IRQ         (COBALT_CPU_IRQ + 5)
+#define COBALT_VIA_IRQ          (COBALT_CPU_IRQ + 6)    /* Chained to VIA ISA bridge */
 
 /*
  * PCI configuration space manifest constants.  These are wired into
@@ -69,16 +74,21 @@
  * Most of this really should go into a separate GT64111 header file.
  */
 #define GT64111_IO_BASE         0x10000000UL
+#define GT64111_IO_END          0x11ffffffUL
+#define GT64111_MEM_BASE        0x12000000UL
+#define GT64111_MEM_END         0x13ffffffUL
 #define GT64111_BASE            0x14000000UL
-#define GALILEO_REG(ofs)        (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
+#define GALILEO_REG(ofs)        CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
 
 #define GALILEO_INL(port)       (*(volatile unsigned int *) GALILEO_REG(port))
 #define GALILEO_OUTL(val, port)                                         \
 do {                                                                    \
-        *(volatile unsigned int *) GALILEO_REG(port) = (port);          \
+        *(volatile unsigned int *) GALILEO_REG(port) = (val);           \
 } while (0)
 
-#define GALILEO_T0EXP           0x0100
+#define GALILEO_INTR_T0EXP      (1 << 8)
+#define GALILEO_INTR_RETRY_CTR  (1 << 20)
+
 #define GALILEO_ENTC0           0x01
 #define GALILEO_SELTC0          0x02
 
@@ -86,5 +96,21 @@ do {									\
         GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) |           \
                 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
 
+#define COBALT_LED_PORT         (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
+# define COBALT_LED_BAR_LEFT    (1 << 0)        /* Qube */
+# define COBALT_LED_BAR_RIGHT   (1 << 1)        /* Qube */
+# define COBALT_LED_WEB         (1 << 2)        /* RaQ */
+# define COBALT_LED_POWER_OFF   (1 << 3)        /* RaQ */
+# define COBALT_LED_RESET       0x0f
+
+#define COBALT_KEY_PORT         ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
+# define COBALT_KEY_CLEAR       (1 << 1)
+# define COBALT_KEY_LEFT        (1 << 2)
+# define COBALT_KEY_UP          (1 << 3)
+# define COBALT_KEY_DOWN        (1 << 4)
+# define COBALT_KEY_RIGHT       (1 << 5)
+# define COBALT_KEY_ENTER       (1 << 6)
+# define COBALT_KEY_SELECT      (1 << 7)
+# define COBALT_KEY_MASK        0xfe
 
 #endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/cobalt/mach-gt64120.h
new file mode 100644
index 000000000000..587fc4378f44
--- /dev/null
+++ b/include/asm-mips/cobalt/mach-gt64120.h
@@ -0,0 +1 @@
+/* there's something here ... in the dark */
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index 2c084cd4bc0a..35d2604fe69c 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -15,10 +15,10 @@ typedef s32		compat_clock_t;
 typedef s32             compat_suseconds_t;
 
 typedef s32             compat_pid_t;
-typedef u32             __compat_uid_t;
-typedef u32             __compat_gid_t;
-typedef u32             __compat_uid32_t;
-typedef u32             __compat_gid32_t;
+typedef s32             __compat_uid_t;
+typedef s32             __compat_gid_t;
+typedef __compat_uid_t  __compat_uid32_t;
+typedef __compat_gid_t  __compat_gid32_t;
 typedef u32             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u32             compat_dev_t;
@@ -54,8 +54,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        __compat_uid32_t        st_uid;
-        __compat_gid32_t        st_gid;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
         compat_dev_t    st_rdev;
         s32             st_pad2[2];
         compat_off_t    st_size;
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 9a2de642eee6..03627cfb3e45 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -4,6 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef __ASM_CPU_FEATURES_H
 #define __ASM_CPU_FEATURES_H
@@ -24,8 +25,19 @@
 #ifndef cpu_has_4kex
 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
 #endif
-#ifndef cpu_has_4ktlb
-#define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
+#ifndef cpu_has_3k_cache
+#define cpu_has_3k_cache        (cpu_data[0].options & MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache        0
+#define cpu_has_8k_cache        0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache        (cpu_data[0].options & MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache      (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_sb1_cache
+#define cpu_has_sb1_cache       (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
 #endif
 #ifndef cpu_has_fpu
 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
@@ -39,9 +51,6 @@
 #ifndef cpu_has_watch
 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
 #endif
-#ifndef cpu_has_mips16
-#define cpu_has_mips16          (cpu_data[0].options & MIPS_CPU_MIPS16)
-#endif
 #ifndef cpu_has_divec
 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
 #endif
@@ -66,6 +75,18 @@
 #ifndef cpu_has_llsc
 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
 #endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
@@ -95,15 +116,16 @@
 #endif
 #endif
 
-/*
- * Certain CPUs may throw bizarre exceptions if not the whole cacheline
- * contains valid instructions.  For these we ensure proper alignment of
- * signal trampolines and pad them to the size of a full cache lines with
- * nops.  This is also used in structure definitions so can't be a test macro
- * like the others.
- */
-#ifndef PLAT_TRAMPOLINE_STUFF_LINE
-#define PLAT_TRAMPOLINE_STUFF_LINE      0UL
+#ifndef cpu_has_dsp
+#define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
+#endif
+
+#ifdef CONFIG_MIPS_MT
+#ifndef cpu_has_mipsmt
+# define cpu_has_mipsmt         (cpu_data[0].ases & MIPS_ASE_MIPSMT)
+#endif
+#else
+# define cpu_has_mipsmt         0
 #endif
 
 #ifdef CONFIG_32BIT
@@ -142,6 +164,22 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_MIPSR2
+# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+#  define cpu_has_vint          (cpu_data[0].options & MIPS_CPU_VINT)
+# else
+#  define cpu_has_vint                  0
+# endif
+# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+#  define cpu_has_veic          (cpu_data[0].options & MIPS_CPU_VEIC)
+# else
+#  define cpu_has_veic                  0
+# endif
+#else
+# define cpu_has_vint                   0
+# define cpu_has_veic                   0
+#endif
+
 #ifndef cpu_has_subset_pcaches
 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 #endif
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 20a35b15a31d..d5cf519f8fcc 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -7,6 +7,7 @@
  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
  * Copyright (C) 1996 Paul M. Antoine
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef __ASM_CPU_INFO_H
 #define __ASM_CPU_INFO_H
@@ -61,6 +62,7 @@ struct cpuinfo_mips {
          * Capability and feature descriptor structure for MIPS CPU
          */
         unsigned long           options;
+        unsigned long           ases;
         unsigned int            processor_id;
         unsigned int            fpu_id;
         unsigned int            cputype;
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index dec060b49556..48eac296060f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -3,6 +3,7 @@
  *        various MIPS cpu types.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_CPU_H
 #define _ASM_CPU_H
@@ -22,12 +23,17 @@
    spec.
 */
 
-#define PRID_COMP_LEGACY       0x000000
-#define PRID_COMP_MIPS         0x010000
-#define PRID_COMP_BROADCOM     0x020000
-#define PRID_COMP_ALCHEMY      0x030000
-#define PRID_COMP_SIBYTE       0x040000
-#define PRID_COMP_SANDCRAFT    0x050000
+#define PRID_COMP_LEGACY        0x000000
+#define PRID_COMP_MIPS          0x010000
+#define PRID_COMP_BROADCOM      0x020000
+#define PRID_COMP_ALCHEMY       0x030000
+#define PRID_COMP_SIBYTE        0x040000
+#define PRID_COMP_SANDCRAFT     0x050000
+#define PRID_COMP_PHILIPS       0x060000
+#define PRID_COMP_TOSHIBA       0x070000
+#define PRID_COMP_LSI           0x080000
+#define PRID_COMP_LEXRA         0x0b0000
+
 
 /*
  * Assigned values for the product ID register.  In order to detect a
@@ -46,6 +52,7 @@
 #define PRID_IMP_VR41XX         0x0c00
 #define PRID_IMP_R12000         0x0e00
 #define PRID_IMP_R8000          0x1000
+#define PRID_IMP_PR4450         0x1200
 #define PRID_IMP_R4600          0x2000
 #define PRID_IMP_R4700          0x2100
 #define PRID_IMP_TX39           0x2200
@@ -60,6 +67,13 @@
 #define PRID_IMP_RM9000         0x3400
 #define PRID_IMP_R5432          0x5400
 #define PRID_IMP_R5500          0x5500
+
+#define PRID_IMP_UNKNOWN        0xff00
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
+
 #define PRID_IMP_4KC            0x8000
 #define PRID_IMP_5KC            0x8100
 #define PRID_IMP_20KC           0x8200
@@ -71,14 +85,15 @@
 #define PRID_IMP_4KEMPR2        0x9100
 #define PRID_IMP_4KSD           0x9200
 #define PRID_IMP_24K            0x9300
-
-#define PRID_IMP_UNKNOWN        0xff00
+#define PRID_IMP_34K            0x9500
+#define PRID_IMP_24KE           0x9600
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  */
 
 #define PRID_IMP_SB1            0x0100
+#define PRID_IMP_SB1A           0x1100
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -177,7 +192,11 @@
 #define CPU_VR4133              56
 #define CPU_AU1550              57
 #define CPU_24K                 58
-#define CPU_LAST                58
+#define CPU_AU1200              59
+#define CPU_34K                 60
+#define CPU_PR4450              61
+#define CPU_SB1A                62
+#define CPU_LAST                62
 
 /*
  * ISA Level encodings
@@ -200,23 +219,37 @@
  * CPU Option encodings
  */
 #define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
-/* Leave a spare bit for variant MMU types... */
-#define MIPS_CPU_4KEX           0x00000004 /* "R4K" exception model */
-#define MIPS_CPU_4KTLB          0x00000008 /* "R4K" TLB handler */
-#define MIPS_CPU_FPU            0x00000010 /* CPU has FPU */
-#define MIPS_CPU_32FPR          0x00000020 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER        0x00000040 /* Cycle count/compare */
-#define MIPS_CPU_WATCH          0x00000080 /* watchpoint registers */
-#define MIPS_CPU_MIPS16         0x00000100 /* code compression */
-#define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
-#define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
-#define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
-#define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
-#define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
-#define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_SUBSET_CACHES  0x00020000 /* P-cache subset enforced */
-#define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_4KEX           0x00000002 /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
+#define MIPS_CPU_SB1_CACHE      0x00000020 /* SB1-style caches */
+#define MIPS_CPU_FPU            0x00000040 /* CPU has FPU */
+#define MIPS_CPU_32FPR          0x00000080 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER        0x00000100 /* Cycle count/compare */
+#define MIPS_CPU_WATCH          0x00000200 /* watchpoint registers */
+#define MIPS_CPU_DIVEC          0x00000400 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE            0x00000800 /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P   0x00001000 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S   0x00002000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK         0x00004000 /* Machine check exception */
+#define MIPS_CPU_EJTAG          0x00008000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX        0x00010000 /* no FPU exception */
+#define MIPS_CPU_LLSC           0x00020000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_SUBSET_CACHES  0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH       0x00080000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT           0x00100000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC           0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
+
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16         0x00000001 /* code compression */
+#define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
+#define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
+
 
 #endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
index 724908b0bf13..19495a490e72 100644
--- a/include/asm-mips/dec/ecc.h
+++ b/include/asm-mips/dec/ecc.h
@@ -49,7 +49,8 @@ struct pt_regs;
 
 extern void dec_ecc_be_init(void);
 extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id,
+                                        struct pt_regs *regs);
 #endif
 
 #endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
index 5e18a7510592..4cbc1f8a1129 100644
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ b/include/asm-mips/dec/ioasic_addrs.h
@@ -45,7 +45,8 @@
 
 
 /*
- * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
+ * Offsets for I/O ASIC registers
+ * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
  */
                                         /* all systems */
 #define IO_REG_SCSI_DMA_P       0x00    /* SCSI DMA Pointer */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
index 946943502f83..eb522aa1e226 100644
--- a/include/asm-mips/dec/kn01.h
+++ b/include/asm-mips/dec/kn01.h
@@ -8,14 +8,12 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_DEC_KN01_H
 #define __ASM_MIPS_DEC_KN01_H
 
-#include <asm/addrspace.h>
-
-#define KN01_SLOT_BASE  KSEG1ADDR(0x10000000)
+#define KN01_SLOT_BASE  0x10000000
 #define KN01_SLOT_SIZE  0x01000000
 
 /*
@@ -41,17 +39,9 @@
 
 
 /*
- * Some port addresses...
- */
-#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE)   /* 0xB8000000 */
-#define KN01_DZ11_BASE  (KN01_SLOT_BASE + KN01_DZ11)    /* 0xBC000000 */
-#define KN01_RTC_BASE   (KN01_SLOT_BASE + KN01_RTC)     /* 0xBD000000 */
-
-
-/*
  * Frame buffer memory address.
  */
-#define KN01_VFB_MEM    KSEG1ADDR(0x0fc00000)
+#define KN01_VFB_MEM    0x0fc00000
 
 /*
  * CPU interrupt bits.
@@ -80,4 +70,22 @@
 #define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
 #define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
 
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct pt_regs;
+
+extern u16 cached_kn01_csr;
+extern spinlock_t kn01_lock;
+
+extern void dec_kn01_be_init(void);
+extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
+                                         struct pt_regs *regs);
+#endif
+
 #endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index f797f7045920..8319ad77b250 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -8,21 +8,12 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_DEC_KN02_H
 #define __ASM_MIPS_DEC_KN02_H
 
-#ifndef __ASSEMBLY__
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#endif
-
-#include <asm/addrspace.h>
-#include <asm/dec/ecc.h>
-
-
-#define KN02_SLOT_BASE  KSEG1ADDR(0x1fc00000)
+#define KN02_SLOT_BASE  0x1fc00000
 #define KN02_SLOT_SIZE  0x00080000
 
 /*
@@ -39,22 +30,14 @@
 
 
 /*
- * Some port addresses...
- */
-#define KN02_DZ11_BASE  (KN02_SLOT_BASE + KN02_DZ11)    /* DZ11 */
-#define KN02_RTC_BASE   (KN02_SLOT_BASE + KN02_RTC)     /* RTC */
-#define KN02_CSR_BASE   (KN02_SLOT_BASE + KN02_CSR)     /* CSR */
-
-
-/*
  * System Control & Status Register bits.
  */
 #define KN02_CSR_RES_28         (0xf<<28)       /* unused */
 #define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
 #define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
 #define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
-#define KN03_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
-#define KN03_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
+#define KN02_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
+#define KN02_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
 #define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
 #define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
 #define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
@@ -63,8 +46,8 @@
 #define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
 #define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
 #define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
-#define KN03_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
-#define KN03_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
+#define KN02_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
+#define KN02_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
 
 
 /*
@@ -98,6 +81,10 @@
 
 
 #ifndef __ASSEMBLY__
+
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
 extern u32 cached_kn02_csr;
 extern spinlock_t kn02_lock;
 extern void init_kn02_irqs(int base);
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
index 648c4dcbba1d..a25f3d7da7f7 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/include/asm-mips/dec/kn02xa.h
@@ -9,7 +9,7 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
  *
  * These are addresses which have to be known early in the boot process.
  * For other addresses refer to tc.h, ioasic_addrs.h and friends.
@@ -17,31 +17,23 @@
 #ifndef __ASM_MIPS_DEC_KN02XA_H
 #define __ASM_MIPS_DEC_KN02XA_H
 
-#include <asm/addrspace.h>
 #include <asm/dec/ioasic_addrs.h>
 
-#define KN02XA_SLOT_BASE        KSEG1ADDR(0x1c000000)
-
-/*
- * Some port addresses...
- */
-#define KN02XA_IOASIC_BASE    (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
-#define KN02XA_RTC_BASE         (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
-
+#define KN02XA_SLOT_BASE        0x1c000000
 
 /*
  * Memory control ASIC registers.
  */
-#define KN02XA_MER      KSEG1ADDR(0x0c400000)   /* memory error register */
-#define KN02XA_MSR      KSEG1ADDR(0x0c800000)   /* memory size register */
+#define KN02XA_MER              0x0c400000      /* memory error register */
+#define KN02XA_MSR              0x0c800000      /* memory size register */
 
 /*
  * CPU control ASIC registers.
  */
-#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000)   /* write timeout config */
-#define KN02XA_EAR      KSEG1ADDR(0x0e000004)   /* error address register */
-#define KN02XA_BOOT0    KSEG1ADDR(0x0e000008)   /* boot 0 register */
-#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c)   /* write err IRQ stat & ack */
+#define KN02XA_MEM_CONF         0x0e000000      /* write timeout config */
+#define KN02XA_EAR              0x0e000004      /* error address register */
+#define KN02XA_BOOT0            0x0e000008      /* boot 0 register */
+#define KN02XA_MEM_INTR         0x0e00000c      /* write err IRQ stat & ack */
 
 /*
  * Memory Error Register bits, common definitions.
@@ -52,8 +44,13 @@
 #define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
 #define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
 #define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
-#define KN02XA_MER_RES_12       (0x3<<12)       /* unused */
-#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask */
+#define KN02XA_MER_SIZE         (1<<13)         /* r/o mirror of MSR_SIZE */
+#define KN02XA_MER_RES_12       (1<<12)         /* unused */
+#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask: */
+#define KN02XA_MER_BYTERR_3     (0x8<<8)        /* byte lane #3 */
+#define KN02XA_MER_BYTERR_2     (0x4<<8)        /* byte lane #2 */
+#define KN02XA_MER_BYTERR_1     (0x2<<8)        /* byte lane #1 */
+#define KN02XA_MER_BYTERR_0     (0x1<<8)        /* byte lane #0 */
 #define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
 
 /*
@@ -72,4 +69,17 @@
 #define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
 #define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
 
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_kn02xa_be_init(void);
+extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
+                                           struct pt_regs *regs);
+#endif
+
 #endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
index 676abd17c6a4..edede923ffb8 100644
--- a/include/asm-mips/dec/kn03.h
+++ b/include/asm-mips/dec/kn03.h
@@ -10,24 +10,15 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_DEC_KN03_H
 #define __ASM_MIPS_DEC_KN03_H
 
-#include <asm/addrspace.h>
 #include <asm/dec/ecc.h>
 #include <asm/dec/ioasic_addrs.h>
 
-#define KN03_SLOT_BASE  KSEG1ADDR(0x1f800000)
-
-/*
- * Some port addresses...
- */
-#define KN03_IOASIC_BASE        (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
-#define KN03_RTC_BASE           (KN03_SLOT_BASE + IOASIC_TOY)   /* RTC */
-#define KN03_MCR_BASE           (KN03_SLOT_BASE + IOASIC_MCR)   /* MCR */
-
+#define KN03_SLOT_BASE          0x1f800000
 
 /*
  * CPU interrupt bits.
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index b120362b8f13..15fe8f881e60 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -1,10 +1,12 @@
 /*
  *      include/asm-mips/dec/kn05.h
  *
- *      DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
+ *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
+ *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
+ *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
  *      definitions.
  *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *      Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
@@ -13,8 +15,8 @@
  *
  *      WARNING!  All this information is pure guesswork based on the
  *      ROM.  It is provided here in hope it will give someone some
- *      food for thought.  No documentation for the KN05 module has
- *      been located so far.
+ *      food for thought.  No documentation for the KN05 nor the KN04
+ *      module has been located so far.
  */
 #ifndef __ASM_MIPS_DEC_KN05_H
 #define __ASM_MIPS_DEC_KN05_H
@@ -24,48 +26,50 @@
 /*
  * The oncard MB (Memory Buffer) ASIC provides an additional address
  * decoder.  Certain address ranges within the "high" 16 slots are
- * passed to the I/O ASIC's decoder like with the KN03.  Others are
- * handled locally.  "Low" slots are always passed.
+ * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
+ * Others are handled locally.  "Low" slots are always passed.
  */
-#define KN05_MB_ROM     (16*IOASIC_SLOT_SIZE)   /* KN05 card ROM */
-#define KN05_IOCTL      (17*IOASIC_SLOT_SIZE)   /* I/O ASIC */
-#define KN05_ESAR       (18*IOASIC_SLOT_SIZE)   /* LANCE MAC address chip */
-#define KN05_LANCE      (19*IOASIC_SLOT_SIZE)   /* LANCE Ethernet */
-#define KN05_MB_INT     (20*IOASIC_SLOT_SIZE)   /* MB interrupt register */
-#define KN05_MB_EA      (21*IOASIC_SLOT_SIZE)   /* MB error address? */
-#define KN05_MB_EC      (22*IOASIC_SLOT_SIZE)   /* MB error ??? */
-#define KN05_MB_CSR     (23*IOASIC_SLOT_SIZE)   /* MB control & status */
-#define KN05_RES_24     (24*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_25     (25*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_26     (26*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_27     (27*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_SCSI       (28*IOASIC_SLOT_SIZE)   /* ASC SCSI */
-#define KN05_RES_29     (29*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_30     (30*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_31     (31*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SLOT_BASE  0x1fc00000
+
+#define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
+#define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
+#define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
+#define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
+#define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
+#define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
 
 /*
  * Bits for the MB interrupt register.
  * The register appears read-only.
  */
-#define KN05_MB_INT_TC          (1<<0)          /* TURBOchannel? */
-#define KN05_MB_INT_RTC         (1<<1)          /* RTC? */
-#define KN05_MB_INT_MT          (1<<3)          /* ??? */
+#define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
+#define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
+#define KN4K_MB_INT_MT          (1<<3)          /* ??? */
 
 /*
  * Bits for the MB control & status register.
  * Set to 0x00bf8001 on my system by the ROM.
  */
-#define KN05_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
-#define KN05_MB_CSR_F           (1<<1)          /* ??? */
-#define KN05_MB_CSR_ECC         (0xff<<2)       /* ??? */
-#define KN05_MB_CSR_OD          (1<<10)         /* ??? */
-#define KN05_MB_CSR_CP          (1<<11)         /* ??? */
-#define KN05_MB_CSR_UNC         (1<<12)         /* ??? */
-#define KN05_MB_CSR_IM          (1<<13)         /* ??? */
-#define KN05_MB_CSR_NC          (1<<14)         /* ??? */
-#define KN05_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
-#define KN05_MB_CSR_MSK         (0x1f<<16)      /* ??? */
-#define KN05_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
+#define KN4K_MB_CSR_F           (1<<1)          /* ??? */
+#define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
+#define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
+#define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
+#define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
+#define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
+#define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
+#define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* ??? */
+#define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
 
 #endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
index a05d6d3395fe..1384dd0964b9 100644
--- a/include/asm-mips/dec/prom.h
+++ b/include/asm-mips/dec/prom.h
@@ -24,7 +24,7 @@
  * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
  * Many of these will work for MIPSen as well!
  */
-#define VEC_RESET               (u64 *)KSEG1ADDR(0x1fc00000)
+#define VEC_RESET               (u64 *)CKSEG1ADDR(0x1fc00000)
                                                         /* Prom base address */
 
 #define PMAX_PROM_ENTRY(x)      (VEC_RESET + (x))       /* Prom jump table */
@@ -111,19 +111,21 @@ extern int (*__pmax_close)(int);
  * On MIPS64 we have to call PROM functions via a helper
  * dispatcher to accomodate ABI incompatibilities.
  */
-#define __DEC_PROM_O32 __attribute__((alias("call_o32")))
-
-int _rex_bootinit(int (*)(void)) __DEC_PROM_O32;
-int _rex_bootread(int (*)(void)) __DEC_PROM_O32;
-int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32;
-unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32;
-void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32;
-int _rex_getsysid(int (*)(void)) __DEC_PROM_O32;
-void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32;
-
-int _prom_getchar(int (*)(void)) __DEC_PROM_O32;
-char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32;
-int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
+#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
+                                 __asm__(#fun " = call_o32")
+
+int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
+int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
+int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
+unsigned long *__DEC_PROM_O32(_rex_slot_address,
+                             (unsigned long *(*)(int), int));
+void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
+int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
+void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
+
+int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
+char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
+int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
 
 
 #define rex_bootinit()          _rex_bootinit(__rex_bootinit)
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h
new file mode 100644
index 000000000000..78af51fbc797
--- /dev/null
+++ b/include/asm-mips/dec/system.h
@@ -0,0 +1,18 @@
+/*
+ *      include/asm-mips/dec/system.h
+ *
+ *      Generic DECstation/DECsystem bits.
+ *
+ *      Copyright (C) 2005  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_DEC_SYSTEM_H
+#define __ASM_DEC_SYSTEM_H
+
+extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
+
+#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h
index d7bba43f863a..9cb51f24d42c 100644
--- a/include/asm-mips/dec/tc.h
+++ b/include/asm-mips/dec/tc.h
@@ -7,10 +7,8 @@
  *
  * Copyright (c) 1998 Harald Koerfgen
  */
-#ifndef ASM_TC_H
-#define ASM_TC_H
-
-extern unsigned long system_base;
+#ifndef __ASM_DEC_TC_H
+#define __ASM_DEC_TC_H
 
 /*
  * Search for a TURBOchannel Option Module
@@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int);
  */
 extern unsigned long get_tc_irq_nr(int);
 /*
- * Return TURBOchannel clock frequency in hz
+ * Return TURBOchannel clock frequency in Hz
  */
 extern unsigned long get_tc_speed(void);
 
-#endif
+#endif /* __ASM_DEC_TC_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index a606dbee0412..85435a8d4e52 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -12,11 +12,9 @@
 
 #include <linux/config.h>
 #include <linux/param.h>
-
+#include <linux/smp.h>
 #include <asm/compiler.h>
 
-extern unsigned long loops_per_jiffy;
-
 static inline void __delay(unsigned long loops)
 {
         if (sizeof(long) == 4)
@@ -82,11 +80,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
         __delay(usecs);
 }
 
-#ifdef CONFIG_SMP
 #define __udelay_val cpu_data[smp_processor_id()].udelay_val
-#else
-#define __udelay_val loops_per_jiffy
-#endif
 
 #define udelay(usecs) __udelay((usecs),__udelay_val)
 
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h
index af28dc88930b..43288634c38a 100644
--- a/include/asm-mips/dma-mapping.h
+++ b/include/asm-mips/dma-mapping.h
@@ -5,13 +5,13 @@
 #include <asm/cache.h>
 
 void *dma_alloc_noncoherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, int flag);
+                           dma_addr_t *dma_handle, gfp_t flag);
 
 void dma_free_noncoherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t dma_handle);
 
 void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, int flag);
+                           dma_addr_t *dma_handle, gfp_t flag);
 
 void dma_free_coherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t dma_handle);
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h
new file mode 100644
index 000000000000..50f556bb4978
--- /dev/null
+++ b/include/asm-mips/dsp.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2005 Mips Technologies
+ * Author: Chris Dearman, chris@mips.com derived from fpu.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_DSP_H
+#define _ASM_DSP_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+#include <asm/mipsregs.h>
+
+#define DSP_DEFAULT     0x00000000
+#define DSP_MASK        0x1f
+
+#define __enable_dsp_hazard()                                           \
+do {                                                                    \
+        asm("_ehb");                                                    \
+} while (0)
+
+static inline void __init_dsp(void)
+{
+        mthi1(0);
+        mtlo1(0);
+        mthi2(0);
+        mtlo2(0);
+        mthi3(0);
+        mtlo3(0);
+        wrdsp(DSP_DEFAULT, DSP_MASK);
+}
+
+static inline void init_dsp(void)
+{
+        if (cpu_has_dsp)
+                __init_dsp();
+}
+
+#define __save_dsp(tsk)                                                 \
+do {                                                                    \
+        tsk->thread.dsp.dspr[0] = mfhi1();                              \
+        tsk->thread.dsp.dspr[1] = mflo1();                              \
+        tsk->thread.dsp.dspr[2] = mfhi2();                              \
+        tsk->thread.dsp.dspr[3] = mflo2();                              \
+        tsk->thread.dsp.dspr[4] = mfhi3();                              \
+        tsk->thread.dsp.dspr[5] = mflo3();                              \
+} while (0)
+
+#define save_dsp(tsk)                                                   \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(tsk);                                        \
+} while (0)
+
+#define __restore_dsp(tsk)                                              \
+do {                                                                    \
+        mthi1(tsk->thread.dsp.dspr[0]);                                 \
+        mtlo1(tsk->thread.dsp.dspr[1]);                                 \
+        mthi2(tsk->thread.dsp.dspr[2]);                                 \
+        mtlo2(tsk->thread.dsp.dspr[3]);                                 \
+        mthi3(tsk->thread.dsp.dspr[4]);                                 \
+        mtlo3(tsk->thread.dsp.dspr[5]);                                 \
+} while (0)
+
+#define restore_dsp(tsk)                                                \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(tsk);                                     \
+} while (0)
+
+#define __get_dsp_regs(tsk)                                             \
+({                                                                      \
+        if (tsk == current)                                             \
+                __save_dsp(current);                                    \
+                                                                        \
+        tsk->thread.dsp.dspr;                                           \
+})
+
+#endif /* _ASM_DSP_H */
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index e48811440015..7420f12742bb 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -2,6 +2,8 @@
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
+ *
+ * Much of this is taken from binutils and GNU libc ...
  */
 #ifndef _ASM_ELF_H
 #define _ASM_ELF_H
@@ -17,6 +19,8 @@
 #define EF_MIPS_ARCH_5          0x40000000      /* -mips5 code.  */
 #define EF_MIPS_ARCH_32         0x50000000      /* MIPS32 code.  */
 #define EF_MIPS_ARCH_64         0x60000000      /* MIPS64 code.  */
+#define EF_MIPS_ARCH_32R2       0x70000000      /* MIPS32 R2 code.  */
+#define EF_MIPS_ARCH_64R2       0x80000000      /* MIPS64 R2 code.  */
 
 /* The ABI of a file. */
 #define EF_MIPS_ABI_O32         0x00001000      /* O32 ABI.  */
@@ -105,7 +109,11 @@
 #define R_MIPS_LOVENDOR         100
 #define R_MIPS_HIVENDOR         127
 
-#define SHN_MIPS_ACCOMON        0xff00
+#define SHN_MIPS_ACCOMON        0xff00          /* Allocated common symbols */
+#define SHN_MIPS_TEXT           0xff01          /* Allocated test symbols.  */
+#define SHN_MIPS_DATA           0xff02          /* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON        0xff03          /* Small common symbols */
+#define SHN_MIPS_SUNDEFINED     0xff04          /* Small undefined symbols */
 
 #define SHT_MIPS_LIST           0x70000000
 #define SHT_MIPS_CONFLICT       0x70000002
@@ -193,50 +201,92 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 #ifdef __KERNEL__
 
+struct mips_abi;
+
+extern struct mips_abi mips_abi;
+extern struct mips_abi mips_abi_32;
+extern struct mips_abi mips_abi_n32;
+
 #ifdef CONFIG_32BIT
 
-#define SET_PERSONALITY(ex, ibcs2)                      \
-do {                                                    \
-        if (ibcs2)                                      \
-                set_personality(PER_SVR4);              \
-        set_personality(PER_LINUX);                     \
+#define SET_PERSONALITY(ex, ibcs2)                                      \
+do {                                                                    \
+        if (ibcs2)                                                      \
+                set_personality(PER_SVR4);                              \
+        set_personality(PER_LINUX);                                     \
+                                                                        \
+        current->thread.abi = &mips_abi;                                \
 } while (0)
 
 #endif /* CONFIG_32BIT */
 
 #ifdef CONFIG_64BIT
 
-#define SET_PERSONALITY(ex, ibcs2)                              \
-do {    current->thread.mflags &= ~MF_ABI_MASK;                 \
-        if ((ex).e_ident[EI_CLASS] == ELFCLASS32) {             \
-                if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&     \
-                     ((ex).e_flags & EF_MIPS_ABI) == 0)         \
-                        current->thread.mflags |= MF_N32;       \
-                else                                            \
-                        current->thread.mflags |= MF_O32;       \
-        } else                                                  \
-                current->thread.mflags |= MF_N64;               \
-        if (ibcs2)                                              \
-                set_personality(PER_SVR4);                      \
-        else if (current->personality != PER_LINUX32)           \
-                set_personality(PER_LINUX);                     \
+#ifdef CONFIG_MIPS32_N32
+#define __SET_PERSONALITY32_N32()                                       \
+        do {                                                            \
+                current->thread.mflags |= MF_N32;                       \
+                current->thread.abi = &mips_abi_n32;                    \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_N32()                                       \
+        do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS32_O32
+#define __SET_PERSONALITY32_O32()                                       \
+        do {                                                            \
+                current->thread.mflags |= MF_O32;                       \
+                current->thread.abi = &mips_abi_32;                     \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_O32()                                       \
+        do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS32_COMPAT
+#define __SET_PERSONALITY32(ex)                                         \
+do {                                                                    \
+        if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&                     \
+             ((ex).e_flags & EF_MIPS_ABI) == 0)                         \
+                __SET_PERSONALITY32_N32();                              \
+        else                                                            \
+                __SET_PERSONALITY32_O32();                              \
+} while (0)
+#else
+#define __SET_PERSONALITY32(ex) do { } while (0)
+#endif
+
+#define SET_PERSONALITY(ex, ibcs2)                                      \
+do {                                                                    \
+        current->thread.mflags &= ~MF_ABI_MASK;                         \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)                       \
+                __SET_PERSONALITY32(ex);                                \
+        else {                                                          \
+                current->thread.mflags |= MF_N64;                       \
+                current->thread.abi = &mips_abi;                        \
+        }                                                               \
+                                                                        \
+        if (ibcs2)                                                      \
+                set_personality(PER_SVR4);                              \
+        else if (current->personality != PER_LINUX32)                   \
+                set_personality(PER_LINUX);                             \
 } while (0)
 
 #endif /* CONFIG_64BIT */
 
 extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
+extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
 
 #define ELF_CORE_COPY_REGS(elf_regs, regs)                      \
         dump_regs((elf_greg_t *)&(elf_regs), regs);
+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
 #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs)                   \
         dump_task_fpu(tsk, elf_fpregs)
 
 #endif /* __KERNEL__ */
 
-/* This one accepts IRIX binaries.  */
-#define irix_elf_check_arch(hdr)        ((hdr)->e_flags & RHF_SGI_ONLY)
-
 #define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h
index 3c0d840e4577..9d3e6e7cdb92 100644
--- a/include/asm-mips/errno.h
+++ b/include/asm-mips/errno.h
@@ -119,6 +119,10 @@
 #define EOWNERDEAD      165     /* Owner died */
 #define ENOTRECOVERABLE 166     /* State not recoverable */
 
+/* for robust mutexes */
+#define EOWNERDEAD      165     /* Owner died */
+#define ENOTRECOVERABLE 166     /* State not recoverable */
+
 #define EDQUOT          1133    /* Quota exceeded */
 
 #ifdef __KERNEL__
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 06c5d13faf66..43d047a9a6af 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -3,11 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
  */
 #ifndef _ASM_FCNTL_H
 #define _ASM_FCNTL_H
 
+#include <linux/config.h>
+
 #define O_APPEND        0x0008
 #define O_SYNC          0x0010
 #define O_NONBLOCK      0x0080
@@ -40,13 +42,13 @@
  * contain all the same fields as struct flock.
  */
 
-#ifndef __mips64
+#ifdef CONFIG_32BIT
 
 struct flock {
         short   l_type;
         short   l_whence;
-        __kernel_off_t l_start;
-        __kernel_off_t l_len;
+        off_t   l_start;
+        off_t   l_len;
         long    l_sysid;
         __kernel_pid_t l_pid;
         long    pad[4];
@@ -54,13 +56,8 @@ struct flock {
 
 #define HAVE_ARCH_STRUCT_FLOCK
 
-#endif
+#endif /* CONFIG_32BIT */
 
 #include <asm-generic/fcntl.h>
 
-typedef struct flock flock_t;
-#ifndef __mips64
-typedef struct flock64 flock64_t;
-#endif
-
 #endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index 26b6a90a690b..73a3028dd9f9 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -107,4 +107,11 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
         return __virt_to_fix(vaddr);
 }
 
+/*
+ * Called from pgtable_init()
+ */
+extern void fixrange_init(unsigned long start, unsigned long end,
+        pgd_t *pgd_base);
+
+
 #endif
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index ea24e733b1bc..9c828b1f8218 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -80,9 +80,14 @@ do {									\
 
 #define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
 
+static inline int __is_fpu_owner(void)
+{
+        return test_thread_flag(TIF_USEDFPU);
+}
+
 static inline int is_fpu_owner(void)
 {
-        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
+        return cpu_has_fpu && __is_fpu_owner();
 }
 
 static inline void own_fpu(void)
@@ -127,7 +132,7 @@ static inline void restore_fp(struct task_struct *tsk)
 static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 {
         if (cpu_has_fpu) {
-                if ((tsk == current) && is_fpu_owner())
+                if ((tsk == current) && __is_fpu_owner())
                         _save_fp(current);
                 return tsk->thread.fpu.hard.fpr;
         }
diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h
index 46972ae2b95d..16cb4d11dd0b 100644
--- a/include/asm-mips/fpu_emulator.h
+++ b/include/asm-mips/fpu_emulator.h
@@ -23,16 +23,15 @@
 #ifndef _ASM_FPU_EMULATOR_H
 #define _ASM_FPU_EMULATOR_H
 
-struct mips_fpu_emulator_private {
-        unsigned int eir;
-        struct {
-                unsigned int emulated;
-                unsigned int loads;
-                unsigned int stores;
-                unsigned int cp1ops;
-                unsigned int cp1xops;
-                unsigned int errors;
-        } stats;
+struct mips_fpu_emulator_stats {
+        unsigned int emulated;
+        unsigned int loads;
+        unsigned int stores;
+        unsigned int cp1ops;
+        unsigned int cp1xops;
+        unsigned int errors;
 };
 
+extern struct mips_fpu_emulator_stats fpuemustats;
+
 #endif /* _ASM_FPU_EMULATOR_H */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 9feff4ce1424..2454c44a8f54 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -3,10 +3,45 @@
 
 #ifdef __KERNEL__
 
+#include <linux/config.h>
 #include <linux/futex.h>
 #include <asm/errno.h>
 #include <asm/uaccess.h>
 
+#ifdef CONFIG_SMP
+#define __FUTEX_SMP_SYNC "      sync                                    \n"
+#else
+#define __FUTEX_SMP_SYNC
+#endif
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)              \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    mips3                                   \n"     \
+        "1:     ll      %1, (%3)        # __futex_atomic_op1    \n"     \
+        "       .set    mips0                                   \n"     \
+        "       " insn  "                                       \n"     \
+        "       .set    mips3                                   \n"     \
+        "2:     sc      $1, (%3)                                \n"     \
+        "       beqzl   $1, 1b                                  \n"     \
+        __FUTEX_SMP_SYNC                                                \
+        "3:                                                     \n"     \
+        "       .set    pop                                     \n"     \
+        "       .set    mips0                                   \n"     \
+        "       .section .fixup,\"ax\"                          \n"     \
+        "4:     li      %0, %5                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section __ex_table,\"a\"                       \n"     \
+        "       "__UA_ADDR "\t1b, 4b                            \n"     \
+        "       "__UA_ADDR "\t2b, 4b                            \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (ret), "=r" (oldval)                                     \
+        : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT));           \
+}
+
 static inline int
 futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
 {
@@ -25,10 +60,25 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
 
         switch (op) {
         case FUTEX_OP_SET:
+                __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg);
+                break;
+
         case FUTEX_OP_ADD:
+                __futex_atomic_op("addu $1, %1, %z4",
+                                  ret, oldval, uaddr, oparg);
+                break;
         case FUTEX_OP_OR:
+                __futex_atomic_op("or   $1, %1, %z4",
+                                  ret, oldval, uaddr, oparg);
+                break;
         case FUTEX_OP_ANDN:
+                __futex_atomic_op("and  $1, %1, %z4",
+                                  ret, oldval, uaddr, ~oparg);
+                break;
         case FUTEX_OP_XOR:
+                __futex_atomic_op("xor  $1, %1, %z4",
+                                  ret, oldval, uaddr, oparg);
+                break;
         default:
                 ret = -ENOSYS;
         }
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index f524eaccd5f1..7517189e469f 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -74,7 +74,8 @@
 #define irq_disable_hazard
         _ehb
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+      defined(CONFIG_CPU_SB1)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -107,6 +108,7 @@ __asm__(
         "       .endm                                           \n\t");
 
 #ifdef CONFIG_CPU_RM9000
+
 /*
  * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
  * use of the JTLB for instructions should not occur for 4 cpu cycles and use
@@ -124,6 +126,9 @@ __asm__(
                 ".set\tmips32\n\t"                                      \
                 "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
                 ".set\tmips0")
+
+#define back_to_back_c0_hazard()        do { } while (0)
+
 #else
 
 /*
@@ -144,15 +149,13 @@ __asm__(
 #endif
 
 /*
- * mtc0->mfc0 hazard
- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
- * It is a MIPS32R2 processor so ehb will clear the hazard.
+ * Interrupt enable/disable hazards
+ * Some processors have hazards when modifying
+ * the status register to change the interrupt state
  */
 
 #ifdef CONFIG_CPU_MIPSR2
-/*
- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
- */
+
 __asm__(
         "       .macro\tirq_enable_hazard                       \n\t"
         "       _ehb                                            \n\t"
@@ -160,17 +163,26 @@ __asm__(
         "                                                       \n\t"
         "       .macro\tirq_disable_hazard                      \n\t"
         "       _ehb                                            \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro\tback_to_back_c0_hazard                  \n\t"
+        "       _ehb                                            \n\t"
         "       .endm");
 
 #define irq_enable_hazard()                                             \
         __asm__ __volatile__(                                           \
-        "_ehb\t\t\t\t# irq_enable_hazard")
+        "irq_enable_hazard")
 
 #define irq_disable_hazard()                                            \
         __asm__ __volatile__(                                           \
-        "_ehb\t\t\t\t# irq_disable_hazard")
+        "irq_disable_hazard")
+
+#define back_to_back_c0_hazard()                                        \
+        __asm__ __volatile__(                                           \
+        "back_to_back_c0_hazard")
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+      defined(CONFIG_CPU_SB1)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -186,6 +198,8 @@ __asm__(
 #define irq_enable_hazard()     do { } while (0)
 #define irq_disable_hazard()    do { } while (0)
 
+#define back_to_back_c0_hazard()        do { } while (0)
+
 #else
 
 /*
@@ -208,10 +222,32 @@ __asm__(
 #define irq_enable_hazard()     do { } while (0)
 #define irq_disable_hazard()                                            \
         __asm__ __volatile__(                                           \
-        "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
+        "irq_disable_hazard")
+
+#define back_to_back_c0_hazard()                                        \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                          \n"             \
+        "       nop; nop; nop                           \n"             \
+        "       .set reorder                            \n")
 
 #endif
 
+#ifdef CONFIG_CPU_MIPSR2
+#define instruction_hazard()                                            \
+do {                                                                    \
+__label__ __next;                                                       \
+        __asm__ __volatile__(                                           \
+        "       jr.hb   %0                                      \n"     \
+        :                                                               \
+        : "r" (&&__next));                                              \
+__next:                                                                 \
+        ;                                                               \
+} while (0)
+
+#else
+#define instruction_hazard() do { } while (0)
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h
index f49930d947d4..8cf598402492 100644
--- a/include/asm-mips/highmem.h
+++ b/include/asm-mips/highmem.h
@@ -75,6 +75,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
 }
 
 static inline void kunmap_atomic(void *kvaddr, enum km_type type) { }
+#define kmap_atomic_pfn(pfn, idx)       page_address(pfn_to_page(pfn))
 
 #define kmap_atomic_to_page(ptr) virt_to_page(ptr)
 
@@ -86,6 +87,7 @@ extern void *__kmap(struct page *page);
 extern void __kunmap(struct page *page);
 extern void *__kmap_atomic(struct page *page, enum km_type type);
 extern void __kunmap_atomic(void *kvaddr, enum km_type type);
+extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
 extern struct page *__kmap_atomic_to_page(void *ptr);
 
 #define kmap                    __kmap
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
index 6ad517241768..e0745f4ff624 100644
--- a/include/asm-mips/inst.h
+++ b/include/asm-mips/inst.h
@@ -28,7 +28,7 @@ enum major_op {
         sdl_op, sdr_op, swr_op, cache_op,
         ll_op, lwc1_op, lwc2_op, pref_op,
         lld_op, ldc1_op, ldc2_op, ld_op,
-        sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
+        sc_op, swc1_op, swc2_op, rdhwr_op,
         scd_op, sdc1_op, sdc2_op, sd_op
 };
 
@@ -62,10 +62,10 @@ enum rt_op {
         spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
         tgei_op, tgeiu_op, tlti_op, tltiu_op,
         teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
-        bltzal_op, bgezal_op, bltzall_op, bgezall_op
-        /*
-         * The others (0x14 - 0x1f) are unused.
-         */
+        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
+        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
+        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
+        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
 };
 
 /*
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
index e8357f5379fa..a5735761f5e5 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/interrupt.h
@@ -11,20 +11,25 @@
 #ifndef _ASM_INTERRUPT_H
 #define _ASM_INTERRUPT_H
 
+#include <linux/config.h>
 #include <asm/hazards.h>
 
 __asm__ (
-        ".macro\tlocal_irq_enable\n\t"
-        ".set\tpush\n\t"
-        ".set\treorder\n\t"
-        ".set\tnoat\n\t"
-        "mfc0\t$1,$12\n\t"
-        "ori\t$1,0x1f\n\t"
-        "xori\t$1,0x1e\n\t"
-        "mtc0\t$1,$12\n\t"
-        "irq_enable_hazard\n\t"
-        ".set\tpop\n\t"
-        ".endm");
+        "       .macro  local_irq_enable                                \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_CPU_MIPSR2
+        "       ei                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1e                                         \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_enable_hazard                                       \n"
+        "       .set    pop                                             \n"
+        "       .endm");
 
 static inline void local_irq_enable(void)
 {
@@ -43,17 +48,21 @@ static inline void local_irq_enable(void)
  * no nops at all.
  */
 __asm__ (
-        ".macro\tlocal_irq_disable\n\t"
-        ".set\tpush\n\t"
-        ".set\tnoat\n\t"
-        "mfc0\t$1,$12\n\t"
-        "ori\t$1,1\n\t"
-        "xori\t$1,1\n\t"
-        ".set\tnoreorder\n\t"
-        "mtc0\t$1,$12\n\t"
-        "irq_disable_hazard\n\t"
-        ".set\tpop\n\t"
-        ".endm");
+        "       .macro  local_irq_disable\n"
+        "       .set    push                                            \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_CPU_MIPSR2
+        "       di                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,1                                            \n"
+        "       xori    $1,1                                            \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
 
 static inline void local_irq_disable(void)
 {
@@ -65,12 +74,12 @@ static inline void local_irq_disable(void)
 }
 
 __asm__ (
-        ".macro\tlocal_save_flags flags\n\t"
-        ".set\tpush\n\t"
-        ".set\treorder\n\t"
-        "mfc0\t\\flags, $12\n\t"
-        ".set\tpop\n\t"
-        ".endm");
+        "       .macro  local_save_flags flags                          \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       mfc0    \\flags, $12                                    \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
 
 #define local_save_flags(x)                                             \
 __asm__ __volatile__(                                                   \
@@ -78,18 +87,22 @@ __asm__ __volatile__(							\
         : "=r" (x))
 
 __asm__ (
-        ".macro\tlocal_irq_save result\n\t"
-        ".set\tpush\n\t"
-        ".set\treorder\n\t"
-        ".set\tnoat\n\t"
-        "mfc0\t\\result, $12\n\t"
-        "ori\t$1, \\result, 1\n\t"
-        "xori\t$1, 1\n\t"
-        ".set\tnoreorder\n\t"
-        "mtc0\t$1, $12\n\t"
-        "irq_disable_hazard\n\t"
-        ".set\tpop\n\t"
-        ".endm");
+        "       .macro  local_irq_save result                           \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_CPU_MIPSR2
+        "       di      \\result                                        \n"
+#else
+        "       mfc0    \\result, $12                                   \n"
+        "       ori     $1, \\result, 1                                 \n"
+        "       xori    $1, 1                                           \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $12                                         \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
 
 #define local_irq_save(x)                                               \
 __asm__ __volatile__(                                                   \
@@ -99,19 +112,37 @@ __asm__ __volatile__(							\
         : "memory")
 
 __asm__ (
-        ".macro\tlocal_irq_restore flags\n\t"
-        ".set\tnoreorder\n\t"
-        ".set\tnoat\n\t"
-        "mfc0\t$1, $12\n\t"
-        "andi\t\\flags, 1\n\t"
-        "ori\t$1, 1\n\t"
-        "xori\t$1, 1\n\t"
-        "or\t\\flags, $1\n\t"
-        "mtc0\t\\flags, $12\n\t"
-        "irq_disable_hazard\n\t"
-        ".set\tat\n\t"
-        ".set\treorder\n\t"
-        ".endm");
+        "       .macro  local_irq_restore flags                         \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+        /*
+         * Slow, but doesn't suffer from a relativly unlikely race
+         * condition we're having since days 1.
+         */
+        "       beqz    \\flags, 1f                                     \n"
+        "        di                                                     \n"
+        "       ei                                                      \n"
+        "1:                                                             \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        /*
+         * Fast, dangerous.  Life is fun, life is good.
+         */
+        "       mfc0    $1, $12                                         \n"
+        "       ins     $1, \\flags, 0, 1                               \n"
+        "       mtc0    $1, $12                                         \n"
+#else
+        "       mfc0    $1, $12                                         \n"
+        "       andi    \\flags, 1                                      \n"
+        "       ori     $1, 1                                           \n"
+        "       xori    $1, 1                                           \n"
+        "       or      \\flags, $1                                     \n"
+        "       mtc0    \\flags, $12                                    \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    at                                              \n"
+        "       .set    reorder                                         \n"
+        "       .endm                                                   \n");
 
 #define local_irq_restore(flags)                                        \
 do {                                                                    \
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
index 4cd36fe98173..92d90f75a636 100644
--- a/include/asm-mips/inventory.h
+++ b/include/asm-mips/inventory.h
@@ -4,6 +4,8 @@
 #ifndef __ASM_INVENTORY_H
 #define __ASM_INVENTORY_H
 
+#include <linux/compiler.h>
+
 typedef struct inventory_s {
         struct inventory_s *inv_next;
         int    inv_class;
@@ -14,7 +16,9 @@ typedef struct inventory_s {
 } inventory_t;
 
 extern int inventory_items;
-void add_to_inventory (int class, int type, int controller, int unit, int state);
-int dump_inventory_to_user (void *userbuf, int size);
+
+extern void add_to_inventory (int class, int type, int controller, int unit, int state);
+extern int dump_inventory_to_user (void __user *userbuf, int size);
+extern int __init init_inventory(void);
 
 #endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 039845f2e6b0..3061870b7f6c 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -25,7 +25,9 @@
 #include <asm/page.h>
 #include <asm/pgtable-bits.h>
 #include <asm/processor.h>
+#include <asm/string.h>
 
+#include <ioremap.h>
 #include <mangle-port.h>
 
 /*
@@ -34,7 +36,7 @@
 #undef CONF_SLOWDOWN_IO
 
 /*
- * Raw operations are never swapped in software.  Otoh values that raw
+ * Raw operations are never swapped in software.  OTOH values that raw
  * operations are working on may or may not have been swapped by the bus
  * hardware.  An example use would be for flash memory that's used for
  * execute in place.
@@ -43,45 +45,53 @@
 # define __raw_ioswabw(x)       (x)
 # define __raw_ioswabl(x)       (x)
 # define __raw_ioswabq(x)       (x)
+# define ____raw_ioswabq(x)     (x)
 
 /*
  * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
  * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "mem_" prefix.
  */
 #if defined(CONFIG_SWAP_IO_SPACE)
 
 # define ioswabb(x)             (x)
+# define mem_ioswabb(x)         (x)
 # ifdef CONFIG_SGI_IP22
 /*
  * IP22 seems braindead enough to swap 16bits values in hardware, but
  * not 32bits.  Go figure... Can't tell without documentation.
  */
 #  define ioswabw(x)            (x)
+#  define mem_ioswabw(x)        le16_to_cpu(x)
 # else
 #  define ioswabw(x)            le16_to_cpu(x)
+#  define mem_ioswabw(x)        (x)
 # endif
 # define ioswabl(x)             le32_to_cpu(x)
+# define mem_ioswabl(x)         (x)
 # define ioswabq(x)             le64_to_cpu(x)
+# define mem_ioswabq(x)         (x)
 
 #else
 
 # define ioswabb(x)             (x)
+# define mem_ioswabb(x)         (x)
 # define ioswabw(x)             (x)
+# define mem_ioswabw(x)         cpu_to_le16(x)
 # define ioswabl(x)             (x)
+# define mem_ioswabl(x)         cpu_to_le32(x)
 # define ioswabq(x)             (x)
+# define mem_ioswabq(x)         cpu_to_le32(x)
 
 #endif
 
-/*
- * Native bus accesses never swapped.
- */
-#define bus_ioswabb(x)          (x)
-#define bus_ioswabw(x)          (x)
-#define bus_ioswabl(x)          (x)
-#define bus_ioswabq(x)          (x)
-
-#define __bus_ioswabq           bus_ioswabq
-
 #define IO_SPACE_LIMIT 0xffff
 
 /*
@@ -194,12 +204,14 @@ extern unsigned long isa_slot_offset;
  */
 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 
-extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
+extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
 extern void __iounmap(volatile void __iomem *addr);
 
-static inline void * __ioremap_mode(phys_t offset, unsigned long size,
+static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
         unsigned long flags)
 {
+#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
+
         if (cpu_has_64bit_addresses) {
                 u64 base = UNCAC_BASE;
 
@@ -209,10 +221,30 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size,
                  */
                 if (flags == _CACHE_UNCACHED)
                         base = (u64) IO_BASE;
-                return (void *) (unsigned long) (base + offset);
+                return (void __iomem *) (unsigned long) (base + offset);
+        } else if (__builtin_constant_p(offset) &&
+                   __builtin_constant_p(size) && __builtin_constant_p(flags)) {
+                phys_t phys_addr, last_addr;
+
+                phys_addr = fixup_bigphys_addr(offset, size);
+
+                /* Don't allow wraparound or zero size. */
+                last_addr = phys_addr + size - 1;
+                if (!size || last_addr < phys_addr)
+                        return NULL;
+
+                /*
+                 * Map uncached objects in the low 512MB of address
+                 * space using KSEG1.
+                 */
+                if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
+                    flags == _CACHE_UNCACHED)
+                        return (void __iomem *)CKSEG1ADDR(phys_addr);
         }
 
         return __ioremap(offset, size, flags);
+
+#undef __IS_LOW512
 }
 
 /*
@@ -264,12 +296,16 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size,
 
 static inline void iounmap(volatile void __iomem *addr)
 {
-        if (cpu_has_64bit_addresses)
+#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
+
+        if (cpu_has_64bit_addresses ||
+            (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
                 return;
 
         __iounmap(addr);
-}
 
+#undef __IS_KSEG1
+}
 
 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
                                                                         \
@@ -319,7 +355,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem)		\
         else if (cpu_has_64bits) {                                      \
                 unsigned long __flags;                                  \
                                                                         \
-                local_irq_save(__flags);                                \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
                 __asm__ __volatile__(                                   \
                         ".set   mips3"          "\t\t# __readq" "\n\t"  \
                         "ld     %L0, %1"                        "\n\t"  \
@@ -328,7 +365,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem)		\
                         ".set   mips0"                          "\n"    \
                         : "=r" (__val)                                  \
                         : "m" (*__mem));                                \
-                local_irq_restore(__flags);                             \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
         } else {                                                        \
                 __val = 0;                                              \
                 BUG();                                                  \
@@ -349,11 +387,11 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
                                                                         \
         __val = pfx##ioswab##bwlq(val);                                 \
                                                                         \
-        if (sizeof(type) != sizeof(u64)) {                              \
-                *__addr = __val;                                        \
-                slow;                                                   \
-        } else                                                          \
-                BUILD_BUG();                                            \
+        /* Really, we want this to be atomic */                         \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
+                                                                        \
+        *__addr = __val;                                                \
+        slow;                                                           \
 }                                                                       \
                                                                         \
 static inline type pfx##in##bwlq##p(unsigned long port)                 \
@@ -364,13 +402,10 @@ static inline type pfx##in##bwlq##p(unsigned long port)			\
         port = __swizzle_addr_##bwlq(port);                             \
         __addr = (void *)(mips_io_port_base + port);                    \
                                                                         \
-        if (sizeof(type) != sizeof(u64)) {                              \
-                __val = *__addr;                                        \
-                slow;                                                   \
-        } else {                                                        \
-                __val = 0;                                              \
-                BUILD_BUG();                                            \
-        }                                                               \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
+                                                                        \
+        __val = *__addr;                                                \
+        slow;                                                           \
                                                                         \
         return pfx##ioswab##bwlq(__val);                                \
 }
@@ -379,27 +414,35 @@ static inline type pfx##in##bwlq##p(unsigned long port)			\
                                                                         \
 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
 
-#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
-                                                                        \
-__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                               \
-__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
-
-#define BUILDIO(bwlq, type)                                             \
+#define BUILDIO_MEM(bwlq, type)                                         \
                                                                         \
-__BUILD_MEMORY_PFX(, bwlq, type)                                        \
 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
-__BUILD_MEMORY_PFX(bus_, bwlq, type)                                    \
-__BUILD_IOPORT_PFX(, bwlq, type)                                        \
-__BUILD_IOPORT_PFX(__raw_, bwlq, type)
+__BUILD_MEMORY_PFX(, bwlq, type)                                        \
+__BUILD_MEMORY_PFX(mem_, bwlq, type)                                    \
+
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+
+#define BUILDIO_IOPORT(bwlq, type)                                      \
+        __BUILD_IOPORT_PFX(, bwlq, type)                                \
+        __BUILD_IOPORT_PFX(mem_, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
 
 #define __BUILDIO(bwlq, type)                                           \
                                                                         \
-__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0)
-
-BUILDIO(b, u8)
-BUILDIO(w, u16)
-BUILDIO(l, u32)
-BUILDIO(q, u64)
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
 
 __BUILDIO(q, u64)
 
@@ -422,7 +465,7 @@ static inline void writes##bwlq(volatile void __iomem *mem, void *addr,	\
         volatile type *__addr = addr;                                   \
                                                                         \
         while (count--) {                                               \
-                __raw_write##bwlq(*__addr, mem);                        \
+                mem_write##bwlq(*__addr, mem);                          \
                 __addr++;                                               \
         }                                                               \
 }                                                                       \
@@ -433,20 +476,20 @@ static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
         volatile type *__addr = addr;                                   \
                                                                         \
         while (count--) {                                               \
-                *__addr = __raw_read##bwlq(mem);                        \
+                *__addr = mem_read##bwlq(mem);                          \
                 __addr++;                                               \
         }                                                               \
 }
 
 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
                                                                         \
-static inline void outs##bwlq(unsigned long port, void *addr,           \
+static inline void outs##bwlq(unsigned long port, const void *addr,     \
                               unsigned int count)                       \
 {                                                                       \
-        volatile type *__addr = addr;                                   \
+        const volatile type *__addr = addr;                             \
                                                                         \
         while (count--) {                                               \
-                __raw_out##bwlq(*__addr, port);                         \
+                mem_out##bwlq(*__addr, port);                           \
                 __addr++;                                               \
         }                                                               \
 }                                                                       \
@@ -457,7 +500,7 @@ static inline void ins##bwlq(unsigned long port, void *addr,		\
         volatile type *__addr = addr;                                   \
                                                                         \
         while (count--) {                                               \
-                *__addr = __raw_in##bwlq(port);                         \
+                *__addr = mem_in##bwlq(port);                           \
                 __addr++;                                               \
         }                                                               \
 }
@@ -470,15 +513,26 @@ __BUILD_IOPORT_STRING(bwlq, type)
 BUILDSTRING(b, u8)
 BUILDSTRING(w, u16)
 BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
 BUILDSTRING(q, u64)
+#endif
 
 
 /* Depends on MIPS II instruction set */
 #define mmiowb() asm volatile ("sync" ::: "memory")
 
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+        memset((void __force *) addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+        memcpy(dst, (void __force *) src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+        memcpy((void __force *) dst, src, count);
+}
 
 /*
  * Memory Mapped I/O
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 3f2470e9e678..8a342ccb34a8 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,11 +24,9 @@ static inline int irq_canonicalize(int irq)
 
 struct pt_regs;
 
-#ifdef CONFIG_PREEMPT
-
 extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
 
-#else
+#ifdef CONFIG_PREEMPT
 
 /*
  * do_IRQ handles all normal device IRQ's (the special
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 86df317b4078..baf412967afa 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -202,20 +202,6 @@ static inline int jmr3927_have_isac(void)
 #endif /* !__ASSEMBLY__ */
 
 /*
- * UART defines for serial.h
- */
-
-/* use Pre-scaler T0 (1/2) */
-#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
-
-#define UART0_ADDR   0xfffef300
-#define UART1_ADDR   0xfffef400
-#define UART0_INT    JMR3927_IRQ_IRC_SIO0
-#define UART1_INT    JMR3927_IRQ_IRC_SIO1
-#define UART0_FLAGS  ASYNC_BOOT_AUTOCONF
-#define UART1_FLAGS  0
-
-/*
  * IRQ mappings
  */
 
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..8327ec341c18 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -60,59 +60,36 @@ void static inline au_sync_delay(int ms)
         mdelay(ms);
 }
 
-void static inline au_writeb(u8 val, int reg)
+void static inline au_writeb(u8 val, unsigned long reg)
 {
         *(volatile u8 *)(reg) = val;
 }
 
-void static inline au_writew(u16 val, int reg)
+void static inline au_writew(u16 val, unsigned long reg)
 {
         *(volatile u16 *)(reg) = val;
 }
 
-void static inline au_writel(u32 val, int reg)
+void static inline au_writel(u32 val, unsigned long reg)
 {
         *(volatile u32 *)(reg) = val;
 }
 
-static inline u8 au_readb(unsigned long port)
+static inline u8 au_readb(unsigned long reg)
 {
-        return (*(volatile u8 *)port);
+        return (*(volatile u8 *)reg);
 }
 
-static inline u16 au_readw(unsigned long port)
+static inline u16 au_readw(unsigned long reg)
 {
-        return (*(volatile u16 *)port);
+        return (*(volatile u16 *)reg);
 }
 
-static inline u32 au_readl(unsigned long port)
+static inline u32 au_readl(unsigned long reg)
 {
-        return (*(volatile u32 *)port);
+        return (*(volatile u32 *)reg);
 }
 
-/* These next three functions should be a generic part of the MIPS
- * kernel (with the 'au_' removed from the name) and selected for
- * processors that support the instructions.
- * Taken from PPC tree.  -- Dan
- */
-/* Return the bit position of the most significant 1 bit in a word */
-static __inline__ int __ilog2(unsigned int x)
-{
-        int lz;
-
-        asm volatile (
-                ".set\tnoreorder\n\t"
-                ".set\tnoat\n\t"
-                ".set\tmips32\n\t"
-                "clz\t%0,%1\n\t"
-                ".set\tmips0\n\t"
-                ".set\tat\n\t"
-                ".set\treorder"
-                : "=r" (lz)
-                : "r" (x));
-
-        return 31 - lz;
-}
 
 static __inline__ int au_ffz(unsigned int x)
 {
@@ -162,28 +139,293 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
 
-/* SDRAM Controller */
+/*
+ * SDRAM Register Offsets
+ */
 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0                0xB4000000
-#define MEM_SDMODE1                0xB4000004
-#define MEM_SDMODE2                0xB4000008
+#define MEM_SDMODE0             (0x0000)
+#define MEM_SDMODE1             (0x0004)
+#define MEM_SDMODE2             (0x0008)
+#define MEM_SDADDR0             (0x000C)
+#define MEM_SDADDR1             (0x0010)
+#define MEM_SDADDR2             (0x0014)
+#define MEM_SDREFCFG    (0x0018)
+#define MEM_SDPRECMD    (0x001C)
+#define MEM_SDAUTOREF   (0x0020)
+#define MEM_SDWRMD0             (0x0024)
+#define MEM_SDWRMD1             (0x0028)
+#define MEM_SDWRMD2             (0x002C)
+#define MEM_SDSLEEP             (0x0030)
+#define MEM_SDSMCKE             (0x0034)
 
-#define MEM_SDADDR0                0xB400000C
-#define MEM_SDADDR1                0xB4000010
-#define MEM_SDADDR2                0xB4000014
+/*
+ * MEM_SDMODE register content definitions
+ */
+#define MEM_SDMODE_F            (1<<22)
+#define MEM_SDMODE_SR           (1<<21)
+#define MEM_SDMODE_BS           (1<<20)
+#define MEM_SDMODE_RS           (3<<18)
+#define MEM_SDMODE_CS           (7<<15)
+#define MEM_SDMODE_TRAS         (15<<11)
+#define MEM_SDMODE_TMRD         (3<<9)
+#define MEM_SDMODE_TWR          (3<<7)
+#define MEM_SDMODE_TRP          (3<<5)
+#define MEM_SDMODE_TRCD         (3<<3)
+#define MEM_SDMODE_TCL          (7<<0)
+
+#define MEM_SDMODE_BS_2Bank     (0<<20)
+#define MEM_SDMODE_BS_4Bank     (1<<20)
+#define MEM_SDMODE_RS_11Row     (0<<18)
+#define MEM_SDMODE_RS_12Row     (1<<18)
+#define MEM_SDMODE_RS_13Row     (2<<18)
+#define MEM_SDMODE_RS_N(N)      ((N)<<18)
+#define MEM_SDMODE_CS_7Col      (0<<15)
+#define MEM_SDMODE_CS_8Col      (1<<15)
+#define MEM_SDMODE_CS_9Col      (2<<15)
+#define MEM_SDMODE_CS_10Col     (3<<15)
+#define MEM_SDMODE_CS_11Col     (4<<15)
+#define MEM_SDMODE_CS_N(N)              ((N)<<15)
+#define MEM_SDMODE_TRAS_N(N)    ((N)<<11)
+#define MEM_SDMODE_TMRD_N(N)    ((N)<<9)
+#define MEM_SDMODE_TWR_N(N)             ((N)<<7)
+#define MEM_SDMODE_TRP_N(N)             ((N)<<5)
+#define MEM_SDMODE_TRCD_N(N)    ((N)<<3)
+#define MEM_SDMODE_TCL_N(N)             ((N)<<0)
 
-#define MEM_SDREFCFG               0xB4000018
-#define MEM_SDPRECMD               0xB400001C
-#define MEM_SDAUTOREF              0xB4000020
+/*
+ * MEM_SDADDR register contents definitions
+ */
+#define MEM_SDADDR_E                    (1<<20)
+#define MEM_SDADDR_CSBA                 (0x03FF<<10)
+#define MEM_SDADDR_CSMASK               (0x03FF<<0)
+#define MEM_SDADDR_CSBA_N(N)    ((N)&(0x03FF<<22)>>12)
+#define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF<<22)>>22)
+
+/*
+ * MEM_SDREFCFG register content definitions
+ */
+#define MEM_SDREFCFG_TRC                (15<<28)
+#define MEM_SDREFCFG_TRPM               (3<<26)
+#define MEM_SDREFCFG_E                  (1<<25)
+#define MEM_SDREFCFG_RE                 (0x1ffffff<<0)
+#define MEM_SDREFCFG_TRC_N(N)   ((N)<<MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N)  ((N)<<MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)   (N)
+#endif
 
-#define MEM_SDWRMD0                0xB4000024
-#define MEM_SDWRMD1                0xB4000028
-#define MEM_SDWRMD2                0xB400002C
+/***********************************************************************/
 
-#define MEM_SDSLEEP                0xB4000030
-#define MEM_SDSMCKE                0xB4000034
+/*
+ * Au1550 SDRAM Register Offsets
+ */
+
+/***********************************************************************/
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0             (0x0800)
+#define MEM_SDMODE1             (0x0808)
+#define MEM_SDMODE2             (0x0810)
+#define MEM_SDADDR0             (0x0820)
+#define MEM_SDADDR1             (0x0828)
+#define MEM_SDADDR2             (0x0830)
+#define MEM_SDCONFIGA   (0x0840)
+#define MEM_SDCONFIGB   (0x0848)
+#define MEM_SDSTAT              (0x0850)
+#define MEM_SDERRADDR   (0x0858)
+#define MEM_SDSTRIDE0   (0x0860)
+#define MEM_SDSTRIDE1   (0x0868)
+#define MEM_SDSTRIDE2   (0x0870)
+#define MEM_SDWRMD0             (0x0880)
+#define MEM_SDWRMD1             (0x0888)
+#define MEM_SDWRMD2             (0x0890)
+#define MEM_SDPRECMD    (0x08C0)
+#define MEM_SDAUTOREF   (0x08C8)
+#define MEM_SDSREF              (0x08D0)
+#define MEM_SDSLEEP             MEM_SDSREF
+
+#endif
+
+/*
+ * Physical base addresses for integrated peripherals
+ */
+
+#ifdef CONFIG_SOC_AU1000
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART2_PHYS_ADDR         0x11300000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
 #endif
 
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1500
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x11500000
+#define MAC1_PHYS_ADDR          0x11510000
+#define MACEN_PHYS_ADDR         0x11520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCI_MEM_PHYS_ADDR     0x400000000ULL
+#define PCI_IO_PHYS_ADDR      0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1100
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define LCD_PHYS_ADDR           0x15000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1550
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBH_PHYS_ADDR          0x14020000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PE_PHYS_ADDR            0x14008000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define PSC2_PHYS_ADDR          0x10A00000
+#define PSC3_PHYS_ADDR          0x10B00000
+#define PCI_MEM_PHYS_ADDR     0x400000000ULL
+#define PCI_IO_PHYS_ADDR      0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1200
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR           0x10300000
+#define CIM_PHYS_ADDR           0x14004000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBM_PHYS_ADDR          0x14020000
+#define USBH_PHYS_ADDR          0x14020100
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define LCD_PHYS_ADDR           0x15000000
+#define SWCNT_PHYS_ADDR         0x1110010C
+#define MAEFE_PHYS_ADDR         0x14012000
+#define MAEBE_PHYS_ADDR         0x14010000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+
+
 /* Static Bus Controller */
 #define MEM_STCFG0                 0xB4001000
 #define MEM_STTIME0                0xB4001004
@@ -369,7 +611,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_MAC0_ENABLE       0xB0520000
 #define AU1000_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1000
+#endif /* CONFIG_SOC_AU1000 */
 
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
@@ -429,6 +671,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_GPIO_207           62
 #define AU1500_GPIO_208_215       63
 
+/* shortcuts */
+#define INTA AU1000_PCI_INTA
+#define INTB AU1000_PCI_INTB
+#define INTC AU1000_PCI_INTC
+#define INTD AU1000_PCI_INTD
+
 #define UART0_ADDR                0xB1100000
 #define UART3_ADDR                0xB1400000
 
@@ -440,7 +688,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1500
+#endif /* CONFIG_SOC_AU1500 */
 
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
@@ -485,6 +733,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_GPIO_13            45
 #define AU1000_GPIO_14            46
 #define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
 
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
@@ -496,7 +760,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1100_ETH0_BASE          0xB0500000
 #define AU1100_MAC0_ENABLE       0xB0520000
 #define NUM_ETH_INTERFACES 1
-#endif // CONFIG_SOC_AU1100
+#endif /* CONFIG_SOC_AU1100 */
 
 #ifdef CONFIG_SOC_AU1550
 #define AU1550_UART0_INT          0
@@ -513,14 +777,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_PSC1_INT           11
 #define AU1550_PSC2_INT           12
 #define AU1550_PSC3_INT           13
-#define AU1550_TOY_INT                    14
-#define AU1550_TOY_MATCH0_INT     15
-#define AU1550_TOY_MATCH1_INT     16
-#define AU1550_TOY_MATCH2_INT     17
-#define AU1550_RTC_INT            18
-#define AU1550_RTC_MATCH0_INT     19
-#define AU1550_RTC_MATCH1_INT     20
-#define AU1550_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                    14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1550_NAND_INT           23
 #define AU1550_USB_DEV_REQ_INT    24
 #define AU1550_USB_DEV_SUS_INT    25
@@ -563,6 +827,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_GPIO_207           62
 #define AU1500_GPIO_208_218       63    // Logical or of GPIO208:218
 
+/* shortcuts */
+#define INTA AU1550_PCI_INTA
+#define INTB AU1550_PCI_INTB
+#define INTC AU1550_PCI_INTC
+#define INTD AU1550_PCI_INTD
+
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
 #define UART3_ADDR                0xB1400000
@@ -575,7 +845,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_MAC0_ENABLE       0xB0520000
 #define AU1550_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1550
+#endif /* CONFIG_SOC_AU1550 */
 
 #ifdef CONFIG_SOC_AU1200
 #define AU1200_UART0_INT          0
@@ -592,14 +862,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1200_PSC1_INT           11
 #define AU1200_AES_INT            12
 #define AU1200_CAMERA_INT         13
-#define AU1200_TOY_INT                    14
-#define AU1200_TOY_MATCH0_INT     15
-#define AU1200_TOY_MATCH1_INT     16
-#define AU1200_TOY_MATCH2_INT     17
-#define AU1200_RTC_INT            18
-#define AU1200_RTC_MATCH0_INT     19
-#define AU1200_RTC_MATCH1_INT     20
-#define AU1200_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                    14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1200_NAND_INT           23
 #define AU1200_GPIO_204           24
 #define AU1200_GPIO_205           25
@@ -607,6 +877,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1200_GPIO_207           27
 #define AU1200_GPIO_208_215       28 // Logical OR of 208:215
 #define AU1200_USB_INT            29
+#define AU1000_USB_HOST_INT               AU1200_USB_INT
 #define AU1200_LCD_INT            30
 #define AU1200_MAE_BOTH_INT       31
 #define AU1000_GPIO_0             32
@@ -645,20 +916,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
 
-#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
-#define USB_HOST_CONFIG           0xB4027ffc
-
-// these are here for prototyping on au1550 (do not exist on au1200)
-#define AU1200_ETH0_BASE      0xB0500000
-#define AU1200_ETH1_BASE      0xB0510000
-#define AU1200_MAC0_ENABLE       0xB0520000
-#define AU1200_MAC1_ENABLE       0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1200
+#define USB_UOC_BASE              0x14020020
+#define USB_UOC_LEN               0x20
+#define USB_OHCI_BASE             0x14020100
+#define USB_OHCI_LEN              0x100
+#define USB_EHCI_BASE             0x14020200
+#define USB_EHCI_LEN              0x100
+#define USB_UDC_BASE              0x14022000
+#define USB_UDC_LEN               0x2000
+#define USB_MSR_BASE                      0xB4020000
+#define USB_MSR_MCFG              4
+#define USBMSRMCFG_OMEMEN         0
+#define USBMSRMCFG_OBMEN          1
+#define USBMSRMCFG_EMEMEN         2
+#define USBMSRMCFG_EBMEN          3
+#define USBMSRMCFG_DMEMEN         4
+#define USBMSRMCFG_DBMEN          5
+#define USBMSRMCFG_GMEMEN         6
+#define USBMSRMCFG_OHCCLKEN       16
+#define USBMSRMCFG_EHCCLKEN       17
+#define USBMSRMCFG_UDCCLKEN       18
+#define USBMSRMCFG_PHYPLLEN       19
+#define USBMSRMCFG_RDCOMB         30
+#define USBMSRMCFG_PFEN           31
+
+#endif /* CONFIG_SOC_AU1200 */
 
 #define AU1000_LAST_INTC0_INT     31
+#define AU1000_LAST_INTC1_INT     63
 #define AU1000_MAX_INTR           63
-
+#define INTX                    0xFF /* not valid */
 
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                   0xB1900000
@@ -730,6 +1017,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define I2S_CONTROL_D         (1<<1)
   #define I2S_CONTROL_CE        (1<<0)
 
+#ifndef CONFIG_SOC_AU1200
+
 /* USB Host Controller */
 #define USB_OHCI_LEN              0x00100000
 
@@ -775,6 +1064,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define USBDEV_ENABLE (1<<1)
   #define USBDEV_CE     (1<<0)
 
+#endif /* !CONFIG_SOC_AU1200 */
+
 /* Ethernet Controllers  */
 
 /* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1464,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define SYS_PF_PSC1_S1                (1 << 1)
   #define SYS_PF_MUST_BE_SET            ((1 << 5) | (1 << 2))
 
+/* Au1200 Only */
+#ifdef CONFIG_SOC_AU1200
+#define SYS_PINFUNC_DMA         (1<<31)
+#define SYS_PINFUNC_S0A         (1<<30)
+#define SYS_PINFUNC_S1A         (1<<29)
+#define SYS_PINFUNC_LP0         (1<<28)
+#define SYS_PINFUNC_LP1         (1<<27)
+#define SYS_PINFUNC_LD16        (1<<26)
+#define SYS_PINFUNC_LD8         (1<<25)
+#define SYS_PINFUNC_LD1         (1<<24)
+#define SYS_PINFUNC_LD0         (1<<23)
+#define SYS_PINFUNC_P1A         (3<<21)
+#define SYS_PINFUNC_P1B         (1<<20)
+#define SYS_PINFUNC_FS3         (1<<19)
+#define SYS_PINFUNC_P0A         (3<<17)
+#define SYS_PINFUNC_CS          (1<<16)
+#define SYS_PINFUNC_CIM         (1<<15)
+#define SYS_PINFUNC_P1C         (1<<14)
+#define SYS_PINFUNC_U1T         (1<<12)
+#define SYS_PINFUNC_U1R         (1<<11)
+#define SYS_PINFUNC_EX1         (1<<10)
+#define SYS_PINFUNC_EX0         (1<<9)
+#define SYS_PINFUNC_U0R         (1<<8)
+#define SYS_PINFUNC_MC          (1<<7)
+#define SYS_PINFUNC_S0B         (1<<6)
+#define SYS_PINFUNC_S0C         (1<<5)
+#define SYS_PINFUNC_P0B         (1<<4)
+#define SYS_PINFUNC_U0T         (1<<3)
+#define SYS_PINFUNC_S1B         (1<<2)
+#endif
+
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -1239,6 +1561,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define SYS_CS_MI2_MASK           (0x7<<SYS_CS_MI2_BIT)
   #define SYS_CS_DI2                (1<<16)
   #define SYS_CS_CI2                (1<<15)
+#ifdef CONFIG_SOC_AU1100
+  #define SYS_CS_ML_BIT             7
+  #define SYS_CS_ML_MASK            (0x7<<SYS_CS_ML_BIT)
+  #define SYS_CS_DL                 (1<<6)
+  #define SYS_CS_CL                 (1<<5)
+#else
   #define SYS_CS_MUH_BIT            12
   #define SYS_CS_MUH_MASK           (0x7<<SYS_CS_MUH_BIT)
   #define SYS_CS_DUH                (1<<11)
@@ -1247,6 +1575,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define SYS_CS_MUD_MASK           (0x7<<SYS_CS_MUD_BIT)
   #define SYS_CS_DUD                (1<<6)
   #define SYS_CS_CUD                (1<<5)
+#endif
   #define SYS_CS_MIR_BIT            2
   #define SYS_CS_MIR_MASK           (0x7<<SYS_CS_MIR_BIT)
   #define SYS_CS_DIR                (1<<1)
@@ -1300,7 +1629,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define SD1_XMIT_FIFO   0xB0680000
 #define SD1_RECV_FIFO   0xB0680004
 
-
 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1691,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
                       _ctl_; })
 
 
-#else /* Au1000 and Au1100 */
+#else /* Au1000 and Au1100 and Au1200 */
 
 /* don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START 0x10000000;
+#define IOPORT_RESOURCE_START 0x10000000
 #define IOPORT_RESOURCE_END   0xffffffff
 #define IOMEM_RESOURCE_START  0x10000000
 #define IOMEM_RESOURCE_END    0xffffffff
 
-#ifdef CONFIG_MIPS_PB1000
-#define PCI_IO_START      0x10000000
-#define PCI_IO_END        0x1000ffff
-#define PCI_MEM_START     0x18000000
-#define PCI_MEM_END       0x18ffffff
-#define PCI_FIRST_DEVFN   0
-#define PCI_LAST_DEVFN    1
-#else
-/* no PCI bus controller */
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
 #define PCI_MEM_END     0
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
-#endif
 
 #endif
 
+#ifndef _LANGUAGE_ASSEMBLY
+typedef volatile struct
+{
+        /* 0x0000 */ u32 toytrim;
+        /* 0x0004 */ u32 toywrite;
+        /* 0x0008 */ u32 toymatch0;
+        /* 0x000C */ u32 toymatch1;
+        /* 0x0010 */ u32 toymatch2;
+        /* 0x0014 */ u32 cntrctrl;
+        /* 0x0018 */ u32 scratch0;
+        /* 0x001C */ u32 scratch1;
+        /* 0x0020 */ u32 freqctrl0;
+        /* 0x0024 */ u32 freqctrl1;
+        /* 0x0028 */ u32 clksrc;
+        /* 0x002C */ u32 pinfunc;
+        /* 0x0030 */ u32 reserved0;
+        /* 0x0034 */ u32 wakemsk;
+        /* 0x0038 */ u32 endian;
+        /* 0x003C */ u32 powerctrl;
+        /* 0x0040 */ u32 toyread;
+        /* 0x0044 */ u32 rtctrim;
+        /* 0x0048 */ u32 rtcwrite;
+        /* 0x004C */ u32 rtcmatch0;
+        /* 0x0050 */ u32 rtcmatch1;
+        /* 0x0054 */ u32 rtcmatch2;
+        /* 0x0058 */ u32 rtcread;
+        /* 0x005C */ u32 wakesrc;
+        /* 0x0060 */ u32 cpupll;
+        /* 0x0064 */ u32 auxpll;
+        /* 0x0068 */ u32 reserved1;
+        /* 0x006C */ u32 reserved2;
+        /* 0x0070 */ u32 reserved3;
+        /* 0x0074 */ u32 reserved4;
+        /* 0x0078 */ u32 slppwr;
+        /* 0x007C */ u32 sleep;
+        /* 0x0080 */ u32 reserved5[32];
+        /* 0x0100 */ u32 trioutrd;
+#define trioutclr trioutrd
+        /* 0x0104 */ u32 reserved6;
+        /* 0x0108 */ u32 outputrd;
+#define outputset outputrd
+        /* 0x010C */ u32 outputclr;
+        /* 0x0110 */ u32 pinstaterd;
+#define pininputen pinstaterd
+
+} AU1X00_SYS;
+
+static AU1X00_SYS* const sys  = (AU1X00_SYS *)SYS_BASE;
+
+#endif
 /* Processor information base on prid.
  * Copied from PowerPC.
  */
+#ifndef _LANGUAGE_ASSEMBLY
 struct cpu_spec {
         /* CPU is matched via (PRID & prid_mask) == prid_value */
         unsigned int    prid_mask;
@@ -1406,3 +1775,6 @@ struct cpu_spec {
 extern struct cpu_spec          cpu_specs[];
 extern struct cpu_spec          *cur_cpu_spec[];
 #endif
+
+#endif
+
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
new file mode 100644
index 000000000000..b7b46dd9b929
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx.h
@@ -0,0 +1,44 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AU1XXX_H_
+#define _AU1XXX_H_
+
+#include <linux/config.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
+#include <asm/mach-db1x00/db1x00.h>
+
+#elif defined(CONFIG_MIPS_PB1550)
+#include <asm/mach-pb1x00/pb1550.h>
+
+#elif defined(CONFIG_MIPS_PB1200)
+#include <asm/mach-pb1x00/pb1200.h>
+
+#elif defined(CONFIG_MIPS_DB1200)
+#include <asm/mach-db1x00/db1200.h>
+
+#endif
+
+#endif /* _AU1XXX_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5eb88cd7d51..b327bcd3fee1 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -45,7 +45,7 @@
 #define DDMA_GLOBAL_BASE        0xb4003000
 #define DDMA_CHANNEL_BASE       0xb4002000
 
-typedef struct dbdma_global {
+typedef volatile struct dbdma_global {
         u32     ddma_config;
         u32     ddma_intstat;
         u32     ddma_throttle;
@@ -62,7 +62,7 @@ typedef struct dbdma_global {
 
 /* The structure of a DMA Channel.
 */
-typedef struct au1xxx_dma_channel {
+typedef volatile struct au1xxx_dma_channel {
         u32     ddma_cfg;       /* See below */
         u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
         u32     ddma_statptr;   /* word aligned pointer to status word */
@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
 /* "Standard" DDMA Descriptor.
  * Must be 32-byte aligned.
  */
-typedef struct au1xxx_ddma_desc {
+typedef volatile struct au1xxx_ddma_desc {
         u32     dscr_cmd0;              /* See below */
         u32     dscr_cmd1;              /* See below */
         u32     dscr_source0;           /* source phys address */
@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
         u32     dscr_dest1;             /* See below */
         u32     dscr_stat;              /* completion status */
         u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+        /* First 32bytes are HW specific!!!
+           Lets have some SW data following.. make sure its 32bytes
+         */
+        u32     sw_status;
+        u32     sw_context;
+        u32     sw_reserved[6];
 } au1x_ddma_desc_t;
 
 #define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
 #define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
 #define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
 
+#define SW_STATUS_INUSE         (1<<0)
+
 /* Command 0 device IDs.
 */
+#ifdef CONFIG_SOC_AU1550
 #define DSCR_CMD0_UART0_TX      0
 #define DSCR_CMD0_UART0_RX      1
 #define DSCR_CMD0_UART3_TX      2
@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
 #define DSCR_CMD0_MAC0_TX       25
 #define DSCR_CMD0_MAC1_RX       26
 #define DSCR_CMD0_MAC1_TX       27
+#endif /* CONFIG_SOC_AU1550 */
+
+#ifdef CONFIG_SOC_AU1200
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART1_TX      2
+#define DSCR_CMD0_UART1_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_MAE_BE        6
+#define DSCR_CMD0_MAE_FE        7
+#define DSCR_CMD0_SDMS_TX0      8
+#define DSCR_CMD0_SDMS_RX0      9
+#define DSCR_CMD0_SDMS_TX1      10
+#define DSCR_CMD0_SDMS_RX1      11
+#define DSCR_CMD0_AES_TX        13
+#define DSCR_CMD0_AES_RX        12
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_CIM_RXA       18
+#define DSCR_CMD0_CIM_RXB       19
+#define DSCR_CMD0_CIM_RXC       20
+#define DSCR_CMD0_MAE_BOTH      21
+#define DSCR_CMD0_LCD           22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_PSC0_SYNC     24
+#define DSCR_CMD0_PSC1_SYNC     25
+#define DSCR_CMD0_CIM_SYNC      26
+#endif /* CONFIG_SOC_AU1200 */
+
 #define DSCR_CMD0_THROTTLE      30
 #define DSCR_CMD0_ALWAYS        31
 #define DSCR_NDEV_IDS           32
+/* THis macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
+#define DSCR_CUSTOM2DEV_ID(x)   ((x)&0xFF)
+
 
 #define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
 #define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
 */
 #define NUM_DBDMA_CHANS 16
 
+/*
+ * Ddma API definitions
+ * FIXME: may not fit to this header file
+ */
+typedef struct dbdma_device_table {
+        u32             dev_id;
+        u32             dev_flags;
+        u32             dev_tsize;
+        u32             dev_devwidth;
+        u32             dev_physaddr;           /* If FIFO */
+        u32             dev_intlevel;
+        u32             dev_intpolarity;
+} dbdev_tab_t;
+
+
+typedef struct dbdma_chan_config {
+        spinlock_t      lock;
+
+        u32                     chan_flags;
+        u32                     chan_index;
+        dbdev_tab_t             *chan_src;
+        dbdev_tab_t             *chan_dest;
+        au1x_dma_chan_t         *chan_ptr;
+        au1x_ddma_desc_t        *chan_desc_base;
+        au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
+        void                    *chan_callparam;
+        void (*chan_callback)(int, void *, struct pt_regs *);
+} chan_tab_t;
+
+#define DEV_FLAGS_INUSE         (1 << 0)
+#define DEV_FLAGS_ANYUSE        (1 << 1)
+#define DEV_FLAGS_OUT           (1 << 2)
+#define DEV_FLAGS_IN            (1 << 3)
+#define DEV_FLAGS_BURSTABLE (1 << 4)
+#define DEV_FLAGS_SYNC          (1 << 5)
+/* end Ddma API definitions */
+
 /* External functions for drivers to use.
 */
 /* Use this to allocate a dbdma channel.  The device ids are one of the
@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
 
 #define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
 
-/* ACK!  These should be in a board specific description file.
-*/
-#ifdef CONFIG_MIPS_PB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#endif
-#ifdef CONFIG_MIPS_DB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#endif
-
-
 /* Set the device width of a in/out fifo.
 */
 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
 
 /* Put buffers on source/destination descriptors.
 */
-u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
-u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
 
 /* Get a buffer from the destination descriptor.
 */
@@ -295,5 +365,29 @@ u32 au1xxx_get_dma_residue(u32 chanid);
 void au1xxx_dbdma_chan_free(u32 chanid);
 void au1xxx_dbdma_dump(u32 chanid);
 
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
+
+u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
+void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
+
+/*
+        Some compatibilty macros --
+                Needed to make changes to API without breaking existing drivers
+*/
+#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
+#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags)
+
+
+#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
+#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags)
+
+/*
+ *      Flags for the put_source/put_dest functions.
+ */
+#define DDMA_FLAGS_IE   (1<<0)
+#define DDMA_FLAGS_NOIE (1<<1)
+
 #endif /* _LANGUAGE_ASSEMBLY */
 #endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
new file mode 100644
index 000000000000..27911e054ffc
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
@@ -0,0 +1,20 @@
+#ifndef __AU1XXX_GPIO_H
+#define __AU1XXX_GPIO_H
+
+void au1xxx_gpio1_set_inputs(void);
+void au1xxx_gpio_tristate(int signal);
+void au1xxx_gpio_write(int signal, int value);
+int  au1xxx_gpio_read(int signal);
+
+typedef volatile struct
+{
+        u32 dir;
+        u32 reserved;
+        u32 output;
+        u32 pinstate;
+        u32 inten;
+        u32 enable;
+
+} AU1X00_GPIO2;
+
+#endif //__AU1XXX_GPIO_H
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
new file mode 100644
index 000000000000..33d275c3b84c
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -0,0 +1,301 @@
+/*
+ * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
+ *
+ * BRIEF MODULE DESCRIPTION
+ * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
+ *
+ * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
+ *       Interface and Linux Device Driver" Application Note.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        #define DMA_WAIT_TIMEOUT        100
+        #define NUM_DESCRIPTORS         PRD_ENTRIES
+#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
+        #define NUM_DESCRIPTORS         2
+#endif
+
+#ifndef AU1XXX_ATA_RQSIZE
+        #define AU1XXX_ATA_RQSIZE       128
+#endif
+
+/* Disable Burstable-Support for DBDMA */
+#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
+        #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON  0
+#endif
+
+#ifdef CONFIG_PM
+/*
+* This will enable the device to be powered up when write() or read()
+* is called. If this is not defined, the driver will return -EBUSY.
+*/
+#define WAKE_ON_ACCESS 1
+
+typedef struct
+{
+        spinlock_t         lock;       /* Used to block on state transitions */
+        au1xxx_power_dev_t *dev;       /* Power Managers device structure */
+        unsigned           stopped;    /* USed to signaling device is stopped */
+} pm_state;
+#endif
+
+
+typedef struct
+{
+        u32                     tx_dev_id, rx_dev_id, target_dev_id;
+        u32                     tx_chan, rx_chan;
+        void                    *tx_desc_head, *rx_desc_head;
+        ide_hwif_t              *hwif;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        ide_drive_t             *drive;
+        u8                      white_list, black_list;
+        struct dbdma_cmd        *dma_table_cpu;
+        dma_addr_t              dma_table_dma;
+        struct scatterlist      *sg_table;
+        int                     sg_nents;
+        int                     sg_dma_direction;
+#endif
+        struct device           *dev;
+        int                     irq;
+        u32                     regbase;
+#ifdef CONFIG_PM
+        pm_state                pm;
+#endif
+} _auide_hwif;
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+struct drive_list_entry {
+        const char * id_model;
+        const char * id_firmware;
+};
+
+/* HD white list */
+static const struct drive_list_entry dma_white_list [] = {
+/*
+ * Hitachi
+ */
+        { "HITACHI_DK14FA-20"    ,       "ALL"           },
+        { "HTS726060M9AT00"      ,       "ALL"           },
+/*
+ * Maxtor
+ */
+        { "Maxtor 6E040L0"      ,       "ALL"           },
+        { "Maxtor 6Y080P0"      ,       "ALL"           },
+        { "Maxtor 6Y160P0"      ,       "ALL"           },
+/*
+ * Seagate
+ */
+        { "ST3120026A"          ,       "ALL"           },
+        { "ST320014A"           ,       "ALL"           },
+        { "ST94011A"            ,       "ALL"           },
+        { "ST340016A"           ,       "ALL"           },
+/*
+ * Western Digital
+ */
+        { "WDC WD400UE-00HCT0"  ,       "ALL"           },
+        { "WDC WD400JB-00JJC0"  ,       "ALL"           },
+        { NULL                  ,       NULL            }
+};
+
+/* HD black list */
+static const struct drive_list_entry dma_black_list [] = {
+/*
+ * Western Digital
+ */
+        { "WDC WD100EB-00CGH0"  ,       "ALL"           },
+        { "WDC WD200BB-00AUA1"  ,       "ALL"           },
+        { "WDC AC24300L"        ,       "ALL"           },
+        { NULL                  ,       NULL            }
+};
+#endif
+
+/* function prototyping */
+u8 auide_inb(unsigned long port);
+u16 auide_inw(unsigned long port);
+u32 auide_inl(unsigned long port);
+void auide_insw(unsigned long port, void *addr, u32 count);
+void auide_insl(unsigned long port, void *addr, u32 count);
+void auide_outb(u8 addr, unsigned long port);
+void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
+void auide_outw(u16 addr, unsigned long port);
+void auide_outl(u32 addr, unsigned long port);
+void auide_outsw(unsigned long port, void *addr, u32 count);
+void auide_outsl(unsigned long port, void *addr, u32 count);
+static void auide_tune_drive(ide_drive_t *drive, byte pio);
+static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
+static int auide_ddma_init( _auide_hwif *auide );
+static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
+int __init auide_probe(void);
+
+#ifdef CONFIG_PM
+        int au1200ide_pm_callback( au1xxx_power_dev_t *dev,
+                                   au1xxx_request_t request, void *data);
+        static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_access( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev );
+#endif
+
+
+/*
+ * Multi-Word DMA + DbDMA functions
+ */
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+
+        static int in_drive_list(struct hd_driveid *id,
+                                 const struct drive_list_entry *drive_table);
+        static int auide_build_sglist(ide_drive_t *drive,  struct request *rq);
+        static int auide_build_dmatable(ide_drive_t *drive);
+        static int auide_dma_end(ide_drive_t *drive);
+        static void auide_dma_start(ide_drive_t *drive );
+        ide_startstop_t auide_dma_intr (ide_drive_t *drive);
+        static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command);
+        static int auide_dma_setup(ide_drive_t *drive);
+        static int auide_dma_check(ide_drive_t *drive);
+        static int auide_dma_test_irq(ide_drive_t *drive);
+        static int auide_dma_host_off(ide_drive_t *drive);
+        static int auide_dma_host_on(ide_drive_t *drive);
+        static int auide_dma_lostirq(ide_drive_t *drive);
+        static int auide_dma_on(ide_drive_t *drive);
+        static void auide_ddma_tx_callback(int irq, void *param,
+                                           struct pt_regs *regs);
+        static void auide_ddma_rx_callback(int irq, void *param,
+                                           struct pt_regs *regs);
+        static int auide_dma_off_quietly(ide_drive_t *drive);
+        static int auide_dma_timeout(ide_drive_t *drive);
+
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
+
+/*******************************************************************************
+* PIO Mode timing calculation :                                                *
+*                                                                              *
+* Static Bus Spec   ATA Spec                                                   *
+*      Tcsoe      =   t1                                                       *
+*      Toecs      =   t9                                                       *
+*      Twcs       =   t9                                                       *
+*      Tcsh       =   t2i | t2                                                 *
+*      Tcsoff     =   t2i | t2                                                 *
+*      Twp        =   t2                                                       *
+*      Tcsw       =   t1                                                       *
+*      Tpm        =   0                                                        *
+*      Ta         =   t1+t2                                                    *
+*******************************************************************************/
+
+#define TCSOE_MASK            (0x07<<29)
+#define TOECS_MASK            (0x07<<26)
+#define TWCS_MASK             (0x07<<28)
+#define TCSH_MASK             (0x0F<<24)
+#define TCSOFF_MASK           (0x07<<20)
+#define TWP_MASK              (0x3F<<14)
+#define TCSW_MASK             (0x0F<<10)
+#define TPM_MASK              (0x0F<<6)
+#define TA_MASK               (0x3F<<0)
+#define TS_MASK               (1<<8)
+
+/* Timing parameters PIO mode 0 */
+#define SBC_IDE_PIO0_TCSOE    (0x04<<29)
+#define SBC_IDE_PIO0_TOECS    (0x01<<26)
+#define SBC_IDE_PIO0_TWCS     (0x02<<28)
+#define SBC_IDE_PIO0_TCSH     (0x08<<24)
+#define SBC_IDE_PIO0_TCSOFF   (0x07<<20)
+#define SBC_IDE_PIO0_TWP      (0x10<<14)
+#define SBC_IDE_PIO0_TCSW     (0x04<<10)
+#define SBC_IDE_PIO0_TPM      (0x0<<6)
+#define SBC_IDE_PIO0_TA       (0x15<<0)
+/* Timing parameters PIO mode 1 */
+#define SBC_IDE_PIO1_TCSOE    (0x03<<29)
+#define SBC_IDE_PIO1_TOECS    (0x01<<26)
+#define SBC_IDE_PIO1_TWCS     (0x01<<28)
+#define SBC_IDE_PIO1_TCSH     (0x06<<24)
+#define SBC_IDE_PIO1_TCSOFF   (0x06<<20)
+#define SBC_IDE_PIO1_TWP      (0x08<<14)
+#define SBC_IDE_PIO1_TCSW     (0x03<<10)
+#define SBC_IDE_PIO1_TPM      (0x00<<6)
+#define SBC_IDE_PIO1_TA       (0x0B<<0)
+/* Timing parameters PIO mode 2 */
+#define SBC_IDE_PIO2_TCSOE    (0x05<<29)
+#define SBC_IDE_PIO2_TOECS    (0x01<<26)
+#define SBC_IDE_PIO2_TWCS     (0x01<<28)
+#define SBC_IDE_PIO2_TCSH     (0x07<<24)
+#define SBC_IDE_PIO2_TCSOFF   (0x07<<20)
+#define SBC_IDE_PIO2_TWP      (0x1F<<14)
+#define SBC_IDE_PIO2_TCSW     (0x05<<10)
+#define SBC_IDE_PIO2_TPM      (0x00<<6)
+#define SBC_IDE_PIO2_TA       (0x22<<0)
+/* Timing parameters PIO mode 3 */
+#define SBC_IDE_PIO3_TCSOE    (0x05<<29)
+#define SBC_IDE_PIO3_TOECS    (0x01<<26)
+#define SBC_IDE_PIO3_TWCS     (0x01<<28)
+#define SBC_IDE_PIO3_TCSH     (0x0D<<24)
+#define SBC_IDE_PIO3_TCSOFF   (0x0D<<20)
+#define SBC_IDE_PIO3_TWP      (0x15<<14)
+#define SBC_IDE_PIO3_TCSW     (0x05<<10)
+#define SBC_IDE_PIO3_TPM      (0x00<<6)
+#define SBC_IDE_PIO3_TA       (0x1A<<0)
+/* Timing parameters PIO mode 4 */
+#define SBC_IDE_PIO4_TCSOE    (0x04<<29)
+#define SBC_IDE_PIO4_TOECS    (0x01<<26)
+#define SBC_IDE_PIO4_TWCS     (0x01<<28)
+#define SBC_IDE_PIO4_TCSH     (0x04<<24)
+#define SBC_IDE_PIO4_TCSOFF   (0x04<<20)
+#define SBC_IDE_PIO4_TWP      (0x0D<<14)
+#define SBC_IDE_PIO4_TCSW     (0x03<<10)
+#define SBC_IDE_PIO4_TPM      (0x00<<6)
+#define SBC_IDE_PIO4_TA       (0x12<<0)
+/* Timing parameters MDMA mode 0 */
+#define SBC_IDE_MDMA0_TCSOE   (0x03<<29)
+#define SBC_IDE_MDMA0_TOECS   (0x01<<26)
+#define SBC_IDE_MDMA0_TWCS    (0x01<<28)
+#define SBC_IDE_MDMA0_TCSH    (0x07<<24)
+#define SBC_IDE_MDMA0_TCSOFF  (0x07<<20)
+#define SBC_IDE_MDMA0_TWP     (0x0C<<14)
+#define SBC_IDE_MDMA0_TCSW    (0x03<<10)
+#define SBC_IDE_MDMA0_TPM     (0x00<<6)
+#define SBC_IDE_MDMA0_TA      (0x0F<<0)
+/* Timing parameters MDMA mode 1 */
+#define SBC_IDE_MDMA1_TCSOE   (0x05<<29)
+#define SBC_IDE_MDMA1_TOECS   (0x01<<26)
+#define SBC_IDE_MDMA1_TWCS    (0x01<<28)
+#define SBC_IDE_MDMA1_TCSH    (0x05<<24)
+#define SBC_IDE_MDMA1_TCSOFF  (0x05<<20)
+#define SBC_IDE_MDMA1_TWP     (0x0F<<14)
+#define SBC_IDE_MDMA1_TCSW    (0x05<<10)
+#define SBC_IDE_MDMA1_TPM     (0x00<<6)
+#define SBC_IDE_MDMA1_TA      (0x15<<0)
+/* Timing parameters MDMA mode 2 */
+#define SBC_IDE_MDMA2_TCSOE   (0x04<<29)
+#define SBC_IDE_MDMA2_TOECS   (0x01<<26)
+#define SBC_IDE_MDMA2_TWCS    (0x01<<28)
+#define SBC_IDE_MDMA2_TCSH    (0x04<<24)
+#define SBC_IDE_MDMA2_TCSOFF  (0x04<<20)
+#define SBC_IDE_MDMA2_TWP     (0x0D<<14)
+#define SBC_IDE_MDMA2_TCSW    (0x04<<10)
+#define SBC_IDE_MDMA2_TPM     (0x00<<6)
+#define SBC_IDE_MDMA2_TA      (0x12<<0)
+
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index 283519dfdec4..8e5fb3c7da4d 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -33,6 +33,8 @@
 #ifndef _AU1000_PSC_H_
 #define _AU1000_PSC_H_
 
+#include <linux/config.h>
+
 /* The PSC base addresses.  */
 #ifdef CONFIG_SOC_AU1550
 #define PSC0_BASE_ADDR          0xb1a00000
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
new file mode 100644
index 000000000000..d3ec6274575a
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/ioremap.h
@@ -0,0 +1,32 @@
+/*
+ *      include/asm-mips/mach-au1x00/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_AU1X00_IOREMAP_H
+#define __ASM_MACH_AU1X00_IOREMAP_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+#ifdef CONFIG_64BIT_PHYS_ADDR
+extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
+#else
+static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+#endif
+
+/*
+ * Allow physical addresses to be fixed up to help 36-bit peripherals.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return __fixup_bigphys_addr(phys_addr, size);
+}
+
+#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
new file mode 100644
index 000000000000..5d894376fc1a
--- /dev/null
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -0,0 +1,224 @@
+/*
+ * AMD Alchemy DB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_DB1200_H
+#define __ASM_DB1200_H
+
+#include <linux/types.h>
+
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE            PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR 0xB9800000
+
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 board;
+                u16 reserved5;
+        /*18*/  u16 disk_leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+
+        /*20*/  u16 intclr;
+                u16 reserved8;
+        /*24*/  u16 intset;
+                u16 reserved9;
+        /*28*/  u16 intclr_mask;
+                u16 reserved10;
+        /*2C*/  u16 intset_mask;
+                u16 reserved11;
+
+        /*30*/  u16 sig_status;
+                u16 reserved12;
+        /*34*/  u16 int_status;
+                u16 reserved13;
+        /*38*/  u16 reserved14;
+                u16 reserved15;
+        /*3C*/  u16 reserved16;
+                u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_IDECBLID    0x0200
+#define BCSR_STATUS_SD0WP               0x0400
+#define BCSR_STATUS_U0RXD               0x1000
+#define BCSR_STATUS_U1RXD               0x2000
+
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+
+#define BCSR_RESETS_ETH         0x0001
+#define BCSR_RESETS_CAMERA      0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_IDE         0x0008
+#define BCSR_RESETS_TV          0x0010
+/* not resets but in the same register */
+#define BCSR_RESETS_PWMR1mUX 0x0800
+#define BCSR_RESETS_PCS0MUX     0x1000
+#define BCSR_RESETS_PCS1MUX     0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+
+#define BCSR_BOARD_LCDVEE       0x0001
+#define BCSR_BOARD_LCDVDD       0x0002
+#define BCSR_BOARD_LCDBL        0x0004
+#define BCSR_BOARD_CAMSNAP      0x0010
+#define BCSR_BOARD_CAMPWR       0x0020
+#define BCSR_BOARD_SD0PWR       0x0040
+
+#define BCSR_LEDS_DECIMALS      0x0003
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC                     0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+
+#define AU1XXX_SMC91111_PHYS_ADDR       (0x19000300)
+#define AU1XXX_SMC91111_IRQ                     DB1200_ETH_INT
+
+#define AU1XXX_ATA_PHYS_ADDR            (0x18800000)
+#define AU1XXX_ATA_PHYS_LEN                     (0x100)
+#define AU1XXX_ATA_REG_OFFSET   (5)
+#define AU1XXX_ATA_INT                  DB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE               128
+
+#define NAND_PHYS_ADDR   0x20000000
+
+/*
+ *      External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the DB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define DB1200_INT_BEGIN                (AU1000_LAST_INTC1_INT + 1)
+#define DB1200_IDE_INT                  (DB1200_INT_BEGIN + 0)
+#define DB1200_ETH_INT                  (DB1200_INT_BEGIN + 1)
+#define DB1200_PC0_INT                  (DB1200_INT_BEGIN + 2)
+#define DB1200_PC0_STSCHG_INT   (DB1200_INT_BEGIN + 3)
+#define DB1200_PC1_INT                  (DB1200_INT_BEGIN + 4)
+#define DB1200_PC1_STSCHG_INT   (DB1200_INT_BEGIN + 5)
+#define DB1200_DC_INT                   (DB1200_INT_BEGIN + 6)
+#define DB1200_FLASHBUSY_INT    (DB1200_INT_BEGIN + 7)
+#define DB1200_PC0_INSERT_INT   (DB1200_INT_BEGIN + 8)
+#define DB1200_PC0_EJECT_INT    (DB1200_INT_BEGIN + 9)
+#define DB1200_PC1_INSERT_INT   (DB1200_INT_BEGIN + 10)
+#define DB1200_PC1_EJECT_INT    (DB1200_INT_BEGIN + 11)
+#define DB1200_SD0_INSERT_INT   (DB1200_INT_BEGIN + 12)
+#define DB1200_SD0_EJECT_INT    (DB1200_INT_BEGIN + 13)
+
+#define DB1200_INT_END                  (DB1200_INT_BEGIN + 15)
+
+/* For drivers/pcmcia/au1000_db1x00.c */
+
+/* PCMCIA Db1x00 specific defines */
+
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+
+#define BOARD_PC0_INT DB1200_PC0_INT
+#define BOARD_PC1_INT DB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+
+#endif /* __ASM_DB1200_H */
+
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
index a326f451253b..6d37a5675803 100644
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ b/include/asm-mips/mach-dec/mc146818rtc.h
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1998, 2001 by Ralf Baechle
  * Copyright (C) 1998 by Harald Koerfgen
- * Copyright (C) 2002  Maciej W. Rozycki
+ * Copyright (C) 2002, 2005  Maciej W. Rozycki
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -14,23 +14,18 @@
 #define __ASM_MIPS_DEC_RTC_DEC_H
 
 #include <linux/types.h>
-
 #include <asm/addrspace.h>
+#include <asm/dec/system.h>
 
 extern volatile u8 *dec_rtc_base;
-extern unsigned long dec_kn_slot_size;
 
-#define RTC_PORT(x)     CPHYSADDR(dec_rtc_base)
+#define RTC_PORT(x)     CPHYSADDR((long)dec_rtc_base)
 #define RTC_IO_EXTENT   dec_kn_slot_size
 #define RTC_IOMAPPED    0
 #undef RTC_IRQ
 
 #define RTC_DEC_YEAR    0x3f    /* Where we store the real year on DECs.  */
 
-#include <linux/mc146818rtc.h>
-#include <linux/module.h>
-#include <linux/types.h>
-
 static inline unsigned char CMOS_READ(unsigned long addr)
 {
         return dec_rtc_base[addr * 4];
diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h
index 0aecfd08e39a..7c185bb06f13 100644
--- a/include/asm-mips/mach-generic/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-generic/cpu-feature-overrides.h
@@ -8,6 +8,6 @@
 #ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 #define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 
-/* Intensionally empty file ...  */
+/* Intentionally empty file ...  */
 
 #endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index cb2edd018ad6..961006948c7c 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -18,6 +18,7 @@
 #include <linux/config.h>
 #include <linux/pci.h>
 #include <linux/stddef.h>
+#include <asm/processor.h>
 
 #ifndef MAX_HWIFS
 # ifdef CONFIG_BLK_DEV_IDEPCI
@@ -104,15 +105,71 @@ static __inline__ unsigned long ide_default_io_base(int index)
 
 /* MIPS port and memory-mapped I/O string operations.  */
 
-#define __ide_insw      insw
-#define __ide_insl      insl
-#define __ide_outsw     outsw
-#define __ide_outsl     outsl
+static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
+{
+        if (cpu_has_dc_aliases) {
+                unsigned long end = addr + size;
+                for (; addr < end; addr += PAGE_SIZE)
+                        flush_dcache_page(virt_to_page(addr));
+        }
+}
+
+static inline void __ide_insw(unsigned long port, void *addr,
+        unsigned int count)
+{
+        insw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+
+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
+{
+        insl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
+
+static inline void __ide_outsw(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        outsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+
+static inline void __ide_outsl(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        outsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
+
+static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
+{
+        readsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+
+static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
+{
+        readsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
+
+static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
+{
+        writesw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+
+static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
+{
+        writesl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
 
-#define __ide_mm_insw   readsw
-#define __ide_mm_insl   readsl
-#define __ide_mm_outsw  writesw
-#define __ide_mm_outsl  writesl
+/* ide_insw calls insw, not __ide_insw.  Why? */
+#undef insw
+#undef insl
+#define insw(port, addr, count) __ide_insw(port, addr, count)
+#define insl(port, addr, count) __ide_insl(port, addr, count)
 
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
new file mode 100644
index 000000000000..9b64ff6e485d
--- /dev/null
+++ b/include/asm-mips/mach-generic/ioremap.h
@@ -0,0 +1,23 @@
+/*
+ *      include/asm-mips/mach-generic/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/include/asm-mips/mach-generic/kernel-entry-init.h
new file mode 100644
index 000000000000..7e66505fa574
--- /dev/null
+++ b/include/asm-mips/mach-generic/kernel-entry-init.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+
+/* Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+.macro  kernel_entry_setup
+.endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+
+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h
new file mode 100644
index 000000000000..373d66dee9d7
--- /dev/null
+++ b/include/asm-mips/mach-generic/kmalloc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_MACH_GENERIC_KMALLOC_H
+#define __ASM_MACH_GENERIC_KMALLOC_H
+
+#include <linux/config.h>
+
+#ifndef CONFIG_DMA_COHERENT
+/*
+ * Total overkill for most systems but need as a safe default.
+ */
+#define ARCH_KMALLOC_MINALIGN   128
+#endif
+
+#endif /* __ASM_MACH_GENERIC_KMALLOC_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 5a2c1efb4eb7..b849d8dd7e78 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -55,13 +55,13 @@
 #endif
 
 #ifdef CONFIG_DMA_NONCOHERENT
-#define CAC_BASE                0x9800000000000000
+#define CAC_BASE                0x9800000000000000UL
 #else
-#define CAC_BASE                0xa800000000000000
+#define CAC_BASE                0xa800000000000000UL
 #endif
-#define IO_BASE                 0x9000000000000000
-#define UNCAC_BASE              0x9000000000000000
-#define MAP_BASE                0xc000000000000000
+#define IO_BASE                 0x9000000000000000UL
+#define UNCAC_BASE              0x9000000000000000UL
+#define MAP_BASE                0xc000000000000000UL
 
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
index 3c8896d9b133..ab9714668177 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -11,6 +11,12 @@
 /*
  * IP22 with a variety of processors so we can't use defaults for everything.
  */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4kcache         1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
 #define cpu_has_mips16          0
 #define cpu_has_divec           0
 #define cpu_has_cache_cdex_p    1
@@ -23,6 +29,8 @@
 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_ic_fills_f_dc   0
 
+#define cpu_has_dsp             0
+
 #define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index e96166f27c49..8385f716798d 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -44,7 +44,7 @@
 #define CAC_BASE                0xffffffff80000000
 #define IO_BASE                 0xffffffffa0000000
 #define UNCAC_BASE              0xffffffffa0000000
-#define MAP_BASE                0xffffffffc0000000
+#define MAP_BASE                0xc000000000000000
 
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index fe96d7358517..4c8a90051fd0 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  1
 
 #define cpu_has_nofpuex         0
diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/include/asm-mips/mach-ip27/kernel-entry-init.h
new file mode 100644
index 000000000000..c1a10314b317
--- /dev/null
+++ b/include/asm-mips/mach-ip27/kernel-entry-init.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
+#define __ASM_MACH_IP27_KERNEL_ENTRY_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn0/hubni.h>
+#include <asm/sn/klkernvars.h>
+
+/*
+ * Returns the local nasid into res.
+ */
+        .macro GET_NASID_ASM res
+        dli     \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
+        ld      \res, (\res)
+        and     \res, NSRI_NODEID_MASK
+        dsrl    \res, NSRI_NODEID_SHFT
+        .endm
+
+/*
+ * Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+        .macro  kernel_entry_setup
+        GET_NASID_ASM   t1
+        move            t2, t1                  # text and data are here
+        MAPPED_KERNEL_SETUP_TLB
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        GET_NASID_ASM   t1
+        dli     t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
+                    KLDIR_OFF_POINTER + CAC_BASE
+        dsll    t1, NASID_SHFT
+        or      t0, t0, t1
+        ld      t0, 0(t0)                       # t0 points to kern_vars struct
+        lh      t1, KV_RO_NASID_OFFSET(t0)
+        lh      t2, KV_RW_NASID_OFFSET(t0)
+        MAPPED_KERNEL_SETUP_TLB
+        ARC64_TWIDDLE_PC
+        .endm
+
+#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/include/asm-mips/mach-ip27/kmalloc.h
new file mode 100644
index 000000000000..426bd049b2d7
--- /dev/null
+++ b/include/asm-mips/mach-ip27/kmalloc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_MACH_IP27_KMALLOC_H
+#define __ASM_MACH_IP27_KMALLOC_H
+
+/*
+ * All happy, no need to define ARCH_KMALLOC_MINALIGN
+ */
+
+#endif /* __ASM_MACH_IP27_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h
index d3f566362e9d..986a3b9b59a7 100644
--- a/include/asm-mips/mach-ip27/mmzone.h
+++ b/include/asm-mips/mach-ip27/mmzone.h
@@ -10,7 +10,6 @@
 #define LEVELS_PER_SLICE        128
 
 struct slice_data {
-        unsigned long irq_alloc_mask[2];
         unsigned long irq_enable_mask[2];
         int level_to_irq[LEVELS_PER_SLICE];
 };
@@ -20,6 +19,7 @@ struct hub_data {
         DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
         cpumask_t       h_cpus;
         unsigned long slice_map;
+        unsigned long irq_alloc_mask[2];
         struct slice_data slice[2];
 };
 
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index e3b3fe32eeb1..45e61785ef42 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -20,6 +20,7 @@
 #define IO_BASE                 0x9200000000000000
 #define MSPEC_BASE              0x9400000000000000
 #define UNCAC_BASE              0x9600000000000000
+#define MAP_BASE                0xc000000000000000
 
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index a70a81257c3d..82141c711c33 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -9,6 +9,9 @@
 #define parent_node(node)       (node)
 #define node_to_cpumask(node)   (hub_data(node)->h_cpus)
 #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
+struct pci_bus;
+extern int pcibus_to_node(struct pci_bus *);
+
 #define pcibus_to_cpumask(bus)  (cpu_online_map)
 
 extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index 04713973c6c3..ab37fc1842ba 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -37,5 +37,6 @@
 #define cpu_has_ejtag           0
 #define cpu_has_vtag_icache     0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 
 #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
new file mode 100644
index 000000000000..9d2d4d9ac036
--- /dev/null
+++ b/include/asm-mips/mach-ip32/kmalloc.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_MACH_IP32_KMALLOC_H
+#define __ASM_MACH_IP32_KMALLOC_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000)
+#define ARCH_KMALLOC_MINALIGN   32
+#else
+#define ARCH_KMALLOC_MINALIGN   128
+#endif
+
+#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
index c7839f85c68d..44abe5c02389 100644
--- a/include/asm-mips/mach-ip32/spaces.h
+++ b/include/asm-mips/mach-ip32/spaces.h
@@ -19,10 +19,10 @@
 #define HIGHMEM_START           (1UL << 59UL)
 #endif
 
-#define CAC_BASE                0x9800000000000000
-#define IO_BASE                 0x9000000000000000
-#define UNCAC_BASE              0x9000000000000000
-#define MAP_BASE                0xc000000000000000
+#define CAC_BASE                0x9800000000000000UL
+#define IO_BASE                 0x9000000000000000UL
+#define UNCAC_BASE              0x9000000000000000UL
+#define MAP_BASE                0xc000000000000000UL
 
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index ca57e7db98bb..a0fde405d4c4 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 
 #define cpu_has_nofpuex         0
@@ -36,10 +37,4 @@
 #define cpu_icache_line_size()  32
 #define cpu_scache_line_size()  32
 
-/*
- * On the RM9000 we need to ensure that I-cache lines being fetches only
- * contain valid instructions are funny things will happen.
- */
-#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
-
 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
index 6f51be571bf0..9f92aed17754 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -17,7 +17,7 @@
 #ifdef CONFIG_CPU_MIPS32
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_4ktlb           1
+#define cpu_has_4kcache         1
 /* #define cpu_has_fpu          ? */
 /* #define cpu_has_32fpr        ? */
 #define cpu_has_counter         1
@@ -37,12 +37,13 @@
 /* #define cpu_has_64bits       ? */
 /* #define cpu_has_64bit_zero_reg ? */
 /* #define cpu_has_subset_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
 #endif
 
 #ifdef CONFIG_CPU_MIPS64
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_4ktlb           1
+#define cpu_has_4kcache         1
 /* #define cpu_has_fpu          ? */
 /* #define cpu_has_32fpr        ? */
 #define cpu_has_counter         1
@@ -62,6 +63,7 @@
 /* #define cpu_has_64bits       ? */
 /* #define cpu_has_64bit_zero_reg ? */
 /* #define cpu_has_subset_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
 #endif
 
 #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h
new file mode 100644
index 000000000000..f8579696ca54
--- /dev/null
+++ b/include/asm-mips/mach-mips/irq.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+
+#include <linux/config.h>
+
+#define NR_IRQS 256
+
+#ifdef CONFIG_SMP
+
+#define ARCH_HAS_IRQ_PER_CPU
+
+#endif
+
+#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
index 7473512384bc..825c5f674dfc 100644
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -28,6 +28,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 
 #define cpu_has_nofpuex         0
@@ -39,10 +40,4 @@
 #define cpu_icache_line_size()  32
 #define cpu_scache_line_size()  32
 
-/*
- * On the RM9000 we need to ensure that I-cache lines being fetches only
- * contain valid instructions are funny things will happen.
- */
-#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
-
 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..9a3088b19bf3
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -0,0 +1,252 @@
+/*
+ * AMD Alchemy PB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1200_H
+#define __ASM_PB1200_H
+
+#include <linux/types.h>
+
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE            PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR 0xAD800000
+
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 board;
+                u16 reserved5;
+        /*18*/  u16 disk_leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+
+        /*20*/  u16 intclr;
+                u16 reserved8;
+        /*24*/  u16 intset;
+                u16 reserved9;
+        /*28*/  u16 intclr_mask;
+                u16 reserved10;
+        /*2C*/  u16 intset_mask;
+                u16 reserved11;
+
+        /*30*/  u16 sig_status;
+                u16 reserved12;
+        /*34*/  u16 int_status;
+                u16 reserved13;
+        /*38*/  u16 reserved14;
+                u16 reserved15;
+        /*3C*/  u16 reserved16;
+                u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_IDECBLID    0x0200
+#define BCSR_STATUS_SD0WP               0x0400
+#define BCSR_STATUS_SD1WP               0x0800
+#define BCSR_STATUS_U0RXD               0x1000
+#define BCSR_STATUS_U1RXD               0x2000
+
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+
+#define BCSR_RESETS_ETH         0x0001
+#define BCSR_RESETS_CAMERA      0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_IDE         0x0008
+/* not resets but in the same register */
+#define BCSR_RESETS_WSCFSM  0x0800
+#define BCSR_RESETS_PCS0MUX     0x1000
+#define BCSR_RESETS_PCS1MUX     0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+#define BCSR_RESETS_SD1MUX  0x8000
+
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+
+#define BCSR_BOARD_LCDVEE       0x0001
+#define BCSR_BOARD_LCDVDD       0x0002
+#define BCSR_BOARD_LCDBL        0x0004
+#define BCSR_BOARD_CAMSNAP      0x0010
+#define BCSR_BOARD_CAMPWR       0x0020
+#define BCSR_BOARD_SD0PWR       0x0040
+#define BCSR_BOARD_SD1PWR       0x0080
+
+#define BCSR_LEDS_DECIMALS      0x00FF
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+
+#define BCSR_SYSTEM_VDDI        0x001F
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC                     0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
+
+/* PCMCIA Db1x00 specific defines */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+
+#define AU1XXX_SMC91111_PHYS_ADDR       (0x0D000300)
+#define AU1XXX_SMC91111_IRQ                     PB1200_ETH_INT
+
+#define AU1XXX_ATA_PHYS_ADDR            (0x0C800000)
+#define AU1XXX_ATA_PHYS_LEN                     (0x100)
+#define AU1XXX_ATA_REG_OFFSET   (5)
+#define AU1XXX_ATA_INT                  PB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE               128
+
+#define NAND_PHYS_ADDR   0x1C000000
+
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1200 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                        (18 >> 2)
+#define NAND_T_PUL                      (30 >> 2)
+#define NAND_T_SU                       (30 >> 2)
+#define NAND_T_WH                       (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
+                        ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
+                        ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
+                        ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+
+
+/*
+ *      External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define PB1200_INT_BEGIN                (AU1000_LAST_INTC1_INT + 1)
+#define PB1200_IDE_INT                  (PB1200_INT_BEGIN + 0)
+#define PB1200_ETH_INT                  (PB1200_INT_BEGIN + 1)
+#define PB1200_PC0_INT                  (PB1200_INT_BEGIN + 2)
+#define PB1200_PC0_STSCHG_INT   (PB1200_INT_BEGIN + 3)
+#define PB1200_PC1_INT                  (PB1200_INT_BEGIN + 4)
+#define PB1200_PC1_STSCHG_INT   (PB1200_INT_BEGIN + 5)
+#define PB1200_DC_INT                   (PB1200_INT_BEGIN + 6)
+#define PB1200_FLASHBUSY_INT    (PB1200_INT_BEGIN + 7)
+#define PB1200_PC0_INSERT_INT   (PB1200_INT_BEGIN + 8)
+#define PB1200_PC0_EJECT_INT    (PB1200_INT_BEGIN + 9)
+#define PB1200_PC1_INSERT_INT   (PB1200_INT_BEGIN + 10)
+#define PB1200_PC1_EJECT_INT    (PB1200_INT_BEGIN + 11)
+#define PB1200_SD0_INSERT_INT   (PB1200_INT_BEGIN + 12)
+#define PB1200_SD0_EJECT_INT    (PB1200_INT_BEGIN + 13)
+#define PB1200_SD1_INSERT_INT   (PB1200_INT_BEGIN + 14)
+#define PB1200_SD1_EJECT_INT    (PB1200_INT_BEGIN + 15)
+
+#define PB1200_INT_END                  (PB1200_INT_BEGIN + 15)
+
+/* For drivers/pcmcia/au1000_db1x00.c */
+#define BOARD_PC0_INT PB1200_PC0_INT
+#define BOARD_PC1_INT PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+
+#endif /* __ASM_PB1200_H */
+
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Clock module specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_CM_H
+#define __PNX8550_CM_H
+
+#define PNX8550_CM_BASE 0xBBE47000
+
+#define PNX8550_CM_PLL0_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
+#define PNX8550_CM_PLL1_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
+#define PNX8550_CM_PLL2_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
+#define PNX8550_CM_PLL3_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
+
+// Table not complete.....
+
+#define PNX8550_CM_PLL_BLOCKED_MASK     0x80000000
+#define PNX8550_CM_PLL_LOCK_MASK        0x40000000
+#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
+#define PNX8550_CM_PLL_N_MASK           0x01ff0000
+#define PNX8550_CM_PLL_M_MASK           0x00003f00
+#define PNX8550_CM_PLL_P_MASK           0x0000000c
+#define PNX8550_CM_PLL_PD_MASK          0x00000002
+
+
+#endif
diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h
new file mode 100644
index 000000000000..07aa85e609bc
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/glb.h
@@ -0,0 +1,86 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   PNX8550 global definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_GLB_H
+#define __PNX8550_GLB_H
+
+#define PNX8550_GLB1_BASE       0xBBE63000
+#define PNX8550_GLB2_BASE       0xBBE4d000
+#define PNX8550_RESET_BASE      0xBBE60000
+
+/* PCI Inta Output Enable Registers */
+#define PNX8550_GLB2_ENAB_INTA_O        *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
+
+/* Bit 1:Enable DAC Powerdown
+     0:DACs are enabled and are working normally
+     1:DACs are powerdown
+*/
+#define PNX8550_GLB_DAC_PD      0x2
+/*   Bit 0:Enable of PCI inta output
+     0 = Disable PCI inta output
+     1 = Enable PCI inta output
+*/
+#define PNX8550_GLB_ENABLE_INTA_O 0x1
+
+/* PCI Direct Mappings */
+#define PNX8550_PCIMEM          0x12000000
+#define PNX8550_PCIMEM_SIZE     0x08000000
+#define PNX8550_PCIIO           0x1c000000
+#define PNX8550_PCIIO_SIZE      0x02000000      /* 32M */
+
+#define PNX8550_PORT_BASE       KSEG1
+
+// GPIO def
+#define PNX8550_GPIO_BASE       0x1Be00000
+
+#define PNX8550_GPIO_DIRQ0       (PNX8550_GPIO_BASE + 0x104500)
+#define PNX8550_GPIO_MC1         (PNX8550_GPIO_BASE + 0x104004)
+#define PNX8550_GPIO_MC_31_BIT   30
+#define PNX8550_GPIO_MC_30_BIT   28
+#define PNX8550_GPIO_MC_29_BIT   26
+#define PNX8550_GPIO_MC_28_BIT   24
+#define PNX8550_GPIO_MC_27_BIT   22
+#define PNX8550_GPIO_MC_26_BIT   20
+#define PNX8550_GPIO_MC_25_BIT   18
+#define PNX8550_GPIO_MC_24_BIT   16
+#define PNX8550_GPIO_MC_23_BIT   14
+#define PNX8550_GPIO_MC_22_BIT   12
+#define PNX8550_GPIO_MC_21_BIT   10
+#define PNX8550_GPIO_MC_20_BIT   8
+#define PNX8550_GPIO_MC_19_BIT   6
+#define PNX8550_GPIO_MC_18_BIT   4
+#define PNX8550_GPIO_MC_17_BIT   2
+#define PNX8550_GPIO_MC_16_BIT   0
+
+#define PNX8550_GPIO_MODE_PRIMOP    0x1
+#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
+#define PNX8550_GPIO_MODE_OPENDR    0x3
+
+// RESET module
+#define PNX8550_RST_CTL             *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
+#define PNX8550_RST_CAUSE           *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
+#define PNX8550_RST_EN_WATCHDOG     *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
+
+#define PNX8550_RST_REL_MIPS_RST_N     0x8
+#define PNX8550_RST_DO_SW_RST          0x4
+#define PNX8550_RST_REL_SYS_RST_OUT    0x2
+#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
+#endif
diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h
new file mode 100644
index 000000000000..0e0668b524f4
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/int.h
@@ -0,0 +1,140 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Interrupt specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_INT_H
+#define __PNX8550_INT_H
+
+#define PNX8550_GIC_BASE        0xBBE3E000
+
+#define PNX8550_GIC_PRIMASK_0   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
+#define PNX8550_GIC_PRIMASK_1   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
+#define PNX8550_GIC_VECTOR_0    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
+#define PNX8550_GIC_VECTOR_1    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
+#define PNX8550_GIC_PEND_1_31   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
+#define PNX8550_GIC_PEND_32_63  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
+#define PNX8550_GIC_PEND_64_70  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
+#define PNX8550_GIC_FEATURES    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
+#define PNX8550_GIC_REQ(x)      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
+#define PNX8550_GIC_MOD_ID      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
+
+// cp0 is two software + six hw exceptions
+#define PNX8550_INT_CP0_TOTINT  8
+#define PNX8550_INT_CP0_MIN     0
+#define PNX8550_INT_CP0_MAX     (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
+
+#define MIPS_CPU_GIC_IRQ        2
+#define MIPS_CPU_TIMER_IRQ      7
+
+// GIC are 71 exceptions connected to cp0's first hardware exception
+#define PNX8550_INT_GIC_TOTINT  71
+#define PNX8550_INT_GIC_MIN     (PNX8550_INT_CP0_MAX+1)
+#define PNX8550_INT_GIC_MAX     (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
+
+#define PNX8550_INT_UNDEF              (PNX8550_INT_GIC_MIN+0)
+#define PNX8550_INT_IPC_TARGET0_MIPS   (PNX8550_INT_GIC_MIN+1)
+#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
+#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
+#define PNX8550_INT_RESERVED_4         (PNX8550_INT_GIC_MIN+4)
+#define PNX8550_INT_USB                (PNX8550_INT_GIC_MIN+5)
+#define PNX8550_INT_GPIO_EQ1           (PNX8550_INT_GIC_MIN+6)
+#define PNX8550_INT_GPIO_EQ2           (PNX8550_INT_GIC_MIN+7)
+#define PNX8550_INT_GPIO_EQ3           (PNX8550_INT_GIC_MIN+8)
+#define PNX8550_INT_GPIO_EQ4           (PNX8550_INT_GIC_MIN+9)
+
+#define PNX8550_INT_GPIO_EQ5           (PNX8550_INT_GIC_MIN+10)
+#define PNX8550_INT_GPIO_EQ6           (PNX8550_INT_GIC_MIN+11)
+#define PNX8550_INT_RESERVED_12        (PNX8550_INT_GIC_MIN+12)
+#define PNX8550_INT_QVCP1              (PNX8550_INT_GIC_MIN+13)
+#define PNX8550_INT_QVCP2              (PNX8550_INT_GIC_MIN+14)
+#define PNX8550_INT_I2C1               (PNX8550_INT_GIC_MIN+15)
+#define PNX8550_INT_I2C2               (PNX8550_INT_GIC_MIN+16)
+#define PNX8550_INT_ISO_UART1          (PNX8550_INT_GIC_MIN+17)
+#define PNX8550_INT_ISO_UART2          (PNX8550_INT_GIC_MIN+18)
+#define PNX8550_INT_UART1              (PNX8550_INT_GIC_MIN+19)
+
+#define PNX8550_INT_UART2              (PNX8550_INT_GIC_MIN+20)
+#define PNX8550_INT_QNTR               (PNX8550_INT_GIC_MIN+21)
+#define PNX8550_INT_RESERVED22         (PNX8550_INT_GIC_MIN+22)
+#define PNX8550_INT_T_DSC              (PNX8550_INT_GIC_MIN+23)
+#define PNX8550_INT_M_DSC              (PNX8550_INT_GIC_MIN+24)
+#define PNX8550_INT_RESERVED25         (PNX8550_INT_GIC_MIN+25)
+#define PNX8550_INT_2D_DRAW_ENG        (PNX8550_INT_GIC_MIN+26)
+#define PNX8550_INT_MEM_BASED_SCALAR1  (PNX8550_INT_GIC_MIN+27)
+#define PNX8550_INT_VIDEO_MPEG         (PNX8550_INT_GIC_MIN+28)
+#define PNX8550_INT_VIDEO_INPUT_P1     (PNX8550_INT_GIC_MIN+29)
+
+#define PNX8550_INT_VIDEO_INPUT_P2     (PNX8550_INT_GIC_MIN+30)
+#define PNX8550_INT_SPDI1              (PNX8550_INT_GIC_MIN+31)
+#define PNX8550_INT_SPDO               (PNX8550_INT_GIC_MIN+32)
+#define PNX8550_INT_AUDIO_INPUT1       (PNX8550_INT_GIC_MIN+33)
+#define PNX8550_INT_AUDIO_OUTPUT1      (PNX8550_INT_GIC_MIN+34)
+#define PNX8550_INT_AUDIO_INPUT2       (PNX8550_INT_GIC_MIN+35)
+#define PNX8550_INT_AUDIO_OUTPUT2      (PNX8550_INT_GIC_MIN+36)
+#define PNX8550_INT_MEMBASED_SCALAR2   (PNX8550_INT_GIC_MIN+37)
+#define PNX8550_INT_VPK                (PNX8550_INT_GIC_MIN+38)
+#define PNX8550_INT_MPEG1_MIPS         (PNX8550_INT_GIC_MIN+39)
+
+#define PNX8550_INT_MPEG1_TM           (PNX8550_INT_GIC_MIN+40)
+#define PNX8550_INT_MPEG2_MIPS         (PNX8550_INT_GIC_MIN+41)
+#define PNX8550_INT_MPEG2_TM           (PNX8550_INT_GIC_MIN+42)
+#define PNX8550_INT_TS_DMA             (PNX8550_INT_GIC_MIN+43)
+#define PNX8550_INT_EDMA               (PNX8550_INT_GIC_MIN+44)
+#define PNX8550_INT_TM_DEBUG1          (PNX8550_INT_GIC_MIN+45)
+#define PNX8550_INT_TM_DEBUG2          (PNX8550_INT_GIC_MIN+46)
+#define PNX8550_INT_PCI_INTA           (PNX8550_INT_GIC_MIN+47)
+#define PNX8550_INT_CLOCK_MODULE       (PNX8550_INT_GIC_MIN+48)
+#define PNX8550_INT_PCI_XIO_INTA_PCI   (PNX8550_INT_GIC_MIN+49)
+
+#define PNX8550_INT_PCI_XIO_INTB_DMA   (PNX8550_INT_GIC_MIN+50)
+#define PNX8550_INT_PCI_XIO_INTC_GPPM  (PNX8550_INT_GIC_MIN+51)
+#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
+#define PNX8550_INT_DVD_CSS            (PNX8550_INT_GIC_MIN+53)
+#define PNX8550_INT_VLD                (PNX8550_INT_GIC_MIN+54)
+#define PNX8550_INT_GPIO_TSU_7_0       (PNX8550_INT_GIC_MIN+55)
+#define PNX8550_INT_GPIO_TSU_15_8      (PNX8550_INT_GIC_MIN+56)
+#define PNX8550_INT_GPIO_CTU_IR        (PNX8550_INT_GIC_MIN+57)
+#define PNX8550_INT_GPIO0              (PNX8550_INT_GIC_MIN+58)
+#define PNX8550_INT_GPIO1              (PNX8550_INT_GIC_MIN+59)
+
+#define PNX8550_INT_GPIO2              (PNX8550_INT_GIC_MIN+60)
+#define PNX8550_INT_GPIO3              (PNX8550_INT_GIC_MIN+61)
+#define PNX8550_INT_GPIO4              (PNX8550_INT_GIC_MIN+62)
+#define PNX8550_INT_GPIO5              (PNX8550_INT_GIC_MIN+63)
+#define PNX8550_INT_GPIO6              (PNX8550_INT_GIC_MIN+64)
+#define PNX8550_INT_GPIO7              (PNX8550_INT_GIC_MIN+65)
+#define PNX8550_INT_PMAN_SECURITY      (PNX8550_INT_GIC_MIN+66)
+#define PNX8550_INT_I2C3               (PNX8550_INT_GIC_MIN+67)
+#define PNX8550_INT_RESERVED_68        (PNX8550_INT_GIC_MIN+68)
+#define PNX8550_INT_SPDI2              (PNX8550_INT_GIC_MIN+69)
+
+#define PNX8550_INT_I2C4               (PNX8550_INT_GIC_MIN+70)
+
+// Timer are 3 exceptions connected to cp0's 7th hardware exception
+#define PNX8550_INT_TIMER_TOTINT       3
+#define PNX8550_INT_TIMER_MIN          (PNX8550_INT_GIC_MAX+1)
+#define PNX8550_INT_TIMER_MAX          (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
+
+#define PNX8550_INT_TIMER1             (PNX8550_INT_TIMER_MIN+0)
+#define PNX8550_INT_TIMER2             (PNX8550_INT_TIMER_MIN+1)
+#define PNX8550_INT_TIMER3             (PNX8550_INT_TIMER_MIN+2)
+#define PNX8550_INT_WATCHDOG           PNX8550_INT_TIMER3
+
+#endif
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
new file mode 100644
index 000000000000..57102fa9da51
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -0,0 +1,262 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ */
+#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_KERNEL_ENTRY_INIT_H
+
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+
+#define CO_CONFIGPR_VALID  0x3F1F41FF    /* valid bits to write to ConfigPR */
+#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
+#define CACHE_OPC      0xBC000000  /* MIPS cache instruction opcode */
+#define ICACHE_LINE_SIZE        32      /* Instruction cache line size bytes */
+#define DCACHE_LINE_SIZE        32      /* Data cache line size in bytes */
+
+#define ICACHE_SET_COUNT        256     /* Instruction cache set count */
+#define DCACHE_SET_COUNT        128     /* Data cache set count */
+
+#define ICACHE_SET_SIZE         (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
+#define DCACHE_SET_SIZE         (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
+
+        .macro  kernel_entry_setup
+        .set    push
+        .set    noreorder
+        /*
+         * PNX8550 entry point, when running a non compressed
+         * kernel. When loading a zImage, the head.S code in
+         * arch/mips/zboot/pnx8550 will init the caches and,
+         * decompress the kernel, and branch to kernel_entry.
+                 */
+cache_begin:    li      t0, (1<<28)
+        mtc0    t0, CP0_STATUS /* cp0 usable */
+        HAZARD_CP0
+
+        mtc0    zero, CP0_CAUSE
+        HAZARD_CP0
+
+
+        /* Set static virtual to phys address translation and TLB disabled */
+        mfc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+
+        and t0,~((1<<19) | (1<<20))     /* TLB/MAP cleared */
+        mtc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+
+        /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
+
+        init_icache
+        nop
+        init_dcache
+        nop
+
+        cachePr4450ICReset
+        nop
+
+        cachePr4450DCReset
+        nop
+
+        /* read ConfigPR into t0 */
+        mfc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+
+        /*  enable the TLB */
+        or      t0, (1<<19)
+
+        /* disable the ICACHE: at least 10x slower */
+        /* or      t0, (1<<26) */
+
+        /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set  */
+        /* or      t0, (1<<27) */
+
+        and     t0, CO_CONFIGPR_VALID
+
+        /* enable TLB. */
+        mtc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+cache_end:
+        /* Setup CMEM_0 to MMIO address space, 2MB */
+        lui    t0, 0x1BE0
+        addi   t0, t0, 0x3
+        mtc0   $8, $22, 4
+        nop
+
+        /* Setup CMEM_1, 128MB */
+        lui    t0, 0x1000
+        addi   t0, t0, 0xf
+        mtc0   $8, $22, 5
+        nop
+
+
+        /* Setup CMEM_2, 32MB */
+        lui    t0, 0x1C00
+        addi   t0, t0, 0xb
+        mtc0   $8, $22, 6
+        nop
+
+        /* Setup CMEM_3, 0MB */
+        lui    t0, 0x0
+        addi   t0, t0, 0x0
+        mtc0   $8, $22, 7
+        nop
+
+        /* Enable cache */
+        mfc0    t0, CP0_CONFIG
+        HAZARD_CP0
+        and     t0, t0, 0xFFFFFFF8
+        or      t0, t0, 3
+        mtc0    t0, CP0_CONFIG
+        HAZARD_CP0
+        .set    pop
+        .endm
+
+        .macro  init_icache
+        .set    push
+        .set    noreorder
+
+        /* Get Cache Configuration */
+        mfc0    t3, CP0_CONFIG, 1
+        HAZARD_CP0
+
+        /* get cache Line size */
+
+        srl   t1, t3, 19   /* C0_CONFIGPR_IL_SHIFT */
+        andi  t1, t1, 0x7  /* C0_CONFIGPR_IL_MASK */
+        beq   t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
+        nop
+        addiu t0, t1, 1
+        ori   t1, zero, 1
+        sllv  t1, t1, t0
+
+        /* get max cache Index */
+        srl   t2, t3, 22  /* C0_CONFIGPR_IS_SHIFT */
+        andi  t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
+        addiu t0, t2, 6
+        ori   t2, zero, 1
+        sllv  t2, t2, t0
+
+        /* get max cache way */
+        srl   t3, t3, 16  /* C0_CONFIGPR_IA_SHIFT */
+        andi  t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
+        addiu t3, t3, 1
+
+        /* total no of cache lines */
+        multu t2, t3             /* max index * max way */
+        mflo  t2
+        addiu t2, t2, -1
+
+        move  t0, zero
+pr4450_next_instruction_cache_set:
+        cache  Index_Invalidate_I, 0(t0)
+        addu  t0, t0, t1         /* add bytes in a line */
+        bne   t2, zero, pr4450_next_instruction_cache_set
+        addiu t2, t2, -1   /* reduce no of lines to invalidate by one */
+pr4450_instr_cache_invalidated:
+        .set    pop
+        .endm
+
+        .macro  init_dcache
+        .set    push
+        .set    noreorder
+        move t1, zero
+
+        /* Store Tag Information */
+        mtc0    zero, CP0_TAGLO, 0
+        HAZARD_CP0
+
+        mtc0    zero, CP0_TAGHI, 0
+        HAZARD_CP0
+
+        /* Cache size is 16384 = 512 lines x 32 bytes per line */
+        or       t2, zero, (128*4)-1  /* 512 lines  */
+        /* Invalidate all lines */
+2:
+        cache Index_Store_Tag_D, 0(t1)
+        addiu    t2, t2, -1
+        bne      t2, zero, 2b
+        addiu    t1, t1, 32        /* 32 bytes in a line */
+        .set pop
+        .endm
+
+        .macro  cachePr4450ICReset
+        .set    push
+        .set    noreorder
+
+        /* Save CP0 status reg on entry; */
+        /* disable interrupts during cache reset */
+        mfc0    t0, CP0_STATUS      /* T0 = interrupt status on entry */
+        HAZARD_CP0
+
+        mtc0    zero, CP0_STATUS   /* disable CPU interrupts */
+        HAZARD_CP0
+
+        or      t1, zero, zero              /* T1 = starting cache index (0) */
+        ori     t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
+
+        icache_invd_loop:
+        /* 9 == register t1 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+                (0 * ICACHE_SET_SIZE))  /* invalidate inst cache WAY0 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+                (1 * ICACHE_SET_SIZE))  /* invalidate inst cache WAY1 */
+
+        addiu   t1, t1, ICACHE_LINE_SIZE    /* T1 = next cache line index */
+        bne     t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
+        addiu   t2, t2, -1        /* decrement T2 set cnt (delay slot) */
+
+        /* Initialize the latches in the instruction cache tag */
+        /* that drive the way selection tri-state bus drivers, by doing a */
+        /* dummy load while the instruction cache is still disabled. */
+        /* TODO: Is this needed ? */
+        la      t1, KSEG0            /* T1 = cached memory base address */
+        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
+
+        mtc0    t0, CP0_STATUS        /* restore interrupt status on entry */
+        HAZARD_CP0
+        .set    pop
+        .endm
+
+        .macro  cachePr4450DCReset
+        .set    push
+        .set    noreorder
+        mfc0    t0, CP0_STATUS           /* T0 = interrupt status on entry */
+        HAZARD_CP0
+        mtc0    zero, CP0_STATUS         /* disable CPU interrupts */
+        HAZARD_CP0
+
+        /* Writeback/invalidate entire data cache sets/ways/lines */
+        or      t1, zero, zero              /* T1 = starting cache index (0) */
+        ori     t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
+
+        dcache_wbinvd_loop:
+        /* 9 == register t1 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (0 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY0 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (1 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY1 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (2 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY2 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (3 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY3 */
+
+        addiu   t1, t1, DCACHE_LINE_SIZE  /* T1 = next data cache line index */
+        bne     t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
+        addiu   t2, t2, -1          /* decrement T2 set cnt (delay slot) */
+
+        /* Initialize the latches in the data cache tag that drive the way
+        selection tri-state bus drivers, by doing a dummy load while the
+        data cache is still in the disabled mode.  TODO: Is this needed ? */
+        la      t1, KSEG0            /* T1 = cached memory base address */
+        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
+
+        mtc0    t0, CP0_STATUS       /* restore interrupt status on entry */
+        HAZARD_CP0
+        .set    pop
+        .endm
+
+#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h
new file mode 100644
index 000000000000..aefbc514ab09
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/nand.h
@@ -0,0 +1,121 @@
+#ifndef __PNX8550_NAND_H
+#define __PNX8550_NAND_H
+
+#define PNX8550_NAND_BASE_ADDR   0x10000000
+#define PNX8550_PCIXIO_BASE      0xBBE40000
+
+#define PNX8550_DMA_EXT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
+#define PNX8550_DMA_INT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
+#define PNX8550_DMA_TRANS_SIZE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
+#define PNX8550_DMA_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
+#define PNX8550_XIO_SEL0         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
+#define PNX8550_GPXIO_ADDR       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
+#define PNX8550_GPXIO_WR         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
+#define PNX8550_GPXIO_RD         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
+#define PNX8550_GPXIO_CTRL       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
+#define PNX8550_XIO_FLASH_CTRL   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
+#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
+#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
+#define PNX8550_GPXIO_INT_CLEAR  *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
+#define PNX8550_DMA_INT_STATUS   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
+#define PNX8550_DMA_INT_ENABLE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
+#define PNX8550_DMA_INT_CLEAR    *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
+
+#define PNX8550_XIO_SEL0_EN_16BIT    0x00800000
+#define PNX8550_XIO_SEL0_USE_ACK     0x00400000
+#define PNX8550_XIO_SEL0_REN_HIGH    0x00100000
+#define PNX8550_XIO_SEL0_REN_LOW     0x00040000
+#define PNX8550_XIO_SEL0_WEN_HIGH    0x00010000
+#define PNX8550_XIO_SEL0_WEN_LOW     0x00004000
+#define PNX8550_XIO_SEL0_WAIT        0x00000200
+#define PNX8550_XIO_SEL0_OFFSET      0x00000020
+#define PNX8550_XIO_SEL0_TYPE_68360  0x00000000
+#define PNX8550_XIO_SEL0_TYPE_NOR    0x00000008
+#define PNX8550_XIO_SEL0_TYPE_NAND   0x00000010
+#define PNX8550_XIO_SEL0_TYPE_IDE    0x00000018
+#define PNX8550_XIO_SEL0_SIZE_8MB    0x00000000
+#define PNX8550_XIO_SEL0_SIZE_16MB   0x00000002
+#define PNX8550_XIO_SEL0_SIZE_32MB   0x00000004
+#define PNX8550_XIO_SEL0_SIZE_64MB   0x00000006
+#define PNX8550_XIO_SEL0_ENAB        0x00000001
+
+#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT)  | \
+                              (PNX8550_XIO_SEL0_REN_HIGH*0)| \
+                              (PNX8550_XIO_SEL0_REN_LOW*2) | \
+                              (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
+                              (PNX8550_XIO_SEL0_WEN_LOW*2) | \
+                              (PNX8550_XIO_SEL0_WAIT*4)    | \
+                              (PNX8550_XIO_SEL0_OFFSET*0)  | \
+                              (PNX8550_XIO_SEL0_TYPE_NAND) | \
+                              (PNX8550_XIO_SEL0_SIZE_32MB) | \
+                              (PNX8550_XIO_SEL0_ENAB))
+
+#define PNX8550_GPXIO_PENDING        0x00000200
+#define PNX8550_GPXIO_DONE           0x00000100
+#define PNX8550_GPXIO_CLR_DONE       0x00000080
+#define PNX8550_GPXIO_INIT           0x00000040
+#define PNX8550_GPXIO_READ_CMD       0x00000010
+#define PNX8550_GPXIO_BEN            0x0000000F
+
+#define PNX8550_XIO_FLASH_64MB       0x00200000
+#define PNX8550_XIO_FLASH_INC_DATA   0x00100000
+#define PNX8550_XIO_FLASH_CMD_PH     0x000C0000
+#define PNX8550_XIO_FLASH_CMD_PH2    0x00080000
+#define PNX8550_XIO_FLASH_CMD_PH1    0x00040000
+#define PNX8550_XIO_FLASH_CMD_PH0    0x00000000
+#define PNX8550_XIO_FLASH_ADR_PH     0x00030000
+#define PNX8550_XIO_FLASH_ADR_PH3    0x00030000
+#define PNX8550_XIO_FLASH_ADR_PH2    0x00020000
+#define PNX8550_XIO_FLASH_ADR_PH1    0x00010000
+#define PNX8550_XIO_FLASH_ADR_PH0    0x00000000
+#define PNX8550_XIO_FLASH_CMD_B(x)   ((x<<8) & 0x0000FF00)
+#define PNX8550_XIO_FLASH_CMD_A(x)   (x & 0x000000FF)
+
+#define PNX8550_XIO_INT_ACK          0x00004000
+#define PNX8550_XIO_INT_COMPL        0x00002000
+#define PNX8550_XIO_INT_NONSUP       0x00000200
+#define PNX8550_XIO_INT_ABORT        0x00000004
+
+#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
+#define PNX8550_DMA_CTRL_SND2XIO     0x00000200
+#define PNX8550_DMA_CTRL_FIX_ADDR    0x00000100
+#define PNX8550_DMA_CTRL_BURST_8     0x00000000
+#define PNX8550_DMA_CTRL_BURST_16    0x00000020
+#define PNX8550_DMA_CTRL_BURST_32    0x00000040
+#define PNX8550_DMA_CTRL_BURST_64    0x00000060
+#define PNX8550_DMA_CTRL_BURST_128   0x00000080
+#define PNX8550_DMA_CTRL_BURST_256   0x000000A0
+#define PNX8550_DMA_CTRL_BURST_512   0x000000C0
+#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
+#define PNX8550_DMA_CTRL_INIT_DMA    0x00000010
+#define PNX8550_DMA_CTRL_CMD_TYPE    0x0000000F
+
+/* see PCI system arch, page 100 for the full list: */
+#define PNX8550_DMA_CTRL_PCI_CMD_READ    0x00000006
+#define PNX8550_DMA_CTRL_PCI_CMD_WRITE   0x00000007
+
+#define PNX8550_DMA_INT_STAT_ACK_DONE   (1<<14)
+#define PNX8550_DMA_INT_STAT_DMA_DONE   (1<<12)
+#define PNX8550_DMA_INT_STAT_DMA_ERR    (1<<9)
+#define PNX8550_DMA_INT_STAT_PERR5      (1<<5)
+#define PNX8550_DMA_INT_STAT_PERR4      (1<<4)
+#define PNX8550_DMA_INT_STAT_M_ABORT    (1<<2)
+#define PNX8550_DMA_INT_STAT_T_ABORT    (1<<1)
+
+#define PNX8550_DMA_INT_EN_ACK_DONE     (1<<14)
+#define PNX8550_DMA_INT_EN_DMA_DONE     (1<<12)
+#define PNX8550_DMA_INT_EN_DMA_ERR      (1<<9)
+#define PNX8550_DMA_INT_EN_PERR5        (1<<5)
+#define PNX8550_DMA_INT_EN_PERR4        (1<<4)
+#define PNX8550_DMA_INT_EN_M_ABORT      (1<<2)
+#define PNX8550_DMA_INT_EN_T_ABORT      (1<<1)
+
+#define PNX8550_DMA_INT_CLR_ACK_DONE    (1<<14)
+#define PNX8550_DMA_INT_CLR_DMA_DONE    (1<<12)
+#define PNX8550_DMA_INT_CLR_DMA_ERR     (1<<9)
+#define PNX8550_DMA_INT_CLR_PERR5       (1<<5)
+#define PNX8550_DMA_INT_CLR_PERR4       (1<<4)
+#define PNX8550_DMA_INT_CLR_M_ABORT     (1<<2)
+#define PNX8550_DMA_INT_CLR_T_ABORT     (1<<1)
+
+#endif
diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h
new file mode 100644
index 000000000000..b921508d701b
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/pci.h
@@ -0,0 +1,185 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_PCI_H
+#define __PNX8550_PCI_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define PCI_CMD_IOR                     0x20
+#define PCI_CMD_IOW                     0x30
+#define PCI_CMD_CONFIG_READ             0xa0
+#define PCI_CMD_CONFIG_WRITE            0xb0
+
+#define PCI_IO_TIMEOUT                  1000
+#define PCI_IO_RETRY                    5
+/* Timeout for IO and CFG accesses.
+   This is in 1/1024 th of a jiffie(=10ms)
+   i.e. approx 10us */
+#define PCI_IO_JIFFIES_TIMEOUT          40
+#define PCI_IO_JIFFIES_SHIFT            10
+
+#define PCI_BYTE_ENABLE_MASK            0x0000000f
+#define PCI_CFG_BUS_SHIFT               16
+#define PCI_CFG_FUNC_SHIFT              8
+#define PCI_CFG_REG_SHIFT               2
+
+#define PCI_BASE                  0x1be00000
+#define PCI_SETUP                 0x00040010
+#define PCI_DIS_REQGNT           (1<<30)
+#define PCI_DIS_REQGNTA          (1<<29)
+#define PCI_DIS_REQGNTB          (1<<28)
+#define PCI_D2_SUPPORT           (1<<27)
+#define PCI_D1_SUPPORT           (1<<26)
+#define PCI_EN_TA                (1<<24)
+#define PCI_EN_PCI2MMI           (1<<23)
+#define PCI_EN_XIO               (1<<22)
+#define PCI_BASE18_PREF          (1<<21)
+#define SIZE_16M                 0x3
+#define SIZE_32M                 0x4
+#define SIZE_64M                 0x5
+#define SIZE_128M                0x6
+#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
+#define PCI_SETUP_BASE18_EN      (1<<17)
+#define PCI_SETUP_BASE14_PREF    (1<<16)
+#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
+#define PCI_SETUP_BASE14_EN      (1<<11)
+#define PCI_SETUP_BASE10_PREF    (1<<10)
+#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
+#define PCI_SETUP_CFGMANAGE_EN   (1<<1)
+#define PCI_SETUP_PCIARB_EN      (1<<0)
+
+#define PCI_CTRL                  0x040014
+#define PCI_SWPB_DCS_PCI         (1<<16)
+#define PCI_SWPB_PCI_PCI         (1<<15)
+#define PCI_SWPB_PCI_DCS         (1<<14)
+#define PCI_REG_WR_POST          (1<<13)
+#define PCI_XIO_WR_POST          (1<<12)
+#define PCI_PCI2_WR_POST         (1<<13)
+#define PCI_PCI1_WR_POST         (1<<12)
+#define PCI_SERR_SEEN            (1<<11)
+#define PCI_B10_SPEC_RD          (1<<6)
+#define PCI_B14_SPEC_RD          (1<<5)
+#define PCI_B18_SPEC_RD          (1<<4)
+#define PCI_B10_NOSUBWORD        (1<<3)
+#define PCI_B14_NOSUBWORD        (1<<2)
+#define PCI_B18_NOSUBWORD        (1<<1)
+#define PCI_RETRY_TMREN          (1<<0)
+
+#define PCI_BASE1_LO              0x040018
+#define PCI_BASE1_HI              0x04001C
+#define PCI_BASE2_LO              0x040020
+#define PCI_BASE2_HI              0x040024
+#define PCI_RDLIFETIM             0x040028
+#define PCI_GPPM_ADDR             0x04002C
+#define PCI_GPPM_WDAT             0x040030
+#define PCI_GPPM_RDAT             0x040034
+#define PCI_GPPM_CTRL             0x040038
+#define GPPM_DONE                (1<<10)
+#define INIT_PCI_CYCLE           (1<<9)
+#define GPPM_CMD(X)              (((X)&0xf)<<4)
+#define GPPM_BYTEEN(X)           ((X)&0xf)
+#define PCI_UNLOCKREG             0x04003C
+#define UNLOCK_SSID(X)           (((X)&0xff)<<8)
+#define UNLOCK_SETUP(X)          (((X)&0xff)<<0)
+#define UNLOCK_MAGIC             0xCA
+#define PCI_DEV_VEND_ID           0x040040
+#define DEVICE_ID(X)             (((X)>>16)&0xffff)
+#define VENDOR_ID(X)             (((X)&0xffff))
+#define PCI_CFG_CMDSTAT           0x040044
+#define PCI_CFG_STATUS(X)            (((X)>>16)&0xffff)
+#define PCI_CFG_COMMAND(X)           ((X)&0xffff)
+#define PCI_CLASS_REV             0x040048
+#define PCI_CLASSCODE(X)         (((X)>>8)&0xffffff)
+#define PCI_REVID(X)             ((X)&0xff)
+#define PCI_LAT_TMR     0x04004c
+#define PCI_BASE10      0x040050
+#define PCI_BASE14      0x040054
+#define PCI_BASE18      0x040058
+#define PCI_SUBSYS_ID   0x04006c
+#define PCI_CAP_PTR     0x040074
+#define PCI_CFG_MISC    0x04007c
+#define PCI_PMC         0x040080
+#define PCI_PWR_STATE   0x040084
+#define PCI_IO          0x040088
+#define PCI_SLVTUNING   0x04008C
+#define PCI_DMATUNING   0x040090
+#define PCI_DMAEADDR    0x040800
+#define PCI_DMAIADDR    0x040804
+#define PCI_DMALEN      0x040808
+#define PCI_DMACTRL     0x04080C
+#define PCI_XIOCTRL     0x040810
+#define PCI_SEL0PROF    0x040814
+#define PCI_SEL1PROF    0x040818
+#define PCI_SEL2PROF    0x04081C
+#define PCI_GPXIOADDR   0x040820
+#define PCI_NANDCTRLS   0x400830
+#define PCI_SEL3PROF    0x040834
+#define PCI_SEL4PROF    0x040838
+#define PCI_GPXIO_STAT  0x040FB0
+#define PCI_GPXIO_IMASK 0x040FB4
+#define PCI_GPXIO_ICLR  0x040FB8
+#define PCI_GPXIO_ISET  0x040FBC
+#define PCI_GPPM_STATUS 0x040FC0
+#define GPPM_DONE      (1<<10)
+#define GPPM_ERR       (1<<9)
+#define GPPM_MPAR_ERR  (1<<8)
+#define GPPM_PAR_ERR   (1<<7)
+#define GPPM_R_MABORT  (1<<2)
+#define GPPM_R_TABORT  (1<<1)
+#define PCI_GPPM_IMASK  0x040FC4
+#define PCI_GPPM_ICLR   0x040FC8
+#define PCI_GPPM_ISET   0x040FCC
+#define PCI_DMA_STATUS  0x040FD0
+#define PCI_DMA_IMASK   0x040FD4
+#define PCI_DMA_ICLR    0x040FD8
+#define PCI_DMA_ISET    0x040FDC
+#define PCI_ISTATUS     0x040FE0
+#define PCI_IMASK       0x040FE4
+#define PCI_ICLR        0x040FE8
+#define PCI_ISET        0x040FEC
+#define PCI_MOD_ID      0x040FFC
+
+/*
+ *  PCI configuration cycle AD bus definition
+ */
+/* Type 0 */
+#define PCI_CFG_TYPE0_REG_SHF           0
+#define PCI_CFG_TYPE0_FUNC_SHF          8
+
+/* Type 1 */
+#define PCI_CFG_TYPE1_REG_SHF           0
+#define PCI_CFG_TYPE1_FUNC_SHF          8
+#define PCI_CFG_TYPE1_DEV_SHF           11
+#define PCI_CFG_TYPE1_BUS_SHF           16
+
+/*
+ *  Ethernet device DP83816 definition
+ */
+#define DP83816_IRQ_ETHER               66
+
+#endif
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
new file mode 100644
index 000000000000..e32b9a23d70e
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/uart.h
@@ -0,0 +1,16 @@
+#ifndef __IP3106_UART_H
+#define __IP3106_UART_H
+
+#include <int.h>
+
+/* early macros for kgdb use. fixme: clean this up */
+
+#define UART_BASE               0xbbe4a000      /* PNX8550 */
+
+#define PNX8550_UART_PORT0      (UART_BASE)
+#define PNX8550_UART_PORT1      (UART_BASE + 0x1000)
+
+#define PNX8550_UART_INT(x)             (PNX8550_INT_GIC_MIN+19+x)
+#define IRQ_TO_UART(x)                  (x-PNX8550_INT_GIC_MIN-19)
+
+#endif
diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h
new file mode 100644
index 000000000000..483b7fc65d41
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/usb.h
@@ -0,0 +1,32 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *  USB specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_USB_H
+#define __PNX8550_USB_H
+
+/*
+ * USB Host controller
+ */
+
+#define PNX8550_USB_OHCI_OP_BASE        0x1be48000
+#define PNX8550_USB_OHCI_OP_LEN         0x1000
+
+#endif
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
index f48736032b2a..79f9b064c864 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -14,7 +14,7 @@
 
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_4ktlb           1
+#define cpu_has_4kcache         1
 #define cpu_has_fpu             1
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
@@ -31,6 +31,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
index a3a2cc6014b2..193a666cd131 100644
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     1
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 
 #define cpu_has_nofpuex         0
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h
new file mode 100644
index 000000000000..cadbe8eda79c
--- /dev/null
+++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h
@@ -0,0 +1,66 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ */
+#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/config.h>
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4kcache         1
+#define cpu_has_fpu             0
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4kcache         1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 58603e3daca6..463d051f4683 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 
 #define cpu_has_nofpuex         0
@@ -36,10 +37,4 @@
 #define cpu_icache_line_size()  32
 #define cpu_scache_line_size()  32
 
-/*
- * On the RM9000 we need to ensure that I-cache lines being fetches only
- * contain valid instructions are funny things will happen.
- */
-#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
-
 #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 65d1d16eab16..25b6ffc26623 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -66,6 +66,7 @@
 #define MIPS_REVISION_CORID_CORE_EMUL      6
 #define MIPS_REVISION_CORID_CORE_FPGA2     7
 #define MIPS_REVISION_CORID_CORE_FPGAR2    8
+#define MIPS_REVISION_CORID_CORE_FPGA3     9
 
 /**** Artificial corid defines ****/
 /*
@@ -79,4 +80,10 @@
 
 extern unsigned int mips_revision_corid;
 
+#ifdef CONFIG_PCI
+extern void mips_pcibios_init(void);
+#else
+#define mips_pcibios_init() do { } while (0)
+#endif
+
 #endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 376181882e81..da6cc2fbbc78 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -25,9 +25,63 @@
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 
-/* Number of IRQ supported on hw interrupt 0. */
-#define MALTAINT_END      16
+/*
+ * Interrupts 0..15 are used for Malta ISA compatible interrupts
+ */
+#define MALTA_INT_BASE          0
+
+/*
+ * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
+ */
+#define MIPSCPU_INT_BASE        16
+
+/* CPU interrupt offsets */
+#define MIPSCPU_INT_SW0         0
+#define MIPSCPU_INT_SW1         1
+#define MIPSCPU_INT_MB0         2
+#define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
+#define MIPSCPU_INT_MB1         3
+#define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
+#define MIPSCPU_INT_MB2         4
+#define MIPSCPU_INT_MB3         5
+#define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
+#define MIPSCPU_INT_MB4         6
+#define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
+#define MIPSCPU_INT_CPUCTR      7
+
+/*
+ * Interrupts 64..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE         64
+
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR          0
+#define MSC01C_INT_PCI          1
+
+/*
+ * Interrupts 64..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE         64
+
+/* SOC-it EIC interrupt offsets */
+#define MSC01E_INT_SW0          1
+#define MSC01E_INT_SW1          2
+#define MSC01E_INT_MB0          3
+#define MSC01E_INT_I8259A       MSC01E_INT_MB0
+#define MSC01E_INT_MB1          4
+#define MSC01E_INT_SMI          MSC01E_INT_MB1
+#define MSC01E_INT_MB2          5
+#define MSC01E_INT_MB3          6
+#define MSC01E_INT_COREHI       MSC01E_INT_MB3
+#define MSC01E_INT_MB4          7
+#define MSC01E_INT_CORELO       MSC01E_INT_MB4
+#define MSC01E_INT_TMR          8
+#define MSC01E_INT_PCI          9
+#define MSC01E_INT_PERFCTR      10
+#define MSC01E_INT_CPUCTR       11
 
+#ifndef __ASSEMBLY__
 extern void maltaint_init(void);
+#endif
 
 #endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 6b2a87a38f4b..8eaefb837b9d 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -1,8 +1,9 @@
 /*
  * PCI Register definitions for the MIPS System Controller.
  *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -29,22 +30,22 @@
 #define MSC01_PCI_CFGADDR_OFS           0x0610
 #define MSC01_PCI_CFGDATA_OFS           0x0618
 #define MSC01_PCI_IACK_OFS              0x0620
-#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
-#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
-#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
-#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
-#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
-#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
-#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
-#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
-#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
-#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
-#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
-#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
-#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
-#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
-#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
-#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
+#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
+#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
+#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
+#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
+#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
+#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
+#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
+#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
+#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
+#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
+#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
+#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
+#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
+#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
+#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
+#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
 #define MSC01_PCI_BAR0_OFS              0x2220
 #define MSC01_PCI_CFG_OFS               0x2380
 #define MSC01_PCI_SWAP_OFS              0x2388
@@ -86,73 +87,73 @@
 #define MSC01_PCI_P2SCMAPL_MAP_SHF      24
 #define MSC01_PCI_P2SCMAPL_MAP_MSK      0xff000000
 
-#define MSC01_PCI_INTCFG_RST_SHF        10
-#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
-#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
-#define MSC01_PCI_INTCFG_MWE_SHF        9
-#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
-#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
-#define MSC01_PCI_INTCFG_DTO_SHF        8
-#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
-#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
-#define MSC01_PCI_INTCFG_MA_SHF         7
-#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
-#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
-#define MSC01_PCI_INTCFG_TA_SHF         6
-#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
-#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
-#define MSC01_PCI_INTCFG_RTY_SHF        5
-#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
-#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
-#define MSC01_PCI_INTCFG_MWP_SHF        4
-#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
-#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
-#define MSC01_PCI_INTCFG_MRP_SHF        3
-#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
-#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
-#define MSC01_PCI_INTCFG_SWP_SHF        2
-#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
-#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
-#define MSC01_PCI_INTCFG_SRP_SHF        1
-#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
-#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
-#define MSC01_PCI_INTCFG_SE_SHF         0
-#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
-#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
+#define MSC01_PCI_INTCFG_RST_SHF        10
+#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
+#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
+#define MSC01_PCI_INTCFG_MWE_SHF        9
+#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
+#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
+#define MSC01_PCI_INTCFG_DTO_SHF        8
+#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
+#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
+#define MSC01_PCI_INTCFG_MA_SHF         7
+#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
+#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
+#define MSC01_PCI_INTCFG_TA_SHF         6
+#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
+#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
+#define MSC01_PCI_INTCFG_RTY_SHF        5
+#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
+#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
+#define MSC01_PCI_INTCFG_MWP_SHF        4
+#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
+#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
+#define MSC01_PCI_INTCFG_MRP_SHF        3
+#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
+#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
+#define MSC01_PCI_INTCFG_SWP_SHF        2
+#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
+#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
+#define MSC01_PCI_INTCFG_SRP_SHF        1
+#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
+#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
+#define MSC01_PCI_INTCFG_SE_SHF         0
+#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
+#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
 
-#define MSC01_PCI_INTSTAT_RST_SHF       10
-#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
-#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
-#define MSC01_PCI_INTSTAT_MWE_SHF       9
-#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
-#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
-#define MSC01_PCI_INTSTAT_DTO_SHF       8
-#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
-#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
-#define MSC01_PCI_INTSTAT_MA_SHF        7
-#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
-#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
-#define MSC01_PCI_INTSTAT_TA_SHF        6
-#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
-#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
-#define MSC01_PCI_INTSTAT_RTY_SHF       5
-#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
-#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
-#define MSC01_PCI_INTSTAT_MWP_SHF       4
-#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
-#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
-#define MSC01_PCI_INTSTAT_MRP_SHF       3
-#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
-#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
-#define MSC01_PCI_INTSTAT_SWP_SHF       2
-#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
-#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
-#define MSC01_PCI_INTSTAT_SRP_SHF       1
-#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
-#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
-#define MSC01_PCI_INTSTAT_SE_SHF        0
-#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
-#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
+#define MSC01_PCI_INTSTAT_RST_SHF       10
+#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
+#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
+#define MSC01_PCI_INTSTAT_MWE_SHF       9
+#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
+#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
+#define MSC01_PCI_INTSTAT_DTO_SHF       8
+#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
+#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
+#define MSC01_PCI_INTSTAT_MA_SHF        7
+#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
+#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
+#define MSC01_PCI_INTSTAT_TA_SHF        6
+#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
+#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
+#define MSC01_PCI_INTSTAT_RTY_SHF       5
+#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
+#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
+#define MSC01_PCI_INTSTAT_MWP_SHF       4
+#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
+#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
+#define MSC01_PCI_INTSTAT_MRP_SHF       3
+#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
+#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
+#define MSC01_PCI_INTSTAT_SWP_SHF       2
+#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
+#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
+#define MSC01_PCI_INTSTAT_SRP_SHF       1
+#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
+#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
+#define MSC01_PCI_INTSTAT_SE_SHF        0
+#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
+#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
 
 #define MSC01_PCI_CFGADDR_BNUM_SHF      16
 #define MSC01_PCI_CFGADDR_BNUM_MSK      0x00ff0000
@@ -167,29 +168,29 @@
 #define MSC01_PCI_CFGDATA_DATA_MSK      0xffffffff
 
 /* The defines below are ONLY valid for a MEM bar! */
-#define MSC01_PCI_BAR0_SIZE_SHF         4
-#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
-#define MSC01_PCI_BAR0_P_SHF            3
-#define MSC01_PCI_BAR0_P_MSK            0x00000008
-#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
-#define MSC01_PCI_BAR0_D_SHF            1
-#define MSC01_PCI_BAR0_D_MSK            0x00000006
-#define MSC01_PCI_BAR0_T_SHF            0
-#define MSC01_PCI_BAR0_T_MSK            0x00000001
-#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
+#define MSC01_PCI_BAR0_SIZE_SHF         4
+#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
+#define MSC01_PCI_BAR0_P_SHF            3
+#define MSC01_PCI_BAR0_P_MSK            0x00000008
+#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
+#define MSC01_PCI_BAR0_D_SHF            1
+#define MSC01_PCI_BAR0_D_MSK            0x00000006
+#define MSC01_PCI_BAR0_T_SHF            0
+#define MSC01_PCI_BAR0_T_MSK            0x00000001
+#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
 
 
-#define MSC01_PCI_CFG_RA_SHF            17
-#define MSC01_PCI_CFG_RA_MSK            0x00020000
-#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
-#define MSC01_PCI_CFG_G_SHF             16
-#define MSC01_PCI_CFG_G_MSK             0x00010000
-#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
-#define MSC01_PCI_CFG_EN_SHF            15
-#define MSC01_PCI_CFG_EN_MSK            0x00008000
-#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
-#define MSC01_PCI_CFG_MAXRTRY_SHF       0
-#define MSC01_PCI_CFG_MAXRTRY_MSK       0x000000ff
+#define MSC01_PCI_CFG_RA_SHF            17
+#define MSC01_PCI_CFG_RA_MSK            0x00020000
+#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
+#define MSC01_PCI_CFG_G_SHF             16
+#define MSC01_PCI_CFG_G_MSK             0x00010000
+#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
+#define MSC01_PCI_CFG_EN_SHF            15
+#define MSC01_PCI_CFG_EN_MSK            0x00008000
+#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
+#define MSC01_PCI_CFG_MAXRTRY_SHF       0
+#define MSC01_PCI_CFG_MAXRTRY_MSK       0x00000fff
 
 #define MSC01_PCI_SWAP_IO_SHF           18
 #define MSC01_PCI_SWAP_IO_MSK           0x000c0000
@@ -206,7 +207,7 @@
  * FIXME - are these macros specific to Malta and co or to the MSC?  If the
  * latter, they should be moved elsewhere.
  */
-#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
+#define MIPS_MSC01_PCI_REG_BASE         0x1bd00000
 
 extern unsigned long _pcictrl_msc;
 
@@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc;
  * Registers absolute addresses
  */
 
-#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
-#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
-#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
-#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
-#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
-#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
-#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
-#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
-#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
-#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
-#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
-#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
-#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
+#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
+#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
+#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
+#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
+#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
+#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
+#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
+#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
+#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
+#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
+#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
+#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
+#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
 #define MSC01_PCI_IACK          (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
 #define MSC01_PCI_HEAD0         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
 #define MSC01_PCI_HEAD1         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
@@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc;
 #define MSC01_PCI_HEAD12        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_HEAD13        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_HEAD14        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_BAR0          (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
 #define MSC01_PCI_CFG           (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
 #define MSC01_PCI_SWAP          (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
new file mode 100644
index 000000000000..acb7c2331d98
--- /dev/null
+++ b/include/asm-mips/mips-boards/sim.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#ifndef _ASM_MIPS_BOARDS_SIM_H
+#define _ASM_MIPS_BOARDS_SIM_H
+
+#define STATS_ON        1
+#define STATS_OFF       2
+#define STATS_CLEAR     3
+#define STATS_DUMP      4
+#define TRACE_ON                5
+#define TRACE_OFF       6
+
+
+#define simcfg(code)                                            \
+({                                         \
+        __asm__  __volatile__( \
+        "sltiu $0,$0, %0" \
+                ::"i"(code)                                     \
+                ); \
+})
+
+
+
+#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
new file mode 100644
index 000000000000..4952e0b3bf11
--- /dev/null
+++ b/include/asm-mips/mips-boards/simint.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _MIPS_SIMINT_H
+#define _MIPS_SIMINT_H
+
+
+#define SIM_INT_BASE            0
+#define MIPSCPU_INT_MB0         2
+#define MIPSCPU_INT_BASE        16
+#define MIPS_CPU_TIMER_IRQ      7
+
+
+#define MIPSCPU_INT_CPUCTR      7
+
+#define MSC01E_INT_BASE         64
+
+#define MIPSCPU_INT_CPUCTR      7
+#define MSC01E_INT_CPUCTR       11
+
+#endif
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
new file mode 100644
index 000000000000..a669c0702c66
--- /dev/null
+++ b/include/asm-mips/mipsmtregs.h
@@ -0,0 +1,391 @@
+/*
+ * MT regs definitions, follows on from mipsregs.h
+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Elizabeth Clarke et. al.
+ *
+ */
+#ifndef _ASM_MIPSMTREGS_H
+#define _ASM_MIPSMTREGS_H
+
+#include <asm/mipsregs.h>
+#include <asm/war.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * C macros
+ */
+
+#define read_c0_mvpcontrol()            __read_32bit_c0_register($0, 1)
+#define write_c0_mvpcontrol(val)        __write_32bit_c0_register($0, 1, val)
+
+#define read_c0_mvpconf0()              __read_32bit_c0_register($0, 2)
+#define read_c0_mvpconf1()              __read_32bit_c0_register($0, 3)
+
+#define read_c0_vpecontrol()            __read_32bit_c0_register($1, 1)
+#define write_c0_vpecontrol(val)        __write_32bit_c0_register($1, 1, val)
+
+#define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
+#define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
+
+#define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
+#define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
+
+#define read_c0_tcbind()                __read_32bit_c0_register($2, 2)
+
+#define read_c0_tccontext()             __read_32bit_c0_register($2, 5)
+#define write_c0_tccontext(val)         __write_32bit_c0_register($2, 5, val)
+
+#else /* Assembly */
+/*
+ * Macros for use in assembly language code
+ */
+
+#define CP0_MVPCONTROL          $0,1
+#define CP0_MVPCONF0            $0,2
+#define CP0_MVPCONF1            $0,3
+#define CP0_VPECONTROL          $1,1
+#define CP0_VPECONF0            $1,2
+#define CP0_VPECONF1            $1,3
+#define CP0_YQMASK              $1,4
+#define CP0_VPESCHEDULE $1,5
+#define CP0_VPESCHEFBK          $1,6
+#define CP0_TCSTATUS            $2,1
+#define CP0_TCBIND              $2,2
+#define CP0_TCRESTART           $2,3
+#define CP0_TCHALT              $2,4
+#define CP0_TCCONTEXT           $2,5
+#define CP0_TCSCHEDULE          $2,6
+#define CP0_TCSCHEFBK           $2,7
+#define CP0_SRSCONF0            $6,1
+#define CP0_SRSCONF1            $6,2
+#define CP0_SRSCONF2            $6,3
+#define CP0_SRSCONF3            $6,4
+#define CP0_SRSCONF4            $6,5
+
+#endif
+
+/* MVPControl fields */
+#define MVPCONTROL_EVP          (_ULCAST_(1))
+
+#define MVPCONTROL_VPC_SHIFT    1
+#define MVPCONTROL_VPC          (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
+
+#define MVPCONTROL_STLB_SHIFT   2
+#define MVPCONTROL_STLB         (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
+
+
+/* MVPConf0 fields */
+#define MVPCONF0_PTC_SHIFT      0
+#define MVPCONF0_PTC            ( _ULCAST_(0xff))
+#define MVPCONF0_PVPE_SHIFT     10
+#define MVPCONF0_PVPE           ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
+#define MVPCONF0_TCA_SHIFT      15
+#define MVPCONF0_TCA            ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
+#define MVPCONF0_PTLBE_SHIFT    16
+#define MVPCONF0_PTLBE          (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
+#define MVPCONF0_TLBS_SHIFT     29
+#define MVPCONF0_TLBS           (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
+#define MVPCONF0_M_SHIFT        31
+#define MVPCONF0_M              (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
+
+
+/* config3 fields */
+#define CONFIG3_MT_SHIFT        2
+#define CONFIG3_MT              (_ULCAST_(1) << CONFIG3_MT_SHIFT)
+
+
+/* VPEControl fields (per VPE) */
+#define VPECONTROL_TARGTC       (_ULCAST_(0xff))
+
+#define VPECONTROL_TE_SHIFT     15
+#define VPECONTROL_TE           (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
+#define VPECONTROL_EXCPT_SHIFT  16
+#define VPECONTROL_EXCPT        (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
+
+/* Thread Exception Codes for EXCPT field */
+#define THREX_TU                0
+#define THREX_TO                1
+#define THREX_IYQ               2
+#define THREX_GSX               3
+#define THREX_YSCH              4
+#define THREX_GSSCH             5
+
+#define VPECONTROL_GSI_SHIFT    20
+#define VPECONTROL_GSI          (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
+#define VPECONTROL_YSI_SHIFT    21
+#define VPECONTROL_YSI          (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
+
+/* VPEConf0 fields (per VPE) */
+#define VPECONF0_VPA_SHIFT      0
+#define VPECONF0_VPA            (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
+#define VPECONF0_MVP_SHIFT      1
+#define VPECONF0_MVP            (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
+#define VPECONF0_XTC_SHIFT      21
+#define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
+
+/* TCStatus fields (per TC) */
+#define TCSTATUS_TASID          (_ULCAST_(0xff))
+#define TCSTATUS_IXMT_SHIFT     10
+#define TCSTATUS_IXMT           (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
+#define TCSTATUS_TKSU_SHIFT     11
+#define TCSTATUS_TKSU           (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
+#define TCSTATUS_A_SHIFT        13
+#define TCSTATUS_A              (_ULCAST_(1) << TCSTATUS_A_SHIFT)
+#define TCSTATUS_DA_SHIFT       15
+#define TCSTATUS_DA             (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
+#define TCSTATUS_DT_SHIFT       20
+#define TCSTATUS_DT             (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
+#define TCSTATUS_TDS_SHIFT      21
+#define TCSTATUS_TDS            (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
+#define TCSTATUS_TSST_SHIFT     22
+#define TCSTATUS_TSST           (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
+#define TCSTATUS_RNST_SHIFT     23
+#define TCSTATUS_RNST           (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
+/* Codes for RNST */
+#define TC_RUNNING              0
+#define TC_WAITING              1
+#define TC_YIELDING             2
+#define TC_GATED                3
+
+#define TCSTATUS_TMX_SHIFT      27
+#define TCSTATUS_TMX            (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
+/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
+
+/* TCBind */
+#define TCBIND_CURVPE_SHIFT     0
+#define TCBIND_CURVPE           (_ULCAST_(0xf))
+
+#define TCBIND_CURTC_SHIFT      21
+
+#define TCBIND_CURTC            (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
+
+/* TCHalt */
+#define TCHALT_H                (_ULCAST_(1))
+
+#ifndef __ASSEMBLY__
+
+extern void mips_mt_regdump(void);
+
+static inline unsigned int dvpe(void)
+{
+        int res = 0;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41610001              # dvpe $1               \n"
+        "       move    %0, $1                                          \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+static inline void __raw_evpe(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41600021              # evpe                  \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n");
+}
+
+/* Enable multiMT if previous suggested it should be.
+   EMT_ENABLE to force */
+
+#define EVPE_ENABLE MVPCONTROL_EVP
+
+static inline void evpe(int previous)
+{
+        if ((previous & MVPCONTROL_EVP))
+                __raw_evpe();
+}
+
+static inline unsigned int dmt(void)
+{
+        int res;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .set    noat                                            \n"
+        "       .word   0x41610BC1                      # dmt $1        \n"
+        "       ehb                                                     \n"
+        "       move    %0, $1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+static inline void __raw_emt(void)
+{
+        __asm__ __volatile__(
+        "       .set    noreorder                                       \n"
+        "       .set    mips32r2                                        \n"
+        "       emt                                                     \n"
+        "       ehb                                                     \n"
+        "       .set    mips0                                           \n"
+        "       .set    reorder");
+}
+
+/* enable multiVPE if previous suggested it should be.
+   EVPE_ENABLE to force */
+
+#define EMT_ENABLE VPECONTROL_TE
+
+static inline void emt(int previous)
+{
+        if ((previous & EMT_ENABLE))
+                __raw_emt();
+}
+
+static inline void ehb(void)
+{
+        __asm__ __volatile__(
+        "       .set    mips32r2                                \n"
+        "       ehb                                             \n"
+        "       .set    mips0                                   \n");
+}
+
+#define mftc0(rt,sel)                                                   \
+({                                                                      \
+         unsigned long  __res;                                          \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
+        "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mftgpr(rt)                                                      \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       mftgpr  %0," #rt "                              \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mftr(rt,u,sel)                                                  \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        ".set noat\n\t"                                                 \
+        "mftr\t%0, " #rt ", " #u ", " #sel "\n\t"                       \
+        ".set at\n\t"                                                   \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mttgpr(rd,v)                                                    \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttgpr $1, " #rd "                            \n"     \
+        "       .word   0x41810020 | (" #rd " << 11)            \n"     \
+        "       .set    pop                                     \n"     \
+        : : "r" (v));                                                   \
+} while (0)
+
+#define mttc0(rd,sel,v)                                                 \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttc0 %0," #rd ", " #sel "                    \n"     \
+        "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (v));                                                     \
+})
+
+
+#define mttr(rd,u,sel,v)                                                \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "mttr   %0," #rd ", " #u ", " #sel                              \
+        : : "r" (v));                                                   \
+})
+
+
+#define settc(tc)                                                       \
+do {                                                                    \
+        write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
+        ehb();                                                          \
+} while (0)
+
+
+/* you *must* set the target tc (settc) before trying to use these */
+#define read_vpe_c0_vpecontrol()        mftc0(1, 1)
+#define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
+#define read_vpe_c0_vpeconf0()          mftc0(1, 2)
+#define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
+#define read_vpe_c0_status()            mftc0(12, 0)
+#define write_vpe_c0_status(val)        mttc0(12, 0, val)
+#define read_vpe_c0_cause()             mftc0(13, 0)
+#define write_vpe_c0_cause(val)         mttc0(13, 0, val)
+#define read_vpe_c0_config()            mftc0(16, 0)
+#define write_vpe_c0_config(val)        mttc0(16, 0, val)
+#define read_vpe_c0_config1()           mftc0(16, 1)
+#define write_vpe_c0_config1(val)       mttc0(16, 1, val)
+#define read_vpe_c0_config7()           mftc0(16, 7)
+#define write_vpe_c0_config7(val)       mttc0(16, 7, val)
+#define read_vpe_c0_ebase()             mftc0(15,1)
+#define write_vpe_c0_ebase(val)         mttc0(15, 1, val)
+#define write_vpe_c0_compare(val)       mttc0(11, 0, val)
+
+
+/* TC */
+#define read_tc_c0_tcstatus()           mftc0(2, 1)
+#define write_tc_c0_tcstatus(val)       mttc0(2,1,val)
+#define read_tc_c0_tcbind()             mftc0(2, 2)
+#define write_tc_c0_tcbind(val)         mttc0(2,2,val)
+#define read_tc_c0_tcrestart()          mftc0(2, 3)
+#define write_tc_c0_tcrestart(val)      mttc0(2,3,val)
+#define read_tc_c0_tchalt()             mftc0(2, 4)
+#define write_tc_c0_tchalt(val)         mttc0(2,4,val)
+#define read_tc_c0_tccontext()          mftc0(2, 5)
+#define write_tc_c0_tccontext(val)      mttc0(2,5,val)
+
+/* GPR */
+#define read_tc_gpr_sp()                mftgpr(29)
+#define write_tc_gpr_sp(val)            mttgpr(29, val)
+#define read_tc_gpr_gp()                mftgpr(28)
+#define write_tc_gpr_gp(val)            mttgpr(28, val)
+
+__BUILD_SET_C0(mvpcontrol)
+
+#endif /* Not __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 2197aa4ce456..80370e0a5589 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -8,7 +8,7 @@
  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2003  Maciej W. Rozycki
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_MIPSREGS_H
 #define _ASM_MIPSREGS_H
@@ -96,6 +96,16 @@
 #define CP0_S1_INTCONTROL $20
 
 /*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL     $12   /* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP     $12   /* MIPSR2 */
+
+/*
  *  TX39 Series
  */
 #define CP0_TX39_CACHE  $7
@@ -281,6 +291,11 @@
 #define ST0_DL                  (_ULCAST_(1) << 24)
 
 /*
+ * Enable the MIPS DSP ASE
+ */
+#define ST0_MX                  0x01000000
+
+/*
  * Bitfields in the TX39 family CP0 Configuration Register 3
  */
 #define TX39_CONF_ICS_SHIFT     19
@@ -433,6 +448,14 @@
 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 
+/* Bits specific to the RM7000.  */
+#define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
+#define RM7K_CONF_TE            (_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
+#define RM7K_CONF_TC            (_ULCAST_(1) << 17)
+#define RM7K_CONF_SI            (_ULCAST_(3) << 20)
+#define RM7K_CONF_SC            (_ULCAST_(1) << 31)
+
 /* Bits specific to the R10000.  */
 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
@@ -475,6 +498,53 @@
 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 
 /*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
+
+#define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
+#define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
+#define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
+
+/*
  * R10000 performance counter definitions.
  *
  * FIXME: The R10000 performance counter opens a nice way to implement CPU
@@ -621,13 +691,13 @@ do {									\
         if (sel == 0)                                                   \
                 __asm__ __volatile__(                                   \
                         "mtc0\t%z0, " #register "\n\t"                  \
-                        : : "Jr" ((unsigned int)value));                \
+                        : : "Jr" ((unsigned int)(value)));              \
         else                                                            \
                 __asm__ __volatile__(                                   \
                         ".set\tmips32\n\t"                              \
                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
                         ".set\tmips0"                                   \
-                        : : "Jr" ((unsigned int)value));                \
+                        : : "Jr" ((unsigned int)(value)));              \
 } while (0)
 
 #define __write_64bit_c0_register(register, sel, value)                 \
@@ -676,7 +746,7 @@ do {									\
 do {                                                                    \
         __asm__ __volatile__(                                           \
                 "ctc0\t%z0, " #register "\n\t"                          \
-                : : "Jr" ((unsigned int)value));                        \
+                : : "Jr" ((unsigned int)(value)));                      \
 } while (0)
 
 /*
@@ -769,12 +839,24 @@ do {									\
 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 
+#define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
+
+#define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
+
 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 
 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 
+#define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
+
+#define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
+
 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 
@@ -790,10 +872,18 @@ do {									\
 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
+#define read_c0_config4()       __read_32bit_c0_register($16, 4)
+#define read_c0_config5()       __read_32bit_c0_register($16, 5)
+#define read_c0_config6()       __read_32bit_c0_register($16, 6)
+#define read_c0_config7()       __read_32bit_c0_register($16, 7)
 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 
 /*
  * The WatchLo register.  There may be upto 8 of them.
@@ -917,6 +1007,22 @@ do {									\
 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
 
+/* MIPSR2 */
+#define read_c0_hwrena()        __read_32bit_c0_register($7,0)
+#define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()        __read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()         __read_32bit_c0_register($15,1)
+#define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
+
 /*
  * Macros to access the floating point coprocessor control registers
  */
@@ -930,6 +1036,284 @@ do {									\
         : "=r" (__res));                                        \
         __res;})
 
+#define rddsp(mask)                                                     \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                            \n"             \
+        "       .set    noat                            \n"             \
+        "       # rddsp $1, %x1                         \n"             \
+        "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
+        "       move    %0, $1                          \n"             \
+        "       .set    pop                             \n"             \
+        : "=r" (__res)                                                  \
+        : "i" (mask));                                                  \
+        __res;                                                          \
+})
+
+#define wrdsp(val, mask)                                                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # wrdsp $1, %x1                                 \n"     \
+        "       .word   0x7c2004f8 | (%x1 << 15)                \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (val), "i" (mask));                                       \
+} while (0)
+
+#if 0   /* Need DSP ASE capable assembler ... */
+#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
+#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
+#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
+#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
+
+#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
+#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
+#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
+#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
+
+#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
+#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
+#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
+#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
+
+#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
+#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
+#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
+#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
+
+#else
+
+#define mfhi0()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac0                \n"                     \
+        "       .word   0x00000810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mfhi1()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac1                \n"                     \
+        "       .word   0x00200810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mfhi2()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac2                \n"                     \
+        "       .word   0x00400810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mfhi3()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac3                \n"                     \
+        "       .word   0x00600810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo0()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac0                \n"                     \
+        "       .word   0x00000812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo1()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac1                \n"                     \
+        "       .word   0x00200812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo2()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac2                \n"                     \
+        "       .word   0x00400812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo3()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac3                \n"                     \
+        "       .word   0x00600812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mthi0(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac0                                \n"     \
+        "       .word   0x00200011                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mthi1(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac1                                \n"     \
+        "       .word   0x00200811                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mthi2(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac2                                \n"     \
+        "       .word   0x00201011                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mthi3(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac3                                \n"     \
+        "       .word   0x00201811                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo0(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac0                                \n"     \
+        "       .word   0x00200013                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo1(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac1                                \n"     \
+        "       .word   0x00200813                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo2(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac2                                \n"     \
+        "       .word   0x00201013                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo3(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac3                                \n"     \
+        "       .word   0x00201813                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#endif
+
 /*
  * TLB operations.
  *
@@ -1012,6 +1396,8 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 45cd72d172e8..19cdf7642e66 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -30,7 +30,7 @@ extern unsigned long pgd_current[];
 
 #ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()                                         \
-        write_c0_context((unsigned long) smp_processor_id() << 23);     \
+        write_c0_context((unsigned long) smp_processor_id() << 25);     \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
 #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
@@ -40,7 +40,7 @@ extern unsigned long pgd_current[];
 #endif
 #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
 #define TLBMISS_HANDLER_SETUP()                                         \
-        write_c0_context((unsigned long) smp_processor_id() << 23);     \
+        write_c0_context((unsigned long) smp_processor_id() << 26);     \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
 
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index d721143dbd47..011caebac369 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -5,6 +5,7 @@
 #ifndef _ASM_MMZONE_H_
 #define _ASM_MMZONE_H_
 
+#include <linux/config.h>
 #include <asm/page.h>
 #include <mmzone.h>
 
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 0be58b2aeb9f..2be399311eec 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -14,15 +14,23 @@ struct mod_arch_specific {
 
 typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
 
-typedef struct
-{
-  Elf64_Addr r_offset;                  /* Address of relocation.  */
-  Elf64_Word r_sym;                     /* Symbol index.  */
-  Elf64_Byte r_ssym;                    /* Special symbol.  */
-  Elf64_Byte r_type3;                   /* Third relocation.  */
-  Elf64_Byte r_type2;                   /* Second relocation.  */
-  Elf64_Byte r_type;                    /* First relocation.  */
-  Elf64_Sxword r_addend;                /* Addend.  */
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+} Elf64_Mips_Rel;
+
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+        Elf64_Sxword r_addend;                  /* Addend.  */
 } Elf64_Mips_Rela;
 
 #ifdef CONFIG_32BIT
@@ -30,6 +38,13 @@ typedef struct
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
+#define Elf_Addr        Elf32_Addr
+
+#define Elf_Mips_Rel    Elf32_Rel
+#define Elf_Mips_Rela   Elf32_Rela
+
+#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
+#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
 
 #endif
 
@@ -38,6 +53,13 @@ typedef struct
 #define Elf_Shdr        Elf64_Shdr
 #define Elf_Sym         Elf64_Sym
 #define Elf_Ehdr        Elf64_Ehdr
+#define Elf_Addr        Elf64_Addr
+
+#define Elf_Mips_Rel    Elf64_Mips_Rel
+#define Elf_Mips_Rela   Elf64_Mips_Rela
+
+#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
+#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
 
 #endif
 
@@ -53,4 +75,54 @@ search_module_dbetables(unsigned long addr)
 }
 #endif
 
+#ifdef CONFIG_CPU_MIPS32_R1
+#define MODULE_PROC_FAMILY "MIPS32_R1"
+#elif defined CONFIG_CPU_MIPS32_R2
+#define MODULE_PROC_FAMILY "MIPS32_R2"
+#elif defined CONFIG_CPU_MIPS64_R1
+#define MODULE_PROC_FAMILY "MIPS64_R1"
+#elif defined CONFIG_CPU_MIPS64_R2
+#define MODULE_PROC_FAMILY "MIPS64_R2"
+#elif defined CONFIG_CPU_R3000
+#define MODULE_PROC_FAMILY "R3000"
+#elif defined CONFIG_CPU_TX39XX
+#define MODULE_PROC_FAMILY "TX39XX"
+#elif defined CONFIG_CPU_VR41XX
+#define MODULE_PROC_FAMILY "VR41XX"
+#elif defined CONFIG_CPU_R4300
+#define MODULE_PROC_FAMILY "R4300"
+#elif defined CONFIG_CPU_R4X00
+#define MODULE_PROC_FAMILY "R4X00"
+#elif defined CONFIG_CPU_TX49XX
+#define MODULE_PROC_FAMILY "TX49XX"
+#elif defined CONFIG_CPU_R5000
+#define MODULE_PROC_FAMILY "R5000"
+#elif defined CONFIG_CPU_R5432
+#define MODULE_PROC_FAMILY "R5432"
+#elif defined CONFIG_CPU_R6000
+#define MODULE_PROC_FAMILY "R6000"
+#elif defined CONFIG_CPU_NEVADA
+#define MODULE_PROC_FAMILY "NEVADA"
+#elif defined CONFIG_CPU_R8000
+#define MODULE_PROC_FAMILY "R8000"
+#elif defined CONFIG_CPU_R10000
+#define MODULE_PROC_FAMILY "R10000"
+#elif defined CONFIG_CPU_RM7000
+#define MODULE_PROC_FAMILY "RM7000"
+#elif defined CONFIG_CPU_RM9000
+#define MODULE_PROC_FAMILY "RM9000"
+#elif defined CONFIG_CPU_SB1
+#define MODULE_PROC_FAMILY "SB1"
+#else
+#error MODULE_PROC_FAMILY undefined for your processor configuration
+#endif
+
+#ifdef CONFIG_32BIT
+#define MODULE_KERNEL_TYPE "32BIT "
+#elif defined CONFIG_64BIT
+#define MODULE_KERNEL_TYPE "64BIT "
+#endif
+
+#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
+
 #endif /* _ASM_MODULE_H */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 309bc3099f68..46f2d23d2697 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -52,7 +52,7 @@ struct __large_pstruct { unsigned long buf[100]; };
 })
 
 #define __get_dbe_asm(insn)                                             \
-({                                                                      \
+{                                                                       \
         __asm__ __volatile__(                                           \
         "1:\t" insn "\t%1,%2\n\t"                                       \
         "move\t%0,$0\n"                                                 \
@@ -67,7 +67,7 @@ struct __large_pstruct { unsigned long buf[100]; };
         ".previous"                                                     \
         :"=r" (__gu_err), "=r" (__gu_val)                               \
         :"o" (__mp(__gu_addr)), "i" (-EFAULT));                         \
-})
+}
 
 extern void __get_dbe_unknown(void);
 
@@ -90,7 +90,7 @@ extern void __get_dbe_unknown(void);
 })
 
 #define __put_dbe_asm(insn)                                             \
-({                                                                      \
+{                                                                       \
         __asm__ __volatile__(                                           \
         "1:\t" insn "\t%1,%2\n\t"                                       \
         "move\t%0,$0\n"                                                 \
@@ -104,7 +104,7 @@ extern void __get_dbe_unknown(void);
         ".previous"                                                     \
         : "=r" (__pu_err)                                               \
         : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT));        \
-})
+}
 
 extern void __put_dbe_unknown(void);
 
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 652b6d67a571..ee25a779bf49 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -87,22 +87,48 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 typedef struct { unsigned long pte; } pte_t;
 #define pte_val(x)      ((x).pte)
 #endif
+#define __pte(x)        ((pte_t) { (x) } )
 
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
+/*
+ * For 3-level pagetables we defines these ourselves, for 2-level the
+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
+ */
+#ifdef CONFIG_64BIT
 
+typedef struct { unsigned long pmd; } pmd_t;
 #define pmd_val(x)      ((x).pmd)
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
+#define __pmd(x)        ((pmd_t) { (x) } )
 
-#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
+#endif
 
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
+/*
+ * Right now we don't support 4-level pagetables, so all pud-related
+ * definitions come from <asm-generic/pgtable-nopud.h>.
+ */
+
+/*
+ * Finall the top of the hierarchy, the pgd
+ */
+typedef struct { unsigned long pgd; } pgd_t;
+#define pgd_val(x)      ((x).pgd)
 #define __pgd(x)        ((pgd_t) { (x) } )
+
+/*
+ * Manipulate page protection bits
+ */
+typedef struct { unsigned long pgprot; } pgprot_t;
+#define pgprot_val(x)   ((x).pgprot)
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
+/*
+ * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
+ * pair of pages we only have a single global bit per pair of pages.  When
+ * writing to the TLB make sure we always have the bit set for both pages
+ * or none.  This macro is used to access the `buddy' of the pte we're just
+ * working on.
+ */
+#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
+
 #endif /* !__ASSEMBLY__ */
 
 /* to align the pointer to the (next) page boundary */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c9a00ca1c012..6c9ad8171a77 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -40,6 +40,11 @@ struct pci_controller {
         unsigned int need_domain_info;
 
         int iommu;
+
+        /* Optional access methods for reading/writing the bus number
+           of the PCI controller */
+        int (*get_busno)(void);
+        void (*set_busno)(int busno);
 };
 
 /*
@@ -142,8 +147,22 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 
 extern void pcibios_resource_to_bus(struct pci_dev *dev,
         struct pci_bus_region *region, struct resource *res);
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-        struct resource *res, struct pci_bus_region *region);
+
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
+
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
 
 #ifdef CONFIG_PCI_DOMAINS
 
@@ -169,17 +188,4 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 /* Do platform specific device initialization at pci_enable_device() time */
 extern int pcibios_plat_dev_init(struct pci_dev *dev);
 
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-        struct resource *root = NULL;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &ioport_resource;
-        if (res->flags & IORESOURCE_MEM)
-                root = &iomem_resource;
-
-        return root;
-}
-
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index ce57288d43bd..fe1df572318b 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -26,10 +26,22 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 }
 
 /*
+ * Initialize a new pmd table with invalid pointers.
+ */
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+#ifdef CONFIG_64BIT
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        set_pud(pud, __pud((unsigned long)pmd));
+}
+#endif
+
+/*
  * Initialize a new pgd / pmd table with invalid pointers.
  */
 extern void pgd_init(unsigned long page);
-extern void pmd_init(unsigned long page, unsigned long pagetable);
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
@@ -86,21 +98,18 @@ static inline void pte_free(struct page *pte)
 #define __pte_free_tlb(tlb,pte)         tlb_remove_page((tlb),(pte))
 
 #ifdef CONFIG_32BIT
-#define pgd_populate(mm, pmd, pte)      BUG()
 
 /*
  * allocating and freeing a pmd is trivial: the 1-entry pmd is
  * inside the pgd, so has no extra memory associated with it.
  */
-#define pmd_alloc_one(mm, addr)         ({ BUG(); ((pmd_t *)2); })
 #define pmd_free(x)                     do { } while (0)
 #define __pmd_free_tlb(tlb,x)           do { } while (0)
+
 #endif
 
 #ifdef CONFIG_64BIT
 
-#define pgd_populate(mm, pgd, pmd)      set_pgd(pgd, __pgd(pmd))
-
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 {
         pmd_t *pmd;
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 7fec93b76da9..0cff64ce0fb8 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -17,6 +17,8 @@
 #include <asm/cachectl.h>
 #include <asm/fixmap.h>
 
+#include <asm-generic/pgtable-nopmd.h>
+
 /*
  * - add_wired_entry() add a fixed TLB entry, and move wired register
  */
@@ -41,42 +43,38 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  * works even with the cache aliasing problem the R4k and above have.
  */
 
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
 #ifdef CONFIG_64BIT_PHYS_ADDR
-#define PMD_SHIFT       21
+#define PGDIR_SHIFT     21
 #else
-#define PMD_SHIFT       22
+#define PGDIR_SHIFT     22
 #endif
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     PMD_SHIFT
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
 /*
  * Entries per page directory level: we use two-level, so
- * we don't really have any PMD directory physically.
+ * we don't really have any PUD/PMD directory physically.
  */
 #ifdef CONFIG_64BIT_PHYS_ADDR
 #define PGD_ORDER       1
-#define PMD_ORDER       0
+#define PUD_ORDER       aieeee_attempt_to_allocate_pud
+#define PMD_ORDER       1
 #define PTE_ORDER       0
 #else
 #define PGD_ORDER       0
-#define PMD_ORDER       0
+#define PUD_ORDER       aieeee_attempt_to_allocate_pud
+#define PMD_ORDER       1
 #define PTE_ORDER       0
 #endif
 
 #define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
-#define PTRS_PER_PMD    1
 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
 #define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
 
-#define VMALLOC_START     KSEG2
+#define VMALLOC_START     MAP_BASE
 
 #ifdef CONFIG_HIGHMEM
 # define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
@@ -91,8 +89,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 #endif
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
@@ -120,17 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp)
         pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
 
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)           { return 0; }
-static inline int pgd_bad(pgd_t pgd)            { return 0; }
-static inline int pgd_present(pgd_t pgd)        { return 1; }
-static inline void pgd_clear(pgd_t *pgdp)       { }
-
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 #define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
 static inline pte_t
@@ -151,27 +137,22 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 #else
 #define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
 
 #define __pgd_offset(address)   pgd_index(address)
+#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 #define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
-#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 
 /* to find an entry in a page-table-directory */
 #define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
 
-/* Find an entry in the second-level page table.. */
-static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
-
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address)                                           \
         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
@@ -221,7 +202,7 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
  */
 #define PTE_FILE_MAX_BITS       27
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
         /* fixme */
 #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
 #define pgoff_to_pte(off) \
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 1011e0635f56..82166b254b27 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -16,13 +16,15 @@
 #include <asm/page.h>
 #include <asm/cachectl.h>
 
+#include <asm-generic/pgtable-nopud.h>
+
 /*
  * Each address space has 2 4K pages as its page directory, giving 1024
  * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
- * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to
- * page tables. Each page table is a single 4K page, giving 512 (==
- * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to
- * invalid_pmd_table, each pmde is initialized to point to
+ * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
+ * tables. Each page table is also a single 4K page, giving 512 (==
+ * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
+ * invalid_pmd_table, each pmd entry is initialized to point to
  * invalid_pte_table, each pte is initialized to 0. When memory is low,
  * and a pmd table or a page table allocation fails, empty_bad_pmd_table
  * and empty_bad_page_table is returned back to higher layer code, so
@@ -36,17 +38,17 @@
  */
 
 /* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT - 3))
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
 #define PMD_SIZE        (1UL << PMD_SHIFT)
 #define PMD_MASK        (~(PMD_SIZE-1))
 
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + 1 - 3))
+#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
 /*
- * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which
+ * For 4kB page size we use a 3 level page tree and an 8kB pud, which
  * permits us mapping 40 bits of virtual address space.
  *
  * We used to implement 41 bits by having an order 1 pmd level but that seemed
@@ -57,7 +59,7 @@
  * two levels would be easy to implement.
  *
  * For 16kB page size we use a 2 level page tree which permits a total of
- * 36 bits of virtual address space.  We could add a third leve. but it seems
+ * 36 bits of virtual address space.  We could add a third level but it seems
  * like at the moment there's no need for this.
  *
  * For 64kB page size we use a 2 level page table tree for a total of 42 bits
@@ -65,21 +67,25 @@
  */
 #ifdef CONFIG_PAGE_SIZE_4KB
 #define PGD_ORDER               1
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
 #ifdef CONFIG_PAGE_SIZE_8KB
 #define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
 #ifdef CONFIG_PAGE_SIZE_16KB
 #define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
 #ifdef CONFIG_PAGE_SIZE_64KB
 #define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
@@ -91,7 +97,7 @@
 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
 
-#define VMALLOC_START           XKSEG
+#define VMALLOC_START           MAP_BASE
 #define VMALLOC_END     \
         (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
 
@@ -102,13 +108,13 @@
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
 
-extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
-extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)];
-extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
-extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
+extern pte_t invalid_pte_table[PTRS_PER_PTE];
+extern pte_t empty_bad_page_table[PTRS_PER_PTE];
+extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
+extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
 
 /*
- * Empty pmd entries point to the invalid_pte_table.
+ * Empty pgd/pmd entries point to the invalid_pte_table.
  */
 static inline int pmd_none(pmd_t pmd)
 {
@@ -128,26 +134,30 @@ static inline void pmd_clear(pmd_t *pmdp)
 }
 
 /*
- * Empty pgd entries point to the invalid_pmd_table.
+ * Empty pud entries point to the invalid_pmd_table.
  */
-static inline int pgd_none(pgd_t pgd)
+static inline int pud_none(pud_t pud)
 {
-        return pgd_val(pgd) == (unsigned long) invalid_pmd_table;
+        return pud_val(pud) == (unsigned long) invalid_pmd_table;
 }
 
-#define pgd_bad(pgd)            (pgd_val(pgd) &~ PAGE_MASK)
+static inline int pud_bad(pud_t pud)
+{
+        return pud_val(pud) & ~PAGE_MASK;
+}
 
-static inline int pgd_present(pgd_t pgd)
+static inline int pud_present(pud_t pud)
 {
-        return pgd_val(pgd) != (unsigned long) invalid_pmd_table;
+        return pud_val(pud) != (unsigned long) invalid_pmd_table;
 }
 
-static inline void pgd_clear(pgd_t *pgdp)
+static inline void pud_clear(pud_t *pudp)
 {
-        pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table);
+        pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
 }
 
-#define pte_page(x)             pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT)))
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
 #ifdef CONFIG_CPU_VR41XX
 #define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
@@ -157,26 +167,27 @@ static inline void pgd_clear(pgd_t *pgdp)
 #endif
 
 #define __pgd_offset(address)   pgd_index(address)
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
+#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+#define __pmd_offset(address)   pmd_index(address)
 
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, 0)
 
-#define pgd_index(address)              ((address) >> PGDIR_SHIFT)
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pmd_index(address)      (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 
 /* to find an entry in a page-table-directory */
 #define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
 
-static inline unsigned long pgd_page(pgd_t pgd)
+static inline unsigned long pud_page(pud_t pud)
 {
-        return pgd_val(pgd);
+        return pud_val(pud);
 }
 
 /* Find an entry in the second-level page table.. */
-static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
+static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
 {
-        return (pmd_t *) pgd_page(*dir) +
-               ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
+        return (pmd_t *) pud_page(*pud) + pmd_index(address);
 }
 
 /* Find an entry in the third-level page table.. */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 3aad751ccd5f..01e76e932e3f 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
  * unpredictable things.  The code (when it is written) to deal with
  * this problem will be in the update_mmu_cache() code for the r4k.
  */
-#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
 
 #define _PAGE_PRESENT               (1<<6)  /* implemented in software */
 #define _PAGE_READ                  (1<<7)  /* implemented in software */
@@ -123,7 +123,7 @@
 
 #endif
 #endif
-#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
+#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
 
 #define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
 #define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -140,7 +140,7 @@
 #define PAGE_CACHABLE_DEFAULT   _CACHE_CACHABLE_COW
 #endif
 
-#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
 #define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT >> 3)
 #else
 #define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT >> 9)
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index eaf5d9b3a0e1..34facd996503 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -8,8 +8,6 @@
 #ifndef _ASM_PGTABLE_H
 #define _ASM_PGTABLE_H
 
-#include <asm-generic/4level-fixup.h>
-
 #include <linux/config.h>
 #ifdef CONFIG_32BIT
 #include <asm/pgtable-32.h>
@@ -18,6 +16,7 @@
 #include <asm/pgtable-64.h>
 #endif
 
+#include <asm/io.h>
 #include <asm/pgtable-bits.h>
 
 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
@@ -76,7 +75,6 @@ extern void paging_init(void);
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
  */
-#define page_pte(page)          page_pte_prot(page, __pgprot(0))
 #define pmd_phys(pmd)           (pmd_val(pmd) - PAGE_OFFSET)
 #define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
 #define pmd_page_kernel(pmd)    pmd_val(pmd)
@@ -84,7 +82,7 @@ extern void paging_init(void);
 #define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline void set_pte(pte_t *ptep, pte_t pte)
 {
         ptep->pte_high = pte.pte_high;
@@ -148,11 +146,18 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
 #endif
 
 /*
- * (pmds are folded into pgds so this doesn't get actually called,
+ * (pmds are folded into puds so this doesn't get actually called,
  * but the define is needed for a generic inline function.)
  */
 #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
-#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0)
+
+#ifdef CONFIG_64BIT
+/*
+ * (puds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
+#endif
 
 #define PGD_T_LOG2      ffz(~sizeof(pgd_t))
 #define PMD_T_LOG2      ffz(~sizeof(pmd_t))
@@ -165,7 +170,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
  * Undefined behaviour if not..
  */
 static inline int pte_user(pte_t pte)   { BUG(); return 0; }
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline int pte_read(pte_t pte)   { return (pte).pte_low & _PAGE_READ; }
 static inline int pte_write(pte_t pte)  { return (pte).pte_low & _PAGE_WRITE; }
 static inline int pte_dirty(pte_t pte)  { return (pte).pte_low & _PAGE_MODIFIED; }
@@ -324,7 +329,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
  */
 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
         pte.pte_low &= _PAGE_CHG_MASK;
@@ -357,7 +362,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 #endif
 
 #ifdef CONFIG_64BIT_PHYS_ADDR
-extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size);
 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
 
 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
@@ -367,7 +371,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                 pgprot_t prot)
 {
         phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-        return remap_pfn_range(vma, vaddr, pfn, size, prot);
+        return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
 }
 #else
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index d6466aa09fb7..f1980c6c3bcc 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -96,12 +96,26 @@ union mips_fpu_union {
         {{0,},} \
 }
 
+#define NUM_DSP_REGS   6
+
+typedef __u32 dspreg_t;
+
+struct mips_dsp_state {
+        dspreg_t        dspr[NUM_DSP_REGS];
+        unsigned int    dspcontrol;
+        unsigned short  used_dsp;
+};
+
+#define INIT_DSP {{0,},}
+
 typedef struct {
         unsigned long seg;
 } mm_segment_t;
 
 #define ARCH_MIN_TASKALIGN      8
 
+struct mips_abi;
+
 /*
  * If you change thread_struct remember to change the #defines below too!
  */
@@ -117,6 +131,9 @@ struct thread_struct {
         /* Saved fpu/fpu emulator stuff. */
         union mips_fpu_union fpu;
 
+        /* Saved state of the DSP ASE, if available. */
+        struct mips_dsp_state dsp;
+
         /* Other stuff associated with the thread. */
         unsigned long cp0_badvaddr;     /* Last user fault */
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
@@ -129,6 +146,7 @@ struct thread_struct {
         unsigned long mflags;
         unsigned long irix_trampoline;  /* Wheee... */
         unsigned long irix_oldctx;
+        struct mips_abi *abi;
 };
 
 #define MF_ABI_MASK     (MF_32BIT_REGS | MF_32BIT_ADDR)
@@ -151,6 +169,10 @@ struct thread_struct {
          */ \
         INIT_FPU, \
         /* \
+         * saved dsp/dsp emulator stuff \
+         */ \
+        INIT_DSP, \
+        /* \
          * Other stuff associated with the process \
          */ \
         0, 0, 0, 0, \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 2b5c624c3d4f..95c5839ac465 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -22,6 +22,8 @@
 #define MMLO            68
 #define FPC_CSR         69
 #define FPC_EIR         70
+#define DSP_BASE        71              /* 3 more hi / lo register pairs */
+#define DSP_CONTROL     77
 
 /*
  * This struct defines the way the registers are stored on the stack during a
@@ -38,18 +40,18 @@ struct pt_regs {
 
         /* Saved special registers. */
         unsigned long cp0_status;
-        unsigned long lo;
         unsigned long hi;
+        unsigned long lo;
         unsigned long cp0_badvaddr;
         unsigned long cp0_cause;
         unsigned long cp0_epc;
 };
 
 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-/* #define PTRACE_GETREGS               12 */
-/* #define PTRACE_SETREGS               13 */
-/* #define PTRACE_GETFPREGS             14 */
-/* #define PTRACE_SETFPREGS             15 */
+#define PTRACE_GETREGS          12
+#define PTRACE_SETREGS          13
+#define PTRACE_GETFPREGS                14
+#define PTRACE_SETFPREGS                15
 /* #define PTRACE_GETFPXREGS            18 */
 /* #define PTRACE_SETFPXREGS            19 */
 
@@ -58,6 +60,13 @@ struct pt_regs {
 #define PTRACE_GET_THREAD_AREA  25
 #define PTRACE_SET_THREAD_AREA  26
 
+/* Calls to trace a 64bit program from a 32bit program.  */
+#define PTRACE_PEEKTEXT_3264    0xc0
+#define PTRACE_PEEKDATA_3264    0xc1
+#define PTRACE_POKETEXT_3264    0xc2
+#define PTRACE_POKEDATA_3264    0xc3
+#define PTRACE_GET_THREAD_AREA_3264     0xc4
+
 #ifdef __KERNEL__
 
 #include <linux/linkage.h>
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 5bea49feec66..a5ea9d828aee 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -21,7 +21,7 @@
  *
  *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
  *    the index bits from the virtual address.  This breaks with tradition
- *    set by the R4000.  To keep unpleassant surprises from happening we pick
+ *    set by the R4000.  To keep unpleasant surprises from happening we pick
  *    an address in KSEG0 / CKSEG0.
  *  - We need a properly sign extended address for 64-bit code.  To get away
  *    without ifdefs we let the compiler do it by a type cast.
@@ -30,11 +30,11 @@
 
 #define cache_op(op,addr)                                               \
         __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
         "       .set    noreorder                               \n"     \
         "       .set    mips3\n\t                               \n"     \
         "       cache   %0, %1                                  \n"     \
-        "       .set    mips0                                   \n"     \
-        "       .set    reorder"                                        \
+        "       .set    pop                                     \n"     \
         :                                                               \
         : "i" (op), "m" (*(unsigned char *)(addr)))
 
@@ -84,14 +84,14 @@ static inline void flush_scache_line(unsigned long addr)
 static inline void protected_flush_icache_line(unsigned long addr)
 {
         __asm__ __volatile__(
-                ".set noreorder\n\t"
-                ".set mips3\n"
-                "1:\tcache %0,(%1)\n"
-                "2:\t.set mips0\n\t"
-                ".set reorder\n\t"
-                ".section\t__ex_table,\"a\"\n\t"
-                STR(PTR)"\t1b,2b\n\t"
-                ".previous"
+                "       .set    push                    \n"
+                "       .set    noreorder               \n"
+                "       .set    mips3                   \n"
+                "1:     cache   %0, (%1)                \n"
+                "2:     .set    pop                     \n"
+                "       .section __ex_table,\"a\"       \n"
+                "       "STR(PTR)" 1b, 2b               \n"
+                "       .previous"
                 :
                 : "i" (Hit_Invalidate_I), "r" (addr));
 }
@@ -100,19 +100,19 @@ static inline void protected_flush_icache_line(unsigned long addr)
  * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
  * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
  * caches.  We're talking about one cacheline unnecessarily getting invalidated
- * here so the penaltiy isn't overly hard.
+ * here so the penalty isn't overly hard.
  */
 static inline void protected_writeback_dcache_line(unsigned long addr)
 {
         __asm__ __volatile__(
-                ".set noreorder\n\t"
-                ".set mips3\n"
-                "1:\tcache %0,(%1)\n"
-                "2:\t.set mips0\n\t"
-                ".set reorder\n\t"
-                ".section\t__ex_table,\"a\"\n\t"
-                STR(PTR)"\t1b,2b\n\t"
-                ".previous"
+                "       .set    push                    \n"
+                "       .set    noreorder               \n"
+                "       .set    mips3                   \n"
+                "1:     cache   %0, (%1)                \n"
+                "2:     .set    pop                     \n"
+                "       .section __ex_table,\"a\"       \n"
+                "       "STR(PTR)" 1b, 2b               \n"
+                "       .previous"
                 :
                 : "i" (Hit_Writeback_Inv_D), "r" (addr));
 }
@@ -120,14 +120,14 @@ static inline void protected_writeback_dcache_line(unsigned long addr)
 static inline void protected_writeback_scache_line(unsigned long addr)
 {
         __asm__ __volatile__(
-                ".set noreorder\n\t"
-                ".set mips3\n"
-                "1:\tcache %0,(%1)\n"
-                "2:\t.set mips0\n\t"
-                ".set reorder\n\t"
-                ".section\t__ex_table,\"a\"\n\t"
-                STR(PTR)"\t1b,2b\n\t"
-                ".previous"
+                "       .set    push                    \n"
+                "       .set    noreorder               \n"
+                "       .set    mips3                   \n"
+                "1:     cache   %0, (%1)                \n"
+                "2:     .set    pop                     \n"
+                "       .section __ex_table,\"a\"       \n"
+                "       "STR(PTR)" 1b, 2b               \n"
+                "       .previous"
                 :
                 : "i" (Hit_Writeback_Inv_SD), "r" (addr));
 }
@@ -142,6 +142,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
 
 #define cache16_unroll32(base,op)                                       \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
         "       .set noreorder                                  \n"     \
         "       .set mips3                                      \n"     \
         "       cache %1, 0x000(%0); cache %1, 0x010(%0)        \n"     \
@@ -160,8 +161,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
         "       cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)        \n"     \
         "       cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)        \n"     \
         "       cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)        \n"     \
-        "       .set mips0                                      \n"     \
-        "       .set reorder                                    \n"     \
+        "       .set pop                                        \n"     \
                 :                                                       \
                 : "r" (base),                                           \
                   "i" (op));
@@ -285,6 +285,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
 
 #define cache32_unroll32(base,op)                                       \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
         "       .set noreorder                                  \n"     \
         "       .set mips3                                      \n"     \
         "       cache %1, 0x000(%0); cache %1, 0x020(%0)        \n"     \
@@ -303,8 +304,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
         "       cache %1, 0x340(%0); cache %1, 0x360(%0)        \n"     \
         "       cache %1, 0x380(%0); cache %1, 0x3a0(%0)        \n"     \
         "       cache %1, 0x3c0(%0); cache %1, 0x3e0(%0)        \n"     \
-        "       .set mips0                                      \n"     \
-        "       .set reorder                                    \n"     \
+        "       .set pop                                        \n"     \
                 :                                                       \
                 : "r" (base),                                           \
                   "i" (op));
@@ -428,6 +428,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
 
 #define cache64_unroll32(base,op)                                       \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
         "       .set noreorder                                  \n"     \
         "       .set mips3                                      \n"     \
         "       cache %1, 0x000(%0); cache %1, 0x040(%0)        \n"     \
@@ -446,8 +447,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
         "       cache %1, 0x680(%0); cache %1, 0x6c0(%0)        \n"     \
         "       cache %1, 0x700(%0); cache %1, 0x740(%0)        \n"     \
         "       cache %1, 0x780(%0); cache %1, 0x7c0(%0)        \n"     \
-        "       .set mips0                                      \n"     \
-        "       .set reorder                                    \n"     \
+        "       .set pop                                        \n"     \
                 :                                                       \
                 : "r" (base),                                           \
                   "i" (op));
@@ -532,6 +532,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
 
 #define cache128_unroll32(base,op)                                      \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
         "       .set noreorder                                  \n"     \
         "       .set mips3                                      \n"     \
         "       cache %1, 0x000(%0); cache %1, 0x080(%0)        \n"     \
@@ -550,8 +551,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
         "       cache %1, 0xd00(%0); cache %1, 0xd80(%0)        \n"     \
         "       cache %1, 0xe00(%0); cache %1, 0xe80(%0)        \n"     \
         "       cache %1, 0xf00(%0); cache %1, 0xf80(%0)        \n"     \
-        "       .set mips0                                      \n"     \
-        "       .set reorder                                    \n"     \
+        "       .set pop                                        \n"     \
                 :                                                       \
                 : "r" (base),                                           \
                   "i" (op));
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 3c4b637fd925..a60e0dc7c9b9 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -14,7 +14,9 @@
 
 #ifdef __KERNEL__
 
+#include <linux/spinlock.h>
 #include <linux/rtc.h>
+#include <asm/time.h>
 
 #define RTC_PIE 0x40            /* periodic interrupt enable */
 #define RTC_AIE 0x20            /* alarm interrupt enable */
@@ -27,11 +29,52 @@
 #define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
 #define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
 
-unsigned int get_rtc_time(struct rtc_time *time);
-int set_rtc_time(struct rtc_time *time);
-unsigned int get_rtc_ss(void);
-int get_rtc_pll(struct rtc_pll_info *pll);
-int set_rtc_pll(struct rtc_pll_info *pll);
+static DEFINE_SPINLOCK(mips_rtc_lock);
 
+static inline unsigned int get_rtc_time(struct rtc_time *time)
+{
+        unsigned long nowtime;
+
+        spin_lock(&mips_rtc_lock);
+        nowtime = rtc_get_time();
+        to_tm(nowtime, time);
+        time->tm_year -= 1900;
+        spin_unlock(&mips_rtc_lock);
+
+        return RTC_24H;
+}
+
+static inline int set_rtc_time(struct rtc_time *time)
+{
+        unsigned long nowtime;
+        int ret;
+
+        spin_lock(&mips_rtc_lock);
+        nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
+                        time->tm_mday, time->tm_hour, time->tm_min,
+                        time->tm_sec);
+        ret = rtc_set_time(nowtime);
+        spin_unlock(&mips_rtc_lock);
+
+        return ret;
+}
+
+static inline unsigned int get_rtc_ss(void)
+{
+        struct rtc_time h;
+
+        get_rtc_time(&h);
+        return h.tm_sec;
+}
+
+static inline int get_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+
+static inline int set_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
 #endif
 #endif
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h
new file mode 100644
index 000000000000..83cdf6ab0d1f
--- /dev/null
+++ b/include/asm-mips/rtlx.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ */
+
+#ifndef _RTLX_H
+#define _RTLX_H_
+
+#define LX_NODE_BASE 10
+
+#define MIPSCPU_INT_BASE       16
+#define MIPS_CPU_RTLX_IRQ 0
+
+#define RTLX_VERSION 1
+#define RTLX_xID 0x12345600
+#define RTLX_ID (RTLX_xID | RTLX_VERSION)
+#define RTLX_CHANNELS 8
+
+enum rtlx_state {
+        RTLX_STATE_UNUSED = 0,
+        RTLX_STATE_INITIALISED,
+        RTLX_STATE_REMOTE_READY,
+        RTLX_STATE_OPENED
+};
+
+#define RTLX_BUFFER_SIZE 1024
+/* each channel supports read and write.
+   linux (vpe0) reads lx_buffer  and writes rt_buffer
+   SP (vpe1) reads rt_buffer and writes lx_buffer
+*/
+typedef struct rtlx_channel {
+        enum rtlx_state rt_state;
+        enum rtlx_state lx_state;
+
+        int buffer_size;
+
+        /* read and write indexes per buffer */
+        int rt_write, rt_read;
+        char *rt_buffer;
+
+        int lx_write, lx_read;
+        char *lx_buffer;
+
+        void *queues;
+
+} rtlx_channel_t;
+
+typedef struct rtlx_info {
+        unsigned long id;
+        enum rtlx_state state;
+
+        struct rtlx_channel channel[RTLX_CHANNELS];
+
+} rtlx_info_t;
+
+#endif
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index c2c97dec661b..3d6aa7c7ea81 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -45,9 +45,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name, count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 4eed8e2acdc3..e796d75f027e 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -52,16 +52,6 @@
 #define JAZZ_SERIAL_PORT_DEFNS
 #endif
 
-#ifdef CONFIG_MIPS_COBALT
-#include <asm/cobalt/cobalt.h>
-#define COBALT_BASE_BAUD  (18432000 / 16)
-#define COBALT_SERIAL_PORT_DEFNS                \
-        /* UART CLK   PORT  IRQ  FLAGS    */            \
-        { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS },   /* ttyS0 */
-#else
-#define COBALT_SERIAL_PORT_DEFNS
-#endif
-
 /*
  * Both Galileo boards have the same UART mappings.
  */
@@ -113,17 +103,6 @@
 #define IVR_SERIAL_PORT_DEFNS
 #endif
 
-#ifdef CONFIG_TOSHIBA_JMR3927
-#include <asm/jmr3927/jmr3927.h>
-#define TXX927_SERIAL_PORT_DEFNS                              \
-    { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT,  \
-      .flags = UART0_FLAGS, .type = 1 },                        \
-    { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT,  \
-      .flags = UART1_FLAGS, .type = 1 },
-#else
-#define TXX927_SERIAL_PORT_DEFNS
-#endif
-
 #ifdef CONFIG_SERIAL_AU1X00
 #include <asm/mach-au1x00/au1000.h>
 #ifdef CONFIG_SOC_AU1000
@@ -227,9 +206,9 @@
 #define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
 
 #define _JAGUAR_ATX_SERIAL_INIT(int, base)                              \
-        { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int,                    \
-          flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),               \
-          iomem_base: (u8 *) base, iomem_reg_shift: 2,                  \
+        { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int,                  \
+          .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),             \
+          .iomem_base = (u8 *) base, iomem_reg_shift: 2,                        \
           io_type: SERIAL_IO_MEM }
 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS                            \
         _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
@@ -243,9 +222,9 @@
 #define OCELOT_3_SERIAL_BASE    (signed)0xfd000020
 
 #define _OCELOT_3_SERIAL_INIT(int, base)                                \
-        { baud_base: OCELOT_3_BASE_BAUD, irq: int,                      \
-          flags: STD_COM_FLAGS,                                         \
-          iomem_base: (u8 *) base, iomem_reg_shift: 2,                  \
+        { .baud_base = OCELOT_3_BASE_BAUD, irq: int,                    \
+          .flags = STD_COM_FLAGS,                                               \
+          .iomem_base = (u8 *) base, iomem_reg_shift: 2,                        \
           io_type: SERIAL_IO_MEM }
 
 #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS                              \
@@ -342,7 +321,6 @@
 #endif /* CONFIG_SGI_IP32 */
 
 #define SERIAL_PORT_DFNS                                \
-        COBALT_SERIAL_PORT_DEFNS                        \
         DDB5477_SERIAL_PORT_DEFNS                       \
         EV96100_SERIAL_PORT_DEFNS                       \
         IP32_SERIAL_PORT_DEFNS                          \
@@ -354,7 +332,6 @@
         MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS              \
         MOMENCO_OCELOT_SERIAL_PORT_DEFNS                \
         MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS              \
-        TXX927_SERIAL_PORT_DEFNS                        \
         AU1000_SERIAL_PORT_DEFNS
 
 #endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index ac3dfc7af5b0..fcec52bafb25 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -128,26 +128,26 @@ struct hpc3_ethregs {
         volatile u32 rx_gfptr;  /* current GIO fifo ptr */
         volatile u32 rx_dfptr;  /* current device fifo ptr */
         u32 _unused1;           /* padding */
-        volatile u32 rx_reset;  /* reset register */
-#define HPC3_ERXRST_CRESET 0x1  /* Reset dma channel and external controller */
-#define HPC3_ERXRST_CLRIRQ 0x2  /* Clear channel interrupt */
-#define HPC3_ERXRST_LBACK  0x4  /* Enable diagnostic loopback mode of Seeq8003 */
-
-        volatile u32 rx_dconfig;        /* DMA configuration register */
-#define HPC3_ERXDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
-#define HPC3_ERXDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
-#define HPC3_ERXDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
-#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
-#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
-#define HPC3_ERXDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
-#define HPC3_ERXDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
-#define HPC3_ERXDCFG_PTO   0x30000 /* Programmed timeout value for above two */
-
-        volatile u32 rx_pconfig;        /* PIO configuration register */
-#define HPC3_ERXPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
-#define HPC3_ERXPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
-#define HPC3_ERXPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
-#define HPC3_ERXPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
+        volatile u32 reset;     /* reset register */
+#define HPC3_ERST_CRESET 0x1    /* Reset dma channel and external controller */
+#define HPC3_ERST_CLRIRQ 0x2    /* Clear channel interrupt */
+#define HPC3_ERST_LBACK  0x4    /* Enable diagnostic loopback mode of Seeq8003 */
+
+        volatile u32 dconfig;    /* DMA configuration register */
+#define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
+#define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
+#define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
+#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
+#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
+#define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
+#define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
+#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
+
+        volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
+#define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
+#define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
+#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
 
         u32 _unused2[0x1000/4 - 8];     /* padding */
 
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
new file mode 100644
index 000000000000..42d4cf00efd3
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -0,0 +1,310 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Interrupt Mapper definitions             File: bcm1480_int.h
+    *
+    *  This module contains constants for manipulating the
+    *  BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
+    *  definitions for the interrupt sources.
+    *
+    *  BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_INT_H
+#define _BCM1480_INT_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+
+/*
+ * The interrupt mapper deals with 128-bit logical registers that are
+ * implemented as pairs of 64-bit registers, with the "low" 64 bits in
+ * a register that has an address 0x1000 higher(!) than the
+ * corresponding "high" register.
+ *
+ * For appropriate registers, bit 0 of the "high" register is a
+ * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
+ * register.
+ */
+
+/*
+ * This entire file uses _BCM1480_ in all the symbols because it is
+ * entirely BCM1480 specific.
+ */
+
+/*
+ * Interrupt sources (Table 22)
+ */
+
+#define K_BCM1480_INT_SOURCES               128
+
+#define _BCM1480_INT_HIGH(k)   (k)
+#define _BCM1480_INT_LOW(k)    ((k)+64)
+
+#define K_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_HIGH(1)
+#define K_BCM1480_INT_GPIO_0                _BCM1480_INT_HIGH(4)
+#define K_BCM1480_INT_GPIO_1                _BCM1480_INT_HIGH(5)
+#define K_BCM1480_INT_GPIO_2                _BCM1480_INT_HIGH(6)
+#define K_BCM1480_INT_GPIO_3                _BCM1480_INT_HIGH(7)
+#define K_BCM1480_INT_PCI_INTA              _BCM1480_INT_HIGH(8)
+#define K_BCM1480_INT_PCI_INTB              _BCM1480_INT_HIGH(9)
+#define K_BCM1480_INT_PCI_INTC              _BCM1480_INT_HIGH(10)
+#define K_BCM1480_INT_PCI_INTD              _BCM1480_INT_HIGH(11)
+#define K_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_HIGH(12)
+#define K_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_HIGH(13)
+#define K_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_HIGH(14)
+#define K_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_HIGH(15)
+#define K_BCM1480_INT_TIMER_0               _BCM1480_INT_HIGH(20)
+#define K_BCM1480_INT_TIMER_1               _BCM1480_INT_HIGH(21)
+#define K_BCM1480_INT_TIMER_2               _BCM1480_INT_HIGH(22)
+#define K_BCM1480_INT_TIMER_3               _BCM1480_INT_HIGH(23)
+#define K_BCM1480_INT_DM_CH_0               _BCM1480_INT_HIGH(28)
+#define K_BCM1480_INT_DM_CH_1               _BCM1480_INT_HIGH(29)
+#define K_BCM1480_INT_DM_CH_2               _BCM1480_INT_HIGH(30)
+#define K_BCM1480_INT_DM_CH_3               _BCM1480_INT_HIGH(31)
+#define K_BCM1480_INT_MAC_0                 _BCM1480_INT_HIGH(36)
+#define K_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_HIGH(37)
+#define K_BCM1480_INT_MAC_1                 _BCM1480_INT_HIGH(38)
+#define K_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_HIGH(39)
+#define K_BCM1480_INT_MAC_2                 _BCM1480_INT_HIGH(40)
+#define K_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_HIGH(41)
+#define K_BCM1480_INT_MAC_3                 _BCM1480_INT_HIGH(42)
+#define K_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_HIGH(43)
+#define K_BCM1480_INT_PMI_LOW               _BCM1480_INT_HIGH(52)
+#define K_BCM1480_INT_PMI_HIGH              _BCM1480_INT_HIGH(53)
+#define K_BCM1480_INT_PMO_LOW               _BCM1480_INT_HIGH(54)
+#define K_BCM1480_INT_PMO_HIGH              _BCM1480_INT_HIGH(55)
+#define K_BCM1480_INT_MBOX_0_0              _BCM1480_INT_HIGH(56)
+#define K_BCM1480_INT_MBOX_0_1              _BCM1480_INT_HIGH(57)
+#define K_BCM1480_INT_MBOX_0_2              _BCM1480_INT_HIGH(58)
+#define K_BCM1480_INT_MBOX_0_3              _BCM1480_INT_HIGH(59)
+#define K_BCM1480_INT_MBOX_1_0              _BCM1480_INT_HIGH(60)
+#define K_BCM1480_INT_MBOX_1_1              _BCM1480_INT_HIGH(61)
+#define K_BCM1480_INT_MBOX_1_2              _BCM1480_INT_HIGH(62)
+#define K_BCM1480_INT_MBOX_1_3              _BCM1480_INT_HIGH(63)
+
+#define K_BCM1480_INT_BAD_ECC               _BCM1480_INT_LOW(1)
+#define K_BCM1480_INT_COR_ECC               _BCM1480_INT_LOW(2)
+#define K_BCM1480_INT_IO_BUS                _BCM1480_INT_LOW(3)
+#define K_BCM1480_INT_PERF_CNT              _BCM1480_INT_LOW(4)
+#define K_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_LOW(5)
+#define K_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_LOW(6)
+#define K_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_LOW(7)
+#define K_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_LOW(8)
+#define K_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_LOW(9)
+#define K_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_LOW(10)
+#define K_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_LOW(11)
+#define K_BCM1480_INT_PCI_ERROR             _BCM1480_INT_LOW(16)
+#define K_BCM1480_INT_PCI_RESET             _BCM1480_INT_LOW(17)
+#define K_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_LOW(18)
+#define K_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_LOW(19)
+#define K_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_LOW(20)
+#define K_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_LOW(21)
+#define K_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_LOW(22)
+#define K_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_LOW(23)
+#define K_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_LOW(24)
+#define K_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_LOW(25)
+#define K_BCM1480_INT_LDT_SMI               _BCM1480_INT_LOW(32)
+#define K_BCM1480_INT_LDT_NMI               _BCM1480_INT_LOW(33)
+#define K_BCM1480_INT_LDT_INIT              _BCM1480_INT_LOW(34)
+#define K_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_LOW(35)
+#define K_BCM1480_INT_LDT_EXT               _BCM1480_INT_LOW(36)
+#define K_BCM1480_INT_SMB_0                 _BCM1480_INT_LOW(40)
+#define K_BCM1480_INT_SMB_1                 _BCM1480_INT_LOW(41)
+#define K_BCM1480_INT_PCMCIA                _BCM1480_INT_LOW(42)
+#define K_BCM1480_INT_UART_0                _BCM1480_INT_LOW(44)
+#define K_BCM1480_INT_UART_1                _BCM1480_INT_LOW(45)
+#define K_BCM1480_INT_UART_2                _BCM1480_INT_LOW(46)
+#define K_BCM1480_INT_UART_3                _BCM1480_INT_LOW(47)
+#define K_BCM1480_INT_GPIO_4                _BCM1480_INT_LOW(52)
+#define K_BCM1480_INT_GPIO_5                _BCM1480_INT_LOW(53)
+#define K_BCM1480_INT_GPIO_6                _BCM1480_INT_LOW(54)
+#define K_BCM1480_INT_GPIO_7                _BCM1480_INT_LOW(55)
+#define K_BCM1480_INT_GPIO_8                _BCM1480_INT_LOW(56)
+#define K_BCM1480_INT_GPIO_9                _BCM1480_INT_LOW(57)
+#define K_BCM1480_INT_GPIO_10               _BCM1480_INT_LOW(58)
+#define K_BCM1480_INT_GPIO_11               _BCM1480_INT_LOW(59)
+#define K_BCM1480_INT_GPIO_12               _BCM1480_INT_LOW(60)
+#define K_BCM1480_INT_GPIO_13               _BCM1480_INT_LOW(61)
+#define K_BCM1480_INT_GPIO_14               _BCM1480_INT_LOW(62)
+#define K_BCM1480_INT_GPIO_15               _BCM1480_INT_LOW(63)
+
+/*
+ * Mask values for each interrupt
+ */
+
+#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))
+#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
+
+#define M_BCM1480_INT_CASCADE               _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
+
+#define M_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
+#define M_BCM1480_INT_GPIO_0                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
+#define M_BCM1480_INT_GPIO_1                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
+#define M_BCM1480_INT_GPIO_2                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
+#define M_BCM1480_INT_GPIO_3                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
+#define M_BCM1480_INT_PCI_INTA              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
+#define M_BCM1480_INT_PCI_INTB              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
+#define M_BCM1480_INT_PCI_INTC              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
+#define M_BCM1480_INT_PCI_INTD              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
+#define M_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
+#define M_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
+#define M_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
+#define M_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
+#define M_BCM1480_INT_TIMER_0               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
+#define M_BCM1480_INT_TIMER_1               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
+#define M_BCM1480_INT_TIMER_2               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
+#define M_BCM1480_INT_TIMER_3               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
+#define M_BCM1480_INT_DM_CH_0               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
+#define M_BCM1480_INT_DM_CH_1               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
+#define M_BCM1480_INT_DM_CH_2               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
+#define M_BCM1480_INT_DM_CH_3               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
+#define M_BCM1480_INT_MAC_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
+#define M_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
+#define M_BCM1480_INT_MAC_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
+#define M_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
+#define M_BCM1480_INT_MAC_2                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
+#define M_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
+#define M_BCM1480_INT_MAC_3                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
+#define M_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
+#define M_BCM1480_INT_PMI_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
+#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
+#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
+#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
+#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
+#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
+#define M_BCM1480_INT_MBOX_0_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
+#define M_BCM1480_INT_MBOX_1_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
+#define M_BCM1480_INT_MBOX_1_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
+#define M_BCM1480_INT_MBOX_1_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
+#define M_BCM1480_INT_MBOX_1_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
+#define M_BCM1480_INT_BAD_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
+#define M_BCM1480_INT_COR_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
+#define M_BCM1480_INT_IO_BUS                _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
+#define M_BCM1480_INT_PERF_CNT              _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
+#define M_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
+#define M_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
+#define M_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
+#define M_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
+#define M_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
+#define M_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
+#define M_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
+#define M_BCM1480_INT_PCI_ERROR             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
+#define M_BCM1480_INT_PCI_RESET             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
+#define M_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
+#define M_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
+#define M_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
+#define M_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
+#define M_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
+#define M_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
+#define M_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
+#define M_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
+#define M_BCM1480_INT_LDT_SMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
+#define M_BCM1480_INT_LDT_NMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
+#define M_BCM1480_INT_LDT_INIT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
+#define M_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
+#define M_BCM1480_INT_LDT_EXT               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
+#define M_BCM1480_INT_SMB_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
+#define M_BCM1480_INT_SMB_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
+#define M_BCM1480_INT_PCMCIA                _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
+#define M_BCM1480_INT_UART_0                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
+#define M_BCM1480_INT_UART_1                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
+#define M_BCM1480_INT_UART_2                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
+#define M_BCM1480_INT_UART_3                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
+#define M_BCM1480_INT_GPIO_4                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
+#define M_BCM1480_INT_GPIO_5                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
+#define M_BCM1480_INT_GPIO_6                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
+#define M_BCM1480_INT_GPIO_7                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
+#define M_BCM1480_INT_GPIO_8                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
+#define M_BCM1480_INT_GPIO_9                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
+#define M_BCM1480_INT_GPIO_10               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
+#define M_BCM1480_INT_GPIO_11               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
+#define M_BCM1480_INT_GPIO_12               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
+#define M_BCM1480_INT_GPIO_13               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
+#define M_BCM1480_INT_GPIO_14               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
+#define M_BCM1480_INT_GPIO_15               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
+
+/*
+ * Interrupt mappings (Table 18)
+ */
+
+#define K_BCM1480_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_BCM1480_INT_MAP_I1    1
+#define K_BCM1480_INT_MAP_I2    2
+#define K_BCM1480_INT_MAP_I3    3
+#define K_BCM1480_INT_MAP_I4    4
+#define K_BCM1480_INT_MAP_I5    5
+#define K_BCM1480_INT_MAP_NMI   6               /* nonmaskable */
+#define K_BCM1480_INT_MAP_DINT  7               /* debug interrupt */
+
+/*
+ * Interrupt LDT Set Register (Table 19)
+ */
+
+#define S_BCM1480_INT_HT_INTMSG             0
+#define M_BCM1480_INT_HT_INTMSG             _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG)
+#define V_BCM1480_INT_HT_INTMSG(x)          _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG)
+#define G_BCM1480_INT_HT_INTMSG(x)          _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG)
+
+#define K_BCM1480_INT_HT_INTMSG_FIXED       0
+#define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
+#define K_BCM1480_INT_HT_INTMSG_SMI         2
+#define K_BCM1480_INT_HT_INTMSG_NMI         3
+#define K_BCM1480_INT_HT_INTMSG_INIT        4
+#define K_BCM1480_INT_HT_INTMSG_STARTUP     5
+#define K_BCM1480_INT_HT_INTMSG_EXTINT      6
+#define K_BCM1480_INT_HT_INTMSG_RESERVED    7
+
+#define M_BCM1480_INT_HT_TRIGGERMODE        _SB_MAKEMASK1(3)
+#define V_BCM1480_INT_HT_EDGETRIGGER        0
+#define V_BCM1480_INT_HT_LEVELTRIGGER       M_BCM1480_INT_HT_TRIGGERMODE
+
+#define M_BCM1480_INT_HT_DESTMODE           _SB_MAKEMASK1(4)
+#define V_BCM1480_INT_HT_PHYSICALDEST       0
+#define V_BCM1480_INT_HT_LOGICALDEST        M_BCM1480_INT_HT_DESTMODE
+
+#define S_BCM1480_INT_HT_INTDEST            5
+#define M_BCM1480_INT_HT_INTDEST            _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST)
+#define V_BCM1480_INT_HT_INTDEST(x)         _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST)
+#define G_BCM1480_INT_HT_INTDEST(x)         _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST)
+
+#define S_BCM1480_INT_HT_VECTOR             13
+#define M_BCM1480_INT_HT_VECTOR             _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR)
+#define V_BCM1480_INT_HT_VECTOR(x)          _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR)
+#define G_BCM1480_INT_HT_VECTOR(x)          _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR)
+
+/*
+ * Vector prefix (Table 4-7)
+ */
+
+#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
+#define M_BCM1480_HTVECT_RAISE_MBOX_0       0x40
+#define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
+#define M_BCM1480_HTVECT_RAISE_MBOX_1       0xC0
+
+#endif /* _BCM1480_INT_H */
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h
new file mode 100644
index 000000000000..886b099565e6
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_l2c.h
@@ -0,0 +1,176 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  L2 Cache constants and macros            File: bcm1480_l2c.h
+    *
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *
+    *  BCM1400 specification level:  1280-UM100-D2 (11/14/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_L2C_H
+#define _BCM1480_L2C_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Format of level 2 cache management address (Table 55)
+ */
+
+#define S_BCM1480_L2C_MGMT_INDEX            5
+#define M_BCM1480_L2C_MGMT_INDEX            _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX)
+#define V_BCM1480_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX)
+#define G_BCM1480_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX)
+
+#define S_BCM1480_L2C_MGMT_WAY              17
+#define M_BCM1480_L2C_MGMT_WAY              _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY)
+#define V_BCM1480_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY)
+#define G_BCM1480_L2C_MGMT_WAY(x)           _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY)
+
+#define M_BCM1480_L2C_MGMT_DIRTY            _SB_MAKEMASK1(20)
+#define M_BCM1480_L2C_MGMT_VALID            _SB_MAKEMASK1(21)
+
+#define S_BCM1480_L2C_MGMT_ECC_DIAG         22
+#define M_BCM1480_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG)
+
+#define A_BCM1480_L2C_MGMT_TAG_BASE         0x00D0000000
+
+#define BCM1480_L2C_ENTRIES_PER_WAY         4096
+#define BCM1480_L2C_NUM_WAYS                8
+
+
+/*
+ * Level 2 Cache Tag register (Table 59)
+ */
+
+#define S_BCM1480_L2C_TAG_MBZ               0
+#define M_BCM1480_L2C_TAG_MBZ               _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ)
+
+#define S_BCM1480_L2C_TAG_INDEX             5
+#define M_BCM1480_L2C_TAG_INDEX             _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX)
+#define V_BCM1480_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX)
+#define G_BCM1480_L2C_TAG_INDEX(x)          _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX)
+
+/* Note that index bit 16 is also tag bit 40 */
+#define S_BCM1480_L2C_TAG_TAG               17
+#define M_BCM1480_L2C_TAG_TAG               _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG)
+#define V_BCM1480_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG)
+#define G_BCM1480_L2C_TAG_TAG(x)            _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG)
+
+#define S_BCM1480_L2C_TAG_ECC               40
+#define M_BCM1480_L2C_TAG_ECC               _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC)
+#define V_BCM1480_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC)
+#define G_BCM1480_L2C_TAG_ECC(x)            _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC)
+
+#define S_BCM1480_L2C_TAG_WAY               46
+#define M_BCM1480_L2C_TAG_WAY               _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY)
+#define V_BCM1480_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY)
+#define G_BCM1480_L2C_TAG_WAY(x)            _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY)
+
+#define M_BCM1480_L2C_TAG_DIRTY             _SB_MAKEMASK1(49)
+#define M_BCM1480_L2C_TAG_VALID             _SB_MAKEMASK1(50)
+
+#define S_BCM1480_L2C_DATA_ECC              51
+#define M_BCM1480_L2C_DATA_ECC              _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC)
+#define V_BCM1480_L2C_DATA_ECC(x)           _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC)
+#define G_BCM1480_L2C_DATA_ECC(x)           _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC)
+
+
+/*
+ * L2 Misc0 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC0_WAY_REMOTE      0
+#define M_BCM1480_L2C_MISC0_WAY_REMOTE      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE)
+#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE)
+
+#define S_BCM1480_L2C_MISC0_WAY_LOCAL       8
+#define M_BCM1480_L2C_MISC0_WAY_LOCAL       _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL)
+#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL)
+
+#define S_BCM1480_L2C_MISC0_WAY_ENABLE      16
+#define M_BCM1480_L2C_MISC0_WAY_ENABLE      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE)
+#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE)
+
+#define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
+#define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE)
+#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE)
+
+#define S_BCM1480_L2C_MISC0_CACHE_QUAD      26
+#define M_BCM1480_L2C_MISC0_CACHE_QUAD      _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD)
+#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD)
+
+#define S_BCM1480_L2C_MISC0_MC_PRIORITY      30
+#define M_BCM1480_L2C_MISC0_MC_PRIORITY      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
+
+#define S_BCM1480_L2C_MISC0_ECC_CLEANUP      31
+#define M_BCM1480_L2C_MISC0_ECC_CLEANUP      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
+
+
+/*
+ * L2 Misc1 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_0      0
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_0      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_1      8
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_1      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_2      16
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_2      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_3      24
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_3      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_4      32
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_4      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4)
+
+
+/*
+ * L2 Misc2 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_8      0
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_8      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8)
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_9      8
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_9      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9)
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_A      16
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_A      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A)
+
+
+#endif /* _BCM1480_L2C_H */
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
new file mode 100644
index 000000000000..6bdc941afc91
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -0,0 +1,962 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Memory Controller constants              File: bcm1480_mc.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *
+    *  BCM1400 specification level:  1280-UM100-D1 (11/14/03 Review Copy)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_MC_H
+#define _BCM1480_MC_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Memory Channel Configuration Register (Table 81)
+ */
+
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0_DEFAULT         V_BCM1480_MC_INTLV0(0)
+
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1_DEFAULT         V_BCM1480_MC_INTLV1(0)
+
+#define S_BCM1480_MC_INTLV2                 16
+#define M_BCM1480_MC_INTLV2                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2)
+#define G_BCM1480_MC_INTLV2(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2_DEFAULT         V_BCM1480_MC_INTLV2(0)
+
+#define S_BCM1480_MC_CS_MODE                32
+#define M_BCM1480_MC_CS_MODE                _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE)
+#define G_BCM1480_MC_CS_MODE(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE_DEFAULT        V_BCM1480_MC_CS_MODE(0)
+
+#define V_BCM1480_MC_CONFIG_DEFAULT         (V_BCM1480_MC_INTLV0_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV1_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV2_DEFAULT  | \
+                                     V_BCM1480_MC_CS_MODE_DEFAULT)
+
+#define K_BCM1480_MC_CS01_MODE              0x03
+#define K_BCM1480_MC_CS02_MODE              0x05
+#define K_BCM1480_MC_CS0123_MODE            0x0F
+#define K_BCM1480_MC_CS0246_MODE            0x55
+#define K_BCM1480_MC_CS0145_MODE            0x33
+#define K_BCM1480_MC_CS0167_MODE            0xC3
+#define K_BCM1480_MC_CSFULL_MODE            0xFF
+
+/*
+ * Chip Select Start Address Register (Table 82)
+ */
+
+#define S_BCM1480_MC_CS0_START              0
+#define M_BCM1480_MC_CS0_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START)
+#define V_BCM1480_MC_CS0_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START)
+#define G_BCM1480_MC_CS0_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START)
+
+#define S_BCM1480_MC_CS1_START              16
+#define M_BCM1480_MC_CS1_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START)
+#define V_BCM1480_MC_CS1_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START)
+#define G_BCM1480_MC_CS1_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START)
+
+#define S_BCM1480_MC_CS2_START              32
+#define M_BCM1480_MC_CS2_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START)
+#define V_BCM1480_MC_CS2_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START)
+#define G_BCM1480_MC_CS2_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START)
+
+#define S_BCM1480_MC_CS3_START              48
+#define M_BCM1480_MC_CS3_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START)
+#define V_BCM1480_MC_CS3_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START)
+#define G_BCM1480_MC_CS3_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START)
+
+/*
+ * Chip Select End Address Register (Table 83)
+ */
+
+#define S_BCM1480_MC_CS0_END                0
+#define M_BCM1480_MC_CS0_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END)
+#define V_BCM1480_MC_CS0_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END)
+#define G_BCM1480_MC_CS0_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END)
+
+#define S_BCM1480_MC_CS1_END                16
+#define M_BCM1480_MC_CS1_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END)
+#define V_BCM1480_MC_CS1_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END)
+#define G_BCM1480_MC_CS1_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END)
+
+#define S_BCM1480_MC_CS2_END                32
+#define M_BCM1480_MC_CS2_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END)
+#define V_BCM1480_MC_CS2_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END)
+#define G_BCM1480_MC_CS2_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END)
+
+#define S_BCM1480_MC_CS3_END                48
+#define M_BCM1480_MC_CS3_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END)
+#define V_BCM1480_MC_CS3_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END)
+#define G_BCM1480_MC_CS3_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END)
+
+/*
+ * Row Address Bit Select Register 0 (Table 84)
+ */
+
+#define S_BCM1480_MC_ROW00                  0
+#define M_BCM1480_MC_ROW00                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW00)
+#define V_BCM1480_MC_ROW00(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00)
+#define G_BCM1480_MC_ROW00(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00)
+
+#define S_BCM1480_MC_ROW01                  8
+#define M_BCM1480_MC_ROW01                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW01)
+#define V_BCM1480_MC_ROW01(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01)
+#define G_BCM1480_MC_ROW01(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01)
+
+#define S_BCM1480_MC_ROW02                  16
+#define M_BCM1480_MC_ROW02                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW02)
+#define V_BCM1480_MC_ROW02(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02)
+#define G_BCM1480_MC_ROW02(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02)
+
+#define S_BCM1480_MC_ROW03                  24
+#define M_BCM1480_MC_ROW03                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW03)
+#define V_BCM1480_MC_ROW03(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03)
+#define G_BCM1480_MC_ROW03(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03)
+
+#define S_BCM1480_MC_ROW04                  32
+#define M_BCM1480_MC_ROW04                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW04)
+#define V_BCM1480_MC_ROW04(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04)
+#define G_BCM1480_MC_ROW04(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04)
+
+#define S_BCM1480_MC_ROW05                  40
+#define M_BCM1480_MC_ROW05                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW05)
+#define V_BCM1480_MC_ROW05(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05)
+#define G_BCM1480_MC_ROW05(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05)
+
+#define S_BCM1480_MC_ROW06                  48
+#define M_BCM1480_MC_ROW06                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW06)
+#define V_BCM1480_MC_ROW06(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06)
+#define G_BCM1480_MC_ROW06(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06)
+
+#define S_BCM1480_MC_ROW07                  56
+#define M_BCM1480_MC_ROW07                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW07)
+#define V_BCM1480_MC_ROW07(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07)
+#define G_BCM1480_MC_ROW07(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07)
+
+/*
+ * Row Address Bit Select Register 1 (Table 85)
+ */
+
+#define S_BCM1480_MC_ROW08                  0
+#define M_BCM1480_MC_ROW08                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW08)
+#define V_BCM1480_MC_ROW08(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08)
+#define G_BCM1480_MC_ROW08(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08)
+
+#define S_BCM1480_MC_ROW09                  8
+#define M_BCM1480_MC_ROW09                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW09)
+#define V_BCM1480_MC_ROW09(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09)
+#define G_BCM1480_MC_ROW09(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09)
+
+#define S_BCM1480_MC_ROW10                  16
+#define M_BCM1480_MC_ROW10                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW10)
+#define V_BCM1480_MC_ROW10(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10)
+#define G_BCM1480_MC_ROW10(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10)
+
+#define S_BCM1480_MC_ROW11                  24
+#define M_BCM1480_MC_ROW11                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW11)
+#define V_BCM1480_MC_ROW11(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11)
+#define G_BCM1480_MC_ROW11(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11)
+
+#define S_BCM1480_MC_ROW12                  32
+#define M_BCM1480_MC_ROW12                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW12)
+#define V_BCM1480_MC_ROW12(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12)
+#define G_BCM1480_MC_ROW12(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12)
+
+#define S_BCM1480_MC_ROW13                  40
+#define M_BCM1480_MC_ROW13                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW13)
+#define V_BCM1480_MC_ROW13(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13)
+#define G_BCM1480_MC_ROW13(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13)
+
+#define S_BCM1480_MC_ROW14                  48
+#define M_BCM1480_MC_ROW14                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW14)
+#define V_BCM1480_MC_ROW14(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14)
+#define G_BCM1480_MC_ROW14(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14)
+
+#define K_BCM1480_MC_ROWX_BIT_SPACING       8
+
+/*
+ * Column Address Bit Select Register 0 (Table 86)
+ */
+
+#define S_BCM1480_MC_COL00                  0
+#define M_BCM1480_MC_COL00                  _SB_MAKEMASK(6,S_BCM1480_MC_COL00)
+#define V_BCM1480_MC_COL00(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL00)
+#define G_BCM1480_MC_COL00(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00)
+
+#define S_BCM1480_MC_COL01                  8
+#define M_BCM1480_MC_COL01                  _SB_MAKEMASK(6,S_BCM1480_MC_COL01)
+#define V_BCM1480_MC_COL01(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL01)
+#define G_BCM1480_MC_COL01(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01)
+
+#define S_BCM1480_MC_COL02                  16
+#define M_BCM1480_MC_COL02                  _SB_MAKEMASK(6,S_BCM1480_MC_COL02)
+#define V_BCM1480_MC_COL02(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL02)
+#define G_BCM1480_MC_COL02(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02)
+
+#define S_BCM1480_MC_COL03                  24
+#define M_BCM1480_MC_COL03                  _SB_MAKEMASK(6,S_BCM1480_MC_COL03)
+#define V_BCM1480_MC_COL03(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL03)
+#define G_BCM1480_MC_COL03(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03)
+
+#define S_BCM1480_MC_COL04                  32
+#define M_BCM1480_MC_COL04                  _SB_MAKEMASK(6,S_BCM1480_MC_COL04)
+#define V_BCM1480_MC_COL04(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL04)
+#define G_BCM1480_MC_COL04(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04)
+
+#define S_BCM1480_MC_COL05                  40
+#define M_BCM1480_MC_COL05                  _SB_MAKEMASK(6,S_BCM1480_MC_COL05)
+#define V_BCM1480_MC_COL05(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL05)
+#define G_BCM1480_MC_COL05(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05)
+
+#define S_BCM1480_MC_COL06                  48
+#define M_BCM1480_MC_COL06                  _SB_MAKEMASK(6,S_BCM1480_MC_COL06)
+#define V_BCM1480_MC_COL06(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL06)
+#define G_BCM1480_MC_COL06(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06)
+
+#define S_BCM1480_MC_COL07                  56
+#define M_BCM1480_MC_COL07                  _SB_MAKEMASK(6,S_BCM1480_MC_COL07)
+#define V_BCM1480_MC_COL07(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL07)
+#define G_BCM1480_MC_COL07(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07)
+
+/*
+ * Column Address Bit Select Register 1 (Table 87)
+ */
+
+#define S_BCM1480_MC_COL08                  0
+#define M_BCM1480_MC_COL08                  _SB_MAKEMASK(6,S_BCM1480_MC_COL08)
+#define V_BCM1480_MC_COL08(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL08)
+#define G_BCM1480_MC_COL08(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08)
+
+#define S_BCM1480_MC_COL09                  8
+#define M_BCM1480_MC_COL09                  _SB_MAKEMASK(6,S_BCM1480_MC_COL09)
+#define V_BCM1480_MC_COL09(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL09)
+#define G_BCM1480_MC_COL09(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09)
+
+#define S_BCM1480_MC_COL10                  16   /* not a valid position, must be prog as 0 */
+
+#define S_BCM1480_MC_COL11                  24
+#define M_BCM1480_MC_COL11                  _SB_MAKEMASK(6,S_BCM1480_MC_COL11)
+#define V_BCM1480_MC_COL11(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL11)
+#define G_BCM1480_MC_COL11(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11)
+
+#define S_BCM1480_MC_COL12                  32
+#define M_BCM1480_MC_COL12                  _SB_MAKEMASK(6,S_BCM1480_MC_COL12)
+#define V_BCM1480_MC_COL12(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL12)
+#define G_BCM1480_MC_COL12(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12)
+
+#define S_BCM1480_MC_COL13                  40
+#define M_BCM1480_MC_COL13                  _SB_MAKEMASK(6,S_BCM1480_MC_COL13)
+#define V_BCM1480_MC_COL13(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL13)
+#define G_BCM1480_MC_COL13(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13)
+
+#define S_BCM1480_MC_COL14                  48
+#define M_BCM1480_MC_COL14                  _SB_MAKEMASK(6,S_BCM1480_MC_COL14)
+#define V_BCM1480_MC_COL14(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL14)
+#define G_BCM1480_MC_COL14(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14)
+
+#define K_BCM1480_MC_COLX_BIT_SPACING       8
+
+/*
+ * CS0 and CS1 Bank Address Bit Select Register (Table 88)
+ */
+
+#define S_BCM1480_MC_CS01_BANK0             0
+#define M_BCM1480_MC_CS01_BANK0             _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0)
+#define V_BCM1480_MC_CS01_BANK0(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0)
+#define G_BCM1480_MC_CS01_BANK0(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0)
+
+#define S_BCM1480_MC_CS01_BANK1             8
+#define M_BCM1480_MC_CS01_BANK1             _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1)
+#define V_BCM1480_MC_CS01_BANK1(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1)
+#define G_BCM1480_MC_CS01_BANK1(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1)
+
+#define S_BCM1480_MC_CS01_BANK2             16
+#define M_BCM1480_MC_CS01_BANK2             _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2)
+#define V_BCM1480_MC_CS01_BANK2(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2)
+#define G_BCM1480_MC_CS01_BANK2(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2)
+
+/*
+ * CS2 and CS3 Bank Address Bit Select Register (Table 89)
+ */
+
+#define S_BCM1480_MC_CS23_BANK0             0
+#define M_BCM1480_MC_CS23_BANK0             _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0)
+#define V_BCM1480_MC_CS23_BANK0(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0)
+#define G_BCM1480_MC_CS23_BANK0(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0)
+
+#define S_BCM1480_MC_CS23_BANK1             8
+#define M_BCM1480_MC_CS23_BANK1             _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1)
+#define V_BCM1480_MC_CS23_BANK1(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1)
+#define G_BCM1480_MC_CS23_BANK1(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1)
+
+#define S_BCM1480_MC_CS23_BANK2             16
+#define M_BCM1480_MC_CS23_BANK2             _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2)
+#define V_BCM1480_MC_CS23_BANK2(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2)
+#define G_BCM1480_MC_CS23_BANK2(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2)
+
+#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
+
+/*
+ * DRAM Command Register (Table 90)
+ */
+
+#define S_BCM1480_MC_COMMAND                0
+#define M_BCM1480_MC_COMMAND                _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND)
+#define V_BCM1480_MC_COMMAND(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND)
+#define G_BCM1480_MC_COMMAND(x)             _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND)
+
+#define K_BCM1480_MC_COMMAND_EMRS           0
+#define K_BCM1480_MC_COMMAND_MRS            1
+#define K_BCM1480_MC_COMMAND_PRE            2
+#define K_BCM1480_MC_COMMAND_AR             3
+#define K_BCM1480_MC_COMMAND_SETRFSH        4
+#define K_BCM1480_MC_COMMAND_CLRRFSH        5
+#define K_BCM1480_MC_COMMAND_SETPWRDN       6
+#define K_BCM1480_MC_COMMAND_CLRPWRDN       7
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_COMMAND_EMRS2          8
+#define K_BCM1480_MC_COMMAND_EMRS3          9
+#define K_BCM1480_MC_COMMAND_ENABLE_MCLK    10
+#define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
+#endif
+
+#define V_BCM1480_MC_COMMAND_EMRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
+#define V_BCM1480_MC_COMMAND_MRS            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
+#define V_BCM1480_MC_COMMAND_PRE            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
+#define V_BCM1480_MC_COMMAND_AR             V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
+#define V_BCM1480_MC_COMMAND_SETRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
+#define V_BCM1480_MC_COMMAND_CLRRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
+#define V_BCM1480_MC_COMMAND_SETPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
+#define V_BCM1480_MC_COMMAND_CLRPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_COMMAND_EMRS2          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
+#define V_BCM1480_MC_COMMAND_EMRS3          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
+#define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
+#define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
+#endif
+
+#define S_BCM1480_MC_CS0                    4
+#define M_BCM1480_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_CS3                    _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_CS4                    _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_CS5                    _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)
+
+#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)
+
+/*
+ * DRAM Mode Register (Table 91)
+ */
+
+#define S_BCM1480_MC_EMODE                  0
+#define M_BCM1480_MC_EMODE                  _SB_MAKEMASK(15,S_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE)
+#define G_BCM1480_MC_EMODE(x)               _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE_DEFAULT          V_BCM1480_MC_EMODE(0)
+
+#define S_BCM1480_MC_MODE                   16
+#define M_BCM1480_MC_MODE                   _SB_MAKEMASK(15,S_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_MODE)
+#define G_BCM1480_MC_MODE(x)                _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE_DEFAULT           V_BCM1480_MC_MODE(0)
+
+#define S_BCM1480_MC_DRAM_TYPE              32
+#define M_BCM1480_MC_DRAM_TYPE              _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE)
+#define V_BCM1480_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE)
+#define G_BCM1480_MC_DRAM_TYPE(x)           _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE)
+
+#define K_BCM1480_MC_DRAM_TYPE_JEDEC        0
+#define K_BCM1480_MC_DRAM_TYPE_FCRAM        1
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_DRAM_TYPE_DDR2         2
+#endif
+
+#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
+#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_DRAM_TYPE_DDR2         V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
+#endif
+
+#define M_BCM1480_MC_GANGED                 _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_BY9_INTF               _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_FORCE_ECC64            _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_ECC_DISABLE            _SB_MAKEMASK1(39)
+
+#define S_BCM1480_MC_PG_POLICY              40
+#define M_BCM1480_MC_PG_POLICY              _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY)
+#define V_BCM1480_MC_PG_POLICY(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY)
+#define G_BCM1480_MC_PG_POLICY(x)           _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY)
+
+#define K_BCM1480_MC_PG_POLICY_CLOSED       0
+#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
+
+#define V_BCM1480_MC_PG_POLICY_CLOSED       V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
+#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_2T_CMD                 _SB_MAKEMASK1(42)
+#define M_BCM1480_MC_ECC_COR_DIS            _SB_MAKEMASK1(43)
+#endif
+
+#define V_BCM1480_MC_DRAMMODE_DEFAULT   V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
+                                V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+
+/*
+ * Memory Clock Configuration Register (Table 92)
+ */
+
+#define S_BCM1480_MC_CLK_RATIO              0
+#define M_BCM1480_MC_CLK_RATIO              _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO)
+#define V_BCM1480_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO)
+#define G_BCM1480_MC_CLK_RATIO(x)           _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO)
+
+#define V_BCM1480_MC_CLK_RATIO_DEFAULT      V_BCM1480_MC_CLK_RATIO(10)
+
+#define S_BCM1480_MC_REF_RATE               8
+#define M_BCM1480_MC_REF_RATE               _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE)
+#define V_BCM1480_MC_REF_RATE(x)            _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE)
+#define G_BCM1480_MC_REF_RATE(x)            _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE)
+
+#define K_BCM1480_MC_REF_RATE_100MHz        0x31
+#define K_BCM1480_MC_REF_RATE_200MHz        0x62
+#define K_BCM1480_MC_REF_RATE_400MHz        0xC4
+
+#define V_BCM1480_MC_REF_RATE_100MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
+#define V_BCM1480_MC_REF_RATE_200MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
+#define V_BCM1480_MC_REF_RATE_400MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
+#define V_BCM1480_MC_REF_RATE_DEFAULT       V_BCM1480_MC_REF_RATE_400MHz
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_AUTO_REF_DIS           _SB_MAKEMASK1(16)
+#endif
+
+/*
+ * ODT Register (Table 99)
+ */
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_RD_ODT0_CS0            _SB_MAKEMASK1(0)
+#define M_BCM1480_MC_RD_ODT0_CS2            _SB_MAKEMASK1(1)
+#define M_BCM1480_MC_RD_ODT0_CS4            _SB_MAKEMASK1(2)
+#define M_BCM1480_MC_RD_ODT0_CS6            _SB_MAKEMASK1(3)
+#define M_BCM1480_MC_WR_ODT0_CS0            _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_WR_ODT0_CS2            _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_WR_ODT0_CS4            _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_WR_ODT0_CS6            _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_RD_ODT2_CS0            _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RD_ODT2_CS2            _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_RD_ODT2_CS4            _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_RD_ODT2_CS6            _SB_MAKEMASK1(11)
+#define M_BCM1480_MC_WR_ODT2_CS0            _SB_MAKEMASK1(12)
+#define M_BCM1480_MC_WR_ODT2_CS2            _SB_MAKEMASK1(13)
+#define M_BCM1480_MC_WR_ODT2_CS4            _SB_MAKEMASK1(14)
+#define M_BCM1480_MC_WR_ODT2_CS6            _SB_MAKEMASK1(15)
+#define M_BCM1480_MC_RD_ODT4_CS0            _SB_MAKEMASK1(16)
+#define M_BCM1480_MC_RD_ODT4_CS2            _SB_MAKEMASK1(17)
+#define M_BCM1480_MC_RD_ODT4_CS4            _SB_MAKEMASK1(18)
+#define M_BCM1480_MC_RD_ODT4_CS6            _SB_MAKEMASK1(19)
+#define M_BCM1480_MC_WR_ODT4_CS0            _SB_MAKEMASK1(20)
+#define M_BCM1480_MC_WR_ODT4_CS2            _SB_MAKEMASK1(21)
+#define M_BCM1480_MC_WR_ODT4_CS4            _SB_MAKEMASK1(22)
+#define M_BCM1480_MC_WR_ODT4_CS6            _SB_MAKEMASK1(23)
+#define M_BCM1480_MC_RD_ODT6_CS0            _SB_MAKEMASK1(24)
+#define M_BCM1480_MC_RD_ODT6_CS2            _SB_MAKEMASK1(25)
+#define M_BCM1480_MC_RD_ODT6_CS4            _SB_MAKEMASK1(26)
+#define M_BCM1480_MC_RD_ODT6_CS6            _SB_MAKEMASK1(27)
+#define M_BCM1480_MC_WR_ODT6_CS0            _SB_MAKEMASK1(28)
+#define M_BCM1480_MC_WR_ODT6_CS2            _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_WR_ODT6_CS4            _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_WR_ODT6_CS6            _SB_MAKEMASK1(31)
+
+#define M_BCM1480_MC_CS_ODD_ODT_EN          _SB_MAKEMASK1(32)
+#endif
+
+/*
+ * Memory DLL Configuration Register (Table 93)
+ */
+
+#define S_BCM1480_MC_ADDR_COARSE_ADJ         0
+#define M_BCM1480_MC_ADDR_COARSE_ADJ         _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_ADDR_FREQ_RANGE            8
+#define M_BCM1480_MC_ADDR_FREQ_RANGE            _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT    V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_ADDR_FINE_ADJ          8
+#define M_BCM1480_MC_ADDR_FINE_ADJ          _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ)
+#define G_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
+
+#define S_BCM1480_MC_DQI_COARSE_ADJ         16
+#define M_BCM1480_MC_DQI_COARSE_ADJ         _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ)
+#define G_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQI_FREQ_RANGE             24
+#define M_BCM1480_MC_DQI_FREQ_RANGE             _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE)
+#define G_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DQI_FINE_ADJ           24
+#define M_BCM1480_MC_DQI_FINE_ADJ           _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ)
+#define G_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
+
+#define S_BCM1480_MC_DQO_COARSE_ADJ         32
+#define M_BCM1480_MC_DQO_COARSE_ADJ         _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ)
+#define G_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQO_FREQ_RANGE             40
+#define M_BCM1480_MC_DQO_FREQ_RANGE             _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE)
+#define G_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DQO_FINE_ADJ           40
+#define M_BCM1480_MC_DQO_FINE_ADJ           _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ)
+#define G_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_PDSEL            44
+#define M_BCM1480_MC_DLL_PDSEL            _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_PDSEL(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL)
+#define G_BCM1480_MC_DLL_PDSEL(x)         _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_DEFAULT_PDSEL    V_BCM1480_MC_DLL_PDSEL(0x0)
+
+#define M_BCM1480_MC_DLL_REGBYPASS        _SB_MAKEMASK1(46)
+#define M_BCM1480_MC_DQO_SHIFT            _SB_MAKEMASK1(47)
+#endif
+
+#define S_BCM1480_MC_DLL_DEFAULT            48
+#define M_BCM1480_MC_DLL_DEFAULT            _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
+#define G_BCM1480_MC_DLL_DEFAULT(x)         _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT    V_BCM1480_MC_DLL_DEFAULT(0x10)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_REGCTRL          54
+#define M_BCM1480_MC_DLL_REGCTRL          _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_REGCTRL(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL)
+#define G_BCM1480_MC_DLL_REGCTRL(x)       _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
+#endif
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_FREQ_RANGE             56
+#define M_BCM1480_MC_DLL_FREQ_RANGE             _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE)
+#define G_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DLL_STEP_SIZE          56
+#define M_BCM1480_MC_DLL_STEP_SIZE          _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE)
+#define G_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_BGCTRL   60
+#define M_BCM1480_MC_DLL_BGCTRL           _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_BGCTRL(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL)
+#define G_BCM1480_MC_DLL_BGCTRL(x)       _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL  V_BCM1480_MC_DLL_BGCTRL(0x0)
+#endif
+
+#define M_BCM1480_MC_DLL_BYPASS             _SB_MAKEMASK1(63)
+
+/*
+ * Memory Drive Configuration Register (Table 94)
+ */
+
+#define S_BCM1480_MC_RTT_BYP_PULLDOWN       0
+#define M_BCM1480_MC_RTT_BYP_PULLDOWN       _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN)
+
+#define S_BCM1480_MC_RTT_BYP_PULLUP         6
+#define M_BCM1480_MC_RTT_BYP_PULLUP         _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP)
+#define V_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP)
+#define G_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP)
+
+#define M_BCM1480_MC_RTT_BYPASS             _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RTT_COMP_MOV_AVG       _SB_MAKEMASK1(9)
+
+#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
+#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+
+#define S_BCM1480_MC_PVT_BYP_C1_PULLUP      15
+#define M_BCM1480_MC_PVT_BYP_C1_PULLUP      _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP)
+
+#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN    20
+#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN    _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+
+#define S_BCM1480_MC_PVT_BYP_C2_PULLUP      25
+#define M_BCM1480_MC_PVT_BYP_C2_PULLUP      _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP)
+
+#define M_BCM1480_MC_PVT_BYPASS             _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_PVT_COMP_MOV_AVG       _SB_MAKEMASK1(31)
+
+#define M_BCM1480_MC_CLK_CLASS              _SB_MAKEMASK1(34)
+#define M_BCM1480_MC_DATA_CLASS             _SB_MAKEMASK1(35)
+#define M_BCM1480_MC_ADDR_CLASS             _SB_MAKEMASK1(36)
+
+#define M_BCM1480_MC_DQ_ODT_75              _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_DQ_ODT_150             _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_DQS_ODT_75             _SB_MAKEMASK1(39)
+#define M_BCM1480_MC_DQS_ODT_150            _SB_MAKEMASK1(40)
+#define M_BCM1480_MC_DQS_DIFF               _SB_MAKEMASK1(41)
+
+/*
+ * ECC Test Data Register (Table 95)
+ */
+
+#define S_BCM1480_MC_DATA_INVERT            0
+#define M_DATA_ECC_INVERT           _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT)
+
+/*
+ * ECC Test ECC Register (Table 96)
+ */
+
+#define S_BCM1480_MC_ECC_INVERT             0
+#define M_BCM1480_MC_ECC_INVERT             _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT)
+
+/*
+ * SDRAM Timing Register  (Table 97)
+ */
+
+#define S_BCM1480_MC_tRCD                   0
+#define M_BCM1480_MC_tRCD                   _SB_MAKEMASK(4,S_BCM1480_MC_tRCD)
+#define V_BCM1480_MC_tRCD(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD)
+#define G_BCM1480_MC_tRCD(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD)
+#define K_BCM1480_MC_tRCD_DEFAULT           3
+#define V_BCM1480_MC_tRCD_DEFAULT           V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
+
+#define S_BCM1480_MC_tCL                    4
+#define M_BCM1480_MC_tCL                    _SB_MAKEMASK(4,S_BCM1480_MC_tCL)
+#define V_BCM1480_MC_tCL(x)                 _SB_MAKEVALUE(x,S_BCM1480_MC_tCL)
+#define G_BCM1480_MC_tCL(x)                 _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL)
+#define K_BCM1480_MC_tCL_DEFAULT            2
+#define V_BCM1480_MC_tCL_DEFAULT            V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
+
+#define M_BCM1480_MC_tCrDh                  _SB_MAKEMASK1(8)
+
+#define S_BCM1480_MC_tWR                    9
+#define M_BCM1480_MC_tWR                    _SB_MAKEMASK(3,S_BCM1480_MC_tWR)
+#define V_BCM1480_MC_tWR(x)                 _SB_MAKEVALUE(x,S_BCM1480_MC_tWR)
+#define G_BCM1480_MC_tWR(x)                 _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR)
+#define K_BCM1480_MC_tWR_DEFAULT            2
+#define V_BCM1480_MC_tWR_DEFAULT            V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
+
+#define S_BCM1480_MC_tCwD                   12
+#define M_BCM1480_MC_tCwD                   _SB_MAKEMASK(4,S_BCM1480_MC_tCwD)
+#define V_BCM1480_MC_tCwD(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD)
+#define G_BCM1480_MC_tCwD(x)                _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD)
+#define K_BCM1480_MC_tCwD_DEFAULT           1
+#define V_BCM1480_MC_tCwD_DEFAULT           V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
+
+#define S_BCM1480_MC_tRP                    16
+#define M_BCM1480_MC_tRP                    _SB_MAKEMASK(4,S_BCM1480_MC_tRP)
+#define V_BCM1480_MC_tRP(x)                 _SB_MAKEVALUE(x,S_BCM1480_MC_tRP)
+#define G_BCM1480_MC_tRP(x)                 _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP)
+#define K_BCM1480_MC_tRP_DEFAULT            4
+#define V_BCM1480_MC_tRP_DEFAULT            V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
+
+#define S_BCM1480_MC_tRRD                   20
+#define M_BCM1480_MC_tRRD                   _SB_MAKEMASK(4,S_BCM1480_MC_tRRD)
+#define V_BCM1480_MC_tRRD(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD)
+#define G_BCM1480_MC_tRRD(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD)
+#define K_BCM1480_MC_tRRD_DEFAULT           2
+#define V_BCM1480_MC_tRRD_DEFAULT           V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
+
+#define S_BCM1480_MC_tRCw                   24
+#define M_BCM1480_MC_tRCw                   _SB_MAKEMASK(5,S_BCM1480_MC_tRCw)
+#define V_BCM1480_MC_tRCw(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw)
+#define G_BCM1480_MC_tRCw(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw)
+#define K_BCM1480_MC_tRCw_DEFAULT           10
+#define V_BCM1480_MC_tRCw_DEFAULT           V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
+
+#define S_BCM1480_MC_tRCr                   32
+#define M_BCM1480_MC_tRCr                   _SB_MAKEMASK(5,S_BCM1480_MC_tRCr)
+#define V_BCM1480_MC_tRCr(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr)
+#define G_BCM1480_MC_tRCr(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr)
+#define K_BCM1480_MC_tRCr_DEFAULT           9
+#define V_BCM1480_MC_tRCr_DEFAULT           V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_tFAW                   40
+#define M_BCM1480_MC_tFAW                   _SB_MAKEMASK(6,S_BCM1480_MC_tFAW)
+#define V_BCM1480_MC_tFAW(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW)
+#define G_BCM1480_MC_tFAW(x)                _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW)
+#define K_BCM1480_MC_tFAW_DEFAULT           0
+#define V_BCM1480_MC_tFAW_DEFAULT           V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
+#endif
+
+#define S_BCM1480_MC_tRFC                   48
+#define M_BCM1480_MC_tRFC                   _SB_MAKEMASK(7,S_BCM1480_MC_tRFC)
+#define V_BCM1480_MC_tRFC(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC)
+#define G_BCM1480_MC_tRFC(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC)
+#define K_BCM1480_MC_tRFC_DEFAULT           12
+#define V_BCM1480_MC_tRFC_DEFAULT           V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
+
+#define S_BCM1480_MC_tFIFO                  56
+#define M_BCM1480_MC_tFIFO                  _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO)
+#define V_BCM1480_MC_tFIFO(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO)
+#define G_BCM1480_MC_tFIFO(x)               _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO)
+#define K_BCM1480_MC_tFIFO_DEFAULT          0
+#define V_BCM1480_MC_tFIFO_DEFAULT          V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
+
+#define S_BCM1480_MC_tW2R                  58
+#define M_BCM1480_MC_tW2R                  _SB_MAKEMASK(2,S_BCM1480_MC_tW2R)
+#define V_BCM1480_MC_tW2R(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R)
+#define G_BCM1480_MC_tW2R(x)               _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R)
+#define K_BCM1480_MC_tW2R_DEFAULT          1
+#define V_BCM1480_MC_tW2R_DEFAULT          V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
+
+#define S_BCM1480_MC_tR2W                  60
+#define M_BCM1480_MC_tR2W                  _SB_MAKEMASK(2,S_BCM1480_MC_tR2W)
+#define V_BCM1480_MC_tR2W(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W)
+#define G_BCM1480_MC_tR2W(x)               _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W)
+#define K_BCM1480_MC_tR2W_DEFAULT          0
+#define V_BCM1480_MC_tR2W_DEFAULT          V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
+
+#define M_BCM1480_MC_tR2R                   _SB_MAKEMASK1(62)
+
+#define V_BCM1480_MC_TIMING_DEFAULT         (M_BCM1480_MC_tR2R | \
+                                     V_BCM1480_MC_tFIFO_DEFAULT | \
+                                     V_BCM1480_MC_tR2W_DEFAULT | \
+                                     V_BCM1480_MC_tW2R_DEFAULT | \
+                                     V_BCM1480_MC_tRFC_DEFAULT | \
+                                     V_BCM1480_MC_tRCr_DEFAULT | \
+                                     V_BCM1480_MC_tRCw_DEFAULT | \
+                                     V_BCM1480_MC_tRRD_DEFAULT | \
+                                     V_BCM1480_MC_tRP_DEFAULT | \
+                                     V_BCM1480_MC_tCwD_DEFAULT | \
+                                     V_BCM1480_MC_tWR_DEFAULT | \
+                                     M_BCM1480_MC_tCrDh | \
+                                     V_BCM1480_MC_tCL_DEFAULT | \
+                                     V_BCM1480_MC_tRCD_DEFAULT)
+
+/*
+ * SDRAM Timing Register 2
+ */
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+
+#define S_BCM1480_MC_tAL                   0
+#define M_BCM1480_MC_tAL                   _SB_MAKEMASK(4,S_BCM1480_MC_tAL)
+#define V_BCM1480_MC_tAL(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tAL)
+#define G_BCM1480_MC_tAL(x)                _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL)
+#define K_BCM1480_MC_tAL_DEFAULT           0
+#define V_BCM1480_MC_tAL_DEFAULT           V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
+
+#define S_BCM1480_MC_tRTP                   4
+#define M_BCM1480_MC_tRTP                   _SB_MAKEMASK(3,S_BCM1480_MC_tRTP)
+#define V_BCM1480_MC_tRTP(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP)
+#define G_BCM1480_MC_tRTP(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP)
+#define K_BCM1480_MC_tRTP_DEFAULT           2
+#define V_BCM1480_MC_tRTP_DEFAULT           V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
+
+#define S_BCM1480_MC_tW2W                   8
+#define M_BCM1480_MC_tW2W                   _SB_MAKEMASK(2,S_BCM1480_MC_tW2W)
+#define V_BCM1480_MC_tW2W(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W)
+#define G_BCM1480_MC_tW2W(x)                _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W)
+#define K_BCM1480_MC_tW2W_DEFAULT           0
+#define V_BCM1480_MC_tW2W_DEFAULT           V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
+
+#define S_BCM1480_MC_tRAP                   12
+#define M_BCM1480_MC_tRAP                  _SB_MAKEMASK(4,S_BCM1480_MC_tRAP)
+#define V_BCM1480_MC_tRAP(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP)
+#define G_BCM1480_MC_tRAP(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP)
+#define K_BCM1480_MC_tRAP_DEFAULT           0
+#define V_BCM1480_MC_tRAP_DEFAULT           V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
+
+#endif
+
+
+
+/*
+ * Global Registers: single instances per BCM1480
+ */
+
+/*
+ * Global Configuration Register (Table 99)
+ */
+
+#define S_BCM1480_MC_BLK_SET_MARK           8
+#define M_BCM1480_MC_BLK_SET_MARK           _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK)
+#define V_BCM1480_MC_BLK_SET_MARK(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK)
+#define G_BCM1480_MC_BLK_SET_MARK(x)        _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK)
+
+#define S_BCM1480_MC_BLK_CLR_MARK           12
+#define M_BCM1480_MC_BLK_CLR_MARK           _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK)
+#define V_BCM1480_MC_BLK_CLR_MARK(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK)
+#define G_BCM1480_MC_BLK_CLR_MARK(x)        _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK)
+
+#define M_BCM1480_MC_PKT_PRIORITY           _SB_MAKEMASK1(16)
+
+#define S_BCM1480_MC_MAX_AGE                20
+#define M_BCM1480_MC_MAX_AGE                _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE)
+#define V_BCM1480_MC_MAX_AGE(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE)
+#define G_BCM1480_MC_MAX_AGE(x)             _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE)
+
+#define M_BCM1480_MC_BERR_DISABLE           _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_FORCE_SEQ              _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_VGEN                   _SB_MAKEMASK1(32)
+
+#define S_BCM1480_MC_SLEW                   33
+#define M_BCM1480_MC_SLEW                   _SB_MAKEMASK(2,S_BCM1480_MC_SLEW)
+#define V_BCM1480_MC_SLEW(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW)
+#define G_BCM1480_MC_SLEW(x)                _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW)
+
+#define M_BCM1480_MC_SSTL_VOLTAGE           _SB_MAKEMASK1(35)
+
+/*
+ * Global Channel Interleave Register (Table 100)
+ */
+
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0)
+
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1)
+
+#define S_BCM1480_MC_INTLV_MODE             16
+#define M_BCM1480_MC_INTLV_MODE             _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE)
+#define V_BCM1480_MC_INTLV_MODE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE)
+#define G_BCM1480_MC_INTLV_MODE(x)          _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE)
+
+#define K_BCM1480_MC_INTLV_MODE_NONE        0x0
+#define K_BCM1480_MC_INTLV_MODE_01          0x1
+#define K_BCM1480_MC_INTLV_MODE_23          0x2
+#define K_BCM1480_MC_INTLV_MODE_01_23       0x3
+#define K_BCM1480_MC_INTLV_MODE_0123        0x4
+
+#define V_BCM1480_MC_INTLV_MODE_NONE        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
+#define V_BCM1480_MC_INTLV_MODE_01          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
+#define V_BCM1480_MC_INTLV_MODE_23          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
+#define V_BCM1480_MC_INTLV_MODE_01_23       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
+#define V_BCM1480_MC_INTLV_MODE_0123        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
+
+/*
+ * ECC Status Register
+ */
+
+#define S_BCM1480_MC_ECC_ERR_ADDR           0
+#define M_BCM1480_MC_ECC_ERR_ADDR           _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR)
+#define V_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR)
+#define G_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_ECC_ERR_RMW            _SB_MAKEMASK1(60)
+#endif
+
+#define M_BCM1480_MC_ECC_MULT_ERR_DET       _SB_MAKEMASK1(61)
+#define M_BCM1480_MC_ECC_UERR_DET           _SB_MAKEMASK1(62)
+#define M_BCM1480_MC_ECC_CERR_DET           _SB_MAKEMASK1(63)
+
+/*
+ * Global ECC Address Register (Table 102)
+ */
+
+#define S_BCM1480_MC_ECC_CORR_ADDR          0
+#define M_BCM1480_MC_ECC_CORR_ADDR          _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR)
+#define V_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR)
+#define G_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR)
+
+/*
+ * Global ECC Correction Register (Table 103)
+ */
+
+#define S_BCM1480_MC_ECC_CORRECT            0
+#define M_BCM1480_MC_ECC_CORRECT            _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT)
+#define V_BCM1480_MC_ECC_CORRECT(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT)
+#define G_BCM1480_MC_ECC_CORRECT(x)         _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT)
+
+/*
+ * Global ECC Performance Counters Control Register (Table 104)
+ */
+
+#define S_BCM1480_MC_CHANNEL_SELECT         0
+#define M_BCM1480_MC_CHANNEL_SELECT         _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT)
+#define V_BCM1480_MC_CHANNEL_SELECT(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT)
+#define G_BCM1480_MC_CHANNEL_SELECT(x)      _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT)
+#define K_BCM1480_MC_CHANNEL_SELECT_0       0x1
+#define K_BCM1480_MC_CHANNEL_SELECT_1       0x2
+#define K_BCM1480_MC_CHANNEL_SELECT_2       0x4
+#define K_BCM1480_MC_CHANNEL_SELECT_3       0x8
+
+#endif /* _BCM1480_MC_H */
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
new file mode 100644
index 000000000000..c2dd2fe3047c
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -0,0 +1,869 @@
+/*  *********************************************************************
+    *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
+    *
+    *  Register Definitions                     File: bcm1480_regs.h
+    *
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the BCM1280 and BCM1480.
+    *
+    *  BCM1480 specification level:  1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _BCM1480_REGS_H
+#define _BCM1480_REGS_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Pull in the BCM1250's registers since a great deal of the 1480's
+    *  functions are the same as the BCM1250.
+    ********************************************************************* */
+
+#include "sb1250_regs.h"
+
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  Register addresses are grouped by function and follow the order
+    *  of the User Manual.
+    *
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.
+    *
+    *  The information in this file is based on the BCM1X55/BCM1X80
+    *  User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+
+
+/*  *********************************************************************
+    * Memory Controller Registers (Section 6)
+    ********************************************************************* */
+
+#define A_BCM1480_MC_BASE_0                 0x0010050000
+#define A_BCM1480_MC_BASE_1                 0x0010051000
+#define A_BCM1480_MC_BASE_2                 0x0010052000
+#define A_BCM1480_MC_BASE_3                 0x0010053000
+#define BCM1480_MC_REGISTER_SPACING         0x1000
+
+#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
+#define A_BCM1480_MC_REGISTER(ctlid,reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
+
+#define R_BCM1480_MC_CONFIG                 0x0000000100
+#define R_BCM1480_MC_CS_START               0x0000000120
+#define R_BCM1480_MC_CS_END                 0x0000000140
+#define S_BCM1480_MC_CS_STARTEND            24
+
+#define R_BCM1480_MC_CS01_ROW0              0x0000000180
+#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
+#define R_BCM1480_MC_CS23_ROW0              0x0000000200
+#define R_BCM1480_MC_CS23_ROW1              0x0000000220
+#define R_BCM1480_MC_CS01_COL0              0x0000000280
+#define R_BCM1480_MC_CS01_COL1              0x00000002A0
+#define R_BCM1480_MC_CS23_COL0              0x0000000300
+#define R_BCM1480_MC_CS23_COL1              0x0000000320
+
+#define R_BCM1480_MC_CSX_BASE               0x0000000180
+#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
+#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */
+
+#define R_BCM1480_MC_CS01_BA                0x0000000380
+#define R_BCM1480_MC_CS23_BA                0x00000003A0
+#define R_BCM1480_MC_DRAMCMD                0x0000000400
+#define R_BCM1480_MC_DRAMMODE               0x0000000420
+#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
+#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
+#define R_BCM1480_MC_TEST_DATA              0x0000000480
+#define R_BCM1480_MC_TEST_ECC               0x00000004A0
+#define R_BCM1480_MC_TIMING1                0x00000004C0
+#define R_BCM1480_MC_TIMING2                0x00000004E0
+#define R_BCM1480_MC_DLL_CFG                0x0000000500
+#define R_BCM1480_MC_DRIVE_CFG              0x0000000520
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define R_BCM1480_MC_ODT                    0x0000000460
+#define R_BCM1480_MC_ECC_STATUS             0x0000000540
+#endif
+
+/* Global registers (single instance) */
+#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
+#define A_BCM1480_MC_GLB_INTLV              0x0010054120
+#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
+#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
+#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
+#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
+
+/*  *********************************************************************
+    * L2 Cache Control Registers (Section 5)
+    ********************************************************************* */
+
+#define A_BCM1480_L2_BASE                   0x0010040000
+
+#define A_BCM1480_L2_READ_TAG               0x0010040018
+#define A_BCM1480_L2_ECC_TAG                0x0010040038
+#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
+#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
+#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
+#define A_BCM1480_L2_MISC_CONFIG            0x0010040040        /* x040 */
+#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060        /* x060 */
+#define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080        /* x080 */
+#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0        /* x0A0 */
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100        /* x100 */
+#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120        /* x120 */
+#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140        /* x140 */
+#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160        /* x160 */
+#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0        /* xxC0 */
+#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0        /* xxE0 */
+#define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
+#define A_BCM1480_L2_BANK_BASE              0x00D0300000
+#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
+#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000
+
+
+/*  *********************************************************************
+    * PCI-X Interface Registers (Section 7)
+    ********************************************************************* */
+
+#define A_BCM1480_PCI_BASE                  0x0010061400
+
+#define A_BCM1480_PCI_RESET                 0x0010061400
+#define A_BCM1480_PCI_DLL                   0x0010061500
+
+#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000
+
+/*  *********************************************************************
+    * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
+    ********************************************************************* */
+
+/* No register changes with Rev.C BCM1250, but one additional MAC */
+
+#define A_BCM1480_MAC_BASE_2        0x0010066000
+
+#ifndef A_MAC_BASE_2
+#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
+#endif
+
+#define A_BCM1480_MAC_BASE_3        0x0010067000
+#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3
+
+#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038
+
+#ifndef R_MAC_DMA_OODPKTLOST
+#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
+#endif
+
+
+/*  *********************************************************************
+    * DUART Registers (Section 14)
+    ********************************************************************* */
+
+/* No significant differences from BCM1250, two DUARTs */
+
+/*  Conventions, per user manual:
+ *     DUART    generic, channels A,B,C,D
+ *     DUART0   implementing channels A,B
+ *     DUART1   inplementing channels C,D
+ */
+
+#define BCM1480_DUART_NUM_PORTS           4
+
+#define A_BCM1480_DUART0                    0x0010060000
+#define A_BCM1480_DUART1                    0x0010060400
+#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
+
+#define BCM1480_DUART_CHANREG_SPACING       0x100
+#define A_BCM1480_DUART_CHANREG(chan,reg)   (A_BCM1480_DUART(chan) \
+                                     + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \
+                                     + (reg))
+#define R_BCM1480_DUART_CHANREG(chan,reg)   (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg))
+
+#define R_BCM1480_DUART_IMRREG(chan)        (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_ISRREG(chan)        (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING)
+
+#define A_BCM1480_DUART_IMRREG(chan)        (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
+#define A_BCM1480_DUART_ISRREG(chan)        (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
+
+/*
+ * These constants are the absolute addresses.
+ */
+
+#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
+#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
+#define A_BCM1480_DUART_STATUS_C            0x0010060420
+#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
+#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
+#define A_BCM1480_DUART_CMD_C               0x0010060450
+#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
+#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
+#define A_BCM1480_DUART_OPCR_C              0x0010060480
+#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490
+
+#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
+#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
+#define A_BCM1480_DUART_STATUS_D            0x0010060520
+#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
+#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
+#define A_BCM1480_DUART_CMD_D               0x0010060550
+#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
+#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
+#define A_BCM1480_DUART_OPCR_D              0x0010060580
+#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590
+
+#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
+#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
+#define A_BCM1480_DUART_ISR_C               0x0010060620
+#define A_BCM1480_DUART_IMR_C               0x0010060630
+#define A_BCM1480_DUART_ISR_D               0x0010060640
+#define A_BCM1480_DUART_IMR_D               0x0010060650
+#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
+#define A_BCM1480_DUART_OPCR_CD             0x0010060670
+#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
+#define A_BCM1480_DUART_ISR_CD              0x0010060690
+#define A_BCM1480_DUART_IMR_CD              0x00100606A0
+#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
+#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
+#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
+#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0
+
+
+/*  *********************************************************************
+    * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
+    ********************************************************************* */
+
+#define A_BCM1480_IO_PCMCIA_CFG_B       0x0010061A58
+#define A_BCM1480_IO_PCMCIA_STATUS_B    0x0010061A68
+
+/*  *********************************************************************
+    * GPIO Registers (Section 17)
+    ********************************************************************* */
+
+/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
+
+#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
+#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)
+
+#define A_GPIO_INT_ADD_TYPE     A_BCM1480_GPIO_INT_ADD_TYPE
+#define R_GPIO_INT_ADD_TYPE     R_BCM1480_GPIO_INT_ADD_TYPE
+
+/*  *********************************************************************
+    * SMBus Registers (Section 18)
+    ********************************************************************* */
+
+/* No changes from BCM1250 */
+
+/*  *********************************************************************
+    * Timer Registers (Sections 4.6)
+    ********************************************************************* */
+
+/* BCM1480 has two additional watchdogs */
+
+/* Watchdog timers */
+
+#define A_BCM1480_SCD_WDOG_2                0x0010022050
+#define A_BCM1480_SCD_WDOG_3                0x0010022150
+
+#define BCM1480_SCD_NUM_WDOGS               4
+
+#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
+#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
+
+#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
+#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
+#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060
+
+#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
+#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
+#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160
+
+/* BCM1480 has two additional compare registers */
+
+#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT         A_SCD_ZBBUS_CYCLE_COUNT
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18
+
+/*  *********************************************************************
+    * System Control Registers (Section 4.2)
+    ********************************************************************* */
+
+/* Scratch register in different place */
+
+#define A_BCM1480_SCD_SCRATCH           0x100200A0
+
+/*  *********************************************************************
+    * System Address Trap Registers (Section 4.9)
+    ********************************************************************* */
+
+/* No changes from BCM1250 */
+
+/*  *********************************************************************
+    * System Interrupt Mapper Registers (Sections 4.3-4.5)
+    ********************************************************************* */
+
+#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
+#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
+#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
+#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
+#define BCM1480_IMR_REGISTER_SPACING        0x2000
+#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
+
+#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
+#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
+
+/* Most IMR registers are 128 bits, implemented as non-contiguous
+   64-bit registers high (_H) and low (_L) */
+#define BCM1480_IMR_HL_SPACING                  0x1000
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
+#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
+#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
+#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
+#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
+#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
+#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
+#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
+#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
+#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
+#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
+#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
+#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200
+
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
+#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100
+
+#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
+                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
+#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
+
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000          /* 0x0x0 */
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008          /* 0x0x8 */
+
+/*  *********************************************************************
+    * System Performance Counter Registers (Section 4.7)
+    ********************************************************************* */
+
+/* BCM1480 has four more performance counter registers, and two control
+   registers. */
+
+#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0
+
+#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
+#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
+#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1
+
+#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
+#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
+#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
+#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3
+
+#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
+#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
+#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
+#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508
+
+/*  *********************************************************************
+    * System Bus Watcher Registers (Section 4.8)
+    ********************************************************************* */
+
+
+/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
+
+#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8
+
+/*  *********************************************************************
+    * System Debug Controller Registers (Section 19)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+/*  *********************************************************************
+    * System Trace Unit Registers (Sections 4.10)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+/*  *********************************************************************
+    * Data Mover DMA Registers (Section 10.7)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+
+/*  *********************************************************************
+    * HyperTransport Interface Registers (Section 8)
+    ********************************************************************* */
+
+#define BCM1480_HT_NUM_PORTS               3
+#define BCM1480_HT_PORT_SPACING            0x800
+#define A_BCM1480_HT_PORT_HEADER(x)        (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
+
+#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
+#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
+#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
+#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000
+
+
+/*  *********************************************************************
+    * Node Controller Registers (Section 9)
+    ********************************************************************* */
+
+#define A_BCM1480_NC_BASE                   0x00DFBD0000
+
+#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
+#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
+#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
+#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
+#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
+#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
+#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0
+
+#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
+#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
+#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
+#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
+
+#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
+#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
+#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
+#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
+#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
+#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
+#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
+#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
+#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
+#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
+#define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
+#define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
+#define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
+
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
+
+
+/*  *********************************************************************
+    * H&R Block Configuration Registers (Section 12.4)
+    ********************************************************************* */
+
+#define A_BCM1480_HR_BASE_0                 0x00DF820000
+#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
+#define A_BCM1480_HR_BASE_2                 0x00DF920000
+#define BCM1480_HR_REGISTER_SPACING         0x80000
+
+#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
+#define A_BCM1480_HR_REGISTER(idx,reg)      (A_BCM1480_HR_BASE(idx) + (reg))
+
+#define R_BCM1480_HR_CFG                    0x0000000000
+
+#define R_BCM1480_HR_MAPPING                0x0000010010
+
+#define BCM1480_HR_RULE_SPACING             0x0000000010
+#define BCM1480_HR_NUM_RULES                16
+#define BCM1480_HR_OP_OFFSET                0x0000000100
+#define BCM1480_HR_TYPE_OFFSET              0x0000000108
+#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+
+#define BCM1480_HR_LEAF_SPACING             0x0000000010
+#define BCM1480_HR_NUM_LEAVES               10
+#define BCM1480_HR_LEAF_OFFSET              0x0000000300
+#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
+
+#define R_BCM1480_HR_EX_LEAF0               0x00000003A0
+
+#define BCM1480_HR_PATH_SPACING             0x0000000010
+#define BCM1480_HR_NUM_PATHS                16
+#define BCM1480_HR_PATH_OFFSET              0x0000000600
+#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
+
+#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700
+
+#define BCM1480_HR_ROUTE_SPACING            8
+#define BCM1480_HR_NUM_ROUTES               512
+#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
+#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
+
+
+/* checked to here - ehs */
+/*  *********************************************************************
+    * Packet Manager DMA Registers (Section 12.5)
+    ********************************************************************* */
+
+#define A_BCM1480_PM_BASE                   0x0010056000
+
+#define A_BCM1480_PMI_LCL_0                 0x0010058000
+#define A_BCM1480_PMO_LCL_0                 0x001005C000
+#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
+
+#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
+#define BCM1480_PM_NUM_CHANNELS             32
+
+#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMI_LCL_REGISTER(idx,reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
+#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMO_LCL_REGISTER(idx,reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
+
+#define BCM1480_PM_INT_PACKING              8
+#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
+#define BCM1480_PM_INT_NUM_FUNCTIONS        3
+
+/*
+ * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
+ */
+
+#define R_BCM1480_PM_BASE_SIZE              0x0000000000
+#define R_BCM1480_PM_CNT                    0x0000000008
+#define R_BCM1480_PM_PFCNT                  0x0000000010
+#define R_BCM1480_PM_LAST                   0x0000000018
+#define R_BCM1480_PM_PFINDX                 0x0000000020
+#define R_BCM1480_PM_INT_WMK                0x0000000028
+#define R_BCM1480_PM_CONFIG0                0x0000000030
+#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
+#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
+#define R_BCM1480_PM_INT_CNFG               0x0000000088
+#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
+#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
+#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */
+
+/*
+ * Global Registers (Not Channelized)
+ */
+
+#define A_BCM1480_PMI_GLB_0                 0x0010056000
+#define A_BCM1480_PMO_GLB_0                 0x0010057000
+
+/*
+ * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
+ */
+
+#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */
+
+#define A_BCM1480_PM_PMO_MAPPING        (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
+
+/*
+ * Interrupt mapping registers
+ */
+
+
+#define A_BCM1480_PMI_INT_0                 0x0010056800
+#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_INT_0                 0x0010057800
+#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
+
+/*
+ * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
+ */
+
+#define R_BCM1480_PM_INT_ST                 0x0000000000
+#define R_BCM1480_PM_INT_MSK                0x0000000040
+#define R_BCM1480_PM_INT_CLR                0x0000000080
+#define R_BCM1480_PM_MRGD_INT               0x00000000C0
+
+/*
+ * Debug registers (global)
+ */
+
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
+#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
+#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
+#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
+#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8
+
+/*  *********************************************************************
+    *  Switch performance counters
+    ********************************************************************* */
+
+#define A_BCM1480_SWPERF_CFG    0xdfb91800
+#define A_BCM1480_SWPERF_CNT0   0xdfb91880
+#define A_BCM1480_SWPERF_CNT1   0xdfb91888
+#define A_BCM1480_SWPERF_CNT2   0xdfb91890
+#define A_BCM1480_SWPERF_CNT3   0xdfb91898
+
+
+/*  *********************************************************************
+    *  Switch Trace Unit
+    ********************************************************************* */
+
+#define A_BCM1480_SWTRC_MATCH_CONTROL_0         0xDFB91000
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0      0xDFB91100
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0       0xDFB91108
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0       0xDFB91200
+#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0        0xDFB91208
+#define A_BCM1480_SWTRC_EVENT_0                 0xDFB91300
+#define A_BCM1480_SWTRC_SEQUENCE_0              0xDFB91400
+
+#define A_BCM1480_SWTRC_CFG                     0xDFB91500
+#define A_BCM1480_SWTRC_READ                    0xDFB91508
+
+#define A_BCM1480_SWDEBUG_SCHEDSTOP             0xDFB92000
+
+#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
+#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
+#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
+
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
+
+
+
+/*  *********************************************************************
+    *  High-Speed Port Registers (Section 13)
+    ********************************************************************* */
+
+#define A_BCM1480_HSP_BASE_0                0x00DF810000
+#define A_BCM1480_HSP_BASE_1                0x00DF890000
+#define A_BCM1480_HSP_BASE_2                0x00DF910000
+#define BCM1480_HSP_REGISTER_SPACING        0x80000
+
+#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
+#define A_BCM1480_HSP_REGISTER(idx,reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
+
+#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
+#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
+
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
+
+#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
+#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
+#define R_BCM1480_HSP_RX_TEST                 0x0000000810
+#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
+#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
+#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
+#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
+#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838
+
+#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
+
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
+
+/* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0
+
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_2      0x00000200C0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_3      0x00000200C8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_4      0x00000200D0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_5      0x00000200D8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_6      0x00000200E0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
+
+#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
+#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
+#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
+#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
+#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
+#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
+#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120
+
+#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
+#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
+#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
+
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
+#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
+#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0
+
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0      0x00000400B0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1      0x00000400B8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
+#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8
+
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
+#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108
+
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
+
+#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
+#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
+#define R_BCM1480_HSP_TX_TEST                 0x0000040810
+
+#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
+#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
+#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
+#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
+#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
+#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
+#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878
+
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
+
+#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
+#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
+
+
+
+/*  *********************************************************************
+    *  Physical Address Map (Table 10 and Figure 7)
+    ********************************************************************* */
+
+#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
+#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
+#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
+#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
+#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
+#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
+#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)
+
+
+/*  *********************************************************************
+    *  L2 Cache as RAM (Table 54)
+    ********************************************************************* */
+
+#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
+#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
+#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
+#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
+#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
+#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
+#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
+#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)
+
+#endif /* _BCM1480_REGS_H */
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
new file mode 100644
index 000000000000..648bed96780f
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -0,0 +1,436 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1400 Board Support Package
+    *
+    *  SCD Constants and Macros                     File: bcm1480_scd.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module.
+    *
+    *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _BCM1480_SCD_H
+#define _BCM1480_SCD_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Pull in the BCM1250's SCD since lots of stuff is the same.
+    ********************************************************************* */
+
+#include "sb1250_scd.h"
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+
+/*
+ * System Identification and Revision Register (Table 12)
+ * Register: SCD_SYSTEM_REVISION
+ * This register is field compatible with the 1250.
+ */
+
+/*
+ * New part definitions
+ */
+
+#define K_SYS_PART_BCM1480          0x1406
+#define K_SYS_PART_BCM1280          0x1206
+#define K_SYS_PART_BCM1455          0x1407
+#define K_SYS_PART_BCM1255          0x1257
+
+/*
+ * Manufacturing Information Register (Table 14)
+ * Register: SCD_SYSTEM_MANUF
+ */
+
+/*
+ * System Configuration Register (Table 15)
+ * Register: SCD_SYSTEM_CFG
+ * Entire register is different from 1250, all new constants below
+ */
+
+#define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
+#define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
+#define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
+#define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
+#define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
+#define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
+
+#define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
+#define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV)
+#define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV)
+#define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV)
+
+#define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
+#define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV)
+#define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV)
+#define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV)
+
+#define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+#define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
+
+#define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
+#define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE)
+#define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE)
+#define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE)
+#define K_BCM1480_SYS_BOOT_MODE_ROM32       0
+#define K_BCM1480_SYS_BOOT_MODE_ROM8        1
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
+#define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
+
+#define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
+#define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
+#define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
+#define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SYS_CONFIG                26
+#define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG)
+#define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG)
+#define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG)
+
+#define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32,15)
+
+#define S_BCM1480_SYS_NODEID                47
+#define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID)
+#define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID)
+#define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID)
+
+#define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
+#define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
+#define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
+#define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
+#define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
+#define S_BCM1480_SYS_DISABLECPU0           56
+#define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
+#define S_BCM1480_SYS_DISABLECPU1           57
+#define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
+#define S_BCM1480_SYS_DISABLECPU2           58
+#define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
+#define S_BCM1480_SYS_DISABLECPU3           59
+#define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
+
+#define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
+#define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
+#define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
+#define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+
+/*
+ * Scratch Register (Table 16)
+ * Register: SCD_SYSTEM_SCRATCH
+ * Same as BCM1250
+ */
+
+
+/*
+ * Mailbox Registers (Table 17)
+ * Registers: SCD_MBOX_{0,1}_CPU_x
+ * Same as BCM1250
+ */
+
+
+/*
+ * See bcm1480_int.h for interrupt mapper registers.
+ */
+
+
+/*
+ * Watchdog Timer Initial Count Registers (Table 23)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ *
+ * The watchdogs are almost the same as the 1250, except
+ * the configuration register has more bits to control the
+ * other CPUs.
+ */
+
+
+/*
+ * Watchdog Timer Configuration Registers (Table 25)
+ * Registers: SCD_WDOG_CFG_x
+ */
+
+#define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
+
+#define S_BCM1480_SCD_WDOG_RESET_TYPE       2
+#define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE)
+
+#define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_BCM1480_SCD_WDOG_RESET_SOFT       1
+#define K_BCM1480_SCD_WDOG_RESET_CPU0       3
+#define K_BCM1480_SCD_WDOG_RESET_CPU1       5
+#define K_BCM1480_SCD_WDOG_RESET_CPU2       9
+#define K_BCM1480_SCD_WDOG_RESET_CPU3       17
+#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
+
+
+#define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
+
+/*
+ * General Timer Initial Count Registers (Table 26)
+ * Registers: SCD_TIMER_INIT_x
+ *
+ * The timer registers are the same as the BCM1250
+ */
+
+
+/*
+ * ZBbus Count Register (Table 29)
+ * Register: ZBBUS_CYCLE_COUNT
+ *
+ * Same as BCM1250
+ */
+
+/*
+ * ZBbus Compare Registers (Table 30)
+ * Registers: ZBBUS_CYCLE_CPx
+ *
+ * Same as BCM1250
+ */
+
+
+/*
+ * System Performance Counter Configuration Register (Table 31)
+ * Register: PERF_CNT_CFG_0
+ *
+ * Since the clear/enable bits are moved compared to the
+ * 1250 and there are more fields, this register will be BCM1480 specific.
+ */
+
+#define S_BCM1480_SPC_CFG_SRC0              0
+#define M_BCM1480_SPC_CFG_SRC0              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0)
+#define V_BCM1480_SPC_CFG_SRC0(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0)
+#define G_BCM1480_SPC_CFG_SRC0(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0)
+
+#define S_BCM1480_SPC_CFG_SRC1              8
+#define M_BCM1480_SPC_CFG_SRC1              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1)
+#define V_BCM1480_SPC_CFG_SRC1(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1)
+#define G_BCM1480_SPC_CFG_SRC1(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1)
+
+#define S_BCM1480_SPC_CFG_SRC2              16
+#define M_BCM1480_SPC_CFG_SRC2              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2)
+#define V_BCM1480_SPC_CFG_SRC2(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2)
+#define G_BCM1480_SPC_CFG_SRC2(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2)
+
+#define S_BCM1480_SPC_CFG_SRC3              24
+#define M_BCM1480_SPC_CFG_SRC3              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3)
+#define V_BCM1480_SPC_CFG_SRC3(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3)
+#define G_BCM1480_SPC_CFG_SRC3(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3)
+
+#define S_BCM1480_SPC_CFG_SRC4              32
+#define M_BCM1480_SPC_CFG_SRC4              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
+#define V_BCM1480_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
+#define G_BCM1480_SPC_CFG_SRC4(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
+
+#define S_BCM1480_SPC_CFG_SRC5              40
+#define M_BCM1480_SPC_CFG_SRC5              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
+#define V_BCM1480_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
+#define G_BCM1480_SPC_CFG_SRC5(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
+
+#define S_BCM1480_SPC_CFG_SRC6              48
+#define M_BCM1480_SPC_CFG_SRC6              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
+#define V_BCM1480_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
+#define G_BCM1480_SPC_CFG_SRC6(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
+
+#define S_BCM1480_SPC_CFG_SRC7              56
+#define M_BCM1480_SPC_CFG_SRC7              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
+#define V_BCM1480_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
+#define G_BCM1480_SPC_CFG_SRC7(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
+
+/*
+ * System Performance Counter Control Register (Table 32)
+ * Register: PERF_CNT_CFG_1
+ * BCM1480 specific
+ */
+
+#define M_BCM1480_SPC_CFG_CLEAR             _SB_MAKEMASK1(0)
+#define M_BCM1480_SPC_CFG_ENABLE            _SB_MAKEMASK1(1)
+
+/*
+ * System Performance Counters (Table 33)
+ * Registers: PERF_CNT_x
+ */
+
+#define S_BCM1480_SPC_CNT_COUNT             0
+#define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT)
+#define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT)
+#define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT)
+
+#define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
+
+
+/*
+ * Bus Watcher Error Status Register (Tables 36, 37)
+ * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
+ * Same as BCM1250.
+ */
+
+/*
+ * Bus Watcher Error Data Registers (Table 38)
+ * Registers: BUS_ERR_DATA_x
+ * Same as BCM1250.
+ */
+
+/*
+ * Bus Watcher L2 ECC Counter Register (Table 39)
+ * Register: BUS_L2_ERRORS
+ * Same as BCM1250.
+ */
+
+
+/*
+ * Bus Watcher Memory and I/O Error Counter Register (Table 40)
+ * Register: BUS_MEM_IO_ERRORS
+ * Same as BCM1250.
+ */
+
+
+/*
+ * Address Trap Registers
+ *
+ * Register layout same as BCM1250, almost.  The bus agents
+ * are different, and the address trap configuration bits are
+ * slightly different.
+ */
+
+#define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4,0)
+#define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40,0)
+
+#define S_BCM1480_ATRAP_CFG_CNT            0
+#define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT)
+#define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT)
+#define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT)
+
+#define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+
+#define S_BCM1480_ATRAP_CFG_AGENTID     8
+#define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID)
+#define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID)
+#define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID)
+
+
+#define K_BCM1480_BUS_AGENT_CPU0            0
+#define K_BCM1480_BUS_AGENT_CPU1            1
+#define K_BCM1480_BUS_AGENT_NC              2
+#define K_BCM1480_BUS_AGENT_IOB             3
+#define K_BCM1480_BUS_AGENT_SCD             4
+#define K_BCM1480_BUS_AGENT_L2C             6
+#define K_BCM1480_BUS_AGENT_MC              7
+#define K_BCM1480_BUS_AGENT_CPU2            8
+#define K_BCM1480_BUS_AGENT_CPU3            9
+#define K_BCM1480_BUS_AGENT_PM              10
+
+#define S_BCM1480_ATRAP_CFG_CATTR           12
+#define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR)
+#define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR)
+#define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR)
+
+#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
+#define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
+#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
+#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
+
+#define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
+
+
+/*
+ * Trace Event Registers (Table 47)
+ * Same as BCM1250.
+ */
+
+/*
+ * Trace Sequence Control Registers (Table 48)
+ * Registers: TRACE_SEQUENCE_x
+ *
+ * Same as BCM1250 except for two new fields.
+ */
+
+
+#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SCD_TRSEQ_SWFUNC          26
+#define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC)
+
+/*
+ * Trace Control Register (Table 49)
+ * Register: TRACE_CFG
+ *
+ * Bits 0..8 are the same as the BCM1250, rest are different.
+ * Entire register is redefined below.
+ */
+
+#define M_BCM1480_SCD_TRACE_CFG_RESET       _SB_MAKEMASK1(0)
+#define M_BCM1480_SCD_TRACE_CFG_START_READ  _SB_MAKEMASK1(1)
+#define M_BCM1480_SCD_TRACE_CFG_START       _SB_MAKEMASK1(2)
+#define M_BCM1480_SCD_TRACE_CFG_STOP        _SB_MAKEMASK1(3)
+#define M_BCM1480_SCD_TRACE_CFG_FREEZE      _SB_MAKEMASK1(4)
+#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
+#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL  _SB_MAKEMASK1(6)
+#define M_BCM1480_SCD_TRACE_CFG_FULL        _SB_MAKEMASK1(7)
+#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT   _SB_MAKEMASK1(8)
+
+#define S_BCM1480_SCD_TRACE_CFG_MODE        16
+#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
+#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
+#define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE)
+
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
+#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
+
+#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR    24
+#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR    _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
+#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
+#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
+
+#endif /* _BCM1480_SCD_H */
diff --git a/include/asm-mips/sibyte/bigsur.h b/include/asm-mips/sibyte/bigsur.h
new file mode 100644
index 000000000000..ebefe797fc1d
--- /dev/null
+++ b/include/asm-mips/sibyte/bigsur.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_BIGSUR_H
+#define __ASM_SIBYTE_BIGSUR_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/bcm1480_int.h>
+
+#ifdef CONFIG_SIBYTE_BIGSUR
+#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+
+#endif /* __ASM_SIBYTE_BIGSUR_H */
+
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index d7b11b6c7c32..900edcbeec37 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -21,8 +21,6 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_SIBYTE_BOARD
-
 #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
     defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
     defined(CONFIG_SIBYTE_LITTLESUR)
@@ -37,6 +35,10 @@
 #include <asm/sibyte/carmel.h>
 #endif
 
+#ifdef CONFIG_SIBYTE_BIGSUR
+#include <asm/sibyte/bigsur.h>
+#endif
+
 #ifdef __ASSEMBLY__
 
 #ifdef LEDS_PHYS
@@ -54,16 +56,6 @@
 #define setleds(t0,t1,c0,c1,c2,c3)
 #endif /* LEDS_PHYS */
 
-#else
-
-#ifdef LEDS_PHYS
-extern void setleds(char *str);
-#else
-#define setleds(s) do { } while (0)
-#endif /* LEDS_PHYS */
-
 #endif /* __ASSEMBLY__ */
 
-#endif /* CONFIG_SIBYTE_BOARD */
-
 #endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index d62da4e2dd36..a474c29cd701 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -27,6 +27,9 @@
 
 #define SB1250_NR_IRQS 64
 
+#define BCM1480_NR_IRQS                 128
+#define BCM1480_NR_IRQS_HALF            64
+
 #define SB1250_DUART_MINOR_BASE         64
 
 #ifndef __ASSEMBLY__
@@ -35,6 +38,7 @@
 
 /* For revision/pass information */
 #include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/bcm1480_scd.h>
 extern unsigned int sb1_pass;
 extern unsigned int soc_pass;
 extern unsigned int soc_type;
@@ -46,6 +50,13 @@ extern unsigned long sb1250_gettimeoffset(void);
 extern void sb1250_mask_irq(int cpu, int irq);
 extern void sb1250_unmask_irq(int cpu, int irq);
 extern void sb1250_smp_finish(void);
+
+extern void bcm1480_time_init(void);
+extern unsigned long bcm1480_gettimeoffset(void);
+extern void bcm1480_mask_irq(int cpu, int irq);
+extern void bcm1480_unmask_irq(int cpu, int irq);
+extern void bcm1480_smp_finish(void);
+
 extern void prom_printf(char *fmt, ...);
 
 #define AT_spin \
@@ -58,6 +69,6 @@ extern void prom_printf(char *fmt, ...);
 
 #endif
 
-#define IOADDR(a) (IO_BASE + (a))
+#define IOADDR(a) ((volatile void __iomem *)(IO_BASE + (a)))
 
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 40ef97c76c8b..335dbaf1d831 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -97,13 +95,17 @@
     *  ordering, so be careful when adding support for new minor revs.
     ********************************************************************* */
 
-#define SIBYTE_HDR_FMASK_1250_ALL               0x00000ff
-#define SIBYTE_HDR_FMASK_1250_PASS1             0x0000001
-#define SIBYTE_HDR_FMASK_1250_PASS2             0x0000002
-#define SIBYTE_HDR_FMASK_1250_PASS3             0x0000004
+#define SIBYTE_HDR_FMASK_1250_ALL               0x000000ff
+#define SIBYTE_HDR_FMASK_1250_PASS1             0x00000001
+#define SIBYTE_HDR_FMASK_1250_PASS2             0x00000002
+#define SIBYTE_HDR_FMASK_1250_PASS3             0x00000004
+
+#define SIBYTE_HDR_FMASK_112x_ALL               0x00000f00
+#define SIBYTE_HDR_FMASK_112x_PASS1             0x00000100
 
-#define SIBYTE_HDR_FMASK_112x_ALL               0x0000f00
-#define SIBYTE_HDR_FMASK_112x_PASS1             0x0000100
+#define SIBYTE_HDR_FMASK_1480_ALL               0x0000f000
+#define SIBYTE_HDR_FMASK_1480_PASS1             0x00001000
+#define SIBYTE_HDR_FMASK_1480_PASS2             0x00002000
 
 /* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
 #define SIBYTE_HDR_FMASK(chip, pass)                                    \
@@ -111,8 +113,17 @@
 #define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
     (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
 
+/* Default constant value for all chips, all revisions */
 #define SIBYTE_HDR_FMASK_ALL                                            \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL              \
+     | SIBYTE_HDR_FMASK_1480_ALL)
+
+/* This one is used for the "original" BCM1250/BCM112x chips.  We use this
+   to weed out constants and macros that do not exist on later chips like
+   the BCM1480  */
+#define SIBYTE_HDR_FMASK_1250_112x_ALL                                  \
     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
+#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
 
 #ifndef SIBYTE_HDR_FEATURES
 #define SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
@@ -133,6 +144,12 @@
 #define SIBYTE_HDR_FEATURE_CHIP(chip)                                   \
     (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
 
+/* True for all versions of the BCM1250 and BCM1125, but not true for
+   anything else */
+#define SIBYTE_HDR_FEATURE_1250_112x \
+      (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
+/*    (!!  (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
+
 /* True if header features enabled for that rev or later, inclusive.  */
 #define SIBYTE_HDR_FEATURE(chip, pass)                                  \
     (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index 3cdb48f50ed0..e6145f524fbd 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -7,9 +7,8 @@
     *  programming the SB1250's DMA controllers, both the data mover
     *  and the Ethernet DMA.
     *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *  Author:  Mitch Lichtenberg
+    *  SB1250 specification level:  User's manual 10/21/02
+    *  BCM1280 specification level: User's manual 11/24/03
     *
     *********************************************************************
     *
@@ -58,17 +57,17 @@
 #define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
 
 #define S_DMA_DESC_TYPE             _SB_MAKE64(1)
-#define M_DMA_DESC_TYPE             _SB_MAKE64(2,S_DMA_DESC_TYPE)
+#define M_DMA_DESC_TYPE             _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
 #define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
 #define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
 
 #define K_DMA_DESC_TYPE_RING_AL         0
 #define K_DMA_DESC_TYPE_CHAIN_AL        1
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define K_DMA_DESC_TYPE_RING_UAL_WI     2
 #define K_DMA_DESC_TYPE_RING_UAL_RMW    3
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
 #define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
@@ -111,11 +110,11 @@
 #define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
 #define M_DMA_L2CA                  _SB_MAKEMASK1(5)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
 #define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
 #define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_DMA_MBZ1                  _SB_MAKEMASK(6,15)
 
@@ -165,14 +164,14 @@
 #define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
 #define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 /*
  * Receive Packet Drop Registers
  */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_OODLOST_RX           _SB_MAKE64(0)
 #define M_DMA_OODLOST_RX           _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
 #define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@@ -180,7 +179,7 @@
 #define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
 #define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
 #define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 /*  *********************************************************************
     *  DMA Descriptors
@@ -201,21 +200,21 @@
 
 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
 #define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
 #define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
 #define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
 #define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
 #define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
 #define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
 #define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
@@ -235,12 +234,12 @@
 #define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
 #define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
 #define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
 #define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
 #define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
 
@@ -255,12 +254,12 @@
 
 #define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
 #define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
 #define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@@ -282,15 +281,16 @@
 #define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
 #define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-/* Note: BADTCPCS is actually in DSCR_B options field */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: This bit is in the DSCR_B options field */
 #define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: These bits are in the DSCR_B options field */
 #define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
 #define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define S_DMA_ETHRX_RXCH            53
 #define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@@ -438,7 +438,7 @@
                                      M_DM_CUR_DSCR_DSCR_COUNT)
 
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
  * Data Mover Channel Partial Result Registers
  * Register: DM_PARTIAL_0
@@ -459,10 +459,10 @@
                                        M_DM_PARTIAL_TCPCS_PARTIAL)
 
 #define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
  * Data Mover CRC Definition Registers
  * Register: CRC_DEF_0
@@ -479,10 +479,10 @@
 #define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
 #define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
                                        M_CRC_DEF_CRC_POLY)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
  * Data Mover CRC/Checksum Definition Registers
  * Register: CTCP_DEF_0
@@ -511,7 +511,7 @@
 #define K_CTCP_DEF_CRC_WIDTH_1        2
 
 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
 /*
@@ -560,12 +560,12 @@
 #define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
 #define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
 #define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
 #define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
 #define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
@@ -574,7 +574,7 @@
 #define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
 #define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
 #define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3,61)
 
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index f1f509f295c4..1b5cbc5c6454 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -6,9 +6,8 @@
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's Generic Bus interface
     *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *  Author:  Mitch Lichtenberg
+    *  SB1250 specification level:  User's manual 10/21/02
+    *  BCM1280 specification level: User's Manual 11/14/03
     *
     *********************************************************************
     *
@@ -51,19 +50,21 @@
 #define M_IO_WIDTH_SEL          _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
 #define K_IO_WIDTH_SEL_1        0
 #define K_IO_WIDTH_SEL_2        1
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define K_IO_WIDTH_SEL_1L       2
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define K_IO_WIDTH_SEL_4        3
 #define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
 #define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
 
 #define S_IO_PARITY_ENA         4
 #define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_IO_BURST_EN           5
 #define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define S_IO_PARITY_ODD         6
 #define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
 #define S_IO_NONMUX             7
@@ -96,8 +97,11 @@
 
 #define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
 
+#define M_IO_BLK_CACHE          _SB_MAKEMASK1(15)
+
+
 /*
- * Generic Bus Region 0 Timing Registers (Table 11-7)
+ * Generic Bus Timing 0 Registers (Table 11-7)
  */
 
 #define S_IO_ALE_WIDTH          0
@@ -105,21 +109,23 @@
 #define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
 #define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_ALE_TO_CS          4
 #define M_IO_ALE_TO_CS          _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
 #define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
 #define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_IO_BURST_WIDTH           _SB_MAKE64(6)
 #define M_IO_BURST_WIDTH           _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
 #define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
 #define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_CS_WIDTH           8
 #define M_IO_CS_WIDTH           _SB_MAKEMASK(5,S_IO_CS_WIDTH)
@@ -141,9 +147,10 @@
 #define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
 #define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_WRITE_WIDTH        4
 #define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
@@ -183,9 +190,127 @@
 #define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
 #define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
 #define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_COH_ERR            _SB_MAKEMASK1(14)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/*
+ * Generic Bus Output Drive Control Register 0 (Table 14-18)
+ */
+
+#define S_IO_SLEW0              0
+#define M_IO_SLEW0              _SB_MAKEMASK(2,S_IO_SLEW0)
+#define V_IO_SLEW0(x)           _SB_MAKEVALUE(x,S_IO_SLEW0)
+#define G_IO_SLEW0(x)           _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0)
+
+#define S_IO_DRV_A              2
+#define M_IO_DRV_A              _SB_MAKEMASK(2,S_IO_DRV_A)
+#define V_IO_DRV_A(x)           _SB_MAKEVALUE(x,S_IO_DRV_A)
+#define G_IO_DRV_A(x)           _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A)
+
+#define S_IO_DRV_B              6
+#define M_IO_DRV_B              _SB_MAKEMASK(2,S_IO_DRV_B)
+#define V_IO_DRV_B(x)           _SB_MAKEVALUE(x,S_IO_DRV_B)
+#define G_IO_DRV_B(x)           _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B)
+
+#define S_IO_DRV_C              10
+#define M_IO_DRV_C              _SB_MAKEMASK(2,S_IO_DRV_C)
+#define V_IO_DRV_C(x)           _SB_MAKEVALUE(x,S_IO_DRV_C)
+#define G_IO_DRV_C(x)           _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C)
+
+#define S_IO_DRV_D              14
+#define M_IO_DRV_D              _SB_MAKEMASK(2,S_IO_DRV_D)
+#define V_IO_DRV_D(x)           _SB_MAKEVALUE(x,S_IO_DRV_D)
+#define G_IO_DRV_D(x)           _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D)
+
+/*
+ * Generic Bus Output Drive Control Register 1 (Table 14-19)
+ */
+
+#define S_IO_DRV_E              2
+#define M_IO_DRV_E              _SB_MAKEMASK(2,S_IO_DRV_E)
+#define V_IO_DRV_E(x)           _SB_MAKEVALUE(x,S_IO_DRV_E)
+#define G_IO_DRV_E(x)           _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E)
+
+#define S_IO_DRV_F              6
+#define M_IO_DRV_F              _SB_MAKEMASK(2,S_IO_DRV_F)
+#define V_IO_DRV_F(x)           _SB_MAKEVALUE(x,S_IO_DRV_F)
+#define G_IO_DRV_F(x)           _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F)
+
+#define S_IO_SLEW1              8
+#define M_IO_SLEW1              _SB_MAKEMASK(2,S_IO_SLEW1)
+#define V_IO_SLEW1(x)           _SB_MAKEVALUE(x,S_IO_SLEW1)
+#define G_IO_SLEW1(x)           _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1)
+
+#define S_IO_DRV_G              10
+#define M_IO_DRV_G              _SB_MAKEMASK(2,S_IO_DRV_G)
+#define V_IO_DRV_G(x)           _SB_MAKEVALUE(x,S_IO_DRV_G)
+#define G_IO_DRV_G(x)           _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G)
+
+#define S_IO_SLEW2              12
+#define M_IO_SLEW2              _SB_MAKEMASK(2,S_IO_SLEW2)
+#define V_IO_SLEW2(x)           _SB_MAKEVALUE(x,S_IO_SLEW2)
+#define G_IO_SLEW2(x)           _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2)
+
+#define S_IO_DRV_H              14
+#define M_IO_DRV_H              _SB_MAKEMASK(2,S_IO_DRV_H)
+#define V_IO_DRV_H(x)           _SB_MAKEVALUE(x,S_IO_DRV_H)
+#define G_IO_DRV_H(x)           _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H)
+
+/*
+ * Generic Bus Output Drive Control Register 2 (Table 14-20)
+ */
+
+#define S_IO_DRV_J              2
+#define M_IO_DRV_J              _SB_MAKEMASK(2,S_IO_DRV_J)
+#define V_IO_DRV_J(x)           _SB_MAKEVALUE(x,S_IO_DRV_J)
+#define G_IO_DRV_J(x)           _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J)
+
+#define S_IO_DRV_K              6
+#define M_IO_DRV_K              _SB_MAKEMASK(2,S_IO_DRV_K)
+#define V_IO_DRV_K(x)           _SB_MAKEVALUE(x,S_IO_DRV_K)
+#define G_IO_DRV_K(x)           _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K)
+
+#define S_IO_DRV_L              10
+#define M_IO_DRV_L              _SB_MAKEMASK(2,S_IO_DRV_L)
+#define V_IO_DRV_L(x)           _SB_MAKEVALUE(x,S_IO_DRV_L)
+#define G_IO_DRV_L(x)           _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L)
+
+#define S_IO_DRV_M              14
+#define M_IO_DRV_M              _SB_MAKEMASK(2,S_IO_DRV_M)
+#define V_IO_DRV_M(x)           _SB_MAKEVALUE(x,S_IO_DRV_M)
+#define G_IO_DRV_M(x)           _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M)
+
+/*
+ * Generic Bus Output Drive Control Register 3 (Table 14-21)
+ */
+
+#define S_IO_SLEW3              0
+#define M_IO_SLEW3              _SB_MAKEMASK(2,S_IO_SLEW3)
+#define V_IO_SLEW3(x)           _SB_MAKEVALUE(x,S_IO_SLEW3)
+#define G_IO_SLEW3(x)           _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3)
+
+#define S_IO_DRV_N              2
+#define M_IO_DRV_N              _SB_MAKEMASK(2,S_IO_DRV_N)
+#define V_IO_DRV_N(x)           _SB_MAKEVALUE(x,S_IO_DRV_N)
+#define G_IO_DRV_N(x)           _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N)
+
+#define S_IO_DRV_P              6
+#define M_IO_DRV_P              _SB_MAKEMASK(2,S_IO_DRV_P)
+#define V_IO_DRV_P(x)           _SB_MAKEVALUE(x,S_IO_DRV_P)
+#define G_IO_DRV_P(x)           _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P)
+
+#define S_IO_DRV_Q              10
+#define M_IO_DRV_Q              _SB_MAKEMASK(2,S_IO_DRV_Q)
+#define V_IO_DRV_Q(x)           _SB_MAKEVALUE(x,S_IO_DRV_Q)
+#define G_IO_DRV_Q(x)           _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q)
+
+#define S_IO_DRV_R              14
+#define M_IO_DRV_R              _SB_MAKEMASK(2,S_IO_DRV_R)
+#define V_IO_DRV_R(x)           _SB_MAKEVALUE(x,S_IO_DRV_R)
+#define G_IO_DRV_R(x)           _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R)
+
 
 /*
  * PCMCIA configuration register (Table 12-6)
@@ -202,6 +327,22 @@
 #define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
 #define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
 
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_PCMCIA_MODE           16
+#define M_PCMCIA_MODE           _SB_MAKEMASK(3,S_PCMCIA_MODE)
+#define V_PCMCIA_MODE(x)        _SB_MAKEVALUE(x,S_PCMCIA_MODE)
+#define G_PCMCIA_MODE(x)        _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE)
+
+#define K_PCMCIA_MODE_PCMA_NOB  0       /* standard PCMCIA "A", no "B" */
+#define K_PCMCIA_MODE_IDEA_NOB  1       /* IDE "A", no "B" */
+#define K_PCMCIA_MODE_PCMIOA_NOB 2      /* PCMCIA with I/O "A", no "B" */
+#define K_PCMCIA_MODE_PCMA_PCMB 4       /* standard PCMCIA "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_IDEA_PCMB 5       /* IDE "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_PCMA_IDEB 6       /* standard PCMCIA "A", IDE "B" */
+#define K_PCMCIA_MODE_IDEA_IDEB 7       /* IDE "A", IDE "B" */
+#endif
+
+
 /*
  * PCMCIA status register (Table 12-7)
  */
@@ -272,5 +413,62 @@
 #define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
 #define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
 
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+
+/*
+ * GPIO Interrupt Additional Type Register
+ */
+
+#define K_GPIO_INTR_BOTHEDGE    0
+#define K_GPIO_INTR_RISEEDGE    1
+#define K_GPIO_INTR_UNPRED1     2
+#define K_GPIO_INTR_UNPRED2     3
+
+#define S_GPIO_INTR_ATYPEX(n)   (((n)/2)*2)
+#define M_GPIO_INTR_ATYPEX(n)   _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n))
+#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n))
+#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n))
+
+#define S_GPIO_INTR_ATYPE0      0
+#define M_GPIO_INTR_ATYPE0      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0)
+#define V_GPIO_INTR_ATYPE0(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0)
+#define G_GPIO_INTR_ATYPE0(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0)
+
+#define S_GPIO_INTR_ATYPE2      2
+#define M_GPIO_INTR_ATYPE2      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2)
+#define V_GPIO_INTR_ATYPE2(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2)
+#define G_GPIO_INTR_ATYPE2(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2)
+
+#define S_GPIO_INTR_ATYPE4      4
+#define M_GPIO_INTR_ATYPE4      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4)
+#define V_GPIO_INTR_ATYPE4(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4)
+#define G_GPIO_INTR_ATYPE4(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4)
+
+#define S_GPIO_INTR_ATYPE6      6
+#define M_GPIO_INTR_ATYPE6      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6)
+#define V_GPIO_INTR_ATYPE6(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6)
+#define G_GPIO_INTR_ATYPE6(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6)
+
+#define S_GPIO_INTR_ATYPE8      8
+#define M_GPIO_INTR_ATYPE8      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8)
+#define V_GPIO_INTR_ATYPE8(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8)
+#define G_GPIO_INTR_ATYPE8(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8)
+
+#define S_GPIO_INTR_ATYPE10     10
+#define M_GPIO_INTR_ATYPE10     _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10)
+#define V_GPIO_INTR_ATYPE10(x)  _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10)
+#define G_GPIO_INTR_ATYPE10(x)  _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10)
+
+#define S_GPIO_INTR_ATYPE12     12
+#define M_GPIO_INTR_ATYPE12     _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12)
+#define V_GPIO_INTR_ATYPE12(x)  _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12)
+#define G_GPIO_INTR_ATYPE12(x)  _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12)
+
+#define S_GPIO_INTR_ATYPE14     14
+#define M_GPIO_INTR_ATYPE14     _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14)
+#define V_GPIO_INTR_ATYPE14(x)  _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14)
+#define G_GPIO_INTR_ATYPE14(x)  _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14)
+#endif
+
 
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index e173e2ea4c98..05c7b39f1b02 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -47,6 +45,10 @@
  * First, the interrupt numbers.
  */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
+
+#define K_INT_SOURCES               64
+
 #define K_INT_WATCHDOG_TIMER_0      0
 #define K_INT_WATCHDOG_TIMER_1      1
 #define K_INT_TIMER_0               2
@@ -244,4 +246,6 @@
 #define M_LDTVECT_RAISEMBOX             0x40
 
 
+#endif  /* 1250/112x */
+
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 8afe8e01581b..842f205094af 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -89,8 +87,13 @@
 #define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
 #define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
 
-#define S_L2C_MGMT_TAG              21
-#define M_L2C_MGMT_TAG              _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
+#define S_L2C_MGMT_ECC_DIAG         21
+#define M_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG)
+#define V_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG)
+#define G_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG)
+
+#define S_L2C_MGMT_TAG              23
+#define M_L2C_MGMT_TAG              _SB_MAKEMASK(4,S_L2C_MGMT_TAG)
 #define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
 #define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
 
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index f2617ded0a8f..7092535d1108 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 18e74e43f4a2..adfc688fa559 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -81,7 +79,10 @@
 #define M_MAC_RESERVED1             _SB_MAKEMASK(8,9)
 
 #define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
-#define M_MAC_RESERVED2             _SB_MAKEMASK1(18)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TIMESTAMP             _SB_MAKEMASK1(18)
+#endif
 #define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
 #define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
 #define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
@@ -132,9 +133,9 @@
 #define M_MAC_RX_CH_SEL_MSB         _SB_MAKEMASK1(44)
 #endif /* 1250 PASS2 || 112x PASS1 */
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_SPLIT_CH_SEL          _SB_MAKEMASK1(45)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
 #define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
@@ -176,10 +177,22 @@
 
 #define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
 
+#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
 #define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
 #define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
 #define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
 #define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
+#endif
+
+/*
+ * MAC reset information register (1280/1255)
+ */
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_RX_CH0_PAUSE_ON   _SB_MAKEMASK1(8)
+#define M_MAC_RX_CH1_PAUSE_ON   _SB_MAKEMASK1(16)
+#define M_MAC_TX_CH0_PAUSE_ON   _SB_MAKEMASK1(24)
+#define M_MAC_TX_CH1_PAUSE_ON   _SB_MAKEMASK1(32)
+#endif
 
 /*
  * MAC DMA Control Register
@@ -267,12 +280,12 @@
 #define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x,S_MAC_IFG_RX)
 #define G_MAC_IFG_RX(x)             _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_MAC_PRE_LEN               _SB_MAKE64(0)
 #define M_MAC_PRE_LEN               _SB_MAKEMASK(6,S_MAC_PRE_LEN)
 #define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
 #define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define S_MAC_IFG_TX                _SB_MAKE64(6)
 #define M_MAC_IFG_TX                _SB_MAKEMASK(6,S_MAC_IFG_TX)
@@ -458,9 +471,9 @@
 #define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
 #define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_TX_PAUSE_ON           _SB_MAKEMASK1(52)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 /*
  * MAC Fifo Pointer Registers (Table 9-19)    [Debug register]
@@ -594,7 +607,7 @@
 #define V_MAC_IPHDR_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
 #define G_MAC_IPHDR_OFFSET(x)   _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
 #define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
 #define V_MAC_RX_CRC_OFFSET(x)  _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
@@ -612,7 +625,7 @@
 #define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
 #define V_MAC_RX_CH_MSN_SEL(x)  _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
 #define G_MAC_RX_CH_MSN_SEL(x)  _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 /*
  * MAC Receive Channel Select Registers (Table 9-25)
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 1dd41c927996..26e421498c97 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -324,6 +322,10 @@
 #define K_MC_tRFC_DEFAULT         12
 #define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
 
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)     /* 1250C3 and later.  */
+#endif
+
 #define S_MC_tCwCr                40
 #define M_MC_tCwCr                _SB_MAKEMASK(4,S_MC_tCwCr)
 #define V_MC_tCwCr(x)             _SB_MAKEVALUE(x,S_MC_tCwCr)
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 9db80cd13a79..bab3a4580a36 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  01/02/2002
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -61,6 +59,8 @@
  * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
  * since there is one reg there (but it could get its addr/offset constant).
  */
+
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 #define A_MC_BASE_0                 0x0010051000
 #define A_MC_BASE_1                 0x0010052000
 #define MC_REGISTER_SPACING         0x1000
@@ -101,10 +101,14 @@
 #define R_MC_TEST_ECC               0x0000000420
 #define R_MC_MCLK_CFG               0x0000000500
 
+#endif  /* 1250 & 112x */
+
 /*  *********************************************************************
     * L2 Cache Control Registers
     ********************************************************************* */
 
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This L2C only on 1250/112x */
+
 #define A_L2_READ_TAG               0x0010040018
 #define A_L2_ECC_TAG                0x0010040038
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
@@ -125,13 +129,16 @@
 #define A_L2_READ_ADDRESS           A_L2_READ_TAG
 #define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
 
+#endif
 
 /*  *********************************************************************
     * PCI Interface Registers
     ********************************************************************* */
 
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This PCI/HT only on 1250/112x */
 #define A_PCI_TYPE00_HEADER         0x00DE000000
 #define A_PCI_TYPE01_HEADER         0x00DE000800
+#endif
 
 
 /*  *********************************************************************
@@ -264,15 +271,15 @@
     ********************************************************************* */
 
 
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 #define R_DUART_NUM_PORTS           2
 
 #define A_DUART                     0x0010060000
 
-#define A_DUART_REG(r)
-
 #define DUART_CHANREG_SPACING       0x100
 #define A_DUART_CHANREG(chan,reg)   (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
 #define R_DUART_CHANREG(chan,reg)   (DUART_CHANREG_SPACING*(chan) + (reg))
+#endif  /* 1250 & 112x */
 
 #define R_DUART_MODE_REG_1          0x100
 #define R_DUART_MODE_REG_2          0x110
@@ -307,11 +314,13 @@
 
 #define DUART_IMRISR_SPACING        0x20
 
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 #define R_DUART_IMRREG(chan)        (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
 #define R_DUART_ISRREG(chan)        (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
 
 #define A_DUART_IMRREG(chan)        (A_DUART + R_DUART_IMRREG(chan))
 #define A_DUART_ISRREG(chan)        (A_DUART + R_DUART_ISRREG(chan))
+#endif  /* 1250 & 112x */
 
 
 
@@ -368,6 +377,8 @@
     ********************************************************************* */
 
 
+#if SIBYTE_HDR_FEATURE_1250_112x        /* sync serial only on 1250/112x */
+
 #define A_SER_BASE_0                0x0010060400
 #define A_SER_BASE_1                0x0010060800
 #define SER_SPACING                 0x400
@@ -457,6 +468,8 @@
 #define R_SER_RMON_RX_ERRORS        0x000001F0
 #define R_SER_RMON_RX_BADADDR       0x000001F8
 
+#endif  /* 1250/112x */
+
 /*  *********************************************************************
     * Generic Bus Registers
     ********************************************************************* */
@@ -634,12 +647,13 @@
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_SCRATCH              0x0010020C10
+#endif /* 1250 PASS2 || 112x PASS1 */
 
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
 #define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
 #define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
-#endif /* 1250 PASS2 || 112x PASS1 */
-
+#endif
 
 /*  *********************************************************************
     * System Control Registers
@@ -667,15 +681,16 @@
 #define A_ADDR_TRAP_CFG_1           0x0010020448
 #define A_ADDR_TRAP_CFG_2           0x0010020450
 #define A_ADDR_TRAP_CFG_3           0x0010020458
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define A_ADDR_TRAP_REG_DEBUG       0x0010020460
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 
 /*  *********************************************************************
     * System Interrupt Mapper Registers
     ********************************************************************* */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define A_IMR_CPU0_BASE                 0x0010020000
 #define A_IMR_CPU1_BASE                 0x0010022000
 #define IMR_REGISTER_SPACING            0x2000
@@ -700,6 +715,7 @@
 #define R_IMR_INTERRUPT_STATUS_COUNT    7
 #define R_IMR_INTERRUPT_MAP_BASE        0x0200
 #define R_IMR_INTERRUPT_MAP_COUNT       64
+#endif  /* 1250/112x */
 
 /*  *********************************************************************
     * System Performance Counter Registers
@@ -718,6 +734,7 @@
 #define A_SCD_BUS_ERR_STATUS        0x0010020880
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
 #endif /* 1250 PASS2 || 112x PASS1 */
 #define A_BUS_ERR_DATA_0            0x00100208A0
 #define A_BUS_ERR_DATA_1            0x00100208A8
@@ -798,6 +815,7 @@
     *  Physical Address Map
     ********************************************************************* */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
 #define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
 #define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
@@ -831,6 +849,7 @@
 #define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
 #define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
 #define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
+#endif
 
 
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index dbbd682fb47e..a667bc14a7cd 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -51,26 +49,70 @@
 #define V_SYS_REVISION(x)           _SB_MAKEVALUE(x,S_SYS_REVISION)
 #define G_SYS_REVISION(x)           _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
 
-#if SIBYTE_HDR_FEATURE_CHIP(1250)
-#define K_SYS_REVISION_BCM1250_PASS1    1
-#define K_SYS_REVISION_BCM1250_PASS2    3
-#define K_SYS_REVISION_BCM1250_A10      11
-#define K_SYS_REVISION_BCM1250_PASS2_2  16
-#define K_SYS_REVISION_BCM1250_B2       17
-#define K_SYS_REVISION_BCM1250_PASS3    32
-#define K_SYS_REVISION_BCM1250_C1       33
+#define K_SYS_REVISION_BCM1250_PASS1    0x01
+
+#define K_SYS_REVISION_BCM1250_PASS2    0x03
+#define K_SYS_REVISION_BCM1250_A1       0x03    /* Pass 2.0 WB */
+#define K_SYS_REVISION_BCM1250_A2       0x04    /* Pass 2.0 FC */
+#define K_SYS_REVISION_BCM1250_A3       0x05    /* Pass 2.1 FC */
+#define K_SYS_REVISION_BCM1250_A4       0x06    /* Pass 2.1 WB */
+#define K_SYS_REVISION_BCM1250_A6       0x07    /* OR 0x04 (A2) w/WID != 0 */
+#define K_SYS_REVISION_BCM1250_A8       0x0b    /* A8/A10 */
+#define K_SYS_REVISION_BCM1250_A9       0x08
+#define K_SYS_REVISION_BCM1250_A10      K_SYS_REVISION_BCM1250_A8
 
+#define K_SYS_REVISION_BCM1250_PASS2_2  0x10
+#define K_SYS_REVISION_BCM1250_B0       K_SYS_REVISION_BCM1250_B1
+#define K_SYS_REVISION_BCM1250_B1       0x10
+#define K_SYS_REVISION_BCM1250_B2       0x11
+
+#define K_SYS_REVISION_BCM1250_C0       0x20
+#define K_SYS_REVISION_BCM1250_C1       0x21
+#define K_SYS_REVISION_BCM1250_C2       0x22
+#define K_SYS_REVISION_BCM1250_C3       0x23
+
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
 /* XXX: discourage people from using these constants.  */
 #define K_SYS_REVISION_PASS1        K_SYS_REVISION_BCM1250_PASS1
 #define K_SYS_REVISION_PASS2        K_SYS_REVISION_BCM1250_PASS2
 #define K_SYS_REVISION_PASS2_2      K_SYS_REVISION_BCM1250_PASS2_2
 #define K_SYS_REVISION_PASS3        K_SYS_REVISION_BCM1250_PASS3
+#define K_SYS_REVISION_BCM1250_PASS3    K_SYS_REVISION_BCM1250_C0
 #endif /* 1250 */
 
-#if SIBYTE_HDR_FEATURE_CHIP(112x)
-#define K_SYS_REVISION_BCM112x_A1       32
-#define K_SYS_REVISION_BCM112x_A2       33
-#endif /* 112x */
+#define K_SYS_REVISION_BCM112x_A1       0x20
+#define K_SYS_REVISION_BCM112x_A2       0x21
+#define K_SYS_REVISION_BCM112x_A3       0x22
+#define K_SYS_REVISION_BCM112x_A4       0x23
+
+#define K_SYS_REVISION_BCM1480_S0       0x01
+#define K_SYS_REVISION_BCM1480_A1       0x02
+#define K_SYS_REVISION_BCM1480_A2       0x03
+#define K_SYS_REVISION_BCM1480_A3       0x04
+#define K_SYS_REVISION_BCM1480_B0       0x11
+
+/*Cache size - 23:20  of revision register*/
+#define S_SYS_L2C_SIZE            _SB_MAKE64(20)
+#define M_SYS_L2C_SIZE            _SB_MAKEMASK(4,S_SYS_L2C_SIZE)
+#define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x,S_SYS_L2C_SIZE)
+#define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE)
+
+#define K_SYS_L2C_SIZE_1MB      0
+#define K_SYS_L2C_SIZE_512KB    5
+#define K_SYS_L2C_SIZE_256KB    2
+#define K_SYS_L2C_SIZE_128KB    1
+
+#define K_SYS_L2C_SIZE_BCM1250  K_SYS_L2C_SIZE_512KB
+#define K_SYS_L2C_SIZE_BCM1125  K_SYS_L2C_SIZE_256KB
+#define K_SYS_L2C_SIZE_BCM1122  K_SYS_L2C_SIZE_128KB
+
+
+/* Number of CPU cores, bits 27:24  of revision register*/
+#define S_SYS_NUM_CPUS            _SB_MAKE64(24)
+#define M_SYS_NUM_CPUS            _SB_MAKEMASK(4,S_SYS_NUM_CPUS)
+#define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x,S_SYS_NUM_CPUS)
+#define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS)
+
 
 /* XXX: discourage people from using these constants.  */
 #define S_SYS_PART                  _SB_MAKE64(16)
@@ -83,6 +125,8 @@
 #define K_SYS_PART_BCM1120          0x1121
 #define K_SYS_PART_BCM1125          0x1123
 #define K_SYS_PART_BCM1125H         0x1124
+#define K_SYS_PART_BCM1122          0x1113
+
 
 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
 #define S_SYS_SOC_TYPE              _SB_MAKE64(16)
@@ -96,6 +140,8 @@
 #define K_SYS_SOC_TYPE_BCM1125      0x3
 #define K_SYS_SOC_TYPE_BCM1125H     0x4
 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5         /* 1250pass2 w/ 1/2 L2.  */
+#define K_SYS_SOC_TYPE_BCM1x80      0x6
+#define K_SYS_SOC_TYPE_BCM1x55      0x7
 
 /*
  * Calculate correct SOC type given a copy of system revision register.
@@ -127,10 +173,12 @@
 #define V_SYS_WID(x)                _SB_MAKEVALUE(x,S_SYS_WID)
 #define G_SYS_WID(x)                _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
 
-/* System Manufacturing Register
-* Register: SCD_SYSTEM_MANUF
-*/
+/*
+ * System Manufacturing Register
+ * Register: SCD_SYSTEM_MANUF
+ */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
 /* Wafer ID: bits 31:0 */
 #define S_SYS_WAFERID1_200        _SB_MAKE64(0)
 #define M_SYS_WAFERID1_200        _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
@@ -139,8 +187,8 @@
 
 #define S_SYS_BIN                 _SB_MAKE64(32)
 #define M_SYS_BIN                 _SB_MAKEMASK(4,S_SYS_BIN)
-#define V_SYS_BIN                 _SB_MAKEVALUE(x,S_SYS_BIN)
-#define G_SYS_BIN                 _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
+#define V_SYS_BIN(x)              _SB_MAKEVALUE(x,S_SYS_BIN)
+#define G_SYS_BIN(x)              _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
 
 /* Wafer ID: bits 39:36 */
 #define S_SYS_WAFERID2_200        _SB_MAKE64(36)
@@ -163,12 +211,14 @@
 #define M_SYS_YPOS                _SB_MAKEMASK(6,S_SYS_YPOS)
 #define V_SYS_YPOS(x)             _SB_MAKEVALUE(x,S_SYS_YPOS)
 #define G_SYS_YPOS(x)             _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
+#endif
 
 /*
  * System Config Register (Table 4-2)
  * Register: SCD_SYSTEM_CFG
  */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
 #define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
 #define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
@@ -253,6 +303,8 @@
 #define M_SYS_SW_FLAG               _SB_MAKEMASK1(63)
 #endif /* 1250 PASS2 || 112x PASS1 */
 
+#endif
+
 
 /*
  * Mailbox Registers (Table 4-3)
@@ -326,6 +378,7 @@
  * System Performance Counters
  */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define S_SPC_CFG_SRC0            0
 #define M_SPC_CFG_SRC0            _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
 #define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
@@ -348,6 +401,7 @@
 
 #define M_SPC_CFG_CLEAR         _SB_MAKEMASK1(32)
 #define M_SPC_CFG_ENABLE        _SB_MAKEMASK1(33)
+#endif
 
 
 /*
@@ -412,6 +466,7 @@
  * Address Trap Registers
  */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define M_ATRAP_INDEX             _SB_MAKEMASK(4,0)
 #define M_ATRAP_ADDRESS           _SB_MAKEMASK(40,0)
 
@@ -436,7 +491,6 @@
 #define K_BUS_AGENT_IOB0        2
 #define K_BUS_AGENT_IOB1        3
 #define K_BUS_AGENT_SCD 4
-#define K_BUS_AGENT_RESERVED    5
 #define K_BUS_AGENT_L2C 6
 #define K_BUS_AGENT_MC  7
 
@@ -454,10 +508,14 @@
 #define K_ATRAP_CFG_CATTR_NOTNONCOH     6
 #define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
 
+#endif  /* 1250/112x */
+
 /*
  * Trace Buffer Config register
  */
 
+#if SIBYTE_HDR_FEATURE_1250_112x
+
 #define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
 #define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
 #define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
@@ -475,6 +533,8 @@
 #define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
 #define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
 
+#endif  /* 1250/112x */
+
 /*
  * Trace Event registers
  */
@@ -578,5 +638,7 @@
 #define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
 #define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
 #define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
+#define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
+#define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
 
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 335c53e92936..279a912213cd 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -6,9 +6,8 @@
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's SMbus devices.
     *
-    *  SB1250 specification level:  01/02/2002
-    *
-    *  Author:  Mitch Lichtenberg
+    *  SB1250 specification level:  10/21/02
+    *  BCM1280 specification level:  11/24/03
     *
     *********************************************************************
     *
@@ -47,6 +46,7 @@
 
 #define K_SMB_FREQ_400KHZ           0x1F
 #define K_SMB_FREQ_100KHZ           0x7D
+#define K_SMB_FREQ_10KHZ            1250
 
 #define S_SMB_CMD                   0
 #define M_SMB_CMD                   _SB_MAKEMASK(8,S_SMB_CMD)
@@ -58,7 +58,11 @@
 
 #define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
 #define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
-#define M_SMB_DATA_OUT              _SB_MAKEMASK1(4)
+
+#define S_SMB_DATA_OUT              4
+#define M_SMB_DATA_OUT              _SB_MAKEMASK1(S_SMB_DATA_OUT)
+#define V_SMB_DATA_OUT(x)           _SB_MAKEVALUE(x,S_SMB_DATA_OUT)
+
 #define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
 #define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
 #define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
@@ -71,8 +75,23 @@
 #define M_SMB_BUSY                  _SB_MAKEMASK1(0)
 #define M_SMB_ERROR                 _SB_MAKEMASK1(1)
 #define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
-#define M_SMB_REF                   _SB_MAKEMASK1(6)
-#define M_SMB_DATA_IN               _SB_MAKEMASK1(7)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_SMB_SCL_IN                5
+#define M_SMB_SCL_IN                _SB_MAKEMASK1(S_SMB_SCL_IN)
+#define V_SMB_SCL_IN(x)             _SB_MAKEVALUE(x,S_SMB_SCL_IN)
+#define G_SMB_SCL_IN(x)             _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_SMB_REF                   6
+#define M_SMB_REF                   _SB_MAKEMASK1(S_SMB_REF)
+#define V_SMB_REF(x)                _SB_MAKEVALUE(x,S_SMB_REF)
+#define G_SMB_REF(x)                _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF)
+
+#define S_SMB_DATA_IN               7
+#define M_SMB_DATA_IN               _SB_MAKEMASK1(S_SMB_DATA_IN)
+#define V_SMB_DATA_IN(x)            _SB_MAKEVALUE(x,S_SMB_DATA_IN)
+#define G_SMB_DATA_IN(x)            _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN)
 
 /*
  * SMBus Start/Command registers (Table 14-9)
@@ -132,16 +151,14 @@
 #define V_SPEC_MB(x)                _SB_MAKEVALUE(x,S_SPEC_PEC)
 
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #define S_SMB_CMDH                  8
-#define M_SMB_CMDH                  _SB_MAKEMASK(8,S_SMBH_CMD)
-#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x,S_SMBH_CMD)
+#define M_SMB_CMDH                  _SB_MAKEMASK(8,S_SMB_CMDH)
+#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x,S_SMB_CMDH)
 
 #define M_SMB_EXTEND                _SB_MAKEMASK1(14)
 
-#define M_SMB_DIR                   _SB_MAKEMASK1(13)
-
 #define S_SMB_DFMT                  8
 #define M_SMB_DFMT                  _SB_MAKEMASK(3,S_SMB_DFMT)
 #define V_SMB_DFMT(x)               _SB_MAKEVALUE(x,S_SMB_DFMT)
@@ -165,6 +182,23 @@
 #define V_SMB_DFMT_CMD5BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
 #define V_SMB_DFMT_RESERVED         V_SMB_DFMT(K_SMB_DFMT_RESERVED)
 
-#endif /* 1250 PASS2 || 112x PASS1 */
+#define S_SMB_AFMT                  11
+#define M_SMB_AFMT                  _SB_MAKEMASK(2,S_SMB_AFMT)
+#define V_SMB_AFMT(x)               _SB_MAKEVALUE(x,S_SMB_AFMT)
+#define G_SMB_AFMT(x)               _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT)
+
+#define K_SMB_AFMT_NONE             0
+#define K_SMB_AFMT_ADDR             1
+#define K_SMB_AFMT_ADDR_CMD1BYTE    2
+#define K_SMB_AFMT_ADDR_CMD2BYTE    3
+
+#define V_SMB_AFMT_NONE             V_SMB_AFMT(K_SMB_AFMT_NONE)
+#define V_SMB_AFMT_ADDR             V_SMB_AFMT(K_SMB_AFMT_ADDR)
+#define V_SMB_AFMT_ADDR_CMD1BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
+#define V_SMB_AFMT_ADDR_CMD2BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
+
+#define M_SMB_DIR                   _SB_MAKEMASK1(13)
+
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index fa2760d38b8b..dd154ac505d8 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index 923ea4f44e0f..e87045e62bf0 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -8,8 +8,6 @@
     *
     *  SB1250 specification level:  User's manual 1/02/02
     *
-    *  Author:  Mitch Lichtenberg
-    *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
@@ -240,7 +238,12 @@
  */
 
 #define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
-#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(1)
+
+#define S_DUART_ISR_RX_A            1
+#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(S_DUART_ISR_RX_A)
+#define V_DUART_ISR_RX_A(x)         _SB_MAKEVALUE(x,S_DUART_ISR_RX_A)
+#define G_DUART_ISR_RX_A(x)         _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A)
+
 #define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
 #define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
 #define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
@@ -331,7 +334,7 @@
 #define M_DUART_OUT_PIN_CLR(chan) \
     (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
  * Full Interrupt Control Register
  */
@@ -345,7 +348,7 @@
 #define M_DUART_INT_TIME           _SB_MAKEMASK(4,S_DUART_INT_TIME)
 #define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x,S_DUART_INT_TIME)
 #define G_DUART_INT_TIME(x)        _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 
 /* ********************************************************************** */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 97fa0494c30c..06e1d528e03a 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -34,7 +34,7 @@
 #define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
 #endif
 #ifdef CONFIG_SIBYTE_LITTLESUR
-#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)"
+#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
 #define SIBYTE_HAVE_PCMCIA 0
 #define SIBYTE_HAVE_IDE    1
 #define SIBYTE_DEFAULT_CONSOLE "cfe0"
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index f7fbebaa0744..8edabb0be23f 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -27,14 +27,15 @@ struct sigcontext {
         unsigned int            sc_fpc_csr;
         unsigned int            sc_fpc_eir;     /* Unused */
         unsigned int            sc_used_math;
-        unsigned int            sc_ssflags;     /* Unused */
+        unsigned int            sc_dsp;         /* dsp status, was sc_ssflags */
         unsigned long long      sc_mdhi;
         unsigned long long      sc_mdlo;
-
-        unsigned int            sc_cause;       /* Unused */
-        unsigned int            sc_badvaddr;    /* Unused */
-
-        unsigned long           sc_sigset[4];   /* kernel's sigset_t */
+        unsigned long           sc_hi1;         /* Was sc_cause */
+        unsigned long           sc_lo1;         /* Was sc_badvaddr */
+        unsigned long           sc_hi2;         /* Was sc_sigset[4] */
+        unsigned long           sc_lo2;
+        unsigned long           sc_hi3;
+        unsigned long           sc_lo3;
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@@ -48,19 +49,19 @@ struct sigcontext {
  * Warning: this structure illdefined with sc_badvaddr being just an unsigned
  * int so it was changed to unsigned long in 2.6.0-test1.  This may break
  * binary compatibility - no prisoners.
+ * DSP ASE in 2.6.12-rc4.  Turn sc_mdhi and sc_mdlo into an array of four
+ * entries, add sc_dsp and sc_reserved for padding.  No prisoners.
  */
 struct sigcontext {
         unsigned long   sc_regs[32];
         unsigned long   sc_fpregs[32];
-        unsigned long   sc_mdhi;
-        unsigned long   sc_mdlo;
+        unsigned long   sc_hi[4];
+        unsigned long   sc_lo[4];
         unsigned long   sc_pc;
-        unsigned long   sc_badvaddr;
-        unsigned int    sc_status;
         unsigned int    sc_fpc_csr;
-        unsigned int    sc_fpc_eir;
         unsigned int    sc_used_math;
-        unsigned int    sc_cause;
+        unsigned int    sc_dsp;
+        unsigned int    sc_reserved;
 };
 
 #ifdef __KERNEL__
@@ -68,23 +69,24 @@ struct sigcontext {
 #include <linux/posix_types.h>
 
 struct sigcontext32 {
-        __u32   sc_regmask;             /* Unused */
-        __u32   sc_status;
-        __u64   sc_pc;
-        __u64   sc_regs[32];
-        __u64   sc_fpregs[32];
-        __u32   sc_ownedfp;             /* Unused */
-        __u32   sc_fpc_csr;
-        __u32   sc_fpc_eir;             /* Unused */
-        __u32   sc_used_math;
-        __u32   sc_ssflags;             /* Unused */
-        __u64   sc_mdhi;
-        __u64   sc_mdlo;
-
-        __u32   sc_cause;               /* Unused */
-        __u32   sc_badvaddr;            /* Unused */
-
-        __u32   sc_sigset[4];           /* kernel's sigset_t */
+        __u32           sc_regmask;     /* Unused */
+        __u32           sc_status;
+        __u64           sc_pc;
+        __u64           sc_regs[32];
+        __u64           sc_fpregs[32];
+        __u32           sc_ownedfp;     /* Unused */
+        __u32           sc_fpc_csr;
+        __u32           sc_fpc_eir;     /* Unused */
+        __u32           sc_used_math;
+        __u32           sc_dsp;         /* dsp status, was sc_ssflags */
+        __u64           sc_mdhi;
+        __u64           sc_mdlo;
+        __u32           sc_hi1;         /* Was sc_cause */
+        __u32           sc_lo1;         /* Was sc_badvaddr */
+        __u32           sc_hi2;         /* Was sc_sigset[4] */
+        __u32           sc_lo2;
+        __u32           sc_hi3;
+        __u32           sc_lo3;
 };
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index 698becab5a9e..2ba313d94a78 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -11,6 +11,7 @@
 
 #include <linux/config.h>
 
+#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
 #undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
 
 #define HAVE_ARCH_SIGINFO_T
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index f2c470f1d369..8ca539e80d87 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -98,12 +98,39 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define MINSIGSTKSZ    2048
 #define SIGSTKSZ       8192
 
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ flag is for shared interrupt support on PCI and EISA.
+ */
+#define SA_SAMPLE_RANDOM        SA_RESTART
+
+#ifdef CONFIG_TRAD_SIGNALS
+#define sig_uses_siginfo(ka)    ((ka)->sa.sa_flags & SA_SIGINFO)
+#else
+#define sig_uses_siginfo(ka)    (1)
+#endif
+
+#endif /* __KERNEL__ */
+
 #define SIG_BLOCK       1       /* for blocking signals */
 #define SIG_UNBLOCK     2       /* for unblocking signals */
 #define SIG_SETMASK     3       /* for setting the signal mask */
 #define SIG_SETMASK32   256     /* Goodie from SGI for BSD compatibility:
                                    set only the low 32 bit of the sigset.  */
-#include <asm-generic/signal.h>
+
+/* Type of a signal handler.  */
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+
+/* Fake signal functions */
+#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
 
 struct sigaction {
         unsigned int    sa_flags;
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
index 0e00dd474afc..fb78773a5efe 100644
--- a/include/asm-mips/sn/sn0/arch.h
+++ b/include/asm-mips/sn/sn0/arch.h
@@ -74,13 +74,8 @@
 #define MAX_MEM_SLOTS   32                      /* max slots per node */
 #endif /* defined(N_MODE) */
 
-#if SABLE_RTL
-#define SLOT_SHIFT              (28)
-#define SLOT_MIN_MEM_SIZE       (16*1024*1024)
-#else
 #define SLOT_SHIFT              (27)
 #define SLOT_MIN_MEM_SIZE       (32*1024*1024)
-#endif
 
 #define CPUS_PER_NODE           2       /* CPUs on a single hub */
 #define CPUS_PER_NODE_SHFT      1       /* Bits to shift in the node number */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index 753b6620e6fa..0bb31e5aaca6 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -37,8 +37,6 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 #define SO_ERROR        0x1007  /* get error status and clear */
 #define SO_SNDBUF       0x1001  /* Send buffer size. */
 #define SO_RCVBUF       0x1002  /* Receive buffer. */
-#define SO_SNDBUFFORCE  0x100a
-#define SO_RCVBUFFORCE  0x100b
 #define SO_SNDLOWAT     0x1003  /* send low-water mark */
 #define SO_RCVLOWAT     0x1004  /* receive low-water mark */
 #define SO_SNDTIMEO     0x1005  /* send timeout */
@@ -69,6 +67,8 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 #define SCM_TIMESTAMP           SO_TIMESTAMP
 
 #define SO_PEERSEC              30
+#define SO_SNDBUFFORCE          31
+#define SO_RCVBUFFORCE          33
 
 #ifdef __KERNEL__
 
@@ -92,6 +92,7 @@ enum sock_type {
         SOCK_RAW        = 3,
         SOCK_RDM        = 4,
         SOCK_SEQPACKET  = 5,
+        SOCK_DCCP       = 6,
         SOCK_PACKET     = 10,
 };
 
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 4d0135b11156..669b8e349ff2 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -9,17 +9,16 @@
 #ifndef _ASM_SPINLOCK_H
 #define _ASM_SPINLOCK_H
 
-#include <linux/config.h>
 #include <asm/war.h>
 
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
 
-#define __raw_spin_is_locked(x) ((x)->lock != 0)
+#define __raw_spin_is_locked(x)       ((x)->lock != 0)
 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 #define __raw_spin_unlock_wait(x) \
-                do { cpu_relax(); } while ((x)->lock)
+        do { cpu_relax(); } while ((x)->lock)
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -119,6 +118,18 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
  * read-locks.
  */
 
+/*
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
+
+/*
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(rw)        (!(rw)->lock)
+
 static inline void __raw_read_lock(raw_rwlock_t *rw)
 {
         unsigned int tmp;
@@ -197,8 +208,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                 "        lui    %1, 0x8000                              \n"
                 "       sc      %1, %0                                  \n"
                 "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       sync                                            \n"
+                "        sync                                           \n"
                 "       .set    reorder                                 \n"
                 : "=m" (rw->lock), "=&r" (tmp)
                 : "m" (rw->lock)
@@ -211,8 +221,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                 "        lui    %1, 0x8000                              \n"
                 "       sc      %1, %0                                  \n"
                 "       beqz    %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       sync                                            \n"
+                "        sync                                           \n"
                 "       .set    reorder                                 \n"
                 : "=m" (rw->lock), "=&r" (tmp)
                 : "m" (rw->lock)
@@ -246,8 +255,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
                 "        lui    %1, 0x8000                              \n"
                 "       sc      %1, %0                                  \n"
                 "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       sync                                            \n"
+                "        sync                                           \n"
                 "       li      %2, 1                                   \n"
                 "       .set    reorder                                 \n"
                 "2:                                                     \n"
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 7b5e64600bc8..a8919dcc93c8 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -60,7 +60,6 @@
                 mfc0    k0, CP0_CONTEXT
                 lui     k1, %hi(kernelsp)
                 srl     k0, k0, 23
-                sll     k0, k0, 2
                 addu    k1, k0
                 LONG_L  k1, %lo(kernelsp)(k1)
 #endif
@@ -76,9 +75,14 @@
 #endif
 #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
                 MFC0    k1, CP0_CONTEXT
+                lui     k0, %highest(kernelsp)
                 dsrl    k1, 23
-                dsll    k1, k1, 3
-                LONG_L  k1, kernelsp(k1)
+                daddiu  k0, %higher(kernelsp)
+                dsll    k0, k0, 16
+                daddiu  k0, %hi(kernelsp)
+                dsll    k0, k0, 16
+                daddu   k1, k1, k0
+                LONG_L  k1, %lo(kernelsp)(k1)
 #endif
                 .endm
 
@@ -86,25 +90,28 @@
 #ifdef CONFIG_32BIT
                 mfc0    \temp, CP0_CONTEXT
                 srl     \temp, 23
-                sll     \temp, 2
-                LONG_S  \stackp, kernelsp(\temp)
 #endif
 #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
                 lw      \temp, TI_CPU(gp)
                 dsll    \temp, 3
-                lui     \temp2, %hi(kernelsp)
-                daddu   \temp, \temp2
-                LONG_S  \stackp, %lo(kernelsp)(\temp)
 #endif
 #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
-                lw      \temp, TI_CPU(gp)
-                dsll    \temp, 3
-                LONG_S  \stackp, kernelsp(\temp)
+                MFC0    \temp, CP0_CONTEXT
+                dsrl    \temp, 23
 #endif
+                LONG_S  \stackp, kernelsp(\temp)
                 .endm
 #else
                 .macro  get_saved_sp    /* Uniprocessor variation */
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
+                lui     k1, %highest(kernelsp)
+                daddiu  k1, %higher(kernelsp)
+                dsll    k1, k1, 16
+                daddiu  k1, %hi(kernelsp)
+                dsll    k1, k1, 16
+#else
                 lui     k1, %hi(kernelsp)
+#endif
                 LONG_L  k1, %lo(kernelsp)(k1)
                 .endm
 
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 6663efd49b27..330c4e497af3 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -17,6 +17,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/cpu-features.h>
+#include <asm/dsp.h>
 #include <asm/ptrace.h>
 #include <asm/war.h>
 #include <asm/interrupt.h>
@@ -70,7 +71,7 @@
  * does not enforce ordering, since there is no data dependency between
  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like thiswhere there are no data dependencies.
+ * in cases like this where there are no data dependencies.
  */
 
 #define read_barrier_depends()  do { } while(0)
@@ -154,15 +155,15 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti);
 
 struct task_struct;
 
-#define switch_to(prev,next,last) \
-do { \
-        (last) = resume(prev, next, next->thread_info); \
+#define switch_to(prev,next,last)                                       \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(prev);                                       \
+        (last) = resume(prev, next, next->thread_info);                 \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(current);                                 \
 } while(0)
 
-#define ROT_IN_PIECES                                                   \
-        "       .set    noreorder       \n"                             \
-        "       .set    reorder         \n"
-
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
         __u32 retval;
@@ -171,14 +172,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                 unsigned long dummy;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
                 "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
                 "       sc      %2, %1                                  \n"
                 "       beqzl   %2, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                 : "R" (*m), "Jr" (val)
                 : "memory");
@@ -186,13 +190,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                 unsigned long dummy;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
                 "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
                 "       sc      %2, %1                                  \n"
                 "       beqz    %2, 1b                                  \n"
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                 : "R" (*m), "Jr" (val)
                 : "memory");
@@ -217,14 +225,15 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                 unsigned long dummy;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %3                  # xchg_u64      \n"
                 "       move    %2, %z4                                 \n"
                 "       scd     %2, %1                                  \n"
                 "       beqzl   %2, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                 : "R" (*m), "Jr" (val)
                 : "memory");
@@ -232,6 +241,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                 unsigned long dummy;
 
                 __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %3                  # xchg_u64      \n"
                 "       move    %2, %z4                                 \n"
                 "       scd     %2, %1                                  \n"
@@ -239,6 +249,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                 : "R" (*m), "Jr" (val)
                 : "memory");
@@ -286,34 +297,41 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 __asm__ __volatile__(
+                "       .set    push                                    \n"
                 "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
                 "       bne     %0, %z3, 2f                             \n"
+                "       .set    mips0                                   \n"
                 "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
                 "       sc      $1, %1                                  \n"
                 "       beqzl   $1, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
                 "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                 : "=&r" (retval), "=m" (*m)
                 : "R" (*m), "Jr" (old), "Jr" (new)
                 : "memory");
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
+                "       .set    push                                    \n"
                 "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
                 "       bne     %0, %z3, 2f                             \n"
+                "       .set    mips0                                   \n"
                 "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
                 "       sc      $1, %1                                  \n"
                 "       beqz    $1, 1b                                  \n"
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
                 "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                 : "=&r" (retval), "=m" (*m)
                 : "R" (*m), "Jr" (old), "Jr" (new)
                 : "memory");
@@ -338,24 +356,27 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 
         if (cpu_has_llsc) {
                 __asm__ __volatile__(
+                "       .set    push                                    \n"
                 "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
                 "       bne     %0, %z3, 2f                             \n"
                 "       move    $1, %z4                                 \n"
                 "       scd     $1, %1                                  \n"
                 "       beqzl   $1, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                 "       sync                                            \n"
 #endif
                 "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                 : "=&r" (retval), "=m" (*m)
                 : "R" (*m), "Jr" (old), "Jr" (new)
                 : "memory");
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
+                "       .set    push                                    \n"
                 "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
                 "       bne     %0, %z3, 2f                             \n"
                 "       move    $1, %z4                                 \n"
@@ -365,7 +386,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
                 "       sync                                            \n"
 #endif
                 "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                 : "=&r" (retval), "=m" (*m)
                 : "R" (*m), "Jr" (old), "Jr" (new)
                 : "memory");
@@ -406,18 +427,20 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 
 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
 
+extern void set_handler (unsigned long offset, void *addr, unsigned long len);
+extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
+extern void *set_vi_handler (int n, void *addr);
+extern void *set_vi_srs_handler (int n, void *addr, int regset);
 extern void *set_except_vector(int n, void *addr);
 extern void per_cpu_trap_init(void);
 
-extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
-        const char *func, unsigned long line);
-extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
-        const char *func, unsigned long line);
+extern NORET_TYPE void die(const char *, struct pt_regs *);
 
-#define die(msg, regs)                                                  \
-        __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
-#define die_if_kernel(msg, regs)                                        \
-        __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
+static inline void die_if_kernel(const char *str, struct pt_regs *regs)
+{
+        if (unlikely(!user_mode(regs)))
+                die(str, regs);
+}
 
 extern int stop_a_enabled;
 
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index a70cb0854c8a..e6c24472e03f 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -26,6 +26,7 @@ struct thread_info {
         struct task_struct      *task;          /* main task structure */
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
+        unsigned long           tp_value;       /* thread pointer */
         __u32                   cpu;            /* current CPU */
         int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
@@ -114,6 +115,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_SYSCALL_AUDIT       4       /* syscall auditing active */
+#define TIF_SECCOMP             5       /* secure computing */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
 #define TIF_MEMDIE              18
@@ -124,13 +126,14 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 
-#define _TIF_WORK_MASK          0x0000ffef      /* work to do on
-                                                   interrupt/exception return */
-#define _TIF_ALLWORK_MASK       0x8000ffff      /* work to do on any return to
-                                                   u-space */
+/* work to do on interrupt/exception return */
+#define _TIF_WORK_MASK          (0x0000ffef & ~_TIF_SECCOMP)
+/* work to do on any return to u-space */
+#define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
 
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index 179012263007..d02e019b0127 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -21,4 +21,7 @@
 extern void (*board_be_init)(void);
 extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 
+extern void (*board_nmi_handler_setup)(void);
+extern void (*board_ejtag_handler_setup)(void);
+
 #endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
new file mode 100644
index 000000000000..0fbedafdcea8
--- /dev/null
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -0,0 +1,207 @@
+/*
+ * linux/include/asm-mips/tx4938/rbtx4938.h
+ * Definitions for TX4937/TX4938
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TX_BOARDS_RBTX4938_H
+#define __ASM_TX_BOARDS_RBTX4938_H
+
+#include <asm/addrspace.h>
+#include <asm/tx4938/tx4938.h>
+
+/* CS */
+#define RBTX4938_CE0    0x1c000000      /* 64M */
+#define RBTX4938_CE2    0x17f00000      /* 1M */
+
+/* Address map */
+#define RBTX4938_FPGA_REG_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000000)
+#define RBTX4938_FPGA_REV_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000002)
+#define RBTX4938_CONFIG1_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000004)
+#define RBTX4938_CONFIG2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000006)
+#define RBTX4938_CONFIG3_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000008)
+#define RBTX4938_LED_ADDR       (KSEG1 + RBTX4938_CE2 + 0x00001000)
+#define RBTX4938_DIPSW_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00001002)
+#define RBTX4938_BDIPSW_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00001004)
+#define RBTX4938_IMASK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002000)
+#define RBTX4938_IMASK2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002002)
+#define RBTX4938_INTPOL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002004)
+#define RBTX4938_ISTAT_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002006)
+#define RBTX4938_ISTAT2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002008)
+#define RBTX4938_IMSTAT_ADDR    (KSEG1 + RBTX4938_CE2 + 0x0000200a)
+#define RBTX4938_IMSTAT2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x0000200c)
+#define RBTX4938_SOFTINT_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00003000)
+#define RBTX4938_PIOSEL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00005000)
+#define RBTX4938_SPICS_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005002)
+#define RBTX4938_SFPWR_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005008)
+#define RBTX4938_SFVOL_ADDR     (KSEG1 + RBTX4938_CE2 + 0x0000500a)
+#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
+#define RBTX4938_SOFTRESETLOCK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00007002)
+#define RBTX4938_PCIRESET_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00007004)
+#define RBTX4938_ETHER_BASE     (KSEG1 + RBTX4938_CE2 + 0x00020000)
+
+/* Ethernet port address (Jumperless Mode (W12:Open)) */
+#define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4938_INTB_PCID      0
+#define RBTX4938_INTB_PCIC      1
+#define RBTX4938_INTB_PCIB      2
+#define RBTX4938_INTB_PCIA      3
+#define RBTX4938_INTB_RTC       4
+#define RBTX4938_INTB_ATA       5
+#define RBTX4938_INTB_MODEM     6
+#define RBTX4938_INTB_SWINT     7
+#define RBTX4938_INTF_PCID      (1 << RBTX4938_INTB_PCID)
+#define RBTX4938_INTF_PCIC      (1 << RBTX4938_INTB_PCIC)
+#define RBTX4938_INTF_PCIB      (1 << RBTX4938_INTB_PCIB)
+#define RBTX4938_INTF_PCIA      (1 << RBTX4938_INTB_PCIA)
+#define RBTX4938_INTF_RTC       (1 << RBTX4938_INTB_RTC)
+#define RBTX4938_INTF_ATA       (1 << RBTX4938_INTB_ATA)
+#define RBTX4938_INTF_MODEM     (1 << RBTX4938_INTB_MODEM)
+#define RBTX4938_INTF_SWINT     (1 << RBTX4938_INTB_SWINT)
+
+#define rbtx4938_fpga_rev_ptr   \
+        ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
+#define rbtx4938_led_ptr        \
+        ((volatile unsigned char *)RBTX4938_LED_ADDR)
+#define rbtx4938_dipsw_ptr      \
+        ((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
+#define rbtx4938_bdipsw_ptr     \
+        ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
+#define rbtx4938_imask_ptr      \
+        ((volatile unsigned char *)RBTX4938_IMASK_ADDR)
+#define rbtx4938_imask2_ptr     \
+        ((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
+#define rbtx4938_intpol_ptr     \
+        ((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
+#define rbtx4938_istat_ptr      \
+        ((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
+#define rbtx4938_istat2_ptr     \
+        ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
+#define rbtx4938_imstat_ptr     \
+        ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
+#define rbtx4938_imstat2_ptr    \
+        ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
+#define rbtx4938_softint_ptr    \
+        ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
+#define rbtx4938_piosel_ptr     \
+        ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
+#define rbtx4938_spics_ptr      \
+        ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
+#define rbtx4938_sfpwr_ptr      \
+        ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
+#define rbtx4938_sfvol_ptr      \
+        ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
+#define rbtx4938_softreset_ptr  \
+        ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
+#define rbtx4938_softresetlock_ptr      \
+        ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
+#define rbtx4938_pcireset_ptr   \
+        ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
+
+/* SPI */
+#define RBTX4938_SEEPROM1_CHIPID        0
+#define RBTX4938_SEEPROM2_CHIPID        1
+#define RBTX4938_SEEPROM3_CHIPID        2
+#define RBTX4938_SRTC_CHIPID    3
+
+/*
+ * IRQ mappings
+ */
+
+#define RBTX4938_SOFT_INT0      0       /* not used */
+#define RBTX4938_SOFT_INT1      1       /* not used */
+#define RBTX4938_IRC_INT        2
+#define RBTX4938_TIMER_INT      7
+
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define RBTX4938_NR_IRQ_LOCAL   8
+#define RBTX4938_NR_IRQ_IRC     32      /* On-Chip IRC */
+#define RBTX4938_NR_IRQ_IOC     8
+
+#define MI8259_IRQ_ISA_RAW_BEG   0      /* optional backplane i8259 */
+#define MI8259_IRQ_ISA_RAW_END  15
+#define TX4938_IRQ_CP0_RAW_BEG   0      /* tx4938 cpu built-in cp0 */
+#define TX4938_IRQ_CP0_RAW_END   7
+#define TX4938_IRQ_PIC_RAW_BEG   0      /* tx4938 cpu build-in pic */
+#define TX4938_IRQ_PIC_RAW_END  31
+
+#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG      /*  0 */
+#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END      /* 15 */
+
+#define TX4938_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG)     /* 16 */
+#define TX4938_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END)     /* 23 */
+
+#define TX4938_IRQ_PIC_BEG  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG)     /* 24 */
+#define TX4938_IRQ_PIC_END  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END)     /* 55 */
+#define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
+#define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
+#define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
+#define TX4938_IRQ_USER1            (TX4938_IRQ_CP0_BEG+1)
+#define TX4938_IRQ_CPU_TIMER        (TX4938_IRQ_CP0_BEG+7)
+
+#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG   0
+#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END   7
+
+#define TOSHIBA_RBTX4938_IRQ_IOC_BEG  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
+#define TOSHIBA_RBTX4938_IRQ_IOC_END  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
+#define RBTX4938_IRQ_LOCAL      TX4938_IRQ_CP0_BEG
+#define RBTX4938_IRQ_IRC        (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
+#define RBTX4938_IRQ_IOC        (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
+#define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
+
+#define RBTX4938_IRQ_LOCAL_SOFT0        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
+#define RBTX4938_IRQ_LOCAL_SOFT1        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
+#define RBTX4938_IRQ_LOCAL_IRC  (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
+#define RBTX4938_IRQ_LOCAL_TIMER        (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
+#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
+#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
+#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
+#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
+#define RBTX4938_IRQ_IRC_DMA(ch,n)      (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
+#define RBTX4938_IRQ_IRC_PIO    (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
+#define RBTX4938_IRQ_IRC_PDMAC  (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
+#define RBTX4938_IRQ_IRC_PCIC   (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
+#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
+#define RBTX4938_IRQ_IRC_NDFMC  (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
+#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
+#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
+#define RBTX4938_IRQ_IRC_ACLC   (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
+#define RBTX4938_IRQ_IRC_ACLCPME        (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
+#define RBTX4938_IRQ_IRC_PCIC1  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
+#define RBTX4938_IRQ_IRC_SPI    (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
+#define RBTX4938_IRQ_IOC_PCID   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
+#define RBTX4938_IRQ_IOC_PCIC   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
+#define RBTX4938_IRQ_IOC_PCIB   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
+#define RBTX4938_IRQ_IOC_PCIA   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
+#define RBTX4938_IRQ_IOC_RTC    (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
+#define RBTX4938_IRQ_IOC_ATA    (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
+#define RBTX4938_IRQ_IOC_MODEM  (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
+#define RBTX4938_IRQ_IOC_SWINT  (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
+
+
+/* IOC (PCI, etc) */
+#define RBTX4938_IRQ_IOCINT     (TX4938_IRQ_NEST_EXT_ON_PIC)
+/* Onboard 10M Ether */
+#define RBTX4938_IRQ_ETHER      (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
+
+#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
+#define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
+
+/* IRCR : Int. Control */
+#define TX4938_IRCR_LOW  0x00000000
+#define TX4938_IRCR_HIGH 0x00000001
+#define TX4938_IRCR_DOWN 0x00000002
+#define TX4938_IRCR_UP   0x00000003
+
+#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
new file mode 100644
index 000000000000..0dbbab820a5a
--- /dev/null
+++ b/include/asm-mips/tx4938/spi.h
@@ -0,0 +1,74 @@
+/*
+ * linux/include/asm-mips/tx4938/spi.h
+ * Definitions for TX4937/TX4938 SPI
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
+#define __ASM_TX_BOARDS_TX4938_SPI_H
+
+/* SPI */
+struct spi_dev_desc {
+        unsigned int baud;
+        unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
+        unsigned int byteorder:1;       /* 0:LSB-First, 1:MSB-First */
+        unsigned int polarity:1;        /* 0:High-Active */
+        unsigned int phase:1;           /* 0:Sample-Then-Shift */
+};
+
+extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
+extern void txx9_spi_irqinit(int irc_irq) __init;
+extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
+                       unsigned char **inbufs, unsigned int *incounts,
+                       unsigned char **outbufs, unsigned int *outcounts,
+                       int cansleep);
+extern int spi_eeprom_write_enable(int chipid, int enable);
+extern int spi_eeprom_read_status(int chipid);
+extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
+extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
+extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
+
+#define TXX9_IMCLK     (txx9_gbus_clock / 2)
+
+/*
+* SPI
+*/
+
+/* SPMCR : SPI Master Control */
+#define TXx9_SPMCR_OPMODE       0xc0
+#define TXx9_SPMCR_CONFIG       0x40
+#define TXx9_SPMCR_ACTIVE       0x80
+#define TXx9_SPMCR_SPSTP        0x02
+#define TXx9_SPMCR_BCLR 0x01
+
+/* SPCR0 : SPI Status */
+#define TXx9_SPCR0_TXIFL_MASK   0xc000
+#define TXx9_SPCR0_RXIFL_MASK   0x3000
+#define TXx9_SPCR0_SIDIE        0x0800
+#define TXx9_SPCR0_SOEIE        0x0400
+#define TXx9_SPCR0_RBSIE        0x0200
+#define TXx9_SPCR0_TBSIE        0x0100
+#define TXx9_SPCR0_IFSPSE       0x0010
+#define TXx9_SPCR0_SBOS 0x0004
+#define TXx9_SPCR0_SPHA 0x0002
+#define TXx9_SPCR0_SPOL 0x0001
+
+/* SPSR : SPI Status */
+#define TXx9_SPSR_TBSI  0x8000
+#define TXx9_SPSR_RBSI  0x4000
+#define TXx9_SPSR_TBS_MASK      0x3800
+#define TXx9_SPSR_RBS_MASK      0x0700
+#define TXx9_SPSR_SPOE  0x0080
+#define TXx9_SPSR_IFSD  0x0008
+#define TXx9_SPSR_SIDLE 0x0004
+#define TXx9_SPSR_STRDY 0x0002
+#define TXx9_SPSR_SRRDY 0x0001
+
+#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
new file mode 100644
index 000000000000..e25b1a0975cb
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -0,0 +1,706 @@
+/*
+ * linux/include/asm-mips/tx4938/tx4938.h
+ * Definitions for TX4937/TX4938
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TX_BOARDS_TX4938_H
+#define __ASM_TX_BOARDS_TX4938_H
+
+#include <asm/tx4938/tx4938_mips.h>
+
+#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
+#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b)
+
+#define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
+
+#define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
+#define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
+
+#define TX4938_PCIIO_0 0x10000000
+#define TX4938_PCIIO_1 0x01010000
+#define TX4938_PCIMEM_0 0x08000000
+#define TX4938_PCIMEM_1 0x11000000
+
+#define TX4938_PCIIO_SIZE_0 0x01000000
+#define TX4938_PCIIO_SIZE_1 0x00010000
+#define TX4938_PCIMEM_SIZE_0 0x08000000
+#define TX4938_PCIMEM_SIZE_1 0x00010000
+
+#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+
+/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
+#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
+#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
+#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
+#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
+#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
+#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
+#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
+#define TX4938_NR_TMR   3
+#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
+#define TX4938_NR_SIO   2
+#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
+#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
+#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
+#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
+#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
+
+#ifndef _LANGUAGE_ASSEMBLY
+#include <asm/byteorder.h>
+
+#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
+
+#define TX4938_RD08( reg      )   (*(vu08*)(reg))
+#define TX4938_WR08( reg, val )  ((*(vu08*)(reg))=(val))
+
+#define TX4938_RD16( reg      )   (*(vu16*)(reg))
+#define TX4938_WR16( reg, val )  ((*(vu16*)(reg))=(val))
+
+#define TX4938_RD32( reg      )   (*(vu32*)(reg))
+#define TX4938_WR32( reg, val )  ((*(vu32*)(reg))=(val))
+
+#define TX4938_RD64( reg      )   (*(vu64*)(reg))
+#define TX4938_WR64( reg, val )  ((*(vu64*)(reg))=(val))
+
+#define TX4938_RD( reg      ) TX4938_RD32( reg )
+#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef __ASSEMBLY__
+#define _CONST64(c)     c
+#else
+#define _CONST64(c)     c##ull
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+#define endian_def_l2(e1,e2)    \
+        volatile unsigned long e1,e2
+#define endian_def_s2(e1,e2)    \
+        volatile unsigned short e1,e2
+#define endian_def_sb2(e1,e2,e3)        \
+        volatile unsigned short e1;volatile unsigned char e2,e3
+#define endian_def_b2s(e1,e2,e3)        \
+        volatile unsigned char e1,e2;volatile unsigned short e3
+#define endian_def_b4(e1,e2,e3,e4)      \
+        volatile unsigned char e1,e2,e3,e4
+#else
+#define endian_def_l2(e1,e2)    \
+        volatile unsigned long e2,e1
+#define endian_def_s2(e1,e2)    \
+        volatile unsigned short e2,e1
+#define endian_def_sb2(e1,e2,e3)        \
+        volatile unsigned char e3,e2;volatile unsigned short e1
+#define endian_def_b2s(e1,e2,e3)        \
+        volatile unsigned short e3;volatile unsigned char e2,e1
+#define endian_def_b4(e1,e2,e3,e4)      \
+        volatile unsigned char e4,e3,e2,e1
+#endif
+
+
+struct tx4938_sdramc_reg {
+        volatile unsigned long long cr[4];
+        volatile unsigned long long unused0[4];
+        volatile unsigned long long tr;
+        volatile unsigned long long unused1[2];
+        volatile unsigned long long cmd;
+        volatile unsigned long long sfcmd;
+};
+
+struct tx4938_ebusc_reg {
+        volatile unsigned long long cr[8];
+};
+
+struct tx4938_dma_reg {
+        struct tx4938_dma_ch_reg {
+                volatile unsigned long long cha;
+                volatile unsigned long long sar;
+                volatile unsigned long long dar;
+                endian_def_l2(unused0, cntr);
+                endian_def_l2(unused1, sair);
+                endian_def_l2(unused2, dair);
+                endian_def_l2(unused3, ccr);
+                endian_def_l2(unused4, csr);
+        } ch[4];
+        volatile unsigned long long dbr[8];
+        volatile unsigned long long tdhr;
+        volatile unsigned long long midr;
+        endian_def_l2(unused0, mcr);
+};
+
+struct tx4938_pcic_reg {
+        volatile unsigned long pciid;
+        volatile unsigned long pcistatus;
+        volatile unsigned long pciccrev;
+        volatile unsigned long pcicfg1;
+        volatile unsigned long p2gm0plbase;             /* +10 */
+        volatile unsigned long p2gm0pubase;
+        volatile unsigned long p2gm1plbase;
+        volatile unsigned long p2gm1pubase;
+        volatile unsigned long p2gm2pbase;              /* +20 */
+        volatile unsigned long p2giopbase;
+        volatile unsigned long unused0;
+        volatile unsigned long pcisid;
+        volatile unsigned long unused1;         /* +30 */
+        volatile unsigned long pcicapptr;
+        volatile unsigned long unused2;
+        volatile unsigned long pcicfg2;
+        volatile unsigned long g2ptocnt;                /* +40 */
+        volatile unsigned long unused3[15];
+        volatile unsigned long g2pstatus;               /* +80 */
+        volatile unsigned long g2pmask;
+        volatile unsigned long pcisstatus;
+        volatile unsigned long pcimask;
+        volatile unsigned long p2gcfg;          /* +90 */
+        volatile unsigned long p2gstatus;
+        volatile unsigned long p2gmask;
+        volatile unsigned long p2gccmd;
+        volatile unsigned long unused4[24];             /* +a0 */
+        volatile unsigned long pbareqport;              /* +100 */
+        volatile unsigned long pbacfg;
+        volatile unsigned long pbastatus;
+        volatile unsigned long pbamask;
+        volatile unsigned long pbabm;           /* +110 */
+        volatile unsigned long pbacreq;
+        volatile unsigned long pbacgnt;
+        volatile unsigned long pbacstate;
+        volatile unsigned long long g2pmgbase[3];               /* +120 */
+        volatile unsigned long long g2piogbase;
+        volatile unsigned long g2pmmask[3];             /* +140 */
+        volatile unsigned long g2piomask;
+        volatile unsigned long long g2pmpbase[3];               /* +150 */
+        volatile unsigned long long g2piopbase;
+        volatile unsigned long pciccfg;         /* +170 */
+        volatile unsigned long pcicstatus;
+        volatile unsigned long pcicmask;
+        volatile unsigned long unused5;
+        volatile unsigned long long p2gmgbase[3];               /* +180 */
+        volatile unsigned long long p2giogbase;
+        volatile unsigned long g2pcfgadrs;              /* +1a0 */
+        volatile unsigned long g2pcfgdata;
+        volatile unsigned long unused6[8];
+        volatile unsigned long g2pintack;
+        volatile unsigned long g2pspc;
+        volatile unsigned long unused7[12];             /* +1d0 */
+        volatile unsigned long long pdmca;              /* +200 */
+        volatile unsigned long long pdmga;
+        volatile unsigned long long pdmpa;
+        volatile unsigned long long pdmctr;
+        volatile unsigned long long pdmcfg;             /* +220 */
+        volatile unsigned long long pdmsts;
+};
+
+struct tx4938_aclc_reg {
+        volatile unsigned long acctlen;
+        volatile unsigned long acctldis;
+        volatile unsigned long acregacc;
+        volatile unsigned long unused0;
+        volatile unsigned long acintsts;
+        volatile unsigned long acintmsts;
+        volatile unsigned long acinten;
+        volatile unsigned long acintdis;
+        volatile unsigned long acsemaph;
+        volatile unsigned long unused1[7];
+        volatile unsigned long acgpidat;
+        volatile unsigned long acgpodat;
+        volatile unsigned long acslten;
+        volatile unsigned long acsltdis;
+        volatile unsigned long acfifosts;
+        volatile unsigned long unused2[11];
+        volatile unsigned long acdmasts;
+        volatile unsigned long acdmasel;
+        volatile unsigned long unused3[6];
+        volatile unsigned long acaudodat;
+        volatile unsigned long acsurrdat;
+        volatile unsigned long accentdat;
+        volatile unsigned long aclfedat;
+        volatile unsigned long acaudiat;
+        volatile unsigned long unused4;
+        volatile unsigned long acmodoat;
+        volatile unsigned long acmodidat;
+        volatile unsigned long unused5[15];
+        volatile unsigned long acrevid;
+};
+
+
+struct tx4938_tmr_reg {
+        volatile unsigned long tcr;
+        volatile unsigned long tisr;
+        volatile unsigned long cpra;
+        volatile unsigned long cprb;
+        volatile unsigned long itmr;
+        volatile unsigned long unused0[3];
+        volatile unsigned long ccdr;
+        volatile unsigned long unused1[3];
+        volatile unsigned long pgmr;
+        volatile unsigned long unused2[3];
+        volatile unsigned long wtmr;
+        volatile unsigned long unused3[43];
+        volatile unsigned long trr;
+};
+
+struct tx4938_sio_reg {
+        volatile unsigned long lcr;
+        volatile unsigned long dicr;
+        volatile unsigned long disr;
+        volatile unsigned long cisr;
+        volatile unsigned long fcr;
+        volatile unsigned long flcr;
+        volatile unsigned long bgr;
+        volatile unsigned long tfifo;
+        volatile unsigned long rfifo;
+};
+
+struct tx4938_pio_reg {
+        volatile unsigned long dout;
+        volatile unsigned long din;
+        volatile unsigned long dir;
+        volatile unsigned long od;
+        volatile unsigned long flag[2];
+        volatile unsigned long pol;
+        volatile unsigned long intc;
+        volatile unsigned long maskcpu;
+        volatile unsigned long maskext;
+};
+struct tx4938_irc_reg {
+        volatile unsigned long cer;
+        volatile unsigned long cr[2];
+        volatile unsigned long unused0;
+        volatile unsigned long ilr[8];
+        volatile unsigned long unused1[4];
+        volatile unsigned long imr;
+        volatile unsigned long unused2[7];
+        volatile unsigned long scr;
+        volatile unsigned long unused3[7];
+        volatile unsigned long ssr;
+        volatile unsigned long unused4[7];
+        volatile unsigned long csr;
+};
+
+struct tx4938_ndfmc_reg {
+        endian_def_l2(unused0, dtr);
+        endian_def_l2(unused1, mcr);
+        endian_def_l2(unused2, sr);
+        endian_def_l2(unused3, isr);
+        endian_def_l2(unused4, imr);
+        endian_def_l2(unused5, spr);
+        endian_def_l2(unused6, rstr);
+};
+
+struct tx4938_spi_reg {
+        volatile unsigned long mcr;
+        volatile unsigned long cr0;
+        volatile unsigned long cr1;
+        volatile unsigned long fs;
+        volatile unsigned long unused1;
+        volatile unsigned long sr;
+        volatile unsigned long dr;
+        volatile unsigned long unused2;
+};
+
+struct tx4938_sramc_reg {
+        volatile unsigned long long cr;
+};
+
+struct tx4938_ccfg_reg {
+        volatile unsigned long long ccfg;
+        volatile unsigned long long crir;
+        volatile unsigned long long pcfg;
+        volatile unsigned long long tear;
+        volatile unsigned long long clkctr;
+        volatile unsigned long long unused0;
+        volatile unsigned long long garbc;
+        volatile unsigned long long unused1;
+        volatile unsigned long long unused2;
+        volatile unsigned long long ramp;
+        volatile unsigned long long unused3;
+        volatile unsigned long long jmpadr;
+};
+
+#undef endian_def_l2
+#undef endian_def_s2
+#undef endian_def_sb2
+#undef endian_def_b2s
+#undef endian_def_b4
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * NDFMC
+ */
+
+/* NDFMCR : NDFMC Mode Control */
+#define TX4938_NDFMCR_WE        0x80
+#define TX4938_NDFMCR_ECC_ALL   0x60
+#define TX4938_NDFMCR_ECC_RESET 0x60
+#define TX4938_NDFMCR_ECC_READ  0x40
+#define TX4938_NDFMCR_ECC_ON    0x20
+#define TX4938_NDFMCR_ECC_OFF   0x00
+#define TX4938_NDFMCR_CE        0x10
+#define TX4938_NDFMCR_BSPRT     0x04
+#define TX4938_NDFMCR_ALE       0x02
+#define TX4938_NDFMCR_CLE       0x01
+
+/* NDFMCR : NDFMC Status */
+#define TX4938_NDFSR_BUSY       0x80
+
+/* NDFMCR : NDFMC Reset */
+#define TX4938_NDFRSTR_RST      0x01
+
+/*
+ * IRC
+ */
+
+#define TX4938_IR_ECCERR        0
+#define TX4938_IR_WTOERR        1
+#define TX4938_NUM_IR_INT       6
+#define TX4938_IR_INT(n)        (2 + (n))
+#define TX4938_NUM_IR_SIO       2
+#define TX4938_IR_SIO(n)        (8 + (n))
+#define TX4938_NUM_IR_DMA       4
+#define TX4938_IR_DMA(ch,n)     ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */
+#define TX4938_IR_PIO   14
+#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PCIC  16
+#define TX4938_NUM_IR_TMR       3
+#define TX4938_IR_TMR(n)        (17 + (n))
+#define TX4938_IR_NDFMC 21
+#define TX4938_IR_PCIERR        22
+#define TX4938_IR_PCIPME        23
+#define TX4938_IR_ACLC  24
+#define TX4938_IR_ACLCPME       25
+#define TX4938_IR_PCIC1 26
+#define TX4938_IR_SPI   31
+#define TX4938_NUM_IR   32
+/* multiplex */
+#define TX4938_IR_ETH0  TX4938_IR_INT(4)
+#define TX4938_IR_ETH1  TX4938_IR_INT(3)
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
+#define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
+#define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
+#define TX4938_CCFG_TINTDIS     0x01000000
+#define TX4938_CCFG_PCI66       0x00800000
+#define TX4938_CCFG_PCIMODE     0x00400000
+#define TX4938_CCFG_PCI1_66     0x00200000
+#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
+#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
+#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
+#define TX4938_CCFG_BEOW        0x00010000
+#define TX4938_CCFG_WR  0x00008000
+#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_PCIXARB     0x00002000
+#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
+#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
+#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
+#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
+#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
+#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
+#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
+#define TX4938_CCFG_PCI1DMD     0x00000100
+#define TX4938_CCFG_SYSSP_MASK  0x000000c0
+#define TX4938_CCFG_ENDIAN      0x00000004
+#define TX4938_CCFG_HALT        0x00000002
+#define TX4938_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
+#define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
+#define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
+#define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
+#define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
+#define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
+#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SYSCLKEN    0x08000000
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4938_PCFG_SEL2        0x00000200
+#define TX4938_PCFG_SEL1        0x00000100
+#define TX4938_PCFG_DMASEL_ALL  0x0000000f
+#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
+#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
+
+/* CLKCTR : Clock Control */
+#define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
+#define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
+#define TX4938_CLKCTR_ETH1CKD   0x80000000
+#define TX4938_CLKCTR_ETH0CKD   0x40000000
+#define TX4938_CLKCTR_SPICKD    0x20000000
+#define TX4938_CLKCTR_SRAMCKD   0x10000000
+#define TX4938_CLKCTR_PCIC1CKD  0x08000000
+#define TX4938_CLKCTR_DMA1CKD   0x04000000
+#define TX4938_CLKCTR_ACLCKD    0x02000000
+#define TX4938_CLKCTR_PIOCKD    0x01000000
+#define TX4938_CLKCTR_DMACKD    0x00800000
+#define TX4938_CLKCTR_PCICKD    0x00400000
+#define TX4938_CLKCTR_TM0CKD    0x00100000
+#define TX4938_CLKCTR_TM1CKD    0x00080000
+#define TX4938_CLKCTR_TM2CKD    0x00040000
+#define TX4938_CLKCTR_SIO0CKD   0x00020000
+#define TX4938_CLKCTR_SIO1CKD   0x00010000
+#define TX4938_CLKCTR_ETH1RST   0x00008000
+#define TX4938_CLKCTR_ETH0RST   0x00004000
+#define TX4938_CLKCTR_SPIRST    0x00002000
+#define TX4938_CLKCTR_SRAMRST   0x00001000
+#define TX4938_CLKCTR_PCIC1RST  0x00000800
+#define TX4938_CLKCTR_DMA1RST   0x00000400
+#define TX4938_CLKCTR_ACLRST    0x00000200
+#define TX4938_CLKCTR_PIORST    0x00000100
+#define TX4938_CLKCTR_DMARST    0x00000080
+#define TX4938_CLKCTR_PCIRST    0x00000040
+#define TX4938_CLKCTR_TM0RST    0x00000010
+#define TX4938_CLKCTR_TM1RST    0x00000008
+#define TX4938_CLKCTR_TM2RST    0x00000004
+#define TX4938_CLKCTR_SIO0RST   0x00000002
+#define TX4938_CLKCTR_SIO1RST   0x00000001
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4938_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4938_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4938_PCIC_G2PSTATUS_RTOE      0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX4938_PCIC_PCISTATUS_ALL       0x0000f900
+
+/* bits for PBACFG */
+#define TX4938_PCIC_PBACFG_FIXPA        0x00000008
+#define TX4938_PCIC_PBACFG_RPBA 0x00000004
+#define TX4938_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4938_PCIC_PBACFG_BMCEN        0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4938_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
+#define TX4938_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
+
+/* bits for G2PIOGBASE */
+#define TX4938_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
+#define TX4938_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4938_PCIC_PCICSTATUS_ALL      0x000007b8
+#define TX4938_PCIC_PCICSTATUS_PME      0x00000400
+#define TX4938_PCIC_PCICSTATUS_TLB      0x00000200
+#define TX4938_PCIC_PCICSTATUS_NIB      0x00000100
+#define TX4938_PCIC_PCICSTATUS_ZIB      0x00000080
+#define TX4938_PCIC_PCICSTATUS_PERR     0x00000020
+#define TX4938_PCIC_PCICSTATUS_SERR     0x00000010
+#define TX4938_PCIC_PCICSTATUS_GBE      0x00000008
+#define TX4938_PCIC_PCICSTATUS_IWB      0x00000002
+#define TX4938_PCIC_PCICSTATUS_E2PDONE  0x00000001
+
+/* bits for PCICCFG */
+#define TX4938_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
+#define TX4938_PCIC_PCICCFG_HRST        0x00000800
+#define TX4938_PCIC_PCICCFG_SRST        0x00000400
+#define TX4938_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4938_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
+#define TX4938_PCIC_PCICCFG_G2PM0EN     0x00000100
+#define TX4938_PCIC_PCICCFG_G2PM1EN     0x00000080
+#define TX4938_PCIC_PCICCFG_G2PM2EN     0x00000040
+#define TX4938_PCIC_PCICCFG_G2PIOEN     0x00000020
+#define TX4938_PCIC_PCICCFG_TCAR        0x00000010
+#define TX4938_PCIC_PCICCFG_ICAEN       0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4938_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
+#define TX4938_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
+#define TX4938_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
+
+/* bits for P2GIOGBASE */
+#define TX4938_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
+#define TX4938_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
+#define TX4938_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
+
+#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4938_PCIC_MAX_DEVNU   TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/* bits for PDMCFG */
+#define TX4938_PCIC_PDMCFG_RSTFIFO      0x00200000
+#define TX4938_PCIC_PDMCFG_EXFER        0x00100000
+#define TX4938_PCIC_PDMCFG_REQDLY_MASK  0x00003800
+#define TX4938_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_16    (1 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_32    (2 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_64    (3 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_128   (4 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_256   (5 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_512   (6 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
+#define TX4938_PCIC_PDMCFG_ERRIE        0x00000400
+#define TX4938_PCIC_PDMCFG_NCCMPIE      0x00000200
+#define TX4938_PCIC_PDMCFG_NTCMPIE      0x00000100
+#define TX4938_PCIC_PDMCFG_CHNEN        0x00000080
+#define TX4938_PCIC_PDMCFG_XFRACT       0x00000040
+#define TX4938_PCIC_PDMCFG_BSWAP        0x00000020
+#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
+#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
+#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
+#define TX4938_PCIC_PDMCFG_XFRDIRC      0x00000002
+#define TX4938_PCIC_PDMCFG_CHRST        0x00000001
+
+/* bits for PDMSTS */
+#define TX4938_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
+#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4938_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
+#define TX4938_PCIC_PDMSTS_FIFORP_MASK  0x00030000
+#define TX4938_PCIC_PDMSTS_ERRINT       0x00000800
+#define TX4938_PCIC_PDMSTS_DONEINT      0x00000400
+#define TX4938_PCIC_PDMSTS_CHNEN        0x00000200
+#define TX4938_PCIC_PDMSTS_XFRACT       0x00000100
+#define TX4938_PCIC_PDMSTS_ACCMP        0x00000080
+#define TX4938_PCIC_PDMSTS_NCCMP        0x00000040
+#define TX4938_PCIC_PDMSTS_NTCMP        0x00000020
+#define TX4938_PCIC_PDMSTS_CFGERR       0x00000008
+#define TX4938_PCIC_PDMSTS_PCIERR       0x00000004
+#define TX4938_PCIC_PDMSTS_CHNERR       0x00000002
+#define TX4938_PCIC_PDMSTS_DATAERR      0x00000001
+#define TX4938_PCIC_PDMSTS_ALL_CMP      0x000000e0
+#define TX4938_PCIC_PDMSTS_ALL_ERR      0x0000000f
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX4938_DMA_MCR_RSFIF    0x00000080
+#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX4938_DMA_MCR_RPRT     0x00000002
+#define TX4938_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX4938_DMA_CCR_IMMCHN   0x20000000
+#define TX4938_DMA_CCR_USEXFSZ  0x10000000
+#define TX4938_DMA_CCR_LE       0x08000000
+#define TX4938_DMA_CCR_DBINH    0x04000000
+#define TX4938_DMA_CCR_SBINH    0x02000000
+#define TX4938_DMA_CCR_CHRST    0x01000000
+#define TX4938_DMA_CCR_RVBYTE   0x00800000
+#define TX4938_DMA_CCR_ACKPOL   0x00400000
+#define TX4938_DMA_CCR_REQPL    0x00200000
+#define TX4938_DMA_CCR_EGREQ    0x00100000
+#define TX4938_DMA_CCR_CHDN     0x00080000
+#define TX4938_DMA_CCR_DNCTL    0x00060000
+#define TX4938_DMA_CCR_EXTRQ    0x00010000
+#define TX4938_DMA_CCR_INTRQD   0x0000e000
+#define TX4938_DMA_CCR_INTENE   0x00001000
+#define TX4938_DMA_CCR_INTENC   0x00000800
+#define TX4938_DMA_CCR_INTENT   0x00000400
+#define TX4938_DMA_CCR_CHNEN    0x00000200
+#define TX4938_DMA_CCR_XFACT    0x00000100
+#define TX4938_DMA_CCR_SMPCHN   0x00000020
+#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
+#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
+#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
+#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_MEMIO    0x00000002
+#define TX4938_DMA_CCR_SNGAD    0x00000001
+
+/* bits for CSRn */
+#define TX4938_DMA_CSR_CHNEN    0x00000400
+#define TX4938_DMA_CSR_STLXFER  0x00000200
+#define TX4938_DMA_CSR_CHNACT   0x00000100
+#define TX4938_DMA_CSR_ABCHC    0x00000080
+#define TX4938_DMA_CSR_NCHNC    0x00000040
+#define TX4938_DMA_CSR_NTRNFC   0x00000020
+#define TX4938_DMA_CSR_EXTDN    0x00000010
+#define TX4938_DMA_CSR_CFERR    0x00000008
+#define TX4938_DMA_CSR_CHERR    0x00000004
+#define TX4938_DMA_CSR_DESERR   0x00000002
+#define TX4938_DMA_CSR_SORERR   0x00000001
+
+/* TX4938 Interrupt Controller (32-bit registers) */
+#define TX4938_IRC_BASE                 0xf510
+#define TX4938_IRC_IRFLAG0              0xf510
+#define TX4938_IRC_IRFLAG1              0xf514
+#define TX4938_IRC_IRPOL                0xf518
+#define TX4938_IRC_IRRCNT               0xf51c
+#define TX4938_IRC_IRMASKINT            0xf520
+#define TX4938_IRC_IRMASKEXT            0xf524
+#define TX4938_IRC_IRDEN                0xf600
+#define TX4938_IRC_IRDM0                0xf604
+#define TX4938_IRC_IRDM1                0xf608
+#define TX4938_IRC_IRLVL0               0xf610
+#define TX4938_IRC_IRLVL1               0xf614
+#define TX4938_IRC_IRLVL2               0xf618
+#define TX4938_IRC_IRLVL3               0xf61c
+#define TX4938_IRC_IRLVL4               0xf620
+#define TX4938_IRC_IRLVL5               0xf624
+#define TX4938_IRC_IRLVL6               0xf628
+#define TX4938_IRC_IRLVL7               0xf62c
+#define TX4938_IRC_IRMSK                0xf640
+#define TX4938_IRC_IREDC                0xf660
+#define TX4938_IRC_IRPND                0xf680
+#define TX4938_IRC_IRCS                 0xf6a0
+#define TX4938_IRC_LIMIT                0xf6ff
+
+
+#ifndef __ASSEMBLY__
+
+#define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
+#define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
+#define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
+#define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
+#define tx4938_ircptr           ((struct tx4938_irc_reg *)TX4938_IRC_REG)
+#define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
+#define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
+#define tx4938_tmrptr(ch)       ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
+#define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
+#define tx4938_pioptr           ((struct tx4938_pio_reg *)TX4938_PIO_REG)
+#define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
+#define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
+#define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
+
+
+#define TX4938_REV_MAJ_MIN()    ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
+#define TX4938_REV_PCODE()      ((unsigned long)tx4938_ccfgptr->crir >> 16)
+
+#define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
+#define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
+
+#define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
+#define TX4938_EBUSC_SIZE(ch)   \
+        (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
+
+
+#endif /* !__ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
new file mode 100644
index 000000000000..cf89b205f103
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -0,0 +1,54 @@
+/*
+ * linux/include/asm-mips/tx4938/tx4938_bitmask.h
+ * Generic bitmask definitions
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+
+#ifndef TX4938_TX4938_MIPS_H
+#define TX4938_TX4938_MIPS_H
+#ifndef __ASSEMBLY__
+
+#define reg_rd08(r)    ((u8 )(*((vu8 *)(r))))
+#define reg_rd16(r)    ((u16)(*((vu16*)(r))))
+#define reg_rd32(r)    ((u32)(*((vu32*)(r))))
+#define reg_rd64(r)    ((u64)(*((vu64*)(r))))
+
+#define reg_wr08(r,v)  ((*((vu8 *)(r)))=((u8 )(v)))
+#define reg_wr16(r,v)  ((*((vu16*)(r)))=((u16)(v)))
+#define reg_wr32(r,v)  ((*((vu32*)(r)))=((u32)(v)))
+#define reg_wr64(r,v)  ((*((vu64*)(r)))=((u64)(v)))
+
+typedef volatile __signed char vs8;
+typedef volatile unsigned char vu8;
+
+typedef volatile __signed short vs16;
+typedef volatile unsigned short vu16;
+
+typedef volatile __signed int vs32;
+typedef volatile unsigned int vu32;
+
+typedef s8 s08;
+typedef vs8 vs08;
+
+typedef u8 u08;
+typedef vu8 vu08;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef volatile __signed__ long vs64;
+typedef volatile unsigned long vu64;
+
+#else
+
+typedef volatile __signed__ long long vs64;
+typedef volatile unsigned long long vu64;
+
+#endif
+#endif
+#endif
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index 5c2c98329012..41bb96bb2120 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -196,63 +196,55 @@
         __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
 
 struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
+#define __m(x) (*(struct __large_struct __user *)(x))
 
 /*
  * Yuck.  We need two variants, one for 64bit operation and one
  * for 32 bit mode and old iron.
  */
 #ifdef __mips64
-#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err)
+#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr)
 #else
-#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err)
+#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr)
 #endif
 
 #define __get_user_nocheck(x,ptr,size)                                  \
 ({                                                                      \
-        __typeof(*(ptr)) __gu_val = 0;                                  \
-        long __gu_addr;                                                 \
+        __typeof(*(ptr)) __gu_val =  (__typeof(*(ptr))) 0;              \
         long __gu_err = 0;                                              \
                                                                         \
-        might_sleep();                                                  \
-        __gu_addr = (long) (ptr);                                       \
         switch (size) {                                                 \
-        case 1: __get_user_asm("lb", __gu_err); break;                  \
-        case 2: __get_user_asm("lh", __gu_err); break;                  \
-        case 4: __get_user_asm("lw", __gu_err); break;                  \
-        case 8: __GET_USER_DW(__gu_err); break;                         \
+        case 1: __get_user_asm("lb", ptr); break;                       \
+        case 2: __get_user_asm("lh", ptr); break;                       \
+        case 4: __get_user_asm("lw", ptr); break;                       \
+        case 8: __GET_USER_DW(ptr); break;                              \
         default: __get_user_unknown(); break;                           \
         }                                                               \
-        x = (__typeof__(*(ptr))) __gu_val;                              \
+        (x) = (__typeof__(*(ptr))) __gu_val;                            \
         __gu_err;                                                       \
 })
 
 #define __get_user_check(x,ptr,size)                                    \
 ({                                                                      \
+        const __typeof__(*(ptr)) __user * __gu_addr = (ptr);            \
         __typeof__(*(ptr)) __gu_val = 0;                                \
-        long __gu_addr;                                                 \
-        long __gu_err;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __gu_addr = (long) (ptr);                                       \
-        __gu_err = access_ok(VERIFY_READ, (void *) __gu_addr, size)     \
-                                ? 0 : -EFAULT;                          \
+        long __gu_err = -EFAULT;                                        \
                                                                         \
-        if (likely(!__gu_err)) {                                        \
+        if (likely(access_ok(VERIFY_READ,  __gu_addr, size))) {         \
                 switch (size) {                                         \
-                case 1: __get_user_asm("lb", __gu_err); break;          \
-                case 2: __get_user_asm("lh", __gu_err); break;          \
-                case 4: __get_user_asm("lw", __gu_err); break;          \
-                case 8: __GET_USER_DW(__gu_err); break;                 \
+                case 1: __get_user_asm("lb", __gu_addr); break;         \
+                case 2: __get_user_asm("lh", __gu_addr); break;         \
+                case 4: __get_user_asm("lw", __gu_addr); break;         \
+                case 8: __GET_USER_DW(__gu_addr); break;                \
                 default: __get_user_unknown(); break;                   \
                 }                                                       \
         }                                                               \
-        x = (__typeof__(*(ptr))) __gu_val;                              \
+        (x) = (__typeof__(*(ptr))) __gu_val;                            \
         __gu_err;                                                       \
 })
 
-#define __get_user_asm(insn,__gu_err)                                   \
-({                                                                      \
+#define __get_user_asm(insn, addr)                                      \
+{                                                                       \
         __asm__ __volatile__(                                           \
         "1:     " insn "        %1, %3                          \n"     \
         "2:                                                     \n"     \
@@ -264,20 +256,20 @@ struct __large_struct { unsigned long buf[100]; };
         "       "__UA_ADDR "\t1b, 3b                            \n"     \
         "       .previous                                       \n"     \
         : "=r" (__gu_err), "=r" (__gu_val)                              \
-        : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT));         \
-})
+        : "0" (0), "o" (__m(addr)), "i" (-EFAULT));                     \
+}
 
 /*
  * Get a long long 64 using 32 bit registers.
  */
-#define __get_user_asm_ll32(__gu_err)                                   \
-({                                                                      \
+#define __get_user_asm_ll32(addr)                                       \
+{                                                                       \
         __asm__ __volatile__(                                           \
-        "1:     lw      %1, %3                                  \n"     \
-        "2:     lw      %D1, %4                                 \n"     \
+        "1:     lw      %1, (%3)                                \n"     \
+        "2:     lw      %D1, 4(%3)                              \n"     \
         "       move    %0, $0                                  \n"     \
         "3:     .section        .fixup,\"ax\"                   \n"     \
-        "4:     li      %0, %5                                  \n"     \
+        "4:     li      %0, %4                                  \n"     \
         "       move    %1, $0                                  \n"     \
         "       move    %D1, $0                                 \n"     \
         "       j       3b                                      \n"     \
@@ -287,9 +279,8 @@ struct __large_struct { unsigned long buf[100]; };
         "       " __UA_ADDR "   2b, 4b                          \n"     \
         "       .previous                                       \n"     \
         : "=r" (__gu_err), "=&r" (__gu_val)                             \
-        : "0" (__gu_err), "o" (__m(__gu_addr)),                         \
-          "o" (__m(__gu_addr + 4)), "i" (-EFAULT));                     \
-})
+        : "0" (0), "r" (addr), "i" (-EFAULT));                          \
+}
 
 extern void __get_user_unknown(void);
 
@@ -298,25 +289,22 @@ extern void __get_user_unknown(void);
  * for 32 bit mode and old iron.
  */
 #ifdef __mips64
-#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val)
+#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
 #else
-#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val)
+#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
 #endif
 
 #define __put_user_nocheck(x,ptr,size)                                  \
 ({                                                                      \
         __typeof__(*(ptr)) __pu_val;                                    \
-        long __pu_addr;                                                 \
         long __pu_err = 0;                                              \
                                                                         \
-        might_sleep();                                                  \
         __pu_val = (x);                                                 \
-        __pu_addr = (long) (ptr);                                       \
         switch (size) {                                                 \
-        case 1: __put_user_asm("sb", __pu_val); break;                  \
-        case 2: __put_user_asm("sh", __pu_val); break;                  \
-        case 4: __put_user_asm("sw", __pu_val); break;                  \
-        case 8: __PUT_USER_DW(__pu_val); break;                         \
+        case 1: __put_user_asm("sb", ptr); break;                       \
+        case 2: __put_user_asm("sh", ptr); break;                       \
+        case 4: __put_user_asm("sw", ptr); break;                       \
+        case 8: __PUT_USER_DW(ptr); break;                              \
         default: __put_user_unknown(); break;                           \
         }                                                               \
         __pu_err;                                                       \
@@ -324,30 +312,24 @@ extern void __get_user_unknown(void);
 
 #define __put_user_check(x,ptr,size)                                    \
 ({                                                                      \
-        __typeof__(*(ptr)) __pu_val;                                    \
-        long __pu_addr;                                                 \
-        long __pu_err;                                                  \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
+        __typeof__(*(ptr)) __pu_val = (x);                              \
+        long __pu_err = -EFAULT;                                        \
                                                                         \
-        might_sleep();                                                  \
-        __pu_val = (x);                                                 \
-        __pu_addr = (long) (ptr);                                       \
-        __pu_err = access_ok(VERIFY_WRITE, (void *) __pu_addr, size)    \
-                                ? 0 : -EFAULT;                          \
-                                                                        \
-        if (likely(!__pu_err)) {                                        \
+        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
                 switch (size) {                                         \
-                case 1: __put_user_asm("sb", __pu_val); break;          \
-                case 2: __put_user_asm("sh", __pu_val); break;          \
-                case 4: __put_user_asm("sw", __pu_val); break;          \
-                case 8: __PUT_USER_DW(__pu_val); break;                 \
+                case 1: __put_user_asm("sb", __pu_addr); break;         \
+                case 2: __put_user_asm("sh", __pu_addr); break;         \
+                case 4: __put_user_asm("sw", __pu_addr); break;         \
+                case 8: __PUT_USER_DW(__pu_addr); break;                \
                 default: __put_user_unknown(); break;                   \
                 }                                                       \
         }                                                               \
         __pu_err;                                                       \
 })
 
-#define __put_user_asm(insn, __pu_val)                                  \
-({                                                                      \
+#define __put_user_asm(insn, ptr)                                       \
+{                                                                       \
         __asm__ __volatile__(                                           \
         "1:     " insn "        %z2, %3         # __put_user_asm\n"     \
         "2:                                                     \n"     \
@@ -359,18 +341,18 @@ extern void __get_user_unknown(void);
         "       " __UA_ADDR "   1b, 3b                          \n"     \
         "       .previous                                       \n"     \
         : "=r" (__pu_err)                                               \
-        : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)),        \
+        : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)),                     \
           "i" (-EFAULT));                                               \
-})
+}
 
-#define __put_user_asm_ll32(__pu_val)                                   \
-({                                                                      \
+#define __put_user_asm_ll32(ptr)                                        \
+{                                                                       \
         __asm__ __volatile__(                                           \
-        "1:     sw      %2, %3          # __put_user_asm_ll32   \n"     \
-        "2:     sw      %D2, %4                                 \n"     \
+        "1:     sw      %2, (%3)        # __put_user_asm_ll32   \n"     \
+        "2:     sw      %D2, 4(%3)                              \n"     \
         "3:                                                     \n"     \
         "       .section        .fixup,\"ax\"                   \n"     \
-        "4:     li      %0, %5                                  \n"     \
+        "4:     li      %0, %4                                  \n"     \
         "       j       3b                                      \n"     \
         "       .previous                                       \n"     \
         "       .section        __ex_table,\"a\"                \n"     \
@@ -378,9 +360,9 @@ extern void __get_user_unknown(void);
         "       " __UA_ADDR "   2b, 4b                          \n"     \
         "       .previous"                                              \
         : "=r" (__pu_err)                                               \
-        : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)),         \
-          "o" (__m(__pu_addr + 4)), "i" (-EFAULT));                     \
-})
+        : "0" (0), "r" (__pu_val), "r" (ptr),                           \
+          "i" (-EFAULT));                                               \
+}
 
 extern void __put_user_unknown(void);
 
@@ -403,7 +385,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 #define __invoke_copy_to_user(to,from,n)                                \
 ({                                                                      \
-        register void *__cu_to_r __asm__ ("$4");                        \
+        register void __user *__cu_to_r __asm__ ("$4");                 \
         register const void *__cu_from_r __asm__ ("$5");                \
         register long __cu_len_r __asm__ ("$6");                        \
                                                                         \
@@ -435,7 +417,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
  */
 #define __copy_to_user(to,from,n)                                       \
 ({                                                                      \
-        void *__cu_to;                                                  \
+        void __user *__cu_to;                                           \
         const void *__cu_from;                                          \
         long __cu_len;                                                  \
                                                                         \
@@ -465,7 +447,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
  */
 #define copy_to_user(to,from,n)                                         \
 ({                                                                      \
-        void *__cu_to;                                                  \
+        void __user *__cu_to;                                           \
         const void *__cu_from;                                          \
         long __cu_len;                                                  \
                                                                         \
@@ -482,7 +464,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define __invoke_copy_from_user(to,from,n)                              \
 ({                                                                      \
         register void *__cu_to_r __asm__ ("$4");                        \
-        register const void *__cu_from_r __asm__ ("$5");                \
+        register const void __user *__cu_from_r __asm__ ("$5");         \
         register long __cu_len_r __asm__ ("$6");                        \
                                                                         \
         __cu_to_r = (to);                                               \
@@ -521,7 +503,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define __copy_from_user(to,from,n)                                     \
 ({                                                                      \
         void *__cu_to;                                                  \
-        const void *__cu_from;                                          \
+        const void __user *__cu_from;                                   \
         long __cu_len;                                                  \
                                                                         \
         might_sleep();                                                  \
@@ -552,7 +534,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define copy_from_user(to,from,n)                                       \
 ({                                                                      \
         void *__cu_to;                                                  \
-        const void *__cu_from;                                          \
+        const void __user *__cu_from;                                   \
         long __cu_len;                                                  \
                                                                         \
         might_sleep();                                                  \
@@ -569,8 +551,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 #define copy_in_user(to,from,n)                                         \
 ({                                                                      \
-        void *__cu_to;                                                  \
-        const void *__cu_from;                                          \
+        void __user *__cu_to;                                           \
+        const void __user *__cu_from;                                   \
         long __cu_len;                                                  \
                                                                         \
         might_sleep();                                                  \
@@ -596,7 +578,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
  * On success, this will be zero.
  */
 static inline __kernel_size_t
-__clear_user(void *addr, __kernel_size_t size)
+__clear_user(void __user *addr, __kernel_size_t size)
 {
         __kernel_size_t res;
 
@@ -616,7 +598,7 @@ __clear_user(void *addr, __kernel_size_t size)
 
 #define clear_user(addr,n)                                              \
 ({                                                                      \
-        void * __cl_addr = (addr);                                      \
+        void __user * __cl_addr = (addr);                               \
         unsigned long __cl_size = (n);                                  \
         if (__cl_size && access_ok(VERIFY_WRITE,                        \
                 ((unsigned long)(__cl_addr)), __cl_size))               \
@@ -645,7 +627,7 @@ __clear_user(void *addr, __kernel_size_t size)
  * and returns @count.
  */
 static inline long
-__strncpy_from_user(char *__to, const char *__from, long __len)
+__strncpy_from_user(char *__to, const char __user *__from, long __len)
 {
         long res;
 
@@ -682,7 +664,7 @@ __strncpy_from_user(char *__to, const char *__from, long __len)
  * and returns @count.
  */
 static inline long
-strncpy_from_user(char *__to, const char *__from, long __len)
+strncpy_from_user(char *__to, const char __user *__from, long __len)
 {
         long res;
 
@@ -701,7 +683,7 @@ strncpy_from_user(char *__to, const char *__from, long __len)
 }
 
 /* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-static inline long __strlen_user(const char *s)
+static inline long __strlen_user(const char __user *s)
 {
         long res;
 
@@ -731,7 +713,7 @@ static inline long __strlen_user(const char *s)
  * If there is a limit on the length of a valid string, you may wish to
  * consider using strnlen_user() instead.
  */
-static inline long strlen_user(const char *s)
+static inline long strlen_user(const char __user *s)
 {
         long res;
 
@@ -748,7 +730,7 @@ static inline long strlen_user(const char *s)
 }
 
 /* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-static inline long __strnlen_user(const char *s, long n)
+static inline long __strnlen_user(const char __user *s, long n)
 {
         long res;
 
@@ -779,7 +761,7 @@ static inline long __strnlen_user(const char *s, long n)
  * If there is a limit on the length of a valid string, you may wish to
  * consider using strnlen_user() instead.
  */
-static inline long strnlen_user(const char *s, long n)
+static inline long strnlen_user(const char __user *s, long n)
 {
         long res;
 
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index ad4d48056307..89ea8b60e945 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -303,16 +303,21 @@
 #define __NR_add_key                    (__NR_Linux + 280)
 #define __NR_request_key                (__NR_Linux + 281)
 #define __NR_keyctl                     (__NR_Linux + 282)
+#define __NR_set_thread_area            (__NR_Linux + 283)
+#define __NR_inotify_init               (__NR_Linux + 284)
+#define __NR_inotify_add_watch          (__NR_Linux + 285)
+#define __NR_inotify_rm_watch           (__NR_Linux + 286)
+
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             282
+#define __NR_Linux_syscalls             286
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         282
+#define __NR_O32_Linux_syscalls         283
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -562,16 +567,20 @@
 #define __NR_add_key                    (__NR_Linux + 239)
 #define __NR_request_key                (__NR_Linux + 240)
 #define __NR_keyctl                     (__NR_Linux + 241)
+#define __NR_set_thread_area            (__NR_Linux + 242)
+#define __NR_inotify_init               (__NR_Linux + 243)
+#define __NR_inotify_add_watch          (__NR_Linux + 244)
+#define __NR_inotify_rm_watch           (__NR_Linux + 245)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             241
+#define __NR_Linux_syscalls             245
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          241
+#define __NR_64_Linux_syscalls          242
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -825,16 +834,20 @@
 #define __NR_add_key                    (__NR_Linux + 243)
 #define __NR_request_key                (__NR_Linux + 244)
 #define __NR_keyctl                     (__NR_Linux + 245)
+#define __NR_set_thread_area            (__NR_Linux + 246)
+#define __NR_inotify_init               (__NR_Linux + 247)
+#define __NR_inotify_add_watch          (__NR_Linux + 248)
+#define __NR_inotify_rm_watch           (__NR_Linux + 249)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             245
+#define __NR_Linux_syscalls             249
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         245
+#define __NR_N32_Linux_syscalls         246
 
 #ifndef __ASSEMBLY__
 
@@ -1164,7 +1177,6 @@ asmlinkage long sys_mmap2(
                         unsigned long fd, unsigned long pgoff);
 asmlinkage int sys_execve(nabi_no_regargs struct pt_regs regs);
 asmlinkage int sys_pipe(nabi_no_regargs struct pt_regs regs);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
index 6b35cf054c79..ca5cec97e167 100644
--- a/include/asm-mips/vga.h
+++ b/include/asm-mips/vga.h
@@ -6,6 +6,8 @@
 #ifndef _ASM_VGA_H
 #define _ASM_VGA_H
 
+#include <asm/byteorder.h>
+
 /*
  *      On the PC, we can just recalculate addresses and then
  *      access the videoram directly without any black magic.
@@ -16,4 +18,27 @@
 #define vga_readb(x)    (*(x))
 #define vga_writeb(x,y) (*(y) = (x))
 
+#define VT_BUF_HAVE_RW
+/*
+ *  These are only needed for supporting VGA or MDA text mode, which use little
+ *  endian byte ordering.
+ *  In other cases, we can optimize by using native byte ordering and
+ *  <linux/vt_buffer.h> has already done the right job for us.
+ */
+
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+        *addr = cpu_to_le16(val);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+        return le16_to_cpu(*addr);
+}
+
+#define scr_memcpyw(d, s, c) memcpy(d, s, c)
+#define scr_memmovew(d, s, c) memmove(d, s, c)
+#define VT_BUF_HAVE_MEMCPYW
+#define VT_BUF_HAVE_MEMMOVEW
+
 #endif /* _ASM_VGA_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 04ee53b34c2e..ad374bd3f130 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -177,6 +177,17 @@
 #endif
 
 /*
+ * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
+ * where invalid instructions in the same I-cache line worth of instructions
+ * being fetched may case spurious exceptions.
+ */
+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
+    defined(CONFIG_PMC_YOSEMITE)
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#endif
+
+
+/*
  * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
  * may cause ll / sc and lld / scd sequences to execute non-atomically.
  */
@@ -187,6 +198,9 @@
 /*
  * Workarounds default to off
  */
+#ifndef ICACHE_REFILLS_WORKAROUND_WAR
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#endif
 #ifndef R4600_V1_INDEX_ICACHEOP_WAR
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #endif
diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
index 30b023411fef..3ce3440d1b0c 100644
--- a/include/asm-parisc/assembly.h
+++ b/include/asm-parisc/assembly.h
@@ -21,7 +21,9 @@
 #ifndef _PARISC_ASSEMBLY_H
 #define _PARISC_ASSEMBLY_H
 
-#ifdef __LP64__
+#define CALLEE_FLOAT_FRAME_SIZE 80
+
+#ifdef CONFIG_64BIT
 #define LDREG   ldd
 #define STREG   std
 #define LDREGX  ldd,s
@@ -30,8 +32,8 @@
 #define SHRREG  shrd
 #define RP_OFFSET       16
 #define FRAME_SIZE      128
-#define CALLEE_SAVE_FRAME_SIZE  144
-#else
+#define CALLEE_REG_FRAME_SIZE   144
+#else   /* CONFIG_64BIT */
 #define LDREG   ldw
 #define STREG   stw
 #define LDREGX  ldwx,s
@@ -40,9 +42,11 @@
 #define SHRREG  shr
 #define RP_OFFSET       20
 #define FRAME_SIZE      64
-#define CALLEE_SAVE_FRAME_SIZE  128
+#define CALLEE_REG_FRAME_SIZE   128
 #endif
 
+#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
+
 #ifdef CONFIG_PA20
 #define BL              b,l
 # ifdef CONFIG_64BIT
@@ -300,9 +304,35 @@
         fldd,mb -8(\regs),       %fr0
         .endm
 
+        .macro  callee_save_float
+        fstd,ma  %fr12, 8(%r30)
+        fstd,ma  %fr13, 8(%r30)
+        fstd,ma  %fr14, 8(%r30)
+        fstd,ma  %fr15, 8(%r30)
+        fstd,ma  %fr16, 8(%r30)
+        fstd,ma  %fr17, 8(%r30)
+        fstd,ma  %fr18, 8(%r30)
+        fstd,ma  %fr19, 8(%r30)
+        fstd,ma  %fr20, 8(%r30)
+        fstd,ma  %fr21, 8(%r30)
+        .endm
+
+        .macro  callee_rest_float
+        fldd,mb -8(%r30),   %fr21
+        fldd,mb -8(%r30),   %fr20
+        fldd,mb -8(%r30),   %fr19
+        fldd,mb -8(%r30),   %fr18
+        fldd,mb -8(%r30),   %fr17
+        fldd,mb -8(%r30),   %fr16
+        fldd,mb -8(%r30),   %fr15
+        fldd,mb -8(%r30),   %fr14
+        fldd,mb -8(%r30),   %fr13
+        fldd,mb -8(%r30),   %fr12
+        .endm
+
 #ifdef __LP64__
         .macro  callee_save
-        std,ma    %r3,  CALLEE_SAVE_FRAME_SIZE(%r30)
+        std,ma    %r3,   CALLEE_REG_FRAME_SIZE(%r30)
         mfctl     %cr27, %r3
         std       %r4,  -136(%r30)
         std       %r5,  -128(%r30)
@@ -340,13 +370,13 @@
         ldd     -128(%r30),    %r5
         ldd     -136(%r30),    %r4
         mtctl   %r3, %cr27
-        ldd,mb  -CALLEE_SAVE_FRAME_SIZE(%r30),    %r3
+        ldd,mb  -CALLEE_REG_FRAME_SIZE(%r30),    %r3
         .endm
 
 #else /* ! __LP64__ */
 
         .macro  callee_save
-        stw,ma   %r3,   CALLEE_SAVE_FRAME_SIZE(%r30)
+        stw,ma   %r3,   CALLEE_REG_FRAME_SIZE(%r30)
         mfctl    %cr27, %r3
         stw      %r4,   -124(%r30)
         stw      %r5,   -120(%r30)
@@ -384,7 +414,7 @@
         ldw     -120(%r30),   %r5
         ldw     -124(%r30),   %r4
         mtctl   %r3, %cr27
-        ldw,mb  -CALLEE_SAVE_FRAME_SIZE(%r30),   %r3
+        ldw,mb  -CALLEE_REG_FRAME_SIZE(%r30),   %r3
         .endm
 #endif /* ! __LP64__ */
 
@@ -450,5 +480,30 @@
         REST_CR (%cr22, PT_PSW  (\regs))
         .endm
 
+
+        /* First step to create a "relied upon translation"
+         * See PA 2.0 Arch. page F-4 and F-5.
+         *
+         * The ssm was originally necessary due to a "PCxT bug".
+         * But someone decided it needed to be added to the architecture
+         * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
+         * It's been carried forward into PA 2.0 Arch as well. :^(
+         *
+         * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
+         * rsm/ssm prevents the ifetch unit from speculatively fetching
+         * instructions past this line in the code stream.
+         * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
+         */
+        .macro  pcxt_ssm_bug
+        rsm     PSW_SM_I,%r0
+        nop     /* 1 */
+        nop     /* 2 */
+        nop     /* 3 */
+        nop     /* 4 */
+        nop     /* 5 */
+        nop     /* 6 */
+        nop     /* 7 */
+        .endm
+
 #endif /* __ASSEMBLY__ */
 #endif
diff --git a/include/asm-parisc/bitops.h b/include/asm-parisc/bitops.h
index af7db694b22d..55b98c67fd82 100644
--- a/include/asm-parisc/bitops.h
+++ b/include/asm-parisc/bitops.h
@@ -2,7 +2,7 @@
 #define _PARISC_BITOPS_H
 
 #include <linux/compiler.h>
-#include <asm/spinlock.h>
+#include <asm/types.h>          /* for BITS_PER_LONG/SHIFT_PER_LONG */
 #include <asm/byteorder.h>
 #include <asm/atomic.h>
 
@@ -12,193 +12,157 @@
  * to include/asm-i386/bitops.h or kerneldoc
  */
 
-#ifdef __LP64__
-#   define SHIFT_PER_LONG 6
-#ifndef BITS_PER_LONG
-#   define BITS_PER_LONG 64
-#endif
-#else
-#   define SHIFT_PER_LONG 5
-#ifndef BITS_PER_LONG
-#   define BITS_PER_LONG 32
-#endif
-#endif
-
-#define CHOP_SHIFTCOUNT(x) ((x) & (BITS_PER_LONG - 1))
+#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
 
 
 #define smp_mb__before_clear_bit()      smp_mb()
 #define smp_mb__after_clear_bit()       smp_mb()
 
-static __inline__ void set_bit(int nr, volatile unsigned long * address)
+/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
+ * on use of volatile and __*_bit() (set/clear/change):
+ *      *_bit() want use of volatile.
+ *      __*_bit() are "relaxed" and don't use spinlock or volatile.
+ */
+
+static __inline__ void set_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
         *addr |= mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 }
 
-static __inline__ void __set_bit(int nr, volatile unsigned long * address)
+static __inline__ void __set_bit(unsigned long nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        *addr |= mask;
+        *m |= 1UL << CHOP_SHIFTCOUNT(nr);
 }
 
-static __inline__ void clear_bit(int nr, volatile unsigned long * address)
+static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        *addr &= ~mask;
+        *addr &= mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 }
 
-static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long * address)
+static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        *addr &= ~mask;
+        *m &= ~(1UL << CHOP_SHIFTCOUNT(nr));
 }
 
-static __inline__ void change_bit(int nr, volatile unsigned long * address)
+static __inline__ void change_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
         *addr ^= mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 }
 
-static __inline__ void __change_bit(int nr, volatile unsigned long * address)
+static __inline__ void __change_bit(unsigned long nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        *addr ^= mask;
+        *m ^= 1UL << CHOP_SHIFTCOUNT(nr);
 }
 
-static __inline__ int test_and_set_bit(int nr, volatile unsigned long * address)
+static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr |= mask;
+        oldbit = *addr;
+        *addr = oldbit | mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * address)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
+        unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr |= mask;
+        oldbit = *addr;
+        *addr = oldbit | mask;
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * address)
+static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr &= ~mask;
+        oldbit = *addr;
+        *addr = oldbit & ~mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long * address)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
+        unsigned long oldbit;
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr &= ~mask;
+        oldbit = *addr;
+        *addr = oldbit & ~mask;
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long * address)
+static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr ^= mask;
+        oldbit = *addr;
+        *addr = oldbit ^ mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int __test_and_change_bit(int nr, volatile unsigned long * address)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
+        unsigned long oldbit;
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr ^= mask;
+        oldbit = *addr;
+        *addr = oldbit ^ mask;
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int test_bit(int nr, const volatile unsigned long *address)
 {
-        unsigned long mask;
-        const unsigned long *addr = (const unsigned long *)address;
-        
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        const unsigned long *addr = (const unsigned long *)address + (nr >> SHIFT_PER_LONG);
         
         return !!(*addr & mask);
 }
@@ -229,7 +193,7 @@ static __inline__ unsigned long __ffs(unsigned long x)
         unsigned long ret;
 
         __asm__(
-#if BITS_PER_LONG > 32
+#ifdef __LP64__
                 " ldi       63,%1\n"
                 " extrd,u,*<>  %0,63,32,%%r0\n"
                 " extrd,u,*TR  %0,31,32,%0\n"   /* move top 32-bits down */
@@ -304,14 +268,7 @@ static __inline__ int fls(int x)
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
-#define hweight64(x)                                            \
-({                                                              \
-        unsigned long __x = (x);                                \
-        unsigned int __w;                                       \
-        __w = generic_hweight32((unsigned int) __x);            \
-        __w += generic_hweight32((unsigned int) (__x>>32));     \
-        __w;                                                    \
-})
+#define hweight64(x) generic_hweight64(x)
 #define hweight32(x) generic_hweight32(x)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
@@ -324,7 +281,13 @@ static __inline__ int fls(int x)
  */
 static inline int sched_find_first_bit(const unsigned long *b)
 {
-#ifndef __LP64__
+#ifdef __LP64__
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 64;
+        return __ffs(b[2]) + 128;
+#else
         if (unlikely(b[0]))
                 return __ffs(b[0]);
         if (unlikely(b[1]))
@@ -334,14 +297,6 @@ static inline int sched_find_first_bit(const unsigned long *b)
         if (b[3])
                 return __ffs(b[3]) + 96;
         return __ffs(b[4]) + 128;
-#else
-        if (unlikely(b[0]))
-                return __ffs(b[0]);
-        if (unlikely(((unsigned int)b[1])))
-                return __ffs(b[1]) + 64;
-        if (b[1] >> 32)
-                return __ffs(b[1] >> 32) + 96;
-        return __ffs(b[2]) + 128;
 #endif
 }
 
@@ -391,7 +346,7 @@ found_middle:
 
 static __inline__ unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset)
 {
-        const unsigned long *p = addr + (offset >> 6);
+        const unsigned long *p = addr + (offset >> SHIFT_PER_LONG);
         unsigned long result = offset & ~(BITS_PER_LONG-1);
         unsigned long tmp;
 
@@ -445,71 +400,90 @@ found_middle:
  * test_and_{set,clear}_bit guarantee atomicity without
  * disabling interrupts.
  */
-#ifdef __LP64__
-#define ext2_set_bit(nr, addr)          __test_and_set_bit((nr) ^ 0x38, (unsigned long *)addr)
-#define ext2_set_bit_atomic(l,nr,addr)  test_and_set_bit((nr) ^ 0x38, (unsigned long *)addr)
-#define ext2_clear_bit(nr, addr)        __test_and_clear_bit((nr) ^ 0x38, (unsigned long *)addr)
-#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit((nr) ^ 0x38, (unsigned long *)addr)
-#else
-#define ext2_set_bit(nr, addr)          __test_and_set_bit((nr) ^ 0x18, (unsigned long *)addr)
-#define ext2_set_bit_atomic(l,nr,addr)  test_and_set_bit((nr) ^ 0x18, (unsigned long *)addr)
-#define ext2_clear_bit(nr, addr)        __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)addr)
-#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)addr)
-#endif
 
-#endif  /* __KERNEL__ */
+/* '3' is bits per byte */
+#define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
 
-static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
-{
-        __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
+#define ext2_test_bit(nr, addr) \
+                        test_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
+#define ext2_set_bit(nr, addr)  \
+                __test_and_set_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
+#define ext2_clear_bit(nr, addr) \
+                __test_and_clear_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
 
-        return (ADDR[nr >> 3] >> (nr & 7)) & 1;
-}
+#define ext2_set_bit_atomic(l,nr,addr) \
+                test_and_set_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
+#define ext2_clear_bit_atomic(l,nr,addr) \
+                test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
+
+#endif  /* __KERNEL__ */
 
-/*
- * This implementation of ext2_find_{first,next}_zero_bit was stolen from
- * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
- */
 
 #define ext2_find_first_zero_bit(addr, size) \
-        ext2_find_next_zero_bit((addr), (size), 0)
+        ext2_find_next_zero_bit((addr), (size), 0)
 
-extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
-        unsigned long size, unsigned long offset)
+/* include/linux/byteorder does not support "unsigned long" type */
+static inline unsigned long ext2_swabp(unsigned long * x)
 {
-        unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
-        unsigned int result = offset & ~31UL;
-        unsigned int tmp;
+#ifdef __LP64__
+        return (unsigned long) __swab64p((u64 *) x);
+#else
+        return (unsigned long) __swab32p((u32 *) x);
+#endif
+}
+
+/* include/linux/byteorder doesn't support "unsigned long" type */
+static inline unsigned long ext2_swab(unsigned long y)
+{
+#ifdef __LP64__
+        return (unsigned long) __swab64((u64) y);
+#else
+        return (unsigned long) __swab32((u32) y);
+#endif
+}
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+{
+        unsigned long *p = (unsigned long *) addr + (offset >> SHIFT_PER_LONG);
+        unsigned long result = offset & ~(BITS_PER_LONG - 1);
+        unsigned long tmp;
 
         if (offset >= size)
                 return size;
         size -= result;
-        offset &= 31UL;
+        offset &= (BITS_PER_LONG - 1UL);
         if (offset) {
-                tmp = cpu_to_le32p(p++);
-                tmp |= ~0UL >> (32-offset);
-                if (size < 32)
+                tmp = ext2_swabp(p++);
+                tmp |= (~0UL >> (BITS_PER_LONG - offset));
+                if (size < BITS_PER_LONG)
                         goto found_first;
-                if (tmp != ~0U)
+                if (~tmp)
                         goto found_middle;
-                size -= 32;
-                result += 32;
+                size -= BITS_PER_LONG;
+                result += BITS_PER_LONG;
         }
-        while (size >= 32) {
-                if ((tmp = cpu_to_le32p(p++)) != ~0U)
-                        goto found_middle;
-                result += 32;
-                size -= 32;
+
+        while (size & ~(BITS_PER_LONG - 1)) {
+                if (~(tmp = *(p++)))
+                        goto found_middle_swap;
+                result += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
         }
         if (!size)
                 return result;
-        tmp = cpu_to_le32p(p);
+        tmp = ext2_swabp(p);
 found_first:
-        tmp |= ~0U << size;
+        tmp |= ~0UL << size;
+        if (tmp == ~0UL)        /* Are any bits zero? */
+                return result + size; /* Nope. Skip ffz */
 found_middle:
         return result + ffz(tmp);
+
+found_middle_swap:
+        return result + ffz(ext2_swab(tmp));
 }
 
+
 /* Bitmap functions for the minix filesystem.  */
 #define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
 #define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
diff --git a/include/asm-parisc/cacheflush.h b/include/asm-parisc/cacheflush.h
index aa592d8c0e39..1bc3c83ee74b 100644
--- a/include/asm-parisc/cacheflush.h
+++ b/include/asm-parisc/cacheflush.h
@@ -100,30 +100,34 @@ static inline void flush_cache_range(struct vm_area_struct *vma,
 
 /* Simple function to work out if we have an existing address translation
  * for a user space vma. */
-static inline pte_t *__translation_exists(struct mm_struct *mm,
-                                          unsigned long addr)
+static inline int translation_exists(struct vm_area_struct *vma,
+                                unsigned long addr, unsigned long pfn)
 {
-        pgd_t *pgd = pgd_offset(mm, addr);
+        pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
         pmd_t *pmd;
-        pte_t *pte;
+        pte_t pte;
 
         if(pgd_none(*pgd))
-                return NULL;
+                return 0;
 
         pmd = pmd_offset(pgd, addr);
         if(pmd_none(*pmd) || pmd_bad(*pmd))
-                return NULL;
+                return 0;
 
-        pte = pte_offset_map(pmd, addr);
+        /* We cannot take the pte lock here: flush_cache_page is usually
+         * called with pte lock already held.  Whereas flush_dcache_page
+         * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
+         * the vma itself is secure, but the pte might come or go racily.
+         */
+        pte = *pte_offset_map(pmd, addr);
+        /* But pte_unmap() does nothing on this architecture */
 
-        /* The PA flush mappings show up as pte_none, but they're
-         * valid none the less */
-        if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0))
-                return NULL;
-        return pte;
-}
-#define translation_exists(vma, addr)   __translation_exists((vma)->vm_mm, addr)
+        /* Filter out coincidental file entries and swap entries */
+        if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
+                return 0;
 
+        return pte_pfn(pte) == pfn;
+}
 
 /* Private function to flush a page from the cache of a non-current
  * process.  cr25 contains the Page Directory of the current user
@@ -175,9 +179,8 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
 {
         BUG_ON(!vma->vm_mm->context);
 
-        if(likely(translation_exists(vma, vmaddr)))
+        if (likely(translation_exists(vma, vmaddr, pfn)))
                 __flush_cache_page(vma, vmaddr);
 
 }
 #endif
-
diff --git a/include/asm-parisc/dma-mapping.h b/include/asm-parisc/dma-mapping.h
index 4db84f969e9e..74d4ac6f2151 100644
--- a/include/asm-parisc/dma-mapping.h
+++ b/include/asm-parisc/dma-mapping.h
@@ -9,8 +9,8 @@
 /* See Documentation/DMA-mapping.txt */
 struct hppa_dma_ops {
         int  (*dma_supported)(struct device *dev, u64 mask);
-        void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, int flag);
-        void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, int flag);
+        void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag);
+        void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag);
         void (*free_consistent)(struct device *dev, size_t size, void *vaddr, dma_addr_t iova);
         dma_addr_t (*map_single)(struct device *dev, void *addr, size_t size, enum dma_data_direction direction);
         void (*unmap_single)(struct device *dev, dma_addr_t iova, size_t size, enum dma_data_direction direction);
@@ -49,14 +49,14 @@ extern struct hppa_dma_ops *hppa_dma_ops;
 
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   int flag)
+                   gfp_t flag)
 {
         return hppa_dma_ops->alloc_consistent(dev, size, dma_handle, flag);
 }
 
 static inline void *
 dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                      int flag)
+                      gfp_t flag)
 {
         return hppa_dma_ops->alloc_noncoherent(dev, size, dma_handle, flag);
 }
diff --git a/include/asm-parisc/errno.h b/include/asm-parisc/errno.h
index 08464c405471..e2f3ddc796be 100644
--- a/include/asm-parisc/errno.h
+++ b/include/asm-parisc/errno.h
@@ -114,6 +114,7 @@
 
 #define ENOTSUP         252     /* Function not implemented (POSIX.4 / HPUX) */
 #define ECANCELLED      253     /* aio request was canceled before complete (POSIX.4 / HPUX) */
+#define ECANCELED       ECANCELLED      /* SuSv3 and Solaris wants one 'L' */
 
 /* for robust mutexes */
 #define EOWNERDEAD      254     /* Owner died */
diff --git a/include/asm-parisc/grfioctl.h b/include/asm-parisc/grfioctl.h
index d3cfc0168fb1..6a910311b56b 100644
--- a/include/asm-parisc/grfioctl.h
+++ b/include/asm-parisc/grfioctl.h
@@ -69,6 +69,8 @@
 #define CRT_ID_TVRX             S9000_ID_98765  /* TVRX (gto/falcon) */
 #define CRT_ID_ARTIST           S9000_ID_ARTIST /* Artist */
 #define CRT_ID_SUMMIT           0x2FC1066B      /* Summit FX2, FX4, FX6 ... */
+#define CRT_ID_LEGO             0x35ACDA30      /* Lego FX5, FX10 ... */
+#define CRT_ID_PINNACLE         0x35ACDA16      /* Pinnacle FXe */ 
 
 /* structure for ioctl(GCDESCRIBE) */
 
diff --git a/include/asm-parisc/ide.h b/include/asm-parisc/ide.h
index 3243cf2cd227..b27bf7aeb256 100644
--- a/include/asm-parisc/ide.h
+++ b/include/asm-parisc/ide.h
@@ -22,7 +22,6 @@
 
 #define ide_request_irq(irq,hand,flg,dev,id)    request_irq((irq),(hand),(flg),(dev),(id))
 #define ide_free_irq(irq,dev_id)                free_irq((irq), (dev_id))
-#define ide_check_region(from,extent)           check_region((from), (extent))
 #define ide_request_region(from,extent,name)    request_region((from), (extent), (name))
 #define ide_release_region(from,extent)         release_region((from), (extent))
 /* Generic I/O and MEMIO string operations.  */
diff --git a/include/asm-parisc/led.h b/include/asm-parisc/led.h
index 1ac8ab6c580d..efadfd543ec6 100644
--- a/include/asm-parisc/led.h
+++ b/include/asm-parisc/led.h
@@ -23,9 +23,6 @@
 
 #define LED_CMD_REG_NONE 0              /* NULL == no addr for the cmd register */
 
-/* led tasklet struct */
-extern struct tasklet_struct led_tasklet;
-
 /* register_led_driver() */
 int __init register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg);
 
diff --git a/include/asm-parisc/mmzone.h b/include/asm-parisc/mmzone.h
index 595d3dce120a..ae039f4fd711 100644
--- a/include/asm-parisc/mmzone.h
+++ b/include/asm-parisc/mmzone.h
@@ -27,12 +27,6 @@ extern struct node_map_data node_data[];
 })
 #define node_localnr(pfn, nid)          ((pfn) - node_start_pfn(nid))
 
-#define local_mapnr(kvaddr)                                             \
-({                                                                      \
-        unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT;               \
-        (__pfn - node_start_pfn(pfn_to_nid(__pfn)));                    \
-})
-
 #define pfn_to_page(pfn)                                                \
 ({                                                                      \
         unsigned long __pfn = (pfn);                                    \
diff --git a/include/asm-parisc/parisc-device.h b/include/asm-parisc/parisc-device.h
index ef69ab4b17a9..1d247e32a608 100644
--- a/include/asm-parisc/parisc-device.h
+++ b/include/asm-parisc/parisc-device.h
@@ -1,7 +1,7 @@
 #include <linux/device.h>
 
 struct parisc_device {
-        unsigned long   hpa;            /* Hard Physical Address */
+        struct resource hpa;            /* Hard Physical Address */
         struct parisc_device_id id;
         struct parisc_driver *driver;   /* Driver for this device */
         char            name[80];       /* The hardware description */
@@ -39,6 +39,11 @@ struct parisc_driver {
 #define to_parisc_driver(d)     container_of(d, struct parisc_driver, drv)
 #define parisc_parent(d)        to_parisc_device(d->dev.parent)
 
+static inline char *parisc_pathname(struct parisc_device *d)
+{
+        return d->dev.bus_id;
+}
+
 static inline void
 parisc_set_drvdata(struct parisc_device *d, void *p)
 {
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index d0b761f690b5..fa39d07d49e9 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -69,7 +69,7 @@ struct pci_hba_data {
 #define PCI_PORT_HBA(a)         ((a) >> HBA_PORT_SPACE_BITS)
 #define PCI_PORT_ADDR(a)        ((a) & (HBA_PORT_SPACE_SIZE - 1))
 
-#if CONFIG_64BIT
+#ifdef CONFIG_64BIT
 #define PCI_F_EXTEND            0xffffffff00000000UL
 #define PCI_IS_LMMIO(hba,a)     pci_is_lmmio(hba,a)
 
diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h
index 820c6e712cd7..c28fb6f48c6c 100644
--- a/include/asm-parisc/pgtable.h
+++ b/include/asm-parisc/pgtable.h
@@ -501,6 +501,8 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
+#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
+
 #define MK_IOSPACE_PFN(space, pfn)      (pfn)
 #define GET_IOSPACE(pfn)                0
 #define GET_PFN(pfn)                    (pfn)
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
index a9dfadd05658..aae40e8c3aa8 100644
--- a/include/asm-parisc/processor.h
+++ b/include/asm-parisc/processor.h
@@ -122,8 +122,27 @@ struct thread_struct {
 }; 
 
 /* Thread struct flags. */
+#define PARISC_UAC_NOPRINT      (1UL << 0)      /* see prctl and unaligned.c */
+#define PARISC_UAC_SIGBUS       (1UL << 1)
 #define PARISC_KERNEL_DEATH     (1UL << 31)     /* see die_if_kernel()... */
 
+#define PARISC_UAC_SHIFT        0
+#define PARISC_UAC_MASK         (PARISC_UAC_NOPRINT|PARISC_UAC_SIGBUS)
+
+#define SET_UNALIGN_CTL(task,value)                                       \
+        ({                                                                \
+        (task)->thread.flags = (((task)->thread.flags & ~PARISC_UAC_MASK) \
+                                | (((value) << PARISC_UAC_SHIFT) &        \
+                                   PARISC_UAC_MASK));                     \
+        0;                                                                \
+        })
+
+#define GET_UNALIGN_CTL(task,addr)                                        \
+        ({                                                                \
+        put_user(((task)->thread.flags & PARISC_UAC_MASK)                 \
+                 >> PARISC_UAC_SHIFT, (int __user *) (addr));             \
+        })
+
 #define INIT_THREAD { \
         regs:   {       gr: { 0, }, \
                         fr: { 0, }, \
diff --git a/include/asm-parisc/psw.h b/include/asm-parisc/psw.h
index 51323029f377..4334d6ca2add 100644
--- a/include/asm-parisc/psw.h
+++ b/include/asm-parisc/psw.h
@@ -1,4 +1,7 @@
 #ifndef _PARISC_PSW_H
+
+#include <linux/config.h>
+
 #define PSW_I   0x00000001
 #define PSW_D   0x00000002
 #define PSW_P   0x00000004
@@ -9,6 +12,16 @@
 #define PSW_G   0x00000040      /* PA1.x only */
 #define PSW_O   0x00000080      /* PA2.0 only */
 
+/* ssm/rsm instructions number PSW_W and PSW_E differently */
+#define PSW_SM_I        PSW_I   /* Enable External Interrupts */
+#define PSW_SM_D        PSW_D
+#define PSW_SM_P        PSW_P
+#define PSW_SM_Q        PSW_Q   /* Enable Interrupt State Collection */
+#define PSW_SM_R        PSW_R   /* Enable Recover Counter Trap */
+#define PSW_SM_W        0x200   /* PA2.0 only : Enable Wide Mode */
+
+#define PSW_SM_QUIET    PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I
+
 #define PSW_CB  0x0000ff00
 
 #define PSW_M   0x00010000
@@ -30,33 +43,21 @@
 #define PSW_Z   0x40000000      /* PA1.x only */
 #define PSW_Y   0x80000000      /* PA1.x only */
 
-#ifdef __LP64__
-#define PSW_HI_CB 0x000000ff    /* PA2.0 only */
+#ifdef CONFIG_64BIT
+#  define PSW_HI_CB 0x000000ff    /* PA2.0 only */
 #endif
 
-/* PSW bits to be used with ssm/rsm */
-#define PSW_SM_I        0x1
-#define PSW_SM_D        0x2
-#define PSW_SM_P        0x4
-#define PSW_SM_Q        0x8
-#define PSW_SM_R        0x10
-#define PSW_SM_F        0x20
-#define PSW_SM_G        0x40
-#define PSW_SM_O        0x80
-#define PSW_SM_E        0x100
-#define PSW_SM_W        0x200
-
-#ifdef __LP64__
-#  define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
-#  define KERNEL_PSW    (PSW_W | PSW_C | PSW_Q | PSW_P | PSW_D)
-#  define REAL_MODE_PSW (PSW_W | PSW_Q)
-#  define USER_PSW_MASK (PSW_W | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
-#  define USER_PSW_HI_MASK (PSW_HI_CB)
-#else
-#  define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
-#  define KERNEL_PSW    (PSW_C | PSW_Q | PSW_P | PSW_D)
-#  define REAL_MODE_PSW (PSW_Q)
-#  define USER_PSW_MASK (PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
+#ifdef CONFIG_64BIT
+#  define USER_PSW_HI_MASK      PSW_HI_CB
+#  define WIDE_PSW              PSW_W
+#else 
+#  define WIDE_PSW              0
 #endif
 
+/* Used when setting up for rfi */
+#define KERNEL_PSW    (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D)
+#define REAL_MODE_PSW (WIDE_PSW | PSW_Q)
+#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
+#define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
+
 #endif
diff --git a/include/asm-parisc/ptrace.h b/include/asm-parisc/ptrace.h
index 3f428aa371a4..93f990e418f1 100644
--- a/include/asm-parisc/ptrace.h
+++ b/include/asm-parisc/ptrace.h
@@ -49,7 +49,7 @@ struct pt_regs {
 #define user_mode(regs)                 (((regs)->iaoq[0] & 3) ? 1 : 0)
 #define user_space(regs)                (((regs)->iasq[1] != 0) ? 1 : 0)
 #define instruction_pointer(regs)       ((regs)->iaoq[0] & ~3)
-#define profile_pc(regs) instruction_pointer(regs)
+unsigned long profile_pc(struct pt_regs *);
 extern void show_regs(struct pt_regs *);
 #endif
 
diff --git a/include/asm-parisc/semaphore.h b/include/asm-parisc/semaphore.h
index f78bb2e34538..c9ee41cd0707 100644
--- a/include/asm-parisc/semaphore.h
+++ b/include/asm-parisc/semaphore.h
@@ -49,9 +49,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-parisc/spinlock.h b/include/asm-parisc/spinlock.h
index 43eaa6e742e0..7c3f406a746a 100644
--- a/include/asm-parisc/spinlock.h
+++ b/include/asm-parisc/spinlock.h
@@ -5,11 +5,6 @@
 #include <asm/processor.h>
 #include <asm/spinlock_types.h>
 
-/* Note that PA-RISC has to use `1' to mean unlocked and `0' to mean locked
- * since it only has load-and-zero. Moreover, at least on some PA processors,
- * the semaphore address has to be 16-byte aligned.
- */
-
 static inline int __raw_spin_is_locked(raw_spinlock_t *x)
 {
         volatile unsigned int *a = __ldcw_align(x);
diff --git a/include/asm-parisc/spinlock_types.h b/include/asm-parisc/spinlock_types.h
index 785bba822fbf..d6b479bdb886 100644
--- a/include/asm-parisc/spinlock_types.h
+++ b/include/asm-parisc/spinlock_types.h
@@ -6,11 +6,15 @@
 #endif
 
 typedef struct {
+#ifdef CONFIG_PA20
+        volatile unsigned int slock;
+# define __RAW_SPIN_LOCK_UNLOCKED { 1 }
+#else
         volatile unsigned int lock[4];
+# define __RAW_SPIN_LOCK_UNLOCKED       { { 1, 1, 1, 1 } }
+#endif
 } raw_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { { 1, 1, 1, 1 } }
-
 typedef struct {
         raw_spinlock_t lock;
         volatile int counter;
diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
index 26ff844a21c1..f3928d3a80cb 100644
--- a/include/asm-parisc/system.h
+++ b/include/asm-parisc/system.h
@@ -138,13 +138,7 @@ static inline void set_eiem(unsigned long val)
 #define set_wmb(var, value)             do { var = value; wmb(); } while (0)
 
 
-/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
-#define __ldcw(a) ({ \
-        unsigned __ret; \
-        __asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \
-        __ret; \
-})
-
+#ifndef CONFIG_PA20
 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
    and GCC only guarantees 8-byte alignment for stack locals, we can't
    be assured of 16-byte alignment for atomic lock data even if we
@@ -152,37 +146,41 @@ static inline void set_eiem(unsigned long val)
    we use a struct containing an array of four ints for the atomic lock
    type and dynamically select the 16-byte aligned int from the array
    for the semaphore.  */
+
 #define __PA_LDCW_ALIGNMENT 16
 #define __ldcw_align(a) ({ \
   unsigned long __ret = (unsigned long) &(a)->lock[0];                  \
   __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \
   (volatile unsigned int *) __ret;                                      \
 })
+#define LDCW    "ldcw"
 
-#ifdef CONFIG_SMP
-# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
-#endif
+#else /*CONFIG_PA20*/
+/* From: "Jim Hull" <jim.hull of hp.com>
+   I've attached a summary of the change, but basically, for PA 2.0, as
+   long as the ",CO" (coherent operation) completer is specified, then the
+   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
+   they only require "natural" alignment (4-byte for ldcw, 8-byte for
+   ldcd). */
 
-#define KERNEL_START (0x10100000 - 0x1000)
+#define __PA_LDCW_ALIGNMENT 4
+#define __ldcw_align(a) ((volatile unsigned int *)a)
+#define LDCW    "ldcw,co"
 
-/* This is for the serialisation of PxTLB broadcasts.  At least on the
- * N class systems, only one PxTLB inter processor broadcast can be
- * active at any one time on the Merced bus.  This tlb purge
- * synchronisation is fairly lightweight and harmless so we activate
- * it on all SMP systems not just the N class. */
-#ifdef CONFIG_SMP
-extern spinlock_t pa_tlb_lock;
+#endif /*!CONFIG_PA20*/
 
-#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
-#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
-
-#else
-
-#define purge_tlb_start(x) do { } while(0)
-#define purge_tlb_end(x) do { } while (0)
+/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
+#define __ldcw(a) ({ \
+        unsigned __ret; \
+        __asm__ __volatile__(LDCW " 0(%1),%0" : "=r" (__ret) : "r" (a)); \
+        __ret; \
+})
 
+#ifdef CONFIG_SMP
+# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
 #endif
 
+#define KERNEL_START (0x10100000 - 0x1000)
 #define arch_align_stack(x) (x)
 
 #endif
diff --git a/include/asm-parisc/tlbflush.h b/include/asm-parisc/tlbflush.h
index eb27b78930e8..e97aa8d1eff5 100644
--- a/include/asm-parisc/tlbflush.h
+++ b/include/asm-parisc/tlbflush.h
@@ -7,6 +7,26 @@
 #include <linux/mm.h>
 #include <asm/mmu_context.h>
 
+
+/* This is for the serialisation of PxTLB broadcasts.  At least on the
+ * N class systems, only one PxTLB inter processor broadcast can be
+ * active at any one time on the Merced bus.  This tlb purge
+ * synchronisation is fairly lightweight and harmless so we activate
+ * it on all SMP systems not just the N class. */
+#ifdef CONFIG_SMP
+extern spinlock_t pa_tlb_lock;
+
+#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
+#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
+
+#else
+
+#define purge_tlb_start(x) do { } while(0)
+#define purge_tlb_end(x) do { } while (0)
+
+#endif
+
+
 extern void flush_tlb_all(void);
 
 /*
@@ -64,29 +84,27 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
 {
         unsigned long npages;
 
-        
         npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-        if (npages >= 512)  /* XXX arbitrary, should be tuned */
+        if (npages >= 512)  /* 2MB of space: arbitrary, should be tuned */
                 flush_tlb_all();
         else {
-
+                preempt_disable();
                 mtsp(vma->vm_mm->context,1);
+                purge_tlb_start();
                 if (split_tlb) {
-                        purge_tlb_start();
                         while (npages--) {
                                 pdtlb(start);
                                 pitlb(start);
                                 start += PAGE_SIZE;
                         }
-                        purge_tlb_end();
                 } else {
-                        purge_tlb_start();
                         while (npages--) {
                                 pdtlb(start);
                                 start += PAGE_SIZE;
                         }
-                        purge_tlb_end();
+                preempt_enable();
                 }
+                purge_tlb_end();
         }
 }
 
diff --git a/include/asm-parisc/types.h b/include/asm-parisc/types.h
index d21b9d0d63ea..34fdce361a5a 100644
--- a/include/asm-parisc/types.h
+++ b/include/asm-parisc/types.h
@@ -33,8 +33,10 @@ typedef unsigned long long __u64;
 
 #ifdef __LP64__
 #define BITS_PER_LONG 64
+#define SHIFT_PER_LONG 6
 #else
 #define BITS_PER_LONG 32
+#define SHIFT_PER_LONG 5
 #endif
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-parisc/unistd.h b/include/asm-parisc/unistd.h
index 6a9f0cadff58..80b7b98c70a1 100644
--- a/include/asm-parisc/unistd.h
+++ b/include/asm-parisc/unistd.h
@@ -687,8 +687,8 @@
 #define __NR_shmget             (__NR_Linux + 194)
 #define __NR_shmctl             (__NR_Linux + 195)
 
-#define __NR_getpmsg            (__NR_Linux + 196)      /* some people actually want streams */
-#define __NR_putpmsg            (__NR_Linux + 197)      /* some people actually want streams */
+#define __NR_getpmsg            (__NR_Linux + 196) /* Somebody *wants* streams? */
+#define __NR_putpmsg            (__NR_Linux + 197)
 
 #define __NR_lstat64            (__NR_Linux + 198)
 #define __NR_truncate64         (__NR_Linux + 199)
@@ -755,8 +755,14 @@
 #define __NR_mbind              (__NR_Linux + 260)
 #define __NR_get_mempolicy      (__NR_Linux + 261)
 #define __NR_set_mempolicy      (__NR_Linux + 262)
+#define __NR_vserver            (__NR_Linux + 263)
+#define __NR_add_key            (__NR_Linux + 264)
+#define __NR_request_key        (__NR_Linux + 265)
+#define __NR_keyctl             (__NR_Linux + 266)
+#define __NR_ioprio_set         (__NR_Linux + 267)
+#define __NR_ioprio_get         (__NR_Linux + 268)
 
-#define __NR_Linux_syscalls     263
+#define __NR_Linux_syscalls     269
 
 #define HPUX_GATEWAY_ADDR       0xC0000004
 #define LINUX_GATEWAY_ADDR      0x100
@@ -807,10 +813,10 @@
 #define K_INLINE_SYSCALL(name, nr, args...)     ({                      \
         long __sys_res;                                                 \
         {                                                               \
-                register unsigned long __res asm("r28");                \
+                register unsigned long __res __asm__("r28");            \
                 K_LOAD_ARGS_##nr(args)                                  \
                 /* FIXME: HACK stw/ldw r19 around syscall */            \
-                asm volatile(                                           \
+                __asm__ volatile(                                       \
                         K_STW_ASM_PIC                                   \
                         "       ble  0x100(%%sr2, %%r0)\n"              \
                         "       ldi %1, %%r20\n"                        \
@@ -1005,7 +1011,6 @@ int sys_clone(unsigned long clone_flags, unsigned long usp,
                 struct pt_regs *regs);
 int sys_vfork(struct pt_regs *regs);
 int sys_pipe(int *fildes);
-long sys_ptrace(long request, pid_t pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-ppc64/a.out.h b/include/asm-powerpc/a.out.h
index 3871e252a6f1..c7393a977364 100644
--- a/include/asm-ppc64/a.out.h
+++ b/include/asm-powerpc/a.out.h
@@ -1,14 +1,5 @@
-#ifndef __PPC64_A_OUT_H__
-#define __PPC64_A_OUT_H__
-
-/*
- * c 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
+#ifndef _ASM_POWERPC_A_OUT_H
+#define _ASM_POWERPC_A_OUT_H
 
 struct exec
 {
@@ -27,6 +18,7 @@ struct exec
 #define N_SYMSIZE(a)    ((a).a_syms)
 
 #ifdef __KERNEL__
+#ifdef __powerpc64__
 
 #define STACK_TOP_USER64 TASK_SIZE_USER64
 #define STACK_TOP_USER32 TASK_SIZE_USER32
@@ -34,6 +26,11 @@ struct exec
 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
                    STACK_TOP_USER32 : STACK_TOP_USER64)
 
+#else /* __powerpc64__ */
+
+#define STACK_TOP TASK_SIZE
+
+#endif /* __powerpc64__ */
 #endif /* __KERNEL__ */
 
-#endif /* __PPC64_A_OUT_H__ */
+#endif /* _ASM_POWERPC_A_OUT_H */
diff --git a/include/asm-ppc/atomic.h b/include/asm-powerpc/atomic.h
index eeafd505836e..ed4b345ed75d 100644
--- a/include/asm-ppc/atomic.h
+++ b/include/asm-powerpc/atomic.h
@@ -1,29 +1,20 @@
+#ifndef _ASM_POWERPC_ATOMIC_H_
+#define _ASM_POWERPC_ATOMIC_H_
+
 /*
  * PowerPC atomic operations
  */
 
-#ifndef _ASM_PPC_ATOMIC_H_
-#define _ASM_PPC_ATOMIC_H_
-
 typedef struct { volatile int counter; } atomic_t;
 
 #ifdef __KERNEL__
+#include <asm/synch.h>
 
-#define ATOMIC_INIT(i)  { (i) }
+#define ATOMIC_INIT(i)          { (i) }
 
 #define atomic_read(v)          ((v)->counter)
 #define atomic_set(v,i)         (((v)->counter) = (i))
 
-extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
-
-#ifdef CONFIG_SMP
-#define SMP_SYNC        "sync"
-#define SMP_ISYNC       "\n\tisync"
-#else
-#define SMP_SYNC        ""
-#define SMP_ISYNC
-#endif
-
 /* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
  * The old ATOMIC_SYNC_FIX covered some but not all of this.
  */
@@ -53,12 +44,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%2         # atomic_add_return\n\
         add     %0,%1,%0\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -88,12 +80,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%2         # atomic_sub_return\n\
         subf    %0,%1,%0\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -121,12 +114,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_inc_return\n\
         addic   %0,%0,1\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1 \n\
         bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "memory");
@@ -164,12 +158,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_dec_return\n\
         addic   %0,%0,-1\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "memory");
@@ -189,13 +184,14 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
         addic.  %0,%0,-1\n\
         blt-    2f\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
         "\n\
 2:"     : "=&r" (t)
         : "r" (&v->counter)
@@ -204,11 +200,10 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         return t;
 }
 
-#define __MB    __asm__ __volatile__ (SMP_SYNC : : : "memory")
-#define smp_mb__before_atomic_dec()     __MB
-#define smp_mb__after_atomic_dec()      __MB
-#define smp_mb__before_atomic_inc()     __MB
-#define smp_mb__after_atomic_inc()      __MB
+#define smp_mb__before_atomic_dec()     smp_mb()
+#define smp_mb__after_atomic_dec()      smp_mb()
+#define smp_mb__before_atomic_inc()     smp_mb()
+#define smp_mb__after_atomic_inc()      smp_mb()
 
 #endif /* __KERNEL__ */
-#endif /* _ASM_PPC_ATOMIC_H_ */
+#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/include/asm-ppc64/auxvec.h b/include/asm-powerpc/auxvec.h
index ac6381a106e1..79d8c4732309 100644
--- a/include/asm-ppc64/auxvec.h
+++ b/include/asm-powerpc/auxvec.h
@@ -1,5 +1,5 @@
-#ifndef __PPC64_AUXVEC_H
-#define __PPC64_AUXVEC_H
+#ifndef _ASM_POWERPC_AUXVEC_H
+#define _ASM_POWERPC_AUXVEC_H
 
 /*
  * We need to put in some extra aux table entries to tell glibc what
@@ -14,6 +14,8 @@
 /* The vDSO location. We have to use the same value as x86 for glibc's
  * sake :-)
  */
+#ifdef __powerpc64__
 #define AT_SYSINFO_EHDR         33
+#endif
 
-#endif /* __PPC64_AUXVEC_H */
+#endif
diff --git a/include/asm-ppc/backlight.h b/include/asm-powerpc/backlight.h
index 3a1c3dede2a0..1ba1f27a0b63 100644
--- a/include/asm-ppc/backlight.h
+++ b/include/asm-powerpc/backlight.h
@@ -1,12 +1,13 @@
 /*
  * Routines for handling backlight control on PowerBooks
  *
- * For now, implementation resides in arch/ppc/kernel/pmac_support.c
+ * For now, implementation resides in
+ * arch/powerpc/platforms/powermac/pmac_support.c
  *
  */
+#ifndef __ASM_POWERPC_BACKLIGHT_H
+#define __ASM_POWERPC_BACKLIGHT_H
 #ifdef __KERNEL__
-#ifndef __ASM_PPC_BACKLIGHT_H
-#define __ASM_PPC_BACKLIGHT_H
 
 /* Abstract values */
 #define BACKLIGHT_OFF   0
@@ -26,5 +27,5 @@ extern int get_backlight_enable(void);
 extern int set_backlight_level(int level);
 extern int get_backlight_level(void);
 
-#endif
 #endif /* __KERNEL__ */
+#endif
diff --git a/include/asm-ppc64/bug.h b/include/asm-powerpc/bug.h
index 160178278861..e4d028e87020 100644
--- a/include/asm-ppc64/bug.h
+++ b/include/asm-powerpc/bug.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_BUG_H
-#define _PPC64_BUG_H
+#ifndef _ASM_POWERPC_BUG_H
+#define _ASM_POWERPC_BUG_H
 
 /*
  * Define an illegal instr to trap on the bug.
@@ -11,9 +11,21 @@
 
 #ifndef __ASSEMBLY__
 
+#ifdef __powerpc64__
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+        ".llong " #label "\n .long " #line "\n .llong " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: tdnei " #ra ", " #rb "\n"
+#define DATA_TYPE long long
+#else 
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+        ".long " #label ", " #line ", " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: twnei " #ra ", " #rb "\n"
+#define DATA_TYPE int
+#endif /* __powerpc64__ */
+
 struct bug_entry {
         unsigned long   bug_addr;
-        long            line;
+        int             line;
         const char      *file;
         const char      *function;
 };
@@ -32,28 +44,28 @@ struct bug_entry *find_bug(unsigned long bugaddr);
         __asm__ __volatile__(                                            \
                 "1:     twi 31,0,0\n"                                    \
                 ".section __bug_table,\"a\"\n\t"                         \
-                "       .llong 1b,%0,%1,%2\n"                            \
+                BUG_TABLE_ENTRY(1b,%0,%1,%2)                             \
                 ".previous"                                              \
                 : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
 } while (0)
 
 #define BUG_ON(x) do {                                          \
         __asm__ __volatile__(                                   \
-                "1:     tdnei %0,0\n"                           \
+                TRAP_OP(%0,0)                                   \
                 ".section __bug_table,\"a\"\n\t"                \
-                "       .llong 1b,%1,%2,%3\n"                   \
+                BUG_TABLE_ENTRY(1b,%1,%2,%3)                    \
                 ".previous"                                     \
-                : : "r" ((long long)(x)), "i" (__LINE__),       \
+                : : "r" ((DATA_TYPE)(x)), "i" (__LINE__),       \
                     "i" (__FILE__), "i" (__FUNCTION__));        \
 } while (0)
 
 #define WARN_ON(x) do {                                         \
         __asm__ __volatile__(                                   \
-                "1:     tdnei %0,0\n"                           \
+                TRAP_OP(%0,0)                                   \
                 ".section __bug_table,\"a\"\n\t"                \
-                "       .llong 1b,%1,%2,%3\n"                   \
+                BUG_TABLE_ENTRY(1b,%1,%2,%3)                    \
                 ".previous"                                     \
-                : : "r" ((long long)(x)),                       \
+                : : "r" ((DATA_TYPE)(x)),                       \
                     "i" (__LINE__ + BUG_WARNING_TRAP),          \
                     "i" (__FILE__), "i" (__FUNCTION__));        \
 } while (0)
@@ -61,9 +73,9 @@ struct bug_entry *find_bug(unsigned long bugaddr);
 #define HAVE_ARCH_BUG
 #define HAVE_ARCH_BUG_ON
 #define HAVE_ARCH_WARN_ON
-#endif
-#endif
+#endif /* CONFIG_BUG */
+#endif /* __ASSEMBLY __ */
 
 #include <asm-generic/bug.h>
 
-#endif
+#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-ppc64/byteorder.h b/include/asm-powerpc/byteorder.h
index 8b57da62b674..b37752214a16 100644
--- a/include/asm-ppc64/byteorder.h
+++ b/include/asm-powerpc/byteorder.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_BYTEORDER_H
-#define _PPC64_BYTEORDER_H
+#ifndef _ASM_POWERPC_BYTEORDER_H
+#define _ASM_POWERPC_BYTEORDER_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -77,10 +77,13 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
 
 #ifndef __STRICT_ANSI__
 #define __BYTEORDER_HAS_U64__
-#endif
+#ifndef __powerpc64__
+#define __SWAB_64_THRU_32__
+#endif /* __powerpc64__ */
+#endif /* __STRICT_ANSI__ */
 
 #endif /* __GNUC__ */
 
 #include <linux/byteorder/big_endian.h>
 
-#endif /* _PPC64_BYTEORDER_H */
+#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/include/asm-ppc64/checksum.h b/include/asm-powerpc/checksum.h
index d22d4469de43..d8354d8a49ce 100644
--- a/include/asm-ppc64/checksum.h
+++ b/include/asm-powerpc/checksum.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_CHECKSUM_H
-#define _PPC64_CHECKSUM_H
+#ifndef _ASM_POWERPC_CHECKSUM_H
+#define _ASM_POWERPC_CHECKSUM_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -41,8 +41,14 @@ extern unsigned int csum_partial(const unsigned char * buff, int len,
                                  unsigned int sum);
 
 /*
- * the same as csum_partial, but copies from src to dst while it
- * checksums
+ * Computes the checksum of a memory block at src, length len,
+ * and adds in "sum" (32-bit), while copying the block to dst.
+ * If an access exception occurs on src or dst, it stores -EFAULT
+ * to *src_err or *dst_err respectively (if that pointer is not
+ * NULL), and, for an error on src, zeroes the rest of dst.
+ *
+ * Like csum_partial, this must be called with even lengths,
+ * except for the last fragment.
  */
 extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
                                               int len, unsigned int sum,
@@ -51,12 +57,18 @@ extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
  * the same as csum_partial, but copies from src to dst while it
  * checksums.
  */
-
 unsigned int csum_partial_copy_nocheck(const char *src, 
                                        char *dst, 
                                        int len, 
                                        unsigned int sum);
 
+#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
+        csum_partial_copy_generic((src), (dst), (len), (sum), (errp), NULL)
+
+#define csum_partial_copy_nocheck(src, dst, len, sum)   \
+        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
+
+
 /*
  * turns a 32-bit partial checksum (e.g. from csum_partial) into a
  * 1's complement 16-bit checksum.
@@ -83,12 +95,7 @@ static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
         return csum_fold(csum_partial(buff, len, 0));
 }
 
-#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
-        csum_partial_copy_generic((src), (dst), (len), (sum), (errp), NULL)
-
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
-
+#ifdef __powerpc64__
 static inline u32 csum_tcpudp_nofold(u32 saddr,
                                      u32 daddr,
                                      unsigned short len,
@@ -103,5 +110,23 @@ static inline u32 csum_tcpudp_nofold(u32 saddr,
         s += (s >> 32);
         return (u32) s;
 }
+#else
+static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
+                                                   unsigned long daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   unsigned int sum)
+{
+    __asm__("\n\
+        addc %0,%0,%1 \n\
+        adde %0,%0,%2 \n\
+        adde %0,%0,%3 \n\
+        addze %0,%0 \n\
+        "
+        : "=r" (sum)
+        : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
+    return sum;
+}
 
 #endif
+#endif
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
new file mode 100644
index 000000000000..c019501daceb
--- /dev/null
+++ b/include/asm-powerpc/cputable.h
@@ -0,0 +1,427 @@
+#ifndef __ASM_POWERPC_CPUTABLE_H
+#define __ASM_POWERPC_CPUTABLE_H
+
+#include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
+
+#define PPC_FEATURE_32                  0x80000000
+#define PPC_FEATURE_64                  0x40000000
+#define PPC_FEATURE_601_INSTR           0x20000000
+#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
+#define PPC_FEATURE_HAS_FPU             0x08000000
+#define PPC_FEATURE_HAS_MMU             0x04000000
+#define PPC_FEATURE_HAS_4xxMAC          0x02000000
+#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
+#define PPC_FEATURE_HAS_SPE             0x00800000
+#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
+#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
+#define PPC_FEATURE_NO_TB               0x00100000
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+/* This structure can grow, it's real size is used by head.S code
+ * via the mkdefs mechanism.
+ */
+struct cpu_spec;
+struct op_powerpc_model;
+
+typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+
+struct cpu_spec {
+        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
+        unsigned int    pvr_mask;
+        unsigned int    pvr_value;
+
+        char            *cpu_name;
+        unsigned long   cpu_features;           /* Kernel features */
+        unsigned int    cpu_user_features;      /* Userland features */
+
+        /* cache line sizes */
+        unsigned int    icache_bsize;
+        unsigned int    dcache_bsize;
+
+        /* number of performance monitor counters */
+        unsigned int    num_pmcs;
+
+        /* this is called to initialize various CPU bits like L1 cache,
+         * BHT, SPD, etc... from head.S before branching to identify_machine
+         */
+        cpu_setup_t     cpu_setup;
+
+        /* Used by oprofile userspace to select the right counters */
+        char            *oprofile_cpu_type;
+
+        /* Processor specific oprofile operations */
+        struct op_powerpc_model *oprofile_model;
+};
+
+extern struct cpu_spec          *cur_cpu_spec;
+
+extern void identify_cpu(unsigned long offset, unsigned long cpu);
+extern void do_cpu_ftr_fixups(unsigned long offset);
+
+#endif /* __ASSEMBLY__ */
+
+/* CPU kernel features */
+
+/* Retain the 32b definitions all use bottom half of word */
+#define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
+#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
+#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
+#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
+#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
+#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
+#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
+#define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
+#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
+#define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
+#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
+#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
+#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
+#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
+#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
+#define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
+#define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
+#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
+#define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
+#define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
+
+#ifdef __powerpc64__
+/* Add the 64b processor unique features in the top half of the word */
+#define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
+#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000001000000000)
+#define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
+#define CPU_FTR_CTRL                    ASM_CONST(0x0000008000000000)
+#define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
+#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
+#else
+/* ensure on 32b processors the flags are available for compiling but
+ * don't do anything */
+#define CPU_FTR_SLB                     ASM_CONST(0x0)
+#define CPU_FTR_16M_PAGE                ASM_CONST(0x0)
+#define CPU_FTR_TLBIEL                  ASM_CONST(0x0)
+#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0)
+#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0)
+#define CPU_FTR_IABR                    ASM_CONST(0x0)
+#define CPU_FTR_MMCRA                   ASM_CONST(0x0)
+#define CPU_FTR_CTRL                    ASM_CONST(0x0)
+#define CPU_FTR_SMT                     ASM_CONST(0x0)
+#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0)
+#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0)
+#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0)
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
+                                        CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
+                                        CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
+
+/* iSeries doesn't support large pages */
+#ifdef CONFIG_PPC_ISERIES
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
+#else
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
+#endif /* CONFIG_PPC_ISERIES */
+
+/* We only set the altivec features if the kernel was compiled with altivec
+ * support
+ */
+#ifdef CONFIG_ALTIVEC
+#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
+#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
+#else
+#define CPU_FTR_ALTIVEC_COMP    0
+#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
+#endif
+
+/* We need to mark all pages as being coherent if we're SMP or we
+ * have a 74[45]x and an MPC107 host bridge.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
+#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
+#else
+#define CPU_FTR_COMMON                  0
+#endif
+
+/* The powersave features NAP & DOZE seems to confuse BDI when
+   debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE  0
+#define CPU_FTR_MAYBE_CAN_NAP   0
+#endif
+
+#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
+                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
+                     !defined(CONFIG_BOOKE))
+
+enum {
+        CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+        CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_NO_DPM,
+        CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+            CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+        CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
+        CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_E200 = CPU_FTR_USE_TB,
+        CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_BIG_PHYS,
+        CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
+#ifdef __powerpc64__
+        CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+        CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+            CPU_FTR_MMCRA | CPU_FTR_CTRL,
+        CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+        CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+        CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+            CPU_FTR_MMCRA | CPU_FTR_SMT |
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+            CPU_FTR_MMCRA_SIHV,
+        CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
+        CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
+#endif
+
+        CPU_FTRS_POSSIBLE =
+#if CLASSIC_PPC
+            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
+            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
+            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
+            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
+            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
+            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
+            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
+            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
+#else
+            CPU_FTRS_GENERIC_32 |
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+            CPU_FTRS_POWER3_32 |
+#endif
+#ifdef CONFIG_POWER4
+            CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
+#endif
+#ifdef CONFIG_8xx
+            CPU_FTRS_8XX |
+#endif
+#ifdef CONFIG_40x
+            CPU_FTRS_40X |
+#endif
+#ifdef CONFIG_44x
+            CPU_FTRS_44X |
+#endif
+#ifdef CONFIG_E200
+            CPU_FTRS_E200 |
+#endif
+#ifdef CONFIG_E500
+            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
+#endif
+#ifdef __powerpc64__
+            CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
+            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
+#endif
+            0,
+
+        CPU_FTRS_ALWAYS =
+#if CLASSIC_PPC
+            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
+            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
+            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
+            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
+            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
+            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
+            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
+            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
+#else
+            CPU_FTRS_GENERIC_32 &
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+            CPU_FTRS_POWER3_32 &
+#endif
+#ifdef CONFIG_POWER4
+            CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
+#endif
+#ifdef CONFIG_8xx
+            CPU_FTRS_8XX &
+#endif
+#ifdef CONFIG_40x
+            CPU_FTRS_40X &
+#endif
+#ifdef CONFIG_44x
+            CPU_FTRS_44X &
+#endif
+#ifdef CONFIG_E200
+            CPU_FTRS_E200 &
+#endif
+#ifdef CONFIG_E500
+            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
+#endif
+#ifdef __powerpc64__
+            CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
+            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
+#endif
+            CPU_FTRS_POSSIBLE,
+};
+
+static inline int cpu_has_feature(unsigned long feature)
+{
+        return (CPU_FTRS_ALWAYS & feature) ||
+               (CPU_FTRS_POSSIBLE
+                & cur_cpu_spec->cpu_features
+                & feature);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef __ASSEMBLY__
+
+#define BEGIN_FTR_SECTION               98:
+
+#ifndef __powerpc64__
+#define END_FTR_SECTION(msk, val)               \
+99:                                             \
+        .section __ftr_fixup,"a";               \
+        .align 2;                               \
+        .long msk;                              \
+        .long val;                              \
+        .long 98b;                              \
+        .long 99b;                              \
+        .previous
+#else /* __powerpc64__ */
+#define END_FTR_SECTION(msk, val)               \
+99:                                             \
+        .section __ftr_fixup,"a";               \
+        .align 3;                               \
+        .llong msk;                             \
+        .llong val;                             \
+        .llong 98b;                             \
+        .llong 99b;                             \
+        .previous
+#endif /* __powerpc64__ */
+
+#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/include/asm-ppc/dbdma.h b/include/asm-powerpc/dbdma.h
index 8973565f95d3..8973565f95d3 100644
--- a/include/asm-ppc/dbdma.h
+++ b/include/asm-powerpc/dbdma.h
diff --git a/include/asm-ppc/dma.h b/include/asm-powerpc/dma.h
index cc8e5cd8c9d2..926378d2cd94 100644
--- a/include/asm-ppc/dma.h
+++ b/include/asm-powerpc/dma.h
@@ -1,18 +1,14 @@
+#ifndef _ASM_POWERPC_DMA_H
+#define _ASM_POWERPC_DMA_H
+
 /*
- * include/asm-ppc/dma.h: Defines for using and allocating dma channels.
+ * Defines for using and allocating dma channels.
  * Written by Hennus Bergman, 1992.
  * High DMA channel support & info by Hannu Savolainen
  * and John Boyd, Nov. 1992.
  * Changes for ppc sound by Christoph Nadig
  */
 
-#ifdef __KERNEL__
-
-#include <linux/config.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-#include <asm/system.h>
-
 /*
  * Note: Adapted for PowerPC by Gary Thomas
  * Modified by Cort Dougan <cort@cs.nmt.edu>
@@ -25,8 +21,10 @@
  * with a grain of salt.
  */
 
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
+#include <linux/config.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+#include <asm/system.h>
 
 #ifndef MAX_DMA_CHANNELS
 #define MAX_DMA_CHANNELS        8
@@ -34,11 +32,9 @@
 
 /* The maximum address that we can perform a DMA transfer to on this platform */
 /* Doesn't really apply... */
-#define MAX_DMA_ADDRESS         0xFFFFFFFF
+#define MAX_DMA_ADDRESS         (~0UL)
 
-/* in arch/ppc/kernel/setup.c -- Cort */
-extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
-extern unsigned long ISA_DMA_THRESHOLD;
+#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
 
 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
 #define dma_outb        outb_p
@@ -171,7 +167,18 @@ extern long ppc_cs4232_dma, ppc_cs4232_dma2;
 #define DMA1_EXT_REG            0x40B
 #define DMA2_EXT_REG            0x4D6
 
+#ifndef __powerpc64__
+    /* in arch/ppc/kernel/setup.c -- Cort */
+    extern unsigned int DMA_MODE_WRITE;
+    extern unsigned int DMA_MODE_READ;
+    extern unsigned long ISA_DMA_THRESHOLD;
+#else
+    #define DMA_MODE_READ       0x44    /* I/O to memory, no autoinit, increment, single mode */
+    #define DMA_MODE_WRITE      0x48    /* memory to I/O, no autoinit, increment, single mode */
+#endif
+
 #define DMA_MODE_CASCADE        0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
 #define DMA_AUTOINIT            0x10
 
 extern spinlock_t dma_spin_lock;
@@ -200,8 +207,9 @@ static __inline__ void enable_dma(unsigned int dmanr)
         if (dmanr <= 3) {
                 dma_outb(dmanr, DMA1_MASK_REG);
                 dma_outb(ucDmaCmd, DMA1_CMD_REG);       /* Enable group */
-        } else
+        } else {
                 dma_outb(dmanr & 3, DMA2_MASK_REG);
+        }
 }
 
 static __inline__ void disable_dma(unsigned int dmanr)
@@ -290,19 +298,26 @@ static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 {
         if (dmanr <= 3) {
-                dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
-                dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                dma_outb(phys & 0xff,
+                         ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                dma_outb((phys >> 8) & 0xff,
+                         ((dmanr & 3) << 1) + IO_DMA1_BASE);
         } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
-                dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
-                dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb(phys & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 8) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
                 dma_outb((dmanr & 3), DMA2_EXT_REG);
         } else {
-                dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
-                dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 1) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 9) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
         }
         set_dma_page(dmanr, phys >> 16);
 }
 
+
 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
  * a specific DMA channel.
  * You must ensure the parameters are valid.
@@ -315,21 +330,24 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 {
         count--;
         if (dmanr <= 3) {
-                dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
-                dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
-                         IO_DMA1_BASE);
+                dma_outb(count & 0xff,
+                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
+                dma_outb((count >> 8) & 0xff,
+                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
         } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
-                dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-                dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
-                         IO_DMA2_BASE);
+                dma_outb(count & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
+                dma_outb((count >> 8) & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
         } else {
-                dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
-                         IO_DMA2_BASE);
-                dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
-                         IO_DMA2_BASE);
+                dma_outb((count >> 1) & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
+                dma_outb((count >> 9) & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
         }
 }
 
+
 /* Get DMA residue count. After a DMA transfer, this
  * should return zero. Reading this while a DMA transfer is
  * still in progress will return unpredictable results.
@@ -340,8 +358,8 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
  */
 static __inline__ int get_dma_residue(unsigned int dmanr)
 {
-        unsigned int io_port = (dmanr <= 3) ?
-            ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
+        unsigned int io_port = (dmanr <= 3)
+            ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
             : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
 
         /* using short to get 16-bit wrap around */
@@ -352,7 +370,6 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
 
         return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
             ? count : (count << 1);
-
 }
 
 /* These are in kernel/dma.c: */
@@ -367,5 +384,7 @@ extern int isa_dma_bridge_buggy;
 #else
 #define isa_dma_bridge_buggy    (0)
 #endif
-#endif                          /* _ASM_DMA_H */
-#endif                          /* __KERNEL__ */
+
+#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
+
+#endif  /* _ASM_POWERPC_DMA_H */
diff --git a/include/asm-ppc64/elf.h b/include/asm-powerpc/elf.h
index c919a89343db..d22b10021b5d 100644
--- a/include/asm-ppc64/elf.h
+++ b/include/asm-powerpc/elf.h
@@ -1,10 +1,11 @@
-#ifndef __PPC64_ELF_H
-#define __PPC64_ELF_H
+#ifndef _ASM_POWERPC_ELF_H
+#define _ASM_POWERPC_ELF_H
 
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/cputable.h>
 #include <asm/auxvec.h>
+#include <asm/page.h>
 
 /* PowerPC relocations defined by the ABIs */
 #define R_PPC_NONE              0
@@ -75,7 +76,7 @@
 #define R_PPC_GOT_DTPREL16_HI   93 /* half16*   (sym+add)@got@dtprel@h */
 #define R_PPC_GOT_DTPREL16_HA   94 /* half16*   (sym+add)@got@dtprel@ha */
 
-/* Keep this the last entry.  */
+/* keep this the last entry. */
 #define R_PPC_NUM               95
 
 /*
@@ -90,8 +91,6 @@
 
 #define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
 #define ELF_NFPREG      33      /* includes fpscr */
-#define ELF_NVRREG32    33      /* includes vscr & vrsave stuffed together */
-#define ELF_NVRREG      34      /* includes vscr & vrsave in split vectors */
 
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
@@ -100,8 +99,21 @@ typedef unsigned int elf_greg_t32;
 typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
 
 /*
- * These are used to set parameters in the core dumps.
+ * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
  */
+#ifdef __powerpc64__
+# define ELF_NVRREG32   33      /* includes vscr & vrsave stuffed together */
+# define ELF_NVRREG     34      /* includes vscr & vrsave in split vectors */
+# define ELF_GREG_TYPE  elf_greg_t64
+#else
+# define ELF_NEVRREG    34      /* includes acc (as 2) */
+# define ELF_NVRREG     33      /* includes vscr */
+# define ELF_GREG_TYPE  elf_greg_t32
+# define ELF_ARCH       EM_PPC
+# define ELF_CLASS      ELFCLASS32
+# define ELF_DATA       ELFDATA2MSB
+#endif /* __powerpc64__ */
+
 #ifndef ELF_ARCH
 # define ELF_ARCH       EM_PPC64
 # define ELF_CLASS      ELFCLASS64
@@ -114,8 +126,9 @@ typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
   typedef elf_greg_t32 elf_greg_t;
   typedef elf_gregset_t32 elf_gregset_t;
 # define elf_addr_t u32
-#endif
+#endif /* ELF_ARCH */
 
+/* Floating point registers */
 typedef double elf_fpreg_t;
 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
@@ -125,7 +138,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  * The entry with index 32 contains the vscr as the last word (offset 12) 
  * within the quadword.  This allows the vscr to be stored as either a 
  * quadword (since it must be copied via a vector register to/from storage) 
- * or as a word.  The entry with index 33 contains the vrsave as the first 
+ * or as a word.  
+ *
+ * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first  
  * word (offset 0) within the quadword.
  *
  * This definition of the VMX state is compatible with the current PPC32 
@@ -138,7 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  */
 typedef __vector128 elf_vrreg_t;
 typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+#ifdef __powerpc64__
 typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
+#endif
 
 /*
  * This is used to ensure we don't load something for the wrong architecture.
@@ -146,7 +163,7 @@ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
 #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
 
 #define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
    use of this is to invoke "./ld.so someprog" to test out a new version of
@@ -158,26 +175,30 @@ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
 #ifdef __KERNEL__
 
 /* Common routine for both 32-bit and 64-bit processes */
-static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs,
+static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
                                             struct pt_regs *regs)
 {
         int i;
-        int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64);
+        int gprs = sizeof(struct pt_regs)/sizeof(ELF_GREG_TYPE);
 
         if (gprs > ELF_NGREG)
                 gprs = ELF_NGREG;
 
         for (i=0; i < gprs; i++)
-                elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i];
+                elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
+
+        memset((char *)(elf_regs) + sizeof(struct pt_regs), 0,          \
+               sizeof(elf_gregset_t) - sizeof(struct pt_regs));
+
 }
-#define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs);
+#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
 
 static inline int dump_task_regs(struct task_struct *tsk,
                                  elf_gregset_t *elf_regs)
 {
         struct pt_regs *regs = tsk->thread.regs;
         if (regs)
-                ppc64_elf_core_copy_regs(*elf_regs, regs);
+                ppc_elf_core_copy_regs(*elf_regs, regs);
 
         return 1;
 }
@@ -186,15 +207,17 @@ static inline int dump_task_regs(struct task_struct *tsk,
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 
 #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
 
-/* XXX Should we define the XFPREGS using altivec ??? */
-
-#endif
+#endif /* __KERNEL__ */
 
-/* This yields a mask that user programs can use to figure out what
+/* ELF_HWCAP yields a mask that user programs can use to figure out what
    instruction set this cpu supports.  This could be done in userspace,
    but it's not easy, and we've already done it here.  */
-
-#define ELF_HWCAP       (cur_cpu_spec->cpu_user_features)
+# define ELF_HWCAP      (cur_cpu_spec->cpu_user_features)
+#ifdef __powerpc64__
+# define ELF_PLAT_INIT(_r, load_addr)   do {    \
+        _r->gpr[2] = load_addr;                 \
+} while (0)
+#endif /* __powerpc64__ */
 
 /* This yields a string that ld.so will use to load implementation
    specific libraries for optimization.  This is more specific in
@@ -205,14 +228,10 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
 
 #define ELF_PLATFORM    (NULL)
 
-#define ELF_PLAT_INIT(_r, load_addr)    do { \
-        memset(_r->gpr, 0, sizeof(_r->gpr)); \
-        _r->ctr = _r->link = _r->xer = _r->ccr = 0; \
-        _r->gpr[2] = load_addr; \
-} while (0)
-
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2)                              \
+
+#ifdef __powerpc64__
+# define SET_PERSONALITY(ex, ibcs2)                             \
 do {                                                            \
         unsigned long new_flags = 0;                            \
         if ((ex).e_ident[EI_CLASS] == ELFCLASS32)               \
@@ -225,7 +244,6 @@ do {								\
         if (personality(current->personality) != PER_LINUX32)   \
                 set_personality(PER_LINUX);                     \
 } while (0)
-
 /*
  * An executable for which elf_read_implies_exec() returns TRUE will
  * have the READ_IMPLIES_EXEC personality flag set automatically. This
@@ -233,19 +251,26 @@ do {								\
  * the 64bit ABI has never had these issues dont enable the workaround
  * even if we have an executable stack.
  */
-#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
+# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
                 (exec_stk != EXSTACK_DISABLE_X) : 0)
+#else 
+# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#endif /* __powerpc64__ */
 
-#endif
+#endif /* __KERNEL__ */
 
 extern int dcache_bsize;
 extern int icache_bsize;
 extern int ucache_bsize;
 
-/* We do have an arch_setup_additional_pages for vDSO matters */
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+#ifdef __powerpc64__
 struct linux_binprm;
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES /* vDSO has arch_setup_additional_pages */
 extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
+#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
+#else
+#define VDSO_AUX_ENT(a,b)
+#endif /* __powerpc64__ */
 
 /*
  * The requirements here are:
@@ -265,9 +290,8 @@ do {									\
         NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
         NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
         NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
-        /* vDSO base */                                                 \
-        NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base);        \
- } while (0)
+        VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base)        \
+} while (0)
 
 /* PowerPC64 relocations defined by the ABIs */
 #define R_PPC64_NONE    R_PPC_NONE
@@ -384,4 +408,4 @@ do {									\
 /* Keep this the last entry.  */
 #define R_PPC64_NUM             107
 
-#endif /* __PPC64_ELF_H */
+#endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-ppc64/firmware.h b/include/asm-powerpc/firmware.h
index 22bb85cf60af..806c142ae9ea 100644
--- a/include/asm-ppc64/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -1,8 +1,4 @@
 /*
- *  include/asm-ppc64/firmware.h
- *
- *  Extracted from include/asm-ppc64/cputable.h
- *
  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  *
  *  Modifications for ppc64:
@@ -13,8 +9,8 @@
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  */
-#ifndef __ASM_PPC_FIRMWARE_H
-#define __ASM_PPC_FIRMWARE_H
+#ifndef __ASM_POWERPC_FIRMWARE_H
+#define __ASM_POWERPC_FIRMWARE_H
 
 #ifdef __KERNEL__
 
@@ -98,4 +94,4 @@ extern firmware_feature_t firmware_features_table[];
 
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
-#endif /* __ASM_PPC_FIRMWARE_H */
+#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/include/asm-powerpc/grackle.h b/include/asm-powerpc/grackle.h
new file mode 100644
index 000000000000..563c7a5e64c9
--- /dev/null
+++ b/include/asm-powerpc/grackle.h
@@ -0,0 +1,7 @@
+/*
+ * Functions for setting up and using a MPC106 northbridge
+ */
+
+#include <asm/pci-bridge.h>
+
+extern void setup_grackle(struct pci_controller *hose);
diff --git a/include/asm-ppc/hardirq.h b/include/asm-powerpc/hardirq.h
index 94f1411b1a93..3b3e3b49ec12 100644
--- a/include/asm-ppc/hardirq.h
+++ b/include/asm-powerpc/hardirq.h
@@ -1,11 +1,8 @@
-#ifdef __KERNEL__
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
+#ifndef _ASM_POWERPC_HARDIRQ_H
+#define _ASM_POWERPC_HARDIRQ_H
 
-#include <linux/config.h>
-#include <linux/cache.h>
-#include <linux/smp_lock.h>
 #include <asm/irq.h>
+#include <asm/bug.h>
 
 /* The __last_jiffy_stamp field is needed to ensure that no decrementer
  * interrupt is lost on SMP machines. Since on most CPUs it is in the same
@@ -13,7 +10,7 @@
  * for uniformity.
  */
 typedef struct {
-        unsigned long __softirq_pending;        /* set_bit is used on this */
+        unsigned int __softirq_pending; /* set_bit is used on this */
         unsigned int __last_jiffy_stamp;
 } ____cacheline_aligned irq_cpustat_t;
 
@@ -27,5 +24,4 @@ static inline void ack_bad_irq(int irq)
         BUG();
 }
 
-#endif /* __ASM_HARDIRQ_H */
-#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/include/asm-ppc/heathrow.h b/include/asm-powerpc/heathrow.h
index 22ac179856b9..22ac179856b9 100644
--- a/include/asm-ppc/heathrow.h
+++ b/include/asm-powerpc/heathrow.h
diff --git a/include/asm-ppc64/hw_irq.h b/include/asm-powerpc/hw_irq.h
index baea40e695ec..c37b31b96337 100644
--- a/include/asm-ppc64/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -1,22 +1,17 @@
 /*
  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- *
- * Use inline IRQs where possible - Anton Blanchard <anton@au.ibm.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
  */
+#ifndef _ASM_POWERPC_HW_IRQ_H
+#define _ASM_POWERPC_HW_IRQ_H
+
 #ifdef __KERNEL__
-#ifndef _PPC64_HW_IRQ_H
-#define _PPC64_HW_IRQ_H
 
 #include <linux/config.h>
 #include <linux/errno.h>
-#include <asm/irq.h>
+#include <asm/ptrace.h>
+#include <asm/processor.h>
 
-int timer_interrupt(struct pt_regs *);
+extern void timer_interrupt(struct pt_regs *);
 extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
 
 #ifdef CONFIG_PPC_ISERIES
@@ -33,45 +28,60 @@ extern void local_irq_restore(unsigned long);
 
 #else
 
-#define local_save_flags(flags) ((flags) = mfmsr())
+#if defined(CONFIG_BOOKE)
+#define SET_MSR_EE(x)   mtmsr(x)
+#define local_irq_restore(flags)        __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
+#elif defined(__powerpc64__)
+#define SET_MSR_EE(x)   __mtmsrd(x, 1)
 #define local_irq_restore(flags) do { \
         __asm__ __volatile__("": : :"memory"); \
         __mtmsrd((flags), 1); \
 } while(0)
+#else
+#define SET_MSR_EE(x)   mtmsr(x)
+#define local_irq_restore(flags)        mtmsr(flags)
+#endif
 
 static inline void local_irq_disable(void)
 {
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 0": : :"memory");
+#else
         unsigned long msr;
-        msr = mfmsr();
-        __mtmsrd(msr & ~MSR_EE, 1);
         __asm__ __volatile__("": : :"memory");
+        msr = mfmsr();
+        SET_MSR_EE(msr & ~MSR_EE);
+#endif
 }
 
 static inline void local_irq_enable(void)
 {
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 1": : :"memory");
+#else
         unsigned long msr;
         __asm__ __volatile__("": : :"memory");
         msr = mfmsr();
-        __mtmsrd(msr | MSR_EE, 1);
+        SET_MSR_EE(msr | MSR_EE);
+#endif
 }
 
-static inline void __do_save_and_cli(unsigned long *flags)
+static inline void local_irq_save_ptr(unsigned long *flags)
 {
         unsigned long msr;
         msr = mfmsr();
         *flags = msr;
-        __mtmsrd(msr & ~MSR_EE, 1);
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 0": : :"memory");
+#else
+        SET_MSR_EE(msr & ~MSR_EE);
+#endif
         __asm__ __volatile__("": : :"memory");
 }
 
-#define local_irq_save(flags)          __do_save_and_cli(&flags)
-
-#define irqs_disabled()                         \
-({                                              \
-        unsigned long flags;                    \
-        local_save_flags(flags);                \
-        !(flags & MSR_EE);                      \
-})
+#define local_save_flags(flags) ((flags) = mfmsr())
+#define local_irq_save(flags)   local_irq_save_ptr(&flags)
+#define irqs_disabled()         ((mfmsr() & MSR_EE) == 0)
 
 #endif /* CONFIG_PPC_ISERIES */
 
@@ -99,6 +109,6 @@ static inline void __do_save_and_cli(unsigned long *flags)
  */
 struct hw_interrupt_type;
 static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
- 
-#endif /* _PPC64_HW_IRQ_H */
-#endif /* __KERNEL__ */
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/include/asm-powerpc/i8259.h b/include/asm-powerpc/i8259.h
new file mode 100644
index 000000000000..fc4bfee124d7
--- /dev/null
+++ b/include/asm-powerpc/i8259.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_POWERPC_I8259_H
+#define _ASM_POWERPC_I8259_H
+
+#include <linux/irq.h>
+
+extern struct hw_interrupt_type i8259_pic;
+
+extern void i8259_init(unsigned long intack_addr, int offset);
+extern int i8259_irq(struct pt_regs *regs);
+extern int i8259_irq_cascade(struct pt_regs *regs, void *unused);
+
+#endif /* _ASM_POWERPC_I8259_H */
diff --git a/include/asm-ppc64/iommu.h b/include/asm-powerpc/iommu.h
index c2f3b6e8a42f..9d91bdd667ae 100644
--- a/include/asm-ppc64/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -1,5 +1,4 @@
 /*
- * iommu.h
  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  * Rewrite, cleanup:
  * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
@@ -22,6 +21,7 @@
 #ifndef _ASM_IOMMU_H
 #define _ASM_IOMMU_H
 
+#include <linux/config.h>
 #include <asm/types.h>
 #include <linux/spinlock.h>
 #include <linux/device.h>
@@ -29,44 +29,11 @@
 
 /*
  * IOMAP_MAX_ORDER defines the largest contiguous block
- * of dma (tce) space we can get.  IOMAP_MAX_ORDER = 13
+ * of dma space we can get.  IOMAP_MAX_ORDER = 13
  * allows up to 2**12 pages (4096 * 4096) = 16 MB
  */
 #define IOMAP_MAX_ORDER 13
 
-/*
- * Tces come in two formats, one for the virtual bus and a different
- * format for PCI
- */
-#define TCE_VB  0
-#define TCE_PCI 1
-
-/* tce_entry
- * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
- * abstracted so layout is irrelevant.
- */
-union tce_entry {
-        unsigned long te_word;
-        struct {
-                unsigned int  tb_cacheBits :6;  /* Cache hash bits - not used */
-                unsigned int  tb_rsvd      :6;
-                unsigned long tb_rpn       :40; /* Real page number */
-                unsigned int  tb_valid     :1;  /* Tce is valid (vb only) */
-                unsigned int  tb_allio     :1;  /* Tce is valid for all lps (vb only) */
-                unsigned int  tb_lpindex   :8;  /* LpIndex for user of TCE (vb only) */
-                unsigned int  tb_pciwr     :1;  /* Write allowed (pci only) */
-                unsigned int  tb_rdwr      :1;  /* Read allowed  (pci), Write allowed (vb) */
-        } te_bits;
-#define te_cacheBits te_bits.tb_cacheBits
-#define te_rpn       te_bits.tb_rpn
-#define te_valid     te_bits.tb_valid
-#define te_allio     te_bits.tb_allio
-#define te_lpindex   te_bits.tb_lpindex
-#define te_pciwr     te_bits.tb_pciwr
-#define te_rdwr      te_bits.tb_rdwr
-};
-
-
 struct iommu_table {
         unsigned long  it_busno;     /* Bus number this table belongs to */
         unsigned long  it_size;      /* Size of iommu table in entries */
@@ -83,6 +50,7 @@ struct iommu_table {
 };
 
 struct scatterlist;
+struct device_node;
 
 #ifdef CONFIG_PPC_MULTIPLATFORM
 
@@ -104,9 +72,8 @@ extern void iommu_devnode_init_pSeries(struct device_node *dn);
 
 #ifdef CONFIG_PPC_ISERIES
 
-struct iSeries_Device_Node;
 /* Creates table for an individual device node */
-extern void iommu_devnode_init_iSeries(struct iSeries_Device_Node *dn);
+extern void iommu_devnode_init_iSeries(struct device_node *dn);
 
 #endif /* CONFIG_PPC_ISERIES */
 
diff --git a/include/asm-ppc/irq.h b/include/asm-powerpc/irq.h
index bd9674807f05..c7c3f912a3c2 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -1,11 +1,23 @@
 #ifdef __KERNEL__
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
+#ifndef _ASM_POWERPC_IRQ_H
+#define _ASM_POWERPC_IRQ_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
 
 #include <linux/config.h>
-#include <asm/machdep.h>                /* ppc_md */
+#include <linux/threads.h>
+
+#include <asm/types.h>
 #include <asm/atomic.h>
 
+/* this number is used when no interrupt has been assigned */
+#define NO_IRQ                  (-1)
+
 /*
  * These constants are used for passing information about interrupt
  * signal polarity and level/edge sensing to the low-level PIC chip
@@ -24,6 +36,50 @@
  */
 #define ARCH_HAS_IRQ_PER_CPU
 
+#define get_irq_desc(irq) (&irq_desc[(irq)])
+
+/* Define a way to iterate across irqs. */
+#define for_each_irq(i) \
+        for ((i) = 0; (i) < NR_IRQS; ++(i))
+
+#ifdef CONFIG_PPC64
+
+/*
+ * Maximum number of interrupt sources that we can handle.
+ */
+#define NR_IRQS         512
+
+/* Interrupt numbers are virtual in case they are sparsely
+ * distributed by the hardware.
+ */
+extern unsigned int virt_irq_to_real_map[NR_IRQS];
+
+/* Create a mapping for a real_irq if it doesn't already exist.
+ * Return the virtual irq as a convenience.
+ */
+int virt_irq_create_mapping(unsigned int real_irq);
+void virt_irq_init(void);
+
+static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
+{
+        return virt_irq_to_real_map[virt_irq];
+}
+
+extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
+
+/*
+ * List of interrupt controllers.
+ */
+#define IC_INVALID    0
+#define IC_OPEN_PIC   1
+#define IC_PPC_XIC    2
+#define IC_BPA_IIC    3
+#define IC_ISERIES    4
+
+extern u64 ppc64_interrupt_controller;
+
+#else /* 32-bit */
+
 #if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
 
@@ -66,11 +122,6 @@
 #define NR_UIC_IRQS UIC_WIDTH
 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 #endif
-static __inline__ int
-irq_canonicalize(int irq)
-{
-        return (irq);
-}
 
 #elif defined(CONFIG_44x)
 #include <asm/ibm44x.h>
@@ -78,12 +129,6 @@ irq_canonicalize(int irq)
 #define NR_UIC_IRQS     32
 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 
-static __inline__ int
-irq_canonicalize(int irq)
-{
-        return (irq);
-}
-
 #elif defined(CONFIG_8xx)
 
 /* Now include the board configuration specific associations.
@@ -170,20 +215,9 @@ irq_canonicalize(int irq)
  */
 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
 
-/* always the same on 8xx -- Cort */
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
 #elif defined(CONFIG_83xx)
 #include <asm/mpc83xx.h>
 
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
 #define NR_IRQS (NR_IPIC_INTS)
 
 #elif defined(CONFIG_85xx)
@@ -307,17 +341,13 @@ static __inline__ int irq_canonicalize(int irq)
 #define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
 #define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
 
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
 #else /* CONFIG_40x + CONFIG_8xx */
 /*
  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
  * so it is the max of them all
  */
 #define NR_IRQS                 256
+#define __DO_IRQ_CANON  1
 
 #ifndef CONFIG_8260
 
@@ -394,25 +424,81 @@ static __inline__ int irq_canonicalize(int irq)
 
 #endif /* CONFIG_8260 */
 
+#endif
+
+#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+/* pedantic: these are long because they are used with set_bit --RR */
+extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
+extern atomic_t ppc_n_lost_interrupts;
+
+#define virt_irq_create_mapping(x)      (x)
+
+#endif
+
 /*
- * This gets called from serial.c, which is now used on
- * powermacs as well as prep/chrp boxes.
- * Prep and chrp both have cascaded 8259 PICs.
+ * Because many systems have two overlapping names spaces for
+ * interrupts (ISA and XICS for example), and the ISA interrupts
+ * have historically not been easy to renumber, we allow ISA
+ * interrupts to take values 0 - 15, and shift up the remaining
+ * interrupts by 0x10.
  */
+#define NUM_ISA_INTERRUPTS      0x10
+extern int __irq_offset_value;
+
+static inline int irq_offset_up(int irq)
+{
+        return(irq + __irq_offset_value);
+}
+
+static inline int irq_offset_down(int irq)
+{
+        return(irq - __irq_offset_value);
+}
+
+static inline int irq_offset_value(void)
+{
+        return __irq_offset_value;
+}
+
+#ifdef __DO_IRQ_CANON
+extern int ppc_do_canonicalize_irqs;
+#else
+#define ppc_do_canonicalize_irqs        0
+#endif
+
 static __inline__ int irq_canonicalize(int irq)
 {
-        if (ppc_md.irq_canonicalize)
-                return ppc_md.irq_canonicalize(irq);
+        if (ppc_do_canonicalize_irqs && irq == 2)
+                irq = 9;
         return irq;
 }
 
-#endif
+extern int distribute_irqs;
 
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-/* pedantic: these are long because they are used with set_bit --RR */
-extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
-extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
-extern atomic_t ppc_n_lost_interrupts;
+struct irqaction;
+struct pt_regs;
+
+#ifdef CONFIG_IRQSTACKS
+/*
+ * Per-cpu stacks for handling hard and soft interrupts.
+ */
+extern struct thread_info *hardirq_ctx[NR_CPUS];
+extern struct thread_info *softirq_ctx[NR_CPUS];
+
+extern void irq_ctx_init(void);
+extern void call_do_softirq(struct thread_info *tp);
+extern int call_handle_IRQ_event(int irq, struct pt_regs *regs,
+                        struct irqaction *action, struct thread_info *tp);
+
+#define __ARCH_HAS_DO_SOFTIRQ
+
+#else
+#define irq_ctx_init()
+
+#endif /* CONFIG_IRQSTACKS */
+
+extern void do_IRQ(struct pt_regs *regs);
 
 #endif /* _ASM_IRQ_H */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/kdebug.h b/include/asm-powerpc/kdebug.h
index d383d161cf8d..9dcbac674811 100644
--- a/include/asm-ppc64/kdebug.h
+++ b/include/asm-powerpc/kdebug.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_KDEBUG_H
-#define _PPC64_KDEBUG_H 1
+#ifndef _ASM_POWERPC_KDEBUG_H
+#define _ASM_POWERPC_KDEBUG_H
 
 /* nearly identical to x86_64/i386 code */
 
@@ -21,7 +21,7 @@ struct die_args {
    then free.
  */
 int register_die_notifier(struct notifier_block *nb);
-extern struct notifier_block *ppc64_die_chain;
+extern struct notifier_block *powerpc_die_chain;
 
 /* Grossly misnamed. */
 enum die_val {
@@ -30,14 +30,13 @@ enum die_val {
         DIE_DABR_MATCH,
         DIE_BPT,
         DIE_SSTEP,
-        DIE_GPF,
         DIE_PAGE_FAULT,
 };
 
 static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
 {
         struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
-        return notifier_call_chain(&ppc64_die_chain, val, &args);
+        return notifier_call_chain(&powerpc_die_chain, val, &args);
 }
 
-#endif
+#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/include/asm-ppc/keylargo.h b/include/asm-powerpc/keylargo.h
index a669a3f0f5a2..a669a3f0f5a2 100644
--- a/include/asm-ppc/keylargo.h
+++ b/include/asm-powerpc/keylargo.h
diff --git a/include/asm-powerpc/kmap_types.h b/include/asm-powerpc/kmap_types.h
new file mode 100644
index 000000000000..b6bac6f61c16
--- /dev/null
+++ b/include/asm-powerpc/kmap_types.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_POWERPC_KMAP_TYPES_H
+#define _ASM_POWERPC_KMAP_TYPES_H
+
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_PPC_SYNC_PAGE,
+        KM_PPC_SYNC_ICACHE,
+        KM_TYPE_NR
+};
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/include/asm-ppc64/kprobes.h b/include/asm-powerpc/kprobes.h
index d9129d2b038e..b2f09f17fbe0 100644
--- a/include/asm-ppc64/kprobes.h
+++ b/include/asm-powerpc/kprobes.h
@@ -1,8 +1,7 @@
-#ifndef _ASM_KPROBES_H
-#define _ASM_KPROBES_H
+#ifndef _ASM_POWERPC_KPROBES_H
+#define _ASM_POWERPC_KPROBES_H
 /*
  *  Kernel Probes (KProbes)
- *  include/asm-ppc64/kprobes.h
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -64,4 +63,4 @@ static inline int kprobe_exceptions_notify(struct notifier_block *self,
         return 0;
 }
 #endif
-#endif                          /* _ASM_KPROBES_H */
+#endif  /* _ASM_POWERPC_KPROBES_H */
diff --git a/include/asm-ppc64/lmb.h b/include/asm-powerpc/lmb.h
index de91e034bd98..ea0afe343545 100644
--- a/include/asm-ppc64/lmb.h
+++ b/include/asm-powerpc/lmb.h
@@ -50,7 +50,7 @@ extern unsigned long __init lmb_alloc_base(unsigned long, unsigned long,
 extern unsigned long __init lmb_phys_mem_size(void);
 extern unsigned long __init lmb_end_of_DRAM(void);
 extern unsigned long __init lmb_abs_to_phys(unsigned long);
-extern void __init lmb_enforce_memory_limit(void);
+extern void __init lmb_enforce_memory_limit(unsigned long);
 
 extern void lmb_dump_all(void);
 
diff --git a/include/asm-ppc64/machdep.h b/include/asm-powerpc/machdep.h
index 8027160ec96d..451b345cfc78 100644
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -1,6 +1,6 @@
+#ifndef _ASM_POWERPC_MACHDEP_H
+#define _ASM_POWERPC_MACHDEP_H
 #ifdef __KERNEL__
-#ifndef _PPC64_MACHDEP_H
-#define _PPC64_MACHDEP_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -16,6 +16,11 @@
 
 #include <asm/setup.h>
 
+/* We export this macro for external modules like Alsa to know if
+ * ppc_md.feature_call is implemented or not
+ */
+#define CONFIG_PPC_HAS_FEATURE_CALLS
+
 struct pt_regs;
 struct pci_bus; 
 struct device_node;
@@ -39,6 +44,7 @@ struct smp_ops_t {
 #endif
 
 struct machdep_calls {
+#ifdef CONFIG_PPC64
         void            (*hpte_invalidate)(unsigned long slot,
                                            unsigned long va,
                                            int large,
@@ -56,9 +62,8 @@ struct machdep_calls {
                                        unsigned long vflags,
                                        unsigned long rflags);
         long            (*hpte_remove)(unsigned long hpte_group);
-        void            (*flush_hash_range)(unsigned long context,
-                                            unsigned long number,
-                                            int local);
+        void            (*flush_hash_range)(unsigned long number, int local);
+
         /* special for kexec, to be called in real mode, linar mapping is
          * destroyed as well */
         void            (*hpte_clear_all)(void);
@@ -75,18 +80,21 @@ struct machdep_calls {
         void            (*iommu_dev_setup)(struct pci_dev *dev);
         void            (*iommu_bus_setup)(struct pci_bus *bus);
         void            (*irq_bus_setup)(struct pci_bus *bus);
+#endif
 
         int             (*probe)(int platform);
         void            (*setup_arch)(void);
         void            (*init_early)(void);
         /* Optional, may be NULL. */
-        void            (*get_cpuinfo)(struct seq_file *m);
+        void            (*show_cpuinfo)(struct seq_file *m);
+        void            (*show_percpuinfo)(struct seq_file *m, int i);
 
         void            (*init_IRQ)(void);
         int             (*get_irq)(struct pt_regs *);
         void            (*cpu_irq_down)(int secondary);
 
         /* PCI stuff */
+        /* Called after scanning the bus, before allocating resources */
         void            (*pcibios_fixup)(void);
         int             (*pci_probe_mode)(struct pci_bus *);
 
@@ -96,9 +104,13 @@ struct machdep_calls {
         void            (*panic)(char *str);
         void            (*cpu_die)(void);
 
+        long            (*time_init)(void); /* Optional, may be NULL */
+
         int             (*set_rtc_time)(struct rtc_time *);
         void            (*get_rtc_time)(struct rtc_time *);
-        void            (*get_boot_time)(struct rtc_time *);
+        unsigned long   (*get_boot_time)(void);
+        unsigned char   (*rtc_read_val)(int addr);
+        void            (*rtc_write_val)(int addr, unsigned char val);
 
         void            (*calibrate_decr)(void);
 
@@ -107,10 +119,12 @@ struct machdep_calls {
         /* Interface for platform error logging */
         void            (*log_error)(char *buf, unsigned int err_type, int fatal);
 
+        unsigned char   (*nvram_read_val)(int addr);
+        void            (*nvram_write_val)(int addr, unsigned char val);
         ssize_t         (*nvram_write)(char *buf, size_t count, loff_t *index);
         ssize_t         (*nvram_read)(char *buf, size_t count, loff_t *index);  
         ssize_t         (*nvram_size)(void);            
-        int             (*nvram_sync)(void);
+        void            (*nvram_sync)(void);
 
         /* Exception handlers */
         void            (*system_reset_exception)(struct pt_regs *regs);
@@ -130,19 +144,97 @@ struct machdep_calls {
         
         /* Get access protection for /dev/mem */
         pgprot_t        (*phys_mem_access_prot)(struct file *file,
-                                                unsigned long offset,
+                                                unsigned long pfn,
                                                 unsigned long size,
                                                 pgprot_t vma_prot);
 
         /* Idle loop for this platform, leave empty for default idle loop */
-        int             (*idle_loop)(void);
+        void            (*idle_loop)(void);
 
-        /* Function to enable pmcs for this platform, called once per cpu. */
+        /* Function to enable performance monitor counters for this
+           platform, called once per cpu. */
         void            (*enable_pmcs)(void);
+
+#ifdef CONFIG_PPC32     /* XXX for now */
+        /* A general init function, called by ppc_init in init/main.c.
+           May be NULL. */
+        void            (*init)(void);
+
+        void            (*idle)(void);
+        void            (*power_save)(void);
+
+        void            (*heartbeat)(void);
+        unsigned long   heartbeat_reset;
+        unsigned long   heartbeat_count;
+
+        void            (*setup_io_mappings)(void);
+
+        void            (*early_serial_map)(void);
+        void            (*kgdb_map_scc)(void);
+
+        /*
+         * optional PCI "hooks"
+         */
+
+        /* Called after PPC generic resource fixup to perform
+           machine specific fixups */
+        void (*pcibios_fixup_resources)(struct pci_dev *);
+
+        /* Called for each PCI bus in the system when it's probed */
+        void (*pcibios_fixup_bus)(struct pci_bus *);
+
+        /* Called when pci_enable_device() is called (initial=0) or
+         * when a device with no assigned resource is found (initial=1).
+         * Returns 0 to allow assignment/enabling of the device. */
+        int  (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
+
+        /* For interrupt routing */
+        unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
+        int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
+
+        /* Called in indirect_* to avoid touching devices */
+        int (*pci_exclude_device)(unsigned char, unsigned char);
+
+        /* Called at then very end of pcibios_init() */
+        void (*pcibios_after_init)(void);
+
+        /* this is for modules, since _machine can be a define -- Cort */
+        int ppc_machine;
+
+#ifdef CONFIG_KEXEC
+        /* Called to shutdown machine specific hardware not already controlled
+         * by other drivers.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_shutdown)(void);
+
+        /* Called to do the minimal shutdown needed to run a kexec'd kernel
+         * to run successfully.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_crash_shutdown)(void);
+
+        /* Called to do what every setup is needed on image and the
+         * reboot code buffer. Returns 0 on success.
+         * Provide your own (maybe dummy) implementation if your platform
+         * claims to support kexec.
+         */
+        int (*machine_kexec_prepare)(struct kimage *image);
+
+        /* Called to handle any machine specific cleanup on image */
+        void (*machine_kexec_cleanup)(struct kimage *image);
+
+        /* Called to perform the _real_ kexec.
+         * Do NOT allocate memory or fail here. We are past the point of
+         * no return.
+         */
+        void (*machine_kexec)(struct kimage *image);
+#endif /* CONFIG_KEXEC */
+#endif /* CONFIG_PPC32 */
 };
 
-extern int default_idle(void);
-extern int native_idle(void);
+extern void default_idle(void);
+extern void native_idle(void);
 
 extern struct machdep_calls ppc_md;
 extern char cmd_line[COMMAND_LINE_SIZE];
@@ -162,6 +254,13 @@ extern sys_ctrler_t sys_ctrler;
 
 #endif /* CONFIG_PPC_PMAC */
 
+extern void setup_pci_ptrs(void);
+
+#ifdef CONFIG_SMP
+/* Poor default implementations */
+extern void __devinit smp_generic_give_timebase(void);
+extern void __devinit smp_generic_take_timebase(void);
+#endif /* CONFIG_SMP */
 
 
 /* Functions to produce codes on the leds.
@@ -181,5 +280,5 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
                 ppc_md.log_error(buf, err_type, fatal);
 }
 
-#endif /* _PPC64_MACHDEP_H */
 #endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/include/asm-ppc/macio.h b/include/asm-powerpc/macio.h
index b553dd4b139e..b553dd4b139e 100644
--- a/include/asm-ppc/macio.h
+++ b/include/asm-powerpc/macio.h
diff --git a/include/asm-ppc/mediabay.h b/include/asm-powerpc/mediabay.h
index 9daa3252d7b6..9daa3252d7b6 100644
--- a/include/asm-ppc/mediabay.h
+++ b/include/asm-powerpc/mediabay.h
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
new file mode 100644
index 000000000000..7083d1f74260
--- /dev/null
+++ b/include/asm-powerpc/mpic.h
@@ -0,0 +1,287 @@
+#ifndef _ASM_POWERPC_MPIC_H
+#define _ASM_POWERPC_MPIC_H
+
+#include <linux/irq.h>
+
+/*
+ * Global registers
+ */
+
+#define MPIC_GREG_BASE                  0x01000
+
+#define MPIC_GREG_FEATURE_0             0x00000
+#define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
+#define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
+#define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
+#define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
+#define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
+#define MPIC_GREG_FEATURE_1             0x00010
+#define MPIC_GREG_GLOBAL_CONF_0         0x00020
+#define         MPIC_GREG_GCONF_RESET                   0x80000000
+#define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
+#define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
+#define MPIC_GREG_GLOBAL_CONF_1         0x00030
+#define MPIC_GREG_VENDOR_0              0x00040
+#define MPIC_GREG_VENDOR_1              0x00050
+#define MPIC_GREG_VENDOR_2              0x00060
+#define MPIC_GREG_VENDOR_3              0x00070
+#define MPIC_GREG_VENDOR_ID             0x00080
+#define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
+#define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
+#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
+#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
+#define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
+#define MPIC_GREG_PROCESSOR_INIT        0x00090
+#define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
+#define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
+#define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
+#define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
+#define MPIC_GREG_SPURIOUS              0x000e0
+#define MPIC_GREG_TIMER_FREQ            0x000f0
+
+/*
+ *
+ * Timer registers
+ */
+#define MPIC_TIMER_BASE                 0x01100
+#define MPIC_TIMER_STRIDE               0x40
+
+#define MPIC_TIMER_CURRENT_CNT          0x00000
+#define MPIC_TIMER_BASE_CNT             0x00010
+#define MPIC_TIMER_VECTOR_PRI           0x00020
+#define MPIC_TIMER_DESTINATION          0x00030
+
+/*
+ * Per-Processor registers
+ */
+
+#define MPIC_CPU_THISBASE               0x00000
+#define MPIC_CPU_BASE                   0x20000
+#define MPIC_CPU_STRIDE                 0x01000
+
+#define MPIC_CPU_IPI_DISPATCH_0         0x00040
+#define MPIC_CPU_IPI_DISPATCH_1         0x00050
+#define MPIC_CPU_IPI_DISPATCH_2         0x00060
+#define MPIC_CPU_IPI_DISPATCH_3         0x00070
+#define MPIC_CPU_CURRENT_TASK_PRI       0x00080
+#define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
+#define MPIC_CPU_WHOAMI                 0x00090
+#define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
+#define MPIC_CPU_INTACK                 0x000a0
+#define MPIC_CPU_EOI                    0x000b0
+
+/*
+ * Per-source registers
+ */
+
+#define MPIC_IRQ_BASE                   0x10000
+#define MPIC_IRQ_STRIDE                 0x00020
+#define MPIC_IRQ_VECTOR_PRI             0x00000
+#define         MPIC_VECPRI_MASK                        0x80000000
+#define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
+#define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
+#define         MPIC_VECPRI_PRIORITY_SHIFT              16
+#define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
+#define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
+#define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
+#define         MPIC_VECPRI_POLARITY_MASK               0x00800000
+#define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
+#define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
+#define         MPIC_VECPRI_SENSE_MASK                  0x00400000
+#define MPIC_IRQ_DESTINATION            0x00010
+
+#define MPIC_MAX_IRQ_SOURCES    2048
+#define MPIC_MAX_CPUS           32
+#define MPIC_MAX_ISU            32
+
+/*
+ * Special vector numbers (internal use only)
+ */
+#define MPIC_VEC_SPURRIOUS      255
+#define MPIC_VEC_IPI_3          254
+#define MPIC_VEC_IPI_2          253
+#define MPIC_VEC_IPI_1          252
+#define MPIC_VEC_IPI_0          251
+
+/* unused */
+#define MPIC_VEC_TIMER_3        250
+#define MPIC_VEC_TIMER_2        249
+#define MPIC_VEC_TIMER_1        248
+#define MPIC_VEC_TIMER_0        247
+
+/* Type definition of the cascade handler */
+typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
+
+#ifdef CONFIG_MPIC_BROKEN_U3
+/* Fixup table entry */
+struct mpic_irq_fixup
+{
+        u8 __iomem      *base;
+        unsigned int   irq;
+};
+#endif /* CONFIG_MPIC_BROKEN_U3 */
+
+
+/* The instance data of a given MPIC */
+struct mpic
+{
+        /* The "linux" controller struct */
+        hw_irq_controller       hc_irq;
+#ifdef CONFIG_SMP
+        hw_irq_controller       hc_ipi;
+#endif
+        const char              *name;
+        /* Flags */
+        unsigned int            flags;
+        /* How many irq sources in a given ISU */
+        unsigned int            isu_size;
+        unsigned int            isu_shift;
+        unsigned int            isu_mask;
+        /* Offset of irq vector numbers */
+        unsigned int            irq_offset;     
+        unsigned int            irq_count;
+        /* Offset of ipi vector numbers */
+        unsigned int            ipi_offset;
+        /* Number of sources */
+        unsigned int            num_sources;
+        /* Number of CPUs */
+        unsigned int            num_cpus;
+        /* cascade handler */
+        mpic_cascade_t          cascade;
+        void                    *cascade_data;
+        unsigned int            cascade_vec;
+        /* senses array */
+        unsigned char           *senses;
+        unsigned int            senses_count;
+
+#ifdef CONFIG_MPIC_BROKEN_U3
+        /* The fixup table */
+        struct mpic_irq_fixup   *fixups;
+        spinlock_t              fixup_lock;
+#endif
+
+        /* The various ioremap'ed bases */
+        volatile u32 __iomem    *gregs;
+        volatile u32 __iomem    *tmregs;
+        volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
+        volatile u32 __iomem    *isus[MPIC_MAX_ISU];
+
+        /* link */
+        struct mpic             *next;
+};
+
+/* This is the primary controller, only that one has IPIs and
+ * has afinity control. A non-primary MPIC always uses CPU0
+ * registers only
+ */
+#define MPIC_PRIMARY                    0x00000001
+/* Set this for a big-endian MPIC */
+#define MPIC_BIG_ENDIAN                 0x00000002
+/* Broken U3 MPIC */
+#define MPIC_BROKEN_U3                  0x00000004
+/* Broken IPI registers (autodetected) */
+#define MPIC_BROKEN_IPI                 0x00000008
+/* MPIC wants a reset */
+#define MPIC_WANTS_RESET                0x00000010
+
+/* Allocate the controller structure and setup the linux irq descs
+ * for the range if interrupts passed in. No HW initialization is
+ * actually performed.
+ * 
+ * @phys_addr:  physial base address of the MPIC
+ * @flags:      flags, see constants above
+ * @isu_size:   number of interrupts in an ISU. Use 0 to use a
+ *              standard ISU-less setup (aka powermac)
+ * @irq_offset: first irq number to assign to this mpic
+ * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
+ *              to match the number of sources
+ * @ipi_offset: first irq number to assign to this mpic IPI sources,
+ *              used only on primary mpic
+ * @senses:     array of sense values
+ * @senses_num: number of entries in the array
+ *
+ * Note about the sense array. If none is passed, all interrupts are
+ * setup to be level negative unless MPIC_BROKEN_U3 is set in which
+ * case they are edge positive (and the array is ignored anyway).
+ * The values in the array start at the first source of the MPIC,
+ * that is senses[0] correspond to linux irq "irq_offset".
+ */
+extern struct mpic *mpic_alloc(unsigned long phys_addr,
+                               unsigned int flags,
+                               unsigned int isu_size,
+                               unsigned int irq_offset,
+                               unsigned int irq_count,
+                               unsigned int ipi_offset,
+                               unsigned char *senses,
+                               unsigned int senses_num,
+                               const char *name);
+
+/* Assign ISUs, to call before mpic_init()
+ *
+ * @mpic:       controller structure as returned by mpic_alloc()
+ * @isu_num:    ISU number
+ * @phys_addr:  physical address of the ISU
+ */
+extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
+                            unsigned long phys_addr);
+
+/* Initialize the controller. After this has been called, none of the above
+ * should be called again for this mpic
+ */
+extern void mpic_init(struct mpic *mpic);
+
+/* Setup a cascade. Currently, only one cascade is supported this
+ * way, though you can always do a normal request_irq() and add
+ * other cascades this way. You should call this _after_ having
+ * added all the ISUs
+ *
+ * @irq_no:     "linux" irq number of the cascade (that is offset'ed vector)
+ * @handler:    cascade handler function
+ */
+extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
+                               void *data);
+
+/*
+ * All of the following functions must only be used after the
+ * ISUs have been assigned and the controller fully initialized
+ * with mpic_init()
+ */
+
+
+/* Change/Read the priority of an interrupt. Default is 8 for irqs and
+ * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
+ * IPI number is then the offset'ed (linux irq number mapped to the IPI)
+ */
+extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
+extern unsigned int mpic_irq_get_priority(unsigned int irq);
+
+/* Setup a non-boot CPU */
+extern void mpic_setup_this_cpu(void);
+
+/* Clean up for kexec (or cpu offline or ...) */
+extern void mpic_teardown_this_cpu(int secondary);
+
+/* Get the current cpu priority for this cpu (0..15) */
+extern int mpic_cpu_get_priority(void);
+
+/* Set the current cpu priority for this cpu */
+extern void mpic_cpu_set_priority(int prio);
+
+/* Request IPIs on primary mpic */
+extern void mpic_request_ipis(void);
+
+/* Send an IPI (non offseted number 0..3) */
+extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
+
+/* Send a message (IPI) to a given target (cpu number or MSG_*) */
+void smp_mpic_message_pass(int target, int msg);
+
+/* Fetch interrupt from a given mpic */
+extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
+/* This one gets to the primary mpic */
+extern int mpic_get_irq(struct pt_regs *regs);
+
+/* global mpic for pSeries */
+extern struct mpic *pSeries_mpic;
+
+#endif  /* _ASM_POWERPC_MPIC_H */
diff --git a/include/asm-ppc/of_device.h b/include/asm-powerpc/of_device.h
index 575bce418f80..ddb16aae0bd6 100644
--- a/include/asm-ppc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -1,5 +1,5 @@
-#ifndef __OF_DEVICE_H__
-#define __OF_DEVICE_H__
+#ifndef _ASM_POWERPC_OF_DEVICE_H
+#define _ASM_POWERPC_OF_DEVICE_H
 
 #include <linux/device.h>
 #include <linux/mod_devicetable.h>
@@ -61,5 +61,4 @@ extern struct of_device *of_platform_device_create(struct device_node *np,
                                                    struct device *parent);
 extern void of_release_dev(struct device *dev);
 
-#endif /* __OF_DEVICE_H__ */
-
+#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/include/asm-ppc/ohare.h b/include/asm-powerpc/ohare.h
index 023b59772231..023b59772231 100644
--- a/include/asm-ppc/ohare.h
+++ b/include/asm-powerpc/ohare.h
diff --git a/include/asm-ppc64/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
index b04f1dfb1421..8013cd273ced 100644
--- a/include/asm-ppc64/oprofile_impl.h
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -9,39 +9,49 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#ifndef OP_IMPL_H
-#define OP_IMPL_H 1
+#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
+#define _ASM_POWERPC_OPROFILE_IMPL_H
 
 #define OP_MAX_COUNTER 8
 
 /* Per-counter configuration as set via oprofilefs.  */
 struct op_counter_config {
+#ifdef __powerpc64__
         unsigned long valid;
+#endif
         unsigned long enabled;
         unsigned long event;
         unsigned long count;
         unsigned long kernel;
+#ifdef __powerpc64__
         /* We dont support per counter user/kernel selection */
+#endif
         unsigned long user;
         unsigned long unit_mask;
 };
 
 /* System-wide configuration as set via oprofilefs.  */
 struct op_system_config {
+#ifdef __powerpc64__
         unsigned long mmcr0;
         unsigned long mmcr1;
         unsigned long mmcra;
+#endif
         unsigned long enable_kernel;
         unsigned long enable_user;
+#ifdef __powerpc64__
         unsigned long backtrace_spinlocks;
+#endif
 };
 
 /* Per-arch configuration */
-struct op_ppc64_model {
+struct op_powerpc_model {
         void (*reg_setup) (struct op_counter_config *,
                            struct op_system_config *,
                            int num_counters);
+#ifdef __powerpc64__
         void (*cpu_setup) (void *);
+#endif
         void (*start) (struct op_counter_config *);
         void (*stop) (void);
         void (*handle_interrupt) (struct pt_regs *,
@@ -49,8 +59,9 @@ struct op_ppc64_model {
         int num_counters;
 };
 
-extern struct op_ppc64_model op_model_rs64;
-extern struct op_ppc64_model op_model_power4;
+#ifdef __powerpc64__
+extern struct op_powerpc_model op_model_rs64;
+extern struct op_powerpc_model op_model_power4;
 
 static inline unsigned int ctr_read(unsigned int i)
 {
@@ -107,5 +118,6 @@ static inline void ctr_write(unsigned int i, unsigned int val)
                 break;
         }
 }
+#endif /* __powerpc64__ */
 
-#endif
+#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/include/asm-ppc64/pSeries_reconfig.h b/include/asm-powerpc/pSeries_reconfig.h
index c0db1ea7f7d1..c0db1ea7f7d1 100644
--- a/include/asm-ppc64/pSeries_reconfig.h
+++ b/include/asm-powerpc/pSeries_reconfig.h
diff --git a/include/asm-ppc/parport.h b/include/asm-powerpc/parport.h
index 11f96d3de5b6..d86b410a6f8b 100644
--- a/include/asm-ppc/parport.h
+++ b/include/asm-powerpc/parport.h
@@ -6,8 +6,8 @@
  * This file should only be included by drivers/parport/parport_pc.c.
  */
 
-#ifndef _ASM_PPC_PARPORT_H
-#define _ASM_PPC_PARPORT_H
+#ifndef _ASM_POWERPC_PARPORT_H
+#define _ASM_POWERPC_PARPORT_H
 
 static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
 static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
@@ -15,4 +15,4 @@ static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
         return parport_pc_find_isa_ports (autoirq, autodma);
 }
 
-#endif /* !(_ASM_PPC_PARPORT_H) */
+#endif /* !(_ASM_POWERPC_PARPORT_H) */
diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
index e9683bcff19b..e9683bcff19b 100644
--- a/include/asm-ppc/pmac_feature.h
+++ b/include/asm-powerpc/pmac_feature.h
diff --git a/include/asm-ppc/pmac_low_i2c.h b/include/asm-powerpc/pmac_low_i2c.h
index 809a5963d5e7..809a5963d5e7 100644
--- a/include/asm-ppc/pmac_low_i2c.h
+++ b/include/asm-powerpc/pmac_low_i2c.h
diff --git a/include/asm-ppc64/pmc.h b/include/asm-powerpc/pmc.h
index d1d297dbccfe..2f3c3fc2b796 100644
--- a/include/asm-ppc64/pmc.h
+++ b/include/asm-powerpc/pmc.h
@@ -16,8 +16,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
-#ifndef _PPC64_PMC_H
-#define _PPC64_PMC_H
+#ifndef _POWERPC_PMC_H
+#define _POWERPC_PMC_H
 
 #include <asm/ptrace.h>
 
@@ -26,6 +26,21 @@ typedef void (*perf_irq_t)(struct pt_regs *);
 int reserve_pmc_hardware(perf_irq_t new_perf_irq);
 void release_pmc_hardware(void);
 
+#ifdef CONFIG_PPC64
 void power4_enable_pmcs(void);
+#endif
 
-#endif /* _PPC64_PMC_H */
+#ifdef CONFIG_FSL_BOOKE
+void init_pmc_stop(int ctr);
+void set_pmc_event(int ctr, int event);
+void set_pmc_user_kernel(int ctr, int user, int kernel);
+void set_pmc_marked(int ctr, int mark0, int mark1);
+void pmc_start_ctr(int ctr, int enable);
+void pmc_start_ctrs(int enable);
+void pmc_stop_ctrs(void);
+void dump_pmcs(void);
+
+extern struct op_powerpc_model op_model_fsl_booke;
+#endif
+
+#endif /* _POWERPC_PMC_H */
diff --git a/include/asm-ppc64/posix_types.h b/include/asm-powerpc/posix_types.h
index 516de7201b5d..c6391077224f 100644
--- a/include/asm-ppc64/posix_types.h
+++ b/include/asm-powerpc/posix_types.h
@@ -1,44 +1,54 @@
-#ifndef _PPC64_POSIX_TYPES_H
-#define _PPC64_POSIX_TYPES_H
+#ifndef _ASM_POWERPC_POSIX_TYPES_H
+#define _ASM_POWERPC_POSIX_TYPES_H
 
 /*
  * This file is generally used by user-level software, so you need to
  * be a little careful about namespace pollution etc.  Also, we cannot
  * assume GCC is being used.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
  */
 
 typedef unsigned long   __kernel_ino_t;
-typedef unsigned long   __kernel_nlink_t;
 typedef unsigned int    __kernel_mode_t;
 typedef long            __kernel_off_t;
-typedef long long       __kernel_loff_t;
 typedef int             __kernel_pid_t;
-typedef int             __kernel_ipc_pid_t;
 typedef unsigned int    __kernel_uid_t;
 typedef unsigned int    __kernel_gid_t;
-typedef unsigned long   __kernel_size_t;
-typedef long            __kernel_ssize_t;
 typedef long            __kernel_ptrdiff_t;
 typedef long            __kernel_time_t;
+typedef long            __kernel_clock_t;
 typedef int             __kernel_timer_t;
 typedef int             __kernel_clockid_t;
 typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
 typedef int             __kernel_daddr_t;
 typedef char *          __kernel_caddr_t;
 typedef unsigned short  __kernel_uid16_t;
 typedef unsigned short  __kernel_gid16_t;
 typedef unsigned int    __kernel_uid32_t;
 typedef unsigned int    __kernel_gid32_t;
-
 typedef unsigned int    __kernel_old_uid_t;
 typedef unsigned int    __kernel_old_gid_t;
+
+#ifdef __powerpc64__
+typedef unsigned long   __kernel_nlink_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
 typedef unsigned long   __kernel_old_dev_t;
+#else
+typedef unsigned short  __kernel_nlink_t;
+typedef short           __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef unsigned int    __kernel_old_dev_t;
+#endif
+
+#ifdef __powerpc64__
+typedef long long       __kernel_loff_t;
+#else
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+#endif
 
 typedef struct {
         int     val[2];
@@ -116,4 +126,4 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *p)
 
 #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
 #endif /* __GNUC__ */
-#endif /* _PPC64_POSIX_TYPES_H */
+#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
new file mode 100644
index 000000000000..a88728fba8f6
--- /dev/null
+++ b/include/asm-powerpc/ppc-pci.h
@@ -0,0 +1,54 @@
+/*
+ * c 2001 PPC 64 Team, IBM Corp
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_PPC_PCI_H
+#define _ASM_POWERPC_PPC_PCI_H
+
+#include <linux/pci.h>
+#include <asm/pci-bridge.h>
+
+extern unsigned long isa_io_base;
+
+extern void pci_setup_pci_controller(struct pci_controller *hose);
+extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
+extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
+
+
+extern struct list_head hose_list;
+extern int global_phb_number;
+
+extern unsigned long find_and_init_phbs(void);
+
+extern struct pci_dev *ppc64_isabridge_dev;     /* may be NULL if no ISA bus */
+
+/* PCI device_node operations */
+struct device_node;
+typedef void *(*traverse_func)(struct device_node *me, void *data);
+void *traverse_pci_devices(struct device_node *start, traverse_func pre,
+                void *data);
+
+void pci_devs_phb_init(void);
+void pci_devs_phb_init_dynamic(struct pci_controller *phb);
+
+/* PCI address cache management routines */
+void pci_addr_cache_insert_device(struct pci_dev *dev);
+void pci_addr_cache_remove_device(struct pci_dev *dev);
+
+/* From rtas_pci.h */
+void init_pci_config_tokens (void);
+unsigned long get_phb_buid (struct device_node *);
+
+/* From pSeries_pci.h */
+extern void pSeries_final_fixup(void);
+extern void pSeries_irq_bus_setup(struct pci_bus *bus);
+
+extern unsigned long pci_probe_only;
+extern unsigned long pci_assign_all_buses;
+extern int pci_read_irq_line(struct pci_dev *pci_dev);
+
+#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index bb53e2def363..f99f2af82ca5 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -1,38 +1,42 @@
 /*
- * include/asm-ppc/ppc_asm.h
- *
- * Definitions used by various bits of low-level assembly code on PowerPC.
- *
  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
  */
+#ifndef _ASM_POWERPC_PPC_ASM_H
+#define _ASM_POWERPC_PPC_ASM_H
 
+#include <linux/stringify.h>
 #include <linux/config.h>
 
+#ifdef __ASSEMBLY__
+
 /*
  * Macros for storing registers into and loading registers from
  * exception frames.
  */
+#ifdef __powerpc64__
+#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
+#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
+#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
+#else
 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
+#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
+#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
+                                SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
+                                REST_10GPRS(22, base)
+#endif
+
+
 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
 
-#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
-                                SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
-                                REST_10GPRS(22, base)
-
 #define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
@@ -47,32 +51,170 @@
 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 
 #define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
-#define SAVE_2VR(n,b,base)      SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VR(n,b,base)      SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
-#define SAVE_8VR(n,b,base)      SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
-#define SAVE_16VR(n,b,base)     SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
-#define SAVE_32VR(n,b,base)     SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
+#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
+#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
+#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
+#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
+#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
 #define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VR(n,b,base)      REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VR(n,b,base)      REST_2VR(n,b,base); REST_2VR(n+2,b,base)
-#define REST_8VR(n,b,base)      REST_4VR(n,b,base); REST_4VR(n+4,b,base)
-#define REST_16VR(n,b,base)     REST_8VR(n,b,base); REST_8VR(n+8,b,base)
-#define REST_32VR(n,b,base)     REST_16VR(n,b,base); REST_16VR(n+16,b,base)
+#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
+#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
+#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
+#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
+#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 
 #define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
-#define SAVE_2EVR(n,s,base)     SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
-#define SAVE_4EVR(n,s,base)     SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
-#define SAVE_8EVR(n,s,base)     SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
-#define SAVE_16EVR(n,s,base)    SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
-#define SAVE_32EVR(n,s,base)    SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
-
+#define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
+#define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
+#define SAVE_8EVRS(n,s,base)    SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
+#define SAVE_16EVRS(n,s,base)   SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
+#define SAVE_32EVRS(n,s,base)   SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
 #define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
-#define REST_2EVR(n,s,base)     REST_EVR(n,s,base); REST_EVR(n+1,s,base)
-#define REST_4EVR(n,s,base)     REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
-#define REST_8EVR(n,s,base)     REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
-#define REST_16EVR(n,s,base)    REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
-#define REST_32EVR(n,s,base)    REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
+#define REST_2EVRS(n,s,base)    REST_EVR(n,s,base); REST_EVR(n+1,s,base)
+#define REST_4EVRS(n,s,base)    REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
+#define REST_8EVRS(n,s,base)    REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
+#define REST_16EVRS(n,s,base)   REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
+#define REST_32EVRS(n,s,base)   REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
+
+/* Macros to adjust thread priority for hardware multithreading */
+#define HMT_VERY_LOW    or      31,31,31        # very low priority
+#define HMT_LOW         or      1,1,1
+#define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
+#define HMT_MEDIUM      or      2,2,2
+#define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
+#define HMT_HIGH        or      3,3,3
+
+/* handle instructions that older assemblers may not know */
+#define RFCI            .long 0x4c000066        /* rfci instruction */
+#define RFDI            .long 0x4c00004e        /* rfdi instruction */
+#define RFMCI           .long 0x4c00004c        /* rfmci instruction */
+
+#ifdef CONFIG_PPC64
+
+#define XGLUE(a,b) a##b
+#define GLUE(a,b) XGLUE(a,b)
+
+#define _GLOBAL(name) \
+        .section ".text"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _KPROBE(name) \
+        .section ".kprobes.text","a"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _STATIC(name) \
+        .section ".text"; \
+        .align 2 ; \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#else /* 32-bit */
+
+#define _GLOBAL(n)      \
+        .text;          \
+        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
+        .globl n;       \
+n:
+
+#define _KPROBE(n)      \
+        .section ".kprobes.text","a";   \
+        .globl  n;      \
+n:
+
+#endif
+
+/* 
+ * LOADADDR( rn, name )
+ *   loads the address of 'name' into 'rn'
+ *
+ * LOADBASE( rn, name )
+ *   loads the address (possibly without the low 16 bits) of 'name' into 'rn'
+ *   suitable for base+disp addressing
+ */
+#ifdef __powerpc64__
+#define LOADADDR(rn,name) \
+        lis     rn,name##@highest;      \
+        ori     rn,rn,name##@higher;    \
+        rldicr  rn,rn,32,31;            \
+        oris    rn,rn,name##@h;         \
+        ori     rn,rn,name##@l
+
+#define LOADBASE(rn,name)               \
+        ld      rn,name@got(r2)
+
+#define OFF(name)       0
+
+#define SET_REG_TO_CONST(reg, value)                    \
+        lis     reg,(((value)>>48)&0xFFFF);             \
+        ori     reg,reg,(((value)>>32)&0xFFFF);         \
+        rldicr  reg,reg,32,31;                          \
+        oris    reg,reg,(((value)>>16)&0xFFFF);         \
+        ori     reg,reg,((value)&0xFFFF);
+
+#define SET_REG_TO_LABEL(reg, label)                    \
+        lis     reg,(label)@highest;                    \
+        ori     reg,reg,(label)@higher;                 \
+        rldicr  reg,reg,32,31;                          \
+        oris    reg,reg,(label)@h;                      \
+        ori     reg,reg,(label)@l;
+
+/* operations for longs and pointers */
+#define LDL     ld
+#define STL     std
+#define CMPI    cmpdi
+#define SZL     8
+
+/* offsets for stack frame layout */
+#define LRSAVE  16
+
+#else /* 32-bit */
+#define LOADADDR(rn,name) \
+        lis     rn,name@ha;     \
+        addi    rn,rn,name@l
+
+#define LOADBASE(rn,name)       \
+        lis     rn,name@ha
+
+#define OFF(name)       name@l
+
+/* operations for longs and pointers */
+#define LDL     lwz
+#define STL     stw
+#define CMPI    cmpwi
+#define SZL     4
+
+/* offsets for stack frame layout */
+#define LRSAVE  4
+
+#endif
 
+/* various errata or part fixups */
 #ifdef CONFIG_PPC601_SYNC_FIX
 #define SYNC                            \
 BEGIN_FTR_SECTION                       \
@@ -93,6 +235,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
 #define ISYNC_601
 #endif
 
+
 #ifndef CONFIG_SMP
 #define TLBSYNC
 #else /* CONFIG_SMP */
@@ -104,6 +247,7 @@ BEGIN_FTR_SECTION			\
 END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #endif
 
+        
 /*
  * This instruction is not implemented on the PPC 603 or 601; however, on
  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
@@ -121,18 +265,52 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
         bdnz    0b
 #endif
 
-#ifdef CONFIG_BOOKE
+
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb)     dcbt    ra, rb;
+#define PPC405_ERR77_SYNC       sync;
+#else
+#define PPC405_ERR77(ra,rb)
+#define PPC405_ERR77_SYNC
+#endif
+
+
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
+
+#if defined(CONFIG_BOOKE)
+#define toreal(rd)
+#define fromreal(rd)
+
 #define tophys(rd,rs)                           \
         addis   rd,rs,0
 
 #define tovirt(rd,rs)                           \
         addis   rd,rs,0
 
-#else  /* CONFIG_BOOKE */
+#elif defined(CONFIG_PPC64)
+#define toreal(rd)              /* we can access c000... in real mode */
+#define fromreal(rd)
+
+#define tophys(rd,rs)                           \
+        clrldi  rd,rs,2
+
+#define tovirt(rd,rs)                           \
+        rotldi  rd,rs,16;                       \
+        ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
+        rotldi  rd,rd,48
+#else
 /*
  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
  * physical base address of RAM at compile time.
  */
+#define toreal(rd)      tophys(rd,rd)
+#define fromreal(rd)    tovirt(rd,rd)
+
 #define tophys(rd,rs)                           \
 0:      addis   rd,rs,-KERNELBASE@h;            \
         .section ".vtop_fixup","aw";            \
@@ -146,22 +324,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
         .align  1;                              \
         .long   0b;                             \
         .previous
-#endif  /* CONFIG_BOOKE */
+#endif
 
-/*
- * On 64-bit cpus, we use the rfid instruction instead of rfi, but
- * we then have to make sure we preserve the top 32 bits except for
- * the 64-bit mode bit, which we clear.
- */
-#ifdef CONFIG_PPC64BRIDGE
-#define FIX_SRR1(ra, rb)        \
-        mr      rb,ra;          \
-        mfmsr   ra;             \
-        clrldi  ra,ra,1;                /* turn off 64-bit mode */ \
-        rldimi  ra,rb,0,32
-#define RFI             .long   0x4c000024      /* rfid instruction */
-#define MTMSRD(r)       .long   (0x7c000164 + ((r) << 21))      /* mtmsrd */
-#define CLR_TOP32(r)    rlwinm  (r),(r),0,0,31  /* clear top 32 bits */
+#ifdef CONFIG_PPC64
+#define RFI             rfid
+#define MTMSRD(r)       mtmsrd  r
 
 #else
 #define FIX_SRR1(ra, rb)
@@ -172,24 +339,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #endif
 #define MTMSRD(r)       mtmsr   r
 #define CLR_TOP32(r)
-#endif /* CONFIG_PPC64BRIDGE */
-
-#define RFCI            .long 0x4c000066        /* rfci instruction */
-#define RFDI            .long 0x4c00004e        /* rfdi instruction */
-#define RFMCI           .long 0x4c00004c        /* rfmci instruction */
-
-#ifdef CONFIG_IBM405_ERR77
-#define PPC405_ERR77(ra,rb)     dcbt    ra, rb;
-#define PPC405_ERR77_SYNC       sync;
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-
-#ifdef CONFIG_IBM440EP_ERR42
-#define PPC440EP_ERR42 isync
-#else
-#define PPC440EP_ERR42
 #endif
 
 /* The boring bits... */
@@ -277,6 +426,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define fr30    30
 #define fr31    31
 
+/* AltiVec Registers (VPRs) */
+
 #define vr0     0
 #define vr1     1
 #define vr2     2
@@ -310,6 +461,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define vr30    30
 #define vr31    31
 
+/* SPE Registers (EVPRs) */
+
 #define evr0    0
 #define evr1    1
 #define evr2    2
@@ -348,3 +501,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define N_RSYM  64
 #define N_SLINE 68
 #define N_SO    100
+
+#define ASM_CONST(x) x
+#else
+  #define __ASM_CONST(x) x##UL
+  #define ASM_CONST(x) __ASM_CONST(x)
+#endif /*  __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-ppc/processor.h b/include/asm-powerpc/processor.h
index b05b5d9cae20..eee954a001fd 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -1,21 +1,28 @@
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_PROCESSOR_H
-#define __ASM_PPC_PROCESSOR_H
+#ifndef _ASM_POWERPC_PROCESSOR_H
+#define _ASM_POWERPC_PROCESSOR_H
 
 /*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
+ * Copyright (C) 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
  */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
 #include <linux/config.h>
-#include <linux/stringify.h>
+#include <asm/reg.h>
 
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/mpc8xx.h>
-#include <asm/reg.h>
+#ifdef CONFIG_PPC64
+#include <asm/systemcfg.h>
+#endif
 
+#ifdef CONFIG_PPC32
+/* 32-bit platform types */
 /* We only need to define a new _MACH_xxx for machines which are part of
  * a configuration which supports more than one type of different machine.
  * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac.
@@ -36,20 +43,6 @@
 #define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
 #define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
 
-#define _GLOBAL(n)\
-        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
-        .globl n;\
-n:
-
-/*
- * this is the minimum allowable io space due to the location
- * of the io areas on prep (first one at 0x80000000) but
- * as soon as I get around to remapping the io areas with the BATs
- * to match the mac we can raise this. -- Cort
- */
-#define TASK_SIZE       (CONFIG_TASK_SIZE)
-
-#ifndef __ASSEMBLY__
 #ifdef CONFIG_PPC_MULTIPLATFORM
 extern int _machine;
 
@@ -67,17 +60,49 @@ extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 #else
 #define _machine 0
 #endif /* CONFIG_PPC_MULTIPLATFORM */
+#endif /* CONFIG_PPC32 */
+
+#ifdef CONFIG_PPC64
+/* Platforms supported by PPC64 */
+#define PLATFORM_PSERIES      0x0100
+#define PLATFORM_PSERIES_LPAR 0x0101
+#define PLATFORM_ISERIES_LPAR 0x0201
+#define PLATFORM_LPAR         0x0001
+#define PLATFORM_POWERMAC     0x0400
+#define PLATFORM_MAPLE        0x0500
+#define PLATFORM_BPA          0x1000
+
+/* Compatibility with drivers coming from PPC32 world */
+#define _machine        (systemcfg->platform)
+#define _MACH_Pmac      PLATFORM_POWERMAC
+#endif
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+/* Macros for adjusting thread priority (hardware multi-threading) */
+#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
+#define HMT_low()        asm volatile("or 1,1,1      # low priority")
+#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
+#define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
+#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
+#define HMT_high()       asm volatile("or 3,3,3      # high priority")
+
+#ifdef __KERNEL__
+
+extern int have_of;
 
 struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
+void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
 void release_thread(struct task_struct *);
 
 /* Prepare to copy thread state - unlazy all lazy status */
 extern void prepare_to_copy(struct task_struct *tsk);
 
-/*
- * Create a new kernel thread.
- */
+/* Create a new kernel thread. */
 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 
 /* Lazy FPU handling on uni-processor */
@@ -85,10 +110,37 @@ extern struct task_struct *last_task_used_math;
 extern struct task_struct *last_task_used_altivec;
 extern struct task_struct *last_task_used_spe;
 
+#ifdef CONFIG_PPC32
+#define TASK_SIZE       (CONFIG_TASK_SIZE)
+
 /* This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
  */
 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
+#endif
+
+#ifdef CONFIG_PPC64
+/* 64-bit user address space is 44-bits (16TB user VM) */
+#define TASK_SIZE_USER64 (0x0000100000000000UL)
+
+/* 
+ * 32-bit user address space is 4GB - 1 page 
+ * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
+ */
+#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
+
+#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
+                TASK_SIZE_USER32 : TASK_SIZE_USER64)
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
+#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
+
+#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
+                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
+#endif
 
 typedef struct {
         unsigned long seg;
@@ -96,18 +148,32 @@ typedef struct {
 
 struct thread_struct {
         unsigned long   ksp;            /* Kernel stack pointer */
+#ifdef CONFIG_PPC64
+        unsigned long   ksp_vsid;
+#endif
         struct pt_regs  *regs;          /* Pointer to saved register state */
         mm_segment_t    fs;             /* for get_fs() validation */
+#ifdef CONFIG_PPC32
         void            *pgdir;         /* root of page-table tree */
-        int             fpexc_mode;     /* floating-point exception mode */
         signed long     last_syscall;
+#endif
 #if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
         unsigned long   dbcr0;          /* debug control register values */
         unsigned long   dbcr1;
 #endif
         double          fpr[32];        /* Complete floating point set */
-        unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
-        unsigned long   fpscr;          /* Floating point status */
+        struct {                        /* fpr ... fpscr must be contiguous */
+
+                unsigned int pad;
+                unsigned int val;       /* Floating point status */
+        } fpscr;
+        int             fpexc_mode;     /* floating-point exception mode */
+#ifdef CONFIG_PPC64
+        unsigned long   start_tb;       /* Start purr when proc switched in */
+        unsigned long   accum_tb;       /* Total accumilated purr for process */
+        unsigned long   vdso_base;      /* base of the vDSO library */
+#endif
+        unsigned long   dabr;           /* Data address breakpoint register */
 #ifdef CONFIG_ALTIVEC
         /* Complete AltiVec register set */
         vector128       vr[32] __attribute((aligned(16)));
@@ -128,51 +194,58 @@ struct thread_struct {
 
 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 
+
+#ifdef CONFIG_PPC32
 #define INIT_THREAD { \
         .ksp = INIT_SP, \
         .fs = KERNEL_DS, \
         .pgdir = swapper_pg_dir, \
         .fpexc_mode = MSR_FE0 | MSR_FE1, \
 }
+#else
+#define INIT_THREAD  { \
+        .ksp = INIT_SP, \
+        .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
+        .fs = KERNEL_DS, \
+        .fpr = {0}, \
+        .fpscr = { .val = 0, }, \
+        .fpexc_mode = MSR_FE0|MSR_FE1, \
+}
+#endif
 
 /*
  * Return saved PC of a blocked thread. For now, this is the "user" PC
  */
-#define thread_saved_pc(tsk)    \
-        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+#define thread_saved_pc(tsk)    \
+        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 
 unsigned long get_wchan(struct task_struct *p);
 
-#define KSTK_EIP(tsk)   ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-#define KSTK_ESP(tsk)   ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
+#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 
 /* Get/set floating-point exception mode */
-#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
-#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
+#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
+#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 
 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 
-static inline unsigned int __unpack_fe01(unsigned int msr_bits)
+static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 {
         return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 }
 
-static inline unsigned int __pack_fe01(unsigned int fpmode)
+static inline unsigned long __pack_fe01(unsigned int fpmode)
 {
         return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 }
 
-/* in process.c - for early bootup debug -- Cort */
-int ll_printk(const char *, ...);
-void ll_puts(const char *);
-
-/* In misc.c */
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
-
+#ifdef CONFIG_PPC64
+#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
+#else
 #define cpu_relax()     barrier()
+#endif
 
 /*
  * Prefetch macros.
@@ -181,21 +254,28 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #define ARCH_HAS_PREFETCHW
 #define ARCH_HAS_SPINLOCK_PREFETCH
 
-extern inline void prefetch(const void *x)
+static inline void prefetch(const void *x)
 {
-         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
+        if (unlikely(!x))
+                return;
+
+        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 }
 
-extern inline void prefetchw(const void *x)
+static inline void prefetchw(const void *x)
 {
-         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
+        if (unlikely(!x))
+                return;
+
+        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 }
 
 #define spin_lock_prefetch(x)   prefetchw(x)
 
-extern int emulate_altivec(struct pt_regs *regs);
-
-#endif /* !__ASSEMBLY__ */
+#ifdef CONFIG_PPC64
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+#endif
 
-#endif /* __ASM_PPC_PROCESSOR_H */
 #endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
new file mode 100644
index 000000000000..3a0104fa0462
--- /dev/null
+++ b/include/asm-powerpc/prom.h
@@ -0,0 +1,219 @@
+#ifndef _POWERPC_PROM_H
+#define _POWERPC_PROM_H
+#ifdef __KERNEL__
+
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <asm/atomic.h>
+
+/* Definitions used by the flattened device tree */
+#define OF_DT_HEADER            0xd00dfeed      /* marker */
+#define OF_DT_BEGIN_NODE        0x1             /* Start of node, full name */
+#define OF_DT_END_NODE          0x2             /* End node */
+#define OF_DT_PROP              0x3             /* Property: name off, size,
+                                                 * content */
+#define OF_DT_NOP               0x4             /* nop */
+#define OF_DT_END               0x9
+
+#define OF_DT_VERSION           0x10
+
+/*
+ * This is what gets passed to the kernel by prom_init or kexec
+ *
+ * The dt struct contains the device tree structure, full pathes and
+ * property contents. The dt strings contain a separate block with just
+ * the strings for the property names, and is fully page aligned and
+ * self contained in a page, so that it can be kept around by the kernel,
+ * each property name appears only once in this page (cheap compression)
+ *
+ * the mem_rsvmap contains a map of reserved ranges of physical memory,
+ * passing it here instead of in the device-tree itself greatly simplifies
+ * the job of everybody. It's just a list of u64 pairs (base/size) that
+ * ends when size is 0
+ */
+struct boot_param_header
+{
+        u32     magic;                  /* magic word OF_DT_HEADER */
+        u32     totalsize;              /* total size of DT block */
+        u32     off_dt_struct;          /* offset to structure */
+        u32     off_dt_strings;         /* offset to strings */
+        u32     off_mem_rsvmap;         /* offset to memory reserve map */
+        u32     version;                /* format version */
+        u32     last_comp_version;      /* last compatible version */
+        /* version 2 fields below */
+        u32     boot_cpuid_phys;        /* Physical CPU id we're booting on */
+        /* version 3 fields below */
+        u32     dt_strings_size;        /* size of the DT strings block */
+};
+
+
+
+typedef u32 phandle;
+typedef u32 ihandle;
+
+struct address_range {
+        unsigned long space;
+        unsigned long address;
+        unsigned long size;
+};
+
+struct interrupt_info {
+        int     line;
+        int     sense;          /* +ve/-ve logic, edge or level, etc. */
+};
+
+struct pci_address {
+        u32 a_hi;
+        u32 a_mid;
+        u32 a_lo;
+};
+
+struct isa_address {
+        u32 a_hi;
+        u32 a_lo;
+};
+
+struct isa_range {
+        struct isa_address isa_addr;
+        struct pci_address pci_addr;
+        unsigned int size;
+};
+
+struct reg_property {
+        unsigned long address;
+        unsigned long size;
+};
+
+struct reg_property32 {
+        unsigned int address;
+        unsigned int size;
+};
+
+struct reg_property64 {
+        u64 address;
+        u64 size;
+};
+
+struct property {
+        char    *name;
+        int     length;
+        unsigned char *value;
+        struct property *next;
+};
+
+struct device_node {
+        char    *name;
+        char    *type;
+        phandle node;
+        phandle linux_phandle;
+        int     n_addrs;
+        struct  address_range *addrs;
+        int     n_intrs;
+        struct  interrupt_info *intrs;
+        char    *full_name;
+
+        struct  property *properties;
+        struct  device_node *parent;
+        struct  device_node *child;
+        struct  device_node *sibling;
+        struct  device_node *next;      /* next device of same type */
+        struct  device_node *allnext;   /* next in list of all nodes */
+        struct  proc_dir_entry *pde;    /* this node's proc directory */
+        struct  kref kref;
+        unsigned long _flags;
+        void    *data;
+};
+
+extern struct device_node *of_chosen;
+
+/* flag descriptions */
+#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */
+
+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
+
+#define HAVE_ARCH_DEVTREE_FIXUPS
+
+static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
+{
+        dn->pde = de;
+}
+
+
+/* OBSOLETE: Old style node lookup */
+extern struct device_node *find_devices(const char *name);
+extern struct device_node *find_type_devices(const char *type);
+extern struct device_node *find_path_device(const char *path);
+extern struct device_node *find_compatible_devices(const char *type,
+                                                   const char *compat);
+extern struct device_node *find_all_nodes(void);
+
+/* New style node lookup */
+extern struct device_node *of_find_node_by_name(struct device_node *from,
+        const char *name);
+extern struct device_node *of_find_node_by_type(struct device_node *from,
+        const char *type);
+extern struct device_node *of_find_compatible_node(struct device_node *from,
+        const char *type, const char *compat);
+extern struct device_node *of_find_node_by_path(const char *path);
+extern struct device_node *of_find_node_by_phandle(phandle handle);
+extern struct device_node *of_find_all_nodes(struct device_node *prev);
+extern struct device_node *of_get_parent(const struct device_node *node);
+extern struct device_node *of_get_next_child(const struct device_node *node,
+                                             struct device_node *prev);
+extern struct device_node *of_node_get(struct device_node *node);
+extern void of_node_put(struct device_node *node);
+
+/* For updating the device tree at runtime */
+extern void of_attach_node(struct device_node *);
+extern void of_detach_node(const struct device_node *);
+
+/* Other Prototypes */
+extern void finish_device_tree(void);
+extern void unflatten_device_tree(void);
+extern void early_init_devtree(void *);
+extern int device_is_compatible(struct device_node *device, const char *);
+extern int machine_is_compatible(const char *compat);
+extern unsigned char *get_property(struct device_node *node, const char *name,
+                                   int *lenp);
+extern void print_properties(struct device_node *node);
+extern int prom_n_addr_cells(struct device_node* np);
+extern int prom_n_size_cells(struct device_node* np);
+extern int prom_n_intr_cells(struct device_node* np);
+extern void prom_get_irq_senses(unsigned char *senses, int off, int max);
+extern void prom_add_property(struct device_node* np, struct property* prop);
+
+#ifdef CONFIG_PPC32
+/*
+ * PCI <-> OF matching functions
+ * (XXX should these be here?)
+ */
+struct pci_bus;
+struct pci_dev;
+extern int pci_device_from_OF_node(struct device_node *node,
+                                   u8* bus, u8* devfn);
+extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
+extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
+extern void pci_create_OF_bus_map(void);
+#endif
+
+extern struct resource *request_OF_resource(struct device_node* node,
+                                int index, const char* name_postfix);
+extern int release_OF_resource(struct device_node* node, int index);
+
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_PROM_H */
diff --git a/include/asm-ppc/reg.h b/include/asm-powerpc/reg.h
index 73c33e3ef9c6..da848412f11b 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -6,53 +6,107 @@
  * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
  */
 
+#ifndef _ASM_POWERPC_REG_H
+#define _ASM_POWERPC_REG_H
 #ifdef __KERNEL__
-#ifndef __ASM_PPC_REGS_H__
-#define __ASM_PPC_REGS_H__
 
 #include <linux/stringify.h>
+#include <asm/cputable.h>
 
 /* Pickup Book E specific registers. */
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 #include <asm/reg_booke.h>
 #endif
 
-/* Machine State Register (MSR) Fields */
-#define MSR_SF          (1<<63)
-#define MSR_ISF         (1<<61)
-#define MSR_VEC         (1<<25)         /* Enable AltiVec */
-#define MSR_POW         (1<<18)         /* Enable Power Management */
-#define MSR_WE          (1<<18)         /* Wait State Enable */
-#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
-#define MSR_CE          (1<<17)         /* Critical Interrupt Enable */
-#define MSR_ILE         (1<<16)         /* Interrupt Little Endian */
-#define MSR_EE          (1<<15)         /* External Interrupt Enable */
-#define MSR_PR          (1<<14)         /* Problem State / Privilege Level */
-#define MSR_FP          (1<<13)         /* Floating Point enable */
-#define MSR_ME          (1<<12)         /* Machine Check Enable */
-#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
-#define MSR_SE          (1<<10)         /* Single Step */
-#define MSR_BE          (1<<9)          /* Branch Trace */
-#define MSR_DE          (1<<9)          /* Debug Exception Enable */
-#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
-#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
-#define MSR_IR          (1<<5)          /* Instruction Relocate */
-#define MSR_DR          (1<<4)          /* Data Relocate */
-#define MSR_PE          (1<<3)          /* Protection Enable */
-#define MSR_PX          (1<<2)          /* Protection Exclusive Mode */
-#define MSR_RI          (1<<1)          /* Recoverable Exception */
-#define MSR_LE          (1<<0)          /* Little Endian */
+#define MSR_SF_LG       63              /* Enable 64 bit mode */
+#define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
+#define MSR_HV_LG       60              /* Hypervisor state */
+#define MSR_VEC_LG      25              /* Enable AltiVec */
+#define MSR_POW_LG      18              /* Enable Power Management */
+#define MSR_WE_LG       18              /* Wait State Enable */
+#define MSR_TGPR_LG     17              /* TLB Update registers in use */
+#define MSR_CE_LG       17              /* Critical Interrupt Enable */
+#define MSR_ILE_LG      16              /* Interrupt Little Endian */
+#define MSR_EE_LG       15              /* External Interrupt Enable */
+#define MSR_PR_LG       14              /* Problem State / Privilege Level */
+#define MSR_FP_LG       13              /* Floating Point enable */
+#define MSR_ME_LG       12              /* Machine Check Enable */
+#define MSR_FE0_LG      11              /* Floating Exception mode 0 */
+#define MSR_SE_LG       10              /* Single Step */
+#define MSR_BE_LG       9               /* Branch Trace */
+#define MSR_DE_LG       9               /* Debug Exception Enable */
+#define MSR_FE1_LG      8               /* Floating Exception mode 1 */
+#define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
+#define MSR_IR_LG       5               /* Instruction Relocate */
+#define MSR_DR_LG       4               /* Data Relocate */
+#define MSR_PE_LG       3               /* Protection Enable */
+#define MSR_PX_LG       2               /* Protection Exclusive Mode */
+#define MSR_PMM_LG      2               /* Performance monitor */
+#define MSR_RI_LG       1               /* Recoverable Exception */
+#define MSR_LE_LG       0               /* Little Endian */
 
+#ifdef __ASSEMBLY__
+#define __MASK(X)       (1<<(X))
+#else
+#define __MASK(X)       (1UL<<(X))
+#endif
+
+#ifdef CONFIG_PPC64
+#define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
+#define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
+#define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
+#else
+/* so tests for these bits fail on 32-bit */
+#define MSR_SF          0
+#define MSR_ISF         0
+#define MSR_HV          0
+#endif
+
+#define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
+#define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
+#define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
+#define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
+#define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
+#define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
+#define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
+#define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
+#define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
+#define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
+#define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
+#define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
+#define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
+#define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
+#define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
+#define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
+#define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
+#define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
+#define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
+#define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
+#ifndef MSR_PMM
+#define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
+#endif
+#define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
+#define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
+
+#ifdef CONFIG_PPC64
+#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
+#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
+
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
+#define MSR_USER64      MSR_USER32 | MSR_SF
+
+#else /* 32-bit */
 /* Default MSR for kernel mode. */
+#ifndef MSR_KERNEL      /* reg_booke.h also defines this */
 #ifdef CONFIG_APUS_FAST_EXCEPT
 #define MSR_KERNEL      (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
-#endif
-
-#ifndef MSR_KERNEL
+#else
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
 #endif
+#endif
 
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
+#endif
 
 /* Floating Point Status and Control Register (FPSCR) Fields */
 #define FPSCR_FX        0x80000000      /* FPU exception summary */
@@ -60,7 +114,7 @@
 #define FPSCR_VX        0x20000000      /* Invalid operation summary */
 #define FPSCR_OX        0x10000000      /* Overflow exception summary */
 #define FPSCR_UX        0x08000000      /* Underflow exception summary */
-#define FPSCR_ZX        0x04000000      /* Zero-devide exception summary */
+#define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
 #define FPSCR_XX        0x02000000      /* Inexact exception summary */
 #define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
 #define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
@@ -85,8 +139,18 @@
 
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_CTR        0x009   /* Count Register */
+#define SPRN_CTRLF      0x088
+#define SPRN_CTRLT      0x098
+#define   CTRL_RUNLATCH 0x1
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
+#define   DABR_TRANSLATION      (1UL << 2)
 #define SPRN_DAR        0x013   /* Data Address Register */
+#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
+#define   DSISR_NOHPTE          0x40000000      /* no translation found */
+#define   DSISR_PROTFAULT       0x08000000      /* protection fault */
+#define   DSISR_ISSTORE         0x02000000      /* access was a store */
+#define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
+#define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
@@ -131,7 +195,6 @@
 #define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
 #define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
 #define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
-#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 #define SPRN_EAR        0x11A           /* External Address Register */
 #define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
 #define SPRN_HASH2      0x3D3           /* Secondary Hash Address Resgister */
@@ -187,6 +250,16 @@
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 #define SPRN_HID4       0x3F4           /* 970 HID4 */
 #define SPRN_HID5       0x3F6           /* 970 HID5 */
+#define SPRN_HID6       0x3F9   /* BE HID 6 */
+#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
+#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
+#define SPRN_TSCR       0x399   /* Thread switch control on BE */
+#define SPRN_TTR        0x39A   /* Thread switch timeout on BE */
+#define   TSCR_DEC_ENABLE       0x200000 /* Decrementer Interrupt */
+#define   TSCR_EE_ENABLE        0x100000 /* External Interrupt */
+#define   TSCR_EE_BOOST         0x080000 /* External Interrupt Boost */
+#define SPRN_TSC        0x3FD   /* Thread switch control on others */
+#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
 #define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
 #define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
@@ -270,22 +343,18 @@
 #define L3CR_L3DO               0x00000040      /* L3 data only mode */
 #define L3CR_PMEN               0x00000004      /* L3 private memory enable */
 #define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
+
 #define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
 #define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
 #define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
 #define SPRN_LDSTDB     0x3f4   /* */
 #define SPRN_LR         0x008   /* Link Register */
-#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
-#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
 #ifndef SPRN_PIR
 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 #endif
-#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
-#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
-#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
-#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
+#define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
 #define SPRN_PVR        0x11F   /* Processor Version Register */
 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
@@ -327,6 +396,52 @@
 #define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
 
+/* Performance monitor SPRs */
+#ifdef CONFIG_PPC64
+#define SPRN_MMCR0      795
+#define   MMCR0_FC      0x80000000UL /* freeze counters */
+#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
+#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
+#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
+#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
+#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
+#define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
+#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
+#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
+#define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
+#define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
+#define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
+#define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
+#define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
+#define SPRN_MMCR1      798
+#define SPRN_MMCRA      0x312
+#define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
+#define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
+#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define SPRN_PMC1       787
+#define SPRN_PMC2       788
+#define SPRN_PMC3       789
+#define SPRN_PMC4       790
+#define SPRN_PMC5       791
+#define SPRN_PMC6       792
+#define SPRN_PMC7       793
+#define SPRN_PMC8       794
+#define SPRN_SIAR       780
+#define SPRN_SDAR       781
+
+#else /* 32-bit */
+#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
+#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
+#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
+#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
+#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
+#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
+
 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
 #define MMCR0_PMC1_CYCLES       (1 << 7)
 #define MMCR0_PMC1_ICACHEMISS   (5 << 7)
@@ -336,14 +451,15 @@
 #define MMCR0_PMC2_ITLB         0x7
 #define MMCR0_PMC2_LOADMISSTIME 0x5
 #define MMCR0_PMXE      (1 << 26)
-
-/* Processor Version Register */
+#endif
 
 /* Processor Version Register (PVR) field extraction */
 
 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
 #define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
 
+#define __is_processor(pv)      (PVR_VER(mfspr(SPRN_PVR)) == (pv))
+
 /*
  * IBM has further subdivided the standard PowerPC 16-bit version and
  * revision subfields of the PVR for the PowerPC 403s into the following:
@@ -399,42 +515,99 @@
 #define PVR_8245        0x80811014
 #define PVR_8260        PVR_8240
 
-#if 0
-/* Segment Registers */
-#define SR0     0
-#define SR1     1
-#define SR2     2
-#define SR3     3
-#define SR4     4
-#define SR5     5
-#define SR6     6
-#define SR7     7
-#define SR8     8
-#define SR9     9
-#define SR10    10
-#define SR11    11
-#define SR12    12
-#define SR13    13
-#define SR14    14
-#define SR15    15
-#endif
+/* 64-bit processors */
+/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
+#define PV_NORTHSTAR    0x0033
+#define PV_PULSAR       0x0034
+#define PV_POWER4       0x0035
+#define PV_ICESTAR      0x0036
+#define PV_SSTAR        0x0037
+#define PV_POWER4p      0x0038
+#define PV_970          0x0039
+#define PV_POWER5       0x003A
+#define PV_POWER5p      0x003B
+#define PV_970FX        0x003C
+#define PV_630          0x0040
+#define PV_630p 0x0041
+#define PV_970MP        0x0044
+#define PV_BE           0x0070
+
+/*
+ * Number of entries in the SLB. If this ever changes we should handle
+ * it with a use a cpu feature fixup.
+ */
+#define SLB_NUM_ENTRIES 64
 
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__
-#define mfmsr()         ({unsigned int rval; \
+#define mfmsr()         ({unsigned long rval; \
                         asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#ifdef CONFIG_PPC64
+#define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
+                                     : : "r" (v))
+#define mtmsrd(v)       __mtmsrd((v), 0)
+#define mtmsr(v)        mtmsrd(v)
+#else
 #define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
+#endif
 
-#define mfspr(rn)       ({unsigned int rval; \
+#define mfspr(rn)       ({unsigned long rval; \
                         asm volatile("mfspr %0," __stringify(rn) \
                                 : "=r" (rval)); rval;})
 #define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
 
+#define mftb()          ({unsigned long rval;   \
+                        asm volatile("mftb %0" : "=r" (rval)); rval;})
+#define mftbl()         ({unsigned long rval;   \
+                        asm volatile("mftbl %0" : "=r" (rval)); rval;})
+
+#define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
+#define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
+
+#ifdef CONFIG_PPC32
 #define mfsrin(v)       ({unsigned int rval; \
                         asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
                                         rval;})
+#endif
 
 #define proc_trap()     asm volatile("trap")
+
+#ifdef CONFIG_PPC64
+static inline void ppc64_runlatch_on(void)
+{
+        unsigned long ctrl;
+
+        if (cpu_has_feature(CPU_FTR_CTRL)) {
+                ctrl = mfspr(SPRN_CTRLF);
+                ctrl |= CTRL_RUNLATCH;
+                mtspr(SPRN_CTRLT, ctrl);
+        }
+}
+
+static inline void ppc64_runlatch_off(void)
+{
+        unsigned long ctrl;
+
+        if (cpu_has_feature(CPU_FTR_CTRL)) {
+                ctrl = mfspr(SPRN_CTRLF);
+                ctrl &= ~CTRL_RUNLATCH;
+                mtspr(SPRN_CTRLT, ctrl);
+        }
+}
+#endif
+
+#define __get_SP()      ({unsigned long sp; \
+                        asm volatile("mr %0,1": "=r" (sp)); sp;})
+
+#else /* __ASSEMBLY__ */
+
+#define RUNLATCH_ON(REG)                        \
+BEGIN_FTR_SECTION                               \
+        mfspr   (REG),SPRN_CTRLF;               \
+        ori     (REG),(REG),CTRL_RUNLATCH;      \
+        mtspr   SPRN_CTRLT,(REG);               \
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
+
 #endif /* __ASSEMBLY__ */
-#endif /* __ASM_PPC_REGS_H__ */
 #endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_REG_H */
diff --git a/include/asm-ppc64/rtas.h b/include/asm-powerpc/rtas.h
index e7d1b5222802..2c050332471d 100644
--- a/include/asm-ppc64/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_RTAS_H
-#define _PPC64_RTAS_H
+#ifndef _POWERPC_RTAS_H
+#define _POWERPC_RTAS_H
 
 #include <linux/spinlock.h>
 #include <asm/page.h>
@@ -190,7 +190,7 @@ extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
 
 struct rtc_time;
-extern void rtas_get_boot_time(struct rtc_time *rtc_time);
+extern unsigned long rtas_get_boot_time(void);
 extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
 extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
 
@@ -246,4 +246,4 @@ extern unsigned long rtas_rmo_buf;
 
 #define GLOBAL_INTERRUPT_QUEUE 9005
 
-#endif /* _PPC64_RTAS_H */
+#endif /* _POWERPC_RTAS_H */
diff --git a/include/asm-powerpc/rtc.h b/include/asm-powerpc/rtc.h
new file mode 100644
index 000000000000..f5802926b6c0
--- /dev/null
+++ b/include/asm-powerpc/rtc.h
@@ -0,0 +1,78 @@
+/*
+ * Real-time clock definitions and interfaces
+ *
+ * Author: Tom Rini <trini@mvista.com>
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Based on:
+ * include/asm-m68k/rtc.h
+ *
+ * Copyright Richard Zidlicky
+ * implementation details for genrtc/q40rtc driver
+ *
+ * And the old drivers/macintosh/rtc.c which was heavily based on:
+ * Linux/SPARC Real Time Clock Driver
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ *
+ * With additional work by Paul Mackerras and Franz Sirl.
+ */
+
+#ifndef __ASM_POWERPC_RTC_H__
+#define __ASM_POWERPC_RTC_H__
+
+#ifdef __KERNEL__
+
+#include <linux/rtc.h>
+
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+#define RTC_PIE 0x40            /* periodic interrupt enable */
+#define RTC_AIE 0x20            /* alarm interrupt enable */
+#define RTC_UIE 0x10            /* update-finished interrupt enable */
+
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+
+static inline unsigned int get_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.get_rtc_time)
+                ppc_md.get_rtc_time(time);
+        return RTC_24H;
+}
+
+/* Set the current date and time in the real time clock. */
+static inline int set_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.set_rtc_time)
+                return ppc_md.set_rtc_time(time);
+        return -EINVAL;
+}
+
+static inline unsigned int get_rtc_ss(void)
+{
+        struct rtc_time h;
+
+        get_rtc_time(&h);
+        return h.tm_sec;
+}
+
+static inline int get_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+static inline int set_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/include/asm-ppc64/rwsem.h b/include/asm-powerpc/rwsem.h
index bd5c2f093575..79bae4933b73 100644
--- a/include/asm-ppc64/rwsem.h
+++ b/include/asm-powerpc/rwsem.h
@@ -1,18 +1,14 @@
+#ifndef _ASM_POWERPC_RWSEM_H
+#define _ASM_POWERPC_RWSEM_H
+
+#ifdef __KERNEL__
+
 /*
  * include/asm-ppc64/rwsem.h: R/W semaphores for PPC using the stuff
  * in lib/rwsem.c.  Adapted largely from include/asm-i386/rwsem.h
  * by Paul Mackerras <paulus@samba.org>.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
  */
 
-#ifndef _PPC64_RWSEM_H
-#define _PPC64_RWSEM_H
-
-#ifdef __KERNEL__
 #include <linux/list.h>
 #include <linux/spinlock.h>
 #include <asm/atomic.h>
@@ -163,5 +159,10 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
         return atomic_add_return(delta, (atomic_t *)(&sem->count));
 }
 
-#endif /* __KERNEL__ */
-#endif /* _PPC_RWSEM_XADD_H */
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_RWSEM_H */
diff --git a/include/asm-ppc64/scatterlist.h b/include/asm-powerpc/scatterlist.h
index cecce6c6dfbb..8c992d1491d4 100644
--- a/include/asm-ppc64/scatterlist.h
+++ b/include/asm-powerpc/scatterlist.h
@@ -1,6 +1,5 @@
-#ifndef _PPC64_SCATTERLIST_H
-#define _PPC64_SCATTERLIST_H
-
+#ifndef _ASM_POWERPC_SCATTERLIST_H
+#define _ASM_POWERPC_SCATTERLIST_H
 /*
  * Copyright (C) 2001 PPC64 Team, IBM Corp
  *
@@ -10,6 +9,7 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#ifdef __KERNEL__
 #include <linux/types.h>
 #include <asm/dma.h>
 
@@ -19,13 +19,27 @@ struct scatterlist {
         unsigned int length;
 
         /* For TCE support */
-        u32 dma_address;
+        dma_addr_t dma_address;
         u32 dma_length;
 };
 
+/*
+ * These macros should be used after a dma_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
 #define sg_dma_address(sg)      ((sg)->dma_address)
+#ifdef __powerpc64__
 #define sg_dma_len(sg)          ((sg)->dma_length)
+#else
+#define sg_dma_len(sg)          ((sg)->length)
+#endif
 
+#ifdef __powerpc64__
 #define ISA_DMA_THRESHOLD       (~0UL)
+#endif
 
-#endif /* !(_PPC64_SCATTERLIST_H) */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SCATTERLIST_H */
diff --git a/include/asm-ppc64/seccomp.h b/include/asm-powerpc/seccomp.h
index c130c334bda1..1e1cfe12882b 100644
--- a/include/asm-ppc64/seccomp.h
+++ b/include/asm-powerpc/seccomp.h
@@ -1,11 +1,6 @@
-#ifndef _ASM_SECCOMP_H
-
-#include <linux/thread_info.h> /* already defines TIF_32BIT */
-
-#ifndef TIF_32BIT
-#error "unexpected TIF_32BIT on ppc64"
-#endif
+#ifndef _ASM_POWERPC_SECCOMP_H
 
+#include <linux/thread_info.h>
 #include <linux/unistd.h>
 
 #define __NR_seccomp_read __NR_read
@@ -18,4 +13,4 @@
 #define __NR_seccomp_exit_32 __NR_exit
 #define __NR_seccomp_sigreturn_32 __NR_sigreturn
 
-#endif /* _ASM_SECCOMP_H */
+#endif  /* _ASM_POWERPC_SECCOMP_H */
diff --git a/include/asm-ppc64/sections.h b/include/asm-powerpc/sections.h
index 308ca6f5ced2..47be2ac2a925 100644
--- a/include/asm-ppc64/sections.h
+++ b/include/asm-powerpc/sections.h
@@ -1,22 +1,11 @@
-#ifndef _PPC64_SECTIONS_H
-#define _PPC64_SECTIONS_H
-
-extern char _end[];
+#ifndef _ASM_POWERPC_SECTIONS_H
+#define _ASM_POWERPC_SECTIONS_H
 
 #include <asm-generic/sections.h>
 
-#define __pmac
-#define __pmacdata
-
-#define __prep
-#define __prepdata
-
-#define __chrp
-#define __chrpdata
-
-#define __openfirmware
-#define __openfirmwaredata
+#ifdef __powerpc64__
 
+extern char _end[];
 
 static inline int in_kernel_text(unsigned long addr)
 {
@@ -27,3 +16,5 @@ static inline int in_kernel_text(unsigned long addr)
 }
 
 #endif
+
+#endif  /* _ASM_POWERPC_SECTIONS_H */
diff --git a/include/asm-ppc64/semaphore.h b/include/asm-powerpc/semaphore.h
index aefe7753ea41..57369d2cadef 100644
--- a/include/asm-ppc64/semaphore.h
+++ b/include/asm-powerpc/semaphore.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_SEMAPHORE_H
-#define _PPC64_SEMAPHORE_H
+#ifndef _ASM_POWERPC_SEMAPHORE_H
+#define _ASM_POWERPC_SEMAPHORE_H
 
 /*
  * Remove spinlock-based RW semaphores; RW semaphore definitions are
@@ -31,9 +31,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name, count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
@@ -95,4 +92,4 @@ static inline void up(struct semaphore * sem)
 
 #endif /* __KERNEL__ */
 
-#endif /* !(_PPC64_SEMAPHORE_H) */
+#endif /* _ASM_POWERPC_SEMAPHORE_H */
diff --git a/include/asm-ppc64/smu.h b/include/asm-powerpc/smu.h
index dee8eefe47bc..dee8eefe47bc 100644
--- a/include/asm-ppc64/smu.h
+++ b/include/asm-powerpc/smu.h
diff --git a/include/asm-ppc64/spinlock_types.h b/include/asm-powerpc/spinlock_types.h
index a37c8eabb9f2..74236c9f05b1 100644
--- a/include/asm-ppc64/spinlock_types.h
+++ b/include/asm-powerpc/spinlock_types.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
+#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
+#define _ASM_POWERPC_SPINLOCK_TYPES_H
 
 #ifndef __LINUX_SPINLOCK_TYPES_H
 # error "please don't include this file directly"
diff --git a/include/asm-ppc64/sstep.h b/include/asm-powerpc/sstep.h
index 4a68db50ee6f..630a9889c07c 100644
--- a/include/asm-ppc64/sstep.h
+++ b/include/asm-powerpc/sstep.h
@@ -16,8 +16,10 @@ struct pt_regs;
  * we don't allow putting a breakpoint on an mtmsrd instruction.
  * Similarly we don't allow breakpoints on rfid instructions.
  * These macros tell us if an instruction is a mtmsrd or rfid.
+ * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
+ * and an mtmsrd (64-bit).
  */
-#define IS_MTMSRD(instr)        (((instr) & 0xfc0007fe) == 0x7c000164)
+#define IS_MTMSRD(instr)        (((instr) & 0xfc0007be) == 0x7c000124)
 #define IS_RFID(instr)          (((instr) & 0xfc0007fe) == 0x4c000024)
 
 /* Emulate instructions that cause a transfer of control. */
diff --git a/include/asm-ppc64/statfs.h b/include/asm-powerpc/statfs.h
index 3c985e5246a7..67024026c10d 100644
--- a/include/asm-ppc64/statfs.h
+++ b/include/asm-powerpc/statfs.h
@@ -1,12 +1,11 @@
-#ifndef _PPC64_STATFS_H
-#define _PPC64_STATFS_H
+#ifndef _ASM_POWERPC_STATFS_H
+#define _ASM_POWERPC_STATFS_H
 
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
+/* For ppc32 we just use the generic definitions, not so simple on ppc64 */
+
+#ifndef __powerpc64__
+#include <asm-generic/statfs.h>
+#else
 
 #ifndef __KERNEL_STRICT_NAMES
 #include <linux/types.h>
@@ -57,5 +56,5 @@ struct compat_statfs64 {
         __u32 f_frsize;
         __u32 f_spare[5];
 };
-
-#endif  /* _PPC64_STATFS_H */
+#endif /* ! __powerpc64__ */
+#endif
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
new file mode 100644
index 000000000000..4660c0394a77
--- /dev/null
+++ b/include/asm-powerpc/synch.h
@@ -0,0 +1,51 @@
+#ifndef _ASM_POWERPC_SYNCH_H 
+#define _ASM_POWERPC_SYNCH_H 
+
+#include <linux/config.h>
+
+#ifdef __powerpc64__
+#define __SUBARCH_HAS_LWSYNC
+#endif
+
+#ifdef __SUBARCH_HAS_LWSYNC
+#    define LWSYNC      lwsync
+#else
+#    define LWSYNC      sync
+#endif
+
+
+/*
+ * Arguably the bitops and *xchg operations don't imply any memory barrier
+ * or SMP ordering, but in fact a lot of drivers expect them to imply
+ * both, since they do on x86 cpus.
+ */
+#ifdef CONFIG_SMP
+#define EIEIO_ON_SMP    "eieio\n"
+#define ISYNC_ON_SMP    "\n\tisync"
+#define SYNC_ON_SMP     __stringify(LWSYNC) "\n"
+#else
+#define EIEIO_ON_SMP
+#define ISYNC_ON_SMP
+#define SYNC_ON_SMP
+#endif
+
+static inline void eieio(void)
+{
+        __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void isync(void)
+{
+        __asm__ __volatile__ ("isync" : : : "memory");
+}
+
+#ifdef CONFIG_SMP
+#define eieio_on_smp()  eieio()
+#define isync_on_smp()  isync()
+#else
+#define eieio_on_smp()  __asm__ __volatile__("": : :"memory")
+#define isync_on_smp()  __asm__ __volatile__("": : :"memory")
+#endif
+
+#endif  /* _ASM_POWERPC_SYNCH_H */
+
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
new file mode 100644
index 000000000000..5b2ecbc47907
--- /dev/null
+++ b/include/asm-powerpc/system.h
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
+ */
+#ifndef _ASM_POWERPC_SYSTEM_H
+#define _ASM_POWERPC_SYSTEM_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+
+#include <asm/hw_irq.h>
+#include <asm/ppc_asm.h>
+#include <asm/atomic.h>
+
+/*
+ * Memory barrier.
+ * The sync instruction guarantees that all memory accesses initiated
+ * by this processor have been performed (with respect to all other
+ * mechanisms that access memory).  The eieio instruction is a barrier
+ * providing an ordering (separately) for (a) cacheable stores and (b)
+ * loads and stores to non-cacheable memory (e.g. I/O devices).
+ *
+ * mb() prevents loads and stores being reordered across this point.
+ * rmb() prevents loads being reordered across this point.
+ * wmb() prevents stores being reordered across this point.
+ * read_barrier_depends() prevents data-dependent loads being reordered
+ *      across this point (nop on PPC).
+ *
+ * We have to use the sync instructions for mb(), since lwsync doesn't
+ * order loads with respect to previous stores.  Lwsync is fine for
+ * rmb(), though.  Note that lwsync is interpreted as sync by
+ * 32-bit and older 64-bit CPUs.
+ *
+ * For wmb(), we use sync since wmb is used in drivers to order
+ * stores to system memory with respect to writes to the device.
+ * However, smp_wmb() can be a lighter-weight eieio barrier on
+ * SMP since it is only used to order updates to system memory.
+ */
+#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
+#define rmb()  __asm__ __volatile__ ("lwsync" : : : "memory")
+#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define read_barrier_depends()  do { } while(0)
+
+#define set_mb(var, value)      do { var = value; mb(); } while (0)
+#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif /* CONFIG_SMP */
+
+#ifdef __KERNEL__
+struct task_struct;
+struct pt_regs;
+
+#ifdef CONFIG_DEBUGGER
+
+extern int (*__debugger)(struct pt_regs *regs);
+extern int (*__debugger_ipi)(struct pt_regs *regs);
+extern int (*__debugger_bpt)(struct pt_regs *regs);
+extern int (*__debugger_sstep)(struct pt_regs *regs);
+extern int (*__debugger_iabr_match)(struct pt_regs *regs);
+extern int (*__debugger_dabr_match)(struct pt_regs *regs);
+extern int (*__debugger_fault_handler)(struct pt_regs *regs);
+
+#define DEBUGGER_BOILERPLATE(__NAME) \
+static inline int __NAME(struct pt_regs *regs) \
+{ \
+        if (unlikely(__ ## __NAME)) \
+                return __ ## __NAME(regs); \
+        return 0; \
+}
+
+DEBUGGER_BOILERPLATE(debugger)
+DEBUGGER_BOILERPLATE(debugger_ipi)
+DEBUGGER_BOILERPLATE(debugger_bpt)
+DEBUGGER_BOILERPLATE(debugger_sstep)
+DEBUGGER_BOILERPLATE(debugger_iabr_match)
+DEBUGGER_BOILERPLATE(debugger_dabr_match)
+DEBUGGER_BOILERPLATE(debugger_fault_handler)
+
+#ifdef CONFIG_XMON
+extern void xmon_init(int enable);
+#endif
+
+#else
+static inline int debugger(struct pt_regs *regs) { return 0; }
+static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
+static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
+static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
+static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
+static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
+static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
+#endif
+
+extern int set_dabr(unsigned long dabr);
+extern void print_backtrace(unsigned long *);
+extern void show_regs(struct pt_regs * regs);
+extern void flush_instruction_cache(void);
+extern void hard_reset_now(void);
+extern void poweroff_now(void);
+
+#ifdef CONFIG_6xx
+extern long _get_L2CR(void);
+extern long _get_L3CR(void);
+extern void _set_L2CR(unsigned long);
+extern void _set_L3CR(unsigned long);
+#else
+#define _get_L2CR()     0L
+#define _get_L3CR()     0L
+#define _set_L2CR(val)  do { } while(0)
+#define _set_L3CR(val)  do { } while(0)
+#endif
+
+extern void via_cuda_init(void);
+extern void read_rtc_time(void);
+extern void pmac_find_display(void);
+extern void giveup_fpu(struct task_struct *);
+extern void disable_kernel_fp(void);
+extern void enable_kernel_fp(void);
+extern void flush_fp_to_thread(struct task_struct *);
+extern void enable_kernel_altivec(void);
+extern void giveup_altivec(struct task_struct *);
+extern void load_up_altivec(struct task_struct *);
+extern int emulate_altivec(struct pt_regs *);
+extern void giveup_spe(struct task_struct *);
+extern void load_up_spe(struct task_struct *);
+extern int fix_alignment(struct pt_regs *);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
+
+#ifdef CONFIG_ALTIVEC
+extern void flush_altivec_to_thread(struct task_struct *);
+#else
+static inline void flush_altivec_to_thread(struct task_struct *t)
+{
+}
+#endif
+
+#ifdef CONFIG_SPE
+extern void flush_spe_to_thread(struct task_struct *);
+#else
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
+#endif
+
+extern int call_rtas(const char *, int, int, unsigned long *, ...);
+extern void cacheable_memzero(void *p, unsigned int nb);
+extern void *cacheable_memcpy(void *, const void *, unsigned int);
+extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
+extern void bad_page_fault(struct pt_regs *, unsigned long, int);
+extern int die(const char *, struct pt_regs *, long);
+extern void _exception(int, struct pt_regs *, int, unsigned long);
+#ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+#endif /* CONFIG_BOOKE_WDT */
+
+/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
+extern unsigned char e2a(unsigned char);
+
+struct device_node;
+extern void note_scsi_host(struct device_node *, void *);
+
+extern struct task_struct *__switch_to(struct task_struct *,
+        struct task_struct *);
+#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
+
+struct thread_struct;
+extern struct task_struct *_switch(struct thread_struct *prev,
+                                   struct thread_struct *next);
+
+extern unsigned int rtas_data;
+extern int mem_init_done;       /* set on boot once kmalloc can be called */
+extern unsigned long memory_limit;
+
+extern int powersave_nap;       /* set if nap mode can be used in idle loop */
+
+/*
+ * Atomic exchange
+ *
+ * Changes the memory location '*ptr' to be val and returns
+ * the previous value stored there.
+ */
+static __inline__ unsigned long
+__xchg_u32(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:     lwarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %3,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (prev), "=m" (*(volatile unsigned int *)p)
+        : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
+        : "cc", "memory");
+
+        return prev;
+}
+
+#ifdef CONFIG_PPC64
+static __inline__ unsigned long
+__xchg_u64(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:     ldarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stdcx.  %3,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
+        : "cc", "memory");
+
+        return prev;
+}
+#endif
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid xchg().
+ */
+extern void __xchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+__xchg(volatile void *ptr, unsigned long x, unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32(ptr, x);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __xchg_u64(ptr, x);
+#endif
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+#define xchg(ptr,x)                                                          \
+  ({                                                                         \
+     __typeof__(*(ptr)) _x_ = (x);                                           \
+     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
+  })
+
+#define tas(ptr) (xchg((ptr),1))
+
+/*
+ * Compare and exchange - if *p == old, set it to new,
+ * and return the old value of *p.
+ */
+#define __HAVE_ARCH_CMPXCHG     1
+
+static __inline__ unsigned long
+__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
+{
+        unsigned int prev;
+
+        __asm__ __volatile__ (
+        EIEIO_ON_SMP
+"1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
+        cmpw    0,%0,%3\n\
+        bne-    2f\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %4,0,%2\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"
+        : "=&r" (prev), "=m" (*p)
+        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "cc", "memory");
+
+        return prev;
+}
+
+#ifdef CONFIG_PPC64
+static __inline__ unsigned long
+__cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__ (
+        EIEIO_ON_SMP
+"1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
+        cmpd    0,%0,%3\n\
+        bne-    2f\n\
+        stdcx.  %4,0,%2\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"
+        : "=&r" (prev), "=m" (*p)
+        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "cc", "memory");
+
+        return prev;
+}
+#endif
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
+          unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __cmpxchg_u64(ptr, old, new);
+#endif
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+#ifdef CONFIG_PPC64
+/*
+ * We handle most unaligned accesses in hardware. On the other hand 
+ * unaligned DMA can be very expensive on some ppc64 IO chips (it does
+ * powers of 2 writes until it reaches sufficient alignment).
+ *
+ * Based on this we disable the IP header alignment in network drivers.
+ */
+#define NET_IP_ALIGN   0
+#endif
+
+#define arch_align_stack(x) (x)
+
+/* Used in very early kernel initialization. */
+extern unsigned long reloc_offset(void);
+extern unsigned long add_reloc_offset(unsigned long);
+extern void reloc_got2(unsigned long);
+
+#define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-powerpc/thread_info.h
index 0494df6fca74..ab17db79f69d 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-powerpc/thread_info.h
@@ -1,15 +1,25 @@
-/* thread_info.h: PPC low-level thread information
+/* thread_info.h: PowerPC low-level thread information
  * adapted from the i386 version by Paul Mackerras
  *
  * Copyright (C) 2002  David Howells (dhowells@redhat.com)
  * - Incorporating suggestions made by Linus Torvalds and Dave Miller
  */
 
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
+#ifndef _ASM_POWERPC_THREAD_INFO_H
+#define _ASM_POWERPC_THREAD_INFO_H
 
 #ifdef __KERNEL__
 
+/* We have 8k stacks on ppc32 and 16k on ppc64 */
+
+#ifdef CONFIG_PPC64
+#define THREAD_SHIFT            14
+#else
+#define THREAD_SHIFT            13
+#endif
+
+#define THREAD_SIZE             (1 << THREAD_SHIFT)
+
 #ifndef __ASSEMBLY__
 #include <linux/config.h>
 #include <linux/cache.h>
@@ -24,7 +34,8 @@ struct thread_info {
         struct task_struct *task;               /* main task structure */
         struct exec_domain *exec_domain;        /* execution domain */
         int             cpu;                    /* cpu we're on */
-        int             preempt_count;          /* 0 => preemptable, <0 => BUG */
+        int             preempt_count;          /* 0 => preemptable,
+                                                   <0 => BUG */
         struct restart_block restart_block;
         /* set by force_successful_syscall_return */
         unsigned char   syscall_noerror;
@@ -54,32 +65,38 @@ struct thread_info {
 
 /* thread information allocation */
 
-#define THREAD_ORDER            2
-#define THREAD_SIZE             (PAGE_SIZE << THREAD_ORDER)
-#define THREAD_SHIFT            (PAGE_SHIFT + THREAD_ORDER)
 #ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(tsk)                                  \
-        ({                                                      \
-                struct thread_info *ret;                        \
-                                                                \
-                ret = kmalloc(THREAD_SIZE, GFP_KERNEL);         \
-                if (ret)                                        \
-                        memset(ret, 0, THREAD_SIZE);            \
-                ret;                                            \
-        })
+#define THREAD_INFO_GFP         GFP_KERNEL | __GFP_ZERO
 #else
-#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
+#define THREAD_INFO_GFP         GFP_KERNEL
 #endif
+
+#if THREAD_SHIFT >= PAGE_SHIFT
+
+#define THREAD_ORDER    (THREAD_SHIFT - PAGE_SHIFT)
+
+#define alloc_thread_info(tsk)  \
+        ((struct thread_info *)__get_free_pages(THREAD_INFO_GFP, THREAD_ORDER))
+#define free_thread_info(ti)    free_pages((unsigned long)ti, THREAD_ORDER)
+
+#else /* THREAD_SHIFT < PAGE_SHIFT */
+
+#define alloc_thread_info(tsk)  kmalloc(THREAD_SIZE, THREAD_INFO_GFP)
 #define free_thread_info(ti)    kfree(ti)
+
+#endif /* THREAD_SHIFT < PAGE_SHIFT */
+
 #define get_thread_info(ti)     get_task_struct((ti)->task)
 #define put_thread_info(ti)     put_task_struct((ti)->task)
 
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
 {
-        struct thread_info *ti;
-        __asm__("clrrdi %0,1,%1" : "=r"(ti) : "i" (THREAD_SHIFT));
-        return ti;
+        register unsigned long sp asm("r1");
+
+        /* gcc4, at least, is smart enough to turn this into a single
+         * rlwinm for ppc32 and clrrdi for ppc64 */
+        return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
 }
 
 #endif /* __ASSEMBLY__ */
@@ -122,4 +139,4 @@ static inline struct thread_info *current_thread_info(void)
 
 #endif /* __KERNEL__ */
 
-#endif /* _ASM_THREAD_INFO_H */
+#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
new file mode 100644
index 000000000000..410e795f7d43
--- /dev/null
+++ b/include/asm-powerpc/time.h
@@ -0,0 +1,226 @@
+/*
+ * Common time prototypes and such for all ppc machines.
+ *
+ * Written by Cort Dougan (cort@cs.nmt.edu) to merge
+ * Paul Mackerras' version and mine for PReP and Pmac.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __POWERPC_TIME_H
+#define __POWERPC_TIME_H
+
+#ifdef __KERNEL__
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/percpu.h>
+
+#include <asm/processor.h>
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+#include <asm/iSeries/HvCall.h>
+#endif
+
+/* time.c */
+extern unsigned long tb_ticks_per_jiffy;
+extern unsigned long tb_ticks_per_usec;
+extern unsigned long tb_ticks_per_sec;
+extern u64 tb_to_xs;
+extern unsigned      tb_to_us;
+extern unsigned long tb_last_stamp;
+extern u64 tb_last_jiffy;
+
+DECLARE_PER_CPU(unsigned long, last_jiffy);
+
+struct rtc_time;
+extern void to_tm(int tim, struct rtc_time * tm);
+extern time_t last_rtc_update;
+
+extern void generic_calibrate_decr(void);
+extern void wakeup_decrementer(void);
+
+/* Some sane defaults: 125 MHz timebase, 1GHz processor */
+extern unsigned long ppc_proc_freq;
+#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
+extern unsigned long ppc_tb_freq;
+#define DEFAULT_TB_FREQ         125000000UL
+
+/*
+ * By putting all of this stuff into a single struct we 
+ * reduce the number of cache lines touched by do_gettimeofday.
+ * Both by collecting all of the data in one cache line and
+ * by touching only one TOC entry on ppc64.
+ */
+struct gettimeofday_vars {
+        u64 tb_to_xs;
+        u64 stamp_xsec;
+        u64 tb_orig_stamp;
+};
+
+struct gettimeofday_struct {
+        unsigned long tb_ticks_per_sec;
+        struct gettimeofday_vars vars[2];
+        struct gettimeofday_vars * volatile varp;
+        unsigned      var_idx;
+        unsigned      tb_to_us;
+};
+
+struct div_result {
+        u64 result_high;
+        u64 result_low;
+};
+
+/* Accessor functions for the timebase (RTC on 601) registers. */
+/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
+#ifdef CONFIG_6xx
+#define __USE_RTC()     (!cpu_has_feature(CPU_FTR_USE_TB))
+#else
+#define __USE_RTC()     0
+#endif
+
+/* On ppc64 this gets us the whole timebase; on ppc32 just the lower half */
+static inline unsigned long get_tbl(void)
+{
+        unsigned long tbl;
+
+#if defined(CONFIG_403GCX)
+        asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
+#else
+        asm volatile("mftb %0" : "=r" (tbl));
+#endif
+        return tbl;
+}
+
+static inline unsigned int get_tbu(void)
+{
+        unsigned int tbu;
+
+#if defined(CONFIG_403GCX)
+        asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
+#else
+        asm volatile("mftbu %0" : "=r" (tbu));
+#endif
+        return tbu;
+}
+
+static inline unsigned int get_rtcl(void)
+{
+        unsigned int rtcl;
+
+        asm volatile("mfrtcl %0" : "=r" (rtcl));
+        return rtcl;
+}
+
+static inline u64 get_rtc(void)
+{
+        unsigned int hi, lo, hi2;
+
+        do {
+                asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
+                             : "=r" (hi), "=r" (lo), "=r" (hi2));
+        } while (hi2 != hi);
+        return (u64)hi * 1000000000 + lo;
+}
+
+#ifdef CONFIG_PPC64
+static inline u64 get_tb(void)
+{
+        return mftb();
+}
+#else
+static inline u64 get_tb(void)
+{
+        unsigned int tbhi, tblo, tbhi2;
+
+        do {
+                tbhi = get_tbu();
+                tblo = get_tbl();
+                tbhi2 = get_tbu();
+        } while (tbhi != tbhi2);
+
+        return ((u64)tbhi << 32) | tblo;
+}
+#endif
+
+static inline void set_tb(unsigned int upper, unsigned int lower)
+{
+        mtspr(SPRN_TBWL, 0);
+        mtspr(SPRN_TBWU, upper);
+        mtspr(SPRN_TBWL, lower);
+}
+
+/* Accessor functions for the decrementer register.
+ * The 4xx doesn't even have a decrementer.  I tried to use the
+ * generic timer interrupt code, which seems OK, with the 4xx PIT
+ * in auto-reload mode.  The problem is PIT stops counting when it
+ * hits zero.  If it would wrap, we could use it just like a decrementer.
+ */
+static inline unsigned int get_dec(void)
+{
+#if defined(CONFIG_40x)
+        return (mfspr(SPRN_PIT));
+#else
+        return (mfspr(SPRN_DEC));
+#endif
+}
+
+static inline void set_dec(int val)
+{
+#if defined(CONFIG_40x)
+        return;         /* Have to let it auto-reload */
+#elif defined(CONFIG_8xx_CPU6)
+        set_dec_cpu6(val);
+#else
+#ifdef CONFIG_PPC_ISERIES
+        struct paca_struct *lpaca = get_paca();
+        int cur_dec;
+
+        if (lpaca->lppaca.shared_proc) {
+                lpaca->lppaca.virtual_decr = val;
+                cur_dec = get_dec();
+                if (cur_dec > val)
+                        HvCall_setVirtualDecr();
+        } else
+#endif
+                mtspr(SPRN_DEC, val);
+#endif /* not 40x or 8xx_CPU6 */
+}
+
+static inline unsigned long tb_ticks_since(unsigned long tstamp)
+{
+        if (__USE_RTC()) {
+                int delta = get_rtcl() - (unsigned int) tstamp;
+                return delta < 0 ? delta + 1000000000 : delta;
+        }
+        return get_tbl() - tstamp;
+}
+
+#define mulhwu(x,y) \
+({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+
+#ifdef CONFIG_PPC64
+#define mulhdu(x,y) \
+({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+#else
+extern u64 mulhdu(u64, u64);
+#endif
+
+extern void smp_space_timers(unsigned int);
+
+extern unsigned mulhwu_scale_factor(unsigned, unsigned);
+extern void div128_by_32(u64 dividend_high, u64 dividend_low,
+                         unsigned divisor, struct div_result *dr);
+
+/* Used to store Processor Utilization register (purr) values */
+
+struct cpu_usage {
+        u64 current_tb;  /* Holds the current purr register values */
+};
+
+DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
+
+#endif /* __KERNEL__ */
+#endif /* __PPC64_TIME_H */
diff --git a/include/asm-ppc64/types.h b/include/asm-powerpc/types.h
index bf294c1761b2..ec3c2ee8bf86 100644
--- a/include/asm-ppc64/types.h
+++ b/include/asm-powerpc/types.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_TYPES_H
-#define _PPC64_TYPES_H
+#ifndef _ASM_POWERPC_TYPES_H
+#define _ASM_POWERPC_TYPES_H
 
 #ifndef __ASSEMBLY__
 
@@ -16,7 +16,11 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#ifdef __powerpc64__
 typedef unsigned int umode_t;
+#else
+typedef unsigned short umode_t;
+#endif
 
 /*
  * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
@@ -32,8 +36,15 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
+#ifdef __powerpc64__
 typedef __signed__ long __s64;
 typedef unsigned long __u64;
+#else
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+#endif /* __powerpc64__ */
 
 typedef struct {
         __u32 u[4];
@@ -45,10 +56,16 @@ typedef struct {
 /*
  * These aren't exported outside the kernel to avoid name space clashes
  */
+#ifdef __powerpc64__
 #define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
 
 #ifndef __ASSEMBLY__
 
+#include <linux/config.h>
+
 typedef signed char s8;
 typedef unsigned char u8;
 
@@ -58,12 +75,21 @@ typedef unsigned short u16;
 typedef signed int s32;
 typedef unsigned int u32;
 
+#ifdef __powerpc64__
 typedef signed long s64;
 typedef unsigned long u64;
+#else
+typedef signed long long s64;
+typedef unsigned long long u64;
+#endif
 
 typedef __vector128 vector128;
 
+#ifdef __powerpc64__
+typedef u64 dma_addr_t;
+#else
 typedef u32 dma_addr_t;
+#endif
 typedef u64 dma64_addr_t;
 
 typedef struct {
@@ -72,8 +98,13 @@ typedef struct {
         unsigned long env;
 } func_descr_t;
 
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
 
-#endif /* _PPC64_TYPES_H */
+#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/include/asm-ppc/uninorth.h b/include/asm-powerpc/uninorth.h
index f737732c3861..f737732c3861 100644
--- a/include/asm-ppc/uninorth.h
+++ b/include/asm-powerpc/uninorth.h
diff --git a/include/asm-ppc/unistd.h b/include/asm-powerpc/unistd.h
index 3173ab3d2eb9..0991dfceef1d 100644
--- a/include/asm-ppc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -3,7 +3,13 @@
 
 /*
  * This file contains the system call numbers.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
  */
+
 #define __NR_restart_syscall      0
 #define __NR_exit                 1
 #define __NR_fork                 2
@@ -196,19 +202,23 @@
 #define __NR_vfork              189
 #define __NR_ugetrlimit         190     /* SuS compliant getrlimit */
 #define __NR_readahead          191
+#ifndef __powerpc64__                   /* these are 32-bit only */
 #define __NR_mmap2              192
 #define __NR_truncate64         193
 #define __NR_ftruncate64        194
 #define __NR_stat64             195
 #define __NR_lstat64            196
 #define __NR_fstat64            197
+#endif
 #define __NR_pciconfig_read     198
 #define __NR_pciconfig_write    199
 #define __NR_pciconfig_iobase   200
 #define __NR_multiplexer        201
 #define __NR_getdents64         202
 #define __NR_pivot_root         203
+#ifndef __powerpc64__
 #define __NR_fcntl64            204
+#endif
 #define __NR_madvise            205
 #define __NR_mincore            206
 #define __NR_gettid             207
@@ -230,7 +240,9 @@
 #define __NR_sched_getaffinity  223
 /* 224 currently unused */
 #define __NR_tuxcall            225
+#ifndef __powerpc64__
 #define __NR_sendfile64         226
+#endif
 #define __NR_io_setup           227
 #define __NR_io_destroy         228
 #define __NR_io_getevents       229
@@ -258,14 +270,16 @@
 #define __NR_utimes             251
 #define __NR_statfs64           252
 #define __NR_fstatfs64          253
+#ifndef __powerpc64__
 #define __NR_fadvise64_64       254
+#endif
 #define __NR_rtas               255
 #define __NR_sys_debug_setcontext 256
 /* Number 257 is reserved for vserver */
 /* 258 currently unused */
-/* Number 259 is reserved for new sys_mbind */
-/* Number 260 is reserved for new sys_get_mempolicy */
-/* Number 261 is reserved for new sys_set_mempolicy */
+#define __NR_mbind              259
+#define __NR_get_mempolicy      260
+#define __NR_set_mempolicy      261
 #define __NR_mq_open            262
 #define __NR_mq_unlink          263
 #define __NR_mq_timedsend       264
@@ -285,7 +299,12 @@
 
 #define __NR_syscalls           278
 
-#define __NR(n) #n
+#ifdef __KERNEL__
+#define __NR__exit __NR_exit
+#define NR_syscalls     __NR_syscalls
+#endif
+
+#ifndef __ASSEMBLY__
 
 /* On powerpc a system call basically clobbers the same registers like a
  * function call, with the exception of LR (which is needed for the
@@ -389,7 +408,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)	\
 {                                                                       \
         __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5);      \
 }
-
 #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
 type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
 {                                                                       \
@@ -398,12 +416,13 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 
 #ifdef __KERNEL__
 
-#define __NR__exit __NR_exit
-#define NR_syscalls     __NR_syscalls
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
@@ -423,23 +442,17 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_RT_SIGACTION
-
-/*
- * Forking from kernel space will result in the child getting a new,
- * empty kernel stack area.  Thus the child cannot access automatic
- * variables set in the parent unless they are in registers, and the
- * procedure where the fork was done cannot return to its caller in
- * the child.
- */
-
-#ifdef __KERNEL_SYSCALLS__
-
-#include <linux/compiler.h>
-#include <linux/types.h>
+#ifdef CONFIG_PPC32
+#define __ARCH_WANT_OLD_STAT
+#endif
+#ifdef CONFIG_PPC64
+#define __ARCH_WANT_COMPAT_SYS_TIME
+#endif
 
 /*
  * System call prototypes.
  */
+#ifdef __KERNEL_SYSCALLS__
 extern pid_t setsid(void);
 extern int write(int fd, const char *buf, off_t count);
 extern int read(int fd, char *buf, off_t count);
@@ -449,10 +462,13 @@ extern int execve(const char *file, char **argv, char **envp);
 extern int open(const char *file, int flag, int mode);
 extern int close(int fd);
 extern pid_t waitpid(pid_t pid, int *wait_stat, int options);
+#endif /* __KERNEL_SYSCALLS__ */
 
-unsigned long sys_mmap(unsigned long addr, size_t len,
-                        unsigned long prot, unsigned long flags,
-                        unsigned long fd, off_t offset);
+/*
+ * Functions that implement syscalls.
+ */
+unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot,
+                       unsigned long flags, unsigned long fd, off_t offset);
 unsigned long sys_mmap2(unsigned long addr, size_t len,
                         unsigned long prot, unsigned long flags,
                         unsigned long fd, unsigned long pgoff);
@@ -461,22 +477,18 @@ int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
                 unsigned long a3, unsigned long a4, unsigned long a5,
                 struct pt_regs *regs);
 int sys_clone(unsigned long clone_flags, unsigned long usp,
-              int __user *parent_tidp, void __user *child_threadptr,
-              int __user *child_tidp, int p6,
-              struct pt_regs *regs);
-int sys_fork(int p1, int p2, int p3, int p4, int p5, int p6,
+                int __user *parent_tidp, void __user *child_threadptr,
+                int __user *child_tidp, int p6, struct pt_regs *regs);
+int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
+                unsigned long p4, unsigned long p5, unsigned long p6,
                 struct pt_regs *regs);
-int sys_vfork(int p1, int p2, int p3, int p4, int p5, int p6,
+int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
+                unsigned long p4, unsigned long p5, unsigned long p6,
                 struct pt_regs *regs);
 int sys_pipe(int __user *fildes);
-int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
-long sys_rt_sigaction(int sig,
-                      const struct sigaction __user *act,
-                      struct sigaction __user *oact,
-                      size_t sigsetsize);
-
-#endif /* __KERNEL_SYSCALLS__ */
+long sys_rt_sigaction(int sig, const struct sigaction __user *act,
+                      struct sigaction __user *oact, size_t sigsetsize);
 
 /*
  * "Conditional" syscalls
@@ -484,10 +496,14 @@ long sys_rt_sigaction(int sig,
  * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
  * but it doesn't work on all toolchains, so we just do it by hand
  */
-#ifndef cond_syscall
+#ifdef CONFIG_PPC32
 #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#else
+#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
 #endif
 
-#endif /* __KERNEL__ */
+#endif          /* __KERNEL__ */
+
+#endif          /* __ASSEMBLY__ */
 
 #endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc64/vga.h b/include/asm-powerpc/vga.h
index c09849743f45..f8d350aabf1a 100644
--- a/include/asm-ppc64/vga.h
+++ b/include/asm-powerpc/vga.h
@@ -1,16 +1,14 @@
+#ifndef _ASM_POWERPC_VGA_H_
+#define _ASM_POWERPC_VGA_H_
+
+#ifdef __KERNEL__
+
 /*
  *      Access to VGA videoram
  *
  *      (c) 1998 Martin Mares <mj@ucw.cz>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
  */
 
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
 
 #include <asm/io.h>
 
@@ -42,9 +40,15 @@ static inline u16 scr_readw(volatile const u16 *addr)
 #endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
 
 extern unsigned long vgacon_remap_base;
+
+#ifdef __powerpc64__
 #define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
+#else
+#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
+#endif
 
 #define vga_readb(x) (*(x))
 #define vga_writeb(x,y) (*(y) = (x))
 
-#endif
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_VGA_H_ */
diff --git a/include/asm-ppc64/vio.h b/include/asm-powerpc/vio.h
index 03f1b95f433b..e0ccf108277c 100644
--- a/include/asm-ppc64/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -1,18 +1,18 @@
 /*
  * IBM PowerPC Virtual I/O Infrastructure Support.
  *
- *    Copyright (c) 2003 IBM Corp.
- *     Dave Engebretsen engebret@us.ibm.com
- *     Santiago Leon santil@us.ibm.com
+ * Copyright (c) 2003 IBM Corp.
+ *  Dave Engebretsen engebret@us.ibm.com
+ *  Santiago Leon santil@us.ibm.com
  *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
  */
 
-#ifndef _ASM_VIO_H
-#define _ASM_VIO_H
+#ifndef _ASM_POWERPC_VIO_H
+#define _ASM_POWERPC_VIO_H
 
 #include <linux/config.h>
 #include <linux/init.h>
@@ -55,10 +55,10 @@ struct vio_dev {
 
 struct vio_driver {
         struct list_head node;
-        char *name;
         const struct vio_device_id *id_table;
         int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
         int (*remove)(struct vio_dev *dev);
+        void (*shutdown)(struct vio_dev *dev);
         unsigned long driver_data;
         struct device_driver driver;
 };
@@ -103,4 +103,4 @@ static inline struct vio_dev *to_vio_dev(struct device *dev)
         return container_of(dev, struct vio_dev, dev);
 }
 
-#endif /* _ASM_VIO_H */
+#endif /* _ASM_POWERPC_VIO_H */
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
new file mode 100644
index 000000000000..43f7129984c7
--- /dev/null
+++ b/include/asm-powerpc/xmon.h
@@ -0,0 +1,12 @@
+#ifndef __PPC_XMON_H
+#define __PPC_XMON_H
+#ifdef __KERNEL__
+
+struct pt_regs;
+
+extern int xmon(struct pt_regs *excp);
+extern void xmon_printf(const char *fmt, ...);
+extern void xmon_init(int);
+
+#endif
+#endif
diff --git a/include/asm-ppc/a.out.h b/include/asm-ppc/a.out.h
deleted file mode 100644
index 8979a94c4a81..000000000000
--- a/include/asm-ppc/a.out.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __PPC_A_OUT_H__
-#define __PPC_A_OUT_H__
-
-/* grabbed from the intel stuff  */
-#define STACK_TOP TASK_SIZE
-
-
-struct exec
-{
-  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-
-#endif
diff --git a/include/asm-ppc/auxvec.h b/include/asm-ppc/auxvec.h
deleted file mode 100644
index 172358df29c8..000000000000
--- a/include/asm-ppc/auxvec.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __PPC_AUXVEC_H
-#define __PPC_AUXVEC_H
-
-/*
- * We need to put in some extra aux table entries to tell glibc what
- * the cache block size is, so it can use the dcbz instruction safely.
- */
-#define AT_DCACHEBSIZE          19
-#define AT_ICACHEBSIZE          20
-#define AT_UCACHEBSIZE          21
-/* A special ignored type value for PPC, for glibc compatibility.  */
-#define AT_IGNOREPPC            22
-
-#endif
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
deleted file mode 100644
index 8b34fd682b0d..000000000000
--- a/include/asm-ppc/bug.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PPC_BUG_H
-#define _PPC_BUG_H
-
-struct bug_entry {
-        unsigned long   bug_addr;
-        int             line;
-        const char      *file;
-        const char      *function;
-};
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP        0x1000000
-
-#ifdef CONFIG_BUG
-#define BUG() do {                                                       \
-        __asm__ __volatile__(                                            \
-                "1:     twi 31,0,0\n"                                    \
-                ".section __bug_table,\"a\"\n\t"                         \
-                "       .long 1b,%0,%1,%2\n"                             \
-                ".previous"                                              \
-                : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do {                                                  \
-        if (!__builtin_constant_p(x) || (x)) {                          \
-                __asm__ __volatile__(                                   \
-                        "1:     twnei %0,0\n"                           \
-                        ".section __bug_table,\"a\"\n\t"                \
-                        "       .long 1b,%1,%2,%3\n"                    \
-                        ".previous"                                     \
-                        : : "r" (x), "i" (__LINE__), "i" (__FILE__),    \
-                            "i" (__FUNCTION__));                        \
-        }                                                               \
-} while (0)
-
-#define WARN_ON(x) do {                                                 \
-        if (!__builtin_constant_p(x) || (x)) {                          \
-                __asm__ __volatile__(                                   \
-                        "1:     twnei %0,0\n"                           \
-                        ".section __bug_table,\"a\"\n\t"                \
-                        "       .long 1b,%1,%2,%3\n"                    \
-                        ".previous"                                     \
-                        : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
-                            "i" (__FILE__), "i" (__FUNCTION__));        \
-        }                                                               \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h
deleted file mode 100644
index c63c81ec7968..000000000000
--- a/include/asm-ppc/byteorder.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef _PPC_BYTEORDER_H
-#define _PPC_BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#ifdef __GNUC__
-#ifdef __KERNEL__
-
-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
-{
-        unsigned val;
-
-        __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
-        return val;
-}
-
-extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
-{
-        __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
-}
-
-extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
-{
-        unsigned val;
-
-        __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
-        return val;
-}
-
-extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
-{
-        __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
-}
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
-{
-        __u16 result;
-
-        __asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value));
-        return result;
-}
-
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
-{
-        __u32 result;
-
-        __asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value));
-        __asm__("rlwimi %0,%2,8,8,15"   : "=&r" (result) : "0" (result),    "r" (value));
-        __asm__("rlwimi %0,%2,24,0,7"   : "=&r" (result) : "0" (result),    "r" (value));
-
-        return result;
-}
-#define __arch__swab32(x) ___arch__swab32(x)
-#define __arch__swab16(x) ___arch__swab16(x)
-
-/* The same, but returns converted value from the location pointer by addr. */
-#define __arch__swab16p(addr) ld_le16(addr)
-#define __arch__swab32p(addr) ld_le32(addr)
-
-/* The same, but do the conversion in situ, ie. put the value back to addr. */
-#define __arch__swab16s(addr) st_le16(addr,*addr)
-#define __arch__swab32s(addr) st_le32(addr,*addr)
-
-#endif /* __KERNEL__ */
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _PPC_BYTEORDER_H */
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 38f2f1be4a87..7a157d0f4b5f 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -9,21 +9,18 @@
 
 /* bytes per L1 cache line */
 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
-#define L1_CACHE_LINE_SIZE      16
-#define LG_L1_CACHE_LINE_SIZE   4
+#define L1_CACHE_SHIFT  4
 #define MAX_COPY_PREFETCH       1
 #elif defined(CONFIG_PPC64BRIDGE)
-#define L1_CACHE_LINE_SIZE      128
-#define LG_L1_CACHE_LINE_SIZE   7
+#define L1_CACHE_SHIFT  7
 #define MAX_COPY_PREFETCH       1
 #else
-#define L1_CACHE_LINE_SIZE      32
-#define LG_L1_CACHE_LINE_SIZE   5
+#define L1_CACHE_SHIFT  5
 #define MAX_COPY_PREFETCH       4
 #endif
 
-#define L1_CACHE_BYTES L1_CACHE_LINE_SIZE
-#define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE
+#define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
+
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 #define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
 
diff --git a/include/asm-ppc/checksum.h b/include/asm-ppc/checksum.h
deleted file mode 100644
index cf953a92c7ab..000000000000
--- a/include/asm-ppc/checksum.h
+++ /dev/null
@@ -1,107 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_CHECKSUM_H
-#define _PPC_CHECKSUM_H
-
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern unsigned int csum_partial(const unsigned char * buff, int len,
-                                 unsigned int sum);
-
-/*
- * Computes the checksum of a memory block at src, length len,
- * and adds in "sum" (32-bit), while copying the block to dst.
- * If an access exception occurs on src or dst, it stores -EFAULT
- * to *src_err or *dst_err respectively (if that pointer is not
- * NULL), and, for an error on src, zeroes the rest of dst.
- *
- * Like csum_partial, this must be called with even lengths,
- * except for the last fragment.
- */
-extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
-                                              int len, unsigned int sum,
-                                              int *src_err, int *dst_err);
-
-#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
-        csum_partial_copy_generic((__force void *)(src), (dst), (len), (sum), (errp), NULL)
-
-/* FIXME: this needs to be written to really do no check -- Cort */
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
-
-/*
- * turns a 32-bit partial checksum (e.g. from csum_partial) into a
- * 1's complement 16-bit checksum.
- */
-static inline unsigned int csum_fold(unsigned int sum)
-{
-        unsigned int tmp;
-
-        /* swap the two 16-bit halves of sum */
-        __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
-        /* if there is a carry from adding the two 16-bit halves,
-           it will carry from the lower half into the upper half,
-           giving us the correct sum in the upper half. */
-        sum = ~(sum + tmp) >> 16;
-        return sum;
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
-{
-        return csum_fold(csum_partial(buff, len, 0));
-}
-
-/*
- * FIXME: I swiped this one from the sparc and made minor modifications.
- * It may not be correct.  -- Cort
- */
-static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
-                                                   unsigned long daddr,
-                                                   unsigned short len,
-                                                   unsigned short proto,
-                                                   unsigned int sum)
-{
-    __asm__("\n\
-        addc %0,%0,%1 \n\
-        adde %0,%0,%2 \n\
-        adde %0,%0,%3 \n\
-        addze %0,%0 \n\
-        "
-        : "=r" (sum)
-        : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
-    return sum;
-}
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.  ihl is the number
- * of 32-bit words and is always >= 5.
- */
-extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl);
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-extern unsigned short csum_tcpudp_magic(unsigned long saddr,
-                                        unsigned long daddr,
-                                        unsigned short len,
-                                        unsigned short proto,
-                                        unsigned int sum);
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 9483d4bfacf7..43d2ebbc7748 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1087,6 +1087,9 @@ typedef struct im_idma {
 #define SCCR_PCIDF_MSK  0x00000078      /* PCI division factor  */
 #define SCCR_PCIDF_SHIFT 3
 
+#ifndef CPM_IMMR_OFFSET
+#define CPM_IMMR_OFFSET 0x101a8
+#endif
 
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
deleted file mode 100644
index e17c492c870b..000000000000
--- a/include/asm-ppc/cputable.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- *  include/asm-ppc/cputable.h
- *
- *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-
-/* Exposed to userland CPU features */
-#define PPC_FEATURE_32                  0x80000000
-#define PPC_FEATURE_64                  0x40000000
-#define PPC_FEATURE_601_INSTR           0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
-#define PPC_FEATURE_HAS_FPU             0x08000000
-#define PPC_FEATURE_HAS_MMU             0x04000000
-#define PPC_FEATURE_HAS_4xxMAC          0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
-#define PPC_FEATURE_HAS_SPE             0x00800000
-#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
-#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
-#define PPC_FEATURE_NO_TB               0x00100000
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mecanism.
- */
-struct cpu_spec;
-
-typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-
-struct cpu_spec {
-        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
-        unsigned int    pvr_mask;
-        unsigned int    pvr_value;
-
-        char            *cpu_name;
-        unsigned int    cpu_features;           /* Kernel features */
-        unsigned int    cpu_user_features;      /* Userland features */
-
-        /* cache line sizes */
-        unsigned int    icache_bsize;
-        unsigned int    dcache_bsize;
-
-        /* number of performance monitor counters */
-        unsigned int    num_pmcs;
-
-        /* this is called to initialize various CPU bits like L1 cache,
-         * BHT, SPD, etc... from head.S before branching to identify_machine
-         */
-        cpu_setup_t     cpu_setup;
-};
-
-extern struct cpu_spec          cpu_specs[];
-extern struct cpu_spec          *cur_cpu_spec[];
-
-static inline unsigned int cpu_has_feature(unsigned int feature)
-{
-        return cur_cpu_spec[0]->cpu_features & feature;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-#define CPU_FTR_SPLIT_ID_CACHE          0x00000001
-#define CPU_FTR_L2CR                    0x00000002
-#define CPU_FTR_SPEC7450                0x00000004
-#define CPU_FTR_ALTIVEC                 0x00000008
-#define CPU_FTR_TAU                     0x00000010
-#define CPU_FTR_CAN_DOZE                0x00000020
-#define CPU_FTR_USE_TB                  0x00000040
-#define CPU_FTR_604_PERF_MON            0x00000080
-#define CPU_FTR_601                     0x00000100
-#define CPU_FTR_HPTE_TABLE              0x00000200
-#define CPU_FTR_CAN_NAP                 0x00000400
-#define CPU_FTR_L3CR                    0x00000800
-#define CPU_FTR_L3_DISABLE_NAP          0x00001000
-#define CPU_FTR_NAP_DISABLE_L2_PR       0x00002000
-#define CPU_FTR_DUAL_PLL_750FX          0x00004000
-#define CPU_FTR_NO_DPM                  0x00008000
-#define CPU_FTR_HAS_HIGH_BATS           0x00010000
-#define CPU_FTR_NEED_COHERENT           0x00020000
-#define CPU_FTR_NO_BTIC                 0x00040000
-#define CPU_FTR_BIG_PHYS                0x00080000
-
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION               98:
-
-#define END_FTR_SECTION(msk, val)               \
-99:                                             \
-        .section __ftr_fixup,"a";               \
-        .align 2;                               \
-        .long msk;                              \
-        .long val;                              \
-        .long 98b;                              \
-        .long 99b;                              \
-        .previous
-
-#else
-
-#define BEGIN_FTR_SECTION               "98:\n"
-#define END_FTR_SECTION(msk, val)               \
-"99:\n"                                         \
-"       .section __ftr_fixup,\"a\";\n"          \
-"       .align 2;\n"                            \
-"       .long "#msk";\n"                        \
-"       .long "#val";\n"                        \
-"       .long 98b;\n"                           \
-"       .long 99b;\n"                           \
-"       .previous\n"
-
-
-#endif /* __ASSEMBLY__ */
-
-#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
-
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
-
diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h
index 061bfcac1bf1..6e9635114433 100644
--- a/include/asm-ppc/dma-mapping.h
+++ b/include/asm-ppc/dma-mapping.h
@@ -19,7 +19,7 @@
  * allocate the space "normally" and use the cache management functions
  * to ensure it is consistent.
  */
-extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, int gfp);
+extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
 extern void __dma_free_coherent(size_t size, void *vaddr);
 extern void __dma_sync(void *vaddr, size_t size, int direction);
 extern void __dma_sync_page(struct page *page, unsigned long offset,
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
deleted file mode 100644
index c25cc35e6ab5..000000000000
--- a/include/asm-ppc/elf.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifndef __PPC_ELF_H
-#define __PPC_ELF_H
-
-/*
- * ELF register definitions..
- */
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/cputable.h>
-#include <asm/auxvec.h>
-
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE              0
-#define R_PPC_ADDR32            1       /* 32bit absolute address */
-#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
-#define R_PPC_ADDR16            3       /* 16bit absolute address */
-#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
-#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN    8
-#define R_PPC_ADDR14_BRNTAKEN   9
-#define R_PPC_REL24             10      /* PC relative 26 bit */
-#define R_PPC_REL14             11      /* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN     12
-#define R_PPC_REL14_BRNTAKEN    13
-#define R_PPC_GOT16             14
-#define R_PPC_GOT16_LO          15
-#define R_PPC_GOT16_HI          16
-#define R_PPC_GOT16_HA          17
-#define R_PPC_PLTREL24          18
-#define R_PPC_COPY              19
-#define R_PPC_GLOB_DAT          20
-#define R_PPC_JMP_SLOT          21
-#define R_PPC_RELATIVE          22
-#define R_PPC_LOCAL24PC         23
-#define R_PPC_UADDR32           24
-#define R_PPC_UADDR16           25
-#define R_PPC_REL32             26
-#define R_PPC_PLT32             27
-#define R_PPC_PLTREL32          28
-#define R_PPC_PLT16_LO          29
-#define R_PPC_PLT16_HI          30
-#define R_PPC_PLT16_HA          31
-#define R_PPC_SDAREL16          32
-#define R_PPC_SECTOFF           33
-#define R_PPC_SECTOFF_LO        34
-#define R_PPC_SECTOFF_HI        35
-#define R_PPC_SECTOFF_HA        36
-/* Keep this the last entry.  */
-#define R_PPC_NUM               37
-
-#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
-#define ELF_NFPREG      33      /* includes fpscr */
-#define ELF_NVRREG      33      /* includes vscr */
-#define ELF_NEVRREG     34      /* includes acc (as 2) */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_ARCH        EM_PPC
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2MSB
-
-/* General registers */
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* Floating point registers */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-/* Altivec registers */
-typedef __vector128 elf_vrreg_t;
-typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
-
-#ifdef __KERNEL__
-
-struct task_struct;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-
-#define elf_check_arch(x) ((x)->e_machine == EM_PPC)
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         (0x08000000)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
-
-#define ELF_CORE_COPY_REGS(gregs, regs)                         \
-        memcpy((gregs), (regs), sizeof(struct pt_regs));        \
-        memset((char *)(gregs) + sizeof(struct pt_regs), 0,     \
-               sizeof(elf_gregset_t) - sizeof(struct pt_regs));
-
-#define ELF_CORE_COPY_TASK_REGS(t, elfregs)                     \
-        ((t)->thread.regs?                                      \
-         ({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0)
-
-extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
-#define ELF_CORE_COPY_FPREGS(t, fpu)    dump_task_fpu((t), (fpu))
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  This could be done in userspace,
-   but it's not easy, and we've already done it here.  */
-
-#define ELF_HWCAP       (cur_cpu_spec[0]->cpu_user_features)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-
-   For the moment, we have only optimizations for the Intel generations,
-   but that could change... */
-
-#define ELF_PLATFORM    (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-
-extern int dcache_bsize;
-extern int icache_bsize;
-extern int ucache_bsize;
-
-/*
- * The requirements here are:
- * - keep the final alignment of sp (sp & 0xf)
- * - make sure the 32-bit value at the first 16 byte aligned position of
- *   AUXV is greater than 16 for glibc compatibility.
- *   AT_IGNOREPPC is used for that.
- * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
- *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
- */
-#define ARCH_DLINFO                                                     \
-do {                                                                    \
-        /* Handle glibc compatibility. */                               \
-        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
-        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
-        /* Cache size items */                                          \
-        NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
-        NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
-        NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
- } while (0)
-
-#endif /* __KERNEL__ */
-#endif
diff --git a/include/asm-ppc/hw_irq.h b/include/asm-ppc/hw_irq.h
deleted file mode 100644
index 47dc7990fb26..000000000000
--- a/include/asm-ppc/hw_irq.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifdef __KERNEL__
-#ifndef _PPC_HW_IRQ_H
-#define _PPC_HW_IRQ_H
-
-#include <asm/ptrace.h>
-#include <asm/reg.h>
-
-extern void timer_interrupt(struct pt_regs *);
-
-#define INLINE_IRQS
-
-#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
-
-#ifdef INLINE_IRQS
-
-static inline void local_irq_disable(void)
-{
-        unsigned long msr;
-        msr = mfmsr();
-        mtmsr(msr & ~MSR_EE);
-        __asm__ __volatile__("": : :"memory");
-}
-
-static inline void local_irq_enable(void)
-{
-        unsigned long msr;
-        __asm__ __volatile__("": : :"memory");
-        msr = mfmsr();
-        mtmsr(msr | MSR_EE);
-}
-
-static inline void local_irq_save_ptr(unsigned long *flags)
-{
-        unsigned long msr;
-        msr = mfmsr();
-        *flags = msr;
-        mtmsr(msr & ~MSR_EE);
-        __asm__ __volatile__("": : :"memory");
-}
-
-#define local_save_flags(flags)         ((flags) = mfmsr())
-#define local_irq_save(flags)           local_irq_save_ptr(&flags)
-#define local_irq_restore(flags)        mtmsr(flags)
-
-#else
-
-extern void local_irq_enable(void);
-extern void local_irq_disable(void);
-extern void local_irq_restore(unsigned long);
-extern void local_save_flags_ptr(unsigned long *);
-
-#define local_save_flags(flags) local_save_flags_ptr(&flags)
-#define local_irq_save(flags) ({local_save_flags(flags);local_irq_disable();})
-
-#endif
-
-extern void do_lost_interrupts(unsigned long);
-
-#define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);})
-#define unmask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->enable) irq_desc[irq].handler->enable(irq);})
-#define ack_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->ack) irq_desc[irq].handler->ack(irq);})
-
-/* Should we handle this via lost interrupts and IPIs or should we don't care like
- * we do now ? --BenH.
- */
-struct hw_interrupt_type;
-static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
-
-
-#endif /* _PPC_HW_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/i8259.h b/include/asm-ppc/i8259.h
deleted file mode 100644
index 091b71295de4..000000000000
--- a/include/asm-ppc/i8259.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _PPC_KERNEL_i8259_H
-#define _PPC_KERNEL_i8259_H
-
-#include <linux/irq.h>
-
-extern struct hw_interrupt_type i8259_pic;
-
-extern void i8259_init(long intack_addr);
-extern int i8259_irq(struct pt_regs *regs);
-
-#endif /* _PPC_KERNEL_i8259_H */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 94d83998a759..f7f614dfc648 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -8,6 +8,7 @@
 
 #include <asm/page.h>
 #include <asm/byteorder.h>
+#include <asm/synch.h>
 #include <asm/mmu.h>
 
 #define SIO_CONFIG_RA   0x398
@@ -440,16 +441,6 @@ extern inline void * phys_to_virt(unsigned long address)
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 
-/*
- * Enforce In-order Execution of I/O:
- * Acts as a barrier to ensure all previous I/O accesses have
- * completed before any further ones are issued.
- */
-extern inline void eieio(void)
-{
-        __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
 /* Enforce in-order execution of data I/O.
  * No distinction between read/write on PPC; use eieio for all three.
  */
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h
deleted file mode 100644
index 6d6fc78731e5..000000000000
--- a/include/asm-ppc/kmap_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_PPC_SYNC_PAGE,
-        KM_PPC_SYNC_ICACHE,
-        KM_TYPE_NR
-};
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index 1d4ab70a56f3..f01255bd1dc3 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -98,7 +98,7 @@ struct machdep_calls {
 
         /* Get access protection for /dev/mem */
         pgprot_t        (*phys_mem_access_prot)(struct file *file,
-                                                unsigned long offset,
+                                                unsigned long pfn,
                                                 unsigned long size,
                                                 pgprot_t vma_prot);
 
@@ -167,7 +167,7 @@ extern sys_ctrler_t sys_ctrler;
 
 #ifdef CONFIG_SMP
 struct smp_ops_t {
-        void  (*message_pass)(int target, int msg, unsigned long data, int wait);
+        void  (*message_pass)(int target, int msg);
         int   (*probe)(void);
         void  (*kick_cpu)(int nr);
         void  (*setup_cpu)(int nr);
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index afe26ffc2e2d..4f152cca13c1 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -164,13 +164,11 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                              struct task_struct *tsk)
 {
 #ifdef CONFIG_ALTIVEC
-        asm volatile (
- BEGIN_FTR_SECTION
-        "dssall;\n"
+        if (cpu_has_feature(CPU_FTR_ALTIVEC))
+        asm volatile ("dssall;\n"
 #ifndef CONFIG_POWER4
          "sync;\n" /* G4 needs a sync here, G5 apparently not */
 #endif
- END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
          : : );
 #endif /* CONFIG_ALTIVEC */
 
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index 9694eca16e92..321452695039 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -92,6 +92,10 @@ enum ppc_sys_devices {
 extern unsigned char __res[];
 #endif
 
+#ifndef BOARD_CHIP_NAME
+#define BOARD_CHIP_NAME ""
+#endif
+
 #endif /* CONFIG_8260 */
 #endif /* !__ASM_PPC_MPC8260_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 516984ee14b5..d98db980cd49 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -67,6 +67,8 @@ extern unsigned char __res[];
 #define MPC85xx_DMA3_SIZE       (0x00080)
 #define MPC85xx_ENET1_OFFSET    (0x24000)
 #define MPC85xx_ENET1_SIZE      (0x01000)
+#define MPC85xx_MIIM_OFFSET     (0x24520)
+#define MPC85xx_MIIM_SIZE       (0x00018)
 #define MPC85xx_ENET2_OFFSET    (0x25000)
 #define MPC85xx_ENET2_SIZE      (0x01000)
 #define MPC85xx_ENET3_OFFSET    (0x26000)
@@ -132,6 +134,7 @@ enum ppc_sys_devices {
         MPC85xx_eTSEC3,
         MPC85xx_eTSEC4,
         MPC85xx_IIC2,
+        MPC85xx_MDIO,
 };
 
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
index 208a2e11daee..46f159cf589e 100644
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -113,6 +113,10 @@ enum ppc_sys_devices {
         MPC8xx_CPM_USB,
 };
 
+#ifndef BOARD_CHIP_NAME
+#define BOARD_CHIP_NAME ""
+#endif
+
 #endif /* !__ASSEMBLY__ */
 #endif /* CONFIG_8xx */
 #endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
index 7848aa610c05..ec2f46629ca2 100644
--- a/include/asm-ppc/open_pic.h
+++ b/include/asm-ppc/open_pic.h
@@ -58,8 +58,7 @@ extern int openpic_get_irq(struct pt_regs *regs);
 extern void openpic_reset_processor_phys(u_int cpumask);
 extern void openpic_setup_ISU(int isu_num, unsigned long addr);
 extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
-extern void smp_openpic_message_pass(int target, int msg, unsigned long data,
-                                     int wait);
+extern void smp_openpic_message_pass(int target, int msg);
 extern void openpic_set_k2_cascade(int irq);
 extern void openpic_set_priority(u_int pri);
 extern u_int openpic_get_priority(void);
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
index 4789dc024240..fc44f7ca62d7 100644
--- a/include/asm-ppc/page.h
+++ b/include/asm-ppc/page.h
@@ -34,6 +34,17 @@ typedef unsigned long pte_basic_t;
 #define PTE_FMT         "%.8lx"
 #endif
 
+/* align addr on a size boundary - adjust address up/down if needed */
+#define _ALIGN_UP(addr,size)    (((addr)+((size)-1))&(~((size)-1)))
+#define _ALIGN_DOWN(addr,size)  ((addr)&(~((size)-1)))
+
+/* align addr on a size boundary - adjust address up if needed */
+#define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)        _ALIGN(addr, PAGE_SIZE)
+
+
 #undef STRICT_MM_TYPECHECKS
 
 #ifdef STRICT_MM_TYPECHECKS
@@ -76,13 +87,6 @@ typedef unsigned long pgprot_t;
 
 #endif
 
-
-/* align addr on a size boundary - adjust address up if needed -- Cort */
-#define _ALIGN(addr,size)       (((addr)+(size)-1)&(~((size)-1)))
-
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
-
 struct page;
 extern void clear_pages(void *page, int order);
 static inline void clear_page(void *page) { clear_pages(page, 0); }
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
index ffa423456c2b..e58c78f90a5a 100644
--- a/include/asm-ppc/pci-bridge.h
+++ b/include/asm-ppc/pci-bridge.h
@@ -79,6 +79,11 @@ struct pci_controller {
         struct resource mem_space;
 };
 
+static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
+{
+        return bus->sysdata;
+}
+
 /* These are used for config access before all the PCI probing
    has been done. */
 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index 9dd06cd40096..61434edbad7b 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -24,9 +24,9 @@ struct pci_dev;
  * Set this to 1 if you want the kernel to re-assign all PCI
  * bus numbers
  */
-extern int pci_assign_all_busses;
+extern int pci_assign_all_buses;
 
-#define pcibios_assign_all_busses()     (pci_assign_all_busses)
+#define pcibios_assign_all_busses()     (pci_assign_all_buses)
 #define pcibios_scan_all_fns(a, b)      0
 
 #define PCIBIOS_MIN_IO          0x1000
@@ -126,7 +126,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev);
 
 struct file;
 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
-                                         unsigned long offset,
+                                         unsigned long pfn,
                                          unsigned long size,
                                          pgprot_t prot);
 
diff --git a/include/asm-ppc/perfmon.h b/include/asm-ppc/perfmon.h
deleted file mode 100644
index 5e7a89c47b5b..000000000000
--- a/include/asm-ppc/perfmon.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __PERFMON_H
-#define __PERFMON_H
-
-extern void (*perf_irq)(struct pt_regs *);
-
-int request_perfmon_irq(void (*handler)(struct pt_regs *));
-void free_perfmon_irq(void);
-
-#ifdef CONFIG_FSL_BOOKE
-void init_pmc_stop(int ctr);
-void set_pmc_event(int ctr, int event);
-void set_pmc_user_kernel(int ctr, int user, int kernel);
-void set_pmc_marked(int ctr, int mark0, int mark1);
-void pmc_start_ctr(int ctr, int enable);
-void pmc_start_ctrs(int enable);
-void pmc_stop_ctrs(void);
-void dump_pmcs(void);
-
-extern struct op_ppc32_model op_model_fsl_booke;
-#endif
-
-#endif /* __PERFMON_H */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index eee601bb9ada..b28a713ba862 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -705,7 +705,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
                                      unsigned long size, pgprot_t vma_prot);
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h
deleted file mode 100644
index a14a82abe8d2..000000000000
--- a/include/asm-ppc/posix_types.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef _PPC_POSIX_TYPES_H
-#define _PPC_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long   __kernel_ino_t;
-typedef unsigned int    __kernel_mode_t;
-typedef unsigned short  __kernel_nlink_t;
-typedef long            __kernel_off_t;
-typedef int             __kernel_pid_t;
-typedef unsigned int    __kernel_uid_t;
-typedef unsigned int    __kernel_gid_t;
-typedef unsigned int    __kernel_size_t;
-typedef int             __kernel_ssize_t;
-typedef long            __kernel_ptrdiff_t;
-typedef long            __kernel_time_t;
-typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
-typedef int             __kernel_timer_t;
-typedef int             __kernel_clockid_t;
-typedef int             __kernel_daddr_t;
-typedef char *          __kernel_caddr_t;
-typedef short             __kernel_ipc_pid_t;
-typedef unsigned short  __kernel_uid16_t;
-typedef unsigned short  __kernel_gid16_t;
-typedef unsigned int    __kernel_uid32_t;
-typedef unsigned int    __kernel_gid32_t;
-
-typedef unsigned int    __kernel_old_uid_t;
-typedef unsigned int    __kernel_old_gid_t;
-typedef unsigned int    __kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long       __kernel_loff_t;
-#endif
-
-typedef struct {
-        int     val[2];
-} __kernel_fsid_t;
-
-#ifndef __GNUC__
-
-#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-#define __FD_ZERO(set)  \
-  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
-
-#else /* __GNUC__ */
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
-    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *p)
-{
-        unsigned int *tmp = (unsigned int *)p->fds_bits;
-        int i;
-
-        if (__builtin_constant_p(__FDSET_LONGS)) {
-                switch (__FDSET_LONGS) {
-                        case 8:
-                                tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
-                                tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
-                                return;
-                }
-        }
-        i = __FDSET_LONGS;
-        while (i) {
-                i--;
-                *tmp = 0;
-                tmp++;
-        }
-}
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-#endif /* __GNUC__ */
-#endif /* _PPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 549f44843c5e..bba5305c29ed 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -18,7 +18,7 @@
 #define __ASM_PPC_SYS_H
 
 #include <linux/init.h>
-#include <linux/device.h>
+#include <linux/platform_device.h>
 #include <linux/types.h>
 
 #if defined(CONFIG_8260)
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
index 7043c164b537..c34fb4e37a97 100644
--- a/include/asm-ppc/ptrace.h
+++ b/include/asm-ppc/ptrace.h
@@ -57,7 +57,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 
 #define force_successful_syscall_return()   \
         do { \
-                current_thread_info()->local_flags |= _TIFL_FORCE_NOERROR; \
+                current_thread_info()->syscall_noerror = 1; \
         } while(0)
 
 /*
diff --git a/include/asm-ppc/rwsem.h b/include/asm-ppc/rwsem.h
deleted file mode 100644
index 3e738f483c11..000000000000
--- a/include/asm-ppc/rwsem.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * include/asm-ppc/rwsem.h: R/W semaphores for PPC using the stuff
- * in lib/rwsem.c.  Adapted largely from include/asm-i386/rwsem.h
- * by Paul Mackerras <paulus@samba.org>.
- */
-
-#ifndef _PPC_RWSEM_H
-#define _PPC_RWSEM_H
-
-#ifdef __KERNEL__
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <asm/atomic.h>
-#include <asm/system.h>
-
-/*
- * the semaphore definition
- */
-struct rw_semaphore {
-        /* XXX this should be able to be an atomic_t  -- paulus */
-        signed long             count;
-#define RWSEM_UNLOCKED_VALUE            0x00000000
-#define RWSEM_ACTIVE_BIAS               0x00000001
-#define RWSEM_ACTIVE_MASK               0x0000ffff
-#define RWSEM_WAITING_BIAS              (-0x00010000)
-#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-        spinlock_t              wait_lock;
-        struct list_head        wait_list;
-#if RWSEM_DEBUG
-        int                     debug;
-#endif
-};
-
-/*
- * initialisation
- */
-#if RWSEM_DEBUG
-#define __RWSEM_DEBUG_INIT      , 0
-#else
-#define __RWSEM_DEBUG_INIT      /* */
-#endif
-
-#define __RWSEM_INITIALIZER(name) \
-        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-          LIST_HEAD_INIT((name).wait_list) \
-          __RWSEM_DEBUG_INIT }
-
-#define DECLARE_RWSEM(name)             \
-        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-
-extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
-
-static inline void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-#if RWSEM_DEBUG
-        sem->debug = 0;
-#endif
-}
-
-/*
- * lock for reading
- */
-static inline void __down_read(struct rw_semaphore *sem)
-{
-        if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
-                smp_wmb();
-        else
-                rwsem_down_read_failed(sem);
-}
-
-static inline int __down_read_trylock(struct rw_semaphore *sem)
-{
-        int tmp;
-
-        while ((tmp = sem->count) >= 0) {
-                if (tmp == cmpxchg(&sem->count, tmp,
-                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
-                        smp_wmb();
-                        return 1;
-                }
-        }
-        return 0;
-}
-
-/*
- * lock for writing
- */
-static inline void __down_write(struct rw_semaphore *sem)
-{
-        int tmp;
-
-        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
-                                (atomic_t *)(&sem->count));
-        if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
-                smp_wmb();
-        else
-                rwsem_down_write_failed(sem);
-}
-
-static inline int __down_write_trylock(struct rw_semaphore *sem)
-{
-        int tmp;
-
-        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
-                      RWSEM_ACTIVE_WRITE_BIAS);
-        smp_wmb();
-        return tmp == RWSEM_UNLOCKED_VALUE;
-}
-
-/*
- * unlock after reading
- */
-static inline void __up_read(struct rw_semaphore *sem)
-{
-        int tmp;
-
-        smp_wmb();
-        tmp = atomic_dec_return((atomic_t *)(&sem->count));
-        if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
-                rwsem_wake(sem);
-}
-
-/*
- * unlock after writing
- */
-static inline void __up_write(struct rw_semaphore *sem)
-{
-        smp_wmb();
-        if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
-                              (atomic_t *)(&sem->count)) < 0)
-                rwsem_wake(sem);
-}
-
-/*
- * implement atomic add functionality
- */
-static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
-{
-        atomic_add(delta, (atomic_t *)(&sem->count));
-}
-
-/*
- * downgrade write lock to read lock
- */
-static inline void __downgrade_write(struct rw_semaphore *sem)
-{
-        int tmp;
-
-        smp_wmb();
-        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
-        if (tmp < 0)
-                rwsem_downgrade_wake(sem);
-}
-
-/*
- * implement exchange and add functionality
- */
-static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
-{
-        smp_mb();
-        return atomic_add_return(delta, (atomic_t *)(&sem->count));
-}
-
-#endif /* __KERNEL__ */
-#endif /* _PPC_RWSEM_XADD_H */
diff --git a/include/asm-ppc/scatterlist.h b/include/asm-ppc/scatterlist.h
deleted file mode 100644
index f21f18f56548..000000000000
--- a/include/asm-ppc/scatterlist.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_SCATTERLIST_H
-#define _PPC_SCATTERLIST_H
-
-#include <asm/dma.h>
-
-struct scatterlist {
-        struct page     *page;
-        unsigned int    offset;
-        dma_addr_t      dma_address;
-        unsigned int    length;
-};
-
-/*
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns, or alternatively stop on the first sg_dma_len(sg) which
- * is 0.
- */
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->length)
-
-#endif /* !(_PPC_SCATTERLIST_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/seccomp.h b/include/asm-ppc/seccomp.h
deleted file mode 100644
index 666c4da96d87..000000000000
--- a/include/asm-ppc/seccomp.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _ASM_SECCOMP_H
-
-#include <linux/unistd.h>
-
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_rt_sigreturn
-
-#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-ppc/sections.h b/include/asm-ppc/sections.h
deleted file mode 100644
index ba8f43ac9bf3..000000000000
--- a/include/asm-ppc/sections.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_SECTIONS_H
-#define _PPC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#define __pmac __attribute__ ((__section__ (".pmac.text")))
-#define __pmacdata __attribute__ ((__section__ (".pmac.data")))
-#define __pmacfunc(__argpmac) \
-        __argpmac __pmac; \
-        __argpmac
-        
-#define __prep __attribute__ ((__section__ (".prep.text")))
-#define __prepdata __attribute__ ((__section__ (".prep.data")))
-#define __prepfunc(__argprep) \
-        __argprep __prep; \
-        __argprep
-
-#define __chrp __attribute__ ((__section__ (".chrp.text")))
-#define __chrpdata __attribute__ ((__section__ (".chrp.data")))
-#define __chrpfunc(__argchrp) \
-        __argchrp __chrp; \
-        __argchrp
-
-/* this is actually just common chrp/pmac code, not OF code -- Cort */
-#define __openfirmware __attribute__ ((__section__ (".openfirmware.text")))
-#define __openfirmwaredata __attribute__ ((__section__ (".openfirmware.data")))
-#define __openfirmwarefunc(__argopenfirmware) \
-        __argopenfirmware __openfirmware; \
-        __argopenfirmware
-        
-#endif /* _PPC_SECTIONS_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/semaphore.h b/include/asm-ppc/semaphore.h
deleted file mode 100644
index 89e6e73be08c..000000000000
--- a/include/asm-ppc/semaphore.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef _PPC_SEMAPHORE_H
-#define _PPC_SEMAPHORE_H
-
-/*
- * Swiped from asm-sparc/semaphore.h and modified
- * -- Cort (cort@cs.nmt.edu)
- *
- * Stole some rw spinlock-based semaphore stuff from asm-alpha/semaphore.h
- * -- Ani Joshi (ajoshi@unixbox.com)
- *
- * Remove spinlock-based RW semaphores; RW semaphore definitions are
- * now in rwsem.h and we use the generic lib/rwsem.c implementation.
- * Rework semaphores to use atomic_dec_if_positive.
- * -- Paul Mackerras (paulus@samba.org)
- */
-
-#ifdef __KERNEL__
-
-#include <asm/atomic.h>
-#include <asm/system.h>
-#include <linux/wait.h>
-#include <linux/rwsem.h>
-
-struct semaphore {
-        /*
-         * Note that any negative value of count is equivalent to 0,
-         * but additionally indicates that some process(es) might be
-         * sleeping on `wait'.
-         */
-        atomic_t count;
-        wait_queue_head_t wait;
-};
-
-#define __SEMAPHORE_INITIALIZER(name, n)                                \
-{                                                                       \
-        .count          = ATOMIC_INIT(n),                               \
-        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
-}
-
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
-
-#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
-        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
-
-#define DECLARE_MUTEX(name)             __DECLARE_SEMAPHORE_GENERIC(name, 1)
-#define DECLARE_MUTEX_LOCKED(name)      __DECLARE_SEMAPHORE_GENERIC(name, 0)
-
-static inline void sema_init (struct semaphore *sem, int val)
-{
-        atomic_set(&sem->count, val);
-        init_waitqueue_head(&sem->wait);
-}
-
-static inline void init_MUTEX (struct semaphore *sem)
-{
-        sema_init(sem, 1);
-}
-
-static inline void init_MUTEX_LOCKED (struct semaphore *sem)
-{
-        sema_init(sem, 0);
-}
-
-extern void __down(struct semaphore * sem);
-extern int  __down_interruptible(struct semaphore * sem);
-extern void __up(struct semaphore * sem);
-
-extern inline void down(struct semaphore * sem)
-{
-        might_sleep();
-
-        /*
-         * Try to get the semaphore, take the slow path if we fail.
-         */
-        if (atomic_dec_return(&sem->count) < 0)
-                __down(sem);
-        smp_wmb();
-}
-
-extern inline int down_interruptible(struct semaphore * sem)
-{
-        int ret = 0;
-
-        might_sleep();
-
-        if (atomic_dec_return(&sem->count) < 0)
-                ret = __down_interruptible(sem);
-        smp_wmb();
-        return ret;
-}
-
-extern inline int down_trylock(struct semaphore * sem)
-{
-        int ret;
-
-        ret = atomic_dec_if_positive(&sem->count) < 0;
-        smp_wmb();
-        return ret;
-}
-
-extern inline void up(struct semaphore * sem)
-{
-        smp_wmb();
-        if (atomic_inc_return(&sem->count) <= 0)
-                __up(sem);
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* !(_PPC_SEMAPHORE_H) */
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
index 829481c0a9dc..30e9268a888c 100644
--- a/include/asm-ppc/smp.h
+++ b/include/asm-ppc/smp.h
@@ -35,6 +35,7 @@ extern cpumask_t cpu_possible_map;
 extern unsigned long smp_proc_in_lock[];
 extern volatile unsigned long cpu_callin_map[];
 extern int smp_tb_synchronized;
+extern struct smp_ops_t *smp_ops;
 
 extern void smp_send_tlb_invalidate(int);
 extern void smp_send_xmon_break(int cpu);
@@ -45,32 +46,31 @@ extern int __cpu_disable(void);
 extern void __cpu_die(unsigned int cpu);
 extern void cpu_die(void) __attribute__((noreturn));
 
-#define NO_PROC_ID              0xFF            /* No processor magic marker */
-#define PROC_CHANGE_PENALTY     20
-
 #define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 extern int __cpu_up(unsigned int cpu);
 
 extern int smp_hw_index[];
-#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
-
-struct klock_info_struct {
-        unsigned long kernel_flag;
-        unsigned char akp;
-};
-
-extern struct klock_info_struct klock_info;
-#define KLOCK_HELD       0xffffffff
-#define KLOCK_CLEAR      0x0
-
+#define hard_smp_processor_id()         (smp_hw_index[smp_processor_id()])
+#define get_hard_smp_processor_id(cpu)  (smp_hw_index[(cpu)])
+#define set_hard_smp_processor_id(cpu, phys)\
+                                        (smp_hw_index[(cpu)] = (phys))
+ 
 #endif /* __ASSEMBLY__ */
 
 #else /* !(CONFIG_SMP) */
 
 static inline void cpu_die(void) { }
+#define get_hard_smp_processor_id(cpu) 0
+#define set_hard_smp_processor_id(cpu, phys)
+#define hard_smp_processor_id() 0
 
 #endif /* !(CONFIG_SMP) */
 
+#ifndef __ASSEMBLY__
+extern int boot_cpuid;
+extern int boot_cpuid_phys;
+#endif
+
 #endif /* !(_PPC_SMP_H) */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
index 20edcf2a6e0c..5c64b75f0295 100644
--- a/include/asm-ppc/spinlock.h
+++ b/include/asm-ppc/spinlock.h
@@ -9,7 +9,7 @@
  * (the type definitions are in asm/raw_spinlock_types.h)
  */
 
-#define __raw_spin_is_locked(x)         ((x)->lock != 0)
+#define __raw_spin_is_locked(x)         ((x)->slock != 0)
 #define __raw_spin_unlock_wait(lock) \
         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
@@ -31,17 +31,17 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         bne-    2b\n\
         isync"
         : "=&r"(tmp)
-        : "r"(&lock->lock), "r"(1)
+        : "r"(&lock->slock), "r"(1)
         : "cr0", "memory");
 }
 
 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
         __asm__ __volatile__("eieio     # __raw_spin_unlock": : :"memory");
-        lock->lock = 0;
+        lock->slock = 0;
 }
 
-#define __raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock))
+#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
 
 /*
  * Read-write spinlocks, allowing multiple readers
diff --git a/include/asm-ppc/spinlock_types.h b/include/asm-ppc/spinlock_types.h
deleted file mode 100644
index 7919ccc75b8a..000000000000
--- a/include/asm-ppc/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
-        volatile unsigned long lock;
-} raw_spinlock_t;
-
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
-
-typedef struct {
-        volatile signed int lock;
-} raw_rwlock_t;
-
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
-
-#endif
diff --git a/include/asm-ppc/statfs.h b/include/asm-ppc/statfs.h
deleted file mode 100644
index 807c69954a1b..000000000000
--- a/include/asm-ppc/statfs.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _PPC_STATFS_H
-#define _PPC_STATFS_H
-
-#include <asm-generic/statfs.h>
-#endif
-
-
-
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
index d754ab570fe0..bd99cb53a19f 100644
--- a/include/asm-ppc/system.h
+++ b/include/asm-ppc/system.h
@@ -70,25 +70,47 @@ extern void _set_L3CR(unsigned long);
 #endif
 extern void via_cuda_init(void);
 extern void pmac_nvram_init(void);
+extern void chrp_nvram_init(void);
 extern void read_rtc_time(void);
 extern void pmac_find_display(void);
 extern void giveup_fpu(struct task_struct *);
 extern void enable_kernel_fp(void);
+extern void flush_fp_to_thread(struct task_struct *);
 extern void enable_kernel_altivec(void);
 extern void giveup_altivec(struct task_struct *);
 extern void load_up_altivec(struct task_struct *);
+extern int emulate_altivec(struct pt_regs *);
 extern void giveup_spe(struct task_struct *);
 extern void load_up_spe(struct task_struct *);
 extern int fix_alignment(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
-extern void cvt_df(double *from, float *to, unsigned long *fpscr);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
+
+#ifdef CONFIG_ALTIVEC
+extern void flush_altivec_to_thread(struct task_struct *);
+#else
+static inline void flush_altivec_to_thread(struct task_struct *t)
+{
+}
+#endif
+
+#ifdef CONFIG_SPE
+extern void flush_spe_to_thread(struct task_struct *);
+#else
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
+#endif
+
 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 extern void cacheable_memzero(void *p, unsigned int nb);
 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern void die(const char *, struct pt_regs *, long);
+extern int die(const char *, struct pt_regs *, long);
 extern void _exception(int, struct pt_regs *, int, unsigned long);
+void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
+
 #ifdef CONFIG_BOOKE_WDT
 extern u32 booke_wdt_enabled;
 extern u32 booke_wdt_period;
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h
deleted file mode 100644
index 27903db42efc..000000000000
--- a/include/asm-ppc/thread_info.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* thread_info.h: PPC low-level thread information
- * adapted from the i386 version by Paul Mackerras
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-struct thread_info {
-        struct task_struct      *task;          /* main task structure */
-        struct exec_domain      *exec_domain;   /* execution domain */
-        unsigned long           flags;          /* low level flags */
-        unsigned long           local_flags;    /* non-racy flags */
-        int                     cpu;            /* cpu we're on */
-        int                     preempt_count;  /* 0 => preemptable,
-                                                   <0 => BUG */
-        struct restart_block    restart_block;
-};
-
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task =         &tsk,                   \
-        .exec_domain =  &default_exec_domain,   \
-        .flags =        0,                      \
-        .local_flags =  0,                      \
-        .cpu =          0,                      \
-        .preempt_count = 1,                     \
-        .restart_block = {                      \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-        struct thread_info *ti;
-        __asm__("rlwinm %0,1,0,0,18" : "=r"(ti));
-        return ti;
-}
-
-/* thread information allocation */
-#define alloc_thread_info(tsk) ((struct thread_info *) \
-                                __get_free_pages(GFP_KERNEL, 1))
-#define free_thread_info(ti)    free_pages((unsigned long) (ti), 1)
-#define get_thread_info(ti)     get_task_struct((ti)->task)
-#define put_thread_info(ti)     put_task_struct((ti)->task)
-#endif /* __ASSEMBLY__ */
-
-/*
- * Size of kernel stack for each process.
- */
-#define THREAD_SIZE             8192    /* 2 pages */
-
-#define PREEMPT_ACTIVE          0x10000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
-#define TIF_SIGPENDING          2       /* signal pending */
-#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      4       /* true if poll_idle() is polling
-                                           TIF_NEED_RESCHED */
-#define TIF_MEMDIE              5
-#define TIF_SYSCALL_AUDIT       6       /* syscall auditing active */
-#define TIF_SECCOMP             7      /* secure computing */
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
-
-#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
-
-/*
- * Non racy (local) flags bit numbers
- */
-#define TIFL_FORCE_NOERROR      0       /* don't return error from current
-                                           syscall even if result < 0 */
-
-/* as above, but as bit values */
-#define _TIFL_FORCE_NOERROR     (1<<TIFL_FORCE_NOERROR)
-
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h
deleted file mode 100644
index 77dc24d7d2ad..000000000000
--- a/include/asm-ppc/types.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _PPC_TYPES_H
-#define _PPC_TYPES_H
-
-#ifndef __ASSEMBLY__
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-typedef struct {
-        __u32 u[4];
-} __vector128;
-
-/*
- * XXX allowed outside of __KERNEL__ for now, until glibc gets
- * a proper set of asm headers of its own.  -- paulus
- */
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#define BITS_PER_LONG 32
-
-#ifndef __ASSEMBLY__
-
-#include <linux/config.h>
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-typedef __vector128 vector128;
-
-/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/include/asm-ppc/vga.h b/include/asm-ppc/vga.h
deleted file mode 100644
index c5864734e3e1..000000000000
--- a/include/asm-ppc/vga.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *      Access to VGA videoram
- *
- *      (c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-#ifdef __KERNEL__
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
-
-#include <asm/io.h>
-
-#include <linux/config.h>
-
-#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
-
-#define VT_BUF_HAVE_RW
-/*
- *  These are only needed for supporting VGA or MDA text mode, which use little
- *  endian byte ordering.
- *  In other cases, we can optimize by using native byte ordering and
- *  <linux/vt_buffer.h> has already done the right job for us.
- */
-
-extern inline void scr_writew(u16 val, volatile u16 *addr)
-{
-    st_le16(addr, val);
-}
-
-extern inline u16 scr_readw(volatile const u16 *addr)
-{
-    return ld_le16(addr);
-}
-
-#define VT_BUF_HAVE_MEMCPYW
-#define scr_memcpyw     memcpy
-
-#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
-
-extern unsigned long vgacon_remap_base;
-#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/xmon.h b/include/asm-ppc/xmon.h
deleted file mode 100644
index 042b83e6680d..000000000000
--- a/include/asm-ppc/xmon.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __PPC_XMON_H
-#define __PPC_XMON_H
-#ifdef __KERNEL__
-
-struct pt_regs;
-
-extern void xmon(struct pt_regs *excp);
-extern void xmon_printf(const char *fmt, ...);
-extern void xmon_map_scc(void);
-extern int xmon_bpt(struct pt_regs *regs);
-extern int xmon_sstep(struct pt_regs *regs);
-extern int xmon_iabr_match(struct pt_regs *regs);
-extern int xmon_dabr_match(struct pt_regs *regs);
-extern void (*xmon_fault_handler)(struct pt_regs *regs);
-
-#endif
-#endif
diff --git a/include/asm-ppc64/abs_addr.h b/include/asm-ppc64/abs_addr.h
index 84c24d4cdb71..dc3fc3fefef2 100644
--- a/include/asm-ppc64/abs_addr.h
+++ b/include/asm-ppc64/abs_addr.h
@@ -63,4 +63,11 @@ static inline unsigned long phys_to_abs(unsigned long pa)
 #define virt_to_abs(va) phys_to_abs(__pa(va))
 #define abs_to_virt(aa) __va(aa)
 
+/*
+ * Converts Virtual Address to Real Address for
+ * Legacy iSeries Hypervisor calls
+ */
+#define iseries_hv_addr(virtaddr)       \
+        (0x8000000000000000 | virt_to_abs(virtaddr))
+
 #endif /* _ABS_ADDR_H */
diff --git a/include/asm-ppc64/atomic.h b/include/asm-ppc64/atomic.h
deleted file mode 100644
index 0e5f25e83bc0..000000000000
--- a/include/asm-ppc64/atomic.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * PowerPC64 atomic operations
- *
- * Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
- * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_PPC64_ATOMIC_H_ 
-#define _ASM_PPC64_ATOMIC_H_
-
-#include <asm/memory.h>
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v)          ((v)->counter)
-#define atomic_set(v,i)         (((v)->counter) = (i))
-
-static __inline__ void atomic_add(int a, atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%3         # atomic_add\n\
-        add     %0,%2,%0\n\
-        stwcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-
-static __inline__ int atomic_add_return(int a, atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%2         # atomic_add_return\n\
-        add     %0,%1,%0\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (a), "r" (&v->counter)
-        : "cc", "memory");
-
-        return t;
-}
-
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-
-static __inline__ void atomic_sub(int a, atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%3         # atomic_sub\n\
-        subf    %0,%2,%0\n\
-        stwcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-
-static __inline__ int atomic_sub_return(int a, atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%2         # atomic_sub_return\n\
-        subf    %0,%1,%0\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (a), "r" (&v->counter)
-        : "cc", "memory");
-
-        return t;
-}
-
-static __inline__ void atomic_inc(atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%2         # atomic_inc\n\
-        addic   %0,%0,1\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%1         # atomic_inc_return\n\
-        addic   %0,%0,1\n\
-        stwcx.  %0,0,%1\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (&v->counter)
-        : "cc", "memory");
-
-        return t;
-}
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-static __inline__ void atomic_dec(atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%2         # atomic_dec\n\
-        addic   %0,%0,-1\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%1         # atomic_dec_return\n\
-        addic   %0,%0,-1\n\
-        stwcx.  %0,0,%1\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (&v->counter)
-        : "cc", "memory");
-
-        return t;
-}
-
-#define atomic_sub_and_test(a, v)       (atomic_sub_return((a), (v)) == 0)
-#define atomic_dec_and_test(v)          (atomic_dec_return((v)) == 0)
-
-/*
- * Atomically test *v and decrement if it is greater than 0.
- * The function returns the old value of *v minus 1.
- */
-static __inline__ int atomic_dec_if_positive(atomic_t *v)
-{
-        int t;
-
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
-        addic.  %0,%0,-1\n\
-        blt-    2f\n\
-        stwcx.  %0,0,%1\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        "\n\
-2:"     : "=&r" (t)
-        : "r" (&v->counter)
-        : "cc", "memory");
-
-        return t;
-}
-
-#define smp_mb__before_atomic_dec()     smp_mb()
-#define smp_mb__after_atomic_dec()      smp_mb()
-#define smp_mb__before_atomic_inc()     smp_mb()
-#define smp_mb__after_atomic_inc()      smp_mb()
-
-#endif /* _ASM_PPC64_ATOMIC_H_ */
diff --git a/include/asm-ppc64/bitops.h b/include/asm-ppc64/bitops.h
index a0f831224f96..dbfa42ef4a99 100644
--- a/include/asm-ppc64/bitops.h
+++ b/include/asm-ppc64/bitops.h
@@ -42,7 +42,7 @@
 
 #ifdef __KERNEL__
 
-#include <asm/memory.h>
+#include <asm/synch.h>
 
 /*
  * clear_bit doesn't imply a memory barrier
diff --git a/include/asm-ppc64/bootinfo.h b/include/asm-ppc64/bootinfo.h
deleted file mode 100644
index f55e7cb48f46..000000000000
--- a/include/asm-ppc64/bootinfo.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Non-machine dependent bootinfo structure.  Basic idea
- * borrowed from the m68k.
- *
- * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
- * Copyright (c) 2001 PPC64 Team, IBM Corp 
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
-#ifndef _PPC64_BOOTINFO_H
-#define _PPC64_BOOTINFO_H
-
-#include <asm/types.h>
-
-/* We use a u32 for the type of the fields since they're written by
- * the bootloader which is a 32-bit process and read by the kernel
- * which is a 64-bit process.  This way they can both agree on the
- * size of the type.
- */
-typedef u32 bi_rec_field;
-
-struct bi_record {
-        bi_rec_field tag;       /* tag ID */
-        bi_rec_field size;      /* size of record (in bytes) */
-        bi_rec_field data[0];   /* data */
-};
-
-#define BI_FIRST                0x1010  /* first record - marker */
-#define BI_LAST                 0x1011  /* last record - marker */
-#define BI_CMD_LINE             0x1012
-#define BI_BOOTLOADER_ID        0x1013
-#define BI_INITRD               0x1014
-#define BI_SYSMAP               0x1015
-#define BI_MACHTYPE             0x1016
-
-static __inline__ struct bi_record * bi_rec_init(unsigned long addr)
-{
-        struct bi_record *bi_recs;
-        bi_recs = (struct bi_record *)_ALIGN(addr, PAGE_SIZE);
-        bi_recs->size = 0;
-        return bi_recs;
-}
-
-static __inline__ struct bi_record * bi_rec_alloc(struct bi_record *rec,
-                                                  unsigned long args)
-{
-        rec = (struct bi_record *)((unsigned long)rec + rec->size);
-        rec->size = sizeof(struct bi_record) + args*sizeof(bi_rec_field);
-        return rec;
-}
-
-static __inline__ struct bi_record * bi_rec_alloc_bytes(struct bi_record *rec,
-                                                        unsigned long bytes)
-{
-        rec = (struct bi_record *)((unsigned long)rec + rec->size);
-        rec->size = sizeof(struct bi_record) + bytes;
-        return rec;
-}
-
-static __inline__ struct bi_record * bi_rec_next(struct bi_record *rec)
-{
-        return (struct bi_record *)((unsigned long)rec + rec->size);
-}
-
-#endif /* _PPC64_BOOTINFO_H */
diff --git a/include/asm-ppc64/btext.h b/include/asm-ppc64/btext.h
index 67aef0cc72c0..71cce36bc630 100644
--- a/include/asm-ppc64/btext.h
+++ b/include/asm-ppc64/btext.h
@@ -15,6 +15,7 @@ extern int boot_text_mapped;
 extern int btext_initialize(struct device_node *np);
 
 extern void map_boot_text(void);
+extern void init_boot_display(void);
 extern void btext_update_display(unsigned long phys, int width, int height,
                                  int depth, int pitch);
 
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
deleted file mode 100644
index acc9b4d6c168..000000000000
--- a/include/asm-ppc64/cputable.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- *  include/asm-ppc64/cputable.h
- *
- *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- *  Modifications for ppc64:
- *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
- * 
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-
-#include <linux/config.h>
-#include <asm/page.h> /* for ASM_CONST */
-
-/* Exposed to userland CPU features - Must match ppc32 definitions */
-#define PPC_FEATURE_32                  0x80000000
-#define PPC_FEATURE_64                  0x40000000
-#define PPC_FEATURE_601_INSTR           0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
-#define PPC_FEATURE_HAS_FPU             0x08000000
-#define PPC_FEATURE_HAS_MMU             0x04000000
-#define PPC_FEATURE_HAS_4xxMAC          0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mechanism.
- */
-struct cpu_spec;
-struct op_ppc64_model;
-
-typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
-
-struct cpu_spec {
-        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
-        unsigned int    pvr_mask;
-        unsigned int    pvr_value;
-
-        char            *cpu_name;
-        unsigned long   cpu_features;           /* Kernel features */
-        unsigned int    cpu_user_features;      /* Userland features */
-
-        /* cache line sizes */
-        unsigned int    icache_bsize;
-        unsigned int    dcache_bsize;
-
-        /* number of performance monitor counters */
-        unsigned int    num_pmcs;
-
-        /* this is called to initialize various CPU bits like L1 cache,
-         * BHT, SPD, etc... from head.S before branching to identify_machine
-         */
-        cpu_setup_t     cpu_setup;
-
-        /* Used by oprofile userspace to select the right counters */
-        char            *oprofile_cpu_type;
-
-        /* Processor specific oprofile operations */
-        struct op_ppc64_model *oprofile_model;
-};
-
-extern struct cpu_spec          cpu_specs[];
-extern struct cpu_spec          *cur_cpu_spec;
-
-static inline unsigned long cpu_has_feature(unsigned long feature)
-{
-        return cur_cpu_spec->cpu_features & feature;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-
-/* Retain the 32b definitions for the time being - use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
-#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
-#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
-#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
-#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
-#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
-#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
-#define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
-#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
-#define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
-#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
-#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
-#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
-#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
-#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
-
-/* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
-#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000001000000000)
-#define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
-/* unused                               ASM_CONST(0x0000008000000000) */
-#define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
-#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
-#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
-#define CPU_FTR_CTRL                    ASM_CONST(0x0000100000000000)
-
-#ifndef __ASSEMBLY__
-
-#define COMMON_USER_PPC64       (PPC_FEATURE_32 | PPC_FEATURE_64 | \
-                                 PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
-
-#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
-                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
-
-/* iSeries doesn't support large pages */
-#ifdef CONFIG_PPC_ISERIES
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
-#else
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
-#endif /* CONFIG_PPC_ISERIES */
-
-#endif /* __ASSEMBLY */
-
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION               98:
-
-#define END_FTR_SECTION(msk, val)               \
-99:                                             \
-        .section __ftr_fixup,"a";               \
-        .align 3;                               \
-        .llong msk;                             \
-        .llong val;                             \
-        .llong 98b;                             \
-        .llong 99b;                             \
-        .previous
-
-#else
-
-#define BEGIN_FTR_SECTION               "98:\n"
-#define END_FTR_SECTION(msk, val)               \
-"99:\n"                                         \
-"       .section __ftr_fixup,\"a\";\n"          \
-"       .align 3;\n"                            \
-"       .llong "#msk";\n"                       \
-"       .llong "#val";\n"                       \
-"       .llong 98b;\n"                          \
-"       .llong 99b;\n"                          \
-"       .previous\n"
-
-#endif /* __ASSEMBLY__ */
-
-#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
-
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
-
diff --git a/include/asm-ppc64/dart.h b/include/asm-ppc64/dart.h
new file mode 100644
index 000000000000..cdf8a2dec05f
--- /dev/null
+++ b/include/asm-ppc64/dart.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _ASM_DART_H
+#define _ASM_DART_H
+
+
+/* physical base of DART registers */
+#define DART_BASE        0xf8033000UL
+
+/* Offset from base to control register */
+#define DARTCNTL   0
+/* Offset from base to exception register */
+#define DARTEXCP   0x10
+/* Offset from base to TLB tag registers */
+#define DARTTAG    0x1000
+
+
+/* Control Register fields */
+
+/* base address of table (pfn) */
+#define DARTCNTL_BASE_MASK    0xfffff
+#define DARTCNTL_BASE_SHIFT   12
+
+#define DARTCNTL_FLUSHTLB     0x400
+#define DARTCNTL_ENABLE       0x200
+
+/* size of table in pages */
+#define DARTCNTL_SIZE_MASK    0x1ff
+#define DARTCNTL_SIZE_SHIFT   0
+
+
+/* DART table fields */
+
+#define DARTMAP_VALID   0x80000000
+#define DARTMAP_RPNMASK 0x00ffffff
+
+
+#define DART_PAGE_SHIFT         12
+#define DART_PAGE_SIZE          (1 << DART_PAGE_SHIFT)
+#define DART_PAGE_FACTOR        (PAGE_SHIFT - DART_PAGE_SHIFT)
+
+
+#endif
diff --git a/include/asm-ppc64/dbdma.h b/include/asm-ppc64/dbdma.h
deleted file mode 100644
index f2d5d5dc3377..000000000000
--- a/include/asm-ppc64/dbdma.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/dbdma.h>
-
diff --git a/include/asm-ppc64/dma.h b/include/asm-ppc64/dma.h
deleted file mode 100644
index dfd1f69059ba..000000000000
--- a/include/asm-ppc64/dma.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/* 
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- * Changes for ppc sound by Christoph Nadig
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <linux/config.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-#include <asm/system.h>
-
-#ifndef MAX_DMA_CHANNELS
-#define MAX_DMA_CHANNELS        8
-#endif
-
-/* The maximum address that we can perform a DMA transfer to on this platform */
-/* Doesn't really apply... */
-#define MAX_DMA_ADDRESS  (~0UL)
-
-#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
-
-#define dma_outb        outb
-#define dma_inb         inb
-
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.  
- * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0   
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
- *
- */
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG            0x08    /* command register (w) */
-#define DMA1_STAT_REG           0x08    /* status register (r) */
-#define DMA1_REQ_REG            0x09    /* request register (w) */
-#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
-#define DMA1_MODE_REG           0x0B    /* mode register (w) */
-#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-
-#define DMA2_CMD_REG            0xD0    /* command register (w) */
-#define DMA2_STAT_REG           0xD0    /* status register (r) */
-#define DMA2_REQ_REG            0xD2    /* request register (w) */
-#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
-#define DMA2_MODE_REG           0xD6    /* mode register (w) */
-#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-
-#define DMA_ADDR_0              0x00    /* DMA address registers */
-#define DMA_ADDR_1              0x02
-#define DMA_ADDR_2              0x04
-#define DMA_ADDR_3              0x06
-#define DMA_ADDR_4              0xC0
-#define DMA_ADDR_5              0xC4
-#define DMA_ADDR_6              0xC8
-#define DMA_ADDR_7              0xCC
-
-#define DMA_CNT_0               0x01    /* DMA count registers */
-#define DMA_CNT_1               0x03
-#define DMA_CNT_2               0x05
-#define DMA_CNT_3               0x07
-#define DMA_CNT_4               0xC2
-#define DMA_CNT_5               0xC6
-#define DMA_CNT_6               0xCA
-#define DMA_CNT_7               0xCE
-
-#define DMA_LO_PAGE_0              0x87    /* DMA page registers */
-#define DMA_LO_PAGE_1              0x83
-#define DMA_LO_PAGE_2              0x81
-#define DMA_LO_PAGE_3              0x82
-#define DMA_LO_PAGE_5              0x8B
-#define DMA_LO_PAGE_6              0x89
-#define DMA_LO_PAGE_7              0x8A
-
-#define DMA_HI_PAGE_0              0x487    /* DMA page registers */
-#define DMA_HI_PAGE_1              0x483
-#define DMA_HI_PAGE_2              0x481
-#define DMA_HI_PAGE_3              0x482
-#define DMA_HI_PAGE_5              0x48B
-#define DMA_HI_PAGE_6              0x489
-#define DMA_HI_PAGE_7              0x48A
-
-#define DMA1_EXT_REG               0x40B
-#define DMA2_EXT_REG               0x4D6
-
-#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT     0x10
-
-extern spinlock_t  dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&dma_spin_lock, flags);
-        return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-        unsigned char ucDmaCmd=0x00;
-
-        if (dmanr != 4)
-        {
-                dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
-                dma_outb(ucDmaCmd, DMA2_CMD_REG);  /* Enable group */
-        }
-        if (dmanr<=3)
-        {
-                dma_outb(dmanr,  DMA1_MASK_REG);
-                dma_outb(ucDmaCmd, DMA1_CMD_REG);  /* Enable group */
-        } else
-        {
-                dma_outb(dmanr & 3,  DMA2_MASK_REG);
-        }
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr | 4,  DMA1_MASK_REG);
-        else
-                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while interrupts are disabled! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(0,  DMA1_CLEAR_FF_REG);
-        else
-                dma_outb(0,  DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-        if (dmanr<=3)
-                dma_outb(mode | dmanr,  DMA1_MODE_REG);
-        else
-                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
-{
-        switch(dmanr) {
-                case 0:
-                        dma_outb(pagenr, DMA_LO_PAGE_0);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_0);
-                        break;
-                case 1:
-                        dma_outb(pagenr, DMA_LO_PAGE_1);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_1);
-                        break;
-                case 2:
-                        dma_outb(pagenr, DMA_LO_PAGE_2);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_2); 
-                        break;
-                case 3:
-                        dma_outb(pagenr, DMA_LO_PAGE_3);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_3); 
-                        break;
-                case 5:
-                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_5);
-                        break;
-                case 6:
-                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_6);
-                        break;
-                case 7:
-                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_7);
-                  break;
-        }
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
-{
-        if (dmanr <= 3)  {
-            dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-            dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-        }  else  {
-            dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-            dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-        }
-        set_dma_page(dmanr, phys>>16);
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        count--;
-        if (dmanr <= 3)  {
-            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-        } else {
-            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-        }
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
-        /* using short to get 16-bit wrap around */
-        unsigned short count;
-
-        count = 1 + dma_inb(io_port);
-        count += dma_inb(io_port) << 8;
-        
-        return (dmanr <= 3)? count : (count<<1);
-}
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;                                        
-#else                                                         
-#define isa_dma_bridge_buggy   (0)
-#endif
-#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
-#endif /* _ASM_DMA_H */
diff --git a/include/asm-ppc64/futex.h b/include/asm-ppc64/futex.h
index cb2640b3a408..266b460de44e 100644
--- a/include/asm-ppc64/futex.h
+++ b/include/asm-ppc64/futex.h
@@ -5,7 +5,7 @@
 
 #include <linux/futex.h>
 #include <asm/errno.h>
-#include <asm/memory.h>
+#include <asm/synch.h>
 #include <asm/uaccess.h>
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
diff --git a/include/asm-ppc64/hardirq.h b/include/asm-ppc64/hardirq.h
deleted file mode 100644
index 4ee72bb1fd48..000000000000
--- a/include/asm-ppc64/hardirq.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/config.h>
-#include <linux/cache.h>
-#include <linux/preempt.h>
-
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-static inline void ack_bad_irq(int irq)
-{
-        printk(KERN_CRIT "illegal vector %d received!\n", irq);
-        BUG();
-}
-
-#endif /* __ASM_HARDIRQ_H */
diff --git a/include/asm-ppc64/iSeries/HvCallHpt.h b/include/asm-ppc64/iSeries/HvCallHpt.h
deleted file mode 100644
index 43a1969230b8..000000000000
--- a/include/asm-ppc64/iSeries/HvCallHpt.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * HvCallHpt.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _HVCALLHPT_H
-#define _HVCALLHPT_H
-
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-
-#include <asm/iSeries/HvCallSc.h>
-#include <asm/iSeries/HvTypes.h>
-#include <asm/mmu.h>
-
-#define HvCallHptGetHptAddress          HvCallHpt +  0
-#define HvCallHptGetHptPages            HvCallHpt +  1
-#define HvCallHptSetPp                  HvCallHpt +  5
-#define HvCallHptSetSwBits              HvCallHpt +  6
-#define HvCallHptUpdate                 HvCallHpt +  7
-#define HvCallHptInvalidateNoSyncICache HvCallHpt +  8
-#define HvCallHptGet                    HvCallHpt + 11
-#define HvCallHptFindNextValid          HvCallHpt + 12
-#define HvCallHptFindValid              HvCallHpt + 13
-#define HvCallHptAddValidate            HvCallHpt + 16
-#define HvCallHptInvalidateSetSwBitsGet HvCallHpt + 18
-
-
-static inline u64 HvCallHpt_getHptAddress(void)
-{
-        return HvCall0(HvCallHptGetHptAddress);
-}
-
-static inline u64 HvCallHpt_getHptPages(void)
-{
-        return HvCall0(HvCallHptGetHptPages);
-}
-
-static inline void HvCallHpt_setPp(u32 hpteIndex, u8 value)
-{
-        HvCall2(HvCallHptSetPp, hpteIndex, value);
-}
-
-static inline void HvCallHpt_setSwBits(u32 hpteIndex, u8 bitson, u8 bitsoff)
-{
-        HvCall3(HvCallHptSetSwBits, hpteIndex, bitson, bitsoff);
-}
-
-static inline void HvCallHpt_invalidateNoSyncICache(u32 hpteIndex)
-{
-        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
-}
-
-static inline u64 HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson,
-                u8 bitsoff)
-{
-        u64 compressedStatus;
-
-        compressedStatus = HvCall4(HvCallHptInvalidateSetSwBitsGet,
-                        hpteIndex, bitson, bitsoff, 1);
-        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
-        return compressedStatus;
-}
-
-static inline u64 HvCallHpt_findValid(hpte_t *hpte, u64 vpn)
-{
-        return HvCall3Ret16(HvCallHptFindValid, hpte, vpn, 0, 0);
-}
-
-static inline u64 HvCallHpt_findNextValid(hpte_t *hpte, u32 hpteIndex,
-                u8 bitson, u8 bitsoff)
-{
-        return HvCall3Ret16(HvCallHptFindNextValid, hpte, hpteIndex,
-                        bitson, bitsoff);
-}
-
-static inline void HvCallHpt_get(hpte_t *hpte, u32 hpteIndex)
-{
-        HvCall2Ret16(HvCallHptGet, hpte, hpteIndex, 0);
-}
-
-static inline void HvCallHpt_addValidate(u32 hpteIndex, u32 hBit, hpte_t *hpte)
-{
-        HvCall4(HvCallHptAddValidate, hpteIndex, hBit, hpte->v, hpte->r);
-}
-
-#endif /* _HVCALLHPT_H */
diff --git a/include/asm-ppc64/iSeries/HvCallPci.h b/include/asm-ppc64/iSeries/HvCallPci.h
deleted file mode 100644
index c8d675c40f5e..000000000000
--- a/include/asm-ppc64/iSeries/HvCallPci.h
+++ /dev/null
@@ -1,533 +0,0 @@
-/*
- * Provides the Hypervisor PCI calls for iSeries Linux Parition.
- * Copyright (C) 2001  <Wayne G Holm> <IBM Corporation>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created, Jan 9, 2001
- */
-
-#ifndef _HVCALLPCI_H
-#define _HVCALLPCI_H
-
-#include <asm/iSeries/HvCallSc.h>
-#include <asm/iSeries/HvTypes.h>
-
-/*
- * DSA == Direct Select Address
- * this struct must be 64 bits in total
- */
-struct HvCallPci_DsaAddr {
-        u16             busNumber;              /* PHB index? */
-        u8              subBusNumber;           /* PCI bus number? */
-        u8              deviceId;               /* device and function? */
-        u8              barNumber;
-        u8              reserved[3];
-};
-
-union HvDsaMap {
-        u64     DsaAddr;
-        struct HvCallPci_DsaAddr Dsa;
-};
-
-struct HvCallPci_LoadReturn {
-        u64             rc;
-        u64             value;
-};
-
-enum HvCallPci_DeviceType {
-        HvCallPci_NodeDevice    = 1,
-        HvCallPci_SpDevice      = 2,
-        HvCallPci_IopDevice     = 3,
-        HvCallPci_BridgeDevice  = 4,
-        HvCallPci_MultiFunctionDevice = 5,
-        HvCallPci_IoaDevice     = 6
-};
-
-
-struct HvCallPci_DeviceInfo {
-        u32     deviceType;             /* See DeviceType enum for values */
-};
-
-struct HvCallPci_BusUnitInfo {
-        u32     sizeReturned;           /* length of data returned */
-        u32     deviceType;             /* see DeviceType enum for values */
-};
-
-struct HvCallPci_BridgeInfo {
-        struct HvCallPci_BusUnitInfo busUnitInfo;  /* Generic bus unit info */
-        u8              subBusNumber;   /* Bus number of secondary bus */
-        u8              maxAgents;      /* Max idsels on secondary bus */
-        u8              maxSubBusNumber; /* Max Sub Bus */
-        u8              logicalSlotNumber; /* Logical Slot Number for IOA */
-};
-
-
-/*
- * Maximum BusUnitInfo buffer size.  Provided for clients so
- * they can allocate a buffer big enough for any type of bus
- * unit.  Increase as needed.
- */
-enum {HvCallPci_MaxBusUnitInfoSize = 128};
-
-struct HvCallPci_BarParms {
-        u64             vaddr;
-        u64             raddr;
-        u64             size;
-        u64             protectStart;
-        u64             protectEnd;
-        u64             relocationOffset;
-        u64             pciAddress;
-        u64             reserved[3];
-};
-
-enum HvCallPci_VpdType {
-        HvCallPci_BusVpd        = 1,
-        HvCallPci_BusAdapterVpd = 2
-};
-
-#define HvCallPciConfigLoad8            HvCallPci + 0
-#define HvCallPciConfigLoad16           HvCallPci + 1
-#define HvCallPciConfigLoad32           HvCallPci + 2
-#define HvCallPciConfigStore8           HvCallPci + 3
-#define HvCallPciConfigStore16          HvCallPci + 4
-#define HvCallPciConfigStore32          HvCallPci + 5
-#define HvCallPciEoi                    HvCallPci + 16
-#define HvCallPciGetBarParms            HvCallPci + 18
-#define HvCallPciMaskFisr               HvCallPci + 20
-#define HvCallPciUnmaskFisr             HvCallPci + 21
-#define HvCallPciSetSlotReset           HvCallPci + 25
-#define HvCallPciGetDeviceInfo          HvCallPci + 27
-#define HvCallPciGetCardVpd             HvCallPci + 28
-#define HvCallPciBarLoad8               HvCallPci + 40
-#define HvCallPciBarLoad16              HvCallPci + 41
-#define HvCallPciBarLoad32              HvCallPci + 42
-#define HvCallPciBarLoad64              HvCallPci + 43
-#define HvCallPciBarStore8              HvCallPci + 44
-#define HvCallPciBarStore16             HvCallPci + 45
-#define HvCallPciBarStore32             HvCallPci + 46
-#define HvCallPciBarStore64             HvCallPci + 47
-#define HvCallPciMaskInterrupts         HvCallPci + 48
-#define HvCallPciUnmaskInterrupts       HvCallPci + 49
-#define HvCallPciGetBusUnitInfo         HvCallPci + 50
-
-static inline u64 HvCallPci_configLoad8(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u8 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        HvCall3Ret16(HvCallPciConfigLoad8, &retVal, *(u64 *)&dsa, offset, 0);
-
-        *value = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_configLoad16(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u16 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        HvCall3Ret16(HvCallPciConfigLoad16, &retVal, *(u64 *)&dsa, offset, 0);
-
-        *value = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u32 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        HvCall3Ret16(HvCallPciConfigLoad32, &retVal, *(u64 *)&dsa, offset, 0);
-
-        *value = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_configStore8(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u8 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        return HvCall4(HvCallPciConfigStore8, *(u64 *)&dsa, offset, value, 0);
-}
-
-static inline u64 HvCallPci_configStore16(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u16 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        return HvCall4(HvCallPciConfigStore16, *(u64 *)&dsa, offset, value, 0);
-}
-
-static inline u64 HvCallPci_configStore32(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u32 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        return HvCall4(HvCallPciConfigStore32, *(u64 *)&dsa, offset, value, 0);
-}
-
-static inline u64 HvCallPci_barLoad8(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u8 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        HvCall3Ret16(HvCallPciBarLoad8, &retVal, *(u64 *)&dsa, offsetParm, 0);
-
-        *valueParm = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_barLoad16(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u16 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        HvCall3Ret16(HvCallPciBarLoad16, &retVal, *(u64 *)&dsa, offsetParm, 0);
-
-        *valueParm = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_barLoad32(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u32 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        HvCall3Ret16(HvCallPciBarLoad32, &retVal, *(u64 *)&dsa, offsetParm, 0);
-
-        *valueParm = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_barLoad64(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u64 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        HvCall3Ret16(HvCallPciBarLoad64, &retVal, *(u64 *)&dsa, offsetParm, 0);
-
-        *valueParm = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_barStore8(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u8 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        return HvCall4(HvCallPciBarStore8, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-
-static inline u64 HvCallPci_barStore16(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u16 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        return HvCall4(HvCallPciBarStore16, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-
-static inline u64 HvCallPci_barStore32(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u32 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        return HvCall4(HvCallPciBarStore32, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-
-static inline u64 HvCallPci_barStore64(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u64 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        return HvCall4(HvCallPciBarStore64, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-
-static inline u64 HvCallPci_eoi(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        HvCall1Ret16(HvCallPciEoi, &retVal, *(u64*)&dsa);
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_getBarParms(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        return HvCall3(HvCallPciGetBarParms, *(u64*)&dsa, parms, sizeofParms);
-}
-
-static inline u64 HvCallPci_maskFisr(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 fisrMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciMaskFisr, *(u64*)&dsa, fisrMask);
-}
-
-static inline u64 HvCallPci_unmaskFisr(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 fisrMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciUnmaskFisr, *(u64*)&dsa, fisrMask);
-}
-
-static inline u64 HvCallPci_setSlotReset(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 onNotOff)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciSetSlotReset, *(u64*)&dsa, onNotOff);
-}
-
-static inline u64 HvCallPci_getDeviceInfo(u16 busNumberParm, u8 subBusParm,
-                u8 deviceNumberParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceNumberParm << 4;
-
-        return HvCall3(HvCallPciGetDeviceInfo, *(u64*)&dsa, parms, sizeofParms);
-}
-
-static inline u64 HvCallPci_maskInterrupts(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 interruptMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciMaskInterrupts, *(u64*)&dsa, interruptMask);
-}
-
-static inline u64 HvCallPci_unmaskInterrupts(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 interruptMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciUnmaskInterrupts, *(u64*)&dsa, interruptMask);
-}
-
-static inline u64 HvCallPci_getBusUnitInfo(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall3(HvCallPciGetBusUnitInfo, *(u64*)&dsa, parms,
-                        sizeofParms);
-}
-
-static inline int HvCallPci_getBusVpd(u16 busNumParm, u64 destParm,
-                u16 sizeParm)
-{
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
-                        sizeParm, HvCallPci_BusVpd);
-        if (xRc == -1)
-                return -1;
-        else
-                return xRc & 0xFFFF;
-}
-
-static inline int HvCallPci_getBusAdapterVpd(u16 busNumParm, u64 destParm,
-                u16 sizeParm)
-{
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
-                        sizeParm, HvCallPci_BusAdapterVpd);
-        if (xRc == -1)
-                return -1;
-        else
-                return xRc & 0xFFFF;
-}
-
-#endif /* _HVCALLPCI_H */
diff --git a/include/asm-ppc64/iSeries/HvCallSm.h b/include/asm-ppc64/iSeries/HvCallSm.h
deleted file mode 100644
index 8a3dbb071a43..000000000000
--- a/include/asm-ppc64/iSeries/HvCallSm.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * HvCallSm.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _HVCALLSM_H
-#define _HVCALLSM_H
-
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-
-#include <asm/iSeries/HvCallSc.h>
-#include <asm/iSeries/HvTypes.h>
-
-#define HvCallSmGet64BitsOfAccessMap    HvCallSm  + 11
-
-static inline u64 HvCallSm_get64BitsOfAccessMap(HvLpIndex lpIndex,
-                u64 indexIntoBitMap)
-{
-        return HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, indexIntoBitMap);
-}
-
-#endif /* _HVCALLSM_H */
diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h
deleted file mode 100644
index c8162e5ccb21..000000000000
--- a/include/asm-ppc64/iSeries/HvReleaseData.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * HvReleaseData.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _HVRELEASEDATA_H
-#define _HVRELEASEDATA_H
-
-/*
- * This control block contains the critical information about the
- * release so that it can be changed in the future (ie, the virtual
- * address of the OS's NACA).
- */
-#include <asm/types.h>
-#include <asm/naca.h>
-
-/*
- * When we IPL a secondary partition, we will check if if the
- * secondary xMinPlicVrmIndex > the primary xVrmIndex.
- * If it is then this tells PLIC that this secondary is not
- * supported running on this "old" of a level of PLIC.
- *
- * Likewise, we will compare the primary xMinSlicVrmIndex to
- * the secondary xVrmIndex.
- * If the primary xMinSlicVrmDelta > secondary xVrmDelta then we
- * know that this PLIC does not support running an OS "that old".
- */
-
-#define HVREL_TAGSINACTIVE      0x8000
-#define HVREL_32BIT             0x4000
-#define HVREL_NOSHAREDPROCS     0x2000
-#define HVREL_NOHMT             0x1000
-
-struct HvReleaseData {
-        u32     xDesc;          /* Descriptor "HvRD" ebcdic     x00-x03 */
-        u16     xSize;          /* Size of this control block   x04-x05 */
-        u16     xVpdAreasPtrOffset; /* Offset in NACA of ItVpdAreas x06-x07 */
-        struct  naca_struct     *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
-        u32     xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
-        u32     xRsvd1;         /* Reserved                     x14-x17 */
-        u16     xFlags;
-        u16     xVrmIndex;      /* VRM Index of OS image        x1A-x1B */
-        u16     xMinSupportedPlicVrmIndex; /* Min PLIC level  (soft) x1C-x1D */
-        u16     xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
-        char    xVrmName[12];   /* Displayable name             x20-x2B */
-        char    xRsvd3[20];     /* Reserved                     x2C-x3F */
-};
-
-extern struct HvReleaseData     hvReleaseData;
-
-#endif /* _HVRELEASEDATA_H */
diff --git a/include/asm-ppc64/iSeries/IoHriMainStore.h b/include/asm-ppc64/iSeries/IoHriMainStore.h
deleted file mode 100644
index 45ed3ea67d06..000000000000
--- a/include/asm-ppc64/iSeries/IoHriMainStore.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * IoHriMainStore.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _IOHRIMAINSTORE_H
-#define _IOHRIMAINSTORE_H
-
-/* Main Store Vpd for Condor,iStar,sStar */
-struct IoHriMainStoreSegment4 {
-        u8      msArea0Exists:1;
-        u8      msArea1Exists:1;
-        u8      msArea2Exists:1;
-        u8      msArea3Exists:1;
-        u8      reserved1:4;
-        u8      reserved2;
-
-        u8      msArea0Functional:1;
-        u8      msArea1Functional:1;
-        u8      msArea2Functional:1;
-        u8      msArea3Functional:1;
-        u8      reserved3:4;
-        u8      reserved4;
-
-        u32     totalMainStore;
-
-        u64     msArea0Ptr;
-        u64     msArea1Ptr;
-        u64     msArea2Ptr;
-        u64     msArea3Ptr;
-
-        u32     cardProductionLevel;
-
-        u32     msAdrHole;
-
-        u8      msArea0HasRiserVpd:1;
-        u8      msArea1HasRiserVpd:1;
-        u8      msArea2HasRiserVpd:1;
-        u8      msArea3HasRiserVpd:1;
-        u8      reserved5:4;
-        u8      reserved6;
-        u16     reserved7;
-
-        u8      reserved8[28];
-
-        u64     nonInterleavedBlocksStartAdr;
-        u64     nonInterleavedBlocksEndAdr;
-};
-
-/* Main Store VPD for Power4 */
-struct IoHriMainStoreChipInfo1 {
-        u32     chipMfgID       __attribute((packed));
-        char    chipECLevel[4]  __attribute((packed));
-};
-
-struct IoHriMainStoreVpdIdData {
-        char    typeNumber[4];
-        char    modelNumber[4];
-        char    partNumber[12];
-        char    serialNumber[12];
-};
-
-struct IoHriMainStoreVpdFruData {
-        char    fruLabel[8]     __attribute((packed));
-        u8      numberOfSlots   __attribute((packed));
-        u8      pluggingType    __attribute((packed));
-        u16     slotMapIndex    __attribute((packed));
-};
-
-struct IoHriMainStoreAdrRangeBlock {
-        void    *blockStart      __attribute((packed));
-        void    *blockEnd        __attribute((packed));
-        u32     blockProcChipId __attribute((packed));
-};
-
-#define MaxAreaAdrRangeBlocks 4
-
-struct IoHriMainStoreArea4 {
-        u32     msVpdFormat                     __attribute((packed));
-        u8      containedVpdType                __attribute((packed));
-        u8      reserved1                       __attribute((packed));
-        u16     reserved2                       __attribute((packed));
-
-        u64     msExists                        __attribute((packed));
-        u64     msFunctional                    __attribute((packed));
-
-        u32     memorySize                      __attribute((packed));
-        u32     procNodeId                      __attribute((packed));
-
-        u32     numAdrRangeBlocks               __attribute((packed));
-        struct IoHriMainStoreAdrRangeBlock xAdrRangeBlock[MaxAreaAdrRangeBlocks]        __attribute((packed));
-
-        struct IoHriMainStoreChipInfo1  chipInfo0       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo1       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo2       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo3       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo4       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo5       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo6       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo7       __attribute((packed));
-
-        void    *msRamAreaArray                 __attribute((packed));
-        u32     msRamAreaArrayNumEntries        __attribute((packed));
-        u32     msRamAreaArrayEntrySize         __attribute((packed));
-
-        u32     numaDimmExists                  __attribute((packed));
-        u32     numaDimmFunctional              __attribute((packed));
-        void    *numaDimmArray                  __attribute((packed));
-        u32     numaDimmArrayNumEntries         __attribute((packed));
-        u32     numaDimmArrayEntrySize          __attribute((packed));
-
-        struct IoHriMainStoreVpdIdData idData   __attribute((packed));
-
-        u64     powerData                       __attribute((packed));
-        u64     cardAssemblyPartNum             __attribute((packed));
-        u64     chipSerialNum                   __attribute((packed));
-
-        u64     reserved3                       __attribute((packed));
-        char    reserved4[16]                   __attribute((packed));
-
-        struct IoHriMainStoreVpdFruData fruData __attribute((packed));
-
-        u8      vpdPortNum                      __attribute((packed));
-        u8      reserved5                       __attribute((packed));
-        u8      frameId                         __attribute((packed));
-        u8      rackUnit                        __attribute((packed));
-        char    asciiKeywordVpd[256]            __attribute((packed));
-        u32     reserved6                       __attribute((packed));
-};
-
-
-struct IoHriMainStoreSegment5 {
-        u16     reserved1;
-        u8      reserved2;
-        u8      msVpdFormat;
-
-        u32     totalMainStore;
-        u64     maxConfiguredMsAdr;
-
-        struct IoHriMainStoreArea4      *msAreaArray;
-        u32     msAreaArrayNumEntries;
-        u32     msAreaArrayEntrySize;
-
-        u32     msAreaExists;
-        u32     msAreaFunctional;
-
-        u64     reserved3;
-};
-
-extern u64      xMsVpd[];
-
-#endif  /* _IOHRIMAINSTORE_H */
diff --git a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h b/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
deleted file mode 100644
index 73b73d80b8b1..000000000000
--- a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * IoHriProcessorVpd.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _IOHRIPROCESSORVPD_H
-#define _IOHRIPROCESSORVPD_H
-
-#include <asm/types.h>
-
-/*
- * This struct maps Processor Vpd that is DMAd to SLIC by CSP
- */
-struct IoHriProcessorVpd {
-        u8      xFormat;                // VPD format indicator         x00-x00
-        u8      xProcStatus:8;          // Processor State              x01-x01
-        u8      xSecondaryThreadCount;  // Secondary thread cnt         x02-x02
-        u8      xSrcType:1;             // Src Type                     x03-x03
-        u8      xSrcSoft:1;             // Src stay soft                ...
-        u8      xSrcParable:1;          // Src parable                  ...
-        u8      xRsvd1:5;               // Reserved                     ...
-        u16     xHvPhysicalProcIndex;   // Hypervisor physical proc index04-x05
-        u16     xRsvd2;                 // Reserved                     x06-x07
-        u32     xHwNodeId;              // Hardware node id             x08-x0B
-        u32     xHwProcId;              // Hardware processor id        x0C-x0F
-
-        u32     xTypeNum;               // Card Type/CCIN number        x10-x13
-        u32     xModelNum;              // Model/Feature number         x14-x17
-        u64     xSerialNum;             // Serial number                x18-x1F
-        char    xPartNum[12];           // Book Part or FPU number      x20-x2B
-        char    xMfgID[4];              // Manufacturing ID             x2C-x2F
-
-        u32     xProcFreq;              // Processor Frequency          x30-x33
-        u32     xTimeBaseFreq;          // Time Base Frequency          x34-x37
-
-        u32     xChipEcLevel;           // Chip EC Levels               x38-x3B
-        u32     xProcIdReg;             // PIR SPR value                x3C-x3F
-        u32     xPVR;                   // PVR value                    x40-x43
-        u8      xRsvd3[12];             // Reserved                     x44-x4F
-
-        u32     xInstCacheSize;         // Instruction cache size in KB x50-x53
-        u32     xInstBlockSize;         // Instruction cache block size x54-x57
-        u32     xDataCacheOperandSize;  // Data cache operand size      x58-x5B
-        u32     xInstCacheOperandSize;  // Inst cache operand size      x5C-x5F
-
-        u32     xDataL1CacheSizeKB;     // L1 data cache size in KB     x60-x63
-        u32     xDataL1CacheLineSize;   // L1 data cache block size     x64-x67
-        u64     xRsvd4;                 // Reserved                     x68-x6F
-
-        u32     xDataL2CacheSizeKB;     // L2 data cache size in KB     x70-x73
-        u32     xDataL2CacheLineSize;   // L2 data cache block size     x74-x77
-        u64     xRsvd5;                 // Reserved                     x78-x7F
-
-        u32     xDataL3CacheSizeKB;     // L3 data cache size in KB     x80-x83
-        u32     xDataL3CacheLineSize;   // L3 data cache block size     x84-x87
-        u64     xRsvd6;                 // Reserved                     x88-x8F
-
-        u64     xFruLabel;              // Card Location Label          x90-x97
-        u8      xSlotsOnCard;           // Slots on card (0=no slots)   x98-x98
-        u8      xPartLocFlag;           // Location flag (0-pluggable 1-imbedded) x99-x99
-        u16     xSlotMapIndex;          // Index in slot map table      x9A-x9B
-        u8      xSmartCardPortNo;       // Smart card port number       x9C-x9C
-        u8      xRsvd7;                 // Reserved                     x9D-x9D
-        u16     xFrameIdAndRackUnit;    // Frame ID and rack unit adr   x9E-x9F
-
-        u8      xRsvd8[24];             // Reserved                     xA0-xB7
-
-        char    xProcSrc[72];           // CSP format SRC               xB8-xFF
-};
-
-extern struct IoHriProcessorVpd xIoHriProcessorVpd[];
-
-#endif /* _IOHRIPROCESSORVPD_H */
diff --git a/include/asm-ppc64/iSeries/ItIplParmsReal.h b/include/asm-ppc64/iSeries/ItIplParmsReal.h
deleted file mode 100644
index ae3417dc599e..000000000000
--- a/include/asm-ppc64/iSeries/ItIplParmsReal.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * ItIplParmsReal.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ITIPLPARMSREAL_H
-#define _ITIPLPARMSREAL_H
-
-/*
- *      This struct maps the IPL Parameters DMA'd from the SP.
- *
- * Warning:
- *      This data must map in exactly 64 bytes and match the architecture for
- *      the IPL parms
- */
-
-#include <asm/types.h>
-
-struct ItIplParmsReal {
-        u8      xFormat;                // Defines format of IplParms   x00-x00
-        u8      xRsvd01:6;              // Reserved                     x01-x01
-        u8      xAlternateSearch:1;     // Alternate search indicator   ...
-        u8      xUaSupplied:1;          // UA Supplied on programmed IPL...
-        u8      xLsUaFormat;            // Format byte for UA           x02-x02
-        u8      xRsvd02;                // Reserved                     x03-x03
-        u32     xLsUa;                  // LS UA                        x04-x07
-        u32     xUnusedLsLid;           // First OS LID to load         x08-x0B
-        u16     xLsBusNumber;           // LS Bus Number                x0C-x0D
-        u8      xLsCardAdr;             // LS Card Address              x0E-x0E
-        u8      xLsBoardAdr;            // LS Board Address             x0F-x0F
-        u32     xRsvd03;                // Reserved                     x10-x13
-        u8      xSpcnPresent:1;         // SPCN present                 x14-x14
-        u8      xCpmPresent:1;          // CPM present                  ...
-        u8      xRsvd04:6;              // Reserved                     ...
-        u8      xRsvd05:4;              // Reserved                     x15-x15
-        u8      xKeyLock:4;             // Keylock setting              ...
-        u8      xRsvd06:6;              // Reserved                     x16-x16
-        u8      xIplMode:2;             // Ipl mode (A|B|C|D)           ...
-        u8      xHwIplType;             // Fast v slow v slow EC HW IPL x17-x17
-        u16     xCpmEnabledIpl:1;       // CPM in effect when IPL initiatedx18-x19
-        u16     xPowerOnResetIpl:1;     // Indicate POR condition       ...
-        u16     xMainStorePreserved:1;  // Main Storage is preserved    ...
-        u16     xRsvd07:13;             // Reserved                     ...
-        u16     xIplSource:16;          // Ipl source                   x1A-x1B
-        u8      xIplReason:8;           // Reason for this IPL          x1C-x1C
-        u8      xRsvd08;                // Reserved                     x1D-x1D
-        u16     xRsvd09;                // Reserved                     x1E-x1F
-        u16     xSysBoxType;            // System Box Type              x20-x21
-        u16     xSysProcType;           // System Processor Type        x22-x23
-        u32     xRsvd10;                // Reserved                     x24-x27
-        u64     xRsvd11;                // Reserved                     x28-x2F
-        u64     xRsvd12;                // Reserved                     x30-x37
-        u64     xRsvd13;                // Reserved                     x38-x3F
-};
-
-extern struct ItIplParmsReal    xItIplParmsReal;
-
-#endif /* _ITIPLPARMSREAL_H */
diff --git a/include/asm-ppc64/iSeries/ItSpCommArea.h b/include/asm-ppc64/iSeries/ItSpCommArea.h
deleted file mode 100644
index 5535f8271c9f..000000000000
--- a/include/asm-ppc64/iSeries/ItSpCommArea.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * ItSpCommArea.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ITSPCOMMAREA_H
-#define _ITSPCOMMAREA_H
-
-
-struct SpCommArea {
-        u32     xDesc;                  // Descriptor (only in new formats)     000-003
-        u8      xFormat;                // Format (only in new formats)         004-004
-        u8      xRsvd1[11];             // Reserved                             005-00F
-        u64     xRawTbAtIplStart;       // Raw HW TB value when IPL is started  010-017
-        u64     xRawTodAtIplStart;      // Raw HW TOD value when IPL is started 018-01F
-        u64     xBcdTimeAtIplStart;     // BCD time when IPL is started         020-027
-        u64     xBcdTimeAtOsStart;      // BCD time when OS passed control      028-02F
-        u8      xRsvd2[80];             // Reserved                             030-07F
-};
-
-extern struct SpCommArea xSpCommArea;
-
-#endif /* _ITSPCOMMAREA_H */
diff --git a/include/asm-ppc64/iSeries/ItVpdAreas.h b/include/asm-ppc64/iSeries/ItVpdAreas.h
deleted file mode 100644
index 71b3ad24f95a..000000000000
--- a/include/asm-ppc64/iSeries/ItVpdAreas.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * ItVpdAreas.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ITVPDAREAS_H
-#define _ITVPDAREAS_H
-
-/*
- * This file defines the address and length of all of the VPD area passed to
- * the OS from PLIC (most of which start from the SP).
- */
-
-#include <asm/types.h>
-
-/* VPD Entry index is carved in stone - cannot be changed (easily). */
-#define ItVpdCecVpd                             0
-#define ItVpdDynamicSpace                       1
-#define ItVpdExtVpd                             2
-#define ItVpdExtVpdOnPanel                      3
-#define ItVpdFirstPaca                          4
-#define ItVpdIoVpd                              5
-#define ItVpdIplParms                           6
-#define ItVpdMsVpd                              7
-#define ItVpdPanelVpd                           8
-#define ItVpdLpNaca                             9
-#define ItVpdBackplaneAndMaybeClockCardVpd      10
-#define ItVpdRecoveryLogBuffer                  11
-#define ItVpdSpCommArea                         12
-#define ItVpdSpLogBuffer                        13
-#define ItVpdSpLogBufferSave                    14
-#define ItVpdSpCardVpd                          15
-#define ItVpdFirstProcVpd                       16
-#define ItVpdApModelVpd                         17
-#define ItVpdClockCardVpd                       18
-#define ItVpdBusExtCardVpd                      19
-#define ItVpdProcCapacityVpd                    20
-#define ItVpdInteractiveCapacityVpd             21
-#define ItVpdFirstSlotLabel                     22
-#define ItVpdFirstLpQueue                       23
-#define ItVpdFirstL3CacheVpd                    24
-#define ItVpdFirstProcFruVpd                    25
-
-#define ItVpdMaxEntries                         26
-
-#define ItDmaMaxEntries                         10
-
-#define ItVpdAreasMaxSlotLabels                 192
-
-
-struct ItVpdAreas {
-        u32     xSlicDesc;              // Descriptor                   000-003
-        u16     xSlicSize;              // Size of this control block   004-005
-        u16     xPlicAdjustVpdLens:1;   // Flag to indicate new interface006-007
-        u16     xRsvd1:15;              // Reserved bits                ...
-        u16     xSlicVpdEntries;        // Number of VPD entries        008-009
-        u16     xSlicDmaEntries;        // Number of DMA entries        00A-00B
-        u16     xSlicMaxLogicalProcs;   // Maximum logical processors   00C-00D
-        u16     xSlicMaxPhysicalProcs;  // Maximum physical processors  00E-00F
-        u16     xSlicDmaToksOffset;     // Offset into this of array    010-011
-        u16     xSlicVpdAdrsOffset;     // Offset into this of array    012-013
-        u16     xSlicDmaLensOffset;     // Offset into this of array    014-015
-        u16     xSlicVpdLensOffset;     // Offset into this of array    016-017
-        u16     xSlicMaxSlotLabels;     // Maximum number of slot labels018-019
-        u16     xSlicMaxLpQueues;       // Maximum number of LP Queues  01A-01B
-        u8      xRsvd2[4];              // Reserved                     01C-01F
-        u64     xRsvd3[12];             // Reserved                     020-07F
-        u32     xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths   080-0A7
-        u32     xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens    0A8-0CF
-        u32     xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths   0D0-12F
-        void    *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers  130-1EF
-};
-
-extern struct ItVpdAreas        itVpdAreas;
-
-#endif /* _ITVPDAREAS_H */
diff --git a/include/asm-ppc64/iSeries/iSeries_irq.h b/include/asm-ppc64/iSeries/iSeries_irq.h
deleted file mode 100644
index 6c9767ac1302..000000000000
--- a/include/asm-ppc64/iSeries/iSeries_irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ISERIES_IRQ_H__
-#define __ISERIES_IRQ_H__
-
-extern void iSeries_init_IRQ(void);
-extern int  iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, HvAgentId);
-extern void iSeries_activate_IRQs(void);
-
-#endif /* __ISERIES_IRQ_H__ */
diff --git a/include/asm-ppc64/iSeries/iSeries_pci.h b/include/asm-ppc64/iSeries/iSeries_pci.h
deleted file mode 100644
index 575f611f8b33..000000000000
--- a/include/asm-ppc64/iSeries/iSeries_pci.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef _ISERIES_64_PCI_H
-#define _ISERIES_64_PCI_H
-
-/*
- * File iSeries_pci.h created by Allan Trautman on Tue Feb 20, 2001.
- *
- * Define some useful macros for the iSeries pci routines.
- * Copyright (C) 2001  Allan H Trautman, IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created Feb 20, 2001
- *   Added device reset, March 22, 2001
- *   Ported to ppc64, May 25, 2001
- * End Change Activity
- */
-
-#include <asm/iSeries/HvCallPci.h>
-#include <asm/abs_addr.h>
-
-struct pci_dev;                         /* For Forward Reference */
-struct iSeries_Device_Node;
-
-/*
- * Gets iSeries Bus, SubBus, DevFn using iSeries_Device_Node structure
- */
-
-#define ISERIES_BUS(DevPtr)     DevPtr->DsaAddr.Dsa.busNumber
-#define ISERIES_SUBBUS(DevPtr)  DevPtr->DsaAddr.Dsa.subBusNumber
-#define ISERIES_DEVICE(DevPtr)  DevPtr->DsaAddr.Dsa.deviceId
-#define ISERIES_DSA(DevPtr)     DevPtr->DsaAddr.DsaAddr
-#define ISERIES_DEVNODE(PciDev) ((struct iSeries_Device_Node *)PciDev->sysdata)
-
-#define EADsMaxAgents 7
-
-/*
- * Decodes Linux DevFn to iSeries DevFn, bridge device, or function.
- * For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h
- */
-
-#define ISERIES_PCI_AGENTID(idsel, func)        \
-        (((idsel & 0x0F) << 4) | (func & 0x07))
-#define ISERIES_ENCODE_DEVICE(agentid)          \
-        ((0x10) | ((agentid & 0x20) >> 2) | (agentid & 0x07))
-
-#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus)          ((subbus >> 5) & 0x7)
-#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)        ((subbus >> 2) & 0x7)
-
-/*
- * Converts Virtual Address to Real Address for Hypervisor calls
- */
-#define ISERIES_HV_ADDR(virtaddr)       \
-        (0x8000000000000000 | virt_to_abs(virtaddr))
-
-/*
- * iSeries Device Information
- */
-struct iSeries_Device_Node {
-        struct list_head Device_List;
-        struct pci_dev  *PciDev;
-        union HvDsaMap  DsaAddr;        /* Direct Select Address */
-                                        /* busNumber, subBusNumber, */
-                                        /* deviceId, barNumber */
-        int             DevFn;          /* Linux devfn */
-        int             Irq;            /* Assigned IRQ */
-        int             Flags;          /* Possible flags(disable/bist)*/
-        u8              LogicalSlot;    /* Hv Slot Index for Tces */
-        struct iommu_table *iommu_table;/* Device TCE Table */
-};
-
-extern void     iSeries_Device_Information(struct pci_dev*, int);
-
-#endif /* _ISERIES_64_PCI_H */
diff --git a/include/asm-ppc64/io.h b/include/asm-ppc64/io.h
index 59c958aea4db..bd7c9532d77b 100644
--- a/include/asm-ppc64/io.h
+++ b/include/asm-ppc64/io.h
@@ -15,7 +15,7 @@
 #ifdef CONFIG_PPC_ISERIES 
 #include <asm/iSeries/iSeries_io.h>
 #endif  
-#include <asm/memory.h>
+#include <asm/synch.h>
 #include <asm/delay.h>
 
 #include <asm-generic/iomap.h>
diff --git a/include/asm-ppc64/irq.h b/include/asm-ppc64/irq.h
deleted file mode 100644
index 99782afb4cde..000000000000
--- a/include/asm-ppc64/irq.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/config.h>
-#include <linux/threads.h>
-
-/*
- * Maximum number of interrupt sources that we can handle.
- */
-#define NR_IRQS         512
-
-/* this number is used when no interrupt has been assigned */
-#define NO_IRQ                  (-1)
-
-/*
- * These constants are used for passing information about interrupt
- * signal polarity and level/edge sensing to the low-level PIC chip
- * drivers.
- */
-#define IRQ_SENSE_MASK          0x1
-#define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
-#define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
-
-#define IRQ_POLARITY_MASK       0x2
-#define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
-#define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
-
-/*
- * IRQ line status macro IRQ_PER_CPU is used
- */
-#define ARCH_HAS_IRQ_PER_CPU
-
-#define get_irq_desc(irq) (&irq_desc[(irq)])
-
-/* Define a way to iterate across irqs. */
-#define for_each_irq(i) \
-        for ((i) = 0; (i) < NR_IRQS; ++(i))
-
-/* Interrupt numbers are virtual in case they are sparsely
- * distributed by the hardware.
- */
-extern unsigned int virt_irq_to_real_map[NR_IRQS];
-
-/* Create a mapping for a real_irq if it doesn't already exist.
- * Return the virtual irq as a convenience.
- */
-int virt_irq_create_mapping(unsigned int real_irq);
-void virt_irq_init(void);
-
-static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
-{
-        return virt_irq_to_real_map[virt_irq];
-}
-
-extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
-
-/*
- * Because many systems have two overlapping names spaces for
- * interrupts (ISA and XICS for example), and the ISA interrupts
- * have historically not been easy to renumber, we allow ISA
- * interrupts to take values 0 - 15, and shift up the remaining
- * interrupts by 0x10.
- */
-#define NUM_ISA_INTERRUPTS      0x10
-extern int __irq_offset_value;
-
-static inline int irq_offset_up(int irq)
-{
-        return(irq + __irq_offset_value);
-}
-
-static inline int irq_offset_down(int irq)
-{
-        return(irq - __irq_offset_value);
-}
-
-static inline int irq_offset_value(void)
-{
-        return __irq_offset_value;
-}
-
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
-extern int distribute_irqs;
-
-struct irqaction;
-struct pt_regs;
-
-#ifdef CONFIG_IRQSTACKS
-/*
- * Per-cpu stacks for handling hard and soft interrupts.
- */
-extern struct thread_info *hardirq_ctx[NR_CPUS];
-extern struct thread_info *softirq_ctx[NR_CPUS];
-
-extern void irq_ctx_init(void);
-extern void call_do_softirq(struct thread_info *tp);
-extern int call_handle_IRQ_event(int irq, struct pt_regs *regs,
-                        struct irqaction *action, struct thread_info *tp);
-
-#define __ARCH_HAS_DO_SOFTIRQ
-
-#else
-#define irq_ctx_init()
-
-#endif /* CONFIG_IRQSTACKS */
-
-#endif /* _ASM_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/keylargo.h b/include/asm-ppc64/keylargo.h
deleted file mode 100644
index 4d78e3d0314c..000000000000
--- a/include/asm-ppc64/keylargo.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/keylargo.h>
-
diff --git a/include/asm-ppc64/kmap_types.h b/include/asm-ppc64/kmap_types.h
deleted file mode 100644
index fd1574648223..000000000000
--- a/include/asm-ppc64/kmap_types.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,    
-        KM_TYPE_NR
-};
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/macio.h b/include/asm-ppc64/macio.h
deleted file mode 100644
index a3028b364f70..000000000000
--- a/include/asm-ppc64/macio.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/macio.h>
-
diff --git a/include/asm-ppc64/memory.h b/include/asm-ppc64/memory.h
deleted file mode 100644
index af53ffb55726..000000000000
--- a/include/asm-ppc64/memory.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef _ASM_PPC64_MEMORY_H_ 
-#define _ASM_PPC64_MEMORY_H_ 
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/config.h>
-
-/*
- * Arguably the bitops and *xchg operations don't imply any memory barrier
- * or SMP ordering, but in fact a lot of drivers expect them to imply
- * both, since they do on x86 cpus.
- */
-#ifdef CONFIG_SMP
-#define EIEIO_ON_SMP    "eieio\n"
-#define ISYNC_ON_SMP    "\n\tisync"
-#define SYNC_ON_SMP     "lwsync\n\t"
-#else
-#define EIEIO_ON_SMP
-#define ISYNC_ON_SMP
-#define SYNC_ON_SMP
-#endif
-
-static inline void eieio(void)
-{
-        __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-static inline void isync(void)
-{
-        __asm__ __volatile__ ("isync" : : : "memory");
-}
-
-#ifdef CONFIG_SMP
-#define eieio_on_smp()  eieio()
-#define isync_on_smp()  isync()
-#else
-#define eieio_on_smp()  __asm__ __volatile__("": : :"memory")
-#define isync_on_smp()  __asm__ __volatile__("": : :"memory")
-#endif
-
-/* Macros for adjusting thread priority (hardware multi-threading) */
-#define HMT_very_low()    asm volatile("or 31,31,31   # very low priority")
-#define HMT_low()       asm volatile("or 1,1,1          # low priority")
-#define HMT_medium_low()  asm volatile("or 6,6,6      # medium low priority")
-#define HMT_medium()    asm volatile("or 2,2,2          # medium priority")
-#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
-#define HMT_high()      asm volatile("or 3,3,3          # high priority")
-
-#define HMT_VERY_LOW    "\tor   31,31,31        # very low priority\n"
-#define HMT_LOW         "\tor   1,1,1           # low priority\n"
-#define HMT_MEDIUM_LOW  "\tor   6,6,6           # medium low priority\n"
-#define HMT_MEDIUM      "\tor   2,2,2           # medium priority\n"
-#define HMT_MEDIUM_HIGH "\tor   5,5,5           # medium high priority\n"
-#define HMT_HIGH        "\tor   3,3,3           # high priority\n"
-
-#endif
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 7bc42eb087ad..e0505acb77d9 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -14,6 +14,7 @@
 #define _PPC64_MMU_H_
 
 #include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
 #include <asm/page.h>
 
 /*
@@ -29,7 +30,7 @@
 
 /* Location of cpu0's segment table */
 #define STAB0_PAGE      0x6
-#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
+#define STAB0_PHYS_ADDR (STAB0_PAGE<<12)
 
 #ifndef __ASSEMBLY__
 extern char initial_stab[];
@@ -205,6 +206,10 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
                                unsigned long prpn,
                                unsigned long vflags, unsigned long rflags);
 
+extern long iSeries_hpte_bolt_or_insert(unsigned long hpte_group,
+                unsigned long va, unsigned long prpn,
+                unsigned long vflags, unsigned long rflags);
+
 extern void stabs_alloc(void);
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/mmzone.h b/include/asm-ppc64/mmzone.h
index ed473f4b0152..80a708e7093a 100644
--- a/include/asm-ppc64/mmzone.h
+++ b/include/asm-ppc64/mmzone.h
@@ -67,9 +67,6 @@ static inline int pa_to_nid(unsigned long pa)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
 
-#define local_mapnr(kvaddr) \
-        ( (__pa(kvaddr) >> PAGE_SHIFT) - node_start_pfn(kvaddr_to_nid(kvaddr)) 
-
 #ifdef CONFIG_DISCONTIGMEM
 
 /*
diff --git a/include/asm-ppc64/of_device.h b/include/asm-ppc64/of_device.h
deleted file mode 100644
index 7bc136e22590..000000000000
--- a/include/asm-ppc64/of_device.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/of_device.h>
-
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
index a15422bcf30d..d404431f0a9a 100644
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -11,13 +11,7 @@
  */
 
 #include <linux/config.h>
-
-#ifdef __ASSEMBLY__
-  #define ASM_CONST(x) x
-#else
-  #define __ASM_CONST(x) x##UL
-  #define ASM_CONST(x) __ASM_CONST(x)
-#endif
+#include <asm/ppc_asm.h> /* for ASM_CONST */
 
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT      12
diff --git a/include/asm-ppc64/parport.h b/include/asm-ppc64/parport.h
deleted file mode 100644
index 2f8874c581cc..000000000000
--- a/include/asm-ppc64/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * parport.h: platform-specific PC-style parport initialisation
- *
- * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-
-#ifndef _ASM_PPC64_PARPORT_H
-#define _ASM_PPC64_PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports (autoirq, autodma);
-}
-
-#endif /* !(_ASM_PPC_PARPORT_H) */
diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h
index d8991389ab39..60cf8c838af0 100644
--- a/include/asm-ppc64/pci-bridge.h
+++ b/include/asm-ppc64/pci-bridge.h
@@ -2,7 +2,9 @@
 #ifndef _ASM_PCI_BRIDGE_H
 #define _ASM_PCI_BRIDGE_H
 
+#include <linux/config.h>
 #include <linux/pci.h>
+#include <linux/list.h>
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -34,7 +36,7 @@ struct pci_controller {
 
         struct pci_ops *ops;
         volatile unsigned int __iomem *cfg_addr;
-        volatile unsigned char __iomem *cfg_data;
+        volatile void __iomem *cfg_data;
 
         /* Currently, we limit ourselves to 1 IO range and 3 mem
          * ranges since the common pci_bus structure can't handle more
@@ -71,6 +73,12 @@ struct pci_dn {
         struct  iommu_table *iommu_table;       /* for phb's or bridges */
         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
         struct  device_node *node;      /* back-pointer to the device_node */
+#ifdef CONFIG_PPC_ISERIES
+        struct  list_head Device_List;
+        int             Irq;            /* Assigned IRQ */
+        int             Flags;          /* Possible flags(disable/bist)*/
+        u8              LogicalSlot;    /* Hv Slot Index for Tces */
+#endif
         u32     config_space[16];       /* saved PCI config space */
 };
 
@@ -96,6 +104,16 @@ static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
         return fetch_dev_dn(dev);
 }
 
+static inline int pci_device_from_OF_node(struct device_node *np,
+                                          u8 *bus, u8 *devfn)
+{
+        if (!PCI_DN(np))
+                return -ENODEV;
+        *bus = PCI_DN(np)->busno;
+        *devfn = PCI_DN(np)->devfn;
+        return 0;
+}
+
 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 {
         if (bus->self)
@@ -105,7 +123,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 }
 
 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
-                                         struct device_node *dev);
+                                         struct device_node *dev, int primary);
 
 extern int pcibios_remove_root_bus(struct pci_controller *phb);
 
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index a88bbfc26967..342e2d755550 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -168,7 +168,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev);
 
 struct file;
 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
-                                         unsigned long offset,
+                                         unsigned long pfn,
                                          unsigned long size,
                                          pgprot_t prot);
 
diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h
index c83679c9d2b0..8c3f574046b6 100644
--- a/include/asm-ppc64/pgtable.h
+++ b/include/asm-ppc64/pgtable.h
@@ -471,17 +471,19 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
                                      unsigned long size, pgprot_t vma_prot);
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 
 #define __HAVE_ARCH_PTE_SAME
 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 #define pmd_ERROR(e) \
         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 #define pud_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pud_val(e))
+        printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
diff --git a/include/asm-ppc64/pmac_feature.h b/include/asm-ppc64/pmac_feature.h
deleted file mode 100644
index e07e36c4cbb2..000000000000
--- a/include/asm-ppc64/pmac_feature.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/pmac_feature.h>
-
diff --git a/include/asm-ppc64/pmac_low_i2c.h b/include/asm-ppc64/pmac_low_i2c.h
deleted file mode 100644
index 7bcfc72c5c8a..000000000000
--- a/include/asm-ppc64/pmac_low_i2c.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/pmac_low_i2c.h>
-
diff --git a/include/asm-ppc64/ppc32.h b/include/asm-ppc64/ppc32.h
index 6b44a8caf395..3945a55d112a 100644
--- a/include/asm-ppc64/ppc32.h
+++ b/include/asm-ppc64/ppc32.h
@@ -70,18 +70,18 @@ typedef struct compat_siginfo {
 #define __old_sigaction32       old_sigaction32
 
 struct __old_sigaction32 {
-        unsigned                sa_handler;
+        compat_uptr_t           sa_handler;
         compat_old_sigset_t     sa_mask;
         unsigned int            sa_flags;
-        unsigned                sa_restorer;     /* not used by Linux/SPARC yet */
+        compat_uptr_t           sa_restorer;     /* not used by Linux/SPARC yet */
 };
 
 
 
 struct sigaction32 {
-       unsigned int  sa_handler;        /* Really a pointer, but need to deal with 32 bits */
+       compat_uptr_t  sa_handler;       /* Really a pointer, but need to deal with 32 bits */
        unsigned int sa_flags;
-       unsigned int sa_restorer;        /* Another 32 bit pointer */
+       compat_uptr_t sa_restorer;       /* Another 32 bit pointer */
        compat_sigset_t sa_mask;         /* A 32 bit mask */
 };
 
@@ -94,9 +94,9 @@ typedef struct sigaltstack_32 {
 struct sigcontext32 {
         unsigned int    _unused[4];
         int             signal;
-        unsigned int    handler;
+        compat_uptr_t   handler;
         unsigned int    oldmask;
-        u32 regs;  /* 4 byte pointer to the pt_regs32 structure. */
+        compat_uptr_t   regs;  /* 4 byte pointer to the pt_regs32 structure. */
 };
 
 struct mcontext32 {
@@ -111,7 +111,7 @@ struct ucontext32 {
         unsigned int            uc_link;
         stack_32_t              uc_stack;
         int                     uc_pad[7];
-        u32                     uc_regs;        /* points to uc_mcontext field */
+        compat_uptr_t           uc_regs;        /* points to uc_mcontext field */
         compat_sigset_t         uc_sigmask;     /* mask last for extensibility */
         /* glibc has 1024-bit signal masks, ours are 64-bit */
         int                     uc_maskext[30];
diff --git a/include/asm-ppc64/ppc_asm.h b/include/asm-ppc64/ppc_asm.h
deleted file mode 100644
index 9031d8a29aca..000000000000
--- a/include/asm-ppc64/ppc_asm.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * arch/ppc64/kernel/ppc_asm.h
- *
- * Definitions used by various bits of low-level assembly code on PowerPC.
- *
- * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#ifndef _PPC64_PPC_ASM_H
-#define _PPC64_PPC_ASM_H
-/*
- * Macros for storing registers into and loading registers from
- * exception frames.
- */
-#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
-#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
-#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-
-#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
-
-#define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
-#define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
-#define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
-#define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
-#define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
-#define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
-#define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
-#define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
-#define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
-#define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
-#define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
-#define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
-
-#define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
-#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
-#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
-#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
-#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
-#define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
-#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
-#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
-#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
-
-/* Macros to adjust thread priority for Iseries hardware multithreading */
-#define HMT_LOW         or 1,1,1
-#define HMT_MEDIUM      or 2,2,2
-#define HMT_HIGH        or 3,3,3
-
-/* Insert the high 32 bits of the MSR into what will be the new
-   MSR (via SRR1 and rfid)  This preserves the MSR.SF and MSR.ISF
-   bits. */
-
-#define FIX_SRR1(ra, rb)        \
-        mr      rb,ra;          \
-        mfmsr   ra;             \
-        rldimi  ra,rb,0,32
-
-#define CLR_TOP32(r)    rlwinm  (r),(r),0,0,31  /* clear top 32 bits */
-
-/* 
- * LOADADDR( rn, name )
- *   loads the address of 'name' into 'rn'
- *
- * LOADBASE( rn, name )
- *   loads the address (less the low 16 bits) of 'name' into 'rn'
- *   suitable for base+disp addressing
- */
-#define LOADADDR(rn,name) \
-        lis     rn,name##@highest;      \
-        ori     rn,rn,name##@higher;    \
-        rldicr  rn,rn,32,31;            \
-        oris    rn,rn,name##@h;         \
-        ori     rn,rn,name##@l
-
-#define LOADBASE(rn,name) \
-        lis     rn,name@highest;        \
-        ori     rn,rn,name@higher;      \
-        rldicr  rn,rn,32,31;            \
-        oris    rn,rn,name@ha
-
-
-#define SET_REG_TO_CONST(reg, value)                    \
-        lis     reg,(((value)>>48)&0xFFFF);             \
-        ori     reg,reg,(((value)>>32)&0xFFFF);         \
-        rldicr  reg,reg,32,31;                          \
-        oris    reg,reg,(((value)>>16)&0xFFFF);         \
-        ori     reg,reg,((value)&0xFFFF);
-
-#define SET_REG_TO_LABEL(reg, label)                    \
-        lis     reg,(label)@highest;                    \
-        ori     reg,reg,(label)@higher;                 \
-        rldicr  reg,reg,32,31;                          \
-        oris    reg,reg,(label)@h;                      \
-        ori     reg,reg,(label)@l;
-
-
-/* PPPBBB - DRENG  If KERNELBASE is always 0xC0...,
- * Then we can easily do this with one asm insn. -Peter
- */
-#define tophys(rd,rs)                           \
-        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
-        rldicr  rd,rd,32,31;                    \
-        sub     rd,rs,rd
-
-#define tovirt(rd,rs)                           \
-        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
-        rldicr  rd,rd,32,31;                    \
-        add     rd,rs,rd
-
-/* Condition Register Bit Fields */
-
-#define cr0     0
-#define cr1     1
-#define cr2     2
-#define cr3     3
-#define cr4     4
-#define cr5     5
-#define cr6     6
-#define cr7     7
-
-
-/* General Purpose Registers (GPRs) */
-
-#define r0      0
-#define r1      1
-#define r2      2
-#define r3      3
-#define r4      4
-#define r5      5
-#define r6      6
-#define r7      7
-#define r8      8
-#define r9      9
-#define r10     10
-#define r11     11
-#define r12     12
-#define r13     13
-#define r14     14
-#define r15     15
-#define r16     16
-#define r17     17
-#define r18     18
-#define r19     19
-#define r20     20
-#define r21     21
-#define r22     22
-#define r23     23
-#define r24     24
-#define r25     25
-#define r26     26
-#define r27     27
-#define r28     28
-#define r29     29
-#define r30     30
-#define r31     31
-
-
-/* Floating Point Registers (FPRs) */
-
-#define fr0     0
-#define fr1     1
-#define fr2     2
-#define fr3     3
-#define fr4     4
-#define fr5     5
-#define fr6     6
-#define fr7     7
-#define fr8     8
-#define fr9     9
-#define fr10    10
-#define fr11    11
-#define fr12    12
-#define fr13    13
-#define fr14    14
-#define fr15    15
-#define fr16    16
-#define fr17    17
-#define fr18    18
-#define fr19    19
-#define fr20    20
-#define fr21    21
-#define fr22    22
-#define fr23    23
-#define fr24    24
-#define fr25    25
-#define fr26    26
-#define fr27    27
-#define fr28    28
-#define fr29    29
-#define fr30    30
-#define fr31    31
-
-#define vr0     0
-#define vr1     1
-#define vr2     2
-#define vr3     3
-#define vr4     4
-#define vr5     5
-#define vr6     6
-#define vr7     7
-#define vr8     8
-#define vr9     9
-#define vr10    10
-#define vr11    11
-#define vr12    12
-#define vr13    13
-#define vr14    14
-#define vr15    15
-#define vr16    16
-#define vr17    17
-#define vr18    18
-#define vr19    19
-#define vr20    20
-#define vr21    21
-#define vr22    22
-#define vr23    23
-#define vr24    24
-#define vr25    25
-#define vr26    26
-#define vr27    27
-#define vr28    28
-#define vr29    29
-#define vr30    30
-#define vr31    31
-
-#endif /* _PPC64_PPC_ASM_H */
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
deleted file mode 100644
index 4146189006e3..000000000000
--- a/include/asm-ppc64/processor.h
+++ /dev/null
@@ -1,558 +0,0 @@
-#ifndef __ASM_PPC64_PROCESSOR_H
-#define __ASM_PPC64_PROCESSOR_H
-
-/*
- * Copyright (C) 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/stringify.h>
-#ifndef __ASSEMBLY__
-#include <linux/config.h>
-#include <asm/atomic.h>
-#include <asm/ppcdebug.h>
-#include <asm/a.out.h>
-#endif
-#include <asm/ptrace.h>
-#include <asm/types.h>
-#include <asm/systemcfg.h>
-#include <asm/cputable.h>
-
-/* Machine State Register (MSR) Fields */
-#define MSR_SF_LG       63              /* Enable 64 bit mode */
-#define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
-#define MSR_HV_LG       60              /* Hypervisor state */
-#define MSR_VEC_LG      25              /* Enable AltiVec */
-#define MSR_POW_LG      18              /* Enable Power Management */
-#define MSR_WE_LG       18              /* Wait State Enable */
-#define MSR_TGPR_LG     17              /* TLB Update registers in use */
-#define MSR_CE_LG       17              /* Critical Interrupt Enable */
-#define MSR_ILE_LG      16              /* Interrupt Little Endian */
-#define MSR_EE_LG       15              /* External Interrupt Enable */
-#define MSR_PR_LG       14              /* Problem State / Privilege Level */
-#define MSR_FP_LG       13              /* Floating Point enable */
-#define MSR_ME_LG       12              /* Machine Check Enable */
-#define MSR_FE0_LG      11              /* Floating Exception mode 0 */
-#define MSR_SE_LG       10              /* Single Step */
-#define MSR_BE_LG       9               /* Branch Trace */
-#define MSR_DE_LG       9               /* Debug Exception Enable */
-#define MSR_FE1_LG      8               /* Floating Exception mode 1 */
-#define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
-#define MSR_IR_LG       5               /* Instruction Relocate */
-#define MSR_DR_LG       4               /* Data Relocate */
-#define MSR_PE_LG       3               /* Protection Enable */
-#define MSR_PX_LG       2               /* Protection Exclusive Mode */
-#define MSR_PMM_LG      2               /* Performance monitor */
-#define MSR_RI_LG       1               /* Recoverable Exception */
-#define MSR_LE_LG       0               /* Little Endian */
-
-#ifdef __ASSEMBLY__
-#define __MASK(X)       (1<<(X))
-#else
-#define __MASK(X)       (1UL<<(X))
-#endif
-
-#define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
-#define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
-#define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
-#define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
-#define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
-#define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
-#define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
-#define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
-#define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
-#define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
-#define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
-#define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
-#define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
-#define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
-#define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
-#define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
-#define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
-#define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
-#define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
-#define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
-#define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
-#define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
-#define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
-#define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
-#define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
-#define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
-
-#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
-#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
-
-#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64      MSR_USER32 | MSR_SF
-
-/* Floating Point Status and Control Register (FPSCR) Fields */
-
-#define FPSCR_FX        0x80000000      /* FPU exception summary */
-#define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
-#define FPSCR_VX        0x20000000      /* Invalid operation summary */
-#define FPSCR_OX        0x10000000      /* Overflow exception summary */
-#define FPSCR_UX        0x08000000      /* Underflow exception summary */
-#define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
-#define FPSCR_XX        0x02000000      /* Inexact exception summary */
-#define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
-#define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
-#define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
-#define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
-#define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
-#define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
-#define FPSCR_FR        0x00040000      /* Fraction rounded */
-#define FPSCR_FI        0x00020000      /* Fraction inexact */
-#define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
-#define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
-#define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
-#define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
-#define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
-#define FPSCR_VE        0x00000080      /* Invalid op exception enable */
-#define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
-#define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
-#define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
-#define FPSCR_XE        0x00000008      /* FP inexact exception enable */
-#define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
-#define FPSCR_RN        0x00000003      /* FPU rounding control */
-
-/* Special Purpose Registers (SPRNs)*/
-
-#define SPRN_CTR        0x009   /* Count Register */
-#define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
-#define   DABR_TRANSLATION      (1UL << 2)
-#define SPRN_DAR        0x013   /* Data Address Register */
-#define SPRN_DEC        0x016   /* Decrement Register */
-#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
-#define   DSISR_NOHPTE          0x40000000      /* no translation found */
-#define   DSISR_PROTFAULT       0x08000000      /* protection fault */
-#define   DSISR_ISSTORE         0x02000000      /* access was a store */
-#define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
-#define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
-#define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
-#define SPRN_MSRDORM    0x3F1   /* Hardware Implementation Register 1 */
-#define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
-#define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
-#define SPRN_NIADORM    0x3F3   /* Hardware Implementation Register 2 */
-#define SPRN_HID4       0x3F4   /* 970 HID4 */
-#define SPRN_HID5       0x3F6   /* 970 HID5 */
-#define SPRN_HID6       0x3F9   /* BE HID 6 */
-#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
-#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
-#define SPRN_TSCR       0x399   /* Thread switch control on BE */
-#define SPRN_TTR        0x39A   /* Thread switch timeout on BE */
-#define   TSCR_DEC_ENABLE       0x200000 /* Decrementer Interrupt */
-#define   TSCR_EE_ENABLE        0x100000 /* External Interrupt */
-#define   TSCR_EE_BOOST         0x080000 /* External Interrupt Boost */
-#define SPRN_TSC        0x3FD   /* Thread switch control on others */
-#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
-#define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
-#define SPRN_LR         0x008   /* Link Register */
-#define SPRN_PIR        0x3FF   /* Processor Identification Register */
-#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
-#define SPRN_PURR       0x135   /* Processor Utilization of Resources Register */
-#define SPRN_PVR        0x11F   /* Processor Version Register */
-#define SPRN_RPA        0x3D6   /* Required Physical Address Register */
-#define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
-#define SPRN_SDR1       0x019   /* MMU Hash Base Register */
-#define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
-#define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
-#define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
-#define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
-#define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
-#define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
-#define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
-#define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
-#define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
-#define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, W/O) */
-#define SPRN_TBWU       0x11D   /* Time Base Write Upper Register (super, W/O) */
-#define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
-#define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
-#define SPRN_XER        0x001   /* Fixed Point Exception Register */
-#define SPRN_VRSAVE     0x100   /* Vector save */
-#define SPRN_CTRLF      0x088
-#define SPRN_CTRLT      0x098
-#define   CTRL_RUNLATCH 0x1
-
-/* Performance monitor SPRs */
-#define SPRN_SIAR       780
-#define SPRN_SDAR       781
-#define SPRN_MMCRA      786
-#define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
-#define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
-#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
-#define SPRN_PMC1       787
-#define SPRN_PMC2       788
-#define SPRN_PMC3       789
-#define SPRN_PMC4       790
-#define SPRN_PMC5       791
-#define SPRN_PMC6       792
-#define SPRN_PMC7       793
-#define SPRN_PMC8       794
-#define SPRN_MMCR0      795
-#define   MMCR0_FC      0x80000000UL /* freeze counters. set to 1 on a perfmon exception */
-#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
-#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
-#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
-#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
-#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
-#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
-#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
-#define   MMCR0_FCECE   0x02000000UL /* freeze counters on enabled condition or event */
-/* time base exception enable */
-#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
-#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
-#define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
-#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
-#define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
-#define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
-#define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
-#define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
-#define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
-#define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
-#define SPRN_MMCR1      798
-
-/* Short-hand versions for a number of the above SPRNs */
-
-#define CTR     SPRN_CTR        /* Counter Register */
-#define DAR     SPRN_DAR        /* Data Address Register */
-#define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
-#define DEC     SPRN_DEC        /* Decrement Register */
-#define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
-#define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
-#define MSRDORM SPRN_MSRDORM    /* MSR Dormant Register */
-#define NIADORM SPRN_NIADORM    /* NIA Dormant Register */
-#define TSC     SPRN_TSC        /* Thread switch control */
-#define TST     SPRN_TST        /* Thread switch timeout */
-#define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
-#define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
-#define __LR    SPRN_LR
-#define PVR     SPRN_PVR        /* Processor Version */
-#define PIR     SPRN_PIR        /* Processor ID */
-#define PURR    SPRN_PURR       /* Processor Utilization of Resource Register */
-#define SDR1    SPRN_SDR1       /* MMU hash base register */
-#define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
-#define SPR1    SPRN_SPRG1
-#define SPR2    SPRN_SPRG2
-#define SPR3    SPRN_SPRG3
-#define SPRG0   SPRN_SPRG0
-#define SPRG1   SPRN_SPRG1
-#define SPRG2   SPRN_SPRG2
-#define SPRG3   SPRN_SPRG3
-#define SRR0    SPRN_SRR0       /* Save and Restore Register 0 */
-#define SRR1    SPRN_SRR1       /* Save and Restore Register 1 */
-#define TBRL    SPRN_TBRL       /* Time Base Read Lower Register */
-#define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
-#define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
-#define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
-#define XER     SPRN_XER
-
-/* Processor Version Register (PVR) field extraction */
-
-#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
-#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
-
-/* Processor Version Numbers */
-#define PV_NORTHSTAR    0x0033
-#define PV_PULSAR       0x0034
-#define PV_POWER4       0x0035
-#define PV_ICESTAR      0x0036
-#define PV_SSTAR        0x0037
-#define PV_POWER4p      0x0038
-#define PV_970          0x0039
-#define PV_POWER5       0x003A
-#define PV_POWER5p      0x003B
-#define PV_970FX        0x003C
-#define PV_630          0x0040
-#define PV_630p         0x0041
-#define PV_970MP        0x0044
-#define PV_BE           0x0070
-
-/* Platforms supported by PPC64 */
-#define PLATFORM_PSERIES      0x0100
-#define PLATFORM_PSERIES_LPAR 0x0101
-#define PLATFORM_ISERIES_LPAR 0x0201
-#define PLATFORM_LPAR         0x0001
-#define PLATFORM_POWERMAC     0x0400
-#define PLATFORM_MAPLE        0x0500
-#define PLATFORM_BPA          0x1000
-
-/* Compatibility with drivers coming from PPC32 world */
-#define _machine        (systemcfg->platform)
-#define _MACH_Pmac      PLATFORM_POWERMAC
-
-/*
- * List of interrupt controllers.
- */
-#define IC_INVALID    0
-#define IC_OPEN_PIC   1
-#define IC_PPC_XIC    2
-#define IC_BPA_IIC    3
-
-#define XGLUE(a,b) a##b
-#define GLUE(a,b) XGLUE(a,b)
-
-#ifdef __ASSEMBLY__
-
-#define _GLOBAL(name) \
-        .section ".text"; \
-        .align 2 ; \
-        .globl name; \
-        .globl GLUE(.,name); \
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#define _KPROBE(name) \
-        .section ".kprobes.text","a"; \
-        .align 2 ; \
-        .globl name; \
-        .globl GLUE(.,name); \
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#define _STATIC(name) \
-        .section ".text"; \
-        .align 2 ; \
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#else /* __ASSEMBLY__ */
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-/* Macros for setting and retrieving special purpose registers */
-
-#define mfmsr()         ({unsigned long rval; \
-                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-
-#define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
-                                     : : "r" (v))
-#define mtmsrd(v)       __mtmsrd((v), 0)
-
-#define mfspr(rn)       ({unsigned long rval; \
-                        asm volatile("mfspr %0," __stringify(rn) \
-                                     : "=r" (rval)); rval;})
-#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
-
-#define mftb()          ({unsigned long rval;   \
-                        asm volatile("mftb %0" : "=r" (rval)); rval;})
-
-#define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
-#define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
-
-#define mfasr()         ({unsigned long rval; \
-                        asm volatile("mfasr %0" : "=r" (rval)); rval;})
-
-static inline void set_tb(unsigned int upper, unsigned int lower)
-{
-        mttbl(0);
-        mttbu(upper);
-        mttbl(lower);
-}
-
-#define __get_SP()      ({unsigned long sp; \
-                        asm volatile("mr %0,1": "=r" (sp)); sp;})
-
-#ifdef __KERNEL__
-
-extern int have_of;
-extern u64 ppc64_interrupt_controller;
-
-struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
-void release_thread(struct task_struct *);
-
-/* Prepare to copy thread state - unlazy all lazy status */
-extern void prepare_to_copy(struct task_struct *tsk);
-
-/* Create a new kernel thread. */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x0000100000000000UL)
-
-/* 
- * 32-bit user address space is 4GB - 1 page 
- * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
- */
-#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
-
-#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
-                TASK_SIZE_USER32 : TASK_SIZE_USER64)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
-#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
-
-#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)||(ppcdebugset(PPCDBG_BINFMT_32ADDR))) ? \
-                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
-
-typedef struct {
-        unsigned long seg;
-} mm_segment_t;
-
-struct thread_struct {
-        unsigned long   ksp;            /* Kernel stack pointer */
-        unsigned long   ksp_vsid;
-        struct pt_regs  *regs;          /* Pointer to saved register state */
-        mm_segment_t    fs;             /* for get_fs() validation */
-        double          fpr[32];        /* Complete floating point set */
-        unsigned long   fpscr;          /* Floating point status (plus pad) */
-        unsigned long   fpexc_mode;     /* Floating-point exception mode */
-        unsigned long   start_tb;       /* Start purr when proc switched in */
-        unsigned long   accum_tb;       /* Total accumilated purr for process */
-        unsigned long   vdso_base;      /* base of the vDSO library */
-        unsigned long   dabr;           /* Data address breakpoint register */
-#ifdef CONFIG_ALTIVEC
-        /* Complete AltiVec register set */
-        vector128       vr[32] __attribute((aligned(16)));
-        /* AltiVec status */
-        vector128       vscr __attribute((aligned(16)));
-        unsigned long   vrsave;
-        int             used_vr;        /* set if process has used altivec */
-#endif /* CONFIG_ALTIVEC */
-};
-
-#define ARCH_MIN_TASKALIGN 16
-
-#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD  { \
-        .ksp = INIT_SP, \
-        .regs = (struct pt_regs *)INIT_SP - 1, \
-        .fs = KERNEL_DS, \
-        .fpr = {0}, \
-        .fpscr = 0, \
-        .fpexc_mode = MSR_FE0|MSR_FE1, \
-}
-
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-#define thread_saved_pc(tsk)    \
-        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
-
-/* Get/set floating-point exception mode */
-#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
-#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
-
-extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
-extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
-
-static inline unsigned int __unpack_fe01(unsigned long msr_bits)
-{
-        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
-}
-
-static inline unsigned long __pack_fe01(unsigned int fpmode)
-{
-        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
-}
-
-#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
-
-/*
- * Prefetch macros.
- */
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-#define ARCH_HAS_SPINLOCK_PREFETCH
-
-static inline void prefetch(const void *x)
-{
-        if (unlikely(!x))
-                return;
-
-        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
-}
-
-static inline void prefetchw(const void *x)
-{
-        if (unlikely(!x))
-                return;
-
-        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
-}
-
-#define spin_lock_prefetch(x)   prefetchw(x)
-
-#define HAVE_ARCH_PICK_MMAP_LAYOUT
-
-static inline void ppc64_runlatch_on(void)
-{
-        unsigned long ctrl;
-
-        if (cpu_has_feature(CPU_FTR_CTRL)) {
-                ctrl = mfspr(SPRN_CTRLF);
-                ctrl |= CTRL_RUNLATCH;
-                mtspr(SPRN_CTRLT, ctrl);
-        }
-}
-
-static inline void ppc64_runlatch_off(void)
-{
-        unsigned long ctrl;
-
-        if (cpu_has_feature(CPU_FTR_CTRL)) {
-                ctrl = mfspr(SPRN_CTRLF);
-                ctrl &= ~CTRL_RUNLATCH;
-                mtspr(SPRN_CTRLT, ctrl);
-        }
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-#define RUNLATCH_ON(REG)                        \
-BEGIN_FTR_SECTION                               \
-        mfspr   (REG),SPRN_CTRLF;               \
-        ori     (REG),(REG),CTRL_RUNLATCH;      \
-        mtspr   SPRN_CTRLT,(REG);               \
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
-#endif
-
-/*
- * Number of entries in the SLB. If this ever changes we should handle
- * it with a use a cpu feature fixup.
- */
-#define SLB_NUM_ENTRIES 64
-
-#endif /* __ASM_PPC64_PROCESSOR_H */
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index c02ec1d6b909..e8d0d2ab4c0f 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -14,6 +14,7 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+#include <linux/config.h>
 #include <linux/proc_fs.h>
 #include <asm/atomic.h>
 
@@ -137,6 +138,9 @@ struct device_node {
         struct  kref kref;
         unsigned long _flags;
         void    *data;
+#ifdef CONFIG_PPC_ISERIES
+        struct list_head Device_List;
+#endif
 };
 
 extern struct device_node *of_chosen;
diff --git a/include/asm-ppc64/smp.h b/include/asm-ppc64/smp.h
index d86f742e9a21..c5e9052e7967 100644
--- a/include/asm-ppc64/smp.h
+++ b/include/asm-ppc64/smp.h
@@ -77,7 +77,6 @@ extern int smt_enabled_at_boot;
 
 extern int smp_mpic_probe(void);
 extern void smp_mpic_setup_cpu(int cpu);
-extern void smp_mpic_message_pass(int target, int msg);
 extern void smp_generic_kick_cpu(int nr);
 
 extern void smp_generic_give_timebase(void);
diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h
index 375015c62f20..99b8ca52f101 100644
--- a/include/asm-ppc64/system.h
+++ b/include/asm-ppc64/system.h
@@ -13,7 +13,7 @@
 #include <asm/page.h>
 #include <asm/processor.h>
 #include <asm/hw_irq.h>
-#include <asm/memory.h>
+#include <asm/synch.h>
 
 /*
  * Memory barrier.
@@ -48,7 +48,7 @@
 #ifdef CONFIG_SMP
 #define smp_mb()        mb()
 #define smp_rmb()       rmb()
-#define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
+#define smp_wmb()       eieio()
 #define smp_read_barrier_depends()  read_barrier_depends()
 #else
 #define smp_mb()        __asm__ __volatile__("": : :"memory")
@@ -120,8 +120,8 @@ extern void giveup_altivec(struct task_struct *);
 extern void disable_kernel_altivec(void);
 extern void enable_kernel_altivec(void);
 extern int emulate_altivec(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
-extern void cvt_df(double *from, float *to, unsigned long *fpscr);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 
 #ifdef CONFIG_ALTIVEC
 extern void flush_altivec_to_thread(struct task_struct *);
@@ -131,7 +131,12 @@ static inline void flush_altivec_to_thread(struct task_struct *t)
 }
 #endif
 
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
+
 extern int mem_init_done;       /* set on boot once kmalloc can be called */
+extern unsigned long memory_limit;
 
 /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
 extern unsigned char e2a(unsigned char);
@@ -144,12 +149,7 @@ struct thread_struct;
 extern struct task_struct * _switch(struct thread_struct *prev,
                                     struct thread_struct *next);
 
-static inline int __is_processor(unsigned long pv)
-{
-        unsigned long pvr;
-        asm("mfspr %0, 0x11F" : "=r" (pvr)); 
-        return(PVR_VER(pvr) == pv);
-}
+extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 
 /*
  * Atomic exchange
diff --git a/include/asm-ppc64/tce.h b/include/asm-ppc64/tce.h
new file mode 100644
index 000000000000..d40b6b42ab35
--- /dev/null
+++ b/include/asm-ppc64/tce.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
+ * Rewrite, cleanup:
+ * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _ASM_TCE_H
+#define _ASM_TCE_H
+
+/*
+ * Tces come in two formats, one for the virtual bus and a different
+ * format for PCI
+ */
+#define TCE_VB  0
+#define TCE_PCI 1
+
+/* TCE page size is 4096 bytes (1 << 12) */
+
+#define TCE_SHIFT       12
+#define TCE_PAGE_SIZE   (1 << TCE_SHIFT)
+#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
+
+
+/* tce_entry
+ * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
+ * abstracted so layout is irrelevant.
+ */
+union tce_entry {
+        unsigned long te_word;
+        struct {
+                unsigned int  tb_cacheBits :6;  /* Cache hash bits - not used */
+                unsigned int  tb_rsvd      :6;
+                unsigned long tb_rpn       :40; /* Real page number */
+                unsigned int  tb_valid     :1;  /* Tce is valid (vb only) */
+                unsigned int  tb_allio     :1;  /* Tce is valid for all lps (vb only) */
+                unsigned int  tb_lpindex   :8;  /* LpIndex for user of TCE (vb only) */
+                unsigned int  tb_pciwr     :1;  /* Write allowed (pci only) */
+                unsigned int  tb_rdwr      :1;  /* Read allowed  (pci), Write allowed (vb) */
+        } te_bits;
+#define te_cacheBits te_bits.tb_cacheBits
+#define te_rpn       te_bits.tb_rpn
+#define te_valid     te_bits.tb_valid
+#define te_allio     te_bits.tb_allio
+#define te_lpindex   te_bits.tb_lpindex
+#define te_pciwr     te_bits.tb_pciwr
+#define te_rdwr      te_bits.tb_rdwr
+};
+
+
+#endif
diff --git a/include/asm-ppc64/time.h b/include/asm-ppc64/time.h
deleted file mode 100644
index c6c762cad8b0..000000000000
--- a/include/asm-ppc64/time.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Common time prototypes and such for all ppc machines.
- *
- * Written by Cort Dougan (cort@cs.nmt.edu) to merge
- * Paul Mackerras' version and mine for PReP and Pmac.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __PPC64_TIME_H
-#define __PPC64_TIME_H
-
-#ifdef __KERNEL__
-#include <linux/config.h>
-#include <linux/types.h>
-#include <linux/mc146818rtc.h>
-
-#include <asm/processor.h>
-#include <asm/paca.h>
-#include <asm/iSeries/HvCall.h>
-
-/* time.c */
-extern unsigned long tb_ticks_per_jiffy;
-extern unsigned long tb_ticks_per_usec;
-extern unsigned long tb_ticks_per_sec;
-extern unsigned long tb_to_xs;
-extern unsigned      tb_to_us;
-extern unsigned long tb_last_stamp;
-
-struct rtc_time;
-extern void to_tm(int tim, struct rtc_time * tm);
-extern time_t last_rtc_update;
-
-void generic_calibrate_decr(void);
-void setup_default_decr(void);
-
-/* Some sane defaults: 125 MHz timebase, 1GHz processor */
-extern unsigned long ppc_proc_freq;
-#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
-extern unsigned long ppc_tb_freq;
-#define DEFAULT_TB_FREQ         125000000UL
-
-/*
- * By putting all of this stuff into a single struct we 
- * reduce the number of cache lines touched by do_gettimeofday.
- * Both by collecting all of the data in one cache line and
- * by touching only one TOC entry
- */
-struct gettimeofday_vars {
-        unsigned long tb_to_xs;
-        unsigned long stamp_xsec;
-        unsigned long tb_orig_stamp;
-};
-
-struct gettimeofday_struct {
-        unsigned long tb_ticks_per_sec;
-        struct gettimeofday_vars vars[2];
-        struct gettimeofday_vars * volatile varp;
-        unsigned      var_idx;
-        unsigned      tb_to_us;
-};
-
-struct div_result {
-        unsigned long result_high;
-        unsigned long result_low;
-};
-
-int via_calibrate_decr(void);
-
-static __inline__ unsigned long get_tb(void)
-{
-        return mftb();
-}
-
-/* Accessor functions for the decrementer register. */
-static __inline__ unsigned int get_dec(void)
-{
-        return (mfspr(SPRN_DEC));
-}
-
-static __inline__ void set_dec(int val)
-{
-#ifdef CONFIG_PPC_ISERIES
-        struct paca_struct *lpaca = get_paca();
-        int cur_dec;
-
-        if (lpaca->lppaca.shared_proc) {
-                lpaca->lppaca.virtual_decr = val;
-                cur_dec = get_dec();
-                if (cur_dec > val)
-                        HvCall_setVirtualDecr();
-        } else
-#endif
-                mtspr(SPRN_DEC, val);
-}
-
-static inline unsigned long tb_ticks_since(unsigned long tstamp)
-{
-        return get_tb() - tstamp;
-}
-
-#define mulhwu(x,y) \
-({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-#define mulhdu(x,y) \
-({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-
-
-unsigned mulhwu_scale_factor(unsigned, unsigned);
-void div128_by_32( unsigned long dividend_high, unsigned long dividend_low,
-                   unsigned divisor, struct div_result *dr );
-
-/* Used to store Processor Utilization register (purr) values */
-
-struct cpu_usage {
-        u64 current_tb;  /* Holds the current purr register values */
-};
-
-DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
-
-#endif /* __KERNEL__ */
-#endif /* __PPC64_TIME_H */
diff --git a/include/asm-ppc64/tlbflush.h b/include/asm-ppc64/tlbflush.h
index 74271d7c1d16..626f505c6ee3 100644
--- a/include/asm-ppc64/tlbflush.h
+++ b/include/asm-ppc64/tlbflush.h
@@ -20,10 +20,8 @@
 struct mm_struct;
 struct ppc64_tlb_batch {
         unsigned long index;
-        unsigned long context;
         struct mm_struct *mm;
         pte_t pte[PPC64_TLB_BATCH_NR];
-        unsigned long addr[PPC64_TLB_BATCH_NR];
         unsigned long vaddr[PPC64_TLB_BATCH_NR];
         unsigned int large;
 };
@@ -48,8 +46,7 @@ static inline void flush_tlb_pending(void)
 #define flush_tlb_kernel_range(start, end)      flush_tlb_pending()
 #define flush_tlb_pgtables(mm, start, end)      do { } while (0)
 
-extern void flush_hash_page(unsigned long context, unsigned long ea, pte_t pte,
-                            int local);
-void flush_hash_range(unsigned long context, unsigned long number, int local);
+extern void flush_hash_page(unsigned long va, pte_t pte, int local);
+void flush_hash_range(unsigned long number, int local);
 
 #endif /* _PPC64_TLBFLUSH_H */
diff --git a/include/asm-ppc64/udbg.h b/include/asm-ppc64/udbg.h
index c786604aef02..8192fb8541cc 100644
--- a/include/asm-ppc64/udbg.h
+++ b/include/asm-ppc64/udbg.h
@@ -28,4 +28,7 @@ extern unsigned long udbg_ifdebug(unsigned long flags);
 extern void __init ppcdbg_initialize(void);
 
 extern void udbg_init_uart(void __iomem *comport, unsigned int speed);
+
+struct device_node;
+extern void udbg_init_scc(struct device_node *np);
 #endif
diff --git a/include/asm-ppc64/uninorth.h b/include/asm-ppc64/uninorth.h
deleted file mode 100644
index 7ad7059f2c80..000000000000
--- a/include/asm-ppc64/uninorth.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/uninorth.h>
-
diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h
deleted file mode 100644
index 977bc980c1af..000000000000
--- a/include/asm-ppc64/unistd.h
+++ /dev/null
@@ -1,487 +0,0 @@
-#ifndef _ASM_PPC_UNISTD_H_
-#define _ASM_PPC_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define __NR_restart_syscall      0
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-#define __NR_waitpid              7
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_time                13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_lchown              16
-#define __NR_break               17
-#define __NR_oldstat             18
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-#define __NR_umount              22
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_ptrace              26
-#define __NR_alarm               27
-#define __NR_oldfstat            28
-#define __NR_pause               29
-#define __NR_utime               30
-#define __NR_stty                31
-#define __NR_gtty                32
-#define __NR_access              33
-#define __NR_nice                34
-#define __NR_ftime               35
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-#define __NR_prof                44
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-#define __NR_signal              48
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_umount2             52
-#define __NR_lock                53
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-#define __NR_mpx                 56
-#define __NR_setpgid             57
-#define __NR_ulimit              58
-#define __NR_oldolduname         59
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-#define __NR_sigaction           67
-#define __NR_sgetmask            68
-#define __NR_ssetmask            69
-#define __NR_setreuid            70
-#define __NR_setregid            71
-#define __NR_sigsuspend          72
-#define __NR_sigpending          73
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-#define __NR_getrlimit           76
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-#define __NR_select              82
-#define __NR_symlink             83
-#define __NR_oldlstat            84
-#define __NR_readlink            85
-#define __NR_uselib              86
-#define __NR_swapon              87
-#define __NR_reboot              88
-#define __NR_readdir             89
-#define __NR_mmap                90
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-#define __NR_profil              98
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-#define __NR_ioperm             101
-#define __NR_socketcall         102
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-#define __NR_olduname           109
-#define __NR_iopl               110
-#define __NR_vhangup            111
-#define __NR_idle               112
-#define __NR_vm86               113
-#define __NR_wait4              114
-#define __NR_swapoff            115
-#define __NR_sysinfo            116
-#define __NR_ipc                117
-#define __NR_fsync              118
-#define __NR_sigreturn          119
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-#define __NR_modify_ldt         123
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-#define __NR_sigprocmask        126
-#define __NR_create_module      127
-#define __NR_init_module        128
-#define __NR_delete_module      129
-#define __NR_get_kernel_syms    130
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-#define __NR_sysfs              135
-#define __NR_personality        136
-#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-#define __NR__newselect         142
-#define __NR_flock              143
-#define __NR_msync              144
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-#define __NR_mlock              150
-#define __NR_munlock            151
-#define __NR_mlockall           152
-#define __NR_munlockall         153
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-#define __NR_query_module       166
-#define __NR_poll               167
-#define __NR_nfsservctl         168
-#define __NR_setresgid          169
-#define __NR_getresgid          170
-#define __NR_prctl              171
-#define __NR_rt_sigreturn       172
-#define __NR_rt_sigaction       173
-#define __NR_rt_sigprocmask     174
-#define __NR_rt_sigpending      175
-#define __NR_rt_sigtimedwait    176
-#define __NR_rt_sigqueueinfo    177
-#define __NR_rt_sigsuspend      178
-#define __NR_pread64            179
-#define __NR_pwrite64           180
-#define __NR_chown              181
-#define __NR_getcwd             182
-#define __NR_capget             183
-#define __NR_capset             184
-#define __NR_sigaltstack        185
-#define __NR_sendfile           186
-#define __NR_getpmsg            187     /* some people actually want streams */
-#define __NR_putpmsg            188     /* some people actually want streams */
-#define __NR_vfork              189
-#define __NR_ugetrlimit         190     /* SuS compliant getrlimit */
-#define __NR_readahead          191
-/* #define __NR_mmap2           192     32bit only */
-/* #define __NR_truncate64      193     32bit only */
-/* #define __NR_ftruncate64     194     32bit only */
-/* #define __NR_stat64          195     32bit only */
-/* #define __NR_lstat64         196     32bit only */
-/* #define __NR_fstat64         197     32bit only */
-#define __NR_pciconfig_read     198
-#define __NR_pciconfig_write    199
-#define __NR_pciconfig_iobase   200
-#define __NR_multiplexer        201
-#define __NR_getdents64         202
-#define __NR_pivot_root         203
-/* #define __NR_fcntl64         204     32bit only */
-#define __NR_madvise            205
-#define __NR_mincore            206
-#define __NR_gettid             207
-#define __NR_tkill              208
-#define __NR_setxattr           209
-#define __NR_lsetxattr          210
-#define __NR_fsetxattr          211
-#define __NR_getxattr           212
-#define __NR_lgetxattr          213
-#define __NR_fgetxattr          214
-#define __NR_listxattr          215
-#define __NR_llistxattr         216
-#define __NR_flistxattr         217
-#define __NR_removexattr        218
-#define __NR_lremovexattr       219
-#define __NR_fremovexattr       220
-#define __NR_futex              221
-#define __NR_sched_setaffinity  222
-#define __NR_sched_getaffinity  223
-/* 224 currently unused */
-#define __NR_tuxcall            225
-/* #define __NR_sendfile64      226     32bit only */
-#define __NR_io_setup           227
-#define __NR_io_destroy         228
-#define __NR_io_getevents       229
-#define __NR_io_submit          230
-#define __NR_io_cancel          231
-#define __NR_set_tid_address    232
-#define __NR_fadvise64          233
-#define __NR_exit_group         234
-#define __NR_lookup_dcookie     235
-#define __NR_epoll_create       236
-#define __NR_epoll_ctl          237
-#define __NR_epoll_wait         238
-#define __NR_remap_file_pages   239
-#define __NR_timer_create       240
-#define __NR_timer_settime      241
-#define __NR_timer_gettime      242
-#define __NR_timer_getoverrun   243
-#define __NR_timer_delete       244
-#define __NR_clock_settime      245
-#define __NR_clock_gettime      246
-#define __NR_clock_getres       247
-#define __NR_clock_nanosleep    248
-#define __NR_swapcontext        249
-#define __NR_tgkill             250
-#define __NR_utimes             251
-#define __NR_statfs64           252
-#define __NR_fstatfs64          253
-/* #define __NR_fadvise64_64    254     32bit only */
-#define __NR_rtas               255
-/* Number 256 is reserved for sys_debug_setcontext */
-/* Number 257 is reserved for vserver */
-/* 258 currently unused */
-#define __NR_mbind              259
-#define __NR_get_mempolicy      260
-#define __NR_set_mempolicy      261
-#define __NR_mq_open            262
-#define __NR_mq_unlink          263
-#define __NR_mq_timedsend       264
-#define __NR_mq_timedreceive    265
-#define __NR_mq_notify          266
-#define __NR_mq_getsetattr      267
-#define __NR_kexec_load         268
-#define __NR_add_key            269
-#define __NR_request_key        270
-#define __NR_keyctl             271
-#define __NR_waitid             272
-#define __NR_ioprio_set         273
-#define __NR_ioprio_get         274
-#define __NR_inotify_init       275
-#define __NR_inotify_add_watch  276
-#define __NR_inotify_rm_watch   277
-
-#define __NR_syscalls           278
-#ifdef __KERNEL__
-#define NR_syscalls     __NR_syscalls
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* On powerpc a system call basically clobbers the same registers like a
- * function call, with the exception of LR (which is needed for the
- * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal
- * an error return status).
- */
-
-#define __syscall_nr(nr, type, name, args...)                           \
-        unsigned long __sc_ret, __sc_err;                               \
-        {                                                               \
-                register unsigned long __sc_0  __asm__ ("r0");          \
-                register unsigned long __sc_3  __asm__ ("r3");          \
-                register unsigned long __sc_4  __asm__ ("r4");          \
-                register unsigned long __sc_5  __asm__ ("r5");          \
-                register unsigned long __sc_6  __asm__ ("r6");          \
-                register unsigned long __sc_7  __asm__ ("r7");          \
-                register unsigned long __sc_8  __asm__ ("r8");          \
-                                                                        \
-                __sc_loadargs_##nr(name, args);                         \
-                __asm__ __volatile__                                    \
-                        ("sc           \n\t"                            \
-                         "mfcr %0      "                                \
-                        : "=&r" (__sc_0),                               \
-                          "=&r" (__sc_3),  "=&r" (__sc_4),              \
-                          "=&r" (__sc_5),  "=&r" (__sc_6),              \
-                          "=&r" (__sc_7),  "=&r" (__sc_8)               \
-                        : __sc_asm_input_##nr                           \
-                        : "cr0", "ctr", "memory",                       \
-                                "r9", "r10","r11", "r12");              \
-                __sc_ret = __sc_3;                                      \
-                __sc_err = __sc_0;                                      \
-        }                                                               \
-        if (__sc_err & 0x10000000)                                      \
-        {                                                               \
-                errno = __sc_ret;                                       \
-                __sc_ret = -1;                                          \
-        }                                                               \
-        return (type) __sc_ret
-
-#define __sc_loadargs_0(name, dummy...)                                 \
-        __sc_0 = __NR_##name
-#define __sc_loadargs_1(name, arg1)                                     \
-        __sc_loadargs_0(name);                                          \
-        __sc_3 = (unsigned long) (arg1)
-#define __sc_loadargs_2(name, arg1, arg2)                               \
-        __sc_loadargs_1(name, arg1);                                    \
-        __sc_4 = (unsigned long) (arg2)
-#define __sc_loadargs_3(name, arg1, arg2, arg3)                         \
-        __sc_loadargs_2(name, arg1, arg2);                              \
-        __sc_5 = (unsigned long) (arg3)
-#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4)                   \
-        __sc_loadargs_3(name, arg1, arg2, arg3);                        \
-        __sc_6 = (unsigned long) (arg4)
-#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5)             \
-        __sc_loadargs_4(name, arg1, arg2, arg3, arg4);                  \
-        __sc_7 = (unsigned long) (arg5)
-#define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6)       \
-        __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5);            \
-        __sc_8 = (unsigned long) (arg6)
-
-#define __sc_asm_input_0 "0" (__sc_0)
-#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
-#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
-#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
-#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
-#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
-#define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8)
-
-#define _syscall0(type,name)                                            \
-type name(void)                                                         \
-{                                                                       \
-        __syscall_nr(0, type, name);                                    \
-}
-
-#define _syscall1(type,name,type1,arg1)                                 \
-type name(type1 arg1)                                                   \
-{                                                                       \
-        __syscall_nr(1, type, name, arg1);                              \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2)                      \
-type name(type1 arg1, type2 arg2)                                       \
-{                                                                       \
-        __syscall_nr(2, type, name, arg1, arg2);                        \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)           \
-type name(type1 arg1, type2 arg2, type3 arg3)                           \
-{                                                                       \
-        __syscall_nr(3, type, name, arg1, arg2, arg3);                  \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4)               \
-{                                                                       \
-        __syscall_nr(4, type, name, arg1, arg2, arg3, arg4);            \
-}
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)   \
-{                                                                       \
-        __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5);      \
-}
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6)       \
-{                                                                       \
-        __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6);        \
-}
-
-#ifdef __KERNEL_SYSCALLS__
-
-/*
- * Forking from kernel space will result in the child getting a new,
- * empty kernel stack area.  Thus the child cannot access automatic
- * variables set in the parent unless they are in registers, and the
- * procedure where the fork was done cannot return to its caller in
- * the child.
- */
-
-/*
- * System call prototypes.
- */
-static inline _syscall3(int, execve, __const__ char *, file, char **, argv,
-                        char **,envp)
-
-#endif /* __KERNEL_SYSCALLS__ */
-
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_COMPAT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-
-unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot,
-                       unsigned long flags, unsigned long fd, off_t offset);
-struct pt_regs;
-int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
-                unsigned long a3, unsigned long a4, unsigned long a5,
-                struct pt_regs *regs);
-int sys_clone(unsigned long clone_flags, unsigned long p2, unsigned long p3,
-                unsigned long p4, unsigned long p5, unsigned long p6,
-                struct pt_regs *regs);
-int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
-                unsigned long p4, unsigned long p5, unsigned long p6,
-                struct pt_regs *regs);
-int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
-                unsigned long p4, unsigned long p5, unsigned long p6,
-                struct pt_regs *regs);
-int sys_pipe(int __user *fildes);
-int sys_ptrace(long request, long pid, long addr, long data);
-struct sigaction;
-long sys_rt_sigaction(int sig, const struct sigaction __user *act,
-                      struct sigaction __user *oact, size_t sigsetsize);
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
-
-#endif          /* __KERNEL__ */
-
-#endif          /* __ASSEMBLY__ */
-
-#endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h
deleted file mode 100644
index 1092af55d707..000000000000
--- a/include/asm-ppc64/xics.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* 
- * arch/ppc64/kernel/xics.h
- *
- * Copyright 2000 IBM Corporation.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#ifndef _PPC64_KERNEL_XICS_H
-#define _PPC64_KERNEL_XICS_H
-
-#include <linux/cache.h>
-
-void xics_init_IRQ(void);
-int xics_get_irq(struct pt_regs *);
-void xics_setup_cpu(void);
-void xics_teardown_cpu(int secondary);
-void xics_cause_IPI(int cpu);
-void xics_request_IPIs(void);
-void xics_migrate_irqs_away(void);
-
-/* first argument is ignored for now*/
-void pSeriesLP_cppr_info(int n_cpu, u8 value);
-
-struct xics_ipi_struct {
-        volatile unsigned long value;
-} ____cacheline_aligned;
-
-extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
-
-#endif /* _PPC64_KERNEL_XICS_H */
diff --git a/include/asm-s390/rwsem.h b/include/asm-s390/rwsem.h
index 8c0cebbfc034..0422a085dd56 100644
--- a/include/asm-s390/rwsem.h
+++ b/include/asm-s390/rwsem.h
@@ -351,5 +351,10 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
         return new;
 }
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* __KERNEL__ */
 #endif /* _S390_RWSEM_H */
diff --git a/include/asm-s390/semaphore.h b/include/asm-s390/semaphore.h
index 873def6f363a..702cf436698c 100644
--- a/include/asm-s390/semaphore.h
+++ b/include/asm-s390/semaphore.h
@@ -29,9 +29,6 @@ struct semaphore {
 #define __SEMAPHORE_INITIALIZER(name,count) \
         { ATOMIC_INIT(count), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h
index 0d51c484c2ea..348a88137445 100644
--- a/include/asm-s390/setup.h
+++ b/include/asm-s390/setup.h
@@ -8,11 +8,14 @@
 #ifndef _ASM_S390_SETUP_H
 #define _ASM_S390_SETUP_H
 
+#include <asm/types.h>
+
 #define PARMAREA                0x10400
 #define COMMAND_LINE_SIZE       896
 #define RAMDISK_ORIGIN          0x800000
 #define RAMDISK_SIZE            0x800000
 #define MEMORY_CHUNKS           16      /* max 0x7fff */
+#define IPL_PARMBLOCK_ORIGIN    0x2000
 
 #ifndef __ASSEMBLY__
 
@@ -64,6 +67,53 @@ extern unsigned int console_irq;
 #define SET_CONSOLE_3215        do { console_mode = 2; } while (0)
 #define SET_CONSOLE_3270        do { console_mode = 3; } while (0)
 
+struct ipl_list_header {
+        u32 length;
+        u8  reserved[3];
+        u8  version;
+} __attribute__((packed));
+
+struct ipl_block_fcp {
+        u32 length;
+        u8  pbt;
+        u8  reserved1[322-1];
+        u16 devno;
+        u8  reserved2[4];
+        u64 wwpn;
+        u64 lun;
+        u32 bootprog;
+        u8  reserved3[12];
+        u64 br_lba;
+        u32 scp_data_len;
+        u8  reserved4[260];
+        u8  scp_data[];
+} __attribute__((packed));
+
+struct ipl_parameter_block {
+        union {
+                u32 length;
+                struct ipl_list_header header;
+        } hdr;
+        struct ipl_block_fcp fcp;
+} __attribute__((packed));
+
+#define IPL_MAX_SUPPORTED_VERSION (0)
+
+#define IPL_TYPE_FCP (0)
+
+/*
+ * IPL validity flags and parameters as detected in head.S
+ */
+extern u32 ipl_parameter_flags;
+extern u16 ipl_devno;
+
+#define IPL_DEVNO_VALID         (ipl_parameter_flags & 1)
+#define IPL_PARMBLOCK_VALID     (ipl_parameter_flags & 2)
+
+#define IPL_PARMBLOCK_START     ((struct ipl_parameter_block *) \
+                                 IPL_PARMBLOCK_ORIGIN)
+#define IPL_PARMBLOCK_SIZE      (IPL_PARMBLOCK_START->hdr.length)
+
 #else 
 
 #ifndef __s390x__
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index 221e965da924..f97d92691f17 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -590,7 +590,6 @@ asmlinkage long sys_clone(struct pt_regs regs);
 asmlinkage long sys_fork(struct pt_regs regs);
 asmlinkage long sys_vfork(struct pt_regs regs);
 asmlinkage long sys_pipe(unsigned long __user *fildes);
-asmlinkage long sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
index 80d164c1529e..d3fa5c2b889d 100644
--- a/include/asm-sh/dma-mapping.h
+++ b/include/asm-sh/dma-mapping.h
@@ -9,7 +9,7 @@
 extern struct bus_type pci_bus_type;
 
 /* arch/sh/mm/consistent.c */
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *handle);
 extern void consistent_free(void *vaddr, size_t size);
 extern void consistent_sync(void *vaddr, size_t size, int direction);
 
@@ -26,7 +26,7 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
 }
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, int flag)
+                         dma_addr_t *dma_handle, gfp_t flag)
 {
         if (sh_mv.mv_consistent_alloc) {
                 void *ret;
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
index 5771f4baa478..3f18aa180516 100644
--- a/include/asm-sh/machvec.h
+++ b/include/asm-sh/machvec.h
@@ -64,7 +64,7 @@ struct sh_machine_vector
 
         void (*mv_heartbeat)(void);
 
-        void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, int);
+        void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t);
         int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t);
 };
 
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 0f4bcaae61bd..aef8ae43de13 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -224,8 +224,6 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
 
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
-
 #define pmd_page_kernel(pmd) \
 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 1be4337f5259..0262d3d1e5e0 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -166,5 +166,10 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
         return atomic_add_return(delta, (atomic_t *)(&sem->count));
 }
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_SH_RWSEM_H */
diff --git a/include/asm-sh/semaphore.h b/include/asm-sh/semaphore.h
index b923a77a8a7e..489f7847c5d9 100644
--- a/include/asm-sh/semaphore.h
+++ b/include/asm-sh/semaphore.h
@@ -33,9 +33,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index ea89e8f223ea..f2c8e14d1fd9 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -503,7 +503,6 @@ asmlinkage int sys_vfork(unsigned long r4, unsigned long r5,
 asmlinkage int sys_pipe(unsigned long r4, unsigned long r5,
                         unsigned long r6, unsigned long r7,
                         struct pt_regs regs);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char *buf,
                                 size_t count, long dummy, loff_t pos);
 asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char *buf,
diff --git a/include/asm-sh64/dma-mapping.h b/include/asm-sh64/dma-mapping.h
index b8d26fe677f4..cc9a2e86f5b4 100644
--- a/include/asm-sh64/dma-mapping.h
+++ b/include/asm-sh64/dma-mapping.h
@@ -25,7 +25,7 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
 }
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, int flag)
+                         dma_addr_t *dma_handle, gfp_t flag)
 {
         return consistent_alloc(NULL, size, dma_handle);
 }
diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h
index 51db4307bfaf..51b05818e4eb 100644
--- a/include/asm-sh64/pgtable.h
+++ b/include/asm-sh64/pgtable.h
@@ -457,9 +457,6 @@ extern inline pte_t pte_mkhuge(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _
 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
 
-#define page_pte_prot(page, prot) mk_pte(page, prot)
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
-
 typedef pte_t *pte_addr_t;
 #define pgtable_cache_init()    do { } while (0)
 
diff --git a/include/asm-sh64/semaphore.h b/include/asm-sh64/semaphore.h
index fce22bb9a546..469526459149 100644
--- a/include/asm-sh64/semaphore.h
+++ b/include/asm-sh64/semaphore.h
@@ -40,9 +40,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-sparc/dma-mapping.h b/include/asm-sparc/dma-mapping.h
index 2dc5bb8effa6..d7c3b0f0a901 100644
--- a/include/asm-sparc/dma-mapping.h
+++ b/include/asm-sparc/dma-mapping.h
@@ -8,7 +8,7 @@
 #else
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, int flag)
+                         dma_addr_t *dma_handle, gfp_t flag)
 {
         BUG();
         return NULL;
diff --git a/include/asm-sparc/floppy.h b/include/asm-sparc/floppy.h
index caf926116506..7a941b800b6b 100644
--- a/include/asm-sparc/floppy.h
+++ b/include/asm-sparc/floppy.h
@@ -17,10 +17,8 @@
 
 /* We don't need no stinkin' I/O port allocation crap. */
 #undef release_region
-#undef check_region
 #undef request_region
 #define release_region(X, Y)    do { } while(0)
-#define check_region(X, Y)      (0)
 #define request_region(X, Y, Z) (1)
 
 /* References:
diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h
index a14e98677500..b33c35411e82 100644
--- a/include/asm-sparc/pgtable.h
+++ b/include/asm-sparc/pgtable.h
@@ -255,8 +255,6 @@ BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
 #define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
 #define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
 
-#define page_pte_prot(page, prot)       mk_pte(page, prot)
-#define page_pte(page)                  mk_pte(page, __pgprot(0))
 #define pfn_pte(pfn, prot)              mk_pte(pfn_to_page(pfn), prot)
 
 BTFIXUPDEF_CALL(unsigned long,   pte_pfn, pte_t)
diff --git a/include/asm-sparc/semaphore.h b/include/asm-sparc/semaphore.h
index 60ac5fd9eb48..f74ba31e265b 100644
--- a/include/asm-sparc/semaphore.h
+++ b/include/asm-sparc/semaphore.h
@@ -22,9 +22,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h
index 1c5da41653a4..c7d5804ba76d 100644
--- a/include/asm-sparc64/dma-mapping.h
+++ b/include/asm-sparc64/dma-mapping.h
@@ -10,7 +10,7 @@
 struct device;
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, int flag)
+                         dma_addr_t *dma_handle, gfp_t flag)
 {
         BUG();
         return NULL;
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index 8c6dfc6c7af6..9a02879b235d 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -231,9 +231,6 @@ extern struct page *mem_map_zero;
 #define pte_pfn(x)              ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT)
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 
-#define page_pte_prot(page, prot)       mk_pte(page, prot)
-#define page_pte(page)                  page_pte_prot(page, __pgprot(0))
-
 static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
 {
         pte_t __pte;
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index 4568ee4022df..cef5e8270421 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -56,6 +56,11 @@ static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
         atomic_add(delta, (atomic_t *)(&sem->count));
 }
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* _SPARC64_RWSEM_H */
diff --git a/include/asm-sparc64/semaphore.h b/include/asm-sparc64/semaphore.h
index 7419dd88b49e..093dcc6788db 100644
--- a/include/asm-sparc64/semaphore.h
+++ b/include/asm-sparc64/semaphore.h
@@ -22,9 +22,6 @@ struct semaphore {
         { ATOMIC_INIT(count), \
           __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name, count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-sparc64/tlb.h b/include/asm-sparc64/tlb.h
index 9baf57db01d2..66138d959df5 100644
--- a/include/asm-sparc64/tlb.h
+++ b/include/asm-sparc64/tlb.h
@@ -25,9 +25,8 @@ struct mmu_gather {
         struct mm_struct *mm;
         unsigned int pages_nr;
         unsigned int need_flush;
-        unsigned int tlb_frozen;
+        unsigned int fullmm;
         unsigned int tlb_nr;
-        unsigned long freed;
         unsigned long vaddrs[TLB_BATCH_NR];
         struct page *pages[FREE_PTE_NR];
 };
@@ -44,14 +43,13 @@ extern void flush_tlb_pending(void);
 
 static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
+        struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
 
         BUG_ON(mp->tlb_nr);
 
         mp->mm = mm;
         mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
-        mp->tlb_frozen = full_mm_flush;
-        mp->freed = 0;
+        mp->fullmm = full_mm_flush;
 
         return mp;
 }
@@ -78,30 +76,19 @@ extern void smp_flush_tlb_mm(struct mm_struct *mm);
 
 static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
 {
-        unsigned long freed = mp->freed;
-        struct mm_struct *mm = mp->mm;
-        unsigned long rss = get_mm_counter(mm, rss);
-
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
-
         tlb_flush_mmu(mp);
 
-        if (mp->tlb_frozen) {
-                if (CTX_VALID(mm->context))
-                        do_flush_tlb_mm(mm);
-                mp->tlb_frozen = 0;
+        if (mp->fullmm) {
+                if (CTX_VALID(mp->mm->context))
+                        do_flush_tlb_mm(mp->mm);
+                mp->fullmm = 0;
         } else
                 flush_tlb_pending();
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-}
 
-static inline unsigned int tlb_is_full_mm(struct mmu_gather *mp)
-{
-        return mp->tlb_frozen;
+        put_cpu_var(mmu_gathers);
 }
 
 static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
diff --git a/include/asm-um/cache.h b/include/asm-um/cache.h
index 4b134fe8504e..a10602a5b2d6 100644
--- a/include/asm-um/cache.h
+++ b/include/asm-um/cache.h
@@ -1,10 +1,21 @@
 #ifndef __UM_CACHE_H
 #define __UM_CACHE_H
 
-/* These are x86 numbers */
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#include <linux/config.h>
 
-#define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
+#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
+# define L1_CACHE_SHIFT         (CONFIG_X86_L1_CACHE_SHIFT)
+#elif defined(CONFIG_UML_X86) /* 64-bit */
+# define L1_CACHE_SHIFT         6 /* Should be 7 on Intel */
+#else
+/* XXX: this was taken from x86, now it's completely random. Luckily only
+ * affects SMP padding. */
+# define L1_CACHE_SHIFT         5
+#endif
+
+/* XXX: this is valid for x86 and x86_64. */
+#define L1_CACHE_SHIFT_MAX      7       /* largest L1 which this arch supports */
+
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
 #endif
diff --git a/include/asm-um/dma-mapping.h b/include/asm-um/dma-mapping.h
index 13e6291f7151..babd29895114 100644
--- a/include/asm-um/dma-mapping.h
+++ b/include/asm-um/dma-mapping.h
@@ -19,7 +19,7 @@ dma_set_mask(struct device *dev, u64 dma_mask)
 
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   int flag)
+                   gfp_t flag)
 {
         BUG();
         return((void *) 0);
diff --git a/include/asm-um/linkage.h b/include/asm-um/linkage.h
index 7dfce37adc8b..e3d62dcbd356 100644
--- a/include/asm-um/linkage.h
+++ b/include/asm-um/linkage.h
@@ -3,4 +3,12 @@
 
 #include "asm/arch/linkage.h"
 
+#include <linux/config.h>
+
+/* <linux/linkage.h> will pick sane defaults */
+#ifdef CONFIG_GPROF
+#undef FASTCALL
+#undef fastcall
+#endif
+
 #endif
diff --git a/include/asm-um/page.h b/include/asm-um/page.h
index 2c192abe9aeb..0229814af31e 100644
--- a/include/asm-um/page.h
+++ b/include/asm-um/page.h
@@ -115,7 +115,7 @@ extern unsigned long uml_physmem;
 #define pfn_valid(pfn) ((pfn) < max_mapnr)
 #define virt_addr_valid(v) pfn_valid(phys_to_pfn(__pa(v)))
 
-extern struct page *arch_validate(struct page *page, int mask, int order);
+extern struct page *arch_validate(struct page *page, gfp_t mask, int order);
 #define HAVE_ARCH_VALIDATE
 
 extern void arch_free_page(struct page *page, int order);
diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h
index 616d02b57ea9..ac64eb955868 100644
--- a/include/asm-um/pgtable.h
+++ b/include/asm-um/pgtable.h
@@ -138,7 +138,7 @@ extern unsigned long pg0[1024];
 
 #define pte_clear(mm,addr,xp) pte_set_val(*(xp), (phys_t) 0, __pgprot(_PAGE_NEWPAGE))
 
-#define pmd_none(x)     (!(pmd_val(x) & ~_PAGE_NEWPAGE))
+#define pmd_none(x)     (!((unsigned long)pmd_val(x) & ~_PAGE_NEWPAGE))
 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 #define pmd_clear(xp)   do { pmd_val(*(xp)) = _PAGE_NEWPAGE; } while (0)
diff --git a/include/asm-v850/semaphore.h b/include/asm-v850/semaphore.h
index c514062bb69e..df6cdecf6c1f 100644
--- a/include/asm-v850/semaphore.h
+++ b/include/asm-v850/semaphore.h
@@ -18,9 +18,6 @@ struct semaphore {
         { ATOMIC_INIT (count), 0,                                             \
           __WAIT_QUEUE_HEAD_INITIALIZER ((name).wait) }
 
-#define __MUTEX_INITIALIZER(name)                                             \
-        __SEMAPHORE_INITIALIZER (name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER (name,count)
 
diff --git a/include/asm-v850/unistd.h b/include/asm-v850/unistd.h
index 3b552096c0e8..5a86f8e976ec 100644
--- a/include/asm-v850/unistd.h
+++ b/include/asm-v850/unistd.h
@@ -452,7 +452,6 @@ unsigned long sys_mmap2(unsigned long addr, size_t len,
 struct pt_regs;
 int sys_execve (char *name, char **argv, char **envp, struct pt_regs *regs);
 int sys_pipe (int *fildes);
-int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-x86_64/dma-mapping.h b/include/asm-x86_64/dma-mapping.h
index 45ca88c875c0..36d16dfbac88 100644
--- a/include/asm-x86_64/dma-mapping.h
+++ b/include/asm-x86_64/dma-mapping.h
@@ -17,7 +17,7 @@ extern dma_addr_t bad_dma_address;
         (swiotlb ? swiotlb_dma_mapping_error(x) : ((x) == bad_dma_address))
 
 void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                         unsigned gfp);
+                         gfp_t gfp);
 void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
                          dma_addr_t dma_handle);
 
diff --git a/include/asm-x86_64/mtrr.h b/include/asm-x86_64/mtrr.h
index c5959d6418bb..66ac1c0f27e1 100644
--- a/include/asm-x86_64/mtrr.h
+++ b/include/asm-x86_64/mtrr.h
@@ -25,6 +25,7 @@
 
 #include <linux/config.h>
 #include <linux/ioctl.h>
+#include <linux/compat.h>
 
 #define MTRR_IOCTL_BASE 'M'
 
@@ -105,4 +106,36 @@ static __inline__ int mtrr_del_page (int reg, unsigned long base,
 
 #endif
 
+#ifdef CONFIG_COMPAT
+
+struct mtrr_sentry32
+{
+    compat_ulong_t base;    /*  Base address     */
+    compat_uint_t size;    /*  Size of region   */
+    compat_uint_t type;     /*  Type of region   */
+};
+
+struct mtrr_gentry32
+{
+    compat_ulong_t regnum;   /*  Register number  */
+    compat_uint_t base;    /*  Base address     */
+    compat_uint_t size;    /*  Size of region   */
+    compat_uint_t type;     /*  Type of region   */
+};
+
+#define MTRR_IOCTL_BASE 'M'
+
+#define MTRRIOC32_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry32)
+#define MTRRIOC32_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry32)
+#define MTRRIOC32_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry32)
+#define MTRRIOC32_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32)
+#define MTRRIOC32_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry32)
+#define MTRRIOC32_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry32)
+#define MTRRIOC32_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry32)
+#define MTRRIOC32_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry32)
+#define MTRRIOC32_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32)
+#define MTRRIOC32_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry32)
+
+#endif /* CONFIG_COMPAT */
+
 #endif  /*  _LINUX_MTRR_H  */
diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h
index 5a82a6762c21..eeb3088a1c9e 100644
--- a/include/asm-x86_64/pci.h
+++ b/include/asm-x86_64/pci.h
@@ -50,10 +50,10 @@ extern int iommu_setup(char *opt);
  * address space.  The networking and block device layers use
  * this boolean for bounce buffer decisions
  *
- * On x86-64 it mostly equals, but we set it to zero to tell some subsystems
- * that an hard or soft IOMMU is available.
+ * On AMD64 it mostly equals, but we set it to zero to tell some subsystems
+ * that an IOMMU is available.
  */
-#define PCI_DMA_BUS_IS_PHYS 0
+#define PCI_DMA_BUS_IS_PHYS     (no_iommu ? 1 : 0)
 
 /*
  * x86-64 always supports DAC, but sometimes it is useful to force
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index dd8711ecaf2f..7a07196a7202 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -318,8 +318,6 @@ static inline int pmd_large(pmd_t pte) {
  * and a page entry and page directory to the page they refer to.
  */
 
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
-
 /*
  * Level 4 access.
  */
diff --git a/include/asm-x86_64/rwsem.h b/include/asm-x86_64/rwsem.h
index c002175b6e82..46077e9c1910 100644
--- a/include/asm-x86_64/rwsem.h
+++ b/include/asm-x86_64/rwsem.h
@@ -274,5 +274,10 @@ LOCK_PREFIX	"xaddl %0,(%2)"
         return tmp+delta;
 }
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
 #endif /* __KERNEL__ */
 #endif /* _X8664_RWSEM_H */
diff --git a/include/asm-x86_64/semaphore.h b/include/asm-x86_64/semaphore.h
index f325e39bf3b9..a389aa6fe80f 100644
--- a/include/asm-x86_64/semaphore.h
+++ b/include/asm-x86_64/semaphore.h
@@ -56,9 +56,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/asm-x86_64/swiotlb.h b/include/asm-x86_64/swiotlb.h
index 9b011dd8d19d..dddf1b218681 100644
--- a/include/asm-x86_64/swiotlb.h
+++ b/include/asm-x86_64/swiotlb.h
@@ -35,7 +35,7 @@ extern void swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg,
                          int nents, int direction);
 extern int swiotlb_dma_mapping_error(dma_addr_t dma_addr);
 extern void *swiotlb_alloc_coherent (struct device *hwdev, size_t size,
-                                     dma_addr_t *dma_handle, int flags);
+                                     dma_addr_t *dma_handle, gfp_t flags);
 extern void swiotlb_free_coherent (struct device *hwdev, size_t size,
                                    void *vaddr, dma_addr_t dma_handle);
 
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index 11ba931cf82f..3c494b65d33a 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -780,8 +780,6 @@ asmlinkage long sys_pipe(int *fildes);
 #include <linux/types.h>
 #include <asm/ptrace.h>
 
-asmlinkage long sys_ptrace(long request, long pid,
-                                unsigned long addr, long data);
 asmlinkage long sys_iopl(unsigned int level, struct pt_regs *regs);
 asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on);
 struct sigaction;
diff --git a/include/asm-xtensa/dma-mapping.h b/include/asm-xtensa/dma-mapping.h
index e86a206f1209..c425f10d086a 100644
--- a/include/asm-xtensa/dma-mapping.h
+++ b/include/asm-xtensa/dma-mapping.h
@@ -28,7 +28,7 @@ extern void consistent_sync(void*, size_t, int);
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 
 void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, int flag);
+                           dma_addr_t *dma_handle, gfp_t flag);
 
 void dma_free_coherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t dma_handle);
diff --git a/include/asm-xtensa/semaphore.h b/include/asm-xtensa/semaphore.h
index 09e89ab3eb61..2a10e193b929 100644
--- a/include/asm-xtensa/semaphore.h
+++ b/include/asm-xtensa/semaphore.h
@@ -29,9 +29,6 @@ struct semaphore {
         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
 
-#define __MUTEX_INITIALIZER(name)                                       \
-        __SEMAPHORE_INITIALIZER(name, 1)
-
 #define __DECLARE_SEMAPHORE_GENERIC(name,count)                         \
         struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 
diff --git a/include/keys/user-type.h b/include/keys/user-type.h
new file mode 100644
index 000000000000..26f6ec38577a
--- /dev/null
+++ b/include/keys/user-type.h
@@ -0,0 +1,47 @@
+/* user-type.h: User-defined key type
+ *
+ * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _KEYS_USER_TYPE_H
+#define _KEYS_USER_TYPE_H
+
+#include <linux/key.h>
+#include <linux/rcupdate.h>
+
+/*****************************************************************************/
+/*
+ * the payload for a key of type "user"
+ * - once filled in and attached to a key:
+ *   - the payload struct is invariant may not be changed, only replaced
+ *   - the payload must be read with RCU procedures or with the key semaphore
+ *     held
+ *   - the payload may only be replaced with the key semaphore write-locked
+ * - the key's data length is the size of the actual data, not including the
+ *   payload wrapper
+ */
+struct user_key_payload {
+        struct rcu_head rcu;            /* RCU destructor */
+        unsigned short  datalen;        /* length of this data */
+        char            data[0];        /* actual data */
+};
+
+extern struct key_type key_type_user;
+
+extern int user_instantiate(struct key *key, const void *data, size_t datalen);
+extern int user_duplicate(struct key *key, const struct key *source);
+extern int user_update(struct key *key, const void *data, size_t datalen);
+extern int user_match(const struct key *key, const void *criterion);
+extern void user_destroy(struct key *key);
+extern void user_describe(const struct key *user, struct seq_file *m);
+extern long user_read(const struct key *key,
+                      char __user *buffer, size_t buflen);
+
+
+#endif /* _KEYS_USER_TYPE_H */
diff --git a/include/linux/ata.h b/include/linux/ata.h
index a5b74efab067..d2873b732bb1 100644
--- a/include/linux/ata.h
+++ b/include/linux/ata.h
@@ -42,13 +42,18 @@ enum {
         ATA_SECT_SIZE           = 512,
 
         ATA_ID_WORDS            = 256,
-        ATA_ID_PROD_OFS         = 27,
-        ATA_ID_FW_REV_OFS       = 23,
         ATA_ID_SERNO_OFS        = 10,
-        ATA_ID_MAJOR_VER        = 80,
-        ATA_ID_PIO_MODES        = 64,
+        ATA_ID_FW_REV_OFS       = 23,
+        ATA_ID_PROD_OFS         = 27,
+        ATA_ID_OLD_PIO_MODES    = 51,
+        ATA_ID_FIELD_VALID      = 53,
         ATA_ID_MWDMA_MODES      = 63,
+        ATA_ID_PIO_MODES        = 64,
+        ATA_ID_EIDE_DMA_MIN     = 65,
+        ATA_ID_EIDE_PIO         = 67,
+        ATA_ID_EIDE_PIO_IORDY   = 68,
         ATA_ID_UDMA_MODES       = 88,
+        ATA_ID_MAJOR_VER        = 80,
         ATA_ID_PIO4             = (1 << 1),
 
         ATA_PCI_CTL_OFS         = 2,
@@ -128,10 +133,15 @@ enum {
         ATA_CMD_PIO_READ_EXT    = 0x24,
         ATA_CMD_PIO_WRITE       = 0x30,
         ATA_CMD_PIO_WRITE_EXT   = 0x34,
+        ATA_CMD_READ_MULTI      = 0xC4,
+        ATA_CMD_READ_MULTI_EXT  = 0x29,
+        ATA_CMD_WRITE_MULTI     = 0xC5,
+        ATA_CMD_WRITE_MULTI_EXT = 0x39,
         ATA_CMD_SET_FEATURES    = 0xEF,
         ATA_CMD_PACKET          = 0xA0,
         ATA_CMD_VERIFY          = 0x40,
         ATA_CMD_VERIFY_EXT      = 0x42,
+        ATA_CMD_INIT_DEV_PARAMS = 0x91,
 
         /* SETFEATURES stuff */
         SETFEATURES_XFER        = 0x03,
@@ -146,14 +156,14 @@ enum {
         XFER_MW_DMA_2           = 0x22,
         XFER_MW_DMA_1           = 0x21,
         XFER_MW_DMA_0           = 0x20,
+        XFER_SW_DMA_2           = 0x12,
+        XFER_SW_DMA_1           = 0x11,
+        XFER_SW_DMA_0           = 0x10,
         XFER_PIO_4              = 0x0C,
         XFER_PIO_3              = 0x0B,
         XFER_PIO_2              = 0x0A,
         XFER_PIO_1              = 0x09,
         XFER_PIO_0              = 0x08,
-        XFER_SW_DMA_2           = 0x12,
-        XFER_SW_DMA_1           = 0x11,
-        XFER_SW_DMA_0           = 0x10,
         XFER_PIO_SLOW           = 0x00,
 
         /* ATAPI stuff */
@@ -181,6 +191,7 @@ enum {
         ATA_TFLAG_ISADDR        = (1 << 1), /* enable r/w to nsect/lba regs */
         ATA_TFLAG_DEVICE        = (1 << 2), /* enable r/w to device reg */
         ATA_TFLAG_WRITE         = (1 << 3), /* data dir: host->dev==1 (write) */
+        ATA_TFLAG_LBA           = (1 << 4), /* enable LBA */
 };
 
 enum ata_tf_protocols {
@@ -250,7 +261,19 @@ struct ata_taskfile {
           ((u64) (id)[(n) + 1] << 16) | \
           ((u64) (id)[(n) + 0]) )
 
-static inline int atapi_cdb_len(u16 *dev_id)
+static inline int ata_id_current_chs_valid(const u16 *id)
+{
+        /* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command 
+           has not been issued to the device then the values of 
+           id[54] to id[56] are vendor specific. */
+        return (id[53] & 0x01) && /* Current translation valid */
+                id[54] &&  /* cylinders in current translation */
+                id[55] &&  /* heads in current translation */
+                id[55] <= 16 &&
+                id[56];    /* sectors in current translation */
+}
+
+static inline int atapi_cdb_len(const u16 *dev_id)
 {
         u16 tmp = dev_id[0] & 0x3;
         switch (tmp) {
@@ -260,7 +283,7 @@ static inline int atapi_cdb_len(u16 *dev_id)
         }
 }
 
-static inline int is_atapi_taskfile(struct ata_taskfile *tf)
+static inline int is_atapi_taskfile(const struct ata_taskfile *tf)
 {
         return (tf->protocol == ATA_PROT_ATAPI) ||
                (tf->protocol == ATA_PROT_ATAPI_NODATA) ||
diff --git a/include/linux/audit.h b/include/linux/audit.h
index b2a2509bd7ea..da3c01955f3d 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -260,11 +260,11 @@ extern int audit_filter_user(struct netlink_skb_parms *cb, int type);
 #ifdef CONFIG_AUDIT
 /* These are defined in audit.c */
                                 /* Public API */
-extern void                 audit_log(struct audit_context *ctx, int gfp_mask,
+extern void                 audit_log(struct audit_context *ctx, gfp_t gfp_mask,
                                       int type, const char *fmt, ...)
                                       __attribute__((format(printf,4,5)));
 
-extern struct audit_buffer *audit_log_start(struct audit_context *ctx, int gfp_mask, int type);
+extern struct audit_buffer *audit_log_start(struct audit_context *ctx, gfp_t gfp_mask, int type);
 extern void                 audit_log_format(struct audit_buffer *ab,
                                              const char *fmt, ...)
                             __attribute__((format(printf,2,3)));
diff --git a/include/linux/bio.h b/include/linux/bio.h
index 3344b4e8e43a..685fd3720df5 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -301,7 +301,7 @@ extern struct bio *bio_map_user_iov(struct request_queue *,
                                     struct sg_iovec *, int, int);
 extern void bio_unmap_user(struct bio *);
 extern struct bio *bio_map_kern(struct request_queue *, void *, unsigned int,
-                                unsigned int);
+                                gfp_t);
 extern void bio_set_pages_dirty(struct bio *bio);
 extern void bio_check_pages_dirty(struct bio *bio);
 extern struct bio *bio_copy_user(struct request_queue *, unsigned long, unsigned int, int);
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 86dd5502b05c..7d8ff97b3e92 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -40,6 +40,8 @@
  * bitmap_weight(src, nbits)                    Hamming Weight: number set bits
  * bitmap_shift_right(dst, src, n, nbits)       *dst = *src >> n
  * bitmap_shift_left(dst, src, n, nbits)        *dst = *src << n
+ * bitmap_remap(dst, src, old, new, nbits)      *dst = map(old, new)(src)
+ * bitmap_bitremap(oldbit, old, new, nbits)     newbit = map(old, new)(oldbit)
  * bitmap_scnprintf(buf, len, src, nbits)       Print bitmap src to buf
  * bitmap_parse(ubuf, ulen, dst, nbits)         Parse bitmap dst from user buf
  * bitmap_scnlistprintf(buf, len, src, nbits)   Print bitmap src as list to buf
@@ -104,6 +106,10 @@ extern int bitmap_scnlistprintf(char *buf, unsigned int len,
                         const unsigned long *src, int nbits);
 extern int bitmap_parselist(const char *buf, unsigned long *maskp,
                         int nmaskbits);
+extern void bitmap_remap(unsigned long *dst, const unsigned long *src,
+                const unsigned long *old, const unsigned long *new, int bits);
+extern int bitmap_bitremap(int oldbit,
+                const unsigned long *old, const unsigned long *new, int bits);
 extern int bitmap_find_free_region(unsigned long *bitmap, int bits, int order);
 extern void bitmap_release_region(unsigned long *bitmap, int pos, int order);
 extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order);
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index efdc9b5bc05c..025a7f084dbd 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -96,8 +96,8 @@ struct io_context {
 
 void put_io_context(struct io_context *ioc);
 void exit_io_context(void);
-struct io_context *current_io_context(int gfp_flags);
-struct io_context *get_io_context(int gfp_flags);
+struct io_context *current_io_context(gfp_t gfp_flags);
+struct io_context *get_io_context(gfp_t gfp_flags);
 void copy_io_context(struct io_context **pdst, struct io_context **psrc);
 void swap_io_context(struct io_context **ioc1, struct io_context **ioc2);
 
@@ -107,9 +107,9 @@ typedef void (rq_end_io_fn)(struct request *);
 struct request_list {
         int count[2];
         int starved[2];
+        int elvpriv;
         mempool_t *rq_pool;
         wait_queue_head_t wait[2];
-        wait_queue_head_t drain;
 };
 
 #define BLK_MAX_CDB     16
@@ -203,6 +203,7 @@ struct request {
 enum rq_flag_bits {
         __REQ_RW,               /* not set, read. set, write */
         __REQ_FAILFAST,         /* no low level driver retries */
+        __REQ_SORTED,           /* elevator knows about this request */
         __REQ_SOFTBARRIER,      /* may not be passed by ioscheduler */
         __REQ_HARDBARRIER,      /* may not be passed by drive either */
         __REQ_CMD,              /* is a regular fs rw request */
@@ -210,6 +211,7 @@ enum rq_flag_bits {
         __REQ_STARTED,          /* drive already may have started this one */
         __REQ_DONTPREP,         /* don't call prep for this one */
         __REQ_QUEUED,           /* uses queueing */
+        __REQ_ELVPRIV,          /* elevator private data attached */
         /*
          * for ATA/ATAPI devices
          */
@@ -235,6 +237,7 @@ enum rq_flag_bits {
 
 #define REQ_RW          (1 << __REQ_RW)
 #define REQ_FAILFAST    (1 << __REQ_FAILFAST)
+#define REQ_SORTED      (1 << __REQ_SORTED)
 #define REQ_SOFTBARRIER (1 << __REQ_SOFTBARRIER)
 #define REQ_HARDBARRIER (1 << __REQ_HARDBARRIER)
 #define REQ_CMD         (1 << __REQ_CMD)
@@ -242,6 +245,7 @@ enum rq_flag_bits {
 #define REQ_STARTED     (1 << __REQ_STARTED)
 #define REQ_DONTPREP    (1 << __REQ_DONTPREP)
 #define REQ_QUEUED      (1 << __REQ_QUEUED)
+#define REQ_ELVPRIV     (1 << __REQ_ELVPRIV)
 #define REQ_PC          (1 << __REQ_PC)
 #define REQ_BLOCK_PC    (1 << __REQ_BLOCK_PC)
 #define REQ_SENSE       (1 << __REQ_SENSE)
@@ -333,6 +337,12 @@ struct request_queue
         end_flush_fn            *end_flush_fn;
 
         /*
+         * Dispatch queue sorting
+         */
+        sector_t                end_sector;
+        struct request          *boundary_rq;
+
+        /*
          * Auto-unplugging state
          */
         struct timer_list       unplug_timer;
@@ -354,7 +364,7 @@ struct request_queue
          * queue needs bounce pages for pages above this limit
          */
         unsigned long           bounce_pfn;
-        unsigned int            bounce_gfp;
+        gfp_t                   bounce_gfp;
 
         /*
          * various queue flags, see QUEUE_* below
@@ -405,8 +415,6 @@ struct request_queue
         unsigned int            sg_reserved_size;
         int                     node;
 
-        struct list_head        drain_list;
-
         /*
          * reserved for flush operations
          */
@@ -434,7 +442,7 @@ enum {
 #define QUEUE_FLAG_DEAD         5       /* queue being torn down */
 #define QUEUE_FLAG_REENTER      6       /* Re-entrancy avoidance */
 #define QUEUE_FLAG_PLUGGED      7       /* queue is plugged */
-#define QUEUE_FLAG_DRAIN        8       /* draining queue for sched switch */
+#define QUEUE_FLAG_ELVSWITCH    8       /* don't use elevator, just do FIFO */
 #define QUEUE_FLAG_FLUSH        9       /* doing barrier flush sequence */
 
 #define blk_queue_plugged(q)    test_bit(QUEUE_FLAG_PLUGGED, &(q)->queue_flags)
@@ -454,6 +462,7 @@ enum {
 #define blk_pm_request(rq)      \
         ((rq)->flags & (REQ_PM_SUSPEND | REQ_PM_RESUME))
 
+#define blk_sorted_rq(rq)       ((rq)->flags & REQ_SORTED)
 #define blk_barrier_rq(rq)      ((rq)->flags & REQ_HARDBARRIER)
 #define blk_barrier_preflush(rq)        ((rq)->flags & REQ_BAR_PREFLUSH)
 #define blk_barrier_postflush(rq)       ((rq)->flags & REQ_BAR_POSTFLUSH)
@@ -550,7 +559,7 @@ extern void generic_make_request(struct bio *bio);
 extern void blk_put_request(struct request *);
 extern void blk_end_sync_rq(struct request *rq);
 extern void blk_attempt_remerge(request_queue_t *, struct request *);
-extern struct request *blk_get_request(request_queue_t *, int, int);
+extern struct request *blk_get_request(request_queue_t *, int, gfp_t);
 extern void blk_insert_request(request_queue_t *, struct request *, int, void *);
 extern void blk_requeue_request(request_queue_t *, struct request *);
 extern void blk_plug_device(request_queue_t *);
@@ -565,7 +574,7 @@ extern void blk_run_queue(request_queue_t *);
 extern void blk_queue_activity_fn(request_queue_t *, activity_fn *, void *);
 extern int blk_rq_map_user(request_queue_t *, struct request *, void __user *, unsigned int);
 extern int blk_rq_unmap_user(struct bio *, unsigned int);
-extern int blk_rq_map_kern(request_queue_t *, struct request *, void *, unsigned int, unsigned int);
+extern int blk_rq_map_kern(request_queue_t *, struct request *, void *, unsigned int, gfp_t);
 extern int blk_rq_map_user_iov(request_queue_t *, struct request *, struct sg_iovec *, int);
 extern int blk_execute_rq(request_queue_t *, struct gendisk *,
                           struct request *, int);
@@ -611,12 +620,21 @@ extern void end_request(struct request *req, int uptodate);
 
 static inline void blkdev_dequeue_request(struct request *req)
 {
-        BUG_ON(list_empty(&req->queuelist));
+        elv_dequeue_request(req->q, req);
+}
 
-        list_del_init(&req->queuelist);
+/*
+ * This should be in elevator.h, but that requires pulling in rq and q
+ */
+static inline void elv_dispatch_add_tail(struct request_queue *q,
+                                         struct request *rq)
+{
+        if (q->last_merge == rq)
+                q->last_merge = NULL;
 
-        if (req->rl)
-                elv_remove_request(req->q, req);
+        q->end_sector = rq_end_sector(rq);
+        q->boundary_rq = rq;
+        list_add_tail(&rq->queuelist, &q->queue_head);
 }
 
 /*
@@ -650,12 +668,10 @@ extern void blk_dump_rq_flags(struct request *, char *);
 extern void generic_unplug_device(request_queue_t *);
 extern void __generic_unplug_device(request_queue_t *);
 extern long nr_blockdev_pages(void);
-extern void blk_wait_queue_drained(request_queue_t *, int);
-extern void blk_finish_queue_drain(request_queue_t *);
 
 int blk_get_queue(request_queue_t *);
-request_queue_t *blk_alloc_queue(int gfp_mask);
-request_queue_t *blk_alloc_queue_node(int,int);
+request_queue_t *blk_alloc_queue(gfp_t);
+request_queue_t *blk_alloc_queue_node(gfp_t, int);
 #define blk_put_queue(q) blk_cleanup_queue((q))
 
 /*
diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h
index 6a1d154c0825..1db061bb6b08 100644
--- a/include/linux/buffer_head.h
+++ b/include/linux/buffer_head.h
@@ -126,8 +126,8 @@ BUFFER_FNS(Eopnotsupp, eopnotsupp)
 /* If we *know* page->private refers to buffer_heads */
 #define page_buffers(page)                                      \
         ({                                                      \
-                BUG_ON(!PagePrivate(page));             \
-                ((struct buffer_head *)(page)->private);        \
+                BUG_ON(!PagePrivate(page));                     \
+                ((struct buffer_head *)page_private(page));     \
         })
 #define page_has_buffers(page)  PagePrivate(page)
 
@@ -188,8 +188,9 @@ extern int buffer_heads_over_limit;
  * Generic address_space_operations implementations for buffer_head-backed
  * address_spaces.
  */
-int try_to_release_page(struct page * page, int gfp_mask);
+int try_to_release_page(struct page * page, gfp_t gfp_mask);
 int block_invalidatepage(struct page *page, unsigned long offset);
+int do_invalidatepage(struct page *page, unsigned long offset);
 int block_write_full_page(struct page *page, get_block_t *get_block,
                                 struct writeback_control *wbc);
 int block_read_full_page(struct page*, get_block_t*);
@@ -219,7 +220,7 @@ static inline void attach_page_buffers(struct page *page,
 {
         page_cache_get(page);
         SetPagePrivate(page);
-        page->private = (unsigned long)head;
+        set_page_private(page, (unsigned long)head);
 }
 
 static inline void get_bh(struct buffer_head *bh)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 86980c68234a..1f7b2c097503 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -32,6 +32,7 @@ struct cpu {
 };
 
 extern int register_cpu(struct cpu *, int, struct node *);
+extern struct sys_device *get_cpu_sysdev(int cpu);
 #ifdef CONFIG_HOTPLUG_CPU
 extern void unregister_cpu(struct cpu *, struct node *);
 #endif
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index ff7f80f48df1..d068176b7ad7 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -23,6 +23,7 @@
 #include <linux/completion.h>
 #include <linux/workqueue.h>
 #include <linux/cpumask.h>
+#include <asm/div64.h>
 
 #define CPUFREQ_NAME_LEN 16
 
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 9bdba8169b41..13e9f4a3ab26 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -12,6 +12,8 @@
  * see bitmap_scnprintf() and bitmap_parse() in lib/bitmap.c.
  * For details of cpulist_scnprintf() and cpulist_parse(), see
  * bitmap_scnlistprintf() and bitmap_parselist(), also in bitmap.c.
+ * For details of cpu_remap(), see bitmap_bitremap in lib/bitmap.c
+ * For details of cpus_remap(), see bitmap_remap in lib/bitmap.c.
  *
  * The available cpumask operations are:
  *
@@ -50,6 +52,8 @@
  * int cpumask_parse(ubuf, ulen, mask)  Parse ascii string as cpumask
  * int cpulist_scnprintf(buf, len, mask) Format cpumask as list for printing
  * int cpulist_parse(buf, map)          Parse ascii string as cpulist
+ * int cpu_remap(oldbit, old, new)      newbit = map(old, new)(oldbit)
+ * int cpus_remap(dst, src, old, new)   *dst = map(old, new)(src)
  *
  * for_each_cpu_mask(cpu, mask)         for-loop cpu over mask
  *
@@ -294,6 +298,22 @@ static inline int __cpulist_parse(const char *buf, cpumask_t *dstp, int nbits)
         return bitmap_parselist(buf, dstp->bits, nbits);
 }
 
+#define cpu_remap(oldbit, old, new) \
+                __cpu_remap((oldbit), &(old), &(new), NR_CPUS)
+static inline int __cpu_remap(int oldbit,
+                const cpumask_t *oldp, const cpumask_t *newp, int nbits)
+{
+        return bitmap_bitremap(oldbit, oldp->bits, newp->bits, nbits);
+}
+
+#define cpus_remap(dst, src, old, new) \
+                __cpus_remap(&(dst), &(src), &(old), &(new), NR_CPUS)
+static inline void __cpus_remap(cpumask_t *dstp, const cpumask_t *srcp,
+                const cpumask_t *oldp, const cpumask_t *newp, int nbits)
+{
+        bitmap_remap(dstp->bits, srcp->bits, oldp->bits, newp->bits, nbits);
+}
+
 #if NR_CPUS > 1
 #define for_each_cpu_mask(cpu, mask)            \
         for ((cpu) = first_cpu(mask);           \
diff --git a/include/linux/cyclomx.h b/include/linux/cyclomx.h
index 04fa7dff079c..300d704bdb9a 100644
--- a/include/linux/cyclomx.h
+++ b/include/linux/cyclomx.h
@@ -37,8 +37,6 @@
 #include <linux/cycx_x25.h>
 #endif
 
-#define is_digit(ch) (((ch)>=(unsigned)'0'&&(ch)<=(unsigned)'9')?1:0)
-
 /* Adapter Data Space.
  * This structure is needed because we handle multiple cards, otherwise
  * static data would do it.
diff --git a/include/linux/cycx_drv.h b/include/linux/cycx_drv.h
index 6621df86a748..12fe6b0bfcff 100644
--- a/include/linux/cycx_drv.h
+++ b/include/linux/cycx_drv.h
@@ -60,6 +60,5 @@ extern int cycx_peek(struct cycx_hw *hw, u32 addr, void *buf, u32 len);
 extern int cycx_poke(struct cycx_hw *hw, u32 addr, void *buf, u32 len);
 extern int cycx_exec(void __iomem *addr);
 
-extern void cycx_inten(struct cycx_hw *hw);
 extern void cycx_intr(struct cycx_hw *hw);
 #endif  /* _CYCX_DRV_H */
diff --git a/include/linux/device.h b/include/linux/device.h
index 95d607a48f06..17cbc6db67b4 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -28,19 +28,6 @@
 #define BUS_ID_SIZE             KOBJ_NAME_LEN
 
 
-enum {
-        SUSPEND_NOTIFY,
-        SUSPEND_SAVE_STATE,
-        SUSPEND_DISABLE,
-        SUSPEND_POWER_DOWN,
-};
-
-enum {
-        RESUME_POWER_ON,
-        RESUME_RESTORE_STATE,
-        RESUME_ENABLE,
-};
-
 struct device;
 struct device_driver;
 struct class;
@@ -115,8 +102,8 @@ struct device_driver {
         int     (*probe)        (struct device * dev);
         int     (*remove)       (struct device * dev);
         void    (*shutdown)     (struct device * dev);
-        int     (*suspend)      (struct device * dev, pm_message_t state, u32 level);
-        int     (*resume)       (struct device * dev, u32 level);
+        int     (*suspend)      (struct device * dev, pm_message_t state);
+        int     (*resume)       (struct device * dev);
 };
 
 
@@ -190,7 +177,43 @@ struct class_attribute class_attr_##_name = __ATTR(_name,_mode,_show,_store)
 extern int class_create_file(struct class *, const struct class_attribute *);
 extern void class_remove_file(struct class *, const struct class_attribute *);
 
+struct class_device_attribute {
+        struct attribute        attr;
+        ssize_t (*show)(struct class_device *, char * buf);
+        ssize_t (*store)(struct class_device *, const char * buf, size_t count);
+};
 
+#define CLASS_DEVICE_ATTR(_name,_mode,_show,_store)             \
+struct class_device_attribute class_device_attr_##_name =       \
+        __ATTR(_name,_mode,_show,_store)
+
+extern int class_device_create_file(struct class_device *,
+                                    const struct class_device_attribute *);
+
+/**
+ * struct class_device - class devices
+ * @class: pointer to the parent class for this class device.  This is required.
+ * @devt: for internal use by the driver core only.
+ * @node: for internal use by the driver core only.
+ * @kobj: for internal use by the driver core only.
+ * @devt_attr: for internal use by the driver core only.
+ * @dev: if set, a symlink to the struct device is created in the sysfs
+ * directory for this struct class device.
+ * @class_data: pointer to whatever you want to store here for this struct
+ * class_device.  Use class_get_devdata() and class_set_devdata() to get and
+ * set this pointer.
+ * @parent: pointer to a struct class_device that is the parent of this struct
+ * class_device.  If NULL, this class_device will show up at the root of the
+ * struct class in sysfs (which is probably what you want to have happen.)
+ * @release: pointer to a release function for this struct class_device.  If
+ * set, this will be called instead of the class specific release function.
+ * Only use this if you want to override the default release function, like
+ * when you are nesting class_device structures.
+ * @hotplug: pointer to a hotplug function for this struct class_device.  If
+ * set, this will be called instead of the class specific hotplug function.
+ * Only use this if you want to override the default hotplug function, like
+ * when you are nesting class_device structures.
+ */
 struct class_device {
         struct list_head        node;
 
@@ -198,9 +221,14 @@ struct class_device {
         struct class            * class;        /* required */
         dev_t                   devt;           /* dev_t, creates the sysfs "dev" */
         struct class_device_attribute *devt_attr;
+        struct class_device_attribute uevent_attr;
         struct device           * dev;          /* not necessary, but nice to have */
         void                    * class_data;   /* class-specific data */
+        struct class_device     *parent;        /* parent of this child device, if there is one */
 
+        void    (*release)(struct class_device *dev);
+        int     (*hotplug)(struct class_device *dev, char **envp,
+                           int num_envp, char *buffer, int buffer_size);
         char    class_id[BUS_ID_SIZE];  /* unique to this class */
 };
 
@@ -228,18 +256,6 @@ extern int class_device_rename(struct class_device *, char *);
 extern struct class_device * class_device_get(struct class_device *);
 extern void class_device_put(struct class_device *);
 
-struct class_device_attribute {
-        struct attribute        attr;
-        ssize_t (*show)(struct class_device *, char * buf);
-        ssize_t (*store)(struct class_device *, const char * buf, size_t count);
-};
-
-#define CLASS_DEVICE_ATTR(_name,_mode,_show,_store)             \
-struct class_device_attribute class_device_attr_##_name =       \
-        __ATTR(_name,_mode,_show,_store)
-
-extern int class_device_create_file(struct class_device *, 
-                                    const struct class_device_attribute *);
 extern void class_device_remove_file(struct class_device *, 
                                      const struct class_device_attribute *);
 extern int class_device_create_bin_file(struct class_device *,
@@ -251,8 +267,8 @@ struct class_interface {
         struct list_head        node;
         struct class            *class;
 
-        int (*add)      (struct class_device *);
-        void (*remove)  (struct class_device *);
+        int (*add)      (struct class_device *, struct class_interface *);
+        void (*remove)  (struct class_device *, struct class_interface *);
 };
 
 extern int class_interface_register(struct class_interface *);
@@ -260,12 +276,29 @@ extern void class_interface_unregister(struct class_interface *);
 
 extern struct class *class_create(struct module *owner, char *name);
 extern void class_destroy(struct class *cls);
-extern struct class_device *class_device_create(struct class *cls, dev_t devt,
-                                                struct device *device, char *fmt, ...)
-                                        __attribute__((format(printf,4,5)));
+extern struct class_device *class_device_create(struct class *cls,
+                                                struct class_device *parent,
+                                                dev_t devt,
+                                                struct device *device,
+                                                char *fmt, ...)
+                                        __attribute__((format(printf,5,6)));
 extern void class_device_destroy(struct class *cls, dev_t devt);
 
 
+/* interface for exporting device attributes */
+struct device_attribute {
+        struct attribute        attr;
+        ssize_t (*show)(struct device *dev, struct device_attribute *attr,
+                        char *buf);
+        ssize_t (*store)(struct device *dev, struct device_attribute *attr,
+                         const char *buf, size_t count);
+};
+
+#define DEVICE_ATTR(_name,_mode,_show,_store) \
+struct device_attribute dev_attr_##_name = __ATTR(_name,_mode,_show,_store)
+
+extern int device_create_file(struct device *device, struct device_attribute * entry);
+extern void device_remove_file(struct device * dev, struct device_attribute * attr);
 struct device {
         struct klist            klist_children;
         struct klist_node       knode_parent;           /* node in sibling list */
@@ -275,6 +308,7 @@ struct device {
 
         struct kobject kobj;
         char    bus_id[BUS_ID_SIZE];    /* position on parent bus */
+        struct device_attribute uevent_attr;
 
         struct semaphore        sem;    /* semaphore to synchronize calls to
                                          * its driver.
@@ -343,23 +377,6 @@ extern int  device_attach(struct device * dev);
 extern void driver_attach(struct device_driver * drv);
 
 
-/* driverfs interface for exporting device attributes */
-
-struct device_attribute {
-        struct attribute        attr;
-        ssize_t (*show)(struct device *dev, struct device_attribute *attr,
-                        char *buf);
-        ssize_t (*store)(struct device *dev, struct device_attribute *attr,
-                         const char *buf, size_t count);
-};
-
-#define DEVICE_ATTR(_name,_mode,_show,_store) \
-struct device_attribute dev_attr_##_name = __ATTR(_name,_mode,_show,_store)
-
-
-extern int device_create_file(struct device *device, struct device_attribute * entry);
-extern void device_remove_file(struct device * dev, struct device_attribute * attr);
-
 /*
  * Platform "fixup" functions - allow the platform to have their say
  * about devices and actions that the general device layer doesn't
@@ -379,32 +396,6 @@ extern struct device * get_device(struct device * dev);
 extern void put_device(struct device * dev);
 
 
-/* drivers/base/platform.c */
-
-struct platform_device {
-        const char      * name;
-        u32             id;
-        struct device   dev;
-        u32             num_resources;
-        struct resource * resource;
-};
-
-#define to_platform_device(x) container_of((x), struct platform_device, dev)
-
-extern int platform_device_register(struct platform_device *);
-extern void platform_device_unregister(struct platform_device *);
-
-extern struct bus_type platform_bus_type;
-extern struct device platform_bus;
-
-extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int);
-extern int platform_get_irq(struct platform_device *, unsigned int);
-extern struct resource *platform_get_resource_byname(struct platform_device *, unsigned int, char *);
-extern int platform_get_irq_byname(struct platform_device *, char *);
-extern int platform_add_devices(struct platform_device **, int);
-
-extern struct platform_device *platform_device_register_simple(char *, unsigned int, struct resource *, unsigned int);
-
 /* drivers/base/power.c */
 extern void device_shutdown(void);
 
diff --git a/include/linux/dmi.h b/include/linux/dmi.h
index a415f1d93e9a..05f4132622fc 100644
--- a/include/linux/dmi.h
+++ b/include/linux/dmi.h
@@ -60,7 +60,7 @@ struct dmi_device {
         void *device_data;      /* Type specific data */
 };
 
-#if defined(CONFIG_X86) && !defined(CONFIG_X86_64)
+#if defined(CONFIG_X86_32)
 
 extern int dmi_check_system(struct dmi_system_id *list);
 extern char * dmi_get_system_info(int field);
diff --git a/include/linux/elevator.h b/include/linux/elevator.h
index ea6bbc2d7407..a74c27e460ba 100644
--- a/include/linux/elevator.h
+++ b/include/linux/elevator.h
@@ -8,18 +8,17 @@ typedef void (elevator_merge_req_fn) (request_queue_t *, struct request *, struc
 
 typedef void (elevator_merged_fn) (request_queue_t *, struct request *);
 
-typedef struct request *(elevator_next_req_fn) (request_queue_t *);
+typedef int (elevator_dispatch_fn) (request_queue_t *, int);
 
-typedef void (elevator_add_req_fn) (request_queue_t *, struct request *, int);
+typedef void (elevator_add_req_fn) (request_queue_t *, struct request *);
 typedef int (elevator_queue_empty_fn) (request_queue_t *);
-typedef void (elevator_remove_req_fn) (request_queue_t *, struct request *);
-typedef void (elevator_requeue_req_fn) (request_queue_t *, struct request *);
 typedef struct request *(elevator_request_list_fn) (request_queue_t *, struct request *);
 typedef void (elevator_completed_req_fn) (request_queue_t *, struct request *);
 typedef int (elevator_may_queue_fn) (request_queue_t *, int, struct bio *);
 
-typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, struct bio *, int);
+typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, struct bio *, gfp_t);
 typedef void (elevator_put_req_fn) (request_queue_t *, struct request *);
+typedef void (elevator_activate_req_fn) (request_queue_t *, struct request *);
 typedef void (elevator_deactivate_req_fn) (request_queue_t *, struct request *);
 
 typedef int (elevator_init_fn) (request_queue_t *, elevator_t *);
@@ -31,10 +30,9 @@ struct elevator_ops
         elevator_merged_fn *elevator_merged_fn;
         elevator_merge_req_fn *elevator_merge_req_fn;
 
-        elevator_next_req_fn *elevator_next_req_fn;
+        elevator_dispatch_fn *elevator_dispatch_fn;
         elevator_add_req_fn *elevator_add_req_fn;
-        elevator_remove_req_fn *elevator_remove_req_fn;
-        elevator_requeue_req_fn *elevator_requeue_req_fn;
+        elevator_activate_req_fn *elevator_activate_req_fn;
         elevator_deactivate_req_fn *elevator_deactivate_req_fn;
 
         elevator_queue_empty_fn *elevator_queue_empty_fn;
@@ -81,15 +79,15 @@ struct elevator_queue
 /*
  * block elevator interface
  */
+extern void elv_dispatch_sort(request_queue_t *, struct request *);
 extern void elv_add_request(request_queue_t *, struct request *, int, int);
 extern void __elv_add_request(request_queue_t *, struct request *, int, int);
 extern int elv_merge(request_queue_t *, struct request **, struct bio *);
 extern void elv_merge_requests(request_queue_t *, struct request *,
                                struct request *);
 extern void elv_merged_request(request_queue_t *, struct request *);
-extern void elv_remove_request(request_queue_t *, struct request *);
+extern void elv_dequeue_request(request_queue_t *, struct request *);
 extern void elv_requeue_request(request_queue_t *, struct request *);
-extern void elv_deactivate_request(request_queue_t *, struct request *);
 extern int elv_queue_empty(request_queue_t *);
 extern struct request *elv_next_request(struct request_queue *q);
 extern struct request *elv_former_request(request_queue_t *, struct request *);
@@ -98,7 +96,7 @@ extern int elv_register_queue(request_queue_t *q);
 extern void elv_unregister_queue(request_queue_t *q);
 extern int elv_may_queue(request_queue_t *, int, struct bio *);
 extern void elv_completed_request(request_queue_t *, struct request *);
-extern int elv_set_request(request_queue_t *, struct request *, struct bio *, int);
+extern int elv_set_request(request_queue_t *, struct request *, struct bio *, gfp_t);
 extern void elv_put_request(request_queue_t *, struct request *);
 
 /*
@@ -142,4 +140,6 @@ enum {
         ELV_MQUEUE_MUST,
 };
 
+#define rq_end_sector(rq)       ((rq)->sector + (rq)->nr_sectors)
+
 #endif
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index 4522c7186bf3..cc84934f9059 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -104,6 +104,22 @@ static inline void random_ether_addr(u8 *addr)
         addr [0] &= 0xfe;       /* clear multicast bit */
         addr [0] |= 0x02;       /* set local assignment bit (IEEE802) */
 }
+
+/**
+ * compare_ether_addr - Compare two Ethernet addresses
+ * @addr1: Pointer to a six-byte array containing the Ethernet address
+ * @addr2 Pointer other six-byte array containing the Ethernet address
+ *
+ * Compare two ethernet addresses, returns 0 if equal
+ */
+static inline unsigned compare_ether_addr(const u8 *_a, const u8 *_b)
+{
+        const u16 *a = (const u16 *) _a;
+        const u16 *b = (const u16 *) _b;
+
+        BUILD_BUG_ON(ETH_ALEN != 6);
+        return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+}
 #endif  /* __KERNEL__ */
 
 #endif  /* _LINUX_ETHERDEVICE_H */
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index ed1440ea4c91..d2c390eff1b2 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -269,6 +269,8 @@ u32 ethtool_op_get_tso(struct net_device *dev);
 int ethtool_op_set_tso(struct net_device *dev, u32 data);
 int ethtool_op_get_perm_addr(struct net_device *dev, 
                              struct ethtool_perm_addr *addr, u8 *data);
+u32 ethtool_op_get_ufo(struct net_device *dev);
+int ethtool_op_set_ufo(struct net_device *dev, u32 data);
 
 /**
  * &ethtool_ops - Alter and report network device settings
@@ -298,6 +300,8 @@ int ethtool_op_get_perm_addr(struct net_device *dev,
  * set_sg: Turn scatter-gather on or off
  * get_tso: Report whether TCP segmentation offload is enabled
  * set_tso: Turn TCP segmentation offload on or off
+ * get_ufo: Report whether UDP fragmentation offload is enabled
+ * set_ufo: Turn UDP fragmentation offload on or off
  * self_test: Run specified self-tests
  * get_strings: Return a set of strings that describe the requested objects 
  * phys_id: Identify the device
@@ -364,6 +368,8 @@ struct ethtool_ops {
         int     (*get_perm_addr)(struct net_device *, struct ethtool_perm_addr *, u8 *);
         int     (*begin)(struct net_device *);
         void    (*complete)(struct net_device *);
+        u32     (*get_ufo)(struct net_device *);
+        int     (*set_ufo)(struct net_device *, u32);
 };
 
 /* CMDs currently supported */
@@ -400,6 +406,8 @@ struct ethtool_ops {
 #define ETHTOOL_GTSO            0x0000001e /* Get TSO enable (ethtool_value) */
 #define ETHTOOL_STSO            0x0000001f /* Set TSO enable (ethtool_value) */
 #define ETHTOOL_GPERMADDR       0x00000020 /* Get permanent hardware address */
+#define ETHTOOL_GUFO            0x00000021 /* Get UFO enable (ethtool_value) */
+#define ETHTOOL_SUFO            0x00000022 /* Set UFO enable (ethtool_value) */
 
 /* compatibility with older code */
 #define SPARC_ETH_GSET          ETHTOOL_GSET
diff --git a/include/linux/fs.h b/include/linux/fs.h
index e0b77c5af9a0..6d6226732c93 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -320,7 +320,7 @@ struct address_space_operations {
         /* Unfortunately this kludge is needed for FIBMAP. Don't use it */
         sector_t (*bmap)(struct address_space *, sector_t);
         int (*invalidatepage) (struct page *, unsigned long);
-        int (*releasepage) (struct page *, int);
+        int (*releasepage) (struct page *, gfp_t);
         ssize_t (*direct_IO)(int, struct kiocb *, const struct iovec *iov,
                         loff_t offset, unsigned long nr_segs);
         struct page* (*get_xip_page)(struct address_space *, sector_t,
@@ -574,7 +574,14 @@ struct file_ra_state {
 #define RA_FLAG_INCACHE 0x02    /* file is already in cache */
 
 struct file {
-        struct list_head        f_list;
+        /*
+         * fu_list becomes invalid after file_free is called and queued via
+         * fu_rcuhead for RCU freeing
+         */
+        union {
+                struct list_head        fu_list;
+                struct rcu_head         fu_rcuhead;
+        } f_u;
         struct dentry           *f_dentry;
         struct vfsmount         *f_vfsmnt;
         struct file_operations  *f_op;
@@ -598,7 +605,6 @@ struct file {
         spinlock_t              f_ep_lock;
 #endif /* #ifdef CONFIG_EPOLL */
         struct address_space    *f_mapping;
-        struct rcu_head         f_rcuhead;
 };
 extern spinlock_t files_lock;
 #define file_list_lock() spin_lock(&files_lock);
diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h
new file mode 100644
index 000000000000..bef23bbf8690
--- /dev/null
+++ b/include/linux/fs_enet_pd.h
@@ -0,0 +1,136 @@
+/*
+ * Platform information definitions for the
+ * universal Freescale Ethernet driver.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+#ifndef FS_ENET_PD_H
+#define FS_ENET_PD_H
+
+#include <linux/version.h>
+#include <asm/types.h>
+
+#define FS_ENET_NAME    "fs_enet"
+
+enum fs_id {
+        fsid_fec1,
+        fsid_fec2,
+        fsid_fcc1,
+        fsid_fcc2,
+        fsid_fcc3,
+        fsid_scc1,
+        fsid_scc2,
+        fsid_scc3,
+        fsid_scc4,
+};
+
+#define FS_MAX_INDEX    9
+
+static inline int fs_get_fec_index(enum fs_id id)
+{
+        if (id >= fsid_fec1 && id <= fsid_fec2)
+                return id - fsid_fec1;
+        return -1;
+}
+
+static inline int fs_get_fcc_index(enum fs_id id)
+{
+        if (id >= fsid_fcc1 && id <= fsid_fcc3)
+                return id - fsid_fcc1;
+        return -1;
+}
+
+static inline int fs_get_scc_index(enum fs_id id)
+{
+        if (id >= fsid_scc1 && id <= fsid_scc4)
+                return id - fsid_scc1;
+        return -1;
+}
+
+enum fs_mii_method {
+        fsmii_fixed,
+        fsmii_fec,
+        fsmii_bitbang,
+};
+
+enum fs_ioport {
+        fsiop_porta,
+        fsiop_portb,
+        fsiop_portc,
+        fsiop_portd,
+        fsiop_porte,
+};
+
+struct fs_mii_bus_info {
+        int method;             /* mii method                  */
+        int id;                 /* the id of the mii_bus       */
+        int disable_aneg;       /* if the controller needs to negothiate speed & duplex */
+        int lpa;                /* the default board-specific vallues will be applied otherwise */
+
+        union {
+                struct {
+                        int duplex;
+                        int speed;
+                } fixed;
+
+                struct {
+                        /* nothing */
+                } fec;
+                
+                struct {
+                        /* nothing */
+                } scc;
+
+                struct {
+                        int mdio_port;  /* port & bit for MDIO */
+                        int mdio_bit;
+                        int mdc_port;   /* port & bit for MDC  */
+                        int mdc_bit;
+                        int delay;      /* delay in us         */
+                } bitbang;
+        } i;
+};
+
+struct fs_platform_info {
+        
+        void(*init_ioports)(void);
+        /* device specific information */
+        int fs_no;              /* controller index            */
+
+        u32 cp_page;            /* CPM page */
+        u32 cp_block;           /* CPM sblock */
+        
+        u32 clk_trx;            /* some stuff for pins & mux configuration*/
+        u32 clk_route;
+        u32 clk_mask;
+        
+        u32 mem_offset;
+        u32 dpram_offset;
+        u32 fcc_regs_c;
+        
+        u32 device_flags;
+
+        int phy_addr;           /* the phy address (-1 no phy) */
+        int phy_irq;            /* the phy irq (if it exists)  */
+
+        const struct fs_mii_bus_info *bus_info;
+
+        int rx_ring, tx_ring;   /* number of buffers on rx     */
+        __u8 macaddr[6];        /* mac address                 */
+        int rx_copybreak;       /* limit we copy small frames  */
+        int use_napi;           /* use NAPI                    */
+        int napi_weight;        /* NAPI weight                 */
+
+        int use_rmii;           /* use RMII mode               */
+};
+
+#endif
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 70f54af87b9f..114d5d59f695 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -47,16 +47,21 @@
 struct gianfar_platform_data {
         /* device specific information */
         u32 device_flags;
-        u32 phy_reg_addr;
 
         /* board specific information */
         u32 board_flags;
-        u32 phy_flags;
-        u32 phyid;
-        u32 interruptPHY;
+        const char *bus_id;
         u8 mac_addr[6];
 };
 
+struct gianfar_mdio_data {
+        /* device specific information */
+        u32 paddr;
+
+        /* board specific information */
+        int irq[32];
+};
+
 /* Flags related to gianfar device features */
 #define FSL_GIANFAR_DEV_HAS_GIGABIT             0x00000001
 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
diff --git a/include/linux/fuse.h b/include/linux/fuse.h
index acbeb96a3353..f98854c2abd7 100644
--- a/include/linux/fuse.h
+++ b/include/linux/fuse.h
@@ -61,7 +61,6 @@ struct fuse_kstatfs {
 #define FATTR_SIZE      (1 << 3)
 #define FATTR_ATIME     (1 << 4)
 #define FATTR_MTIME     (1 << 5)
-#define FATTR_CTIME     (1 << 6)
 
 /**
  * Flags returned by the OPEN request
diff --git a/include/linux/gameport.h b/include/linux/gameport.h
index cd623eccdbea..2401dea2b867 100644
--- a/include/linux/gameport.h
+++ b/include/linux/gameport.h
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <linux/list.h>
 #include <linux/device.h>
+#include <linux/timer.h>
 
 struct gameport {
 
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 01796c41c951..eabdb5cce357 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -119,7 +119,7 @@ struct gendisk {
         int policy;
 
         atomic_t sync_io;               /* RAID */
-        unsigned long stamp, stamp_idle;
+        unsigned long stamp;
         int in_flight;
 #ifdef  CONFIG_SMP
         struct disk_stats *dkstats;
@@ -132,6 +132,7 @@ struct gendisk {
 struct disk_attribute {
         struct attribute attr;
         ssize_t (*show)(struct gendisk *, char *);
+        ssize_t (*store)(struct gendisk *, const char *, size_t);
 };
 
 /* 
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index 3010e172394d..c3779432a723 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -12,8 +12,8 @@ struct vm_area_struct;
  * GFP bitmasks..
  */
 /* Zone modifiers in GFP_ZONEMASK (see linux/mmzone.h - low two bits) */
-#define __GFP_DMA       0x01u
-#define __GFP_HIGHMEM   0x02u
+#define __GFP_DMA       ((__force gfp_t)0x01u)
+#define __GFP_HIGHMEM   ((__force gfp_t)0x02u)
 
 /*
  * Action modifiers - doesn't change the zoning
@@ -26,24 +26,24 @@ struct vm_area_struct;
  *
  * __GFP_NORETRY: The VM implementation must not retry indefinitely.
  */
-#define __GFP_WAIT      0x10u   /* Can wait and reschedule? */
-#define __GFP_HIGH      0x20u   /* Should access emergency pools? */
-#define __GFP_IO        0x40u   /* Can start physical IO? */
-#define __GFP_FS        0x80u   /* Can call down to low-level FS? */
-#define __GFP_COLD      0x100u  /* Cache-cold page required */
-#define __GFP_NOWARN    0x200u  /* Suppress page allocation failure warning */
-#define __GFP_REPEAT    0x400u  /* Retry the allocation.  Might fail */
-#define __GFP_NOFAIL    0x800u  /* Retry for ever.  Cannot fail */
-#define __GFP_NORETRY   0x1000u /* Do not retry.  Might fail */
-#define __GFP_NO_GROW   0x2000u /* Slab internal usage */
-#define __GFP_COMP      0x4000u /* Add compound page metadata */
-#define __GFP_ZERO      0x8000u /* Return zeroed page on success */
-#define __GFP_NOMEMALLOC 0x10000u /* Don't use emergency reserves */
-#define __GFP_NORECLAIM  0x20000u /* No realy zone reclaim during allocation */
-#define __GFP_HARDWALL   0x40000u /* Enforce hardwall cpuset memory allocs */
+#define __GFP_WAIT      ((__force gfp_t)0x10u)  /* Can wait and reschedule? */
+#define __GFP_HIGH      ((__force gfp_t)0x20u)  /* Should access emergency pools? */
+#define __GFP_IO        ((__force gfp_t)0x40u)  /* Can start physical IO? */
+#define __GFP_FS        ((__force gfp_t)0x80u)  /* Can call down to low-level FS? */
+#define __GFP_COLD      ((__force gfp_t)0x100u) /* Cache-cold page required */
+#define __GFP_NOWARN    ((__force gfp_t)0x200u) /* Suppress page allocation failure warning */
+#define __GFP_REPEAT    ((__force gfp_t)0x400u) /* Retry the allocation.  Might fail */
+#define __GFP_NOFAIL    ((__force gfp_t)0x800u) /* Retry for ever.  Cannot fail */
+#define __GFP_NORETRY   ((__force gfp_t)0x1000u)/* Do not retry.  Might fail */
+#define __GFP_NO_GROW   ((__force gfp_t)0x2000u)/* Slab internal usage */
+#define __GFP_COMP      ((__force gfp_t)0x4000u)/* Add compound page metadata */
+#define __GFP_ZERO      ((__force gfp_t)0x8000u)/* Return zeroed page on success */
+#define __GFP_NOMEMALLOC ((__force gfp_t)0x10000u) /* Don't use emergency reserves */
+#define __GFP_NORECLAIM  ((__force gfp_t)0x20000u) /* No realy zone reclaim during allocation */
+#define __GFP_HARDWALL   ((__force gfp_t)0x40000u) /* Enforce hardwall cpuset memory allocs */
 
 #define __GFP_BITS_SHIFT 20     /* Room for 20 __GFP_FOO bits */
-#define __GFP_BITS_MASK ((1 << __GFP_BITS_SHIFT) - 1)
+#define __GFP_BITS_MASK ((__force gfp_t)((1 << __GFP_BITS_SHIFT) - 1))
 
 /* if you forget to add the bitmask here kernel will crash, period */
 #define GFP_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_FS| \
@@ -64,6 +64,7 @@ struct vm_area_struct;
 
 #define GFP_DMA         __GFP_DMA
 
+#define gfp_zone(mask) ((__force int)((mask) & (__force gfp_t)GFP_ZONEMASK))
 
 /*
  * There is only one page-allocator function, and two main namespaces to
@@ -94,7 +95,7 @@ static inline struct page *alloc_pages_node(int nid, gfp_t gfp_mask,
                 return NULL;
 
         return __alloc_pages(gfp_mask, order,
-                NODE_DATA(nid)->node_zonelists + (gfp_mask & GFP_ZONEMASK));
+                NODE_DATA(nid)->node_zonelists + gfp_zone(gfp_mask));
 }
 
 #ifdef CONFIG_NUMA
diff --git a/include/linux/hil.h b/include/linux/hil.h
new file mode 100644
index 000000000000..13352d7d0caf
--- /dev/null
+++ b/include/linux/hil.h
@@ -0,0 +1,483 @@
+#ifndef _HIL_H_
+#define _HIL_H_
+
+/*
+ * Hewlett Packard Human Interface Loop (HP-HIL) Protocol -- header.
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ * A note of thanks to HP for providing and shipping reference materials
+ * free of charge to help in the development of HIL support for Linux.
+ *
+ */
+
+#include <asm/types.h>
+
+/* Physical constants relevant to raw loop/device timing. 
+ */ 
+
+#define HIL_CLOCK               8MHZ
+#define HIL_EK1_CLOCK           30HZ
+#define HIL_EK2_CLOCK           60HZ
+
+#define HIL_TIMEOUT_DEV         5       /* ms */
+#define HIL_TIMEOUT_DEVS        10      /* ms */
+#define HIL_TIMEOUT_NORESP      10      /* ms */
+#define HIL_TIMEOUT_DEVS_DATA   16      /* ms */
+#define HIL_TIMEOUT_SELFTEST    200     /* ms */
+
+
+/* Actual wire line coding.  These will only be useful if someone is 
+ * implementing a software MLC to run HIL devices on a non-parisc machine.
+ */
+
+#define HIL_WIRE_PACKET_LEN     15
+enum hil_wire_bitpos {
+        HIL_WIRE_START          = 0,
+        HIL_WIRE_ADDR2,
+        HIL_WIRE_ADDR1,
+        HIL_WIRE_ADDR0,
+        HIL_WIRE_COMMAND,
+        HIL_WIRE_DATA7,
+        HIL_WIRE_DATA6,
+        HIL_WIRE_DATA5,
+        HIL_WIRE_DATA4,
+        HIL_WIRE_DATA3,
+        HIL_WIRE_DATA2,
+        HIL_WIRE_DATA1,
+        HIL_WIRE_DATA0,
+        HIL_WIRE_PARITY,
+        HIL_WIRE_STOP
+};
+
+/* HP documentation uses these bit positions to refer to commands;
+ * we will call these "packets".
+ */
+enum hil_pkt_bitpos {
+        HIL_PKT_CMD             = 0x00000800,
+        HIL_PKT_ADDR2           = 0x00000400,
+        HIL_PKT_ADDR1           = 0x00000200,
+        HIL_PKT_ADDR0           = 0x00000100,
+        HIL_PKT_ADDR_MASK       = 0x00000700,
+        HIL_PKT_ADDR_SHIFT      = 8,
+        HIL_PKT_DATA7           = 0x00000080,
+        HIL_PKT_DATA6           = 0x00000040,
+        HIL_PKT_DATA5           = 0x00000020,
+        HIL_PKT_DATA4           = 0x00000010,
+        HIL_PKT_DATA3           = 0x00000008,
+        HIL_PKT_DATA2           = 0x00000004,
+        HIL_PKT_DATA1           = 0x00000002,
+        HIL_PKT_DATA0           = 0x00000001,
+        HIL_PKT_DATA_MASK       = 0x000000FF,
+        HIL_PKT_DATA_SHIFT      = 0
+};
+
+/* The HIL MLC also has several error/status/control bits.  We extend the 
+ * "packet" to include these when direct access to the MLC is available,
+ * or emulate them in cases where they are not available. 
+ *
+ * This way the device driver knows that the underlying MLC driver
+ * has had to deal with loop errors.
+ */
+enum hil_error_bitpos {
+        HIL_ERR_OB      = 0x00000800, /* MLC is busy sending an auto-poll, 
+                                         or we have filled up the output 
+                                         buffer and must wait. */
+        HIL_ERR_INT     = 0x00010000, /* A normal interrupt has occurred. */
+        HIL_ERR_NMI     = 0x00020000, /* An NMI has occurred. */
+        HIL_ERR_LERR    = 0x00040000, /* A poll didn't come back. */
+        HIL_ERR_PERR    = 0x01000000, /* There was a Parity Error. */
+        HIL_ERR_FERR    = 0x02000000, /* There was a Framing Error. */
+        HIL_ERR_FOF     = 0x04000000  /* Input FIFO Overflowed. */
+};
+
+enum hil_control_bitpos {
+        HIL_CTRL_TEST   = 0x00010000,
+        HIL_CTRL_IPF    = 0x00040000,
+        HIL_CTRL_APE    = 0x02000000
+};
+
+/* Bits 30,31 are unused, we use them to control write behavior. */
+#define HIL_DO_ALTER_CTRL  0x40000000 /* Write MSW of packet to control 
+                                          before writing LSW to loop */
+#define HIL_CTRL_ONLY      0xc0000000 /* *Only* alter the control registers */
+
+/* This gives us a 32-bit "packet" 
+ */
+typedef u32 hil_packet;
+
+
+/* HIL Loop commands 
+ */
+enum hil_command {
+        HIL_CMD_IFC     = 0x00, /* Interface Clear */
+        HIL_CMD_EPT     = 0x01, /* Enter Pass-Thru Mode */
+        HIL_CMD_ELB     = 0x02, /* Enter Loop-Back Mode */
+        HIL_CMD_IDD     = 0x03, /* Identify and Describe */
+        HIL_CMD_DSR     = 0x04, /* Device Soft Reset */
+        HIL_CMD_PST     = 0x05, /* Perform Self Test */
+        HIL_CMD_RRG     = 0x06, /* Read Register */
+        HIL_CMD_WRG     = 0x07, /* Write Register */
+        HIL_CMD_ACF     = 0x08, /* Auto Configure */
+        HIL_CMDID_ACF   = 0x07, /* Auto Configure bits with incremented ID */
+        HIL_CMD_POL     = 0x10, /* Poll */
+        HIL_CMDCT_POL   = 0x0f, /* Poll command bits with item count  */
+        HIL_CMD_RPL     = 0x20, /* RePoll */
+        HIL_CMDCT_RPL   = 0x0f, /* RePoll command bits with item count */
+        HIL_CMD_RNM     = 0x30, /* Report Name */
+        HIL_CMD_RST     = 0x31, /* Report Status */
+        HIL_CMD_EXD     = 0x32, /* Extended Describe */
+        HIL_CMD_RSC     = 0x33, /* Report Security Code */
+
+        /* 0x34 to 0x3c reserved for future use  */
+
+        HIL_CMD_DKA     = 0x3d, /* Disable Keyswitch Autorepeat */
+        HIL_CMD_EK1     = 0x3e, /* Enable Keyswitch Autorepeat 1 */
+        HIL_CMD_EK2     = 0x3f, /* Enable Keyswitch Autorepeat 2 */
+        HIL_CMD_PR1     = 0x40, /* Prompt1 */  
+        HIL_CMD_PR2     = 0x41, /* Prompt2 */
+        HIL_CMD_PR3     = 0x42, /* Prompt3 */
+        HIL_CMD_PR4     = 0x43, /* Prompt4 */
+        HIL_CMD_PR5     = 0x44, /* Prompt5 */
+        HIL_CMD_PR6     = 0x45, /* Prompt6 */
+        HIL_CMD_PR7     = 0x46, /* Prompt7 */
+        HIL_CMD_PRM     = 0x47, /* Prompt (General Purpose) */
+        HIL_CMD_AK1     = 0x48, /* Acknowlege1 */  
+        HIL_CMD_AK2     = 0x49, /* Acknowlege2 */
+        HIL_CMD_AK3     = 0x4a, /* Acknowlege3 */
+        HIL_CMD_AK4     = 0x4b, /* Acknowlege4 */
+        HIL_CMD_AK5     = 0x4c, /* Acknowlege5 */
+        HIL_CMD_AK6     = 0x4d, /* Acknowlege6 */
+        HIL_CMD_AK7     = 0x4e, /* Acknowlege7 */
+        HIL_CMD_ACK     = 0x4f, /* Acknowlege (General Purpose) */
+
+        /* 0x50 to 0x78 reserved for future use  */
+        /* 0x80 to 0xEF device-specific commands */
+        /* 0xf0 to 0xf9 reserved for future use  */
+
+        HIL_CMD_RIO     = 0xfa, /* Register I/O Error */
+        HIL_CMD_SHR     = 0xfb, /* System Hard Reset */
+        HIL_CMD_TER     = 0xfc, /* Transmission Error */
+        HIL_CMD_CAE     = 0xfd, /* Configuration Address Error */
+        HIL_CMD_DHR     = 0xfe, /* Device Hard Reset */
+
+        /* 0xff is prohibited from use. */
+};
+
+
+/* 
+ * Response "records" to HIL commands
+ */
+
+/* Device ID byte 
+ */
+#define HIL_IDD_DID_TYPE_MASK           0xe0    /* Primary type bits */
+#define HIL_IDD_DID_TYPE_KB_INTEGRAL    0xa0    /* Integral keyboard */
+#define HIL_IDD_DID_TYPE_KB_ITF         0xc0    /* ITD keyboard */
+#define HIL_IDD_DID_TYPE_KB_RSVD        0xe0    /* Reserved keyboard type */
+#define HIL_IDD_DID_TYPE_KB_LANG_MASK   0x1f    /* Keyboard locale bits */
+#define HIL_IDD_DID_KBLANG_USE_ESD      0x00    /* Use ESD Locale instead */
+#define HIL_IDD_DID_TYPE_ABS            0x80    /* Absolute Positioners */
+#define HIL_IDD_DID_ABS_RSVD1_MASK      0xf8    /* Reserved */
+#define HIL_IDD_DID_ABS_RSVD1           0x98
+#define HIL_IDD_DID_ABS_TABLET_MASK     0xf8    /* Tablets and digitizers */
+#define HIL_IDD_DID_ABS_TABLET          0x90
+#define HIL_IDD_DID_ABS_TSCREEN_MASK    0xfc    /* Touch screens */
+#define HIL_IDD_DID_ABS_TSCREEN         0x8c
+#define HIL_IDD_DID_ABS_RSVD2_MASK      0xfc    /* Reserved */
+#define HIL_IDD_DID_ABS_RSVD2           0x88
+#define HIL_IDD_DID_ABS_RSVD3_MASK      0xfc    /* Reserved */
+#define HIL_IDD_DID_ABS_RSVD3           0x80
+#define HIL_IDD_DID_TYPE_REL            0x60    /* Relative Positioners */
+#define HIL_IDD_DID_REL_RSVD1_MASK      0xf0    /* Reserved */
+#define HIL_IDD_DID_REL_RSVD1           0x70
+#define HIL_IDD_DID_REL_RSVD2_MASK      0xfc    /* Reserved */
+#define HIL_IDD_DID_REL_RSVD2           0x6c
+#define HIL_IDD_DID_REL_MOUSE_MASK      0xfc    /* Mouse */
+#define HIL_IDD_DID_REL_MOUSE           0x68
+#define HIL_IDD_DID_REL_QUAD_MASK       0xf8    /* Other Quadrature Devices */
+#define HIL_IDD_DID_REL_QUAD            0x60
+#define HIL_IDD_DID_TYPE_CHAR           0x40    /* Character Entry */
+#define HIL_IDD_DID_CHAR_BARCODE_MASK   0xfc    /* Barcode Reader */
+#define HIL_IDD_DID_CHAR_BARCODE        0x5c
+#define HIL_IDD_DID_CHAR_RSVD1_MASK     0xfc    /* Reserved */
+#define HIL_IDD_DID_CHAR_RSVD1          0x58
+#define HIL_IDD_DID_CHAR_RSVD2_MASK     0xf8    /* Reserved */
+#define HIL_IDD_DID_CHAR_RSVD2          0x50
+#define HIL_IDD_DID_CHAR_RSVD3_MASK     0xf0    /* Reserved */
+#define HIL_IDD_DID_CHAR_RSVD3          0x40
+#define HIL_IDD_DID_TYPE_OTHER          0x20    /* Miscellaneous */
+#define HIL_IDD_DID_OTHER_RSVD1_MASK    0xf0    /* Reserved */
+#define HIL_IDD_DID_OTHER_RSVD1         0x30
+#define HIL_IDD_DID_OTHER_BARCODE_MASK  0xfc    /* Tone Generator */
+#define HIL_IDD_DID_OTHER_BARCODE       0x2c
+#define HIL_IDD_DID_OTHER_RSVD2_MASK    0xfc    /* Reserved */
+#define HIL_IDD_DID_OTHER_RSVD2         0x28
+#define HIL_IDD_DID_OTHER_RSVD3_MASK    0xf8    /* Reserved */
+#define HIL_IDD_DID_OTHER_RSVD3         0x20
+#define HIL_IDD_DID_TYPE_KEYPAD         0x00    /* Vectra Keyboard */
+
+/* IDD record header 
+ */
+#define HIL_IDD_HEADER_AXSET_MASK       0x03    /* Number of axis in a set */
+#define HIL_IDD_HEADER_RSC              0x04    /* Supports RSC command */
+#define HIL_IDD_HEADER_EXD              0x08    /* Supports EXD command */
+#define HIL_IDD_HEADER_IOD              0x10    /* IOD byte to follow */
+#define HIL_IDD_HEADER_16BIT            0x20    /* 16 (vs. 8) bit resolution */
+#define HIL_IDD_HEADER_ABS              0x40    /* Reports Absolute Position */
+#define HIL_IDD_HEADER_2X_AXIS          0x80    /* Two sets of 1-3 axis */
+
+/* I/O Descriptor
+ */
+#define HIL_IDD_IOD_NBUTTON_MASK        0x07    /* Number of buttons */
+#define HIL_IDD_IOD_PROXIMITY           0x08    /* Proximity in/out events */
+#define HIL_IDD_IOD_PROMPT_MASK         0x70    /* Number of prompts/acks */
+#define HIL_IDD_IOD_PROMPT_SHIFT        4
+#define HIL_IDD_IOD_PROMPT              0x80    /* Generic prompt/ack */
+
+#define HIL_IDD_NUM_AXES_PER_SET(header_packet) \
+((header_packet) & HIL_IDD_HEADER_AXSET_MASK)
+
+#define HIL_IDD_NUM_AXSETS(header_packet) \
+(2 - !((header_packet) & HIL_IDD_HEADER_2X_AXIS))
+
+#define HIL_IDD_LEN(header_packet) \
+((4 - !(header_packet & HIL_IDD_HEADER_IOD) -                   \
+  2 * !(HIL_IDD_NUM_AXES_PER_SET(header_packet))) +             \
+  2 * HIL_IDD_NUM_AXES_PER_SET(header_packet) *                 \
+ !!((header_packet) & HIL_IDD_HEADER_ABS))
+
+/* The following HIL_IDD_* macros assume you have an array of 
+ * packets and/or unpacked 8-bit data in the order that they 
+ * were received.
+ */
+
+#define HIL_IDD_AXIS_COUNTS_PER_M(header_ptr) \
+(!(HIL_IDD_NUM_AXSETS(*(header_ptr))) ? -1 :                    \
+(((*(header_ptr + 1) & HIL_PKT_DATA_MASK) +                     \
+  ((*(header_ptr + 2) & HIL_PKT_DATA_MASK)) << 8)               \
+* ((*(header_ptr) & HIL_IDD_HEADER_16BIT) ? 100 : 1)))
+
+#define HIL_IDD_AXIS_MAX(header_ptr, __axnum) \
+((!(*(header_ptr) & HIL_IDD_HEADER_ABS) ||                      \
+  (HIL_IDD_NUM_AXES_PER_SET(*(header_ptr)) <= __axnum)) ? 0 :   \
+ ((HIL_PKT_DATA_MASK & *((header_ptr) + 3 + 2 * __axnum)) +     \
+  ((HIL_PKT_DATA_MASK & *((header_ptr) + 4 + 2 * __axnum)) << 8)))
+
+#define HIL_IDD_IOD(header_ptr) \
+(*(header_ptr + HIL_IDD_LEN((*header_ptr)) - 1))
+
+#define HIL_IDD_HAS_GEN_PROMPT(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) &&                          \
+ (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROMPT))
+
+#define HIL_IDD_HAS_GEN_PROXIMITY(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) &&                          \
+ (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROXIMITY))
+
+#define HIL_IDD_NUM_BUTTONS(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) ?                           \
+ (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NBUTTON_MASK) : 0)
+
+#define HIL_IDD_NUM_PROMPTS(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) ?                           \
+ ((HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NPROMPT_MASK)          \
+  >> HIL_IDD_IOD_PROMPT_SHIFT) : 0)
+
+/* The response to HIL EXD commands -- the "extended describe record" */
+#define HIL_EXD_HEADER_WRG              0x03    /* Supports type2 WRG */
+#define HIL_EXD_HEADER_WRG_TYPE1        0x01    /* Supports type1 WRG */
+#define HIL_EXD_HEADER_WRG_TYPE2        0x02    /* Supports type2 WRG */
+#define HIL_EXD_HEADER_RRG              0x04    /* Supports RRG command */
+#define HIL_EXD_HEADER_RNM              0x10    /* Supports RNM command */
+#define HIL_EXD_HEADER_RST              0x20    /* Supports RST command */
+#define HIL_EXD_HEADER_LOCALE           0x40    /* Contains locale code */
+
+#define HIL_EXD_NUM_RRG(header_ptr) \
+((*header_ptr & HIL_EXD_HEADER_RRG) ? \
+ (*(header_ptr + 1) & HIL_PKT_DATA_MASK) : 0)
+
+#define HIL_EXD_NUM_WWG(header_ptr) \
+((*header_ptr & HIL_EXD_HEADER_WRG) ?                           \
+ (*(header_ptr + 2 - !(*header_ptr & HIL_EXD_HEADER_RRG)) &     \
+    HIL_PKT_DATA_MASK) : 0)
+
+#define HIL_EXD_LEN(header_ptr) \
+(!!(*header_ptr & HIL_EXD_HEADER_RRG) +                         \
+ !!(*header_ptr & HIL_EXD_HEADER_WRG) +                         \
+ !!(*header_ptr & HIL_EXD_HEADER_LOCALE) +                      \
+ 2 * !!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) + 1)
+
+#define HIL_EXD_LOCALE(header_ptr) \
+(!(*header_ptr & HIL_EXD_HEADER_LOCALE) ? -1 :                  \
+ (*(header_ptr + HIL_EXD_LEN(header_ptr) - 1) & HIL_PKT_DATA_MASK))
+
+#define HIL_EXD_WRG_TYPE2_LEN(header_ptr) \
+(!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) ? -1 :                       \
+ (*(header_ptr + HIL_EXD_LEN(header_ptr) - 2 -                          \
+    !!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) +     \
+ ((*(header_ptr + HIL_EXD_LEN(header_ptr) - 1 -                         \
+     !!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) << 8))
+
+/* Device locale codes. */ 
+
+/* Last defined locale code.  Everything above this is "Reserved",
+   and note that this same table applies to the Device ID Byte where 
+   keyboards may have a nationality code which is only 5 bits. */
+#define HIL_LOCALE_MAX 0x1f
+
+/* Map to hopefully useful strings.  I was trying to make these look
+   like locale.aliases strings do; maybe that isn't the right table to
+   emulate.  In either case, I didn't have much to work on. */
+#define HIL_LOCALE_MAP \
+"",                     /* 0x00 Reserved */             \
+"",                     /* 0x01 Reserved */             \
+"",                     /* 0x02 Reserved */             \
+"swiss.french",         /* 0x03 Swiss/French */         \
+"portuguese",           /* 0x04 Portuguese */           \
+"arabic",               /* 0x05 Arabic */               \
+"hebrew",               /* 0x06 Hebrew */               \
+"english.canadian",     /* 0x07 Canadian English */     \
+"turkish",              /* 0x08 Turkish */              \
+"greek",                /* 0x09 Greek */                \
+"thai",                 /* 0x0a Thai (Thailand) */      \
+"italian",              /* 0x0b Italian */              \
+"korean",               /* 0x0c Hangul (Korea) */       \
+"dutch",                /* 0x0d Dutch */                \
+"swedish",              /* 0x0e Swedish */              \
+"german",               /* 0x0f German */               \
+"chinese",              /* 0x10 Chinese-PRC */          \
+"chinese",              /* 0x11 Chinese-ROC */          \
+"swiss.french",         /* 0x12 Swiss/French II */      \
+"spanish",              /* 0x13 Spanish */              \
+"swiss.german",         /* 0x14 Swiss/German II */      \
+"flemish",              /* 0x15 Belgian (Flemish) */    \
+"finnish",              /* 0x16 Finnish */              \
+"english.uk",           /* 0x17 United Kingdom */       \
+"french.canadian",      /* 0x18 French/Canadian */      \
+"swiss.german",         /* 0x19 Swiss/German */         \
+"norwegian",            /* 0x1a Norwegian */            \
+"french",               /* 0x1b French */               \
+"danish",               /* 0x1c Danish */               \
+"japanese",             /* 0x1d Katakana */             \
+"spanish",              /* 0x1e Latin American/Spanish*/\
+"english.us"            /* 0x1f United States */        \
+
+
+/* HIL keycodes */
+#define HIL_KEYCODES_SET1_TBLSIZE 128
+#define HIL_KEYCODES_SET1       \
+   KEY_5,               KEY_RESERVED,   KEY_RIGHTALT,   KEY_LEFTALT,    \
+   KEY_RIGHTSHIFT,      KEY_LEFTSHIFT,  KEY_LEFTCTRL,   KEY_SYSRQ,      \
+   KEY_KP4,             KEY_KP8,        KEY_KP5,        KEY_KP9,        \
+   KEY_KP6,             KEY_KP7,        KEY_KPCOMMA,    KEY_KPENTER,    \
+   KEY_KP1,             KEY_KPSLASH,    KEY_KP2,        KEY_KPPLUS,     \
+   KEY_KP3,             KEY_KPASTERISK, KEY_KP0,        KEY_KPMINUS,    \
+   KEY_B,               KEY_V,          KEY_C,          KEY_X,          \
+   KEY_Z,               KEY_RESERVED,   KEY_RESERVED,   KEY_ESC,        \
+   KEY_6,               KEY_F10,        KEY_3,          KEY_F11,        \
+   KEY_KPDOT,           KEY_F9,         KEY_TAB /*KP*/, KEY_F12,        \
+   KEY_H,               KEY_G,          KEY_F,          KEY_D,          \
+   KEY_S,               KEY_A,          KEY_RESERVED,   KEY_CAPSLOCK,   \
+   KEY_U,               KEY_Y,          KEY_T,          KEY_R,          \
+   KEY_E,               KEY_W,          KEY_Q,          KEY_TAB,        \
+   KEY_7,               KEY_6,          KEY_5,          KEY_4,          \
+   KEY_3,               KEY_2,          KEY_1,          KEY_GRAVE,      \
+   KEY_F13,             KEY_F14,        KEY_F15,        KEY_F16,        \
+   KEY_F17,             KEY_F18,        KEY_F19,        KEY_F20,        \
+   KEY_MENU,            KEY_F4,         KEY_F3,         KEY_F2,         \
+   KEY_F1,              KEY_VOLUMEUP,   KEY_STOP,       KEY_SENDFILE,   \
+   KEY_SYSRQ,           KEY_F5,         KEY_F6,         KEY_F7,         \
+   KEY_F8,              KEY_VOLUMEDOWN, KEY_DEL_EOL,    KEY_DEL_EOS,    \
+   KEY_8,               KEY_9,          KEY_0,          KEY_MINUS,      \
+   KEY_EQUAL,           KEY_BACKSPACE,  KEY_INS_LINE,   KEY_DEL_LINE,   \
+   KEY_I,               KEY_O,          KEY_P,          KEY_LEFTBRACE,  \
+   KEY_RIGHTBRACE,      KEY_BACKSLASH,  KEY_INSERT,     KEY_DELETE,     \
+   KEY_J,               KEY_K,          KEY_L,          KEY_SEMICOLON,  \
+   KEY_APOSTROPHE,      KEY_ENTER,      KEY_HOME,       KEY_PAGEUP,     \
+   KEY_M,               KEY_COMMA,      KEY_DOT,        KEY_SLASH,      \
+   KEY_BACKSLASH,       KEY_SELECT,     KEY_102ND,      KEY_PAGEDOWN,   \
+   KEY_N,               KEY_SPACE,      KEY_NEXT,       KEY_RESERVED,   \
+   KEY_LEFT,            KEY_DOWN,       KEY_UP,         KEY_RIGHT
+
+
+#define HIL_KEYCODES_SET3_TBLSIZE 128
+#define HIL_KEYCODES_SET3       \
+  KEY_RESERVED, KEY_ESC,        KEY_1,          KEY_2,                  \
+  KEY_3,        KEY_4,          KEY_5,          KEY_6,                  \
+  KEY_7,        KEY_8,          KEY_9,          KEY_0,                  \
+  KEY_MINUS,    KEY_EQUAL,      KEY_BACKSPACE,  KEY_TAB,                \
+  KEY_Q,        KEY_W,          KEY_E,          KEY_R,                  \
+  KEY_T,        KEY_Y,          KEY_U,          KEY_I,                  \
+  KEY_O,        KEY_P,          KEY_LEFTBRACE,  KEY_RIGHTBRACE,         \
+  KEY_ENTER,    KEY_LEFTCTRL,   KEY_A,          KEY_S,                  \
+  KEY_D,        KEY_F,          KEY_G,          KEY_H,                  \
+  KEY_J,        KEY_K,          KEY_L,          KEY_SEMICOLON,          \
+  KEY_APOSTROPHE,KEY_GRAVE,     KEY_LEFTSHIFT,  KEY_BACKSLASH,          \
+  KEY_Z,        KEY_X,          KEY_C,          KEY_V,                  \
+  KEY_B,        KEY_N,          KEY_M,          KEY_COMMA,              \
+  KEY_DOT,      KEY_SLASH,      KEY_RIGHTSHIFT, KEY_KPASTERISK,         \
+  KEY_LEFTALT,  KEY_SPACE,      KEY_CAPSLOCK,   KEY_F1,                 \
+  KEY_F2,       KEY_F3,         KEY_F4,         KEY_F5,                 \
+  KEY_F6,       KEY_F7,         KEY_F8,         KEY_F9,                 \
+  KEY_F10,      KEY_NUMLOCK,    KEY_SCROLLLOCK, KEY_KP7,                \
+  KEY_KP8,      KEY_KP9,        KEY_KPMINUS,    KEY_KP4,                \
+  KEY_KP5,      KEY_KP6,        KEY_KPPLUS,     KEY_KP1,                \
+  KEY_KP2,      KEY_KP3,        KEY_KP0,        KEY_KPDOT,              \
+  KEY_SYSRQ,    KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_UP,       KEY_LEFT,       KEY_DOWN,       KEY_RIGHT,              \
+  KEY_HOME,     KEY_PAGEUP,     KEY_END,        KEY_PAGEDOWN,           \
+  KEY_INSERT,   KEY_DELETE,     KEY_102ND,      KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_F1,       KEY_F2,         KEY_F3,         KEY_F4,                 \
+  KEY_F5,       KEY_F6,         KEY_F7,         KEY_F8,                 \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED
+
+
+/* Response to POL command, the "poll record header" */
+
+#define HIL_POL_NUM_AXES_MASK   0x03    /* Number of axis reported */
+#define HIL_POL_CTS             0x04    /* Device ready to receive data */
+#define HIL_POL_STATUS_PENDING  0x08    /* Device has status to report */
+#define HIL_POL_CHARTYPE_MASK   0x70    /* Type of character data to follow */
+#define HIL_POL_CHARTYPE_NONE   0x00    /* No character data to follow */
+#define HIL_POL_CHARTYPE_RSVD1  0x10    /* Reserved Set 1 */
+#define HIL_POL_CHARTYPE_ASCII  0x20    /* U.S. ASCII */
+#define HIL_POL_CHARTYPE_BINARY 0x30    /* Binary data */
+#define HIL_POL_CHARTYPE_SET1   0x40    /* Keycode Set 1 */
+#define HIL_POL_CHARTYPE_RSVD2  0x50    /* Reserved Set 2 */
+#define HIL_POL_CHARTYPE_SET2   0x60    /* Keycode Set 2 */
+#define HIL_POL_CHARTYPE_SET3   0x70    /* Keycode Set 3 */
+#define HIL_POL_AXIS_ALT        0x80    /* Data is from axis set 2 */
+
+
+#endif /* _HIL_H_ */
diff --git a/include/linux/hil_mlc.h b/include/linux/hil_mlc.h
new file mode 100644
index 000000000000..8df29ca48a13
--- /dev/null
+++ b/include/linux/hil_mlc.h
@@ -0,0 +1,168 @@
+/*
+ * HP Human Interface Loop Master Link Controller driver.
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ */
+
+#include <linux/hil.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <asm/semaphore.h>
+#include <linux/serio.h>
+#include <linux/list.h>
+
+typedef struct hil_mlc hil_mlc;
+
+/* The HIL has a complicated state engine.
+ * We define the structure of nodes in the state engine here.
+ */
+enum hilse_act {
+        /* HILSE_OUT prepares to receive input if the next node
+         * is an IN or EXPECT, and then sends the given packet.
+         */
+        HILSE_OUT = 0,
+
+        /* HILSE_CTS checks if the loop is busy. */
+        HILSE_CTS,
+
+        /* HILSE_OUT_LAST sends the given command packet to 
+         * the last configured/running device on the loop.
+         */
+        HILSE_OUT_LAST,
+
+        /* HILSE_OUT_DISC sends the given command packet to
+         * the next device past the last configured/running one.
+         */
+        HILSE_OUT_DISC,
+
+        /* HILSE_FUNC runs a callback function with given arguments.
+         * a positive return value causes the "ugly" branch to be taken.
+         */
+        HILSE_FUNC,
+
+        /* HILSE_IN simply expects any non-errored packet to arrive 
+         * within arg usecs.
+         */
+        HILSE_IN                = 0x100,
+
+        /* HILSE_EXPECT expects a particular packet to arrive 
+         * within arg usecs, any other packet is considered an error.
+         */
+        HILSE_EXPECT,
+
+        /* HILSE_EXPECT_LAST as above but dev field should be last 
+         * discovered/operational device.
+         */
+        HILSE_EXPECT_LAST,
+
+        /* HILSE_EXPECT_LAST as above but dev field should be first 
+         * undiscovered/inoperational device.
+         */
+        HILSE_EXPECT_DISC
+};
+
+typedef int     (hilse_func) (hil_mlc *mlc, int arg);
+struct hilse_node {
+        enum hilse_act          act;    /* How to process this node         */
+        union {
+                hilse_func      *func;  /* Function to call if HILSE_FUNC   */
+                hil_packet      packet; /* Packet to send or to compare     */
+        } object;
+        int                     arg;    /* Timeout in usec or parm for func */
+        int                     good;   /* Node to jump to on success       */
+        int                     bad;    /* Node to jump to on error         */
+        int                     ugly;   /* Node to jump to on timeout       */
+};
+
+/* Methods for back-end drivers, e.g. hp_sdc_mlc */
+typedef int     (hil_mlc_cts) (hil_mlc *mlc);
+typedef void    (hil_mlc_out) (hil_mlc *mlc);
+typedef int     (hil_mlc_in)  (hil_mlc *mlc, suseconds_t timeout);
+
+struct hil_mlc_devinfo {
+        uint8_t idd[16];        /* Device ID Byte and Describe Record */
+        uint8_t rsc[16];        /* Security Code Header and Record */
+        uint8_t exd[16];        /* Extended Describe Record */
+        uint8_t rnm[16];        /* Device name as returned by RNM command */
+};
+
+struct hil_mlc_serio_map {
+        hil_mlc *mlc;
+        int di_revmap;
+        int didx;
+};
+
+/* How many (possibly old/detached) devices the we try to keep track of */
+#define HIL_MLC_DEVMEM 16
+
+struct hil_mlc {
+        struct list_head        list;   /* hil_mlc is organized as linked list */
+
+        rwlock_t                lock;
+
+        void *priv; /* Data specific to a particular type of MLC */
+
+        int                     seidx;  /* Current node in state engine */
+        int                     istarted, ostarted;
+
+        hil_mlc_cts             *cts;
+        struct semaphore        csem;   /* Raised when loop idle */
+
+        hil_mlc_out             *out;
+        struct semaphore        osem;   /* Raised when outpacket dispatched */
+        hil_packet              opacket;
+
+        hil_mlc_in              *in;
+        struct semaphore        isem;   /* Raised when a packet arrives */
+        hil_packet              ipacket[16];
+        hil_packet              imatch;
+        int                     icount;
+        struct timeval          instart;
+        suseconds_t             intimeout;
+
+        int                     ddi;    /* Last operational device id */
+        int                     lcv;    /* LCV to throttle loops */
+        struct timeval          lcv_tv; /* Time loop was started */
+
+        int                     di_map[7]; /* Maps below items to live devs */
+        struct hil_mlc_devinfo  di[HIL_MLC_DEVMEM];
+        struct serio            *serio[HIL_MLC_DEVMEM];
+        struct hil_mlc_serio_map serio_map[HIL_MLC_DEVMEM];
+        hil_packet              serio_opacket[HIL_MLC_DEVMEM];
+        int                     serio_oidx[HIL_MLC_DEVMEM];
+        struct hil_mlc_devinfo  di_scratch; /* Temporary area */
+
+        int                     opercnt;
+
+        struct tasklet_struct   *tasklet;
+};
+
+int hil_mlc_register(hil_mlc *mlc);
+int hil_mlc_unregister(hil_mlc *mlc);
diff --git a/include/linux/hp_sdc.h b/include/linux/hp_sdc.h
new file mode 100644
index 000000000000..debd71515312
--- /dev/null
+++ b/include/linux/hp_sdc.h
@@ -0,0 +1,300 @@
+/*
+ * HP i8042 System Device Controller -- header
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * 
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ * System Device Controller Microprocessor Firmware Theory of Operation
+ *      for Part Number 1820-4784 Revision B.  Dwg No. A-1820-4784-2
+ *
+ */
+
+#ifndef _LINUX_HP_SDC_H
+#define _LINUX_HP_SDC_H
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/timer.h>
+#if defined(__hppa__)
+#include <asm/hardware.h>
+#endif
+
+
+/* No 4X status reads take longer than this (in usec).
+ */
+#define HP_SDC_MAX_REG_DELAY 20000
+
+typedef void (hp_sdc_irqhook) (int irq, void *dev_id, 
+                               uint8_t status, uint8_t data);
+
+int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback);
+int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback);
+int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback);
+int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback);
+int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback);
+int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback);
+
+typedef struct {
+        int actidx;     /* Start of act.  Acts are atomic WRT I/O to SDC */
+        int idx;        /* Index within the act */
+        int endidx;     /* transaction is over and done if idx == endidx */
+        uint8_t *seq;   /* commands/data for the transaction */
+        union {
+          hp_sdc_irqhook   *irqhook;    /* Callback, isr or tasklet context */
+          struct semaphore *semaphore;  /* Semaphore to sleep on. */
+        } act;
+} hp_sdc_transaction;
+int hp_sdc_enqueue_transaction(hp_sdc_transaction *this);
+int hp_sdc_dequeue_transaction(hp_sdc_transaction *this);
+
+/* The HP_SDC_ACT* values are peculiar to this driver.
+ * Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another
+ * act to perform the dealloc.
+ */
+#define HP_SDC_ACT_PRECMD       0x01            /* Send a command first */
+#define HP_SDC_ACT_DATAREG      0x02            /* Set data registers */
+#define HP_SDC_ACT_DATAOUT      0x04            /* Send data bytes */
+#define HP_SDC_ACT_POSTCMD      0x08            /* Send command after */
+#define HP_SDC_ACT_DATAIN       0x10            /* Collect data after */
+#define HP_SDC_ACT_DURING       0x1f
+#define HP_SDC_ACT_SEMAPHORE    0x20            /* Raise semaphore after */
+#define HP_SDC_ACT_CALLBACK     0x40            /* Pass data to IRQ handler */
+#define HP_SDC_ACT_DEALLOC      0x80            /* Destroy transaction after */
+#define HP_SDC_ACT_AFTER        0xe0
+#define HP_SDC_ACT_DEAD         0x60            /* Act timed out. */
+
+/* Rest of the flags are straightforward representation of the SDC interface */
+#define HP_SDC_STATUS_IBF       0x02    /* Input buffer full */
+
+#define HP_SDC_STATUS_IRQMASK   0xf0    /* Bits containing "level 1" irq */
+#define HP_SDC_STATUS_PERIODIC  0x10    /* Periodic 10ms timer */
+#define HP_SDC_STATUS_USERTIMER 0x20    /* "Special purpose" timer */
+#define HP_SDC_STATUS_TIMER     0x30    /* Both PERIODIC and USERTIMER */
+#define HP_SDC_STATUS_REG       0x40    /* Data from an i8042 register */
+#define HP_SDC_STATUS_HILCMD    0x50    /* Command from HIL MLC */
+#define HP_SDC_STATUS_HILDATA   0x60    /* Data from HIL MLC */
+#define HP_SDC_STATUS_PUP       0x70    /* Sucessful power-up self test */
+#define HP_SDC_STATUS_KCOOKED   0x80    /* Key from cooked kbd */
+#define HP_SDC_STATUS_KRPG      0xc0    /* Key from Repeat Gen */
+#define HP_SDC_STATUS_KMOD_SUP  0x10    /* Shift key is up */
+#define HP_SDC_STATUS_KMOD_CUP  0x20    /* Control key is up */
+
+#define HP_SDC_NMISTATUS_FHS    0x40    /* NMI is a fast handshake irq */
+
+/* Internal i8042 registers (there are more, but they are not too useful). */
+
+#define HP_SDC_USE              0x02    /* Resource usage (including OB bit) */
+#define HP_SDC_IM               0x04    /* Interrupt mask */
+#define HP_SDC_CFG              0x11    /* Configuration register */
+#define HP_SDC_KBLANGUAGE       0x12    /* Keyboard language */
+
+#define HP_SDC_D0               0x70    /* General purpose data buffer 0 */
+#define HP_SDC_D1               0x71    /* General purpose data buffer 1 */
+#define HP_SDC_D2               0x72    /* General purpose data buffer 2 */
+#define HP_SDC_D3               0x73    /* General purpose data buffer 3 */
+#define HP_SDC_VT1              0x74    /* Timer for voice 1 */
+#define HP_SDC_VT2              0x75    /* Timer for voice 2 */
+#define HP_SDC_VT3              0x76    /* Timer for voice 3 */
+#define HP_SDC_VT4              0x77    /* Timer for voice 4 */
+#define HP_SDC_KBN              0x78    /* Which HIL devs are Nimitz */
+#define HP_SDC_KBC              0x79    /* Which HIL devs are cooked kbds */
+#define HP_SDC_LPS              0x7a    /* i8042's view of HIL status */
+#define HP_SDC_LPC              0x7b    /* i8042's view of HIL "control" */
+#define HP_SDC_RSV              0x7c    /* Reserved "for testing" */
+#define HP_SDC_LPR              0x7d    /* i8042 count of HIL reconfigs */
+#define HP_SDC_XTD              0x7e    /* "Extended Configuration" register */
+#define HP_SDC_STR              0x7f    /* i8042 self-test result */
+
+/* Bitfields for above registers */
+#define HP_SDC_USE_LOOP         0x04    /* Command is currently on the loop. */
+
+#define HP_SDC_IM_MASK          0x1f    /* these bits not part of cmd/status */
+#define HP_SDC_IM_FH            0x10    /* Mask the fast handshake irq */
+#define HP_SDC_IM_PT            0x08    /* Mask the periodic timer irq */
+#define HP_SDC_IM_TIMERS        0x04    /* Mask the MT/DT/CT irq */
+#define HP_SDC_IM_RESET         0x02    /* Mask the reset key irq */
+#define HP_SDC_IM_HIL           0x01    /* Mask the HIL MLC irq */
+
+#define HP_SDC_CFG_ROLLOVER     0x08    /* WTF is "N-key rollover"? */
+#define HP_SDC_CFG_KBD          0x10    /* There is a keyboard */
+#define HP_SDC_CFG_NEW          0x20    /* Supports/uses HIL MLC */
+#define HP_SDC_CFG_KBD_OLD      0x03    /* keyboard code for non-HIL */
+#define HP_SDC_CFG_KBD_NEW      0x07    /* keyboard code from HIL autoconfig */
+#define HP_SDC_CFG_REV          0x40    /* Code revision bit */
+#define HP_SDC_CFG_IDPROM       0x80    /* IDPROM present in kbd (not HIL) */
+
+#define HP_SDC_LPS_NDEV         0x07    /* # devices autoconfigured on HIL */
+#define HP_SDC_LPS_ACSUCC       0x08    /* loop autoconfigured successfully */
+#define HP_SDC_LPS_ACFAIL       0x80    /* last loop autoconfigure failed */
+
+#define HP_SDC_LPC_APE_IPF      0x01    /* HIL MLC APE/IPF (autopoll) set */
+#define HP_SDC_LPC_ARCONERR     0x02    /* i8042 autoreconfigs loop on err */
+#define HP_SDC_LPC_ARCQUIET     0x03    /* i8042 doesn't report autoreconfigs*/
+#define HP_SDC_LPC_COOK         0x10    /* i8042 cooks devices in _KBN */
+#define HP_SDC_LPC_RC           0x80    /* causes autoreconfig */
+
+#define HP_SDC_XTD_REV          0x07    /* contains revision code */
+#define HP_SDC_XTD_REV_STRINGS(val, str) \
+switch (val) {                                          \
+        case 0x1: str = "1820-3712"; break;             \
+        case 0x2: str = "1820-4379"; break;             \
+        case 0x3: str = "1820-4784"; break;             \
+        default: str = "unknown";                       \
+};
+#define HP_SDC_XTD_BEEPER       0x08    /* TI SN76494 beeper available */
+#define HP_SDC_XTD_BBRTC        0x20    /* OKI MSM-58321 BBRTC present */
+
+#define HP_SDC_CMD_LOAD_RT      0x31    /* Load real time (from 8042) */
+#define HP_SDC_CMD_LOAD_FHS     0x36    /* Load the fast handshake timer */
+#define HP_SDC_CMD_LOAD_MT      0x38    /* Load the match timer */
+#define HP_SDC_CMD_LOAD_DT      0x3B    /* Load the delay timer */
+#define HP_SDC_CMD_LOAD_CT      0x3E    /* Load the cycle timer */
+
+#define HP_SDC_CMD_SET_IM       0x40    /* 010xxxxx == set irq mask */
+
+/* The documents provided do not explicitly state that all registers betweem 
+ * 0x01 and 0x1f inclusive can be read by sending their register index as a 
+ * command, but this is implied and appears to be the case.
+ */
+#define HP_SDC_CMD_READ_RAM     0x00    /* Load from i8042 RAM (autoinc) */
+#define HP_SDC_CMD_READ_USE     0x02    /* Undocumented! Load from usage reg */
+#define HP_SDC_CMD_READ_IM      0x04    /* Load current interrupt mask */
+#define HP_SDC_CMD_READ_KCC     0x11    /* Load primary kbd config code */
+#define HP_SDC_CMD_READ_KLC     0x12    /* Load primary kbd language code */
+#define HP_SDC_CMD_READ_T1      0x13    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T2      0x14    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T3      0x15    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T4      0x16    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T5      0x17    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_D0      0xf0    /* Load from i8042 RAM location 0x70 */
+#define HP_SDC_CMD_READ_D1      0xf1    /* Load from i8042 RAM location 0x71 */
+#define HP_SDC_CMD_READ_D2      0xf2    /* Load from i8042 RAM location 0x72 */
+#define HP_SDC_CMD_READ_D3      0xf3    /* Load from i8042 RAM location 0x73 */
+#define HP_SDC_CMD_READ_VT1     0xf4    /* Load from i8042 RAM location 0x74 */
+#define HP_SDC_CMD_READ_VT2     0xf5    /* Load from i8042 RAM location 0x75 */
+#define HP_SDC_CMD_READ_VT3     0xf6    /* Load from i8042 RAM location 0x76 */
+#define HP_SDC_CMD_READ_VT4     0xf7    /* Load from i8042 RAM location 0x77 */
+#define HP_SDC_CMD_READ_KBN     0xf8    /* Load from i8042 RAM location 0x78 */
+#define HP_SDC_CMD_READ_KBC     0xf9    /* Load from i8042 RAM location 0x79 */
+#define HP_SDC_CMD_READ_LPS     0xfa    /* Load from i8042 RAM location 0x7a */
+#define HP_SDC_CMD_READ_LPC     0xfb    /* Load from i8042 RAM location 0x7b */
+#define HP_SDC_CMD_READ_RSV     0xfc    /* Load from i8042 RAM location 0x7c */
+#define HP_SDC_CMD_READ_LPR     0xfd    /* Load from i8042 RAM location 0x7d */
+#define HP_SDC_CMD_READ_XTD     0xfe    /* Load from i8042 RAM location 0x7e */
+#define HP_SDC_CMD_READ_STR     0xff    /* Load from i8042 RAM location 0x7f */
+
+#define HP_SDC_CMD_SET_ARD      0xA0    /* Set emulated autorepeat delay */
+#define HP_SDC_CMD_SET_ARR      0xA2    /* Set emulated autorepeat rate */
+#define HP_SDC_CMD_SET_BELL     0xA3    /* Set voice 3 params for "beep" cmd */
+#define HP_SDC_CMD_SET_RPGR     0xA6    /* Set "RPG" irq rate (doesn't work) */
+#define HP_SDC_CMD_SET_RTMS     0xAD    /* Set the RTC time (milliseconds) */
+#define HP_SDC_CMD_SET_RTD      0xAF    /* Set the RTC time (days) */
+#define HP_SDC_CMD_SET_FHS      0xB2    /* Set fast handshake timer */
+#define HP_SDC_CMD_SET_MT       0xB4    /* Set match timer */
+#define HP_SDC_CMD_SET_DT       0xB7    /* Set delay timer */
+#define HP_SDC_CMD_SET_CT       0xBA    /* Set cycle timer */
+#define HP_SDC_CMD_SET_RAMP     0xC1    /* Reset READ_RAM autoinc counter */
+#define HP_SDC_CMD_SET_D0       0xe0    /* Load to i8042 RAM location 0x70 */
+#define HP_SDC_CMD_SET_D1       0xe1    /* Load to i8042 RAM location 0x71 */
+#define HP_SDC_CMD_SET_D2       0xe2    /* Load to i8042 RAM location 0x72 */
+#define HP_SDC_CMD_SET_D3       0xe3    /* Load to i8042 RAM location 0x73 */
+#define HP_SDC_CMD_SET_VT1      0xe4    /* Load to i8042 RAM location 0x74 */
+#define HP_SDC_CMD_SET_VT2      0xe5    /* Load to i8042 RAM location 0x75 */
+#define HP_SDC_CMD_SET_VT3      0xe6    /* Load to i8042 RAM location 0x76 */
+#define HP_SDC_CMD_SET_VT4      0xe7    /* Load to i8042 RAM location 0x77 */
+#define HP_SDC_CMD_SET_KBN      0xe8    /* Load to i8042 RAM location 0x78 */
+#define HP_SDC_CMD_SET_KBC      0xe9    /* Load to i8042 RAM location 0x79 */
+#define HP_SDC_CMD_SET_LPS      0xea    /* Load to i8042 RAM location 0x7a */
+#define HP_SDC_CMD_SET_LPC      0xeb    /* Load to i8042 RAM location 0x7b */
+#define HP_SDC_CMD_SET_RSV      0xec    /* Load to i8042 RAM location 0x7c */
+#define HP_SDC_CMD_SET_LPR      0xed    /* Load to i8042 RAM location 0x7d */
+#define HP_SDC_CMD_SET_XTD      0xee    /* Load to i8042 RAM location 0x7e */
+#define HP_SDC_CMD_SET_STR      0xef    /* Load to i8042 RAM location 0x7f */
+
+#define HP_SDC_CMD_DO_RTCW      0xc2    /* i8042 RAM 0x70 --> RTC */
+#define HP_SDC_CMD_DO_RTCR      0xc3    /* RTC[0x70 0:3] --> irq/status/data */
+#define HP_SDC_CMD_DO_BEEP      0xc4    /* i8042 RAM 0x70-74  --> beeper,VT3 */
+#define HP_SDC_CMD_DO_HIL       0xc5    /* i8042 RAM 0x70-73 --> 
+                                           HIL MLC R0,R1 i8042 HIL watchdog */
+
+/* Values used to (de)mangle input/output to/from the HIL MLC */
+#define HP_SDC_DATA             0x40    /* Data from an 8042 register */
+#define HP_SDC_HIL_CMD          0x50    /* Data from HIL MLC R1/8042 */
+#define HP_SDC_HIL_R1MASK       0x0f    /* Contents of HIL MLC R1 0:3 */
+#define HP_SDC_HIL_AUTO         0x10    /* Set if POL results from i8042 */   
+#define HP_SDC_HIL_ISERR        0x80    /* Has meaning as in next 4 values */
+#define HP_SDC_HIL_RC_DONE      0x80    /* i8042 auto-configured loop */
+#define HP_SDC_HIL_ERR          0x81    /* HIL MLC R2 had a bit set */
+#define HP_SDC_HIL_TO           0x82    /* i8042 HIL watchdog expired */
+#define HP_SDC_HIL_RC           0x84    /* i8042 is auto-configuring loop */
+#define HP_SDC_HIL_DAT          0x60    /* Data from HIL MLC R0 */
+
+
+typedef struct {
+        rwlock_t        ibf_lock;
+        rwlock_t        lock;           /* user/tasklet lock */
+        rwlock_t        rtq_lock;       /* isr/tasklet lock */
+        rwlock_t        hook_lock;      /* isr/user lock for handler add/del */
+
+        unsigned int    irq, nmi;       /* Our IRQ lines */
+        unsigned long   base_io, status_io, data_io; /* Our IO ports */
+
+        uint8_t         im;             /* Interrupt mask */
+        int             set_im;         /* Interrupt mask needs to be set. */
+
+        int             ibf;            /* Last known status of IBF flag */
+        uint8_t         wi;             /* current i8042 write index */
+        uint8_t         r7[4];          /* current i8042[0x70 - 0x74] values */
+        uint8_t         r11, r7e;       /* Values from version/revision regs */
+
+        hp_sdc_irqhook  *timer, *reg, *hil, *pup, *cooked;
+
+#define HP_SDC_QUEUE_LEN 16
+        hp_sdc_transaction *tq[HP_SDC_QUEUE_LEN]; /* All pending read/writes */
+
+        int             rcurr, rqty;    /* Current read transact in process */
+        struct timeval  rtv;            /* Time when current read started */
+        int             wcurr;          /* Current write transact in process */
+
+        int             dev_err;        /* carries status from registration */
+#if defined(__hppa__)
+        struct parisc_device    *dev;
+#elif defined(__mc68000__)
+        void            *dev;
+#else
+#error No support for device registration on this arch yet.
+#endif
+
+        struct timer_list kicker;       /* Keeps below task alive */
+        struct tasklet_struct   task;
+
+} hp_i8042_sdc;
+
+#endif /* _LINUX_HP_SDC_H */
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index d664330d900e..0cea162b08c0 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -16,7 +16,6 @@ static inline int is_vm_hugetlb_page(struct vm_area_struct *vma)
 int hugetlb_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *);
 int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *);
 int follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, struct page **, struct vm_area_struct **, unsigned long *, int *, int);
-void zap_hugepage_range(struct vm_area_struct *, unsigned long, unsigned long);
 void unmap_hugepage_range(struct vm_area_struct *, unsigned long, unsigned long);
 int hugetlb_prefault(struct address_space *, struct vm_area_struct *);
 int hugetlb_report_meminfo(char *);
@@ -87,7 +86,6 @@ static inline unsigned long hugetlb_total_pages(void)
 #define follow_huge_addr(mm, addr, write)       ERR_PTR(-EINVAL)
 #define copy_hugetlb_page_range(src, dst, vma)  ({ BUG(); 0; })
 #define hugetlb_prefault(mapping, vma)          ({ BUG(); 0; })
-#define zap_hugepage_range(vma, start, len)     BUG()
 #define unmap_hugepage_range(vma, start, end)   BUG()
 #define is_hugepage_mem_enough(size)            0
 #define hugetlb_report_meminfo(buf)             0
diff --git a/include/linux/i2c-algo-bit.h b/include/linux/i2c-algo-bit.h
index 110904481238..c0e7fab28ce3 100644
--- a/include/linux/i2c-algo-bit.h
+++ b/include/linux/i2c-algo-bit.h
@@ -21,8 +21,6 @@
 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
    Frodo Looijaard <frodol@dds.nl> */
 
-/* $Id: i2c-algo-bit.h,v 1.10 2003/01/21 08:08:16 kmalkki Exp $ */
-
 #ifndef _LINUX_I2C_ALGO_BIT_H
 #define _LINUX_I2C_ALGO_BIT_H
 
@@ -46,8 +44,6 @@ struct i2c_algo_bit_data {
         int timeout;            /* in jiffies */
 };
 
-#define I2C_BIT_ADAP_MAX        16
-
 int i2c_bit_add_bus(struct i2c_adapter *);
 int i2c_bit_del_bus(struct i2c_adapter *);
 
diff --git a/include/linux/i2c-algo-pca.h b/include/linux/i2c-algo-pca.h
index 941b786c5732..226693e0d88b 100644
--- a/include/linux/i2c-algo-pca.h
+++ b/include/linux/i2c-algo-pca.h
@@ -9,8 +9,6 @@ struct i2c_algo_pca_data {
         int  (*wait_for_interrupt)      (struct i2c_algo_pca_data *adap);
 };
 
-#define I2C_PCA_ADAP_MAX        16
-
 int i2c_pca_add_bus(struct i2c_adapter *);
 int i2c_pca_del_bus(struct i2c_adapter *);
 
diff --git a/include/linux/i2c-algo-pcf.h b/include/linux/i2c-algo-pcf.h
index 2a508562255f..18b0adf57a3d 100644
--- a/include/linux/i2c-algo-pcf.h
+++ b/include/linux/i2c-algo-pcf.h
@@ -22,8 +22,6 @@
 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
    Frodo Looijaard <frodol@dds.nl> */
 
-/* $Id: i2c-algo-pcf.h,v 1.8 2003/01/21 08:08:16 kmalkki Exp $ */
-
 #ifndef _LINUX_I2C_ALGO_PCF_H
 #define _LINUX_I2C_ALGO_PCF_H
 
@@ -41,8 +39,6 @@ struct i2c_algo_pcf_data {
         int timeout;
 };
 
-#define I2C_PCF_ADAP_MAX        16
-
 int i2c_pcf_add_bus(struct i2c_adapter *);
 int i2c_pcf_del_bus(struct i2c_adapter *);
 
diff --git a/include/linux/i2c-dev.h b/include/linux/i2c-dev.h
index 541695679762..81c229a0fbca 100644
--- a/include/linux/i2c-dev.h
+++ b/include/linux/i2c-dev.h
@@ -19,8 +19,6 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
-/* $Id: i2c-dev.h,v 1.13 2003/01/21 08:08:16 kmalkki Exp $ */
-
 #ifndef _LINUX_I2C_DEV_H
 #define _LINUX_I2C_DEV_H
 
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 44f30876a1c9..1ce4b54caa21 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -164,10 +164,7 @@
 
 /* --- Bit algorithm adapters                                           */
 #define I2C_HW_B_LP             0x010000 /* Parallel port Philips style */
-#define I2C_HW_B_LPC            0x010001 /* Parallel port control reg. */
 #define I2C_HW_B_SER            0x010002 /* Serial line interface */
-#define I2C_HW_B_ELV            0x010003 /* ELV Card */
-#define I2C_HW_B_VELLE          0x010004 /* Vellemann K8000 */
 #define I2C_HW_B_BT848          0x010005 /* BT848 video boards */
 #define I2C_HW_B_WNV            0x010006 /* Winnov Videums */
 #define I2C_HW_B_VIA            0x010007 /* Via vt82c586b */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 3d49a305bf88..5e19a7ba69b2 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -23,15 +23,15 @@
 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
    Frodo Looijaard <frodol@dds.nl> */
 
-/* $Id: i2c.h,v 1.68 2003/01/21 08:08:16 kmalkki Exp $ */
-
 #ifndef _LINUX_I2C_H
 #define _LINUX_I2C_H
 
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/i2c-id.h>
+#include <linux/mod_devicetable.h>
 #include <linux/device.h>       /* for struct device */
+#include <linux/sched.h>        /* for completion */
 #include <asm/semaphore.h>
 
 /* --- For i2c-isa ---------------------------------------------------- */
@@ -94,10 +94,10 @@ extern s32 i2c_smbus_write_byte_data(struct i2c_client * client,
 extern s32 i2c_smbus_read_word_data(struct i2c_client * client, u8 command);
 extern s32 i2c_smbus_write_word_data(struct i2c_client * client,
                                      u8 command, u16 value);
-/* Returns the number of bytes transferred */
 extern s32 i2c_smbus_write_block_data(struct i2c_client * client,
                                       u8 command, u8 length,
                                       u8 *values);
+/* Returns the number of read bytes */
 extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client,
                                          u8 command, u8 *values);
 
@@ -391,10 +391,6 @@ struct i2c_msg {
 #define I2C_FUNC_10BIT_ADDR             0x00000002
 #define I2C_FUNC_PROTOCOL_MANGLING      0x00000004 /* I2C_M_{REV_DIR_ADDR,NOSTART,..} */
 #define I2C_FUNC_SMBUS_HWPEC_CALC       0x00000008 /* SMBus 2.0 */
-#define I2C_FUNC_SMBUS_READ_WORD_DATA_PEC  0x00000800 /* SMBus 2.0 */ 
-#define I2C_FUNC_SMBUS_WRITE_WORD_DATA_PEC 0x00001000 /* SMBus 2.0 */ 
-#define I2C_FUNC_SMBUS_PROC_CALL_PEC    0x00002000 /* SMBus 2.0 */
-#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL_PEC 0x00004000 /* SMBus 2.0 */
 #define I2C_FUNC_SMBUS_BLOCK_PROC_CALL  0x00008000 /* SMBus 2.0 */
 #define I2C_FUNC_SMBUS_QUICK            0x00010000 
 #define I2C_FUNC_SMBUS_READ_BYTE        0x00020000 
@@ -410,8 +406,6 @@ struct i2c_msg {
 #define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK  0x08000000 /* w/ 1-byte reg. addr. */
 #define I2C_FUNC_SMBUS_READ_I2C_BLOCK_2  0x10000000 /* I2C-like block xfer  */
 #define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK_2 0x20000000 /* w/ 2-byte reg. addr. */
-#define I2C_FUNC_SMBUS_READ_BLOCK_DATA_PEC  0x40000000 /* SMBus 2.0 */
-#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA_PEC 0x80000000 /* SMBus 2.0 */
 
 #define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
                              I2C_FUNC_SMBUS_WRITE_BYTE)
@@ -425,17 +419,6 @@ struct i2c_msg {
                                   I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
 #define I2C_FUNC_SMBUS_I2C_BLOCK_2 (I2C_FUNC_SMBUS_READ_I2C_BLOCK_2 | \
                                     I2C_FUNC_SMBUS_WRITE_I2C_BLOCK_2)
-#define I2C_FUNC_SMBUS_BLOCK_DATA_PEC (I2C_FUNC_SMBUS_READ_BLOCK_DATA_PEC | \
-                                       I2C_FUNC_SMBUS_WRITE_BLOCK_DATA_PEC)
-#define I2C_FUNC_SMBUS_WORD_DATA_PEC  (I2C_FUNC_SMBUS_READ_WORD_DATA_PEC | \
-                                       I2C_FUNC_SMBUS_WRITE_WORD_DATA_PEC)
-
-#define I2C_FUNC_SMBUS_READ_BYTE_PEC            I2C_FUNC_SMBUS_READ_BYTE_DATA
-#define I2C_FUNC_SMBUS_WRITE_BYTE_PEC           I2C_FUNC_SMBUS_WRITE_BYTE_DATA
-#define I2C_FUNC_SMBUS_READ_BYTE_DATA_PEC       I2C_FUNC_SMBUS_READ_WORD_DATA
-#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA_PEC      I2C_FUNC_SMBUS_WRITE_WORD_DATA
-#define I2C_FUNC_SMBUS_BYTE_PEC                 I2C_FUNC_SMBUS_BYTE_DATA
-#define I2C_FUNC_SMBUS_BYTE_DATA_PEC            I2C_FUNC_SMBUS_WORD_DATA
 
 #define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
                              I2C_FUNC_SMBUS_BYTE | \
@@ -443,20 +426,17 @@ struct i2c_msg {
                              I2C_FUNC_SMBUS_WORD_DATA | \
                              I2C_FUNC_SMBUS_PROC_CALL | \
                              I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
-                             I2C_FUNC_SMBUS_WRITE_BLOCK_DATA_PEC | \
                              I2C_FUNC_SMBUS_I2C_BLOCK)
 
 /* 
  * Data for SMBus Messages 
  */
 #define I2C_SMBUS_BLOCK_MAX     32      /* As specified in SMBus standard */    
-#define I2C_SMBUS_I2C_BLOCK_MAX 32      /* Not specified but we use same structure */
 union i2c_smbus_data {
         __u8 byte;
         __u16 word;
-        __u8 block[I2C_SMBUS_BLOCK_MAX + 3]; /* block[0] is used for length */
-                          /* one more for read length in block process call */
-                                                    /* and one more for PEC */
+        __u8 block[I2C_SMBUS_BLOCK_MAX + 2]; /* block[0] is used for length */
+                               /* and one more for user-space compatibility */
 };
 
 /* smbus_access read or write markers */
@@ -473,10 +453,6 @@ union i2c_smbus_data {
 #define I2C_SMBUS_BLOCK_DATA        5
 #define I2C_SMBUS_I2C_BLOCK_DATA    6
 #define I2C_SMBUS_BLOCK_PROC_CALL   7           /* SMBus 2.0 */
-#define I2C_SMBUS_BLOCK_DATA_PEC    8           /* SMBus 2.0 */
-#define I2C_SMBUS_PROC_CALL_PEC     9           /* SMBus 2.0 */
-#define I2C_SMBUS_BLOCK_PROC_CALL_PEC  10       /* SMBus 2.0 */
-#define I2C_SMBUS_WORD_DATA_PEC    11           /* SMBus 2.0 */
 
 
 /* ----- commands for the ioctl like i2c_command call:
@@ -506,11 +482,6 @@ union i2c_smbus_data {
 
 #define I2C_SMBUS       0x0720  /* SMBus-level access */
 
-/* ... algo-bit.c recognizes */
-#define I2C_UDELAY      0x0705  /* set delay in microsecs between each  */
-                                /* written byte (except address)        */
-#define I2C_MDELAY      0x0706  /* millisec delay between written bytes */
-
 /* ----- I2C-DEV: char device interface stuff ------------------------- */
 
 #define I2C_MAJOR       89              /* Device major number          */
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index bdc286ec947c..d79c8a4bc4f8 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -25,10 +25,14 @@
 /* How many different OSM's are we allowing */
 #define I2O_MAX_DRIVERS         8
 
-#include <asm/io.h>
-#include <asm/semaphore.h>      /* Needed for MUTEX init macros */
 #include <linux/pci.h>
 #include <linux/dma-mapping.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>    /* work_struct */
+
+#include <asm/io.h>
+#include <asm/semaphore.h>      /* Needed for MUTEX init macros */
 
 /* message queue empty */
 #define I2O_QUEUE_EMPTY         0xffffffff
@@ -66,8 +70,6 @@ struct i2o_device {
         struct device device;
 
         struct semaphore lock;  /* device lock */
-
-        struct class_device classdev;   /* i2o device class */
 };
 
 /*
@@ -194,7 +196,7 @@ struct i2o_controller {
         struct resource mem_resource;   /* Mem resource allocated to the IOP */
 
         struct device device;
-        struct class_device classdev;   /* I2O controller class */
+        struct class_device *classdev;  /* I2O controller class device */
         struct i2o_device *exec;        /* Executive */
 #if BITS_PER_LONG == 64
         spinlock_t context_list_lock;   /* lock for context_list */
@@ -492,7 +494,7 @@ static inline int i2o_dma_map_sg(struct i2o_controller *c,
  *      Returns 0 on success or -ENOMEM on failure.
  */
 static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
-                                size_t len, unsigned int gfp_mask)
+                                size_t len, gfp_t gfp_mask)
 {
         struct pci_dev *pdev = to_pci_dev(dev);
         int dma_64 = 0;
@@ -551,7 +553,7 @@ static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
  *      Returns the 0 on success or negative error code on failure.
  */
 static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
-                                  size_t len, unsigned int gfp_mask)
+                                  size_t len, gfp_t gfp_mask)
 {
         i2o_dma_free(dev, addr);
 
diff --git a/include/linux/ibmtr.h b/include/linux/ibmtr.h
index 2ef0b21517fb..1c7a0dd5536a 100644
--- a/include/linux/ibmtr.h
+++ b/include/linux/ibmtr.h
@@ -7,8 +7,8 @@
 /* ported to the Alpha architecture 02/20/96 (just used the HZ macro) */
 
 #define TR_RETRY_INTERVAL       (30*HZ) /* 500 on PC = 5 s */
-#define TR_RST_TIME             (HZ/20) /* 5 on PC = 50 ms */
-#define TR_BUSY_INTERVAL        (HZ/5)  /* 5 on PC = 200 ms */
+#define TR_RST_TIME             (msecs_to_jiffies(50))  /* 5 on PC = 50 ms */
+#define TR_BUSY_INTERVAL        (msecs_to_jiffies(200)) /* 5 on PC = 200 ms */
 #define TR_SPIN_INTERVAL        (3*HZ)  /* 3 seconds before init timeout */
 
 #define TR_ISA 1
diff --git a/include/linux/ide.h b/include/linux/ide.h
index a6dbb51ecd7b..3461abc1e854 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -218,7 +218,7 @@ typedef enum {	ide_unknown,	ide_generic,	ide_pci,
                 ide_rz1000,     ide_trm290,
                 ide_cmd646,     ide_cy82c693,   ide_4drives,
                 ide_pmac,       ide_etrax100,   ide_acorn,
-                ide_forced
+                ide_au1xxx, ide_forced
 } hwif_chipset_t;
 
 /*
diff --git a/include/linux/idr.h b/include/linux/idr.h
index ca3b7e462576..7fb3ff9c7b0e 100644
--- a/include/linux/idr.h
+++ b/include/linux/idr.h
@@ -71,8 +71,9 @@ struct idr {
  */
 
 void *idr_find(struct idr *idp, int id);
-int idr_pre_get(struct idr *idp, unsigned gfp_mask);
+int idr_pre_get(struct idr *idp, gfp_t gfp_mask);
 int idr_get_new(struct idr *idp, void *ptr, int *id);
 int idr_get_new_above(struct idr *idp, void *ptr, int starting_id, int *id);
 void idr_remove(struct idr *idp, int id);
+void idr_destroy(struct idr *idp);
 void idr_init(struct idr *idp);
diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h
index 0856548a2a08..a8b1a2071838 100644
--- a/include/linux/if_arp.h
+++ b/include/linux/if_arp.h
@@ -84,6 +84,7 @@
 #define ARPHRD_IEEE802_TR 800           /* Magic type ident for TR      */
 #define ARPHRD_IEEE80211 801            /* IEEE 802.11                  */
 #define ARPHRD_IEEE80211_PRISM 802      /* IEEE 802.11 + Prism2 header  */
+#define ARPHRD_IEEE80211_RADIOTAP 803   /* IEEE 802.11 + radiotap header */
 
 #define ARPHRD_VOID       0xFFFF        /* Void type, nothing is known */
 #define ARPHRD_NONE       0xFFFE        /* zero header length */
diff --git a/include/linux/input.h b/include/linux/input.h
index e8c296ff6257..f623c745c21c 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -12,6 +12,7 @@
 #ifdef __KERNEL__
 #include <linux/time.h>
 #include <linux/list.h>
+#include <linux/device.h>
 #else
 #include <sys/time.h>
 #include <sys/ioctl.h>
@@ -644,6 +645,7 @@ struct input_absinfo {
 #define BUS_ADB                 0x17
 #define BUS_I2C                 0x18
 #define BUS_HOST                0x19
+#define BUS_GSC                 0x1A
 
 /*
  * Values describing the status of an effect
@@ -889,11 +891,15 @@ struct input_dev {
         struct semaphore sem;   /* serializes open and close operations */
         unsigned int users;
 
-        struct device *dev;
+        struct class_device cdev;
+        struct device *dev;     /* will be removed soon */
+
+        int dynalloc;   /* temporarily */
 
         struct list_head        h_list;
         struct list_head        node;
 };
+#define to_input_dev(d) container_of(d, struct input_dev, cdev)
 
 /*
  * Structure for hotplug & device<->driver matching.
@@ -984,6 +990,23 @@ static inline void init_input_dev(struct input_dev *dev)
         INIT_LIST_HEAD(&dev->node);
 }
 
+struct input_dev *input_allocate_device(void);
+
+static inline void input_free_device(struct input_dev *dev)
+{
+        kfree(dev);
+}
+
+static inline struct input_dev *input_get_device(struct input_dev *dev)
+{
+        return to_input_dev(class_device_get(&dev->cdev));
+}
+
+static inline void input_put_device(struct input_dev *dev)
+{
+        class_device_put(&dev->cdev);
+}
+
 void input_register_device(struct input_dev *);
 void input_unregister_device(struct input_dev *);
 
@@ -1052,7 +1075,7 @@ static inline void input_set_abs_params(struct input_dev *dev, int axis, int min
         dev->absbit[LONG(axis)] |= BIT(axis);
 }
 
-extern struct class *input_class;
+extern struct class input_class;
 
 #endif
 #endif
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index ff853b3173c6..be197eb90077 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -69,7 +69,7 @@ extern int journal_enable_debug;
 #define jbd_debug(f, a...)      /**/
 #endif
 
-extern void * __jbd_kmalloc (const char *where, size_t size, int flags, int retry);
+extern void * __jbd_kmalloc (const char *where, size_t size, gfp_t flags, int retry);
 #define jbd_kmalloc(size, flags) \
         __jbd_kmalloc(__FUNCTION__, (size), (flags), journal_oom_retry)
 #define jbd_rep_kmalloc(size, flags) \
@@ -890,7 +890,7 @@ extern int	 journal_forget (handle_t *, struct buffer_head *);
 extern void      journal_sync_buffer (struct buffer_head *);
 extern int       journal_invalidatepage(journal_t *,
                                 struct page *, unsigned long);
-extern int       journal_try_to_free_buffers(journal_t *, struct page *, int);
+extern int       journal_try_to_free_buffers(journal_t *, struct page *, gfp_t);
 extern int       journal_stop(handle_t *);
 extern int       journal_flush (journal_t *);
 extern void      journal_lock_updates (journal_t *);
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 4367ce4db52a..f1925ccc9fe1 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -307,7 +307,7 @@ struct sysinfo {
         char _f[20-2*sizeof(long)-sizeof(int)]; /* Padding: libc5 uses this.. */
 };
 
-/* Force a compilation error if condition is false */
+/* Force a compilation error if condition is true */
 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
 
 #ifdef CONFIG_SYSCTL
diff --git a/include/linux/key-ui.h b/include/linux/key-ui.h
index 7a2e332067c3..e8b8a7a5c496 100644
--- a/include/linux/key-ui.h
+++ b/include/linux/key-ui.h
@@ -24,7 +24,8 @@ extern spinlock_t key_serial_lock;
 #define KEY_WRITE       0x04    /* require permission to update / modify */
 #define KEY_SEARCH      0x08    /* require permission to search (keyring) or find (key) */
 #define KEY_LINK        0x10    /* require permission to link */
-#define KEY_ALL         0x1f    /* all the above permissions */
+#define KEY_SETATTR     0x20    /* require permission to change attributes */
+#define KEY_ALL         0x3f    /* all the above permissions */
 
 /*
  * the keyring payload contains a list of the keys to which the keyring is
diff --git a/include/linux/key.h b/include/linux/key.h
index f1efa016dbf3..53513a3be53b 100644
--- a/include/linux/key.h
+++ b/include/linux/key.h
@@ -40,28 +40,32 @@ struct key;
 #define KEY_POS_WRITE   0x04000000      /* possessor can update key payload / add link to keyring */
 #define KEY_POS_SEARCH  0x08000000      /* possessor can find a key in search / search a keyring */
 #define KEY_POS_LINK    0x10000000      /* possessor can create a link to a key/keyring */
-#define KEY_POS_ALL     0x1f000000
+#define KEY_POS_SETATTR 0x20000000      /* possessor can set key attributes */
+#define KEY_POS_ALL     0x3f000000
 
 #define KEY_USR_VIEW    0x00010000      /* user permissions... */
 #define KEY_USR_READ    0x00020000
 #define KEY_USR_WRITE   0x00040000
 #define KEY_USR_SEARCH  0x00080000
 #define KEY_USR_LINK    0x00100000
-#define KEY_USR_ALL     0x001f0000
+#define KEY_USR_SETATTR 0x00200000
+#define KEY_USR_ALL     0x003f0000
 
 #define KEY_GRP_VIEW    0x00000100      /* group permissions... */
 #define KEY_GRP_READ    0x00000200
 #define KEY_GRP_WRITE   0x00000400
 #define KEY_GRP_SEARCH  0x00000800
 #define KEY_GRP_LINK    0x00001000
-#define KEY_GRP_ALL     0x00001f00
+#define KEY_GRP_SETATTR 0x00002000
+#define KEY_GRP_ALL     0x00003f00
 
 #define KEY_OTH_VIEW    0x00000001      /* third party permissions... */
 #define KEY_OTH_READ    0x00000002
 #define KEY_OTH_WRITE   0x00000004
 #define KEY_OTH_SEARCH  0x00000008
 #define KEY_OTH_LINK    0x00000010
-#define KEY_OTH_ALL     0x0000001f
+#define KEY_OTH_SETATTR 0x00000020
+#define KEY_OTH_ALL     0x0000003f
 
 struct seq_file;
 struct user_struct;
@@ -119,6 +123,7 @@ struct key {
         struct key_type         *type;          /* type of key */
         struct rw_semaphore     sem;            /* change vs change sem */
         struct key_user         *user;          /* owner of this key */
+        void                    *security;      /* security data for this key */
         time_t                  expiry;         /* time at which key expires (or 0) */
         uid_t                   uid;
         gid_t                   gid;
diff --git a/include/linux/kobj_map.h b/include/linux/kobj_map.h
index b6cc10bf8dfc..cbe7d8008042 100644
--- a/include/linux/kobj_map.h
+++ b/include/linux/kobj_map.h
@@ -1,5 +1,7 @@
 #ifdef __KERNEL__
 
+#include <asm/semaphore.h>
+
 typedef struct kobject *kobj_probe_t(dev_t, int *, void *);
 struct kobj_map;
 
diff --git a/include/linux/kobject.h b/include/linux/kobject.h
index 3b22304f12fd..7f7403aa4a41 100644
--- a/include/linux/kobject.h
+++ b/include/linux/kobject.h
@@ -65,7 +65,7 @@ extern void kobject_unregister(struct kobject *);
 extern struct kobject * kobject_get(struct kobject *);
 extern void kobject_put(struct kobject *);
 
-extern char * kobject_get_path(struct kobject *, int);
+extern char * kobject_get_path(struct kobject *, gfp_t);
 
 struct kobj_type {
         void (*release)(struct kobject *);
diff --git a/include/linux/kthread.h b/include/linux/kthread.h
index 3fa786448db3..ebdd41fd1082 100644
--- a/include/linux/kthread.h
+++ b/include/linux/kthread.h
@@ -70,6 +70,18 @@ void kthread_bind(struct task_struct *k, unsigned int cpu);
 int kthread_stop(struct task_struct *k);
 
 /**
+ * kthread_stop_sem: stop a thread created by kthread_create().
+ * @k: thread created by kthread_create().
+ * @s: semaphore that @k waits on while idle.
+ *
+ * Does essentially the same thing as kthread_stop() above, but wakes
+ * @k by calling up(@s).
+ *
+ * Returns the result of threadfn(), or -EINTR if wake_up_process()
+ * was never called. */
+int kthread_stop_sem(struct task_struct *k, struct semaphore *s);
+
+/**
  * kthread_should_stop: should this kthread return now?
  *
  * When someone calls kthread_stop on your kthread, it will be woken
diff --git a/include/linux/libata.h b/include/linux/libata.h
index ceee1fc42c60..0ba3af7a1236 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -91,12 +91,13 @@ enum {
         ATA_SHT_EMULATED        = 1,
         ATA_SHT_CMD_PER_LUN     = 1,
         ATA_SHT_THIS_ID         = -1,
-        ATA_SHT_USE_CLUSTERING  = 0,
+        ATA_SHT_USE_CLUSTERING  = 1,
 
         /* struct ata_device stuff */
         ATA_DFLAG_LBA48         = (1 << 0), /* device supports LBA48 */
         ATA_DFLAG_PIO           = (1 << 1), /* device currently in PIO mode */
         ATA_DFLAG_LOCK_SECTORS  = (1 << 2), /* don't adjust max_sectors */
+        ATA_DFLAG_LBA           = (1 << 3), /* device supports LBA */
 
         ATA_DEV_UNKNOWN         = 0,    /* unknown device */
         ATA_DEV_ATA             = 1,    /* ATA device */
@@ -154,17 +155,28 @@ enum {
         ATA_SHIFT_UDMA          = 0,
         ATA_SHIFT_MWDMA         = 8,
         ATA_SHIFT_PIO           = 11,
+        
+        /* Masks for port functions */
+        ATA_PORT_PRIMARY        = (1 << 0),
+        ATA_PORT_SECONDARY      = (1 << 1),
 };
 
-enum pio_task_states {
-        PIO_ST_UNKNOWN,
-        PIO_ST_IDLE,
-        PIO_ST_POLL,
-        PIO_ST_TMOUT,
-        PIO_ST,
-        PIO_ST_LAST,
-        PIO_ST_LAST_POLL,
-        PIO_ST_ERR,
+enum hsm_task_states {
+        HSM_ST_UNKNOWN,
+        HSM_ST_IDLE,
+        HSM_ST_POLL,
+        HSM_ST_TMOUT,
+        HSM_ST,
+        HSM_ST_LAST,
+        HSM_ST_LAST_POLL,
+        HSM_ST_ERR,
+};
+
+enum ata_completion_errors {
+        AC_ERR_OTHER            = (1 << 0),
+        AC_ERR_DEV              = (1 << 1),
+        AC_ERR_ATA_BUS          = (1 << 2),
+        AC_ERR_HOST_BUS         = (1 << 3),
 };
 
 /* forward declarations */
@@ -174,7 +186,7 @@ struct ata_port;
 struct ata_queued_cmd;
 
 /* typedefs */
-typedef int (*ata_qc_cb_t) (struct ata_queued_cmd *qc, u8 drv_stat);
+typedef int (*ata_qc_cb_t) (struct ata_queued_cmd *qc, unsigned int err_mask);
 
 struct ata_ioports {
         unsigned long           cmd_addr;
@@ -197,7 +209,7 @@ struct ata_ioports {
 struct ata_probe_ent {
         struct list_head        node;
         struct device           *dev;
-        struct ata_port_operations      *port_ops;
+        const struct ata_port_operations *port_ops;
         Scsi_Host_Template      *sht;
         struct ata_ioports      port[ATA_MAX_PORTS];
         unsigned int            n_ports;
@@ -220,7 +232,7 @@ struct ata_host_set {
         void __iomem            *mmio_base;
         unsigned int            n_ports;
         void                    *private_data;
-        struct ata_port_operations *ops;
+        const struct ata_port_operations *ops;
         struct ata_port *       ports[0];
 };
 
@@ -278,15 +290,18 @@ struct ata_device {
         u8                      xfer_mode;
         unsigned int            xfer_shift;     /* ATA_SHIFT_xxx */
 
-        /* cache info about current transfer mode */
-        u8                      xfer_protocol;  /* taskfile xfer protocol */
-        u8                      read_cmd;       /* opcode to use on read */
-        u8                      write_cmd;      /* opcode to use on write */
+        unsigned int            multi_count;    /* sectors count for
+                                                   READ/WRITE MULTIPLE */
+
+        /* for CHS addressing */
+        u16                     cylinders;      /* Number of cylinders */
+        u16                     heads;          /* Number of heads */
+        u16                     sectors;        /* Number of sectors per track */
 };
 
 struct ata_port {
         struct Scsi_Host        *host;  /* our co-allocated scsi host */
-        struct ata_port_operations      *ops;
+        const struct ata_port_operations *ops;
         unsigned long           flags;  /* ATA_FLAG_xxx */
         unsigned int            id;     /* unique id req'd by scsi midlyr */
         unsigned int            port_no; /* unique port #; from zero */
@@ -319,7 +334,7 @@ struct ata_port {
         struct work_struct      packet_task;
 
         struct work_struct      pio_task;
-        unsigned int            pio_task_state;
+        unsigned int            hsm_task_state;
         unsigned long           pio_task_timeout;
 
         void                    *private_data;
@@ -333,13 +348,12 @@ struct ata_port_operations {
         void (*set_piomode) (struct ata_port *, struct ata_device *);
         void (*set_dmamode) (struct ata_port *, struct ata_device *);
 
-        void (*tf_load) (struct ata_port *ap, struct ata_taskfile *tf);
+        void (*tf_load) (struct ata_port *ap, const struct ata_taskfile *tf);
         void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
 
-        void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf);
+        void (*exec_command)(struct ata_port *ap, const struct ata_taskfile *tf);
         u8   (*check_status)(struct ata_port *ap);
         u8   (*check_altstatus)(struct ata_port *ap);
-        u8   (*check_err)(struct ata_port *ap);
         void (*dev_select)(struct ata_port *ap, unsigned int device);
 
         void (*phy_reset) (struct ata_port *ap);
@@ -377,9 +391,22 @@ struct ata_port_info {
         unsigned long           pio_mask;
         unsigned long           mwdma_mask;
         unsigned long           udma_mask;
-        struct ata_port_operations      *port_ops;
+        const struct ata_port_operations *port_ops;
+};
+
+struct ata_timing {
+        unsigned short mode;            /* ATA mode */
+        unsigned short setup;           /* t1 */
+        unsigned short act8b;           /* t2 for 8-bit I/O */
+        unsigned short rec8b;           /* t2i for 8-bit I/O */
+        unsigned short cyc8b;           /* t0 for 8-bit I/O */
+        unsigned short active;          /* t2 or tD */
+        unsigned short recover;         /* t2i or tK */
+        unsigned short cycle;           /* t0 */
+        unsigned short udma;            /* t2CYCTYP/2 */
 };
 
+#define FIT(v,vmin,vmax)        max_t(short,min_t(short,v,vmax),vmin)
 
 extern void ata_port_probe(struct ata_port *);
 extern void __sata_phy_reset(struct ata_port *ap);
@@ -392,7 +419,7 @@ extern int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_i
                              unsigned int n_ports);
 extern void ata_pci_remove_one (struct pci_dev *pdev);
 #endif /* CONFIG_PCI */
-extern int ata_device_add(struct ata_probe_ent *ent);
+extern int ata_device_add(const struct ata_probe_ent *ent);
 extern void ata_host_set_remove(struct ata_host_set *host_set);
 extern int ata_scsi_detect(Scsi_Host_Template *sht);
 extern int ata_scsi_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
@@ -400,19 +427,20 @@ extern int ata_scsi_queuecmd(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmn
 extern int ata_scsi_error(struct Scsi_Host *host);
 extern int ata_scsi_release(struct Scsi_Host *host);
 extern unsigned int ata_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
+extern int ata_ratelimit(void);
+
 /*
  * Default driver ops implementations
  */
-extern void ata_tf_load(struct ata_port *ap, struct ata_taskfile *tf);
+extern void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
 extern void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
-extern void ata_tf_to_fis(struct ata_taskfile *tf, u8 *fis, u8 pmp);
-extern void ata_tf_from_fis(u8 *fis, struct ata_taskfile *tf);
+extern void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp);
+extern void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf);
 extern void ata_noop_dev_select (struct ata_port *ap, unsigned int device);
 extern void ata_std_dev_select (struct ata_port *ap, unsigned int device);
 extern u8 ata_check_status(struct ata_port *ap);
 extern u8 ata_altstatus(struct ata_port *ap);
-extern u8 ata_chk_err(struct ata_port *ap);
-extern void ata_exec_command(struct ata_port *ap, struct ata_taskfile *tf);
+extern void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf);
 extern int ata_port_start (struct ata_port *ap);
 extern void ata_port_stop (struct ata_port *ap);
 extern void ata_host_stop (struct ata_host_set *host_set);
@@ -423,8 +451,8 @@ extern void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf,
                 unsigned int buflen);
 extern void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
                  unsigned int n_elem);
-extern unsigned int ata_dev_classify(struct ata_taskfile *tf);
-extern void ata_dev_id_string(u16 *id, unsigned char *s,
+extern unsigned int ata_dev_classify(const struct ata_taskfile *tf);
+extern void ata_dev_id_string(const u16 *id, unsigned char *s,
                               unsigned int ofs, unsigned int len);
 extern void ata_dev_config(struct ata_port *ap, unsigned int i);
 extern void ata_bmdma_setup (struct ata_queued_cmd *qc);
@@ -432,7 +460,7 @@ extern void ata_bmdma_start (struct ata_queued_cmd *qc);
 extern void ata_bmdma_stop(struct ata_queued_cmd *qc);
 extern u8   ata_bmdma_status(struct ata_port *ap);
 extern void ata_bmdma_irq_clear(struct ata_port *ap);
-extern void ata_qc_complete(struct ata_queued_cmd *qc, u8 drv_stat);
+extern void ata_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask);
 extern void ata_eng_timeout(struct ata_port *ap);
 extern void ata_scsi_simulate(u16 *id, struct scsi_cmnd *cmd,
                               void (*done)(struct scsi_cmnd *));
@@ -441,6 +469,32 @@ extern int ata_std_bios_param(struct scsi_device *sdev,
                               sector_t capacity, int geom[]);
 extern int ata_scsi_slave_config(struct scsi_device *sdev);
 
+/*
+ * Timing helpers
+ */
+extern int ata_timing_compute(struct ata_device *, unsigned short,
+                              struct ata_timing *, int, int);
+extern void ata_timing_merge(const struct ata_timing *,
+                             const struct ata_timing *, struct ata_timing *,
+                             unsigned int);
+
+enum {
+        ATA_TIMING_SETUP        = (1 << 0),
+        ATA_TIMING_ACT8B        = (1 << 1),
+        ATA_TIMING_REC8B        = (1 << 2),
+        ATA_TIMING_CYC8B        = (1 << 3),
+        ATA_TIMING_8BIT         = ATA_TIMING_ACT8B | ATA_TIMING_REC8B |
+                                  ATA_TIMING_CYC8B,
+        ATA_TIMING_ACTIVE       = (1 << 4),
+        ATA_TIMING_RECOVER      = (1 << 5),
+        ATA_TIMING_CYCLE        = (1 << 6),
+        ATA_TIMING_UDMA         = (1 << 7),
+        ATA_TIMING_ALL          = ATA_TIMING_SETUP | ATA_TIMING_ACT8B |
+                                  ATA_TIMING_REC8B | ATA_TIMING_CYC8B |
+                                  ATA_TIMING_ACTIVE | ATA_TIMING_RECOVER |
+                                  ATA_TIMING_CYCLE | ATA_TIMING_UDMA,
+};
+
 
 #ifdef CONFIG_PCI
 struct pci_bits {
@@ -452,8 +506,8 @@ struct pci_bits {
 
 extern void ata_pci_host_stop (struct ata_host_set *host_set);
 extern struct ata_probe_ent *
-ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port);
-extern int pci_test_config_bits(struct pci_dev *pdev, struct pci_bits *bits);
+ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int portmask);
+extern int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits);
 
 #endif /* CONFIG_PCI */
 
@@ -463,7 +517,7 @@ static inline unsigned int ata_tag_valid(unsigned int tag)
         return (tag < ATA_MAX_QUEUE) ? 1 : 0;
 }
 
-static inline unsigned int ata_dev_present(struct ata_device *dev)
+static inline unsigned int ata_dev_present(const struct ata_device *dev)
 {
         return ((dev->class == ATA_DEV_ATA) ||
                 (dev->class == ATA_DEV_ATAPI));
@@ -662,11 +716,28 @@ static inline unsigned int sata_dev_present(struct ata_port *ap)
         return ((scr_read(ap, SCR_STATUS) & 0xf) == 0x3) ? 1 : 0;
 }
 
-static inline int ata_try_flush_cache(struct ata_device *dev)
+static inline int ata_try_flush_cache(const struct ata_device *dev)
 {
         return ata_id_wcache_enabled(dev->id) ||
                ata_id_has_flush(dev->id) ||
                ata_id_has_flush_ext(dev->id);
 }
 
+static inline unsigned int ac_err_mask(u8 status)
+{
+        if (status & ATA_BUSY)
+                return AC_ERR_ATA_BUS;
+        if (status & (ATA_ERR | ATA_DF))
+                return AC_ERR_DEV;
+        return 0;
+}
+
+static inline unsigned int __ac_err_mask(u8 status)
+{
+        unsigned int mask = ac_err_mask(status);
+        if (mask == 0)
+                return AC_ERR_OTHER;
+        return mask;
+}
+
 #endif /* __LINUX_LIBATA_H__ */
diff --git a/include/linux/loop.h b/include/linux/loop.h
index 53fa51595443..40f63c9879d2 100644
--- a/include/linux/loop.h
+++ b/include/linux/loop.h
@@ -52,7 +52,7 @@ struct loop_device {
         unsigned        lo_blocksize;
         void            *key_data; 
 
-        int             old_gfp_mask;
+        gfp_t           old_gfp_mask;
 
         spinlock_t              lo_lock;
         struct bio              *lo_bio;
diff --git a/include/linux/mbcache.h b/include/linux/mbcache.h
index 9263d2db2d67..99e044b4efc6 100644
--- a/include/linux/mbcache.h
+++ b/include/linux/mbcache.h
@@ -22,7 +22,7 @@ struct mb_cache_entry {
 };
 
 struct mb_cache_op {
-        int (*free)(struct mb_cache_entry *, int);
+        int (*free)(struct mb_cache_entry *, gfp_t);
 };
 
 /* Functions on caches */
diff --git a/include/linux/memory.h b/include/linux/memory.h
new file mode 100644
index 000000000000..0def328ab5cf
--- /dev/null
+++ b/include/linux/memory.h
@@ -0,0 +1,94 @@
+/*
+ * include/linux/memory.h - generic memory definition
+ *
+ * This is mainly for topological representation. We define the
+ * basic "struct memory_block" here, which can be embedded in per-arch
+ * definitions or NUMA information.
+ *
+ * Basic handling of the devices is done in drivers/base/memory.c
+ * and system devices are handled in drivers/base/sys.c.
+ *
+ * Memory block are exported via sysfs in the class/memory/devices/
+ * directory.
+ *
+ */
+#ifndef _LINUX_MEMORY_H_
+#define _LINUX_MEMORY_H_
+
+#include <linux/sysdev.h>
+#include <linux/node.h>
+#include <linux/compiler.h>
+
+#include <asm/semaphore.h>
+
+struct memory_block {
+        unsigned long phys_index;
+        unsigned long state;
+        /*
+         * This serializes all state change requests.  It isn't
+         * held during creation because the control files are
+         * created long after the critical areas during
+         * initialization.
+         */
+        struct semaphore state_sem;
+        int phys_device;                /* to which fru does this belong? */
+        void *hw;                       /* optional pointer to fw/hw data */
+        int (*phys_callback)(struct memory_block *);
+        struct sys_device sysdev;
+};
+
+/* These states are exposed to userspace as text strings in sysfs */
+#define MEM_ONLINE              (1<<0) /* exposed to userspace */
+#define MEM_GOING_OFFLINE       (1<<1) /* exposed to userspace */
+#define MEM_OFFLINE             (1<<2) /* exposed to userspace */
+
+/*
+ * All of these states are currently kernel-internal for notifying
+ * kernel components and architectures.
+ *
+ * For MEM_MAPPING_INVALID, all notifier chains with priority >0
+ * are called before pfn_to_page() becomes invalid.  The priority=0
+ * entry is reserved for the function that actually makes
+ * pfn_to_page() stop working.  Any notifiers that want to be called
+ * after that should have priority <0.
+ */
+#define MEM_MAPPING_INVALID     (1<<3)
+
+#ifndef CONFIG_MEMORY_HOTPLUG
+static inline int memory_dev_init(void)
+{
+        return 0;
+}
+static inline int register_memory_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
+static inline void unregister_memory_notifier(struct notifier_block *nb)
+{
+}
+#else
+extern int register_memory(struct memory_block *, struct mem_section *section, struct node *);
+extern int register_new_memory(struct mem_section *);
+extern int unregister_memory_section(struct mem_section *);
+extern int memory_dev_init(void);
+extern int register_memory_notifier(struct notifier_block *nb);
+extern void unregister_memory_notifier(struct notifier_block *nb);
+
+#define CONFIG_MEM_BLOCK_SIZE   (PAGES_PER_SECTION<<PAGE_SHIFT)
+
+extern int invalidate_phys_mapping(unsigned long, unsigned long);
+struct notifier_block;
+
+extern int register_memory_notifier(struct notifier_block *nb);
+extern void unregister_memory_notifier(struct notifier_block *nb);
+
+extern struct sysdev_class memory_sysdev_class;
+#endif /* CONFIG_MEMORY_HOTPLUG */
+
+#define hotplug_memory_notifier(fn, pri) {                      \
+        static struct notifier_block fn##_mem_nb =              \
+                { .notifier_call = fn, .priority = pri };       \
+        register_memory_notifier(&fn##_mem_nb);                 \
+}
+
+#endif /* _LINUX_MEMORY_H_ */
diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h
new file mode 100644
index 000000000000..01f03bc06eff
--- /dev/null
+++ b/include/linux/memory_hotplug.h
@@ -0,0 +1,104 @@
+#ifndef __LINUX_MEMORY_HOTPLUG_H
+#define __LINUX_MEMORY_HOTPLUG_H
+
+#include <linux/mmzone.h>
+#include <linux/spinlock.h>
+#include <linux/mmzone.h>
+#include <linux/notifier.h>
+
+#ifdef CONFIG_MEMORY_HOTPLUG
+/*
+ * pgdat resizing functions
+ */
+static inline
+void pgdat_resize_lock(struct pglist_data *pgdat, unsigned long *flags)
+{
+        spin_lock_irqsave(&pgdat->node_size_lock, *flags);
+}
+static inline
+void pgdat_resize_unlock(struct pglist_data *pgdat, unsigned long *flags)
+{
+        spin_unlock_irqrestore(&pgdat->node_size_lock, *flags);
+}
+static inline
+void pgdat_resize_init(struct pglist_data *pgdat)
+{
+        spin_lock_init(&pgdat->node_size_lock);
+}
+/*
+ * Zone resizing functions
+ */
+static inline unsigned zone_span_seqbegin(struct zone *zone)
+{
+        return read_seqbegin(&zone->span_seqlock);
+}
+static inline int zone_span_seqretry(struct zone *zone, unsigned iv)
+{
+        return read_seqretry(&zone->span_seqlock, iv);
+}
+static inline void zone_span_writelock(struct zone *zone)
+{
+        write_seqlock(&zone->span_seqlock);
+}
+static inline void zone_span_writeunlock(struct zone *zone)
+{
+        write_sequnlock(&zone->span_seqlock);
+}
+static inline void zone_seqlock_init(struct zone *zone)
+{
+        seqlock_init(&zone->span_seqlock);
+}
+extern int zone_grow_free_lists(struct zone *zone, unsigned long new_nr_pages);
+extern int zone_grow_waitqueues(struct zone *zone, unsigned long nr_pages);
+extern int add_one_highpage(struct page *page, int pfn, int bad_ppro);
+/* need some defines for these for archs that don't support it */
+extern void online_page(struct page *page);
+/* VM interface that may be used by firmware interface */
+extern int add_memory(u64 start, u64 size);
+extern int remove_memory(u64 start, u64 size);
+extern int online_pages(unsigned long, unsigned long);
+
+/* reasonably generic interface to expand the physical pages in a zone  */
+extern int __add_pages(struct zone *zone, unsigned long start_pfn,
+        unsigned long nr_pages);
+#else /* ! CONFIG_MEMORY_HOTPLUG */
+/*
+ * Stub functions for when hotplug is off
+ */
+static inline void pgdat_resize_lock(struct pglist_data *p, unsigned long *f) {}
+static inline void pgdat_resize_unlock(struct pglist_data *p, unsigned long *f) {}
+static inline void pgdat_resize_init(struct pglist_data *pgdat) {}
+
+static inline unsigned zone_span_seqbegin(struct zone *zone)
+{
+        return 0;
+}
+static inline int zone_span_seqretry(struct zone *zone, unsigned iv)
+{
+        return 0;
+}
+static inline void zone_span_writelock(struct zone *zone) {}
+static inline void zone_span_writeunlock(struct zone *zone) {}
+static inline void zone_seqlock_init(struct zone *zone) {}
+
+static inline int mhp_notimplemented(const char *func)
+{
+        printk(KERN_WARNING "%s() called, with CONFIG_MEMORY_HOTPLUG disabled\n", func);
+        dump_stack();
+        return -ENOSYS;
+}
+
+static inline int __add_pages(struct zone *zone, unsigned long start_pfn,
+        unsigned long nr_pages)
+{
+        return mhp_notimplemented(__FUNCTION__);
+}
+#endif /* ! CONFIG_MEMORY_HOTPLUG */
+static inline int __remove_pages(struct zone *zone, unsigned long start_pfn,
+        unsigned long nr_pages)
+{
+        printk(KERN_WARNING "%s() called, not yet supported\n", __FUNCTION__);
+        dump_stack();
+        return -ENOSYS;
+}
+#endif /* __LINUX_MEMORY_HOTPLUG_H */
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 58385ee1c0ac..8b67cf837ca9 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -27,10 +27,10 @@
 
 #include <linux/config.h>
 #include <linux/mmzone.h>
-#include <linux/bitmap.h>
 #include <linux/slab.h>
 #include <linux/rbtree.h>
 #include <linux/spinlock.h>
+#include <linux/nodemask.h>
 
 struct vm_area_struct;
 
@@ -47,8 +47,7 @@ struct vm_area_struct;
  * Locking policy for interlave:
  * In process context there is no locking because only the process accesses
  * its own state. All vma manipulation is somewhat protected by a down_read on
- * mmap_sem. For allocating in the interleave policy the page_table_lock
- * must be also aquired to protect il_next.
+ * mmap_sem.
  *
  * Freeing policy:
  * When policy is MPOL_BIND v.zonelist is kmalloc'ed and must be kfree'd.
@@ -63,7 +62,7 @@ struct mempolicy {
         union {
                 struct zonelist  *zonelist;     /* bind */
                 short            preferred_node; /* preferred */
-                DECLARE_BITMAP(nodes, MAX_NUMNODES); /* interleave */
+                nodemask_t       nodes;         /* interleave */
                 /* undefined for default */
         } v;
 };
@@ -155,6 +154,7 @@ struct mempolicy *get_vma_policy(struct task_struct *task,
 
 extern void numa_default_policy(void);
 extern void numa_policy_init(void);
+extern void numa_policy_rebind(const nodemask_t *old, const nodemask_t *new);
 extern struct mempolicy default_policy;
 
 #else
@@ -227,6 +227,11 @@ static inline void numa_default_policy(void)
 {
 }
 
+static inline void numa_policy_rebind(const nodemask_t *old,
+                                        const nodemask_t *new)
+{
+}
+
 #endif /* CONFIG_NUMA */
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 9b8d0476988a..68f5a0f392dd 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -158,6 +158,7 @@ extern int mii_link_ok (struct mii_if_info *mii);
 extern int mii_nway_restart (struct mii_if_info *mii);
 extern int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd);
 extern int mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd);
+extern int mii_check_gmii_support(struct mii_if_info *mii);
 extern void mii_check_link (struct mii_if_info *mii);
 extern unsigned int mii_check_media (struct mii_if_info *mii,
                                      unsigned int ok_to_print,
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 097b3a3c693d..5c1fb0a2e806 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -157,7 +157,7 @@ extern unsigned int kobjsize(const void *objp);
 
 #define VM_DONTCOPY     0x00020000      /* Do not copy this vma on fork */
 #define VM_DONTEXPAND   0x00040000      /* Cannot expand with mremap() */
-#define VM_RESERVED     0x00080000      /* Don't unmap it from swap_out */
+#define VM_RESERVED     0x00080000      /* Pages managed in a special way */
 #define VM_ACCOUNT      0x00100000      /* Is a VM accounted object */
 #define VM_HUGETLB      0x00400000      /* Huge TLB Page VM */
 #define VM_NONLINEAR    0x00800000      /* Is non-linear (remap_file_pages) */
@@ -226,13 +226,18 @@ struct page {
                                          * to show when page is mapped
                                          * & limit reverse map searches.
                                          */
-        unsigned long private;          /* Mapping-private opaque data:
+        union {
+                unsigned long private;  /* Mapping-private opaque data:
                                          * usually used for buffer_heads
                                          * if PagePrivate set; used for
                                          * swp_entry_t if PageSwapCache
                                          * When page is free, this indicates
                                          * order in the buddy system.
                                          */
+#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+                spinlock_t ptl;
+#endif
+        } u;
         struct address_space *mapping;  /* If low bit clear, points to
                                          * inode address_space, or NULL.
                                          * If page mapped as anonymous
@@ -260,6 +265,9 @@ struct page {
 #endif /* WANT_PAGE_VIRTUAL */
 };
 
+#define page_private(page)              ((page)->u.private)
+#define set_page_private(page, v)       ((page)->u.private = (v))
+
 /*
  * FIXME: take this include out, include page-flags.h in
  * files which need it (119 of them)
@@ -311,17 +319,17 @@ extern void FASTCALL(__page_cache_release(struct page *));
 
 #ifdef CONFIG_HUGETLB_PAGE
 
-static inline int page_count(struct page *p)
+static inline int page_count(struct page *page)
 {
-        if (PageCompound(p))
-                p = (struct page *)p->private;
-        return atomic_read(&(p)->_count) + 1;
+        if (PageCompound(page))
+                page = (struct page *)page_private(page);
+        return atomic_read(&page->_count) + 1;
 }
 
 static inline void get_page(struct page *page)
 {
         if (unlikely(PageCompound(page)))
-                page = (struct page *)page->private;
+                page = (struct page *)page_private(page);
         atomic_inc(&page->_count);
 }
 
@@ -338,7 +346,7 @@ static inline void get_page(struct page *page)
 
 static inline void put_page(struct page *page)
 {
-        if (!PageReserved(page) && put_page_testzero(page))
+        if (put_page_testzero(page))
                 __page_cache_release(page);
 }
 
@@ -587,7 +595,7 @@ static inline int PageAnon(struct page *page)
 static inline pgoff_t page_index(struct page *page)
 {
         if (unlikely(PageSwapCache(page)))
-                return page->private;
+                return page_private(page);
         return page->index;
 }
 
@@ -682,7 +690,7 @@ struct zap_details {
 
 unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address,
                 unsigned long size, struct zap_details *);
-unsigned long unmap_vmas(struct mmu_gather **tlb, struct mm_struct *mm,
+unsigned long unmap_vmas(struct mmu_gather **tlb,
                 struct vm_area_struct *start_vma, unsigned long start_addr,
                 unsigned long end_addr, unsigned long *nr_accounted,
                 struct zap_details *);
@@ -704,10 +712,6 @@ static inline void unmap_shared_mapping_range(struct address_space *mapping,
 }
 
 extern int vmtruncate(struct inode * inode, loff_t offset);
-extern pud_t *FASTCALL(__pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address));
-extern pmd_t *FASTCALL(__pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address));
-extern pte_t *FASTCALL(pte_alloc_kernel(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
-extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
 extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot);
 extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot);
 extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
@@ -723,6 +727,7 @@ void install_arg_page(struct vm_area_struct *, struct page *, unsigned long);
 
 int get_user_pages(struct task_struct *tsk, struct mm_struct *mm, unsigned long start,
                 int len, int write, int force, struct page **pages, struct vm_area_struct **vmas);
+void print_bad_pte(struct vm_area_struct *, pte_t, unsigned long);
 
 int __set_page_dirty_buffers(struct page *page);
 int __set_page_dirty_nobuffers(struct page *page);
@@ -747,7 +752,7 @@ extern unsigned long do_mremap(unsigned long addr,
  * The callback will be passed nr_to_scan == 0 when the VM is querying the
  * cache size, so a fastpath for that case is appropriate.
  */
-typedef int (*shrinker_t)(int nr_to_scan, unsigned int gfp_mask);
+typedef int (*shrinker_t)(int nr_to_scan, gfp_t gfp_mask);
 
 /*
  * Add an aging callback.  The int is the number of 'seeks' it takes
@@ -759,38 +764,83 @@ struct shrinker;
 extern struct shrinker *set_shrinker(int, shrinker_t);
 extern void remove_shrinker(struct shrinker *shrinker);
 
-/*
- * On a two-level or three-level page table, this ends up being trivial. Thus
- * the inlining and the symmetry break with pte_alloc_map() that does all
- * of this out-of-line.
- */
+int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address);
+int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address);
+int __pte_alloc(struct mm_struct *mm, pmd_t *pmd, unsigned long address);
+int __pte_alloc_kernel(pmd_t *pmd, unsigned long address);
+
 /*
  * The following ifdef needed to get the 4level-fixup.h header to work.
  * Remove it when 4level-fixup.h has been removed.
  */
-#ifdef CONFIG_MMU
-#ifndef __ARCH_HAS_4LEVEL_HACK 
+#if defined(CONFIG_MMU) && !defined(__ARCH_HAS_4LEVEL_HACK)
 static inline pud_t *pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address)
 {
-        if (pgd_none(*pgd))
-                return __pud_alloc(mm, pgd, address);
-        return pud_offset(pgd, address);
+        return (unlikely(pgd_none(*pgd)) && __pud_alloc(mm, pgd, address))?
+                NULL: pud_offset(pgd, address);
 }
 
 static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address)
 {
-        if (pud_none(*pud))
-                return __pmd_alloc(mm, pud, address);
-        return pmd_offset(pud, address);
+        return (unlikely(pud_none(*pud)) && __pmd_alloc(mm, pud, address))?
+                NULL: pmd_offset(pud, address);
 }
-#endif
-#endif /* CONFIG_MMU */
+#endif /* CONFIG_MMU && !__ARCH_HAS_4LEVEL_HACK */
+
+#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+/*
+ * We tuck a spinlock to guard each pagetable page into its struct page,
+ * at page->private, with BUILD_BUG_ON to make sure that this will not
+ * overflow into the next struct page (as it might with DEBUG_SPINLOCK).
+ * When freeing, reset page->mapping so free_pages_check won't complain.
+ */
+#define __pte_lockptr(page)     &((page)->u.ptl)
+#define pte_lock_init(_page)    do {                                    \
+        spin_lock_init(__pte_lockptr(_page));                           \
+} while (0)
+#define pte_lock_deinit(page)   ((page)->mapping = NULL)
+#define pte_lockptr(mm, pmd)    ({(void)(mm); __pte_lockptr(pmd_page(*(pmd)));})
+#else
+/*
+ * We use mm->page_table_lock to guard all pagetable pages of the mm.
+ */
+#define pte_lock_init(page)     do {} while (0)
+#define pte_lock_deinit(page)   do {} while (0)
+#define pte_lockptr(mm, pmd)    ({(void)(pmd); &(mm)->page_table_lock;})
+#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+
+#define pte_offset_map_lock(mm, pmd, address, ptlp)     \
+({                                                      \
+        spinlock_t *__ptl = pte_lockptr(mm, pmd);       \
+        pte_t *__pte = pte_offset_map(pmd, address);    \
+        *(ptlp) = __ptl;                                \
+        spin_lock(__ptl);                               \
+        __pte;                                          \
+})
+
+#define pte_unmap_unlock(pte, ptl)      do {            \
+        spin_unlock(ptl);                               \
+        pte_unmap(pte);                                 \
+} while (0)
+
+#define pte_alloc_map(mm, pmd, address)                 \
+        ((unlikely(!pmd_present(*(pmd))) && __pte_alloc(mm, pmd, address))? \
+                NULL: pte_offset_map(pmd, address))
+
+#define pte_alloc_map_lock(mm, pmd, address, ptlp)      \
+        ((unlikely(!pmd_present(*(pmd))) && __pte_alloc(mm, pmd, address))? \
+                NULL: pte_offset_map_lock(mm, pmd, address, ptlp))
+
+#define pte_alloc_kernel(pmd, address)                  \
+        ((unlikely(!pmd_present(*(pmd))) && __pte_alloc_kernel(pmd, address))? \
+                NULL: pte_offset_kernel(pmd, address))
 
 extern void free_area_init(unsigned long * zones_size);
 extern void free_area_init_node(int nid, pg_data_t *pgdat,
         unsigned long * zones_size, unsigned long zone_start_pfn, 
         unsigned long *zholes_size);
 extern void memmap_init_zone(unsigned long, int, unsigned long, unsigned long);
+extern void setup_per_zone_pages_min(void);
 extern void mem_init(void);
 extern void show_mem(void);
 extern void si_meminfo(struct sysinfo * val);
@@ -834,6 +884,7 @@ extern int split_vma(struct mm_struct *,
 extern int insert_vm_struct(struct mm_struct *, struct vm_area_struct *);
 extern void __vma_link_rb(struct mm_struct *, struct vm_area_struct *,
         struct rb_node **, struct rb_node *);
+extern void unlink_file_vma(struct vm_area_struct *);
 extern struct vm_area_struct *copy_vma(struct vm_area_struct **,
         unsigned long addr, unsigned long len, pgoff_t pgoff);
 extern void exit_mmap(struct mm_struct *);
@@ -894,7 +945,8 @@ void handle_ra_miss(struct address_space *mapping,
 unsigned long max_sane_readahead(unsigned long nr);
 
 /* Do stack extension */
-extern int expand_stack(struct vm_area_struct * vma, unsigned long address);
+extern int expand_stack(struct vm_area_struct *vma, unsigned long address);
+extern int expand_upwards(struct vm_area_struct *vma, unsigned long address);
 
 /* Look up the first VMA which satisfies  addr < vm_end,  NULL if none. */
 extern struct vm_area_struct * find_vma(struct mm_struct * mm, unsigned long addr);
@@ -917,40 +969,28 @@ static inline unsigned long vma_pages(struct vm_area_struct *vma)
         return (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
 }
 
-extern struct vm_area_struct *find_extend_vma(struct mm_struct *mm, unsigned long addr);
+struct vm_area_struct *find_extend_vma(struct mm_struct *, unsigned long addr);
+struct page *vmalloc_to_page(void *addr);
+unsigned long vmalloc_to_pfn(void *addr);
+int remap_pfn_range(struct vm_area_struct *, unsigned long addr,
+                        unsigned long pfn, unsigned long size, pgprot_t);
 
-extern struct page * vmalloc_to_page(void *addr);
-extern unsigned long vmalloc_to_pfn(void *addr);
-extern struct page * follow_page(struct mm_struct *mm, unsigned long address,
-                int write);
-extern int check_user_page_readable(struct mm_struct *mm, unsigned long address);
-int remap_pfn_range(struct vm_area_struct *, unsigned long,
-                unsigned long, unsigned long, pgprot_t);
+struct page *follow_page(struct mm_struct *, unsigned long address,
+                        unsigned int foll_flags);
+#define FOLL_WRITE      0x01    /* check pte is writable */
+#define FOLL_TOUCH      0x02    /* mark page accessed */
+#define FOLL_GET        0x04    /* do get_page on page */
+#define FOLL_ANON       0x08    /* give ZERO_PAGE if no pgtable */
 
 #ifdef CONFIG_PROC_FS
-void __vm_stat_account(struct mm_struct *, unsigned long, struct file *, long);
+void vm_stat_account(struct mm_struct *, unsigned long, struct file *, long);
 #else
-static inline void __vm_stat_account(struct mm_struct *mm,
+static inline void vm_stat_account(struct mm_struct *mm,
                         unsigned long flags, struct file *file, long pages)
 {
 }
 #endif /* CONFIG_PROC_FS */
 
-static inline void vm_stat_account(struct vm_area_struct *vma)
-{
-        __vm_stat_account(vma->vm_mm, vma->vm_flags, vma->vm_file,
-                                                        vma_pages(vma));
-}
-
-static inline void vm_stat_unaccount(struct vm_area_struct *vma)
-{
-        __vm_stat_account(vma->vm_mm, vma->vm_flags, vma->vm_file,
-                                                        -vma_pages(vma));
-}
-
-/* update per process rss and vm hiwater data */
-extern void update_mem_hiwater(struct task_struct *tsk);
-
 #ifndef CONFIG_DEBUG_PAGEALLOC
 static inline void
 kernel_map_pages(struct page *page, int numpages, int enable)
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 1ab78e8d6c53..aef6042f8f0b 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -50,7 +50,7 @@ struct mmc_command {
 #define MMC_ERR_INVALID 5
 
         struct mmc_data         *data;          /* data segment associated with cmd */
-        struct mmc_request      *mrq;           /* assoicated request */
+        struct mmc_request      *mrq;           /* associated request */
 };
 
 struct mmc_data {
@@ -68,7 +68,7 @@ struct mmc_data {
         unsigned int            bytes_xfered;
 
         struct mmc_command      *stop;          /* stop command */
-        struct mmc_request      *mrq;           /* assoicated request */
+        struct mmc_request      *mrq;           /* associated request */
 
         unsigned int            sg_len;         /* size of scatter list */
         struct scatterlist      *sg;            /* I/O scatter list */
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 5ed471b58f4f..f5fa3082fd6a 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -12,6 +12,7 @@
 #include <linux/threads.h>
 #include <linux/numa.h>
 #include <linux/init.h>
+#include <linux/seqlock.h>
 #include <asm/atomic.h>
 
 /* Free memory management - zoned buddy allocator.  */
@@ -137,6 +138,10 @@ struct zone {
          * free areas of different sizes
          */
         spinlock_t              lock;
+#ifdef CONFIG_MEMORY_HOTPLUG
+        /* see spanned/present_pages for more description */
+        seqlock_t               span_seqlock;
+#endif
         struct free_area        free_area[MAX_ORDER];
 
 
@@ -220,6 +225,16 @@ struct zone {
         /* zone_start_pfn == zone_start_paddr >> PAGE_SHIFT */
         unsigned long           zone_start_pfn;
 
+        /*
+         * zone_start_pfn, spanned_pages and present_pages are all
+         * protected by span_seqlock.  It is a seqlock because it has
+         * to be read outside of zone->lock, and it is done in the main
+         * allocator path.  But, it is written quite infrequently.
+         *
+         * The lock is declared along with zone->lock because it is
+         * frequently read in proximity to zone->lock.  It's good to
+         * give them a chance of being in the same cacheline.
+         */
         unsigned long           spanned_pages;  /* total size, including holes */
         unsigned long           present_pages;  /* amount of memory (excluding holes) */
 
@@ -273,6 +288,16 @@ typedef struct pglist_data {
         struct page *node_mem_map;
 #endif
         struct bootmem_data *bdata;
+#ifdef CONFIG_MEMORY_HOTPLUG
+        /*
+         * Must be held any time you expect node_start_pfn, node_present_pages
+         * or node_spanned_pages stay constant.  Holding this will also
+         * guarantee that any pfn_valid() stays that way.
+         *
+         * Nests above zone->lock and zone->size_seqlock.
+         */
+        spinlock_t node_size_lock;
+#endif
         unsigned long node_start_pfn;
         unsigned long node_present_pages; /* total number of physical pages */
         unsigned long node_spanned_pages; /* total size of physical page
@@ -293,6 +318,8 @@ typedef struct pglist_data {
 #endif
 #define nid_page_nr(nid, pagenr)        pgdat_page_nr(NODE_DATA(nid),(pagenr))
 
+#include <linux/memory_hotplug.h>
+
 extern struct pglist_data *pgdat_list;
 
 void __get_zone_counts(unsigned long *active, unsigned long *inactive,
@@ -302,7 +329,7 @@ void get_zone_counts(unsigned long *active, unsigned long *inactive,
 void build_all_zonelists(void);
 void wakeup_kswapd(struct zone *zone, int order);
 int zone_watermark_ok(struct zone *z, int order, unsigned long mark,
-                int alloc_type, int can_try_harder, int gfp_high);
+                int alloc_type, int can_try_harder, gfp_t gfp_high);
 
 #ifdef CONFIG_HAVE_MEMORY_PRESENT
 void memory_present(int nid, unsigned long start, unsigned long end);
@@ -509,6 +536,7 @@ static inline struct mem_section *__nr_to_section(unsigned long nr)
                 return NULL;
         return &mem_section[SECTION_NR_TO_ROOT(nr)][nr & SECTION_ROOT_MASK];
 }
+extern int __section_nr(struct mem_section* ms);
 
 /*
  * We use the lower bits of the mem_map pointer to store
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 2f0299a448f6..7b08c11ec4cc 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -244,4 +244,9 @@ struct pcmcia_device_id {
 #define PCMCIA_DEV_ID_MATCH_FAKE_CIS    0x0200
 #define PCMCIA_DEV_ID_MATCH_ANONYMOUS   0x0400
 
+/* I2C */
+struct i2c_device_id {
+        __u16 id;
+};
+
 #endif /* LINUX_MOD_DEVICETABLE_H */
diff --git a/include/linux/module.h b/include/linux/module.h
index f05372b7fe77..84d75f3a8aca 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -554,7 +554,9 @@ static inline void MODULE_PARM_(void) { }
 #ifdef MODULE
 /* DEPRECATED: Do not use. */
 #define MODULE_PARM(var,type)                                               \
-struct obsolete_modparm __parm_##var __attribute__((section("__obsparm"))) = \
+extern struct obsolete_modparm __parm_##var \
+__attribute__((section("__obsparm"))); \
+struct obsolete_modparm __parm_##var = \
 { __stringify(var), type, &MODULE_PARM_ }; \
 __MODULE_PARM_TYPE(var, type);
 #else
diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h
index 9a3d27257984..941da5c016a0 100644
--- a/include/linux/msdos_fs.h
+++ b/include/linux/msdos_fs.h
@@ -282,6 +282,17 @@ static inline u8 fat_attr(struct inode *inode)
                 MSDOS_I(inode)->i_attrs;
 }
 
+static inline unsigned char fat_checksum(const __u8 *name)
+{
+        unsigned char s = name[0];
+        s = (s<<7) + (s>>1) + name[1];  s = (s<<7) + (s>>1) + name[2];
+        s = (s<<7) + (s>>1) + name[3];  s = (s<<7) + (s>>1) + name[4];
+        s = (s<<7) + (s>>1) + name[5];  s = (s<<7) + (s>>1) + name[6];
+        s = (s<<7) + (s>>1) + name[7];  s = (s<<7) + (s>>1) + name[8];
+        s = (s<<7) + (s>>1) + name[9];  s = (s<<7) + (s>>1) + name[10];
+        return s;
+}
+
 static inline sector_t fat_clus_to_blknr(struct msdos_sb_info *sbi, int clus)
 {
         return ((sector_t)clus - FAT_START_ENT) * sbi->sec_per_clus
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index 142963f01d29..fc28841f3409 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -8,7 +8,10 @@
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/list.h>
+#include <linux/string.h>
+
 #include <linux/mtd/compatmac.h>
+
 #include <asm/unaligned.h>
 #include <asm/system.h>
 #include <asm/io.h>
diff --git a/include/linux/namei.h b/include/linux/namei.h
index 7db67b008cac..1c975d0d9e94 100644
--- a/include/linux/namei.h
+++ b/include/linux/namei.h
@@ -8,6 +8,7 @@ struct vfsmount;
 struct open_intent {
         int     flags;
         int     create_mode;
+        struct file *file;
 };
 
 enum { MAX_NESTED_LINKS = 5 };
@@ -65,6 +66,13 @@ extern int FASTCALL(link_path_walk(const char *, struct nameidata *));
 extern void path_release(struct nameidata *);
 extern void path_release_on_umount(struct nameidata *);
 
+extern int __user_path_lookup_open(const char __user *, unsigned lookup_flags, struct nameidata *nd, int open_flags);
+extern int path_lookup_open(const char *, unsigned lookup_flags, struct nameidata *, int open_flags);
+extern struct file *lookup_instantiate_filp(struct nameidata *nd, struct dentry *dentry,
+                int (*open)(struct inode *, struct file *));
+extern struct file *nameidata_to_filp(struct nameidata *nd, int flags);
+extern void release_open_intent(struct nameidata *);
+
 extern struct dentry * lookup_one_len(const char *, struct dentry *, int);
 extern struct dentry * lookup_hash(struct qstr *, struct dentry *);
 
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 368e4c825ff1..c6efce4a04a4 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -308,6 +308,7 @@ struct net_device
 #define NETIF_F_VLAN_CHALLENGED 1024    /* Device cannot handle VLAN packets */
 #define NETIF_F_TSO             2048    /* Can offload TCP/IP segmentation */
 #define NETIF_F_LLTX            4096    /* LockLess TX */
+#define NETIF_F_UFO             8192    /* Can offload UDP Large Send*/
 
         struct net_device       *next_sched;
 
@@ -873,11 +874,9 @@ static inline void netif_rx_complete(struct net_device *dev)
 
 static inline void netif_poll_disable(struct net_device *dev)
 {
-        while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) {
+        while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state))
                 /* No hurry. */
-                current->state = TASK_INTERRUPTIBLE;
-                schedule_timeout(1);
-        }
+                schedule_timeout_interruptible(1);
 }
 
 static inline void netif_poll_enable(struct net_device *dev)
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 9a6047ff1b25..325fe7ae49bb 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -41,6 +41,10 @@
 #define NFS_MAX_FILE_IO_BUFFER_SIZE     32768
 #define NFS_DEF_FILE_IO_BUFFER_SIZE     4096
 
+/* Default timeout values */
+#define NFS_MAX_UDP_TIMEOUT     (60*HZ)
+#define NFS_MAX_TCP_TIMEOUT     (600*HZ)
+
 /*
  * superblock magic number for NFS
  */
@@ -137,6 +141,7 @@ struct nfs_inode {
         unsigned long           attrtimeo_timestamp;
         __u64                   change_attr;            /* v4 only */
 
+        unsigned long           last_updated;
         /* "Generation counter" for the attribute cache. This is
          * bumped whenever we update the metadata on the
          * server.
@@ -236,13 +241,17 @@ static inline int nfs_caches_unstable(struct inode *inode)
         return atomic_read(&NFS_I(inode)->data_updates) != 0;
 }
 
+static inline void nfs_mark_for_revalidate(struct inode *inode)
+{
+        spin_lock(&inode->i_lock);
+        NFS_I(inode)->cache_validity |= NFS_INO_INVALID_ATTR | NFS_INO_INVALID_ACCESS;
+        spin_unlock(&inode->i_lock);
+}
+
 static inline void NFS_CACHEINV(struct inode *inode)
 {
-        if (!nfs_caches_unstable(inode)) {
-                spin_lock(&inode->i_lock);
-                NFS_I(inode)->cache_validity |= NFS_INO_INVALID_ATTR | NFS_INO_INVALID_ACCESS;
-                spin_unlock(&inode->i_lock);
-        }
+        if (!nfs_caches_unstable(inode))
+                nfs_mark_for_revalidate(inode);
 }
 
 static inline int nfs_server_capable(struct inode *inode, int cap)
@@ -276,7 +285,7 @@ static inline long nfs_save_change_attribute(struct inode *inode)
 static inline int nfs_verify_change_attribute(struct inode *inode, unsigned long chattr)
 {
         return !nfs_caches_unstable(inode)
-                && chattr == NFS_I(inode)->cache_change_attribute;
+                && time_after_eq(chattr, NFS_I(inode)->cache_change_attribute);
 }
 
 /*
@@ -286,6 +295,7 @@ extern void nfs_zap_caches(struct inode *);
 extern struct inode *nfs_fhget(struct super_block *, struct nfs_fh *,
                                 struct nfs_fattr *);
 extern int nfs_refresh_inode(struct inode *, struct nfs_fattr *);
+extern int nfs_post_op_update_inode(struct inode *inode, struct nfs_fattr *fattr);
 extern int nfs_getattr(struct vfsmount *, struct dentry *, struct kstat *);
 extern int nfs_permission(struct inode *, int, struct nameidata *);
 extern int nfs_access_get_cached(struct inode *, struct rpc_cred *, struct nfs_access_entry *);
@@ -312,6 +322,12 @@ extern void nfs_file_clear_open_context(struct file *filp);
 /* linux/net/ipv4/ipconfig.c: trims ip addr off front of name, too. */
 extern u32 root_nfs_parse_addr(char *name); /*__init*/
 
+static inline void nfs_fattr_init(struct nfs_fattr *fattr)
+{
+        fattr->valid = 0;
+        fattr->time_start = jiffies;
+}
+
 /*
  * linux/fs/nfs/file.c
  */
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index a2bf6914ff1b..40718669b9c8 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -41,7 +41,7 @@ struct nfs_fattr {
         __u32                   bitmap[2];      /* NFSv4 returned attribute bitmap */
         __u64                   change_attr;    /* NFSv4 change attribute */
         __u64                   pre_change_attr;/* pre-op NFSv4 change attribute */
-        unsigned long           timestamp;
+        unsigned long           time_start;
 };
 
 #define NFS_ATTR_WCC            0x0001          /* pre-op WCC data    */
@@ -96,12 +96,13 @@ struct nfs4_change_info {
         u64                     after;
 };
 
+struct nfs_seqid;
 /*
  * Arguments to the open call.
  */
 struct nfs_openargs {
         const struct nfs_fh *   fh;
-        __u32                   seqid;
+        struct nfs_seqid *      seqid;
         int                     open_flags;
         __u64                   clientid;
         __u32                   id;
@@ -123,6 +124,7 @@ struct nfs_openres {
         struct nfs4_change_info cinfo;
         __u32                   rflags;
         struct nfs_fattr *      f_attr;
+        struct nfs_fattr *      dir_attr;
         const struct nfs_server *server;
         int                     delegation_type;
         nfs4_stateid            delegation;
@@ -136,7 +138,7 @@ struct nfs_openres {
 struct nfs_open_confirmargs {
         const struct nfs_fh *   fh;
         nfs4_stateid            stateid;
-        __u32                   seqid;
+        struct nfs_seqid *      seqid;
 };
 
 struct nfs_open_confirmres {
@@ -148,13 +150,16 @@ struct nfs_open_confirmres {
  */
 struct nfs_closeargs {
         struct nfs_fh *         fh;
-        nfs4_stateid            stateid;
-        __u32                   seqid;
+        nfs4_stateid *          stateid;
+        struct nfs_seqid *      seqid;
         int                     open_flags;
+        const u32 *             bitmask;
 };
 
 struct nfs_closeres {
         nfs4_stateid            stateid;
+        struct nfs_fattr *      fattr;
+        const struct nfs_server *server;
 };
 /*
  *  * Arguments to the lock,lockt, and locku call.
@@ -164,30 +169,19 @@ struct nfs_lowner {
         u32                     id;
 };
 
-struct nfs_open_to_lock {
-        __u32                   open_seqid;
-        nfs4_stateid            open_stateid;
-        __u32                   lock_seqid;
-        struct nfs_lowner       lock_owner;
-};
-
-struct nfs_exist_lock {
-        nfs4_stateid            stateid;
-        __u32                   seqid;
-};
-
 struct nfs_lock_opargs {
+        struct nfs_seqid *      lock_seqid;
+        nfs4_stateid *          lock_stateid;
+        struct nfs_seqid *      open_seqid;
+        nfs4_stateid *          open_stateid;
+        struct nfs_lowner       lock_owner;
         __u32                   reclaim;
         __u32                   new_lock_owner;
-        union {
-                struct nfs_open_to_lock *open_lock;
-                struct nfs_exist_lock   *exist_lock;
-        } u;
 };
 
 struct nfs_locku_opargs {
-        __u32                   seqid;
-        nfs4_stateid            stateid;
+        struct nfs_seqid *      seqid;
+        nfs4_stateid *          stateid;
 };
 
 struct nfs_lockargs {
@@ -262,6 +256,7 @@ struct nfs_writeargs {
         enum nfs3_stable_how    stable;
         unsigned int            pgbase;
         struct page **          pages;
+        const u32 *             bitmask;
 };
 
 struct nfs_writeverf {
@@ -273,6 +268,7 @@ struct nfs_writeres {
         struct nfs_fattr *      fattr;
         struct nfs_writeverf *  verf;
         __u32                   count;
+        const struct nfs_server *server;
 };
 
 /*
@@ -550,6 +546,7 @@ struct nfs4_create_res {
         struct nfs_fh *                 fh;
         struct nfs_fattr *              fattr;
         struct nfs4_change_info         dir_cinfo;
+        struct nfs_fattr *              dir_fattr;
 };
 
 struct nfs4_fsinfo_arg {
@@ -571,8 +568,17 @@ struct nfs4_link_arg {
         const struct nfs_fh *           fh;
         const struct nfs_fh *           dir_fh;
         const struct qstr *             name;
+        const u32 *                     bitmask;
+};
+
+struct nfs4_link_res {
+        const struct nfs_server *       server;
+        struct nfs_fattr *              fattr;
+        struct nfs4_change_info         cinfo;
+        struct nfs_fattr *              dir_attr;
 };
 
+
 struct nfs4_lookup_arg {
         const struct nfs_fh *           dir_fh;
         const struct qstr *             name;
@@ -619,6 +625,13 @@ struct nfs4_readlink {
 struct nfs4_remove_arg {
         const struct nfs_fh *           fh;
         const struct qstr *             name;
+        const u32 *                     bitmask;
+};
+
+struct nfs4_remove_res {
+        const struct nfs_server *       server;
+        struct nfs4_change_info         cinfo;
+        struct nfs_fattr *              dir_attr;
 };
 
 struct nfs4_rename_arg {
@@ -626,11 +639,15 @@ struct nfs4_rename_arg {
         const struct nfs_fh *           new_dir;
         const struct qstr *             old_name;
         const struct qstr *             new_name;
+        const u32 *                     bitmask;
 };
 
 struct nfs4_rename_res {
+        const struct nfs_server *       server;
         struct nfs4_change_info         old_cinfo;
+        struct nfs_fattr *              old_fattr;
         struct nfs4_change_info         new_cinfo;
+        struct nfs_fattr *              new_fattr;
 };
 
 struct nfs4_setclientid {
@@ -722,7 +739,7 @@ struct nfs_rpc_ops {
         int     (*write)   (struct nfs_write_data *);
         int     (*commit)  (struct nfs_write_data *);
         int     (*create)  (struct inode *, struct dentry *,
-                            struct iattr *, int);
+                            struct iattr *, int, struct nameidata *);
         int     (*remove)  (struct inode *, struct qstr *);
         int     (*unlink_setup)  (struct rpc_message *,
                             struct dentry *, struct qstr *);
diff --git a/include/linux/nodemask.h b/include/linux/nodemask.h
index e96fe9062500..4726ef7ba8e8 100644
--- a/include/linux/nodemask.h
+++ b/include/linux/nodemask.h
@@ -12,6 +12,8 @@
  * see bitmap_scnprintf() and bitmap_parse() in lib/bitmap.c.
  * For details of nodelist_scnprintf() and nodelist_parse(), see
  * bitmap_scnlistprintf() and bitmap_parselist(), also in bitmap.c.
+ * For details of node_remap(), see bitmap_bitremap in lib/bitmap.c.
+ * For details of nodes_remap(), see bitmap_remap in lib/bitmap.c.
  *
  * The available nodemask operations are:
  *
@@ -52,6 +54,8 @@
  * int nodemask_parse(ubuf, ulen, mask) Parse ascii string as nodemask
  * int nodelist_scnprintf(buf, len, mask) Format nodemask as list for printing
  * int nodelist_parse(buf, map)         Parse ascii string as nodelist
+ * int node_remap(oldbit, old, new)     newbit = map(old, new)(oldbit)
+ * int nodes_remap(dst, src, old, new)  *dst = map(old, new)(dst)
  *
  * for_each_node_mask(node, mask)       for-loop node over mask
  *
@@ -307,6 +311,22 @@ static inline int __nodelist_parse(const char *buf, nodemask_t *dstp, int nbits)
         return bitmap_parselist(buf, dstp->bits, nbits);
 }
 
+#define node_remap(oldbit, old, new) \
+                __node_remap((oldbit), &(old), &(new), MAX_NUMNODES)
+static inline int __node_remap(int oldbit,
+                const nodemask_t *oldp, const nodemask_t *newp, int nbits)
+{
+        return bitmap_bitremap(oldbit, oldp->bits, newp->bits, nbits);
+}
+
+#define nodes_remap(dst, src, old, new) \
+                __nodes_remap(&(dst), &(src), &(old), &(new), MAX_NUMNODES)
+static inline void __nodes_remap(nodemask_t *dstp, const nodemask_t *srcp,
+                const nodemask_t *oldp, const nodemask_t *newp, int nbits)
+{
+        bitmap_remap(dstp->bits, srcp->bits, oldp->bits, newp->bits, nbits);
+}
+
 #if MAX_NUMNODES > 1
 #define for_each_node_mask(node, mask)                  \
         for ((node) = first_node(mask);                 \
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index acbf31c154f8..ba6c310a055f 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -21,16 +21,17 @@
 
 static inline gfp_t mapping_gfp_mask(struct address_space * mapping)
 {
-        return mapping->flags & __GFP_BITS_MASK;
+        return (__force gfp_t)mapping->flags & __GFP_BITS_MASK;
 }
 
 /*
  * This is non-atomic.  Only to be used before the mapping is activated.
  * Probably needs a barrier...
  */
-static inline void mapping_set_gfp_mask(struct address_space *m, int mask)
+static inline void mapping_set_gfp_mask(struct address_space *m, gfp_t mask)
 {
-        m->flags = (m->flags & ~__GFP_BITS_MASK) | mask;
+        m->flags = (m->flags & ~(__force unsigned long)__GFP_BITS_MASK) |
+                                (__force unsigned long)mask;
 }
 
 /*
@@ -69,7 +70,7 @@ extern struct page * find_lock_page(struct address_space *mapping,
 extern struct page * find_trylock_page(struct address_space *mapping,
                                 unsigned long index);
 extern struct page * find_or_create_page(struct address_space *mapping,
-                                unsigned long index, unsigned int gfp_mask);
+                                unsigned long index, gfp_t gfp_mask);
 unsigned find_get_pages(struct address_space *mapping, pgoff_t start,
                         unsigned int nr_pages, struct page **pages);
 unsigned find_get_pages_tag(struct address_space *mapping, pgoff_t *index,
@@ -92,9 +93,9 @@ extern int read_cache_pages(struct address_space *mapping,
                 struct list_head *pages, filler_t *filler, void *data);
 
 int add_to_page_cache(struct page *page, struct address_space *mapping,
-                                unsigned long index, int gfp_mask);
+                                unsigned long index, gfp_t gfp_mask);
 int add_to_page_cache_lru(struct page *page, struct address_space *mapping,
-                                unsigned long index, int gfp_mask);
+                                unsigned long index, gfp_t gfp_mask);
 extern void remove_from_page_cache(struct page *page);
 extern void __remove_from_page_cache(struct page *page);
 
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7349058ed778..3596ac94ecff 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -132,6 +132,7 @@ struct pci_dev {
         unsigned int    is_enabled:1;   /* pci_enable_device has been called */
         unsigned int    is_busmaster:1; /* device is busmaster */
         unsigned int    no_msi:1;       /* device may not use msi */
+        unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
 
         u32             saved_config_space[16]; /* config space saved at suspend time */
         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
@@ -490,6 +491,9 @@ extern void pci_disable_msix(struct pci_dev *dev);
 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
 #endif
 
+extern void pci_block_user_cfg_access(struct pci_dev *dev);
+extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
+
 /*
  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
  * a PCI domain is defined to be a set of PCI busses which share
@@ -560,6 +564,9 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
 
 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
 
+static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
+static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
+
 #endif /* CONFIG_PCI */
 
 /* Include architecture-dependent settings and functions */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index f74ed9462475..56192005fa4d 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -96,6 +96,9 @@
 #define PCI_CLASS_SERIAL_ACCESS         0x0c01
 #define PCI_CLASS_SERIAL_SSA            0x0c02
 #define PCI_CLASS_SERIAL_USB            0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI       0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI       0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI       0x0c0320
 #define PCI_CLASS_SERIAL_FIBER          0x0c04
 #define PCI_CLASS_SERIAL_SMBUS          0x0c05
 
@@ -132,9 +135,6 @@
 
 #define PCI_VENDOR_ID_COMPAQ            0x0e11
 #define PCI_DEVICE_ID_COMPAQ_TOKENRING  0x0508
-#define PCI_DEVICE_ID_COMPAQ_1280       0x3033
-#define PCI_DEVICE_ID_COMPAQ_TRIFLEX    0x4000
-#define PCI_DEVICE_ID_COMPAQ_6010       0x6010
 #define PCI_DEVICE_ID_COMPAQ_TACHYON    0xa0fc
 #define PCI_DEVICE_ID_COMPAQ_SMART2P    0xae10
 #define PCI_DEVICE_ID_COMPAQ_NETEL100   0xae32
@@ -274,7 +274,6 @@
 #define PCI_DEVICE_ID_ATI_RAGE128_PP    0x5050
 #define PCI_DEVICE_ID_ATI_RAGE128_PQ    0x5051
 #define PCI_DEVICE_ID_ATI_RAGE128_PR    0x5052
-#define PCI_DEVICE_ID_ATI_RAGE128_TR    0x5452
 #define PCI_DEVICE_ID_ATI_RAGE128_PS    0x5053
 #define PCI_DEVICE_ID_ATI_RAGE128_PT    0x5054
 #define PCI_DEVICE_ID_ATI_RAGE128_PU    0x5055
@@ -282,8 +281,6 @@
 #define PCI_DEVICE_ID_ATI_RAGE128_PW    0x5057
 #define PCI_DEVICE_ID_ATI_RAGE128_PX    0x5058
 /* Rage128 M4 */
-#define PCI_DEVICE_ID_ATI_RADEON_LE     0x4d45
-#define PCI_DEVICE_ID_ATI_RADEON_LF     0x4d46
 /* Radeon R100 */
 #define PCI_DEVICE_ID_ATI_RADEON_QD     0x5144
 #define PCI_DEVICE_ID_ATI_RADEON_QE     0x5145
@@ -304,32 +301,22 @@
 #define PCI_DEVICE_ID_ATI_RADEON_QW     0x5157
 #define PCI_DEVICE_ID_ATI_RADEON_QX     0x5158
 /* Radeon NV-100 */
-#define PCI_DEVICE_ID_ATI_RADEON_N1     0x5159
-#define PCI_DEVICE_ID_ATI_RADEON_N2     0x515a
 /* Radeon RV250 (9000) */
 #define PCI_DEVICE_ID_ATI_RADEON_Id     0x4964
 #define PCI_DEVICE_ID_ATI_RADEON_Ie     0x4965
 #define PCI_DEVICE_ID_ATI_RADEON_If     0x4966
 #define PCI_DEVICE_ID_ATI_RADEON_Ig     0x4967
 /* Radeon RV280 (9200) */
-#define PCI_DEVICE_ID_ATI_RADEON_Y_     0x5960
 #define PCI_DEVICE_ID_ATI_RADEON_Ya     0x5961
 #define PCI_DEVICE_ID_ATI_RADEON_Yd     0x5964
 /* Radeon R300 (9500) */
-#define PCI_DEVICE_ID_ATI_RADEON_AD     0x4144
 /* Radeon R300 (9700) */
 #define PCI_DEVICE_ID_ATI_RADEON_ND     0x4e44
 #define PCI_DEVICE_ID_ATI_RADEON_NE     0x4e45
 #define PCI_DEVICE_ID_ATI_RADEON_NF     0x4e46
 #define PCI_DEVICE_ID_ATI_RADEON_NG     0x4e47
-#define PCI_DEVICE_ID_ATI_RADEON_AE     0x4145
-#define PCI_DEVICE_ID_ATI_RADEON_AF     0x4146
 /* Radeon R350 (9800) */
-#define PCI_DEVICE_ID_ATI_RADEON_NH     0x4e48
-#define PCI_DEVICE_ID_ATI_RADEON_NI     0x4e49
 /* Radeon RV350 (9600) */
-#define PCI_DEVICE_ID_ATI_RADEON_AP     0x4150
-#define PCI_DEVICE_ID_ATI_RADEON_AR     0x4152
 /* Radeon M6 */
 #define PCI_DEVICE_ID_ATI_RADEON_LY     0x4c59
 #define PCI_DEVICE_ID_ATI_RADEON_LZ     0x4c5a
@@ -342,10 +329,6 @@
 #define PCI_DEVICE_ID_ATI_RADEON_Lf     0x4c66
 #define PCI_DEVICE_ID_ATI_RADEON_Lg     0x4c67
 /* Radeon */
-#define PCI_DEVICE_ID_ATI_RADEON_RA     0x5144
-#define PCI_DEVICE_ID_ATI_RADEON_RB     0x5145
-#define PCI_DEVICE_ID_ATI_RADEON_RC     0x5146
-#define PCI_DEVICE_ID_ATI_RADEON_RD     0x5147
 /* RadeonIGP */
 #define PCI_DEVICE_ID_ATI_RS100         0xcab0
 #define PCI_DEVICE_ID_ATI_RS200         0xcab2
@@ -446,45 +429,28 @@
 #define PCI_DEVICE_ID_CIRRUS_5465       0x00d6
 #define PCI_DEVICE_ID_CIRRUS_6729       0x1100
 #define PCI_DEVICE_ID_CIRRUS_6832       0x1110
-#define PCI_DEVICE_ID_CIRRUS_7542       0x1200
 #define PCI_DEVICE_ID_CIRRUS_7543       0x1202
-#define PCI_DEVICE_ID_CIRRUS_7541       0x1204
 #define PCI_DEVICE_ID_CIRRUS_4610       0x6001
 #define PCI_DEVICE_ID_CIRRUS_4612       0x6003
 #define PCI_DEVICE_ID_CIRRUS_4615       0x6004
-#define PCI_DEVICE_ID_CIRRUS_4281       0x6005
 
 #define PCI_VENDOR_ID_IBM               0x1014
-#define PCI_DEVICE_ID_IBM_FIRE_CORAL    0x000a
 #define PCI_DEVICE_ID_IBM_TR            0x0018
-#define PCI_DEVICE_ID_IBM_82G2675       0x001d
-#define PCI_DEVICE_ID_IBM_MCA           0x0020
-#define PCI_DEVICE_ID_IBM_82351         0x0022
-#define PCI_DEVICE_ID_IBM_PYTHON        0x002d
-#define PCI_DEVICE_ID_IBM_SERVERAID     0x002e
 #define PCI_DEVICE_ID_IBM_TR_WAKE       0x003e
-#define PCI_DEVICE_ID_IBM_MPIC          0x0046
-#define PCI_DEVICE_ID_IBM_3780IDSP      0x007d
-#define PCI_DEVICE_ID_IBM_CHUKAR        0x0096
 #define PCI_DEVICE_ID_IBM_CPC710_PCI64  0x00fc
-#define PCI_DEVICE_ID_IBM_CPC710_PCI32  0x0105
-#define PCI_DEVICE_ID_IBM_405GP         0x0156
 #define PCI_DEVICE_ID_IBM_SNIPE         0x0180
-#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
 #define PCI_DEVICE_ID_IBM_CITRINE               0x028C
 #define PCI_DEVICE_ID_IBM_GEMSTONE              0xB166
-#define PCI_DEVICE_ID_IBM_MPIC_2        0xffff
 #define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031
 #define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219
 #define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX         0x021A
 #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM     0x0251
 #define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL  0x252
 
-#define PCI_VENDOR_ID_COMPEX2           0x101a // pci.ids says "AT&T GIS (NCR)"
+#define PCI_VENDOR_ID_COMPEX2           0x101a /* pci.ids says "AT&T GIS (NCR)" */
 #define PCI_DEVICE_ID_COMPEX2_100VG     0x0005
 
 #define PCI_VENDOR_ID_WD                0x101c
-#define PCI_DEVICE_ID_WD_7197           0x3296
 #define PCI_DEVICE_ID_WD_90C            0xc24a
 
 #define PCI_VENDOR_ID_AMI               0x101e
@@ -501,33 +467,18 @@
 #define PCI_DEVICE_ID_AMD_FE_GATE_7006  0x7006
 #define PCI_DEVICE_ID_AMD_FE_GATE_7007  0x7007
 #define PCI_DEVICE_ID_AMD_FE_GATE_700C  0x700C
-#define PCI_DEVICE_ID_AMD_FE_GATE_700D  0x700D
 #define PCI_DEVICE_ID_AMD_FE_GATE_700E  0x700E
-#define PCI_DEVICE_ID_AMD_FE_GATE_700F  0x700F
-#define PCI_DEVICE_ID_AMD_COBRA_7400    0x7400
 #define PCI_DEVICE_ID_AMD_COBRA_7401    0x7401
-#define PCI_DEVICE_ID_AMD_COBRA_7403    0x7403
-#define PCI_DEVICE_ID_AMD_COBRA_7404    0x7404
-#define PCI_DEVICE_ID_AMD_VIPER_7408    0x7408
 #define PCI_DEVICE_ID_AMD_VIPER_7409    0x7409
 #define PCI_DEVICE_ID_AMD_VIPER_740B    0x740B
-#define PCI_DEVICE_ID_AMD_VIPER_740C    0x740C
 #define PCI_DEVICE_ID_AMD_VIPER_7410    0x7410
 #define PCI_DEVICE_ID_AMD_VIPER_7411    0x7411
 #define PCI_DEVICE_ID_AMD_VIPER_7413    0x7413
-#define PCI_DEVICE_ID_AMD_VIPER_7414    0x7414
-#define PCI_DEVICE_ID_AMD_OPUS_7440     0x7440
-#       define PCI_DEVICE_ID_AMD_VIPER_7440     PCI_DEVICE_ID_AMD_OPUS_7440
+#define PCI_DEVICE_ID_AMD_VIPER_7440    0x7440
 #define PCI_DEVICE_ID_AMD_OPUS_7441     0x7441
-#       define PCI_DEVICE_ID_AMD_VIPER_7441     PCI_DEVICE_ID_AMD_OPUS_7441
 #define PCI_DEVICE_ID_AMD_OPUS_7443     0x7443
-#       define PCI_DEVICE_ID_AMD_VIPER_7443     PCI_DEVICE_ID_AMD_OPUS_7443
+#define PCI_DEVICE_ID_AMD_VIPER_7443    0x7443
 #define PCI_DEVICE_ID_AMD_OPUS_7445     0x7445
-#define PCI_DEVICE_ID_AMD_OPUS_7448     0x7448
-# define        PCI_DEVICE_ID_AMD_VIPER_7448    PCI_DEVICE_ID_AMD_OPUS_7448
-#define PCI_DEVICE_ID_AMD_OPUS_7449     0x7449
-#       define PCI_DEVICE_ID_AMD_VIPER_7449     PCI_DEVICE_ID_AMD_OPUS_7449
-#define PCI_DEVICE_ID_AMD_8111_LAN      0x7462
 #define PCI_DEVICE_ID_AMD_8111_LPC      0x7468
 #define PCI_DEVICE_ID_AMD_8111_IDE      0x7469
 #define PCI_DEVICE_ID_AMD_8111_SMBUS2   0x746a
@@ -585,7 +536,6 @@
 #define PCI_DEVICE_ID_CT_65550          0x00e0
 #define PCI_DEVICE_ID_CT_65554          0x00e4
 #define PCI_DEVICE_ID_CT_65555          0x00e5
-#define PCI_DEVICE_ID_CT_69000          0x00c0
 
 #define PCI_VENDOR_ID_MIRO              0x1031
 #define PCI_DEVICE_ID_MIRO_36050        0x5601
@@ -639,7 +589,6 @@
 #define PCI_DEVICE_ID_SI_550            0x0550
 #define PCI_DEVICE_ID_SI_540_VGA        0x5300
 #define PCI_DEVICE_ID_SI_550_VGA        0x5315
-#define PCI_DEVICE_ID_SI_601            0x0601
 #define PCI_DEVICE_ID_SI_620            0x0620
 #define PCI_DEVICE_ID_SI_630            0x0630
 #define PCI_DEVICE_ID_SI_633            0x0633
@@ -650,30 +599,22 @@
 #define PCI_DEVICE_ID_SI_648            0x0648
 #define PCI_DEVICE_ID_SI_650            0x0650
 #define PCI_DEVICE_ID_SI_651            0x0651
-#define PCI_DEVICE_ID_SI_652            0x0652
 #define PCI_DEVICE_ID_SI_655            0x0655
 #define PCI_DEVICE_ID_SI_661            0x0661
 #define PCI_DEVICE_ID_SI_730            0x0730
 #define PCI_DEVICE_ID_SI_733            0x0733
 #define PCI_DEVICE_ID_SI_630_VGA        0x6300
-#define PCI_DEVICE_ID_SI_730_VGA        0x7300
 #define PCI_DEVICE_ID_SI_735            0x0735
 #define PCI_DEVICE_ID_SI_740            0x0740
 #define PCI_DEVICE_ID_SI_741            0x0741
 #define PCI_DEVICE_ID_SI_745            0x0745
 #define PCI_DEVICE_ID_SI_746            0x0746
-#define PCI_DEVICE_ID_SI_748            0x0748
-#define PCI_DEVICE_ID_SI_750            0x0750
-#define PCI_DEVICE_ID_SI_751            0x0751
-#define PCI_DEVICE_ID_SI_752            0x0752
 #define PCI_DEVICE_ID_SI_755            0x0755
 #define PCI_DEVICE_ID_SI_760            0x0760
 #define PCI_DEVICE_ID_SI_900            0x0900
 #define PCI_DEVICE_ID_SI_961            0x0961
 #define PCI_DEVICE_ID_SI_962            0x0962
 #define PCI_DEVICE_ID_SI_963            0x0963
-#define PCI_DEVICE_ID_SI_5107           0x5107
-#define PCI_DEVICE_ID_SI_5300           0x5300
 #define PCI_DEVICE_ID_SI_5511           0x5511
 #define PCI_DEVICE_ID_SI_5513           0x5513
 #define PCI_DEVICE_ID_SI_5518           0x5518
@@ -685,10 +626,6 @@
 #define PCI_DEVICE_ID_SI_5597           0x5597
 #define PCI_DEVICE_ID_SI_5598           0x5598
 #define PCI_DEVICE_ID_SI_5600           0x5600
-#define PCI_DEVICE_ID_SI_6300           0x6300
-#define PCI_DEVICE_ID_SI_6306           0x6306
-#define PCI_DEVICE_ID_SI_6326           0x6326
-#define PCI_DEVICE_ID_SI_7001           0x7001
 #define PCI_DEVICE_ID_SI_7012           0x7012
 #define PCI_DEVICE_ID_SI_7013           0x7013
 #define PCI_DEVICE_ID_SI_7016           0x7016
@@ -709,23 +646,19 @@
 #define PCI_DEVICE_ID_HP_DIVA_TOSCA1    0x1049
 #define PCI_DEVICE_ID_HP_DIVA_TOSCA2    0x104A
 #define PCI_DEVICE_ID_HP_DIVA_MAESTRO   0x104B
-#define PCI_DEVICE_ID_HP_PCI_LBA        0x1054
-#define PCI_DEVICE_ID_HP_REO_SBA        0x10f0
 #define PCI_DEVICE_ID_HP_REO_IOC        0x10f1
 #define PCI_DEVICE_ID_HP_VISUALIZE_FXE  0x108b
 #define PCI_DEVICE_ID_HP_DIVA_HALFDOME  0x1223
 #define PCI_DEVICE_ID_HP_DIVA_KEYSTONE  0x1226
 #define PCI_DEVICE_ID_HP_DIVA_POWERBAR  0x1227
-#define PCI_DEVICE_ID_HP_ZX1_SBA        0x1229
 #define PCI_DEVICE_ID_HP_ZX1_IOC        0x122a
 #define PCI_DEVICE_ID_HP_PCIX_LBA       0x122e
 #define PCI_DEVICE_ID_HP_SX1000_IOC     0x127c
 #define PCI_DEVICE_ID_HP_DIVA_EVEREST   0x1282
 #define PCI_DEVICE_ID_HP_DIVA_AUX       0x1290
 #define PCI_DEVICE_ID_HP_DIVA_RMP3      0x1301
-#define PCI_DEVICE_ID_HP_CISS           0x3210
+#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a
 #define PCI_DEVICE_ID_HP_CISSA          0x3220
-#define PCI_DEVICE_ID_HP_CISSB          0x3222
 #define PCI_DEVICE_ID_HP_CISSC          0x3230
 #define PCI_DEVICE_ID_HP_CISSD          0x3238
 #define PCI_DEVICE_ID_HP_ZX2_IOC        0x4031
@@ -733,8 +666,6 @@
 #define PCI_VENDOR_ID_PCTECH            0x1042
 #define PCI_DEVICE_ID_PCTECH_RZ1000     0x1000
 #define PCI_DEVICE_ID_PCTECH_RZ1001     0x1001
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_0  0x3000
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_1  0x3010
 #define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
 
 #define PCI_VENDOR_ID_ASUSTEK           0x1043
@@ -744,24 +675,15 @@
 #define PCI_DEVICE_ID_DPT               0xa400
 
 #define PCI_VENDOR_ID_OPTI              0x1045
-#define PCI_DEVICE_ID_OPTI_92C178       0xc178
-#define PCI_DEVICE_ID_OPTI_82C557       0xc557
 #define PCI_DEVICE_ID_OPTI_82C558       0xc558
 #define PCI_DEVICE_ID_OPTI_82C621       0xc621
 #define PCI_DEVICE_ID_OPTI_82C700       0xc700
-#define PCI_DEVICE_ID_OPTI_82C701       0xc701
-#define PCI_DEVICE_ID_OPTI_82C814       0xc814
-#define PCI_DEVICE_ID_OPTI_82C822       0xc822
-#define PCI_DEVICE_ID_OPTI_82C861       0xc861
 #define PCI_DEVICE_ID_OPTI_82C825       0xd568
 
 #define PCI_VENDOR_ID_ELSA              0x1048
 #define PCI_DEVICE_ID_ELSA_MICROLINK    0x1000
 #define PCI_DEVICE_ID_ELSA_QS3000       0x3000
 
-#define PCI_VENDOR_ID_SGS               0x104a
-#define PCI_DEVICE_ID_SGS_2000          0x0008
-#define PCI_DEVICE_ID_SGS_1764          0x0009
 
 #define PCI_VENDOR_ID_BUSLOGIC                0x104B
 #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
@@ -769,7 +691,6 @@
 #define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
 
 #define PCI_VENDOR_ID_TI                0x104c
-#define PCI_DEVICE_ID_TI_TVP4010        0x3d04
 #define PCI_DEVICE_ID_TI_TVP4020        0x3d07
 #define PCI_DEVICE_ID_TI_4450           0x8011
 #define PCI_DEVICE_ID_TI_XX21_XX11      0x8031
@@ -803,14 +724,10 @@
 #define PCI_DEVICE_ID_TI_X420           0xac8e
 
 #define PCI_VENDOR_ID_SONY              0x104d
-#define PCI_DEVICE_ID_SONY_CXD3222      0x8039
 
-#define PCI_VENDOR_ID_OAK               0x104e
-#define PCI_DEVICE_ID_OAK_OTI107        0x0107
 
 /* Winbond have two vendor IDs! See 0x10ad as well */
 #define PCI_VENDOR_ID_WINBOND2          0x1050
-#define PCI_DEVICE_ID_WINBOND2_89C940   0x0940
 #define PCI_DEVICE_ID_WINBOND2_89C940F  0x5a5a
 #define PCI_DEVICE_ID_WINBOND2_6692     0x6692
 
@@ -819,19 +736,15 @@
   
 #define PCI_VENDOR_ID_EFAR              0x1055
 #define PCI_DEVICE_ID_EFAR_SLC90E66_1   0x9130
-#define PCI_DEVICE_ID_EFAR_SLC90E66_0   0x9460
-#define PCI_DEVICE_ID_EFAR_SLC90E66_2   0x9462
 #define PCI_DEVICE_ID_EFAR_SLC90E66_3   0x9463
 
 #define PCI_VENDOR_ID_MOTOROLA          0x1057
-#define PCI_VENDOR_ID_MOTOROLA_OOPS     0x1507
 #define PCI_DEVICE_ID_MOTOROLA_MPC105   0x0001
 #define PCI_DEVICE_ID_MOTOROLA_MPC106   0x0002
 #define PCI_DEVICE_ID_MOTOROLA_MPC107   0x0004
 #define PCI_DEVICE_ID_MOTOROLA_RAVEN    0x4801
 #define PCI_DEVICE_ID_MOTOROLA_FALCON   0x4802
 #define PCI_DEVICE_ID_MOTOROLA_HAWK     0x4803
-#define PCI_DEVICE_ID_MOTOROLA_CPX8216  0x4806
 #define PCI_DEVICE_ID_MOTOROLA_HARRIER  0x480b
 #define PCI_DEVICE_ID_MOTOROLA_MPC5200  0x5803
 
@@ -842,33 +755,19 @@
 #define PCI_DEVICE_ID_PROMISE_20262     0x4d38
 #define PCI_DEVICE_ID_PROMISE_20263     0x0D38
 #define PCI_DEVICE_ID_PROMISE_20268     0x4d68
-#define PCI_DEVICE_ID_PROMISE_20268R    0x6268
 #define PCI_DEVICE_ID_PROMISE_20269     0x4d69
 #define PCI_DEVICE_ID_PROMISE_20270     0x6268
 #define PCI_DEVICE_ID_PROMISE_20271     0x6269
 #define PCI_DEVICE_ID_PROMISE_20275     0x1275
 #define PCI_DEVICE_ID_PROMISE_20276     0x5275
 #define PCI_DEVICE_ID_PROMISE_20277     0x7275
-#define PCI_DEVICE_ID_PROMISE_5300      0x5300
 
-#define PCI_VENDOR_ID_N9                0x105d
-#define PCI_DEVICE_ID_N9_I128           0x2309
-#define PCI_DEVICE_ID_N9_I128_2         0x2339
-#define PCI_DEVICE_ID_N9_I128_T2R       0x493d
 
 #define PCI_VENDOR_ID_UMC               0x1060
 #define PCI_DEVICE_ID_UMC_UM8673F       0x0101
-#define PCI_DEVICE_ID_UMC_UM8891A       0x0891
 #define PCI_DEVICE_ID_UMC_UM8886BF      0x673a
 #define PCI_DEVICE_ID_UMC_UM8886A       0x886a
-#define PCI_DEVICE_ID_UMC_UM8881F       0x8881
-#define PCI_DEVICE_ID_UMC_UM8886F       0x8886
-#define PCI_DEVICE_ID_UMC_UM9017F       0x9017
-#define PCI_DEVICE_ID_UMC_UM8886N       0xe886
-#define PCI_DEVICE_ID_UMC_UM8891N       0xe891
 
-#define PCI_VENDOR_ID_X                 0x1061
-#define PCI_DEVICE_ID_X_AGX016          0x0001
 
 #define PCI_VENDOR_ID_MYLEX             0x1069
 #define PCI_DEVICE_ID_MYLEX_DAC960_P    0x0001
@@ -879,37 +778,26 @@
 #define PCI_DEVICE_ID_MYLEX_DAC960_BA   0xBA56
 #define PCI_DEVICE_ID_MYLEX_DAC960_GEM  0xB166
 
-#define PCI_VENDOR_ID_PICOP             0x1066
-#define PCI_DEVICE_ID_PICOP_PT86C52X    0x0001
-#define PCI_DEVICE_ID_PICOP_PT80C524    0x8002
 
 #define PCI_VENDOR_ID_APPLE             0x106b
 #define PCI_DEVICE_ID_APPLE_BANDIT      0x0001
-#define PCI_DEVICE_ID_APPLE_GC          0x0002
 #define PCI_DEVICE_ID_APPLE_HYDRA       0x000e
 #define PCI_DEVICE_ID_APPLE_UNI_N_FW    0x0018
-#define PCI_DEVICE_ID_APPLE_KL_USB      0x0019
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP   0x0020
 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC  0x0021
-#define PCI_DEVICE_ID_APPLE_KEYLARGO    0x0022
 #define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024
-#define PCI_DEVICE_ID_APPLE_KEYLARGO_P  0x0025
-#define PCI_DEVICE_ID_APPLE_KL_USB_P    0x0026
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e
-#define PCI_DEVICE_ID_APPLE_UNI_N_FW2   0x0030
 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
 #define PCI_DEVICE_ID_APPLE_UNI_N_ATA   0x0033
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP2  0x0034
 #define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b
-#define PCI_DEVICE_ID_APPLE_KEYLARGO_I  0x003e
 #define PCI_DEVICE_ID_APPLE_K2_ATA100   0x0043
 #define PCI_DEVICE_ID_APPLE_U3_AGP      0x004b
 #define PCI_DEVICE_ID_APPLE_K2_GMAC     0x004c
 #define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
 #define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
-#define PCI_DEVICE_ID_APPLE_SH_FW       0x0052
 #define PCI_DEVICE_ID_APPLE_U3L_AGP     0x0058
 #define PCI_DEVICE_ID_APPLE_U3H_AGP     0x0059
 #define PCI_DEVICE_ID_APPLE_TIGON3      0x1645
@@ -922,12 +810,9 @@
 #define PCI_DEVICE_ID_YAMAHA_744        0x0010
 #define PCI_DEVICE_ID_YAMAHA_754        0x0012
 
-#define PCI_VENDOR_ID_NEXGEN            0x1074
-#define PCI_DEVICE_ID_NEXGEN_82C501     0x4e78
 
 #define PCI_VENDOR_ID_QLOGIC            0x1077
 #define PCI_DEVICE_ID_QLOGIC_ISP1020    0x1020
-#define PCI_DEVICE_ID_QLOGIC_ISP1022    0x1022
 #define PCI_DEVICE_ID_QLOGIC_ISP2100    0x2100
 #define PCI_DEVICE_ID_QLOGIC_ISP2200    0x2200
 #define PCI_DEVICE_ID_QLOGIC_ISP2300    0x2300
@@ -945,32 +830,20 @@
 #define PCI_DEVICE_ID_CYRIX_PCI_MASTER  0x0001
 #define PCI_DEVICE_ID_CYRIX_5520        0x0002
 #define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
-#define PCI_DEVICE_ID_CYRIX_5530_SMI    0x0101
 #define PCI_DEVICE_ID_CYRIX_5530_IDE    0x0102
 #define PCI_DEVICE_ID_CYRIX_5530_AUDIO  0x0103
 #define PCI_DEVICE_ID_CYRIX_5530_VIDEO  0x0104
 
-#define PCI_VENDOR_ID_LEADTEK           0x107d
-#define PCI_DEVICE_ID_LEADTEK_805       0x0000
 
-#define PCI_VENDOR_ID_INTERPHASE        0x107e
-#define PCI_DEVICE_ID_INTERPHASE_5526   0x0004
-#define PCI_DEVICE_ID_INTERPHASE_55x6   0x0005
-#define PCI_DEVICE_ID_INTERPHASE_5575   0x0008
 
 #define PCI_VENDOR_ID_CONTAQ            0x1080
-#define PCI_DEVICE_ID_CONTAQ_82C599     0x0600
 #define PCI_DEVICE_ID_CONTAQ_82C693     0xc693
 
-#define PCI_VENDOR_ID_FOREX             0x1083
 
 #define PCI_VENDOR_ID_OLICOM            0x108d
-#define PCI_DEVICE_ID_OLICOM_OC3136     0x0001
-#define PCI_DEVICE_ID_OLICOM_OC2315     0x0011
 #define PCI_DEVICE_ID_OLICOM_OC2325     0x0012
 #define PCI_DEVICE_ID_OLICOM_OC2183     0x0013
 #define PCI_DEVICE_ID_OLICOM_OC2326     0x0014
-#define PCI_DEVICE_ID_OLICOM_OC6151     0x0021
 
 #define PCI_VENDOR_ID_SUN               0x108e
 #define PCI_DEVICE_ID_SUN_EBUS          0x1000
@@ -989,49 +862,31 @@
 #define PCI_DEVICE_ID_SUN_CASSINI       0xabba
 
 #define PCI_VENDOR_ID_CMD               0x1095
-#define PCI_DEVICE_ID_CMD_640           0x0640
 #define PCI_DEVICE_ID_CMD_643           0x0643
 #define PCI_DEVICE_ID_CMD_646           0x0646
-#define PCI_DEVICE_ID_CMD_647           0x0647
 #define PCI_DEVICE_ID_CMD_648           0x0648
 #define PCI_DEVICE_ID_CMD_649           0x0649
-#define PCI_DEVICE_ID_CMD_670           0x0670
-#define PCI_DEVICE_ID_CMD_680           0x0680
 
 #define PCI_DEVICE_ID_SII_680           0x0680
 #define PCI_DEVICE_ID_SII_3112          0x3112
 #define PCI_DEVICE_ID_SII_1210SA        0x0240
 
-#define PCI_VENDOR_ID_VISION            0x1098
-#define PCI_DEVICE_ID_VISION_QD8500     0x0001
-#define PCI_DEVICE_ID_VISION_QD8580     0x0002
 
 #define PCI_VENDOR_ID_BROOKTREE         0x109e
-#define PCI_DEVICE_ID_BROOKTREE_848     0x0350
-#define PCI_DEVICE_ID_BROOKTREE_849A    0x0351
-#define PCI_DEVICE_ID_BROOKTREE_878_1   0x036e
 #define PCI_DEVICE_ID_BROOKTREE_878     0x0878
 #define PCI_DEVICE_ID_BROOKTREE_879     0x0879
-#define PCI_DEVICE_ID_BROOKTREE_8474    0x8474
 
-#define PCI_VENDOR_ID_SIERRA            0x10a8
-#define PCI_DEVICE_ID_SIERRA_STB        0x0000
 
 #define PCI_VENDOR_ID_SGI               0x10a9
 #define PCI_DEVICE_ID_SGI_IOC3          0x0003
 #define PCI_DEVICE_ID_SGI_IOC4          0x100a
 #define PCI_VENDOR_ID_SGI_LITHIUM       0x1002
 
-#define PCI_VENDOR_ID_ACC               0x10aa
-#define PCI_DEVICE_ID_ACC_2056          0x0000
 
 #define PCI_VENDOR_ID_WINBOND           0x10ad
-#define PCI_DEVICE_ID_WINBOND_83769     0x0001
 #define PCI_DEVICE_ID_WINBOND_82C105    0x0105
 #define PCI_DEVICE_ID_WINBOND_83C553    0x0565
 
-#define PCI_VENDOR_ID_DATABOOK          0x10b3
-#define PCI_DEVICE_ID_DATABOOK_87144    0xb106
 
 #define PCI_VENDOR_ID_PLX               0x10b5
 #define PCI_DEVICE_ID_PLX_R685          0x1030
@@ -1042,33 +897,19 @@
 #define PCI_DEVICE_ID_PLX_DJINN_ITOO    0x1151
 #define PCI_DEVICE_ID_PLX_R753          0x1152
 #define PCI_DEVICE_ID_PLX_OLITEC        0x1187
-#define PCI_DEVICE_ID_PLX_9030          0x9030
 #define PCI_DEVICE_ID_PLX_9050          0x9050
-#define PCI_DEVICE_ID_PLX_9060          0x9060
-#define PCI_DEVICE_ID_PLX_9060ES        0x906E
-#define PCI_DEVICE_ID_PLX_9060SD        0x906D
 #define PCI_DEVICE_ID_PLX_9080          0x9080
 #define PCI_DEVICE_ID_PLX_GTEK_SERIAL2  0xa001
 
 #define PCI_VENDOR_ID_MADGE             0x10b6
 #define PCI_DEVICE_ID_MADGE_MK2         0x0002
-#define PCI_DEVICE_ID_MADGE_C155S       0x1001
 
 #define PCI_VENDOR_ID_3COM              0x10b7
 #define PCI_DEVICE_ID_3COM_3C985        0x0001
 #define PCI_DEVICE_ID_3COM_3C940        0x1700
 #define PCI_DEVICE_ID_3COM_3C339        0x3390
 #define PCI_DEVICE_ID_3COM_3C359        0x3590
-#define PCI_DEVICE_ID_3COM_3C590        0x5900
-#define PCI_DEVICE_ID_3COM_3C595TX      0x5950
-#define PCI_DEVICE_ID_3COM_3C595T4      0x5951
-#define PCI_DEVICE_ID_3COM_3C595MII     0x5952
 #define PCI_DEVICE_ID_3COM_3C940B       0x80eb
-#define PCI_DEVICE_ID_3COM_3C900TPO     0x9000
-#define PCI_DEVICE_ID_3COM_3C900COMBO   0x9001
-#define PCI_DEVICE_ID_3COM_3C905TX      0x9050
-#define PCI_DEVICE_ID_3COM_3C905T4      0x9051
-#define PCI_DEVICE_ID_3COM_3C905B_TX    0x9055
 #define PCI_DEVICE_ID_3COM_3CR990       0x9900
 #define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902
 #define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903
@@ -1078,24 +919,11 @@
 #define PCI_DEVICE_ID_3COM_3CR990SVR97  0x9909
 #define PCI_DEVICE_ID_3COM_3CR990SVR    0x990a
 
-#define PCI_VENDOR_ID_SMC               0x10b8
-#define PCI_DEVICE_ID_SMC_EPIC100       0x0005
 
 #define PCI_VENDOR_ID_AL                0x10b9
-#define PCI_DEVICE_ID_AL_M1445          0x1445
-#define PCI_DEVICE_ID_AL_M1449          0x1449
-#define PCI_DEVICE_ID_AL_M1451          0x1451
-#define PCI_DEVICE_ID_AL_M1461          0x1461
-#define PCI_DEVICE_ID_AL_M1489          0x1489
-#define PCI_DEVICE_ID_AL_M1511          0x1511
-#define PCI_DEVICE_ID_AL_M1513          0x1513
-#define PCI_DEVICE_ID_AL_M1521          0x1521
-#define PCI_DEVICE_ID_AL_M1523          0x1523
-#define PCI_DEVICE_ID_AL_M1531          0x1531
 #define PCI_DEVICE_ID_AL_M1533          0x1533
 #define PCI_DEVICE_ID_AL_M1535          0x1535
 #define PCI_DEVICE_ID_AL_M1541          0x1541
-#define PCI_DEVICE_ID_AL_M1543          0x1543
 #define PCI_DEVICE_ID_AL_M1563          0x1563
 #define PCI_DEVICE_ID_AL_M1621          0x1621
 #define PCI_DEVICE_ID_AL_M1631          0x1631
@@ -1108,49 +936,23 @@
 #define PCI_DEVICE_ID_AL_M1681          0x1681
 #define PCI_DEVICE_ID_AL_M1683          0x1683
 #define PCI_DEVICE_ID_AL_M1689          0x1689
-#define PCI_DEVICE_ID_AL_M3307          0x3307
-#define PCI_DEVICE_ID_AL_M4803          0x5215
 #define PCI_DEVICE_ID_AL_M5219          0x5219
 #define PCI_DEVICE_ID_AL_M5228          0x5228
 #define PCI_DEVICE_ID_AL_M5229          0x5229
-#define PCI_DEVICE_ID_AL_M5237          0x5237
-#define PCI_DEVICE_ID_AL_M5243          0x5243
 #define PCI_DEVICE_ID_AL_M5451          0x5451
 #define PCI_DEVICE_ID_AL_M7101          0x7101
 
-#define PCI_VENDOR_ID_MITSUBISHI        0x10ba
 
-#define PCI_VENDOR_ID_SURECOM           0x10bd
-#define PCI_DEVICE_ID_SURECOM_NE34      0x0e34
 
 #define PCI_VENDOR_ID_NEOMAGIC          0x10c8
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV       0x0005
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS   0x0083
 #define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
 #define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
 #define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
 
-#define PCI_VENDOR_ID_ASP               0x10cd
-#define PCI_DEVICE_ID_ASP_ABP940        0x1200
-#define PCI_DEVICE_ID_ASP_ABP940U       0x1300
-#define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
-
-#define PCI_VENDOR_ID_MACRONIX          0x10d9
-#define PCI_DEVICE_ID_MACRONIX_MX98713  0x0512
-#define PCI_DEVICE_ID_MACRONIX_MX987x5  0x0531
 
 #define PCI_VENDOR_ID_TCONRAD           0x10da
 #define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
 
-#define PCI_VENDOR_ID_CERN              0x10dc
-#define PCI_DEVICE_ID_CERN_SPSB_PMC     0x0001
-#define PCI_DEVICE_ID_CERN_SPSB_PCI     0x0002
-#define PCI_DEVICE_ID_CERN_HIPPI_DST    0x0021
-#define PCI_DEVICE_ID_CERN_HIPPI_SRC    0x0022
 
 #define PCI_VENDOR_ID_NVIDIA                    0x10de
 #define PCI_DEVICE_ID_NVIDIA_TNT                0x0020
@@ -1196,7 +998,6 @@
 #define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
 #define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
 #define PCI_DEVICE_ID_NVIDIA_NFORCE3            0x00d1
-#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO         0x00da
 #define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS      0x00d4
 #define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE        0x00d5
 #define PCI_DEVICE_ID_NVIDIA_NVENET_3           0x00d6
@@ -1283,7 +1084,6 @@
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2 0x037F
 #define PCI_DEVICE_ID_NVIDIA_NVENET_12          0x0268
 #define PCI_DEVICE_ID_NVIDIA_NVENET_13          0x0269
-#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO        0x026B
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800   0x0280
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
@@ -1334,24 +1134,13 @@
 #define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
 
 #define PCI_VENDOR_ID_IMS               0x10e0
-#define PCI_DEVICE_ID_IMS_8849          0x8849
 #define PCI_DEVICE_ID_IMS_TT128         0x9128
 #define PCI_DEVICE_ID_IMS_TT3D          0x9135
 
-#define PCI_VENDOR_ID_TEKRAM2           0x10e1
-#define PCI_DEVICE_ID_TEKRAM2_690c      0x690c
 
-#define PCI_VENDOR_ID_TUNDRA            0x10e3
-#define PCI_DEVICE_ID_TUNDRA_CA91C042   0x0000
 
-#define PCI_VENDOR_ID_AMCC              0x10e8
-#define PCI_DEVICE_ID_AMCC_MYRINET      0x8043
-#define PCI_DEVICE_ID_AMCC_PARASTATION  0x8062
-#define PCI_DEVICE_ID_AMCC_S5933        0x807d
-#define PCI_DEVICE_ID_AMCC_S5933_HEPC3  0x809c
 
 #define PCI_VENDOR_ID_INTERG            0x10ea
-#define PCI_DEVICE_ID_INTERG_1680       0x1680
 #define PCI_DEVICE_ID_INTERG_1682       0x1682
 #define PCI_DEVICE_ID_INTERG_2000       0x2000
 #define PCI_DEVICE_ID_INTERG_2010       0x2010
@@ -1359,32 +1148,23 @@
 #define PCI_DEVICE_ID_INTERG_5050       0x5050
 
 #define PCI_VENDOR_ID_REALTEK           0x10ec
-#define PCI_DEVICE_ID_REALTEK_8029      0x8029
-#define PCI_DEVICE_ID_REALTEK_8129      0x8129
 #define PCI_DEVICE_ID_REALTEK_8139      0x8139
-#define PCI_DEVICE_ID_REALTEK_8169      0x8169
 
 #define PCI_VENDOR_ID_XILINX            0x10ee
 #define PCI_DEVICE_ID_RME_DIGI96        0x3fc0
 #define PCI_DEVICE_ID_RME_DIGI96_8      0x3fc1
 #define PCI_DEVICE_ID_RME_DIGI96_8_PRO  0x3fc2
 #define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
-#define PCI_DEVICE_ID_XILINX_HAMMERFALL 0x3fc4
 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
-#define PCI_DEVICE_ID_TURBOPAM          0x4020
 
-#define PCI_VENDOR_ID_TRUEVISION        0x10fa
-#define PCI_DEVICE_ID_TRUEVISION_T1000  0x000c
 
 #define PCI_VENDOR_ID_INIT              0x1101
-#define PCI_DEVICE_ID_INIT_320P         0x9100
-#define PCI_DEVICE_ID_INIT_360P         0x9500
 
-#define PCI_VENDOR_ID_CREATIVE          0x1102 // duplicate: ECTIVA
+#define PCI_VENDOR_ID_CREATIVE          0x1102 /* duplicate: ECTIVA */
 #define PCI_DEVICE_ID_CREATIVE_EMU10K1  0x0002
 
-#define PCI_VENDOR_ID_ECTIVA            0x1102 // duplicate: CREATIVE
+#define PCI_VENDOR_ID_ECTIVA            0x1102 /* duplicate: CREATIVE */
 #define PCI_DEVICE_ID_ECTIVA_EV1938     0x8938
 
 #define PCI_VENDOR_ID_TTI               0x1103
@@ -1394,7 +1174,7 @@
 #define PCI_DEVICE_ID_TTI_HPT302        0x0006
 #define PCI_DEVICE_ID_TTI_HPT371        0x0007
 #define PCI_DEVICE_ID_TTI_HPT374        0x0008
-#define PCI_DEVICE_ID_TTI_HPT372N       0x0009  // apparently a 372N variant?
+#define PCI_DEVICE_ID_TTI_HPT372N       0x0009  /* apparently a 372N variant? */
 
 #define PCI_VENDOR_ID_VIA               0x1106
 #define PCI_DEVICE_ID_VIA_8763_0        0x0198
@@ -1407,36 +1187,25 @@
 #define PCI_DEVICE_ID_VIA_8363_0        0x0305
 #define PCI_DEVICE_ID_VIA_8371_0        0x0391
 #define PCI_DEVICE_ID_VIA_8501_0        0x0501
-#define PCI_DEVICE_ID_VIA_82C505        0x0505
 #define PCI_DEVICE_ID_VIA_82C561        0x0561
 #define PCI_DEVICE_ID_VIA_82C586_1      0x0571
 #define PCI_DEVICE_ID_VIA_82C576        0x0576
-#define PCI_DEVICE_ID_VIA_82C585        0x0585
 #define PCI_DEVICE_ID_VIA_82C586_0      0x0586
-#define PCI_DEVICE_ID_VIA_82C595        0x0595
 #define PCI_DEVICE_ID_VIA_82C596        0x0596
 #define PCI_DEVICE_ID_VIA_82C597_0      0x0597
 #define PCI_DEVICE_ID_VIA_82C598_0      0x0598
 #define PCI_DEVICE_ID_VIA_8601_0        0x0601
 #define PCI_DEVICE_ID_VIA_8605_0        0x0605
-#define PCI_DEVICE_ID_VIA_82C680        0x0680
 #define PCI_DEVICE_ID_VIA_82C686        0x0686
 #define PCI_DEVICE_ID_VIA_82C691_0      0x0691
-#define PCI_DEVICE_ID_VIA_82C693        0x0693
-#define PCI_DEVICE_ID_VIA_82C693_1      0x0698
-#define PCI_DEVICE_ID_VIA_82C926        0x0926
 #define PCI_DEVICE_ID_VIA_82C576_1      0x1571
-#define PCI_DEVICE_ID_VIA_82C595_97     0x1595
 #define PCI_DEVICE_ID_VIA_82C586_2      0x3038
 #define PCI_DEVICE_ID_VIA_82C586_3      0x3040
-#define PCI_DEVICE_ID_VIA_6305          0x3044
 #define PCI_DEVICE_ID_VIA_82C596_3      0x3050
 #define PCI_DEVICE_ID_VIA_82C596B_3     0x3051
 #define PCI_DEVICE_ID_VIA_82C686_4      0x3057
 #define PCI_DEVICE_ID_VIA_82C686_5      0x3058
 #define PCI_DEVICE_ID_VIA_8233_5        0x3059
-#define PCI_DEVICE_ID_VIA_8233_7        0x3065
-#define PCI_DEVICE_ID_VIA_82C686_6      0x3068
 #define PCI_DEVICE_ID_VIA_8233_0        0x3074
 #define PCI_DEVICE_ID_VIA_8633_0        0x3091
 #define PCI_DEVICE_ID_VIA_8367_0        0x3099
@@ -1454,38 +1223,23 @@
 #define PCI_DEVICE_ID_VIA_XN266         0x3156
 #define PCI_DEVICE_ID_VIA_8754C_0       0x3168
 #define PCI_DEVICE_ID_VIA_8235          0x3177
-#define PCI_DEVICE_ID_VIA_P4N333        0x3178
 #define PCI_DEVICE_ID_VIA_8385_0        0x3188
 #define PCI_DEVICE_ID_VIA_8377_0        0x3189
 #define PCI_DEVICE_ID_VIA_8378_0        0x3205
 #define PCI_DEVICE_ID_VIA_8783_0        0x3208
-#define PCI_DEVICE_ID_VIA_P4M400        0x3209
 #define PCI_DEVICE_ID_VIA_8237          0x3227
 #define PCI_DEVICE_ID_VIA_3296_0        0x0296
-#define PCI_DEVICE_ID_VIA_86C100A       0x6100
 #define PCI_DEVICE_ID_VIA_8231          0x8231
 #define PCI_DEVICE_ID_VIA_8231_4        0x8235
 #define PCI_DEVICE_ID_VIA_8365_1        0x8305
 #define PCI_DEVICE_ID_VIA_8371_1        0x8391
-#define PCI_DEVICE_ID_VIA_8501_1        0x8501
-#define PCI_DEVICE_ID_VIA_82C597_1      0x8597
 #define PCI_DEVICE_ID_VIA_82C598_1      0x8598
-#define PCI_DEVICE_ID_VIA_8601_1        0x8601
-#define PCI_DEVICE_ID_VIA_8505_1        0x8605
-#define PCI_DEVICE_ID_VIA_8633_1        0xB091
-#define PCI_DEVICE_ID_VIA_8367_1        0xB099
-#define PCI_DEVICE_ID_VIA_P4X266_1      0xB101
-#define PCI_DEVICE_ID_VIA_8615_1        0xB103
-#define PCI_DEVICE_ID_VIA_8361_1        0xB112
-#define PCI_DEVICE_ID_VIA_8235_1        0xB168
 #define PCI_DEVICE_ID_VIA_838X_1        0xB188
 #define PCI_DEVICE_ID_VIA_83_87XX_1     0xB198
 
 #define PCI_VENDOR_ID_SIEMENS           0x110A
 #define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
 
-#define PCI_VENDOR_ID_SMC2              0x1113
-#define PCI_DEVICE_ID_SMC2_1211TX       0x1211
 
 #define PCI_VENDOR_ID_VORTEX            0x1119
 #define PCI_DEVICE_ID_VORTEX_GDT60x0    0x0000
@@ -1508,18 +1262,6 @@
 #define PCI_DEVICE_ID_VORTEX_GDT6557RP  0x0103
 #define PCI_DEVICE_ID_VORTEX_GDT6x11RP  0x0104
 #define PCI_DEVICE_ID_VORTEX_GDT6x21RP  0x0105
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125
 
 #define PCI_VENDOR_ID_EF                0x111a
 #define PCI_DEVICE_ID_EF_ATM_FPGA       0x0000
@@ -1531,21 +1273,15 @@
 #define PCI_DEVICE_ID_IDT_IDT77201      0x0001
 
 #define PCI_VENDOR_ID_FORE              0x1127
-#define PCI_DEVICE_ID_FORE_PCA200PC     0x0210
 #define PCI_DEVICE_ID_FORE_PCA200E      0x0300
 
-#define PCI_VENDOR_ID_IMAGINGTECH       0x112f
-#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000
 
 #define PCI_VENDOR_ID_PHILIPS           0x1131
-#define PCI_DEVICE_ID_PHILIPS_SAA7145   0x7145
 #define PCI_DEVICE_ID_PHILIPS_SAA7146   0x7146
 #define PCI_DEVICE_ID_PHILIPS_SAA9730   0x9730
 
 #define PCI_VENDOR_ID_EICON             0x1133
-#define PCI_DEVICE_ID_EICON_DIVA20PRO   0xe001
 #define PCI_DEVICE_ID_EICON_DIVA20      0xe002
-#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
 #define PCI_DEVICE_ID_EICON_DIVA20_U    0xe004
 #define PCI_DEVICE_ID_EICON_DIVA201     0xe005
 #define PCI_DEVICE_ID_EICON_DIVA202     0xe00b
@@ -1557,35 +1293,17 @@
 #define PCI_VENDOR_ID_ZIATECH           0x1138
 #define PCI_DEVICE_ID_ZIATECH_5550_HC   0x5550
  
-#define PCI_VENDOR_ID_CYCLONE           0x113c
-#define PCI_DEVICE_ID_CYCLONE_SDK       0x0001
 
-#define PCI_VENDOR_ID_ALLIANCE          0x1142
-#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210
-#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422
-#define PCI_DEVICE_ID_ALLIANCE_AT24     0x6424
-#define PCI_DEVICE_ID_ALLIANCE_AT3D     0x643d
 
 #define PCI_VENDOR_ID_SYSKONNECT        0x1148
-#define PCI_DEVICE_ID_SYSKONNECT_FP     0x4000
 #define PCI_DEVICE_ID_SYSKONNECT_TR     0x4200
 #define PCI_DEVICE_ID_SYSKONNECT_GE     0x4300
 #define PCI_DEVICE_ID_SYSKONNECT_YU     0x4320
 #define PCI_DEVICE_ID_SYSKONNECT_9DXX   0x4400
 #define PCI_DEVICE_ID_SYSKONNECT_9MXX   0x4500
 
-#define PCI_VENDOR_ID_VMIC              0x114a
-#define PCI_DEVICE_ID_VMIC_VME          0x7587
 
 #define PCI_VENDOR_ID_DIGI              0x114f
-#define PCI_DEVICE_ID_DIGI_EPC          0x0002
-#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH  0x0003
-#define PCI_DEVICE_ID_DIGI_XEM          0x0004
-#define PCI_DEVICE_ID_DIGI_XR           0x0005
-#define PCI_DEVICE_ID_DIGI_CX           0x0006
-#define PCI_DEVICE_ID_DIGI_XRJ          0x0009
-#define PCI_DEVICE_ID_DIGI_EPCJ         0x000a
-#define PCI_DEVICE_ID_DIGI_XR_920       0x0027
 #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E  0x0070
 #define PCI_DEVICE_ID_DIGI_DF_M_E       0x0071
 #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A  0x0072
@@ -1595,23 +1313,15 @@
 #define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
 #define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
 
-#define PCI_VENDOR_ID_MUTECH            0x1159
-#define PCI_DEVICE_ID_MUTECH_MV1000     0x0001
 
 #define PCI_VENDOR_ID_XIRCOM            0x115d
-#define PCI_DEVICE_ID_XIRCOM_X3201_ETH  0x0003
 #define PCI_DEVICE_ID_XIRCOM_RBM56G     0x0101
 #define PCI_DEVICE_ID_XIRCOM_X3201_MDM  0x0103
 
-#define PCI_VENDOR_ID_RENDITION         0x1163
-#define PCI_DEVICE_ID_RENDITION_VERITE  0x0001
-#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
 
 #define PCI_VENDOR_ID_SERVERWORKS         0x1166
 #define PCI_DEVICE_ID_SERVERWORKS_HE      0x0008
 #define PCI_DEVICE_ID_SERVERWORKS_LE      0x0009
-#define PCI_DEVICE_ID_SERVERWORKS_CIOB30  0x0010
-#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011
 #define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
 #define PCI_DEVICE_ID_SERVERWORKS_OSB4    0x0200
 #define PCI_DEVICE_ID_SERVERWORKS_CSB5    0x0201
@@ -1621,13 +1331,7 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
 #define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
-#define PCI_DEVICE_ID_SERVERWORKS_GCLE    0x0225
-#define PCI_DEVICE_ID_SERVERWORKS_GCLE2   0x0227
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
 
 #define PCI_VENDOR_ID_SBE               0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100      0x0301
@@ -1638,17 +1342,12 @@
 #define PCI_DEVICE_ID_TOSHIBA_PICCOLO   0x0102
 #define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0103
 #define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0105
-#define PCI_DEVICE_ID_TOSHIBA_601       0x0601
 #define PCI_DEVICE_ID_TOSHIBA_TOPIC95   0x060a
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_A 0x0603
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_B 0x060a
 #define PCI_DEVICE_ID_TOSHIBA_TOPIC97   0x060f
 #define PCI_DEVICE_ID_TOSHIBA_TOPIC100  0x0617
 
 #define PCI_VENDOR_ID_TOSHIBA_2         0x102f
-#define PCI_DEVICE_ID_TOSHIBA_TX3927    0x000a
 #define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
-#define PCI_DEVICE_ID_TOSHIBA_TX4927    0x0180
 #define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC     0x0108
 #define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
 
@@ -1663,7 +1362,6 @@
 #define PCI_DEVICE_ID_DLINK_DGE510T     0x4c00
 
 #define PCI_VENDOR_ID_ARTOP             0x1191
-#define PCI_DEVICE_ID_ARTOP_ATP8400     0x0004
 #define PCI_DEVICE_ID_ARTOP_ATP850UF    0x0005
 #define PCI_DEVICE_ID_ARTOP_ATP860      0x0006
 #define PCI_DEVICE_ID_ARTOP_ATP860R     0x0007
@@ -1676,16 +1374,11 @@
 #define PCI_DEVICE_ID_ARTOP_AEC7612D    0x8040
 #define PCI_DEVICE_ID_ARTOP_AEC7612SUW  0x8050
 #define PCI_DEVICE_ID_ARTOP_8060        0x8060
-#define PCI_DEVICE_ID_ARTOP_AEC67160    0x8080
-#define PCI_DEVICE_ID_ARTOP_AEC67160_2  0x8081
-#define PCI_DEVICE_ID_ARTOP_AEC67162    0x808a
 
 #define PCI_VENDOR_ID_ZEITNET           0x1193
 #define PCI_DEVICE_ID_ZEITNET_1221      0x0001
 #define PCI_DEVICE_ID_ZEITNET_1225      0x0002
 
-#define PCI_VENDOR_ID_OMEGA             0x119b
-#define PCI_DEVICE_ID_OMEGA_82C092G     0x1221
 
 #define PCI_VENDOR_ID_FUJITSU_ME        0x119e
 #define PCI_DEVICE_ID_FUJITSU_FS155     0x0001
@@ -1695,61 +1388,41 @@
 #define PCI_SUBDEVICE_ID_KEYSPAN_SX2    0x5334
 
 #define PCI_VENDOR_ID_MARVELL           0x11ab
-#define PCI_DEVICE_ID_MARVELL_GT64011   0x4146
-#define PCI_DEVICE_ID_MARVELL_GT64111   0x4146
 #define PCI_DEVICE_ID_MARVELL_GT64260   0x6430
 #define PCI_DEVICE_ID_MARVELL_MV64360   0x6460
 #define PCI_DEVICE_ID_MARVELL_MV64460   0x6480
 #define PCI_DEVICE_ID_MARVELL_GT96100   0x9652
 #define PCI_DEVICE_ID_MARVELL_GT96100A  0x9653
 
-#define PCI_VENDOR_ID_LITEON            0x11ad
-#define PCI_DEVICE_ID_LITEON_LNE100TX   0x0002
 
 #define PCI_VENDOR_ID_V3                0x11b0
 #define PCI_DEVICE_ID_V3_V960           0x0001
-#define PCI_DEVICE_ID_V3_V350           0x0001
-#define PCI_DEVICE_ID_V3_V961           0x0002
 #define PCI_DEVICE_ID_V3_V351           0x0002
 
-#define PCI_VENDOR_ID_NP                0x11bc
-#define PCI_DEVICE_ID_NP_PCI_FDDI       0x0001
 
 #define PCI_VENDOR_ID_ATT               0x11c1
-#define PCI_DEVICE_ID_ATT_L56XMF        0x0440
 #define PCI_DEVICE_ID_ATT_VENUS_MODEM   0x480
 
-#define PCI_VENDOR_ID_NEC2              0x11c3 /* NEC (2nd) */
 
 #define PCI_VENDOR_ID_SPECIALIX         0x11cb
 #define PCI_DEVICE_ID_SPECIALIX_IO8     0x2000
-#define PCI_DEVICE_ID_SPECIALIX_XIO     0x4000
 #define PCI_DEVICE_ID_SPECIALIX_RIO     0x8000
 #define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
 
-#define PCI_VENDOR_ID_AURAVISION        0x11d1
-#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7
 
 #define PCI_VENDOR_ID_ANALOG_DEVICES    0x11d4
 #define PCI_DEVICE_ID_AD1889JS          0x1889
 
-#define PCI_VENDOR_ID_IKON              0x11d5
-#define PCI_DEVICE_ID_IKON_10115        0x0115
-#define PCI_DEVICE_ID_IKON_10117        0x0117
 
-#define PCI_VENDOR_ID_SEGA              0x11db
 #define PCI_DEVICE_ID_SEGA_BBA          0x1234
 
 #define PCI_VENDOR_ID_ZORAN             0x11de
 #define PCI_DEVICE_ID_ZORAN_36057       0x6057
 #define PCI_DEVICE_ID_ZORAN_36120       0x6120
 
-#define PCI_VENDOR_ID_KINETIC           0x11f4
-#define PCI_DEVICE_ID_KINETIC_2915      0x2915
 
 #define PCI_VENDOR_ID_COMPEX            0x11f6
 #define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
-#define PCI_DEVICE_ID_COMPEX_RL2000     0x1401
 
 #define PCI_VENDOR_ID_RP                0x11fe
 #define PCI_DEVICE_ID_RP32INTF          0x0001
@@ -1763,7 +1436,6 @@
 #define PCI_DEVICE_ID_RP16SNI           0x0009  
 #define PCI_DEVICE_ID_RPP4              0x000A
 #define PCI_DEVICE_ID_RPP8              0x000B
-#define PCI_DEVICE_ID_RP8M              0x000C
 #define PCI_DEVICE_ID_RP4M              0x000D
 #define PCI_DEVICE_ID_RP2_232           0x000E
 #define PCI_DEVICE_ID_RP2_422           0x000F
@@ -1791,10 +1463,6 @@
 #define PCI_DEVICE_ID_PC300_TE_M_2      0x0320
 #define PCI_DEVICE_ID_PC300_TE_M_1      0x0321
 
-/* Allied Telesyn */
-#define PCI_VENDOR_ID_AT                0x1259
-#define PCI_SUBDEVICE_ID_AT_2701FX      0x2703
-
 #define PCI_VENDOR_ID_ESSENTIAL         0x120f
 #define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER      0x0001
 
@@ -1811,10 +1479,7 @@
 #define PCI_DEVICE_ID_3DFX_VOODOO3      0x0005
 #define PCI_DEVICE_ID_3DFX_VOODOO5      0x0009
 
-#define PCI_VENDOR_ID_SIGMADES          0x1236
-#define PCI_DEVICE_ID_SIGMADES_6425     0x6401
 
-#define PCI_VENDOR_ID_CCUBE             0x123f
 
 #define PCI_VENDOR_ID_AVM               0x1244
 #define PCI_DEVICE_ID_AVM_B1            0x0700
@@ -1824,19 +1489,8 @@
 #define PCI_DEVICE_ID_AVM_C2            0x1100
 #define PCI_DEVICE_ID_AVM_T1            0x1200
 
-#define PCI_VENDOR_ID_DIPIX             0x1246
 
 #define PCI_VENDOR_ID_STALLION          0x124d
-#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
-#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
-#define PCI_DEVICE_ID_STALLION_EIOPCI   0x0003
-
-#define PCI_VENDOR_ID_OPTIBASE          0x1255
-#define PCI_DEVICE_ID_OPTIBASE_FORGE    0x1110
-#define PCI_DEVICE_ID_OPTIBASE_FUSION   0x1210
-#define PCI_DEVICE_ID_OPTIBASE_VPLEX    0x2110
-#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC  0x2120
-#define PCI_DEVICE_ID_OPTIBASE_VQUEST   0x2130
 
 /* Allied Telesyn */
 #define PCI_VENDOR_ID_AT                0x1259
@@ -1845,7 +1499,6 @@
 
 #define PCI_VENDOR_ID_ESS               0x125d
 #define PCI_DEVICE_ID_ESS_ESS1968       0x1968
-#define PCI_DEVICE_ID_ESS_AUDIOPCI      0x1969
 #define PCI_DEVICE_ID_ESS_ESS1978       0x1978
 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
@@ -1858,11 +1511,7 @@
 
 #define PCI_VENDOR_ID_SATSAGEM          0x1267
 #define PCI_DEVICE_ID_SATSAGEM_NICCY    0x1016
-#define PCI_DEVICE_ID_SATSAGEM_PCR2101  0x5352
-#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
 
-#define PCI_VENDOR_ID_HUGHES            0x1273
-#define PCI_DEVICE_ID_HUGHES_DIRECPC    0x0002
 
 #define PCI_VENDOR_ID_ENSONIQ           0x1274
 #define PCI_DEVICE_ID_ENSONIQ_CT5880    0x5880
@@ -1883,13 +1532,10 @@
 #define PCI_DEVICE_ID_ITE_IT8330G_0     0xe886
 
 /* formerly Platform Tech */
-#define PCI_VENDOR_ID_ESS_OLD           0x1285
 #define PCI_DEVICE_ID_ESS_ESS0100       0x0100
 
 #define PCI_VENDOR_ID_ALTEON            0x12ae
-#define PCI_DEVICE_ID_ALTEON_ACENIC     0x0001
 
-#define PCI_VENDOR_ID_USR               0x12B9
 
 #define PCI_SUBVENDOR_ID_CONNECT_TECH                   0x12c4
 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232           0x0001
@@ -1904,8 +1550,6 @@
 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1        0x000A
 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1        0x000B
 
-#define PCI_VENDOR_ID_PICTUREL          0x12c5
-#define PCI_DEVICE_ID_PICTUREL_PCIVST   0x0081
 
 #define PCI_VENDOR_ID_NVIDIA_SGS        0x12d2
 #define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
@@ -1927,8 +1571,6 @@
 #define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
 #define PCI_DEVICE_ID_LML_33R10         0x8a02
 
-#define PCI_VENDOR_ID_CBOARDS           0x1307
-#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
 
 #define PCI_VENDOR_ID_SIIG              0x131f
 #define PCI_SUBVENDOR_ID_SIIG           0x131f
@@ -1972,7 +1614,6 @@
 #define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL    0x2050
 
 #define PCI_VENDOR_ID_RADISYS           0x1331
-#define PCI_DEVICE_ID_RADISYS_ENP2611   0x0030
 
 #define PCI_VENDOR_ID_DOMEX             0x134a
 #define PCI_DEVICE_ID_DOMEX_DMX3191D    0x0001
@@ -1980,8 +1621,6 @@
 #define PCI_VENDOR_ID_QUATECH           0x135C
 #define PCI_DEVICE_ID_QUATECH_QSC100    0x0010
 #define PCI_DEVICE_ID_QUATECH_DSC100    0x0020
-#define PCI_DEVICE_ID_QUATECH_DSC200    0x0030
-#define PCI_DEVICE_ID_QUATECH_QSC200    0x0040
 #define PCI_DEVICE_ID_QUATECH_ESC100D   0x0050
 #define PCI_DEVICE_ID_QUATECH_ESC100M   0x0060
 
@@ -2000,7 +1639,6 @@
 #define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO         0x0106
 #define PCI_SUBDEVICE_ID_HYPERCOPE_METRO        0x0107
 #define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2       0x0108
-#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS       0x0109
 
 #define PCI_VENDOR_ID_KAWASAKI          0x136b
 #define PCI_DEVICE_ID_MCHIP_KL5A72002   0xff01
@@ -2014,12 +1652,9 @@
 #define PCI_DEVICE_ID_LMC_SSI           0x0005
 #define PCI_DEVICE_ID_LMC_T1            0x0006
 
-#define PCI_VENDOR_ID_MARIAN            0x1382
-#define PCI_DEVICE_ID_MARIAN_PRODIF_PLUS 0x2048
 
 #define PCI_VENDOR_ID_NETGEAR           0x1385
 #define PCI_DEVICE_ID_NETGEAR_GA620     0x620a
-#define PCI_DEVICE_ID_NETGEAR_GA622     0x622a
 
 #define PCI_VENDOR_ID_APPLICOM          0x1389
 #define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
@@ -2042,9 +1677,6 @@
 #define PCI_DEVICE_ID_MOXA_CP134U       0x1340
 #define PCI_DEVICE_ID_MOXA_C168         0x1680
 #define PCI_DEVICE_ID_MOXA_CP168U       0x1681
-#define PCI_DEVICE_ID_MOXA_CP204J       0x2040
-#define PCI_DEVICE_ID_MOXA_C218         0x2180
-#define PCI_DEVICE_ID_MOXA_C320         0x3200
 
 #define PCI_VENDOR_ID_CCD               0x1397
 #define PCI_DEVICE_ID_CCD_2BD0          0x2bd0
@@ -2065,9 +1697,7 @@
 
 #define PCI_VENDOR_ID_MICROGATE         0x13c0
 #define PCI_DEVICE_ID_MICROGATE_USC     0x0010
-#define PCI_DEVICE_ID_MICROGATE_SCC     0x0020
 #define PCI_DEVICE_ID_MICROGATE_SCA     0x0030
-#define PCI_DEVICE_ID_MICROGATE_USC2    0x0210
 
 #define PCI_VENDOR_ID_3WARE             0x13C1
 #define PCI_DEVICE_ID_3WARE_1000        0x1000
@@ -2118,10 +1748,6 @@
 
 #define PCI_VENDOR_ID_SAMSUNG           0x144d
 
-#define PCI_VENDOR_ID_AIRONET           0x14b9
-#define PCI_DEVICE_ID_AIRONET_4800_1    0x0001
-#define PCI_DEVICE_ID_AIRONET_4800      0x4500 // values switched?  see
-#define PCI_DEVICE_ID_AIRONET_4500      0x4800 // drivers/net/aironet4500_card.c
 
 #define PCI_VENDOR_ID_TITAN             0x14D2
 #define PCI_DEVICE_ID_TITAN_010L        0x8001
@@ -2140,8 +1766,6 @@
 #define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
 #define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
 
-#define PCI_VENDOR_ID_SIPACKETS         0x14d9
-#define PCI_DEVICE_ID_SP_HT             0x0010
 
 #define PCI_VENDOR_ID_AFAVLAB           0x14db
 #define PCI_DEVICE_ID_AFAVLAB_P028      0x2180
@@ -2164,11 +1788,13 @@
 #define PCI_DEVICE_ID_TIGON3_5721       0x1659
 #define PCI_DEVICE_ID_TIGON3_5705M      0x165d
 #define PCI_DEVICE_ID_TIGON3_5705M_2    0x165e
+#define PCI_DEVICE_ID_TIGON3_5714       0x1668
 #define PCI_DEVICE_ID_TIGON3_5780       0x166a
 #define PCI_DEVICE_ID_TIGON3_5780S      0x166b
 #define PCI_DEVICE_ID_TIGON3_5705F      0x166e
 #define PCI_DEVICE_ID_TIGON3_5750       0x1676
 #define PCI_DEVICE_ID_TIGON3_5751       0x1677
+#define PCI_DEVICE_ID_TIGON3_5715       0x1678
 #define PCI_DEVICE_ID_TIGON3_5750M      0x167c
 #define PCI_DEVICE_ID_TIGON3_5751M      0x167d
 #define PCI_DEVICE_ID_TIGON3_5751F      0x167e
@@ -2206,8 +1832,6 @@
 
 #define PCI_VENDOR_ID_CHELSIO           0x1425
 
-#define PCI_VENDOR_ID_MIPS              0x153f
-#define PCI_DEVICE_ID_SOC_IT            0x0001
 
 #define PCI_VENDOR_ID_SYBA              0x1592
 #define PCI_DEVICE_ID_SYBA_2P_EPP       0x0782
@@ -2227,15 +1851,7 @@
 #define PCI_DEVICE_ID_MELLANOX_SINAI    0x6274
 
 #define PCI_VENDOR_ID_PDC               0x15e9
-#define PCI_DEVICE_ID_PDC_1841          0x1841
 
-#define PCI_VENDOR_ID_MACROLINK         0x15ed
-#define PCI_DEVICE_ID_MACROLINK_MCCS8   0x1000
-#define PCI_DEVICE_ID_MACROLINK_MCCS    0x1001
-#define PCI_DEVICE_ID_MACROLINK_MCCS8H  0x1002
-#define PCI_DEVICE_ID_MACROLINK_MCCSH   0x1003
-#define PCI_DEVICE_ID_MACROLINK_MCCR8   0x2000
-#define PCI_DEVICE_ID_MACROLINK_MCCR    0x2001
 
 #define PCI_VENDOR_ID_FARSITE           0x1619
 #define PCI_DEVICE_ID_FARSITE_T2P       0x0400
@@ -2253,7 +1869,6 @@
 #define PCI_DEVICE_ID_REVOLUTION        0x0044
 
 #define PCI_VENDOR_ID_LINKSYS           0x1737
-#define PCI_DEVICE_ID_LINKSYS_EG1032    0x1032
 #define PCI_DEVICE_ID_LINKSYS_EG1064    0x1064
 
 #define PCI_VENDOR_ID_ALTIMA            0x173b
@@ -2268,7 +1883,6 @@
 #define PCI_DEVICE_ID_HERC_WIN          0x5732
 #define PCI_DEVICE_ID_HERC_UNI          0x5832
 
-#define PCI_VENDOR_ID_INFINICON         0x1820
 
 #define PCI_VENDOR_ID_SITECOM           0x182d
 #define PCI_DEVICE_ID_SITECOM_DC105V2   0x3069
@@ -2278,8 +1892,6 @@
 #define PCI_VENDOR_ID_TDI               0x192E
 #define PCI_DEVICE_ID_TDI_EHCI          0x0101
 
-#define PCI_VENDOR_ID_SYMPHONY          0x1c1c
-#define PCI_DEVICE_ID_SYMPHONY_101      0x0001
 
 #define PCI_VENDOR_ID_TEKRAM            0x1de1
 #define PCI_DEVICE_ID_TEKRAM_DC290      0xdc29
@@ -2288,70 +1900,33 @@
 #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
 
 #define PCI_VENDOR_ID_3DLABS            0x3d3d
-#define PCI_DEVICE_ID_3DLABS_300SX      0x0001
-#define PCI_DEVICE_ID_3DLABS_500TX      0x0002
-#define PCI_DEVICE_ID_3DLABS_DELTA      0x0003
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA   0x0004
-#define PCI_DEVICE_ID_3DLABS_MX         0x0006
 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2  0x0007
-#define PCI_DEVICE_ID_3DLABS_GAMMA      0x0008
 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
 
-#define PCI_VENDOR_ID_AVANCE            0x4005
-#define PCI_DEVICE_ID_AVANCE_ALG2064    0x2064
-#define PCI_DEVICE_ID_AVANCE_2302       0x2302
 
 #define PCI_VENDOR_ID_AKS               0x416c
 #define PCI_DEVICE_ID_AKS_ALADDINCARD   0x0100
-#define PCI_DEVICE_ID_AKS_CPC           0x0200
 
-#define PCI_VENDOR_ID_REDCREEK          0x4916
-#define PCI_DEVICE_ID_RC45              0x1960
 
-#define PCI_VENDOR_ID_NETVIN            0x4a14
-#define PCI_DEVICE_ID_NETVIN_NV5000SC   0x5000
 
 #define PCI_VENDOR_ID_S3                0x5333
-#define PCI_DEVICE_ID_S3_PLATO_PXS      0x0551
-#define PCI_DEVICE_ID_S3_ViRGE          0x5631
 #define PCI_DEVICE_ID_S3_TRIO           0x8811
-#define PCI_DEVICE_ID_S3_AURORA64VP     0x8812
-#define PCI_DEVICE_ID_S3_TRIO64UVP      0x8814
-#define PCI_DEVICE_ID_S3_ViRGE_VX       0x883d
 #define PCI_DEVICE_ID_S3_868            0x8880
-#define PCI_DEVICE_ID_S3_928            0x88b0
-#define PCI_DEVICE_ID_S3_864_1          0x88c0
-#define PCI_DEVICE_ID_S3_864_2          0x88c1
-#define PCI_DEVICE_ID_S3_964_1          0x88d0
-#define PCI_DEVICE_ID_S3_964_2          0x88d1
 #define PCI_DEVICE_ID_S3_968            0x88f0
-#define PCI_DEVICE_ID_S3_TRIO64V2       0x8901
-#define PCI_DEVICE_ID_S3_PLATO_PXG      0x8902
-#define PCI_DEVICE_ID_S3_ViRGE_DXGX     0x8a01
-#define PCI_DEVICE_ID_S3_ViRGE_GX2      0x8a10
 #define PCI_DEVICE_ID_S3_SAVAGE4        0x8a25
-#define PCI_DEVICE_ID_S3_ViRGE_MX       0x8c01
-#define PCI_DEVICE_ID_S3_ViRGE_MXP      0x8c02
-#define PCI_DEVICE_ID_S3_ViRGE_MXPMV    0x8c03
 #define PCI_DEVICE_ID_S3_PROSAVAGE8     0x8d04
 #define PCI_DEVICE_ID_S3_SONICVIBES     0xca00
 
 #define PCI_VENDOR_ID_DUNORD            0x5544
 #define PCI_DEVICE_ID_DUNORD_I3000      0x0001
 
+
 #define PCI_VENDOR_ID_DCI               0x6666
 #define PCI_DEVICE_ID_DCI_PCCOM4        0x0001
 #define PCI_DEVICE_ID_DCI_PCCOM8        0x0002
 
-#define PCI_VENDOR_ID_DUNORD            0x5544
-#define PCI_DEVICE_ID_DUNORD_I3000      0x0001
-
-#define PCI_VENDOR_ID_GENROCO           0x5555
-#define PCI_DEVICE_ID_GENROCO_HFP832    0x0003
-
 #define PCI_VENDOR_ID_INTEL             0x8086
 #define PCI_DEVICE_ID_INTEL_EESSC       0x0008
-#define PCI_DEVICE_ID_INTEL_21145       0x0039
 #define PCI_DEVICE_ID_INTEL_PXHD_0      0x0320
 #define PCI_DEVICE_ID_INTEL_PXHD_1      0x0321
 #define PCI_DEVICE_ID_INTEL_PXH_0       0x0329
@@ -2360,30 +1935,17 @@
 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 #define PCI_DEVICE_ID_INTEL_82378       0x0484
-#define PCI_DEVICE_ID_INTEL_82430       0x0486
-#define PCI_DEVICE_ID_INTEL_82434       0x04a3
 #define PCI_DEVICE_ID_INTEL_I960        0x0960
 #define PCI_DEVICE_ID_INTEL_I960RM      0x0962
-#define PCI_DEVICE_ID_INTEL_82562ET     0x1031
-#define PCI_DEVICE_ID_INTEL_82801CAM    0x1038
 #define PCI_DEVICE_ID_INTEL_82815_MC    0x1130
-#define PCI_DEVICE_ID_INTEL_82815_AB    0x1131
 #define PCI_DEVICE_ID_INTEL_82815_CGC   0x1132
-#define PCI_DEVICE_ID_INTEL_82559ER     0x1209
 #define PCI_DEVICE_ID_INTEL_82092AA_0   0x1221
-#define PCI_DEVICE_ID_INTEL_82092AA_1   0x1222
-#define PCI_DEVICE_ID_INTEL_7116        0x1223
 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550  
-#define PCI_DEVICE_ID_INTEL_7505_1      0x2552  
 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
-#define PCI_DEVICE_ID_INTEL_82596       0x1226
-#define PCI_DEVICE_ID_INTEL_82865       0x1227
-#define PCI_DEVICE_ID_INTEL_82557       0x1229
 #define PCI_DEVICE_ID_INTEL_82437       0x122d
 #define PCI_DEVICE_ID_INTEL_82371FB_0   0x122e
 #define PCI_DEVICE_ID_INTEL_82371FB_1   0x1230
 #define PCI_DEVICE_ID_INTEL_82371MX     0x1234
-#define PCI_DEVICE_ID_INTEL_82437MX     0x1235
 #define PCI_DEVICE_ID_INTEL_82441       0x1237
 #define PCI_DEVICE_ID_INTEL_82380FB     0x124b
 #define PCI_DEVICE_ID_INTEL_82439       0x1250
@@ -2392,83 +1954,53 @@
 #define PCI_DEVICE_ID_INTEL_82845_HB    0x1a30
 #define PCI_DEVICE_ID_INTEL_82801AA_0   0x2410
 #define PCI_DEVICE_ID_INTEL_82801AA_1   0x2411
-#define PCI_DEVICE_ID_INTEL_82801AA_2   0x2412
 #define PCI_DEVICE_ID_INTEL_82801AA_3   0x2413
 #define PCI_DEVICE_ID_INTEL_82801AA_5   0x2415
 #define PCI_DEVICE_ID_INTEL_82801AA_6   0x2416
 #define PCI_DEVICE_ID_INTEL_82801AA_8   0x2418
 #define PCI_DEVICE_ID_INTEL_82801AB_0   0x2420
 #define PCI_DEVICE_ID_INTEL_82801AB_1   0x2421
-#define PCI_DEVICE_ID_INTEL_82801AB_2   0x2422
 #define PCI_DEVICE_ID_INTEL_82801AB_3   0x2423
 #define PCI_DEVICE_ID_INTEL_82801AB_5   0x2425
 #define PCI_DEVICE_ID_INTEL_82801AB_6   0x2426
 #define PCI_DEVICE_ID_INTEL_82801AB_8   0x2428
 #define PCI_DEVICE_ID_INTEL_82801BA_0   0x2440
-#define PCI_DEVICE_ID_INTEL_82801BA_1   0x2442
 #define PCI_DEVICE_ID_INTEL_82801BA_2   0x2443
-#define PCI_DEVICE_ID_INTEL_82801BA_3   0x2444
 #define PCI_DEVICE_ID_INTEL_82801BA_4   0x2445
-#define PCI_DEVICE_ID_INTEL_82801BA_5   0x2446
 #define PCI_DEVICE_ID_INTEL_82801BA_6   0x2448
-#define PCI_DEVICE_ID_INTEL_82801BA_7   0x2449
 #define PCI_DEVICE_ID_INTEL_82801BA_8   0x244a
 #define PCI_DEVICE_ID_INTEL_82801BA_9   0x244b
 #define PCI_DEVICE_ID_INTEL_82801BA_10  0x244c
 #define PCI_DEVICE_ID_INTEL_82801BA_11  0x244e
 #define PCI_DEVICE_ID_INTEL_82801E_0    0x2450
-#define PCI_DEVICE_ID_INTEL_82801E_2    0x2452
-#define PCI_DEVICE_ID_INTEL_82801E_3    0x2453
-#define PCI_DEVICE_ID_INTEL_82801E_9    0x2459
 #define PCI_DEVICE_ID_INTEL_82801E_11   0x245b
-#define PCI_DEVICE_ID_INTEL_82801E_13   0x245d
-#define PCI_DEVICE_ID_INTEL_82801E_14   0x245e
 #define PCI_DEVICE_ID_INTEL_82801CA_0   0x2480
-#define PCI_DEVICE_ID_INTEL_82801CA_2   0x2482
 #define PCI_DEVICE_ID_INTEL_82801CA_3   0x2483
-#define PCI_DEVICE_ID_INTEL_82801CA_4   0x2484
 #define PCI_DEVICE_ID_INTEL_82801CA_5   0x2485
 #define PCI_DEVICE_ID_INTEL_82801CA_6   0x2486
-#define PCI_DEVICE_ID_INTEL_82801CA_7   0x2487
 #define PCI_DEVICE_ID_INTEL_82801CA_10  0x248a
 #define PCI_DEVICE_ID_INTEL_82801CA_11  0x248b
 #define PCI_DEVICE_ID_INTEL_82801CA_12  0x248c
 #define PCI_DEVICE_ID_INTEL_82801DB_0   0x24c0
 #define PCI_DEVICE_ID_INTEL_82801DB_1   0x24c1
-#define PCI_DEVICE_ID_INTEL_82801DB_2   0x24c2
 #define PCI_DEVICE_ID_INTEL_82801DB_3   0x24c3
-#define PCI_DEVICE_ID_INTEL_82801DB_4   0x24c4
 #define PCI_DEVICE_ID_INTEL_82801DB_5   0x24c5
 #define PCI_DEVICE_ID_INTEL_82801DB_6   0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DB_7   0x24c7
 #define PCI_DEVICE_ID_INTEL_82801DB_9   0x24c9
 #define PCI_DEVICE_ID_INTEL_82801DB_10  0x24ca
 #define PCI_DEVICE_ID_INTEL_82801DB_11  0x24cb
 #define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
-#define PCI_DEVICE_ID_INTEL_82801DB_13  0x24cd
 #define PCI_DEVICE_ID_INTEL_82801EB_0   0x24d0
 #define PCI_DEVICE_ID_INTEL_82801EB_1   0x24d1
-#define PCI_DEVICE_ID_INTEL_82801EB_2   0x24d2
 #define PCI_DEVICE_ID_INTEL_82801EB_3   0x24d3
-#define PCI_DEVICE_ID_INTEL_82801EB_4   0x24d4
 #define PCI_DEVICE_ID_INTEL_82801EB_5   0x24d5
 #define PCI_DEVICE_ID_INTEL_82801EB_6   0x24d6
-#define PCI_DEVICE_ID_INTEL_82801EB_7   0x24d7
 #define PCI_DEVICE_ID_INTEL_82801EB_11  0x24db
-#define PCI_DEVICE_ID_INTEL_82801EB_13  0x24dd
 #define PCI_DEVICE_ID_INTEL_ESB_1       0x25a1
 #define PCI_DEVICE_ID_INTEL_ESB_2       0x25a2
-#define PCI_DEVICE_ID_INTEL_ESB_3       0x25a3
-#define PCI_DEVICE_ID_INTEL_ESB_31      0x25b0
 #define PCI_DEVICE_ID_INTEL_ESB_4       0x25a4
 #define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
-#define PCI_DEVICE_ID_INTEL_ESB_6       0x25a7
-#define PCI_DEVICE_ID_INTEL_ESB_7       0x25a9
-#define PCI_DEVICE_ID_INTEL_ESB_8       0x25aa
 #define PCI_DEVICE_ID_INTEL_ESB_9       0x25ab
-#define PCI_DEVICE_ID_INTEL_ESB_11      0x25ac
-#define PCI_DEVICE_ID_INTEL_ESB_12      0x25ad
-#define PCI_DEVICE_ID_INTEL_ESB_13      0x25ae
 #define PCI_DEVICE_ID_INTEL_82820_HB    0x2500
 #define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
 #define PCI_DEVICE_ID_INTEL_82850_HB    0x2530
@@ -2478,7 +2010,6 @@
 #define PCI_DEVICE_ID_INTEL_82865_HB    0x2570
 #define PCI_DEVICE_ID_INTEL_82865_IG    0x2572
 #define PCI_DEVICE_ID_INTEL_82875_HB    0x2578
-#define PCI_DEVICE_ID_INTEL_82875_IG    0x257b
 #define PCI_DEVICE_ID_INTEL_82915G_HB   0x2580
 #define PCI_DEVICE_ID_INTEL_82915G_IG   0x2582
 #define PCI_DEVICE_ID_INTEL_82915GM_HB  0x2590
@@ -2488,80 +2019,23 @@
 #define PCI_DEVICE_ID_INTEL_ICH6_0      0x2640
 #define PCI_DEVICE_ID_INTEL_ICH6_1      0x2641
 #define PCI_DEVICE_ID_INTEL_ICH6_2      0x2642
-#define PCI_DEVICE_ID_INTEL_ICH6_3      0x2651
-#define PCI_DEVICE_ID_INTEL_ICH6_4      0x2652
-#define PCI_DEVICE_ID_INTEL_ICH6_5      0x2653
-#define PCI_DEVICE_ID_INTEL_ICH6_6      0x2658
-#define PCI_DEVICE_ID_INTEL_ICH6_7      0x2659
-#define PCI_DEVICE_ID_INTEL_ICH6_8      0x265a
-#define PCI_DEVICE_ID_INTEL_ICH6_9      0x265b
-#define PCI_DEVICE_ID_INTEL_ICH6_10     0x265c
-#define PCI_DEVICE_ID_INTEL_ICH6_11     0x2660
-#define PCI_DEVICE_ID_INTEL_ICH6_12     0x2662
-#define PCI_DEVICE_ID_INTEL_ICH6_13     0x2664
-#define PCI_DEVICE_ID_INTEL_ICH6_14     0x2666
-#define PCI_DEVICE_ID_INTEL_ICH6_15     0x2668
 #define PCI_DEVICE_ID_INTEL_ICH6_16     0x266a
 #define PCI_DEVICE_ID_INTEL_ICH6_17     0x266d
 #define PCI_DEVICE_ID_INTEL_ICH6_18     0x266e
 #define PCI_DEVICE_ID_INTEL_ICH6_19     0x266f
 #define PCI_DEVICE_ID_INTEL_ESB2_0      0x2670
-#define PCI_DEVICE_ID_INTEL_ESB2_1      0x2680
-#define PCI_DEVICE_ID_INTEL_ESB2_2      0x2681
-#define PCI_DEVICE_ID_INTEL_ESB2_3      0x2682
-#define PCI_DEVICE_ID_INTEL_ESB2_4      0x2683
-#define PCI_DEVICE_ID_INTEL_ESB2_5      0x2688
-#define PCI_DEVICE_ID_INTEL_ESB2_6      0x2689
-#define PCI_DEVICE_ID_INTEL_ESB2_7      0x268a
-#define PCI_DEVICE_ID_INTEL_ESB2_8      0x268b
-#define PCI_DEVICE_ID_INTEL_ESB2_9      0x268c
-#define PCI_DEVICE_ID_INTEL_ESB2_10     0x2690
-#define PCI_DEVICE_ID_INTEL_ESB2_11     0x2692
-#define PCI_DEVICE_ID_INTEL_ESB2_12     0x2694
-#define PCI_DEVICE_ID_INTEL_ESB2_13     0x2696
 #define PCI_DEVICE_ID_INTEL_ESB2_14     0x2698
-#define PCI_DEVICE_ID_INTEL_ESB2_15     0x2699
-#define PCI_DEVICE_ID_INTEL_ESB2_16     0x269a
 #define PCI_DEVICE_ID_INTEL_ESB2_17     0x269b
 #define PCI_DEVICE_ID_INTEL_ESB2_18     0x269e
 #define PCI_DEVICE_ID_INTEL_ICH7_0      0x27b8
 #define PCI_DEVICE_ID_INTEL_ICH7_1      0x27b9
-#define PCI_DEVICE_ID_INTEL_ICH7_2      0x27c0
-#define PCI_DEVICE_ID_INTEL_ICH7_3      0x27c1
 #define PCI_DEVICE_ID_INTEL_ICH7_30     0x27b0
 #define PCI_DEVICE_ID_INTEL_ICH7_31     0x27bd
-#define PCI_DEVICE_ID_INTEL_ICH7_5      0x27c4
-#define PCI_DEVICE_ID_INTEL_ICH7_6      0x27c5
-#define PCI_DEVICE_ID_INTEL_ICH7_7      0x27c8
-#define PCI_DEVICE_ID_INTEL_ICH7_8      0x27c9
-#define PCI_DEVICE_ID_INTEL_ICH7_9      0x27ca
-#define PCI_DEVICE_ID_INTEL_ICH7_10     0x27cb
-#define PCI_DEVICE_ID_INTEL_ICH7_11     0x27cc
-#define PCI_DEVICE_ID_INTEL_ICH7_12     0x27d0
-#define PCI_DEVICE_ID_INTEL_ICH7_13     0x27d2
-#define PCI_DEVICE_ID_INTEL_ICH7_14     0x27d4
-#define PCI_DEVICE_ID_INTEL_ICH7_15     0x27d6
-#define PCI_DEVICE_ID_INTEL_ICH7_16     0x27d8
 #define PCI_DEVICE_ID_INTEL_ICH7_17     0x27da
-#define PCI_DEVICE_ID_INTEL_ICH7_18     0x27dc
 #define PCI_DEVICE_ID_INTEL_ICH7_19     0x27dd
 #define PCI_DEVICE_ID_INTEL_ICH7_20     0x27de
 #define PCI_DEVICE_ID_INTEL_ICH7_21     0x27df
-#define PCI_DEVICE_ID_INTEL_ICH7_22     0x27e0
-#define PCI_DEVICE_ID_INTEL_ICH7_23     0x27e2
 #define PCI_DEVICE_ID_INTEL_82855PM_HB  0x3340
-#define PCI_DEVICE_ID_INTEL_ESB2_19     0x3500
-#define PCI_DEVICE_ID_INTEL_ESB2_20     0x3501
-#define PCI_DEVICE_ID_INTEL_ESB2_21     0x3504
-#define PCI_DEVICE_ID_INTEL_ESB2_22     0x3505
-#define PCI_DEVICE_ID_INTEL_ESB2_23     0x350c
-#define PCI_DEVICE_ID_INTEL_ESB2_24     0x350d
-#define PCI_DEVICE_ID_INTEL_ESB2_25     0x3510
-#define PCI_DEVICE_ID_INTEL_ESB2_26     0x3511
-#define PCI_DEVICE_ID_INTEL_ESB2_27     0x3514
-#define PCI_DEVICE_ID_INTEL_ESB2_28     0x3515
-#define PCI_DEVICE_ID_INTEL_ESB2_29     0x3518
-#define PCI_DEVICE_ID_INTEL_ESB2_30     0x3519
 #define PCI_DEVICE_ID_INTEL_82830_HB    0x3575
 #define PCI_DEVICE_ID_INTEL_82830_CGC   0x3577
 #define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580
@@ -2575,7 +2049,6 @@
 #define PCI_DEVICE_ID_INTEL_MCH_PC      0x3599
 #define PCI_DEVICE_ID_INTEL_MCH_PC1     0x359a
 #define PCI_DEVICE_ID_INTEL_E7525_MCH   0x359e
-#define PCI_DEVICE_ID_INTEL_80310       0x530d
 #define PCI_DEVICE_ID_INTEL_82371SB_0   0x7000
 #define PCI_DEVICE_ID_INTEL_82371SB_1   0x7010
 #define PCI_DEVICE_ID_INTEL_82371SB_2   0x7020
@@ -2600,22 +2073,15 @@
 #define PCI_DEVICE_ID_INTEL_440MX_6     0x7196
 #define PCI_DEVICE_ID_INTEL_82443MX_0   0x7198
 #define PCI_DEVICE_ID_INTEL_82443MX_1   0x7199
-#define PCI_DEVICE_ID_INTEL_82443MX_2   0x719a
 #define PCI_DEVICE_ID_INTEL_82443MX_3   0x719b
 #define PCI_DEVICE_ID_INTEL_82443GX_0   0x71a0
-#define PCI_DEVICE_ID_INTEL_82443GX_1   0x71a1
 #define PCI_DEVICE_ID_INTEL_82443GX_2   0x71a2
-#define PCI_DEVICE_ID_INTEL_82372FB_0   0x7600
 #define PCI_DEVICE_ID_INTEL_82372FB_1   0x7601
-#define PCI_DEVICE_ID_INTEL_82372FB_2   0x7602
-#define PCI_DEVICE_ID_INTEL_82372FB_3   0x7603
 #define PCI_DEVICE_ID_INTEL_82454GX     0x84c4
-#define PCI_DEVICE_ID_INTEL_82450GX     0x84c5
 #define PCI_DEVICE_ID_INTEL_82451NX     0x84ca
 #define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
 #define PCI_DEVICE_ID_INTEL_84460GX     0x84ea
 #define PCI_DEVICE_ID_INTEL_IXP4XX      0x8500
-#define PCI_DEVICE_ID_INTEL_IXP2400     0x9001
 #define PCI_DEVICE_ID_INTEL_IXP2800     0x9004
 #define PCI_DEVICE_ID_INTEL_S21152BB    0xb152
 
@@ -2628,7 +2094,6 @@
 #define PCI_SUBDEVICE_ID_COMPUTONE_PG6  0x0003
 
 #define PCI_VENDOR_ID_KTI               0x8e2e
-#define PCI_DEVICE_ID_KTI_ET32P2        0x3000
 
 #define PCI_VENDOR_ID_ADAPTEC           0x9004
 #define PCI_DEVICE_ID_ADAPTEC_7810      0x1078
@@ -2636,7 +2101,6 @@
 #define PCI_DEVICE_ID_ADAPTEC_38602     0x3860
 #define PCI_DEVICE_ID_ADAPTEC_7850      0x5078
 #define PCI_DEVICE_ID_ADAPTEC_7855      0x5578
-#define PCI_DEVICE_ID_ADAPTEC_5800      0x5800
 #define PCI_DEVICE_ID_ADAPTEC_3860      0x6038
 #define PCI_DEVICE_ID_ADAPTEC_1480A     0x6075
 #define PCI_DEVICE_ID_ADAPTEC_7860      0x6078
@@ -2656,7 +2120,6 @@
 #define PCI_DEVICE_ID_ADAPTEC_7886      0x8678
 #define PCI_DEVICE_ID_ADAPTEC_7887      0x8778
 #define PCI_DEVICE_ID_ADAPTEC_7888      0x8878
-#define PCI_DEVICE_ID_ADAPTEC_1030      0x8b78
 
 #define PCI_VENDOR_ID_ADAPTEC2          0x9005
 #define PCI_DEVICE_ID_ADAPTEC2_2940U2   0x0010
@@ -2676,8 +2139,6 @@
 #define PCI_DEVICE_ID_ADAPTEC2_7899P    0x00cf
 #define PCI_DEVICE_ID_ADAPTEC2_SCAMP    0x0503
 
-#define PCI_VENDOR_ID_ATRONICS          0x907f
-#define PCI_DEVICE_ID_ATRONICS_2015     0x2015
 
 #define PCI_VENDOR_ID_HOLTEK            0x9412
 #define PCI_DEVICE_ID_HOLTEK_6565       0x6565
@@ -2696,6 +2157,7 @@
 
 #define PCI_SUBVENDOR_ID_EXSYS          0xd84d
 #define PCI_SUBDEVICE_ID_EXSYS_4014     0x4014
+#define PCI_SUBDEVICE_ID_EXSYS_4055     0x4055
 
 #define PCI_VENDOR_ID_TIGERJET          0xe159
 #define PCI_DEVICE_ID_TIGERJET_300      0x0001
@@ -2709,7 +2171,3 @@
 #define PCI_DEVICE_ID_RME_DIGI32_PRO    0x9897
 #define PCI_DEVICE_ID_RME_DIGI32_8      0x9898
 
-#define PCI_VENDOR_ID_ARK               0xedd8
-#define PCI_DEVICE_ID_ARK_STING         0xa091
-#define PCI_DEVICE_ID_ARK_STINGARK      0xa099
-#define PCI_DEVICE_ID_ARK_2000MT        0xa0a1
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
new file mode 100644
index 000000000000..a726225e0afe
--- /dev/null
+++ b/include/linux/platform_device.h
@@ -0,0 +1,40 @@
+/*
+ * platform_device.h - generic, centralized driver model
+ *
+ * Copyright (c) 2001-2003 Patrick Mochel <mochel@osdl.org>
+ *
+ * This file is released under the GPLv2
+ *
+ * See Documentation/driver-model/ for more information.
+ */
+
+#ifndef _PLATFORM_DEVICE_H_
+#define _PLATFORM_DEVICE_H_
+
+#include <linux/device.h>
+
+struct platform_device {
+        const char      * name;
+        u32             id;
+        struct device   dev;
+        u32             num_resources;
+        struct resource * resource;
+};
+
+#define to_platform_device(x) container_of((x), struct platform_device, dev)
+
+extern int platform_device_register(struct platform_device *);
+extern void platform_device_unregister(struct platform_device *);
+
+extern struct bus_type platform_bus_type;
+extern struct device platform_bus;
+
+extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int);
+extern int platform_get_irq(struct platform_device *, unsigned int);
+extern struct resource *platform_get_resource_byname(struct platform_device *, unsigned int, char *);
+extern int platform_get_irq_byname(struct platform_device *, char *);
+extern int platform_add_devices(struct platform_device **, int);
+
+extern struct platform_device *platform_device_register_simple(char *, unsigned int, struct resource *, unsigned int);
+
+#endif /* _PLATFORM_DEVICE_H_ */
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 5cfb07648eca..1514098d156d 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -170,6 +170,7 @@ typedef int __bitwise suspend_disk_method_t;
 
 struct pm_ops {
         suspend_disk_method_t pm_disk_mode;
+        int (*valid)(suspend_state_t state);
         int (*prepare)(suspend_state_t state);
         int (*enter)(suspend_state_t state);
         int (*finish)(suspend_state_t state);
@@ -219,10 +220,11 @@ typedef struct pm_message {
 
 struct dev_pm_info {
         pm_message_t            power_state;
+        unsigned                can_wakeup:1;
 #ifdef  CONFIG_PM
+        unsigned                should_wakeup:1;
         pm_message_t            prev_state;
         void                    * saved_state;
-        atomic_t                pm_users;
         struct device           * pm_parent;
         struct list_head        entry;
 #endif
@@ -236,13 +238,48 @@ extern void device_resume(void);
 
 #ifdef CONFIG_PM
 extern int device_suspend(pm_message_t state);
-#else
+
+#define device_set_wakeup_enable(dev,val) \
+        ((dev)->power.should_wakeup = !!(val))
+#define device_may_wakeup(dev) \
+        (device_can_wakeup(dev) && (dev)->power.should_wakeup)
+
+extern int dpm_runtime_suspend(struct device *, pm_message_t);
+extern void dpm_runtime_resume(struct device *);
+
+#else /* !CONFIG_PM */
+
 static inline int device_suspend(pm_message_t state)
 {
         return 0;
 }
+
+#define device_set_wakeup_enable(dev,val)       do{}while(0)
+#define device_may_wakeup(dev)                  (0)
+
+static inline int dpm_runtime_suspend(struct device * dev, pm_message_t state)
+{
+        return 0;
+}
+
+static inline void dpm_runtime_resume(struct device * dev)
+{
+
+}
+
 #endif
 
+/* changes to device_may_wakeup take effect on the next pm state change.
+ * by default, devices should wakeup if they can.
+ */
+#define device_can_wakeup(dev) \
+        ((dev)->power.can_wakeup)
+#define device_init_wakeup(dev,val) \
+        do { \
+                device_can_wakeup(dev) = !!(val); \
+                device_set_wakeup_enable(dev,val); \
+        } while(0)
+
 #endif /* __KERNEL__ */
 
 #endif /* _LINUX_PM_H */
diff --git a/include/linux/radix-tree.h b/include/linux/radix-tree.h
index 045d4761febc..9f0f9281f42a 100644
--- a/include/linux/radix-tree.h
+++ b/include/linux/radix-tree.h
@@ -24,7 +24,7 @@
 
 struct radix_tree_root {
         unsigned int            height;
-        unsigned int            gfp_mask;
+        gfp_t                   gfp_mask;
         struct radix_tree_node  *rnode;
 };
 
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 70191a5a148f..cce25591eec2 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -275,6 +275,7 @@ static inline int rcu_pending(int cpu)
 extern void rcu_init(void);
 extern void rcu_check_callbacks(int cpu, int user);
 extern void rcu_restart_cpu(int cpu);
+extern long rcu_batches_completed(void);
 
 /* Exported interfaces */
 extern void FASTCALL(call_rcu(struct rcu_head *head, 
diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h
index af00b10294cd..001ab82df051 100644
--- a/include/linux/reiserfs_fs.h
+++ b/include/linux/reiserfs_fs.h
@@ -1972,7 +1972,7 @@ extern struct address_space_operations reiserfs_address_space_operations;
 
 /* fix_nodes.c */
 #ifdef CONFIG_REISERFS_CHECK
-void *reiserfs_kmalloc(size_t size, int flags, struct super_block *s);
+void *reiserfs_kmalloc(size_t size, gfp_t flags, struct super_block *s);
 void reiserfs_kfree(const void *vp, size_t size, struct super_block *s);
 #else
 static inline void *reiserfs_kmalloc(size_t size, int flags,
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index e80fb7ee6efd..35b30e6c8cf8 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -95,8 +95,8 @@ int try_to_unmap(struct page *);
 /*
  * Called from mm/filemap_xip.c to unmap empty zero page
  */
-pte_t *page_check_address(struct page *, struct mm_struct *, unsigned long);
-
+pte_t *page_check_address(struct page *, struct mm_struct *,
+                                unsigned long, spinlock_t **);
 
 /*
  * Used by swapoff to help locate where page is expected in vma.
diff --git a/include/linux/rwsem-spinlock.h b/include/linux/rwsem-spinlock.h
index b52a2af25f1f..f30f805080ae 100644
--- a/include/linux/rwsem-spinlock.h
+++ b/include/linux/rwsem-spinlock.h
@@ -61,5 +61,10 @@ extern void FASTCALL(__up_read(struct rw_semaphore *sem));
 extern void FASTCALL(__up_write(struct rw_semaphore *sem));
 extern void FASTCALL(__downgrade_write(struct rw_semaphore *sem));
 
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->activity != 0);
+}
+
 #endif /* __KERNEL__ */
 #endif /* _LINUX_RWSEM_SPINLOCK_H */
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 7f717e95ae37..66ff545552f7 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -1,14 +1,23 @@
 #ifndef _LINUX_SCATTERLIST_H
 #define _LINUX_SCATTERLIST_H
 
-static inline void sg_init_one(struct scatterlist *sg,
-                               u8 *buf, unsigned int buflen)
-{
-        memset(sg, 0, sizeof(*sg));
+#include <asm/scatterlist.h>
+#include <linux/mm.h>
+#include <linux/string.h>
 
+static inline void sg_set_buf(struct scatterlist *sg, void *buf,
+                              unsigned int buflen)
+{
         sg->page = virt_to_page(buf);
         sg->offset = offset_in_page(buf);
         sg->length = buflen;
 }
 
+static inline void sg_init_one(struct scatterlist *sg, void *buf,
+                               unsigned int buflen)
+{
+        memset(sg, 0, sizeof(*sg));
+        sg_set_buf(sg, buf, buflen);
+}
+
 #endif /* _LINUX_SCATTERLIST_H */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 27519df0f987..03b68a7b4b82 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -249,6 +249,36 @@ arch_get_unmapped_area_topdown(struct file *filp, unsigned long addr,
 extern void arch_unmap_area(struct mm_struct *, unsigned long);
 extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 
+#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+/*
+ * The mm counters are not protected by its page_table_lock,
+ * so must be incremented atomically.
+ */
+#ifdef ATOMIC64_INIT
+#define set_mm_counter(mm, member, value) atomic64_set(&(mm)->_##member, value)
+#define get_mm_counter(mm, member) ((unsigned long)atomic64_read(&(mm)->_##member))
+#define add_mm_counter(mm, member, value) atomic64_add(value, &(mm)->_##member)
+#define inc_mm_counter(mm, member) atomic64_inc(&(mm)->_##member)
+#define dec_mm_counter(mm, member) atomic64_dec(&(mm)->_##member)
+typedef atomic64_t mm_counter_t;
+#else /* !ATOMIC64_INIT */
+/*
+ * The counters wrap back to 0 at 2^32 * PAGE_SIZE,
+ * that is, at 16TB if using 4kB page size.
+ */
+#define set_mm_counter(mm, member, value) atomic_set(&(mm)->_##member, value)
+#define get_mm_counter(mm, member) ((unsigned long)atomic_read(&(mm)->_##member))
+#define add_mm_counter(mm, member, value) atomic_add(value, &(mm)->_##member)
+#define inc_mm_counter(mm, member) atomic_inc(&(mm)->_##member)
+#define dec_mm_counter(mm, member) atomic_dec(&(mm)->_##member)
+typedef atomic_t mm_counter_t;
+#endif /* !ATOMIC64_INIT */
+
+#else  /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+/*
+ * The mm counters are protected by its page_table_lock,
+ * so can be incremented directly.
+ */
 #define set_mm_counter(mm, member, value) (mm)->_##member = (value)
 #define get_mm_counter(mm, member) ((mm)->_##member)
 #define add_mm_counter(mm, member, value) (mm)->_##member += (value)
@@ -256,6 +286,20 @@ extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 #define dec_mm_counter(mm, member) (mm)->_##member--
 typedef unsigned long mm_counter_t;
 
+#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+
+#define get_mm_rss(mm)                                  \
+        (get_mm_counter(mm, file_rss) + get_mm_counter(mm, anon_rss))
+#define update_hiwater_rss(mm)  do {                    \
+        unsigned long _rss = get_mm_rss(mm);            \
+        if ((mm)->hiwater_rss < _rss)                   \
+                (mm)->hiwater_rss = _rss;               \
+} while (0)
+#define update_hiwater_vm(mm)   do {                    \
+        if ((mm)->hiwater_vm < (mm)->total_vm)          \
+                (mm)->hiwater_vm = (mm)->total_vm;      \
+} while (0)
+
 struct mm_struct {
         struct vm_area_struct * mmap;           /* list of VMAs */
         struct rb_root mm_rb;
@@ -279,15 +323,20 @@ struct mm_struct {
                                                  * by mmlist_lock
                                                  */
 
+        /* Special counters, in some configurations protected by the
+         * page_table_lock, in other configurations by being atomic.
+         */
+        mm_counter_t _file_rss;
+        mm_counter_t _anon_rss;
+
+        unsigned long hiwater_rss;      /* High-watermark of RSS usage */
+        unsigned long hiwater_vm;       /* High-water virtual memory usage */
+
+        unsigned long total_vm, locked_vm, shared_vm, exec_vm;
+        unsigned long stack_vm, reserved_vm, def_flags, nr_ptes;
         unsigned long start_code, end_code, start_data, end_data;
         unsigned long start_brk, brk, start_stack;
         unsigned long arg_start, arg_end, env_start, env_end;
-        unsigned long total_vm, locked_vm, shared_vm;
-        unsigned long exec_vm, stack_vm, reserved_vm, def_flags, nr_ptes;
-
-        /* Special counters protected by the page_table_lock */
-        mm_counter_t _rss;
-        mm_counter_t _anon_rss;
 
         unsigned long saved_auxv[AT_VECTOR_SIZE]; /* for /proc/PID/auxv */
 
@@ -308,11 +357,7 @@ struct mm_struct {
         /* aio bits */
         rwlock_t                ioctx_list_lock;
         struct kioctx           *ioctx_list;
-
         struct kioctx           default_kioctx;
-
-        unsigned long hiwater_rss;      /* High-water RSS usage */
-        unsigned long hiwater_vm;       /* High-water virtual memory usage */
 };
 
 struct sighand_struct {
@@ -895,7 +940,7 @@ extern int set_cpus_allowed(task_t *p, cpumask_t new_mask);
 #else
 static inline int set_cpus_allowed(task_t *p, cpumask_t new_mask)
 {
-        if (!cpus_intersects(new_mask, cpu_online_map))
+        if (!cpu_isset(0, new_mask))
                 return -EINVAL;
         return 0;
 }
@@ -1039,6 +1084,11 @@ extern int do_sigaltstack(const stack_t __user *, stack_t __user *, unsigned lon
 #define SEND_SIG_PRIV   ((struct siginfo *) 1)
 #define SEND_SIG_FORCED ((struct siginfo *) 2)
 
+static inline int is_si_special(const struct siginfo *info)
+{
+        return info <= SEND_SIG_FORCED;
+}
+
 /* True if we are on the alternate signal stack.  */
 
 static inline int on_sig_stack(unsigned long sp)
@@ -1166,7 +1216,7 @@ extern void unhash_process(struct task_struct *p);
 /*
  * Protects ->fs, ->files, ->mm, ->ptrace, ->group_info, ->comm, keyring
  * subscriptions and synchronises with wait4().  Also used in procfs.  Also
- * pins the final release of task.io_context.
+ * pins the final release of task.io_context.  Also protects ->cpuset.
  *
  * Nests both inside and outside of read_lock(&tasklist_lock).
  * It must not be nested with write_lock_irq(&tasklist_lock),
diff --git a/include/linux/sdladrv.h b/include/linux/sdladrv.h
index 78f634007fc6..c85e103d5e7b 100644
--- a/include/linux/sdladrv.h
+++ b/include/linux/sdladrv.h
@@ -52,12 +52,8 @@ typedef struct sdlahw
 
 extern int sdla_setup   (sdlahw_t* hw, void* sfm, unsigned len);
 extern int sdla_down    (sdlahw_t* hw);
-extern int sdla_inten   (sdlahw_t* hw);
-extern int sdla_intde   (sdlahw_t* hw);
-extern int sdla_intack  (sdlahw_t* hw);
 extern void S514_intack  (sdlahw_t* hw, u32 int_status);
 extern void read_S514_int_stat (sdlahw_t* hw, u32* int_status);
-extern int sdla_intr    (sdlahw_t* hw);
 extern int sdla_mapmem  (sdlahw_t* hw, unsigned long addr);
 extern int sdla_peek    (sdlahw_t* hw, unsigned long addr, void* buf,
                          unsigned len);
diff --git a/include/linux/security.h b/include/linux/security.h
index 627382e74057..f7e0ae018712 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -30,6 +30,7 @@
 #include <linux/shm.h>
 #include <linux/msg.h>
 #include <linux/sched.h>
+#include <linux/key.h>
 
 struct ctl_table;
 
@@ -385,6 +386,9 @@ struct swap_info_struct;
  *      NULL to request the size of the buffer required.  @size indicates
  *      the size of @buffer in bytes.  Note that @name is the remainder
  *      of the attribute name after the security. prefix has been removed.
+ *      @err is the return value from the preceding fs getxattr call,
+ *      and can be used by the security module to determine whether it
+ *      should try and canonicalize the attribute value.
  *      Return number of bytes used/required on success.
  * @inode_setsecurity:
  *      Set the security label associated with @name for @inode from the
@@ -785,6 +789,27 @@ struct swap_info_struct;
  * @sk_free_security:
  *      Deallocate security structure.
  *
+ * Security hooks affecting all Key Management operations
+ *
+ * @key_alloc:
+ *      Permit allocation of a key and assign security data. Note that key does
+ *      not have a serial number assigned at this point.
+ *      @key points to the key.
+ *      Return 0 if permission is granted, -ve error otherwise.
+ * @key_free:
+ *      Notification of destruction; free security data.
+ *      @key points to the key.
+ *      No return value.
+ * @key_permission:
+ *      See whether a specific operational right is granted to a process on a
+ *      key.
+ *      @key_ref refers to the key (key pointer + possession attribute bit).
+ *      @context points to the process to provide the context against which to
+ *       evaluate the security data on the key.
+ *      @perm describes the combination of permissions required of this key.
+ *      Return 1 if permission granted, 0 if permission denied and -ve it the
+ *      normal permissions model should be effected.
+ *
  * Security hooks affecting all System V IPC operations.
  *
  * @ipc_permission:
@@ -1091,7 +1116,7 @@ struct security_operations {
         int (*inode_getxattr) (struct dentry *dentry, char *name);
         int (*inode_listxattr) (struct dentry *dentry);
         int (*inode_removexattr) (struct dentry *dentry, char *name);
-        int (*inode_getsecurity)(struct inode *inode, const char *name, void *buffer, size_t size);
+        int (*inode_getsecurity)(struct inode *inode, const char *name, void *buffer, size_t size, int err);
         int (*inode_setsecurity)(struct inode *inode, const char *name, const void *value, size_t size, int flags);
         int (*inode_listsecurity)(struct inode *inode, char *buffer, size_t buffer_size);
 
@@ -1210,9 +1235,20 @@ struct security_operations {
         int (*socket_shutdown) (struct socket * sock, int how);
         int (*socket_sock_rcv_skb) (struct sock * sk, struct sk_buff * skb);
         int (*socket_getpeersec) (struct socket *sock, char __user *optval, int __user *optlen, unsigned len);
-        int (*sk_alloc_security) (struct sock *sk, int family, int priority);
+        int (*sk_alloc_security) (struct sock *sk, int family, gfp_t priority);
         void (*sk_free_security) (struct sock *sk);
 #endif  /* CONFIG_SECURITY_NETWORK */
+
+        /* key management security hooks */
+#ifdef CONFIG_KEYS
+        int (*key_alloc)(struct key *key);
+        void (*key_free)(struct key *key);
+        int (*key_permission)(key_ref_t key_ref,
+                              struct task_struct *context,
+                              key_perm_t perm);
+
+#endif  /* CONFIG_KEYS */
+
 };
 
 /* global variables */
@@ -1580,11 +1616,11 @@ static inline int security_inode_removexattr (struct dentry *dentry, char *name)
         return security_ops->inode_removexattr (dentry, name);
 }
 
-static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size)
+static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size, int err)
 {
         if (unlikely (IS_PRIVATE (inode)))
                 return 0;
-        return security_ops->inode_getsecurity(inode, name, buffer, size);
+        return security_ops->inode_getsecurity(inode, name, buffer, size, err);
 }
 
 static inline int security_inode_setsecurity(struct inode *inode, const char *name, const void *value, size_t size, int flags)
@@ -2222,7 +2258,7 @@ static inline int security_inode_removexattr (struct dentry *dentry, char *name)
         return cap_inode_removexattr(dentry, name);
 }
 
-static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size)
+static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size, int err)
 {
         return -EOPNOTSUPP;
 }
@@ -2761,5 +2797,45 @@ static inline void security_sk_free(struct sock *sk)
 }
 #endif  /* CONFIG_SECURITY_NETWORK */
 
+#ifdef CONFIG_KEYS
+#ifdef CONFIG_SECURITY
+static inline int security_key_alloc(struct key *key)
+{
+        return security_ops->key_alloc(key);
+}
+
+static inline void security_key_free(struct key *key)
+{
+        security_ops->key_free(key);
+}
+
+static inline int security_key_permission(key_ref_t key_ref,
+                                          struct task_struct *context,
+                                          key_perm_t perm)
+{
+        return security_ops->key_permission(key_ref, context, perm);
+}
+
+#else
+
+static inline int security_key_alloc(struct key *key)
+{
+        return 0;
+}
+
+static inline void security_key_free(struct key *key)
+{
+}
+
+static inline int security_key_permission(key_ref_t key_ref,
+                                          struct task_struct *context,
+                                          key_perm_t perm)
+{
+        return 0;
+}
+
+#endif
+#endif /* CONFIG_KEYS */
+
 #endif /* ! __LINUX_SECURITY_H */
 
diff --git a/include/linux/serial.h b/include/linux/serial.h
index 12cd9cf65e8f..33fc8cb8ddfb 100644
--- a/include/linux/serial.h
+++ b/include/linux/serial.h
@@ -11,6 +11,7 @@
 #define _LINUX_SERIAL_H
 
 #ifdef __KERNEL__
+#include <linux/types.h>
 #include <asm/page.h>
 
 /*
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index 317a979b24de..2b799d40d669 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -12,7 +12,7 @@
 #define _LINUX_SERIAL_8250_H
 
 #include <linux/serial_core.h>
-#include <linux/device.h>
+#include <linux/platform_device.h>
 
 /*
  * This is the platform device platform_data structure
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 27db8da43aa4..2b0401b93f2b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -39,7 +39,8 @@
 #define PORT_RSA        13
 #define PORT_NS16550A   14
 #define PORT_XSCALE     15
-#define PORT_MAX_8250   15      /* max port ID */
+#define PORT_IP3106     16
+#define PORT_MAX_8250   16      /* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
diff --git a/include/linux/serial_ip3106.h b/include/linux/serial_ip3106.h
new file mode 100644
index 000000000000..f500ac602c5c
--- /dev/null
+++ b/include/linux/serial_ip3106.h
@@ -0,0 +1,81 @@
+/*
+ * Embedded Alley Solutions, source@embeddedalley.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _LINUX_SERIAL_IP3106_H
+#define _LINUX_SERIAL_IP3106_H
+
+#include <linux/serial_core.h>
+#include <linux/device.h>
+
+#define IP3106_NR_PORTS         2
+
+struct ip3106_port {
+        struct uart_port        port;
+        struct timer_list       timer;
+        unsigned int            old_status;
+};
+
+/* register offsets */
+#define IP3106_LCR              0
+#define IP3106_MCR              0x004
+#define IP3106_BAUD             0x008
+#define IP3106_CFG              0x00c
+#define IP3106_FIFO             0x028
+#define IP3106_ISTAT            0xfe0
+#define IP3106_IEN              0xfe4
+#define IP3106_ICLR             0xfe8
+#define IP3106_ISET             0xfec
+#define IP3106_PD               0xff4
+#define IP3106_MID              0xffc
+
+#define IP3106_UART_LCR_TXBREAK         (1<<30)
+#define IP3106_UART_LCR_PAREVN          0x10000000
+#define IP3106_UART_LCR_PAREN           0x08000000
+#define IP3106_UART_LCR_2STOPB          0x04000000
+#define IP3106_UART_LCR_8BIT            0x01000000
+#define IP3106_UART_LCR_TX_RST          0x00040000
+#define IP3106_UART_LCR_RX_RST          0x00020000
+#define IP3106_UART_LCR_RX_NEXT         0x00010000
+
+#define IP3106_UART_MCR_SCR             0xFF000000
+#define IP3106_UART_MCR_DCD             0x00800000
+#define IP3106_UART_MCR_CTS             0x00100000
+#define IP3106_UART_MCR_LOOP            0x00000010
+#define IP3106_UART_MCR_RTS             0x00000002
+#define IP3106_UART_MCR_DTR             0x00000001
+
+#define IP3106_UART_INT_TX              0x00000080
+#define IP3106_UART_INT_EMPTY           0x00000040
+#define IP3106_UART_INT_RCVTO           0x00000020
+#define IP3106_UART_INT_RX              0x00000010
+#define IP3106_UART_INT_RXOVRN          0x00000008
+#define IP3106_UART_INT_FRERR           0x00000004
+#define IP3106_UART_INT_BREAK           0x00000002
+#define IP3106_UART_INT_PARITY          0x00000001
+#define IP3106_UART_INT_ALLRX           0x0000003F
+#define IP3106_UART_INT_ALLTX           0x000000C0
+
+#define IP3106_UART_FIFO_TXFIFO         0x001F0000
+#define IP3106_UART_FIFO_TXFIFO_STA     (0x1f<<16)
+#define IP3106_UART_FIFO_RXBRK          0x00008000
+#define IP3106_UART_FIFO_RXFE           0x00004000
+#define IP3106_UART_FIFO_RXPAR          0x00002000
+#define IP3106_UART_FIFO_RXFIFO         0x00001F00
+#define IP3106_UART_FIFO_RBRTHR         0x000000FF
+
+#endif
diff --git a/include/linux/signal.h b/include/linux/signal.h
index 7be18b5e2fb4..5dd5f02c5c5f 100644
--- a/include/linux/signal.h
+++ b/include/linux/signal.h
@@ -25,7 +25,6 @@
 
 struct sigqueue {
         struct list_head list;
-        spinlock_t *lock;
         int flags;
         siginfo_t info;
         struct user_struct *user;
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 8f5d9e7f8734..4286d832166f 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -137,6 +137,8 @@ struct skb_shared_info {
         unsigned int    nr_frags;
         unsigned short  tso_size;
         unsigned short  tso_segs;
+        unsigned short  ufo_size;
+        unsigned int    ip6_frag_id;
         struct sk_buff  *frag_list;
         skb_frag_t      frags[MAX_SKB_FRAGS];
 };
@@ -171,7 +173,6 @@ enum {
  *      struct sk_buff - socket buffer
  *      @next: Next buffer in list
  *      @prev: Previous buffer in list
- *      @list: List we are on
  *      @sk: Socket we are owned by
  *      @tstamp: Time we arrived
  *      @dev: Device we arrived on/are leaving by
@@ -190,6 +191,7 @@ enum {
  *      @cloned: Head may be cloned (check refcnt to be sure)
  *      @nohdr: Payload reference only, must not modify header
  *      @pkt_type: Packet class
+ *      @fclone: skbuff clone status
  *      @ip_summed: Driver fed us an IP checksum
  *      @priority: Packet queueing priority
  *      @users: User count - see {datagram,tcp}.c
@@ -202,6 +204,7 @@ enum {
  *      @destructor: Destruct function
  *      @nfmark: Can be used for communication between hooks
  *      @nfct: Associated connection, if any
+ *      @ipvs_property: skbuff is owned by ipvs
  *      @nfctinfo: Relationship of this skb to the connection
  *      @nf_bridge: Saved data about a bridged frame - see br_netfilter.c
  *      @tc_index: Traffic control index
@@ -340,6 +343,11 @@ extern void	      skb_over_panic(struct sk_buff *skb, int len,
 extern void           skb_under_panic(struct sk_buff *skb, int len,
                                       void *here);
 
+extern int skb_append_datato_frags(struct sock *sk, struct sk_buff *skb,
+                        int getfrag(void *from, char *to, int offset,
+                        int len,int odd, struct sk_buff *skb),
+                        void *from, int length);
+
 struct skb_seq_state
 {
         __u32           lower_offset;
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 5fc04a16ecb0..09b9aa60063d 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -121,7 +121,7 @@ extern unsigned int ksize(const void *);
 extern void *kmem_cache_alloc_node(kmem_cache_t *, gfp_t flags, int node);
 extern void *kmalloc_node(size_t size, gfp_t flags, int node);
 #else
-static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int node)
+static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, gfp_t flags, int node)
 {
         return kmem_cache_alloc(cachep, flags);
 }
diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h
index cdc99a27840d..0e9682c9def5 100644
--- a/include/linux/spinlock.h
+++ b/include/linux/spinlock.h
@@ -171,23 +171,42 @@ extern int __lockfunc generic__raw_read_trylock(raw_rwlock_t *lock);
 #define write_lock_irq(lock)            _write_lock_irq(lock)
 #define write_lock_bh(lock)             _write_lock_bh(lock)
 
-#define spin_unlock(lock)               _spin_unlock(lock)
-#define write_unlock(lock)              _write_unlock(lock)
-#define read_unlock(lock)               _read_unlock(lock)
+/*
+ * We inline the unlock functions in the nondebug case:
+ */
+#if defined(CONFIG_DEBUG_SPINLOCK) || defined(CONFIG_PREEMPT) || !defined(CONFIG_SMP)
+# define spin_unlock(lock)              _spin_unlock(lock)
+# define read_unlock(lock)              _read_unlock(lock)
+# define write_unlock(lock)             _write_unlock(lock)
+#else
+# define spin_unlock(lock)              __raw_spin_unlock(&(lock)->raw_lock)
+# define read_unlock(lock)              __raw_read_unlock(&(lock)->raw_lock)
+# define write_unlock(lock)             __raw_write_unlock(&(lock)->raw_lock)
+#endif
+
+#if defined(CONFIG_DEBUG_SPINLOCK) || defined(CONFIG_PREEMPT) || !defined(CONFIG_SMP)
+# define spin_unlock_irq(lock)          _spin_unlock_irq(lock)
+# define read_unlock_irq(lock)          _read_unlock_irq(lock)
+# define write_unlock_irq(lock)         _write_unlock_irq(lock)
+#else
+# define spin_unlock_irq(lock) \
+    do { __raw_spin_unlock(&(lock)->raw_lock); local_irq_enable(); } while (0)
+# define read_unlock_irq(lock) \
+    do { __raw_read_unlock(&(lock)->raw_lock); local_irq_enable(); } while (0)
+# define write_unlock_irq(lock) \
+    do { __raw_write_unlock(&(lock)->raw_lock); local_irq_enable(); } while (0)
+#endif
 
 #define spin_unlock_irqrestore(lock, flags) \
                                         _spin_unlock_irqrestore(lock, flags)
-#define spin_unlock_irq(lock)           _spin_unlock_irq(lock)
 #define spin_unlock_bh(lock)            _spin_unlock_bh(lock)
 
 #define read_unlock_irqrestore(lock, flags) \
                                         _read_unlock_irqrestore(lock, flags)
-#define read_unlock_irq(lock)           _read_unlock_irq(lock)
 #define read_unlock_bh(lock)            _read_unlock_bh(lock)
 
 #define write_unlock_irqrestore(lock, flags) \
                                         _write_unlock_irqrestore(lock, flags)
-#define write_unlock_irq(lock)          _write_unlock_irq(lock)
 #define write_unlock_bh(lock)           _write_unlock_bh(lock)
 
 #define spin_trylock_bh(lock)           __cond_lock(_spin_trylock_bh(lock))
diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h
index 04ebc24db348..b68c11a2d6dd 100644
--- a/include/linux/sunrpc/auth.h
+++ b/include/linux/sunrpc/auth.h
@@ -66,7 +66,12 @@ struct rpc_cred_cache {
 
 struct rpc_auth {
         unsigned int            au_cslack;      /* call cred size estimate */
-        unsigned int            au_rslack;      /* reply verf size guess */
+                                /* guess at number of u32's auth adds before
+                                 * reply data; normally the verifier size: */
+        unsigned int            au_rslack;
+                                /* for gss, used to calculate au_rslack: */
+        unsigned int            au_verfsize;
+
         unsigned int            au_flags;       /* various flags */
         struct rpc_authops *    au_ops;         /* operations */
         rpc_authflavor_t        au_flavor;      /* pseudoflavor (note may
diff --git a/include/linux/sunrpc/debug.h b/include/linux/sunrpc/debug.h
index eadb31e3c198..1a42d902bc11 100644
--- a/include/linux/sunrpc/debug.h
+++ b/include/linux/sunrpc/debug.h
@@ -32,6 +32,7 @@
 #define RPCDBG_AUTH             0x0010
 #define RPCDBG_PMAP             0x0020
 #define RPCDBG_SCHED            0x0040
+#define RPCDBG_TRANS            0x0080
 #define RPCDBG_SVCSOCK          0x0100
 #define RPCDBG_SVCDSP           0x0200
 #define RPCDBG_MISC             0x0400
@@ -94,6 +95,8 @@ enum {
         CTL_NLMDEBUG,
         CTL_SLOTTABLE_UDP,
         CTL_SLOTTABLE_TCP,
+        CTL_MIN_RESVPORT,
+        CTL_MAX_RESVPORT,
 };
 
 #endif /* _LINUX_SUNRPC_DEBUG_H_ */
diff --git a/include/linux/sunrpc/gss_api.h b/include/linux/sunrpc/gss_api.h
index 689262f63059..9b8bcf125c18 100644
--- a/include/linux/sunrpc/gss_api.h
+++ b/include/linux/sunrpc/gss_api.h
@@ -40,14 +40,21 @@ int gss_import_sec_context(
                 struct gss_ctx          **ctx_id);
 u32 gss_get_mic(
                 struct gss_ctx          *ctx_id,
-                u32                     qop,
                 struct xdr_buf          *message,
                 struct xdr_netobj       *mic_token);
 u32 gss_verify_mic(
                 struct gss_ctx          *ctx_id,
                 struct xdr_buf          *message,
-                struct xdr_netobj       *mic_token,
-                u32                     *qstate);
+                struct xdr_netobj       *mic_token);
+u32 gss_wrap(
+                struct gss_ctx          *ctx_id,
+                int                     offset,
+                struct xdr_buf          *outbuf,
+                struct page             **inpages);
+u32 gss_unwrap(
+                struct gss_ctx          *ctx_id,
+                int                     offset,
+                struct xdr_buf          *inbuf);
 u32 gss_delete_sec_context(
                 struct gss_ctx          **ctx_id);
 
@@ -56,7 +63,6 @@ char *gss_service_to_auth_domain_name(struct gss_api_mech *, u32 service);
 
 struct pf_desc {
         u32     pseudoflavor;
-        u32     qop;
         u32     service;
         char    *name;
         char    *auth_domain_name;
@@ -85,14 +91,21 @@ struct gss_api_ops {
                         struct gss_ctx          *ctx_id);
         u32 (*gss_get_mic)(
                         struct gss_ctx          *ctx_id,
-                        u32                     qop, 
                         struct xdr_buf          *message,
                         struct xdr_netobj       *mic_token);
         u32 (*gss_verify_mic)(
                         struct gss_ctx          *ctx_id,
                         struct xdr_buf          *message,
-                        struct xdr_netobj       *mic_token,
-                        u32                     *qstate);
+                        struct xdr_netobj       *mic_token);
+        u32 (*gss_wrap)(
+                        struct gss_ctx          *ctx_id,
+                        int                     offset,
+                        struct xdr_buf          *outbuf,
+                        struct page             **inpages);
+        u32 (*gss_unwrap)(
+                        struct gss_ctx          *ctx_id,
+                        int                     offset,
+                        struct xdr_buf          *buf);
         void (*gss_delete_sec_context)(
                         void                    *internal_ctx_id);
 };
diff --git a/include/linux/sunrpc/gss_err.h b/include/linux/sunrpc/gss_err.h
index 92608a2e574c..a6807867bd21 100644
--- a/include/linux/sunrpc/gss_err.h
+++ b/include/linux/sunrpc/gss_err.h
@@ -66,16 +66,6 @@ typedef unsigned int OM_uint32;
 
 
 /*
- * Define the default Quality of Protection for per-message services.  Note
- * that an implementation that offers multiple levels of QOP may either reserve
- * a value (for example zero, as assumed here) to mean "default protection", or
- * alternatively may simply equate GSS_C_QOP_DEFAULT to a specific explicit
- * QOP value.  However a value of 0 should always be interpreted by a GSSAPI
- * implementation as a request for the default protection level.
- */
-#define GSS_C_QOP_DEFAULT 0
-
-/*
  * Expiration time of 2^32-1 seconds means infinite lifetime for a
  * credential or security context
  */
diff --git a/include/linux/sunrpc/gss_krb5.h b/include/linux/sunrpc/gss_krb5.h
index ffe31d2eb9ec..2c3601d31045 100644
--- a/include/linux/sunrpc/gss_krb5.h
+++ b/include/linux/sunrpc/gss_krb5.h
@@ -116,18 +116,22 @@ enum seal_alg {
 
 s32
 make_checksum(s32 cksumtype, char *header, int hdrlen, struct xdr_buf *body,
-                   struct xdr_netobj *cksum);
+                   int body_offset, struct xdr_netobj *cksum);
+
+u32 gss_get_mic_kerberos(struct gss_ctx *, struct xdr_buf *,
+                struct xdr_netobj *);
+
+u32 gss_verify_mic_kerberos(struct gss_ctx *, struct xdr_buf *,
+                struct xdr_netobj *);
 
 u32
-krb5_make_token(struct krb5_ctx *context_handle, int qop_req,
-        struct xdr_buf *input_message_buffer,
-        struct xdr_netobj *output_message_buffer, int toktype);
+gss_wrap_kerberos(struct gss_ctx *ctx_id, int offset,
+                struct xdr_buf *outbuf, struct page **pages);
 
 u32
-krb5_read_token(struct krb5_ctx *context_handle,
-          struct xdr_netobj *input_token_buffer,
-          struct xdr_buf *message_buffer,
-          int *qop_state, int toktype);
+gss_unwrap_kerberos(struct gss_ctx *ctx_id, int offset,
+                struct xdr_buf *buf);
+
 
 u32
 krb5_encrypt(struct crypto_tfm * key,
@@ -137,6 +141,13 @@ u32
 krb5_decrypt(struct crypto_tfm * key,
              void *iv, void *in, void *out, int length); 
 
+int
+gss_encrypt_xdr_buf(struct crypto_tfm *tfm, struct xdr_buf *outbuf, int offset,
+                struct page **pages);
+
+int
+gss_decrypt_xdr_buf(struct crypto_tfm *tfm, struct xdr_buf *inbuf, int offset);
+
 s32
 krb5_make_seq_num(struct crypto_tfm * key,
                 int direction,
diff --git a/include/linux/sunrpc/gss_spkm3.h b/include/linux/sunrpc/gss_spkm3.h
index b5c9968c3c17..0beb2cf00a84 100644
--- a/include/linux/sunrpc/gss_spkm3.h
+++ b/include/linux/sunrpc/gss_spkm3.h
@@ -41,9 +41,9 @@ struct spkm3_ctx {
 #define SPKM_WRAP_TOK   5
 #define SPKM_DEL_TOK    6
 
-u32 spkm3_make_token(struct spkm3_ctx *ctx, int qop_req, struct xdr_buf * text, struct xdr_netobj * token, int toktype);
+u32 spkm3_make_token(struct spkm3_ctx *ctx, struct xdr_buf * text, struct xdr_netobj * token, int toktype);
 
-u32 spkm3_read_token(struct spkm3_ctx *ctx, struct xdr_netobj *read_token, struct xdr_buf *message_buffer, int *qop_state, int toktype);
+u32 spkm3_read_token(struct spkm3_ctx *ctx, struct xdr_netobj *read_token, struct xdr_buf *message_buffer, int toktype);
 
 #define CKSUMTYPE_RSA_MD5            0x0007
 
diff --git a/include/linux/sunrpc/msg_prot.h b/include/linux/sunrpc/msg_prot.h
index 15f115332389..f43f237360ae 100644
--- a/include/linux/sunrpc/msg_prot.h
+++ b/include/linux/sunrpc/msg_prot.h
@@ -76,5 +76,30 @@ enum rpc_auth_stat {
 
 #define RPC_MAXNETNAMELEN       256
 
+/*
+ * From RFC 1831:
+ *
+ * "A record is composed of one or more record fragments.  A record
+ *  fragment is a four-byte header followed by 0 to (2**31) - 1 bytes of
+ *  fragment data.  The bytes encode an unsigned binary number; as with
+ *  XDR integers, the byte order is from highest to lowest.  The number
+ *  encodes two values -- a boolean which indicates whether the fragment
+ *  is the last fragment of the record (bit value 1 implies the fragment
+ *  is the last fragment) and a 31-bit unsigned binary value which is the
+ *  length in bytes of the fragment's data.  The boolean value is the
+ *  highest-order bit of the header; the length is the 31 low-order bits.
+ *  (Note that this record specification is NOT in XDR standard form!)"
+ *
+ * The Linux RPC client always sends its requests in a single record
+ * fragment, limiting the maximum payload size for stream transports to
+ * 2GB.
+ */
+
+typedef u32     rpc_fraghdr;
+
+#define RPC_LAST_STREAM_FRAGMENT        (1U << 31)
+#define RPC_FRAGMENT_SIZE_MASK          (~RPC_LAST_STREAM_FRAGMENT)
+#define RPC_MAX_FRAGMENT_SIZE           ((1U << 31) - 1)
+
 #endif /* __KERNEL__ */
 #endif /* _LINUX_SUNRPC_MSGPROT_H_ */
diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h
index 23448d0fb5bc..5da968729cf8 100644
--- a/include/linux/sunrpc/xdr.h
+++ b/include/linux/sunrpc/xdr.h
@@ -161,14 +161,10 @@ typedef struct {
 
 typedef size_t (*skb_read_actor_t)(skb_reader_t *desc, void *to, size_t len);
 
+extern int csum_partial_copy_to_xdr(struct xdr_buf *, struct sk_buff *);
 extern ssize_t xdr_partial_copy_from_skb(struct xdr_buf *, unsigned int,
                 skb_reader_t *, skb_read_actor_t);
 
-struct socket;
-struct sockaddr;
-extern int xdr_sendpages(struct socket *, struct sockaddr *, int,
-                struct xdr_buf *, unsigned int, int);
-
 extern int xdr_encode_word(struct xdr_buf *, int, u32);
 extern int xdr_decode_word(struct xdr_buf *, int, u32 *);
 
diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
index e618c1649814..3b8b6e823c70 100644
--- a/include/linux/sunrpc/xprt.h
+++ b/include/linux/sunrpc/xprt.h
@@ -1,5 +1,5 @@
 /*
- *  linux/include/linux/sunrpc/clnt_xprt.h
+ *  linux/include/linux/sunrpc/xprt.h
  *
  *  Declarations for the RPC transport interface.
  *
@@ -15,20 +15,6 @@
 #include <linux/sunrpc/sched.h>
 #include <linux/sunrpc/xdr.h>
 
-/*
- * The transport code maintains an estimate on the maximum number of out-
- * standing RPC requests, using a smoothed version of the congestion
- * avoidance implemented in 44BSD. This is basically the Van Jacobson
- * congestion algorithm: If a retransmit occurs, the congestion window is
- * halved; otherwise, it is incremented by 1/cwnd when
- *
- *      -       a reply is received and
- *      -       a full number of requests are outstanding and
- *      -       the congestion window hasn't been updated recently.
- *
- * Upper procedures may check whether a request would block waiting for
- * a free RPC slot by using the RPC_CONGESTED() macro.
- */
 extern unsigned int xprt_udp_slot_table_entries;
 extern unsigned int xprt_tcp_slot_table_entries;
 
@@ -36,34 +22,23 @@ extern unsigned int xprt_tcp_slot_table_entries;
 #define RPC_DEF_SLOT_TABLE      (16U)
 #define RPC_MAX_SLOT_TABLE      (128U)
 
-#define RPC_CWNDSHIFT           (8U)
-#define RPC_CWNDSCALE           (1U << RPC_CWNDSHIFT)
-#define RPC_INITCWND            RPC_CWNDSCALE
-#define RPC_MAXCWND(xprt)       ((xprt)->max_reqs << RPC_CWNDSHIFT)
-#define RPCXPRT_CONGESTED(xprt) ((xprt)->cong >= (xprt)->cwnd)
-
-/* Default timeout values */
-#define RPC_MAX_UDP_TIMEOUT     (60*HZ)
-#define RPC_MAX_TCP_TIMEOUT     (600*HZ)
-
 /*
- * Wait duration for an RPC TCP connection to be established.  Solaris
- * NFS over TCP uses 60 seconds, for example, which is in line with how
- * long a server takes to reboot.
+ * RPC call and reply header size as number of 32bit words (verifier
+ * size computed separately)
  */
-#define RPC_CONNECT_TIMEOUT     (60*HZ)
+#define RPC_CALLHDRSIZE         6
+#define RPC_REPHDRSIZE          4
 
 /*
- * Delay an arbitrary number of seconds before attempting to reconnect
- * after an error.
+ * Parameters for choosing a free port
  */
-#define RPC_REESTABLISH_TIMEOUT (15*HZ)
+extern unsigned int xprt_min_resvport;
+extern unsigned int xprt_max_resvport;
 
-/* RPC call and reply header size as number of 32bit words (verifier
- * size computed separately)
- */
-#define RPC_CALLHDRSIZE         6
-#define RPC_REPHDRSIZE          4
+#define RPC_MIN_RESVPORT        (1U)
+#define RPC_MAX_RESVPORT        (65535U)
+#define RPC_DEF_MIN_RESVPORT    (650U)
+#define RPC_DEF_MAX_RESVPORT    (1023U)
 
 /*
  * This describes a timeout strategy
@@ -76,6 +51,9 @@ struct rpc_timeout {
         unsigned char           to_exponential;
 };
 
+struct rpc_task;
+struct rpc_xprt;
+
 /*
  * This describes a complete RPC request
  */
@@ -95,7 +73,10 @@ struct rpc_rqst {
         int                     rq_cong;        /* has incremented xprt->cong */
         int                     rq_received;    /* receive completed */
         u32                     rq_seqno;       /* gss seq no. used on req. */
-
+        int                     rq_enc_pages_num;
+        struct page             **rq_enc_pages; /* scratch pages for use by
+                                                   gss privacy code */
+        void (*rq_release_snd_buf)(struct rpc_rqst *); /* release rq_enc_pages */
         struct list_head        rq_list;
 
         struct xdr_buf          rq_private_buf;         /* The receive buffer
@@ -121,12 +102,21 @@ struct rpc_rqst {
 #define rq_svec                 rq_snd_buf.head
 #define rq_slen                 rq_snd_buf.len
 
-#define XPRT_LAST_FRAG          (1 << 0)
-#define XPRT_COPY_RECM          (1 << 1)
-#define XPRT_COPY_XID           (1 << 2)
-#define XPRT_COPY_DATA          (1 << 3)
+struct rpc_xprt_ops {
+        void            (*set_buffer_size)(struct rpc_xprt *xprt, size_t sndsize, size_t rcvsize);
+        int             (*reserve_xprt)(struct rpc_task *task);
+        void            (*release_xprt)(struct rpc_xprt *xprt, struct rpc_task *task);
+        void            (*connect)(struct rpc_task *task);
+        int             (*send_request)(struct rpc_task *task);
+        void            (*set_retrans_timeout)(struct rpc_task *task);
+        void            (*timer)(struct rpc_task *task);
+        void            (*release_request)(struct rpc_task *task);
+        void            (*close)(struct rpc_xprt *xprt);
+        void            (*destroy)(struct rpc_xprt *xprt);
+};
 
 struct rpc_xprt {
+        struct rpc_xprt_ops *   ops;            /* transport methods */
         struct socket *         sock;           /* BSD socket layer */
         struct sock *           inet;           /* INET layer */
 
@@ -137,11 +127,13 @@ struct rpc_xprt {
         unsigned long           cong;           /* current congestion */
         unsigned long           cwnd;           /* congestion window */
 
-        unsigned int            rcvsize,        /* socket receive buffer size */
-                                sndsize;        /* socket send buffer size */
+        size_t                  rcvsize,        /* transport rcv buffer size */
+                                sndsize;        /* transport send buffer size */
 
         size_t                  max_payload;    /* largest RPC payload size,
                                                    in bytes */
+        unsigned int            tsh_size;       /* size of transport specific
+                                                   header */
 
         struct rpc_wait_queue   sending;        /* requests waiting to send */
         struct rpc_wait_queue   resend;         /* requests waiting to resend */
@@ -150,11 +142,9 @@ struct rpc_xprt {
         struct list_head        free;           /* free slots */
         struct rpc_rqst *       slot;           /* slot table storage */
         unsigned int            max_reqs;       /* total slots */
-        unsigned long           sockstate;      /* Socket state */
+        unsigned long           state;          /* transport state */
         unsigned char           shutdown   : 1, /* being shut down */
-                                nocong     : 1, /* no congestion control */
-                                resvport   : 1, /* use a reserved port */
-                                stream     : 1; /* TCP */
+                                resvport   : 1; /* use a reserved port */
 
         /*
          * XID
@@ -171,22 +161,27 @@ struct rpc_xprt {
         unsigned long           tcp_copied,     /* copied to request */
                                 tcp_flags;
         /*
-         * Connection of sockets
+         * Connection of transports
          */
-        struct work_struct      sock_connect;
+        unsigned long           connect_timeout,
+                                bind_timeout,
+                                reestablish_timeout;
+        struct work_struct      connect_worker;
         unsigned short          port;
+
         /*
-         * Disconnection of idle sockets
+         * Disconnection of idle transports
          */
         struct work_struct      task_cleanup;
         struct timer_list       timer;
-        unsigned long           last_used;
+        unsigned long           last_used,
+                                idle_timeout;
 
         /*
          * Send stuff
          */
-        spinlock_t              sock_lock;      /* lock socket info */
-        spinlock_t              xprt_lock;      /* lock xprt info */
+        spinlock_t              transport_lock; /* lock transport info */
+        spinlock_t              reserve_lock;   /* lock slot table */
         struct rpc_task *       snd_task;       /* Task blocked in send */
 
         struct list_head        recv;
@@ -195,37 +190,111 @@ struct rpc_xprt {
         void                    (*old_data_ready)(struct sock *, int);
         void                    (*old_state_change)(struct sock *);
         void                    (*old_write_space)(struct sock *);
-
-        wait_queue_head_t       cong_wait;
 };
 
+#define XPRT_LAST_FRAG          (1 << 0)
+#define XPRT_COPY_RECM          (1 << 1)
+#define XPRT_COPY_XID           (1 << 2)
+#define XPRT_COPY_DATA          (1 << 3)
+
 #ifdef __KERNEL__
 
-struct rpc_xprt *       xprt_create_proto(int proto, struct sockaddr_in *addr,
-                                        struct rpc_timeout *toparms);
-int                     xprt_destroy(struct rpc_xprt *);
-void                    xprt_set_timeout(struct rpc_timeout *, unsigned int,
-                                        unsigned long);
+/*
+ * Transport operations used by ULPs
+ */
+struct rpc_xprt *       xprt_create_proto(int proto, struct sockaddr_in *addr, struct rpc_timeout *to);
+void                    xprt_set_timeout(struct rpc_timeout *to, unsigned int retr, unsigned long incr);
 
-void                    xprt_reserve(struct rpc_task *);
-int                     xprt_prepare_transmit(struct rpc_task *);
-void                    xprt_transmit(struct rpc_task *);
-void                    xprt_receive(struct rpc_task *);
+/*
+ * Generic internal transport functions
+ */
+void                    xprt_connect(struct rpc_task *task);
+void                    xprt_reserve(struct rpc_task *task);
+int                     xprt_reserve_xprt(struct rpc_task *task);
+int                     xprt_reserve_xprt_cong(struct rpc_task *task);
+int                     xprt_prepare_transmit(struct rpc_task *task);
+void                    xprt_transmit(struct rpc_task *task);
+void                    xprt_abort_transmit(struct rpc_task *task);
 int                     xprt_adjust_timeout(struct rpc_rqst *req);
-void                    xprt_release(struct rpc_task *);
-void                    xprt_connect(struct rpc_task *);
-void                    xprt_sock_setbufsize(struct rpc_xprt *);
-
-#define XPRT_LOCKED     0
-#define XPRT_CONNECT    1
-#define XPRT_CONNECTING 2
-
-#define xprt_connected(xp)              (test_bit(XPRT_CONNECT, &(xp)->sockstate))
-#define xprt_set_connected(xp)          (set_bit(XPRT_CONNECT, &(xp)->sockstate))
-#define xprt_test_and_set_connected(xp) (test_and_set_bit(XPRT_CONNECT, &(xp)->sockstate))
-#define xprt_test_and_clear_connected(xp) \
-                                        (test_and_clear_bit(XPRT_CONNECT, &(xp)->sockstate))
-#define xprt_clear_connected(xp)        (clear_bit(XPRT_CONNECT, &(xp)->sockstate))
+void                    xprt_release_xprt(struct rpc_xprt *xprt, struct rpc_task *task);
+void                    xprt_release_xprt_cong(struct rpc_xprt *xprt, struct rpc_task *task);
+void                    xprt_release(struct rpc_task *task);
+int                     xprt_destroy(struct rpc_xprt *xprt);
+
+static inline u32 *xprt_skip_transport_header(struct rpc_xprt *xprt, u32 *p)
+{
+        return p + xprt->tsh_size;
+}
+
+/*
+ * Transport switch helper functions
+ */
+void                    xprt_set_retrans_timeout_def(struct rpc_task *task);
+void                    xprt_set_retrans_timeout_rtt(struct rpc_task *task);
+void                    xprt_wake_pending_tasks(struct rpc_xprt *xprt, int status);
+void                    xprt_wait_for_buffer_space(struct rpc_task *task);
+void                    xprt_write_space(struct rpc_xprt *xprt);
+void                    xprt_update_rtt(struct rpc_task *task);
+void                    xprt_adjust_cwnd(struct rpc_task *task, int result);
+struct rpc_rqst *       xprt_lookup_rqst(struct rpc_xprt *xprt, u32 xid);
+void                    xprt_complete_rqst(struct rpc_task *task, int copied);
+void                    xprt_release_rqst_cong(struct rpc_task *task);
+void                    xprt_disconnect(struct rpc_xprt *xprt);
+
+/*
+ * Socket transport setup operations
+ */
+int                     xs_setup_udp(struct rpc_xprt *xprt, struct rpc_timeout *to);
+int                     xs_setup_tcp(struct rpc_xprt *xprt, struct rpc_timeout *to);
+
+/*
+ * Reserved bit positions in xprt->state
+ */
+#define XPRT_LOCKED             (0)
+#define XPRT_CONNECTED          (1)
+#define XPRT_CONNECTING         (2)
+
+static inline void xprt_set_connected(struct rpc_xprt *xprt)
+{
+        set_bit(XPRT_CONNECTED, &xprt->state);
+}
+
+static inline void xprt_clear_connected(struct rpc_xprt *xprt)
+{
+        clear_bit(XPRT_CONNECTED, &xprt->state);
+}
+
+static inline int xprt_connected(struct rpc_xprt *xprt)
+{
+        return test_bit(XPRT_CONNECTED, &xprt->state);
+}
+
+static inline int xprt_test_and_set_connected(struct rpc_xprt *xprt)
+{
+        return test_and_set_bit(XPRT_CONNECTED, &xprt->state);
+}
+
+static inline int xprt_test_and_clear_connected(struct rpc_xprt *xprt)
+{
+        return test_and_clear_bit(XPRT_CONNECTED, &xprt->state);
+}
+
+static inline void xprt_clear_connecting(struct rpc_xprt *xprt)
+{
+        smp_mb__before_clear_bit();
+        clear_bit(XPRT_CONNECTING, &xprt->state);
+        smp_mb__after_clear_bit();
+}
+
+static inline int xprt_connecting(struct rpc_xprt *xprt)
+{
+        return test_bit(XPRT_CONNECTING, &xprt->state);
+}
+
+static inline int xprt_test_and_set_connecting(struct rpc_xprt *xprt)
+{
+        return test_and_set_bit(XPRT_CONNECTING, &xprt->state);
+}
 
 #endif /* __KERNEL__*/
 
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index ad15a54806d8..a61c04f804b2 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -71,7 +71,12 @@ void restore_processor_state(void);
 struct saved_context;
 void __save_processor_state(struct saved_context *ctxt);
 void __restore_processor_state(struct saved_context *ctxt);
-extern unsigned long get_usable_page(unsigned gfp_mask);
-extern void free_eaten_memory(void);
+unsigned long get_safe_page(gfp_t gfp_mask);
+
+/*
+ * XXX: We try to keep some more pages free so that I/O operations succeed
+ * without paging. Might this be more?
+ */
+#define PAGES_FOR_IO    512
 
 #endif /* _LINUX_SWSUSP_H */
diff --git a/include/linux/swap.h b/include/linux/swap.h
index a7bf1a3b1496..20c975642cab 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -171,8 +171,8 @@ extern int rotate_reclaimable_page(struct page *page);
 extern void swap_setup(void);
 
 /* linux/mm/vmscan.c */
-extern int try_to_free_pages(struct zone **, unsigned int);
-extern int zone_reclaim(struct zone *, unsigned int, unsigned int);
+extern int try_to_free_pages(struct zone **, gfp_t);
+extern int zone_reclaim(struct zone *, gfp_t, unsigned int);
 extern int shrink_all_memory(int);
 extern int vm_swappiness;
 
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index a6f03e473737..c7007b1db91d 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -491,6 +491,7 @@ asmlinkage long sys_nfsservctl(int cmd,
 asmlinkage long sys_syslog(int type, char __user *buf, int len);
 asmlinkage long sys_uselib(const char __user *library);
 asmlinkage long sys_ni_syscall(void);
+asmlinkage long sys_ptrace(long request, long pid, long addr, long data);
 
 asmlinkage long sys_add_key(const char __user *_type,
                             const char __user *_description,
diff --git a/include/linux/textsearch.h b/include/linux/textsearch.h
index 515046d1b2f4..7dac8f04d28e 100644
--- a/include/linux/textsearch.h
+++ b/include/linux/textsearch.h
@@ -8,6 +8,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 
 struct ts_config;
 
@@ -40,7 +41,7 @@ struct ts_state
 struct ts_ops
 {
         const char              *name;
-        struct ts_config *      (*init)(const void *, unsigned int, int);
+        struct ts_config *      (*init)(const void *, unsigned int, gfp_t);
         unsigned int            (*find)(struct ts_config *,
                                         struct ts_state *);
         void                    (*destroy)(struct ts_config *);
@@ -148,7 +149,7 @@ static inline unsigned int textsearch_get_pattern_len(struct ts_config *conf)
 extern int textsearch_register(struct ts_ops *);
 extern int textsearch_unregister(struct ts_ops *);
 extern struct ts_config *textsearch_prepare(const char *, const void *,
-                                            unsigned int, int, int);
+                                            unsigned int, gfp_t, int);
 extern void textsearch_destroy(struct ts_config *conf);
 extern unsigned int textsearch_find_continuous(struct ts_config *,
                                                struct ts_state *,
diff --git a/include/linux/timer.h b/include/linux/timer.h
index 3340f3bd135d..72f3a7781106 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -12,16 +12,12 @@ struct timer_list {
         struct list_head entry;
         unsigned long expires;
 
-        unsigned long magic;
-
         void (*function)(unsigned long);
         unsigned long data;
 
         struct timer_base_s *base;
 };
 
-#define TIMER_MAGIC     0x4b87ad6e
-
 extern struct timer_base_s __init_timer_base;
 
 #define TIMER_INITIALIZER(_function, _expires, _data) {         \
@@ -29,7 +25,6 @@ extern struct timer_base_s __init_timer_base;
                 .expires = (_expires),                          \
                 .data = (_data),                                \
                 .base = &__init_timer_base,                     \
-                .magic = TIMER_MAGIC,                           \
         }
 
 #define DEFINE_TIMER(_name, _function, _expires, _data)         \
@@ -38,6 +33,15 @@ extern struct timer_base_s __init_timer_base;
 
 void fastcall init_timer(struct timer_list * timer);
 
+static inline void setup_timer(struct timer_list * timer,
+                                void (*function)(unsigned long),
+                                unsigned long data)
+{
+        timer->function = function;
+        timer->data = data;
+        init_timer(timer);
+}
+
 /***
  * timer_pending - is a timer pending?
  * @timer: the timer in question
@@ -74,8 +78,9 @@ extern unsigned long next_timer_interrupt(void);
  * Timers with an ->expired field in the past will be executed in the next
  * timer tick.
  */
-static inline void add_timer(struct timer_list * timer)
+static inline void add_timer(struct timer_list *timer)
 {
+        BUG_ON(timer_pending(timer));
         __mod_timer(timer, timer->expires);
 }
 
diff --git a/include/linux/timex.h b/include/linux/timex.h
index 7e050a2cc35b..04a4a8cb4ed3 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -282,6 +282,13 @@ static inline int ntp_synced(void)
         return !(time_status & STA_UNSYNC);
 }
 
+/* Required to safely shift negative values */
+#define shift_right(x, s) ({    \
+        __typeof__(x) __x = (x);        \
+        __typeof__(s) __s = (s);        \
+        __x < 0 ? -(-__x >> __s) : __x >> __s;  \
+})
+
 
 #ifdef CONFIG_TIME_INTERPOLATION
 
diff --git a/include/linux/types.h b/include/linux/types.h
index 0aee34f9da9f..21b9ce803644 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -151,7 +151,12 @@ typedef unsigned long sector_t;
  */
 
 #ifdef __CHECKER__
-#define __bitwise __attribute__((bitwise))
+#define __bitwise__ __attribute__((bitwise))
+#else
+#define __bitwise__
+#endif
+#ifdef __CHECK_ENDIAN__
+#define __bitwise __bitwise__
 #else
 #define __bitwise
 #endif
@@ -166,7 +171,7 @@ typedef __u64 __bitwise __be64;
 #endif
 
 #ifdef __KERNEL__
-typedef unsigned __nocast gfp_t;
+typedef unsigned __bitwise__ gfp_t;
 #endif
 
 struct ustat {
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 4dbe580f9335..748d04385256 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -57,6 +57,7 @@ struct usb_host_endpoint {
         struct usb_endpoint_descriptor  desc;
         struct list_head                urb_list;
         void                            *hcpriv;
+        struct kobject                  *kobj;  /* For sysfs info */
 
         unsigned char *extra;   /* Extra descriptors */
         int extralen;
@@ -136,7 +137,8 @@ struct usb_interface {
                                          * active alternate setting */
         unsigned num_altsetting;        /* number of alternate settings */
 
-        int minor;                      /* minor number this interface is bound to */
+        int minor;                      /* minor number this interface is
+                                         * bound to */
         enum usb_interface_condition condition;         /* state of binding */
         struct device dev;              /* interface specific device info */
         struct class_device *class_dev;
@@ -229,7 +231,7 @@ struct usb_interface_cache {
 struct usb_host_config {
         struct usb_config_descriptor    desc;
 
-        char *string;
+        char *string;           /* iConfiguration string, if present */
         /* the interfaces associated with this configuration,
          * stored in no particular order */
         struct usb_interface *interface[USB_MAXINTERFACES];
@@ -248,7 +250,7 @@ int __usb_get_extra_descriptor(char *buffer, unsigned size,
         __usb_get_extra_descriptor((ifpoint)->extra,(ifpoint)->extralen,\
                 type,(void**)ptr)
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 struct usb_operations;
 
@@ -268,7 +270,8 @@ struct usb_bus {
         unsigned is_b_host:1;           /* true during some HNP roleswitches */
         unsigned b_hnp_enable:1;        /* OTG: did A-Host enable HNP? */
 
-        int devnum_next;                /* Next open device number in round-robin allocation */
+        int devnum_next;                /* Next open device number in
+                                         * round-robin allocation */
 
         struct usb_devmap devmap;       /* device address allocation map */
         struct usb_operations *op;      /* Operations (specific to the HC) */
@@ -289,15 +292,16 @@ struct usb_bus {
         struct dentry *usbfs_dentry;    /* usbfs dentry entry for the bus */
 
         struct class_device *class_dev; /* class device for this bus */
-        struct kref kref;               /* handles reference counting this bus */
-        void (*release)(struct usb_bus *bus);   /* function to destroy this bus's memory */
+        struct kref kref;               /* reference counting for this bus */
+        void (*release)(struct usb_bus *bus);
+
 #if defined(CONFIG_USB_MON)
         struct mon_bus *mon_bus;        /* non-null when associated */
         int monitored;                  /* non-zero when monitored */
 #endif
 };
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 /* This is arbitrary.
  * From USB 2.0 spec Table 11-13, offset 7, a hub can
@@ -326,7 +330,8 @@ struct usb_device {
 
         struct semaphore serialize;
 
-        unsigned int toggle[2];         /* one bit for each endpoint ([0] = IN, [1] = OUT) */
+        unsigned int toggle[2];         /* one bit for each endpoint
+                                         * ([0] = IN, [1] = OUT) */
 
         struct usb_device *parent;      /* our hub, unless we're the root */
         struct usb_bus *bus;            /* Bus we're part of */
@@ -343,12 +348,14 @@ struct usb_device {
 
         char **rawdescriptors;          /* Raw descriptors for each config */
 
-        int have_langid;                /* whether string_langid is valid yet */
+        int have_langid;                /* whether string_langid is valid */
         int string_langid;              /* language ID for strings */
 
-        char *product;
-        char *manufacturer;
-        char *serial;                   /* static strings from the device */
+        /* static strings from the device */
+        char *product;                  /* iProduct string, if present */
+        char *manufacturer;             /* iManufacturer string, if present */
+        char *serial;                   /* iSerialNumber string, if present */
+
         struct list_head filelist;
         struct class_device *class_dev;
         struct dentry *usbfs_dentry;    /* usbfs dentry entry for the device */
@@ -440,22 +447,31 @@ extern struct usb_host_interface *usb_altnum_to_altsetting(
  * USB 2.0 root hubs (EHCI host controllers) will get one path ID if they are
  * high speed, and a different one if they are full or low speed.
  */
-static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
+static inline int usb_make_path (struct usb_device *dev, char *buf,
+                size_t size)
 {
         int actual;
-        actual = snprintf (buf, size, "usb-%s-%s", dev->bus->bus_name, dev->devpath);
+        actual = snprintf (buf, size, "usb-%s-%s", dev->bus->bus_name,
+                        dev->devpath);
         return (actual >= (int)size) ? -1 : actual;
 }
 
 /*-------------------------------------------------------------------------*/
 
-#define USB_DEVICE_ID_MATCH_DEVICE              (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT)
-#define USB_DEVICE_ID_MATCH_DEV_RANGE           (USB_DEVICE_ID_MATCH_DEV_LO | USB_DEVICE_ID_MATCH_DEV_HI)
-#define USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION  (USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_RANGE)
+#define USB_DEVICE_ID_MATCH_DEVICE \
+                (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT)
+#define USB_DEVICE_ID_MATCH_DEV_RANGE \
+                (USB_DEVICE_ID_MATCH_DEV_LO | USB_DEVICE_ID_MATCH_DEV_HI)
+#define USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION \
+                (USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_RANGE)
 #define USB_DEVICE_ID_MATCH_DEV_INFO \
-        (USB_DEVICE_ID_MATCH_DEV_CLASS | USB_DEVICE_ID_MATCH_DEV_SUBCLASS | USB_DEVICE_ID_MATCH_DEV_PROTOCOL)
+                (USB_DEVICE_ID_MATCH_DEV_CLASS | \
+                USB_DEVICE_ID_MATCH_DEV_SUBCLASS | \
+                USB_DEVICE_ID_MATCH_DEV_PROTOCOL)
 #define USB_DEVICE_ID_MATCH_INT_INFO \
-        (USB_DEVICE_ID_MATCH_INT_CLASS | USB_DEVICE_ID_MATCH_INT_SUBCLASS | USB_DEVICE_ID_MATCH_INT_PROTOCOL)
+                (USB_DEVICE_ID_MATCH_INT_CLASS | \
+                USB_DEVICE_ID_MATCH_INT_SUBCLASS | \
+                USB_DEVICE_ID_MATCH_INT_PROTOCOL)
 
 /**
  * USB_DEVICE - macro used to describe a specific usb device
@@ -466,9 +482,11 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
  * specific device.
  */
 #define USB_DEVICE(vend,prod) \
-        .match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = (vend), .idProduct = (prod)
+        .match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = (vend), \
+                        .idProduct = (prod)
 /**
- * USB_DEVICE_VER - macro used to describe a specific usb device with a version range
+ * USB_DEVICE_VER - macro used to describe a specific usb device with a
+ *              version range
  * @vend: the 16 bit USB Vendor ID
  * @prod: the 16 bit USB Product ID
  * @lo: the bcdDevice_lo value
@@ -478,7 +496,9 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
  * specific device, with a version range.
  */
 #define USB_DEVICE_VER(vend,prod,lo,hi) \
-        .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION, .idVendor = (vend), .idProduct = (prod), .bcdDevice_lo = (lo), .bcdDevice_hi = (hi)
+        .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION, \
+        .idVendor = (vend), .idProduct = (prod), \
+        .bcdDevice_lo = (lo), .bcdDevice_hi = (hi)
 
 /**
  * USB_DEVICE_INFO - macro used to describe a class of usb devices
@@ -490,7 +510,8 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
  * specific class of devices.
  */
 #define USB_DEVICE_INFO(cl,sc,pr) \
-        .match_flags = USB_DEVICE_ID_MATCH_DEV_INFO, .bDeviceClass = (cl), .bDeviceSubClass = (sc), .bDeviceProtocol = (pr)
+        .match_flags = USB_DEVICE_ID_MATCH_DEV_INFO, .bDeviceClass = (cl), \
+        .bDeviceSubClass = (sc), .bDeviceProtocol = (pr)
 
 /**
  * USB_INTERFACE_INFO - macro used to describe a class of usb interfaces 
@@ -502,9 +523,10 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
  * specific class of interfaces.
  */
 #define USB_INTERFACE_INFO(cl,sc,pr) \
-        .match_flags = USB_DEVICE_ID_MATCH_INT_INFO, .bInterfaceClass = (cl), .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr)
+        .match_flags = USB_DEVICE_ID_MATCH_INT_INFO, .bInterfaceClass = (cl), \
+        .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr)
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 /**
  * struct usb_driver - identifies USB driver to usbcore
@@ -557,7 +579,8 @@ struct usb_driver {
 
         void (*disconnect) (struct usb_interface *intf);
 
-        int (*ioctl) (struct usb_interface *intf, unsigned int code, void *buf);
+        int (*ioctl) (struct usb_interface *intf, unsigned int code,
+                        void *buf);
 
         int (*suspend) (struct usb_interface *intf, pm_message_t message);
         int (*resume) (struct usb_interface *intf);
@@ -572,10 +595,8 @@ extern struct bus_type usb_bus_type;
 
 /**
  * struct usb_class_driver - identifies a USB driver that wants to use the USB major number
- * @name: devfs name for this driver.  Will also be used by the driver
- *      class code to create a usb class device.
+ * @name: the usb class device name for this driver.  Will show up in sysfs.
  * @fops: pointer to the struct file_operations of this driver.
- * @mode: the mode for the devfs file to be created for this driver.
  * @minor_base: the start of the minor range for this driver.
  *
  * This structure is used for the usb_register_dev() and
@@ -585,8 +606,7 @@ extern struct bus_type usb_bus_type;
 struct usb_class_driver {
         char *name;
         struct file_operations *fops;
-        mode_t mode;
-        int minor_base; 
+        int minor_base;
 };
 
 /*
@@ -603,7 +623,7 @@ extern void usb_deregister_dev(struct usb_interface *intf,
 
 extern int usb_disabled(void);
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 /*
  * URB support, for asynchronous request completions
@@ -613,12 +633,14 @@ extern int usb_disabled(void);
  * urb->transfer_flags:
  */
 #define URB_SHORT_NOT_OK        0x0001  /* report short reads as errors */
-#define URB_ISO_ASAP            0x0002  /* iso-only, urb->start_frame ignored */
+#define URB_ISO_ASAP            0x0002  /* iso-only, urb->start_frame
+                                         * ignored */
 #define URB_NO_TRANSFER_DMA_MAP 0x0004  /* urb->transfer_dma valid on submit */
 #define URB_NO_SETUP_DMA_MAP    0x0008  /* urb->setup_dma valid on submit */
 #define URB_NO_FSBR             0x0020  /* UHCI-specific */
-#define URB_ZERO_PACKET         0x0040  /* Finish bulk OUTs with short packet */
-#define URB_NO_INTERRUPT        0x0080  /* HINT: no non-error interrupt needed */
+#define URB_ZERO_PACKET         0x0040  /* Finish bulk OUT with short packet */
+#define URB_NO_INTERRUPT        0x0080  /* HINT: no non-error interrupt
+                                         * needed */
 
 struct usb_iso_packet_descriptor {
         unsigned int offset;
@@ -806,7 +828,8 @@ struct urb
         u8 reject;                      /* submissions will fail */
 
         /* public, documented fields in the urb that can be used by drivers */
-        struct list_head urb_list;      /* list head for use by the urb owner */
+        struct list_head urb_list;      /* list head for use by the urb's
+                                         * current owner */
         struct usb_device *dev;         /* (in) pointer to associated device */
         unsigned int pipe;              /* (in) pipe information */
         int status;                     /* (return) non-ISO status */
@@ -819,14 +842,16 @@ struct urb
         dma_addr_t setup_dma;           /* (in) dma addr for setup_packet */
         int start_frame;                /* (modify) start frame (ISO) */
         int number_of_packets;          /* (in) number of ISO packets */
-        int interval;                   /* (modify) transfer interval (INT/ISO) */
+        int interval;                   /* (modify) transfer interval
+                                         * (INT/ISO) */
         int error_count;                /* (return) number of ISO errors */
         void *context;                  /* (in) context for completion */
         usb_complete_t complete;        /* (in) completion routine */
-        struct usb_iso_packet_descriptor iso_frame_desc[0];     /* (in) ISO ONLY */
+        struct usb_iso_packet_descriptor iso_frame_desc[0];
+                                        /* (in) ISO ONLY */
 };
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 /**
  * usb_fill_control_urb - initializes a control urb
@@ -933,17 +958,17 @@ static inline void usb_fill_int_urb (struct urb *urb,
 }
 
 extern void usb_init_urb(struct urb *urb);
-extern struct urb *usb_alloc_urb(int iso_packets, unsigned mem_flags);
+extern struct urb *usb_alloc_urb(int iso_packets, gfp_t mem_flags);
 extern void usb_free_urb(struct urb *urb);
 #define usb_put_urb usb_free_urb
 extern struct urb *usb_get_urb(struct urb *urb);
-extern int usb_submit_urb(struct urb *urb, unsigned mem_flags);
+extern int usb_submit_urb(struct urb *urb, gfp_t mem_flags);
 extern int usb_unlink_urb(struct urb *urb);
 extern void usb_kill_urb(struct urb *urb);
 
 #define HAVE_USB_BUFFERS
 void *usb_buffer_alloc (struct usb_device *dev, size_t size,
-        unsigned mem_flags, dma_addr_t *dma);
+        gfp_t mem_flags, dma_addr_t *dma);
 void usb_buffer_free (struct usb_device *dev, size_t size,
         void *addr, dma_addr_t dma);
 
@@ -974,11 +999,6 @@ extern int usb_bulk_msg(struct usb_device *usb_dev, unsigned int pipe,
         void *data, int len, int *actual_length,
         int timeout);
 
-/* selective suspend/resume */
-extern int usb_suspend_device(struct usb_device *dev, pm_message_t message);
-extern int usb_resume_device(struct usb_device *dev);
-
-
 /* wrappers around usb_control_msg() for the most common standard requests */
 extern int usb_get_descriptor(struct usb_device *dev, unsigned char desctype,
         unsigned char descindex, void *buf, int size);
@@ -1050,13 +1070,13 @@ int usb_sg_init (
         struct scatterlist      *sg,
         int                     nents,
         size_t                  length,
-        unsigned                mem_flags
+        gfp_t                   mem_flags
 );
 void usb_sg_cancel (struct usb_sg_request *io);
 void usb_sg_wait (struct usb_sg_request *io);
 
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 /*
  * For various legacy reasons, Linux has a small cookie that's paired with
@@ -1097,23 +1117,34 @@ void usb_sg_wait (struct usb_sg_request *io);
 /* The D0/D1 toggle bits ... USE WITH CAUTION (they're almost hcd-internal) */
 #define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> (ep)) & 1)
 #define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << (ep)))
-#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << (ep))) | ((bit) << (ep)))
+#define usb_settoggle(dev, ep, out, bit) \
+                ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << (ep))) | \
+                 ((bit) << (ep)))
 
 
-static inline unsigned int __create_pipe(struct usb_device *dev, unsigned int endpoint)
+static inline unsigned int __create_pipe(struct usb_device *dev,
+                unsigned int endpoint)
 {
         return (dev->devnum << 8) | (endpoint << 15);
 }
 
 /* Create various pipes... */
-#define usb_sndctrlpipe(dev,endpoint)   ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint))
-#define usb_rcvctrlpipe(dev,endpoint)   ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndisocpipe(dev,endpoint)   ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint))
-#define usb_rcvisocpipe(dev,endpoint)   ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndbulkpipe(dev,endpoint)   ((PIPE_BULK << 30) | __create_pipe(dev,endpoint))
-#define usb_rcvbulkpipe(dev,endpoint)   ((PIPE_BULK << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndintpipe(dev,endpoint)    ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint))
-#define usb_rcvintpipe(dev,endpoint)    ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndctrlpipe(dev,endpoint)   \
+        ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvctrlpipe(dev,endpoint)   \
+        ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndisocpipe(dev,endpoint)   \
+        ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvisocpipe(dev,endpoint)   \
+        ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndbulkpipe(dev,endpoint)   \
+        ((PIPE_BULK << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvbulkpipe(dev,endpoint)   \
+        ((PIPE_BULK << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndintpipe(dev,endpoint)    \
+        ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvintpipe(dev,endpoint)    \
+        ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
 
 /*-------------------------------------------------------------------------*/
 
@@ -1137,17 +1168,29 @@ usb_maxpacket(struct usb_device *udev, int pipe, int is_out)
         return le16_to_cpu(ep->desc.wMaxPacketSize);
 }
 
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
+
+/* Events from the usb core */
+#define USB_DEVICE_ADD          0x0001
+#define USB_DEVICE_REMOVE       0x0002
+#define USB_BUS_ADD             0x0003
+#define USB_BUS_REMOVE          0x0004
+extern void usb_register_notify(struct notifier_block *nb);
+extern void usb_unregister_notify(struct notifier_block *nb);
 
 #ifdef DEBUG
-#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , __FILE__ , ## arg)
+#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , \
+        __FILE__ , ## arg)
 #else
 #define dbg(format, arg...) do {} while (0)
 #endif
 
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , __FILE__ , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n" , __FILE__ , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n" , __FILE__ , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , \
+        __FILE__ , ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n" , \
+        __FILE__ , ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n" , \
+        __FILE__ , ## arg)
 
 
 #endif  /* __KERNEL__ */
diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h
index 71e608607324..ff81117eb733 100644
--- a/include/linux/usb_gadget.h
+++ b/include/linux/usb_gadget.h
@@ -107,18 +107,18 @@ struct usb_ep_ops {
         int (*disable) (struct usb_ep *ep);
 
         struct usb_request *(*alloc_request) (struct usb_ep *ep,
-                unsigned gfp_flags);
+                gfp_t gfp_flags);
         void (*free_request) (struct usb_ep *ep, struct usb_request *req);
 
         void *(*alloc_buffer) (struct usb_ep *ep, unsigned bytes,
-                dma_addr_t *dma, unsigned gfp_flags);
+                dma_addr_t *dma, gfp_t gfp_flags);
         void (*free_buffer) (struct usb_ep *ep, void *buf, dma_addr_t dma,
                 unsigned bytes);
         // NOTE:  on 2.6, drivers may also use dma_map() and
         // dma_sync_single_*() to directly manage dma overhead. 
 
         int (*queue) (struct usb_ep *ep, struct usb_request *req,
-                unsigned gfp_flags);
+                gfp_t gfp_flags);
         int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
 
         int (*set_halt) (struct usb_ep *ep, int value);
@@ -214,7 +214,7 @@ usb_ep_disable (struct usb_ep *ep)
  * Returns the request, or null if one could not be allocated.
  */
 static inline struct usb_request *
-usb_ep_alloc_request (struct usb_ep *ep, unsigned gfp_flags)
+usb_ep_alloc_request (struct usb_ep *ep, gfp_t gfp_flags)
 {
         return ep->ops->alloc_request (ep, gfp_flags);
 }
@@ -254,7 +254,7 @@ usb_ep_free_request (struct usb_ep *ep, struct usb_request *req)
  */
 static inline void *
 usb_ep_alloc_buffer (struct usb_ep *ep, unsigned len, dma_addr_t *dma,
-        unsigned gfp_flags)
+        gfp_t gfp_flags)
 {
         return ep->ops->alloc_buffer (ep, len, dma, gfp_flags);
 }
@@ -330,7 +330,7 @@ usb_ep_free_buffer (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned len)
  * reported when the usb peripheral is disconnected.
  */
 static inline int
-usb_ep_queue (struct usb_ep *ep, struct usb_request *req, unsigned gfp_flags)
+usb_ep_queue (struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags)
 {
         return ep->ops->queue (ep, req, gfp_flags);
 }
diff --git a/include/linux/usb_otg.h b/include/linux/usb_otg.h
index c6683146e9b0..f827f6e203c2 100644
--- a/include/linux/usb_otg.h
+++ b/include/linux/usb_otg.h
@@ -63,6 +63,10 @@ struct otg_transceiver {
         int     (*set_power)(struct otg_transceiver *otg,
                                 unsigned mA);
 
+        /* for non-OTG B devices: set transceiver into suspend mode */
+        int     (*set_suspend)(struct otg_transceiver *otg,
+                                int suspend);
+
         /* for B devices only:  start session with A-Host */
         int     (*start_srp)(struct otg_transceiver *otg);
 
@@ -108,6 +112,15 @@ otg_set_power(struct otg_transceiver *otg, unsigned mA)
 }
 
 static inline int
+otg_set_suspend(struct otg_transceiver *otg, int suspend)
+{
+        if (otg->set_suspend != NULL)
+                return otg->set_suspend(otg, suspend);
+        else
+                return 0;
+}
+
+static inline int
 otg_start_srp(struct otg_transceiver *otg)
 {
         return otg->start_srp(otg);
diff --git a/include/linux/usbdevice_fs.h b/include/linux/usbdevice_fs.h
index 9facf733800c..8859f0b41543 100644
--- a/include/linux/usbdevice_fs.h
+++ b/include/linux/usbdevice_fs.h
@@ -140,6 +140,12 @@ struct usbdevfs_urb32 {
         compat_caddr_t usercontext; /* unused */
         struct usbdevfs_iso_packet_desc iso_frame_desc[0];
 };
+
+struct usbdevfs_ioctl32 {
+        s32 ifno;
+        s32 ioctl_code;
+        compat_caddr_t data;
+};
 #endif
 
 #define USBDEVFS_CONTROL           _IOWR('U', 0, struct usbdevfs_ctrltransfer)
@@ -160,6 +166,7 @@ struct usbdevfs_urb32 {
 #define USBDEVFS_RELEASEINTERFACE  _IOR('U', 16, unsigned int)
 #define USBDEVFS_CONNECTINFO       _IOW('U', 17, struct usbdevfs_connectinfo)
 #define USBDEVFS_IOCTL             _IOWR('U', 18, struct usbdevfs_ioctl)
+#define USBDEVFS_IOCTL32           _IOWR('U', 18, struct usbdevfs_ioctl32)
 #define USBDEVFS_HUB_PORTINFO      _IOR('U', 19, struct usbdevfs_hub_portinfo)
 #define USBDEVFS_RESET             _IO('U', 20)
 #define USBDEVFS_CLEAR_HALT        _IOR('U', 21, unsigned int)
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 3701a0673d2c..1d5577b2b752 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -32,10 +32,14 @@ struct vm_struct {
  *      Highlevel APIs for driver use
  */
 extern void *vmalloc(unsigned long size);
+extern void *vmalloc_node(unsigned long size, int node);
 extern void *vmalloc_exec(unsigned long size);
 extern void *vmalloc_32(unsigned long size);
 extern void *__vmalloc(unsigned long size, gfp_t gfp_mask, pgprot_t prot);
-extern void *__vmalloc_area(struct vm_struct *area, gfp_t gfp_mask, pgprot_t prot);
+extern void *__vmalloc_area(struct vm_struct *area, gfp_t gfp_mask,
+                                pgprot_t prot);
+extern void *__vmalloc_node(unsigned long size, gfp_t gfp_mask,
+                                pgprot_t prot, int node);
 extern void vfree(void *addr);
 
 extern void *vmap(struct page **pages, unsigned int count,
@@ -48,6 +52,8 @@ extern void vunmap(void *addr);
 extern struct vm_struct *get_vm_area(unsigned long size, unsigned long flags);
 extern struct vm_struct *__get_vm_area(unsigned long size, unsigned long flags,
                                         unsigned long start, unsigned long end);
+extern struct vm_struct *get_vm_area_node(unsigned long size,
+                                        unsigned long flags, int node);
 extern struct vm_struct *remove_vm_area(void *addr);
 extern struct vm_struct *__remove_vm_area(void *addr);
 extern int map_vm_area(struct vm_struct *area, pgprot_t prot,
diff --git a/include/linux/wanpipe.h b/include/linux/wanpipe.h
index 167d956c492b..dae9860091dd 100644
--- a/include/linux/wanpipe.h
+++ b/include/linux/wanpipe.h
@@ -265,15 +265,6 @@ typedef struct {
 #include <linux/tty_driver.h>
 #include <linux/tty_flip.h>
 
-
-#define is_digit(ch) (((ch)>=(unsigned)'0'&&(ch)<=(unsigned)'9')?1:0)
-#define is_alpha(ch) ((((ch)>=(unsigned)'a'&&(ch)<=(unsigned)'z')||\
-                  ((ch)>=(unsigned)'A'&&(ch)<=(unsigned)'Z'))?1:0)
-#define is_hex_digit(ch) ((((ch)>=(unsigned)'0'&&(ch)<=(unsigned)'9')||\
-                  ((ch)>=(unsigned)'a'&&(ch)<=(unsigned)'f')||\
-                  ((ch)>=(unsigned)'A'&&(ch)<=(unsigned)'F'))?1:0)
-
-
 /****** Data Structures *****************************************************/
 
 /* Adapter Data Space.
diff --git a/include/linux/x1205.h b/include/linux/x1205.h
new file mode 100644
index 000000000000..64fd3af894a5
--- /dev/null
+++ b/include/linux/x1205.h
@@ -0,0 +1,31 @@
+/*
+ *  x1205.h - defines for drivers/i2c/chips/x1205.c
+ *  Copyright 2004 Karen Spearel
+ *  Copyright 2005 Alessandro Zummo
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+
+#ifndef __LINUX_X1205_H__
+#define __LINUX_X1205_H__
+
+/* commands */
+
+#define X1205_CMD_GETDATETIME   0
+#define X1205_CMD_SETTIME       1
+#define X1205_CMD_SETDATETIME   2
+#define X1205_CMD_GETALARM      3
+#define X1205_CMD_SETALARM      4
+#define X1205_CMD_GETDTRIM      5
+#define X1205_CMD_SETDTRIM      6
+#define X1205_CMD_GETATRIM      7
+#define X1205_CMD_SETATRIM      8
+
+extern int x1205_do_command(unsigned int cmd, void *arg);
+extern int x1205_direct_attach(int adapter_id,
+        struct i2c_client_address_data *address_data);
+
+#endif /* __LINUX_X1205_H__ */
diff --git a/include/linux/zutil.h b/include/linux/zutil.h
index fdfd5ed41ec4..ee0c59cf2136 100644
--- a/include/linux/zutil.h
+++ b/include/linux/zutil.h
@@ -15,7 +15,6 @@
 
 #include <linux/zlib.h>
 #include <linux/string.h>
-#include <linux/errno.h>
 #include <linux/kernel.h>
 
 typedef unsigned char  uch;
diff --git a/include/media/ovcamchip.h b/include/media/ovcamchip.h
index cb7c0aa96f22..8138983adced 100644
--- a/include/media/ovcamchip.h
+++ b/include/media/ovcamchip.h
@@ -17,20 +17,6 @@
 #include <linux/videodev.h>
 #include <linux/i2c.h>
 
-/* Remove these once they are officially defined */
-#ifndef I2C_DRIVERID_OVCAMCHIP
-        #define I2C_DRIVERID_OVCAMCHIP  0xf00f
-#endif
-#ifndef I2C_HW_SMBUS_OV511
-        #define I2C_HW_SMBUS_OV511      0xfe
-#endif
-#ifndef I2C_HW_SMBUS_OV518
-        #define I2C_HW_SMBUS_OV518      0xff
-#endif
-#ifndef I2C_HW_SMBUS_OVFX2
-        #define I2C_HW_SMBUS_OVFX2      0xfd
-#endif
-
 /* --------------------------------- */
 /*           ENUMERATIONS            */
 /* --------------------------------- */
diff --git a/include/net/ax25.h b/include/net/ax25.h
index 9dbcd9e51c00..2250a18b0cbb 100644
--- a/include/net/ax25.h
+++ b/include/net/ax25.h
@@ -171,7 +171,7 @@ typedef struct {
         ax25_address            calls[AX25_MAX_DIGIS];
         unsigned char           repeated[AX25_MAX_DIGIS];
         unsigned char           ndigi;
-        char                    lastrepeat;
+        signed char             lastrepeat;
 } ax25_digi;
 
 typedef struct ax25_route {
@@ -237,8 +237,7 @@ typedef struct ax25_cb {
 static __inline__ void ax25_cb_put(ax25_cb *ax25)
 {
         if (atomic_dec_and_test(&ax25->refcount)) {
-                if (ax25->digipeat)
-                        kfree(ax25->digipeat);
+                kfree(ax25->digipeat);
                 kfree(ax25);
         }
 }
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 210458624840..e42d728b1620 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -171,4 +171,10 @@ static inline int skb_frags_no(struct sk_buff *skb)
 
 int bt_err(__u16 code);
 
+extern int hci_sock_init(void);
+extern int hci_sock_cleanup(void);
+
+extern int bt_sysfs_init(void);
+extern void bt_sysfs_cleanup(void);
+
 #endif /* __BLUETOOTH_H */
diff --git a/include/net/bluetooth/rfcomm.h b/include/net/bluetooth/rfcomm.h
index fbe557f7ea1d..e656be7c001a 100644
--- a/include/net/bluetooth/rfcomm.h
+++ b/include/net/bluetooth/rfcomm.h
@@ -275,9 +275,6 @@ static inline void rfcomm_session_hold(struct rfcomm_session *s)
         atomic_inc(&s->refcnt);
 }
 
-/* ---- RFCOMM chechsum ---- */
-extern u8 rfcomm_crc_table[];
-
 /* ---- RFCOMM sockets ---- */
 struct sockaddr_rc {
         sa_family_t     rc_family;
diff --git a/include/net/dst.h b/include/net/dst.h
index 4a056a682435..6c196a5baf24 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -94,7 +94,6 @@ struct dst_ops
         struct dst_entry *      (*negative_advice)(struct dst_entry *);
         void                    (*link_failure)(struct sk_buff *);
         void                    (*update_pmtu)(struct dst_entry *dst, u32 mtu);
-        int                     (*get_mss)(struct dst_entry *dst, u32 mtu);
         int                     entry_size;
 
         atomic_t                entries;
diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h
index dc36b1be6745..5e38dca1d082 100644
--- a/include/net/ieee80211.h
+++ b/include/net/ieee80211.h
@@ -11,19 +11,26 @@
  *
  * Adaption to a generic IEEE 802.11 stack by James Ketrenos
  * <jketreno@linux.intel.com>
- * Copyright (c) 2004, Intel Corporation
+ * Copyright (c) 2004-2005, Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation. See README and COPYING for
  * more details.
+ *
+ * API Version History
+ * 1.0.x -- Initial version
+ * 1.1.x -- Added radiotap, QoS, TIM, ieee80211_geo APIs,
+ *          various structure changes, and crypto API init method
  */
 #ifndef IEEE80211_H
 #define IEEE80211_H
-#include <linux/if_ether.h> /* ETH_ALEN */
-#include <linux/kernel.h>   /* ARRAY_SIZE */
+#include <linux/if_ether.h>     /* ETH_ALEN */
+#include <linux/kernel.h>       /* ARRAY_SIZE */
 #include <linux/wireless.h>
 
+#define IEEE80211_VERSION "git-1.1.6"
+
 #define IEEE80211_DATA_LEN              2304
 /* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
    6.2.1.1.2.
@@ -33,34 +40,13 @@
    represents the 2304 bytes of real data, plus a possible 8 bytes of
    WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
 
-
-#define IEEE80211_HLEN                  30
-#define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
-
-struct ieee80211_hdr {
-        __le16 frame_ctl;
-        __le16 duration_id;
-        u8 addr1[ETH_ALEN];
-        u8 addr2[ETH_ALEN];
-        u8 addr3[ETH_ALEN];
-        __le16 seq_ctl;
-        u8 addr4[ETH_ALEN];
-} __attribute__ ((packed));
-
-struct ieee80211_hdr_3addr {
-        __le16 frame_ctl;
-        __le16 duration_id;
-        u8 addr1[ETH_ALEN];
-        u8 addr2[ETH_ALEN];
-        u8 addr3[ETH_ALEN];
-        __le16 seq_ctl;
-} __attribute__ ((packed));
-
 #define IEEE80211_1ADDR_LEN 10
 #define IEEE80211_2ADDR_LEN 16
 #define IEEE80211_3ADDR_LEN 24
 #define IEEE80211_4ADDR_LEN 30
 #define IEEE80211_FCS_LEN    4
+#define IEEE80211_HLEN                  (IEEE80211_4ADDR_LEN)
+#define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
 
 #define MIN_FRAG_THRESHOLD     256U
 #define MAX_FRAG_THRESHOLD     2346U
@@ -113,11 +99,11 @@ struct ieee80211_hdr_3addr {
 #define IEEE80211_STYPE_CFACK           0x0050
 #define IEEE80211_STYPE_CFPOLL          0x0060
 #define IEEE80211_STYPE_CFACKPOLL       0x0070
+#define IEEE80211_STYPE_QOS_DATA        0x0080
 
 #define IEEE80211_SCTL_FRAG             0x000F
 #define IEEE80211_SCTL_SEQ              0xFFF0
 
-
 /* debug macros */
 
 #ifdef CONFIG_IEEE80211_DEBUG
@@ -128,8 +114,7 @@ do { if (ieee80211_debug_level & (level)) \
          in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
 #else
 #define IEEE80211_DEBUG(level, fmt, args...) do {} while (0)
-#endif  /* CONFIG_IEEE80211_DEBUG */
-
+#endif                          /* CONFIG_IEEE80211_DEBUG */
 
 /* debug macros not dependent on CONFIG_IEEE80211_DEBUG */
 
@@ -140,7 +125,6 @@ do { if (ieee80211_debug_level & (level)) \
  * messages. It should never be used for passing essid to user space. */
 const char *escape_essid(const char *essid, u8 essid_len);
 
-
 /*
  * To use the debug system:
  *
@@ -177,6 +161,7 @@ const char *escape_essid(const char *essid, u8 essid_len);
 
 #define IEEE80211_DL_TX            (1<<8)
 #define IEEE80211_DL_RX            (1<<9)
+#define IEEE80211_DL_QOS           (1<<31)
 
 #define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a)
 #define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a)
@@ -190,9 +175,10 @@ const char *escape_essid(const char *essid, u8 essid_len);
 #define IEEE80211_DEBUG_DROP(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a)
 #define IEEE80211_DEBUG_TX(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a)
 #define IEEE80211_DEBUG_RX(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a)
+#define IEEE80211_DEBUG_QOS(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a)
 #include <linux/netdevice.h>
 #include <linux/wireless.h>
-#include <linux/if_arp.h> /* ARPHRD_ETHER */
+#include <linux/if_arp.h>       /* ARPHRD_ETHER */
 
 #ifndef WIRELESS_SPY
 #define WIRELESS_SPY            /* enable iwspy support */
@@ -200,10 +186,10 @@ const char *escape_essid(const char *essid, u8 essid_len);
 #include <net/iw_handler.h>     /* new driver API */
 
 #ifndef ETH_P_PAE
-#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
-#endif /* ETH_P_PAE */
+#define ETH_P_PAE 0x888E        /* Port Access Entity (IEEE 802.1X) */
+#endif                          /* ETH_P_PAE */
 
-#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
+#define ETH_P_PREAUTH 0x88C7    /* IEEE 802.11i pre-authentication */
 
 #ifndef ETH_P_80211_RAW
 #define ETH_P_80211_RAW (ETH_P_ECONET + 1)
@@ -215,10 +201,10 @@ const char *escape_essid(const char *essid, u8 essid_len);
 
 struct ieee80211_snap_hdr {
 
-        u8    dsap;   /* always 0xAA */
-        u8    ssap;   /* always 0xAA */
-        u8    ctrl;   /* always 0x03 */
-        u8    oui[P80211_OUI_LEN];    /* organizational universal id */
+        u8 dsap;                /* always 0xAA */
+        u8 ssap;                /* always 0xAA */
+        u8 ctrl;                /* always 0x03 */
+        u8 oui[P80211_OUI_LEN]; /* organizational universal id */
 
 } __attribute__ ((packed));
 
@@ -246,8 +232,9 @@ struct ieee80211_snap_hdr {
 #define WLAN_CAPABILITY_PBCC (1<<6)
 #define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
 #define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8)
+#define WLAN_CAPABILITY_QOS (1<<9)
 #define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10)
-#define WLAN_CAPABILITY_OSSS_OFDM (1<<13)
+#define WLAN_CAPABILITY_DSSS_OFDM (1<<13)
 
 /* Status codes */
 enum ieee80211_statuscode {
@@ -312,14 +299,12 @@ enum ieee80211_reasoncode {
         WLAN_REASON_CIPHER_SUITE_REJECTED = 24,
 };
 
-
 #define IEEE80211_STATMASK_SIGNAL (1<<0)
 #define IEEE80211_STATMASK_RSSI (1<<1)
 #define IEEE80211_STATMASK_NOISE (1<<2)
 #define IEEE80211_STATMASK_RATE (1<<3)
 #define IEEE80211_STATMASK_WEMASK 0x7
 
-
 #define IEEE80211_CCK_MODULATION    (1<<0)
 #define IEEE80211_OFDM_MODULATION   (1<<1)
 
@@ -377,9 +362,6 @@ enum ieee80211_reasoncode {
 #define IEEE80211_NUM_CCK_RATES             4
 #define IEEE80211_OFDM_SHIFT_MASK_A         4
 
-
-
-
 /* NOTE: This data is for statistical purposes; not all hardware provides this
  *       information for frames received.  Not setting these will not cause
  *       any adverse affects. */
@@ -388,7 +370,7 @@ struct ieee80211_rx_stats {
         s8 rssi;
         u8 signal;
         u8 noise;
-        u16 rate; /* in 100 kbps */
+        u16 rate;               /* in 100 kbps */
         u8 received_channel;
         u8 control;
         u8 mask;
@@ -439,38 +421,44 @@ struct ieee80211_device;
 
 #include "ieee80211_crypt.h"
 
-#define SEC_KEY_1         (1<<0)
-#define SEC_KEY_2         (1<<1)
-#define SEC_KEY_3         (1<<2)
-#define SEC_KEY_4         (1<<3)
-#define SEC_ACTIVE_KEY    (1<<4)
-#define SEC_AUTH_MODE     (1<<5)
-#define SEC_UNICAST_GROUP (1<<6)
-#define SEC_LEVEL         (1<<7)
-#define SEC_ENABLED       (1<<8)
-
-#define SEC_LEVEL_0      0 /* None */
-#define SEC_LEVEL_1      1 /* WEP 40 and 104 bit */
-#define SEC_LEVEL_2      2 /* Level 1 + TKIP */
-#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
-#define SEC_LEVEL_3      4 /* Level 2 + CCMP */
-
-#define WEP_KEYS 4
-#define WEP_KEY_LEN 13
+#define SEC_KEY_1               (1<<0)
+#define SEC_KEY_2               (1<<1)
+#define SEC_KEY_3               (1<<2)
+#define SEC_KEY_4               (1<<3)
+#define SEC_ACTIVE_KEY          (1<<4)
+#define SEC_AUTH_MODE           (1<<5)
+#define SEC_UNICAST_GROUP       (1<<6)
+#define SEC_LEVEL               (1<<7)
+#define SEC_ENABLED             (1<<8)
+#define SEC_ENCRYPT             (1<<9)
+
+#define SEC_LEVEL_0             0       /* None */
+#define SEC_LEVEL_1             1       /* WEP 40 and 104 bit */
+#define SEC_LEVEL_2             2       /* Level 1 + TKIP */
+#define SEC_LEVEL_2_CKIP        3       /* Level 1 + CKIP */
+#define SEC_LEVEL_3             4       /* Level 2 + CCMP */
+
+#define SEC_ALG_NONE            0
+#define SEC_ALG_WEP             1
+#define SEC_ALG_TKIP            2
+#define SEC_ALG_CCMP            3
+
+#define WEP_KEYS                4
+#define WEP_KEY_LEN             13
+#define SCM_KEY_LEN             32
+#define SCM_TEMPORAL_KEY_LENGTH 16
 
 struct ieee80211_security {
         u16 active_key:2,
-            enabled:1,
-            auth_mode:2,
-            auth_algo:4,
-            unicast_uses_group:1;
+            enabled:1,
+            auth_mode:2, auth_algo:4, unicast_uses_group:1, encrypt:1;
+        u8 encode_alg[WEP_KEYS];
         u8 key_sizes[WEP_KEYS];
-        u8 keys[WEP_KEYS][WEP_KEY_LEN];
+        u8 keys[WEP_KEYS][SCM_KEY_LEN];
         u8 level;
         u16 flags;
 } __attribute__ ((packed));
 
-
 /*
 
  802.11 data frame from AP
@@ -494,7 +482,7 @@ enum ieee80211_mfie {
         MFIE_TYPE_RATES = 1,
         MFIE_TYPE_FH_SET = 2,
         MFIE_TYPE_DS_SET = 3,
-        MFIE_TYPE_CF_SET =  4,
+        MFIE_TYPE_CF_SET = 4,
         MFIE_TYPE_TIM = 5,
         MFIE_TYPE_IBSS_SET = 6,
         MFIE_TYPE_COUNTRY = 7,
@@ -516,11 +504,75 @@ enum ieee80211_mfie {
         MFIE_TYPE_RSN = 48,
         MFIE_TYPE_RATES_EX = 50,
         MFIE_TYPE_GENERIC = 221,
+        MFIE_TYPE_QOS_PARAMETER = 222,
 };
 
-struct ieee80211_info_element_hdr {
-        u8 id;
-        u8 len;
+/* Minimal header; can be used for passing 802.11 frames with sufficient
+ * information to determine what type of underlying data type is actually
+ * stored in the data. */
+struct ieee80211_hdr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 payload[0];
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_1addr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 payload[0];
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_2addr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 payload[0];
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_3addr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+        u8 payload[0];
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_4addr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+        u8 addr4[ETH_ALEN];
+        u8 payload[0];
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_3addrqos {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+        u8 payload[0];
+        __le16 qos_ctl;
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_4addrqos {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+        u8 addr4[ETH_ALEN];
+        u8 payload[0];
+        __le16 qos_ctl;
 } __attribute__ ((packed));
 
 struct ieee80211_info_element {
@@ -546,49 +598,77 @@ struct ieee80211_info_element {
         u16 status;
 */
 
-struct ieee80211_authentication {
+struct ieee80211_auth {
         struct ieee80211_hdr_3addr header;
         __le16 algorithm;
         __le16 transaction;
         __le16 status;
-        struct ieee80211_info_element info_element;
+        /* challenge */
+        struct ieee80211_info_element info_element[0];
 } __attribute__ ((packed));
 
+struct ieee80211_disassoc {
+        struct ieee80211_hdr_3addr header;
+        __le16 reason;
+} __attribute__ ((packed));
+
+/* Alias deauth for disassoc */
+#define ieee80211_deauth ieee80211_disassoc
+
+struct ieee80211_probe_request {
+        struct ieee80211_hdr_3addr header;
+        /* SSID, supported rates */
+        struct ieee80211_info_element info_element[0];
+} __attribute__ ((packed));
 
 struct ieee80211_probe_response {
         struct ieee80211_hdr_3addr header;
         u32 time_stamp[2];
         __le16 beacon_interval;
         __le16 capability;
-        struct ieee80211_info_element info_element;
+        /* SSID, supported rates, FH params, DS params,
+         * CF params, IBSS params, TIM (if beacon), RSN */
+        struct ieee80211_info_element info_element[0];
 } __attribute__ ((packed));
 
-struct ieee80211_assoc_request_frame {
+/* Alias beacon for probe_response */
+#define ieee80211_beacon ieee80211_probe_response
+
+struct ieee80211_assoc_request {
+        struct ieee80211_hdr_3addr header;
+        __le16 capability;
+        __le16 listen_interval;
+        /* SSID, supported rates, RSN */
+        struct ieee80211_info_element info_element[0];
+} __attribute__ ((packed));
+
+struct ieee80211_reassoc_request {
+        struct ieee80211_hdr_3addr header;
         __le16 capability;
         __le16 listen_interval;
         u8 current_ap[ETH_ALEN];
-        struct ieee80211_info_element info_element;
+        struct ieee80211_info_element info_element[0];
 } __attribute__ ((packed));
 
-struct ieee80211_assoc_response_frame {
+struct ieee80211_assoc_response {
         struct ieee80211_hdr_3addr header;
         __le16 capability;
         __le16 status;
         __le16 aid;
-        struct ieee80211_info_element info_element; /* supported rates */
+        /* supported rates */
+        struct ieee80211_info_element info_element[0];
 } __attribute__ ((packed));
 
-
 struct ieee80211_txb {
         u8 nr_frags;
         u8 encrypted;
-        u16 reserved;
-        u16 frag_size;
-        u16 payload_size;
+        u8 rts_included;
+        u8 reserved;
+        __le16 frag_size;
+        __le16 payload_size;
         struct sk_buff *fragments[0];
 };
 
-
 /* SWEEP TABLE ENTRIES NUMBER */
 #define MAX_SWEEP_TAB_ENTRIES             42
 #define MAX_SWEEP_TAB_ENTRIES_PER_PACKET  7
@@ -604,9 +684,68 @@ struct ieee80211_txb {
 
 #define MAX_WPA_IE_LEN 64
 
-#define NETWORK_EMPTY_ESSID (1<<0)
-#define NETWORK_HAS_OFDM    (1<<1)
-#define NETWORK_HAS_CCK     (1<<2)
+#define NETWORK_EMPTY_ESSID    (1<<0)
+#define NETWORK_HAS_OFDM       (1<<1)
+#define NETWORK_HAS_CCK        (1<<2)
+
+/* QoS structure */
+#define NETWORK_HAS_QOS_PARAMETERS      (1<<3)
+#define NETWORK_HAS_QOS_INFORMATION     (1<<4)
+#define NETWORK_HAS_QOS_MASK            (NETWORK_HAS_QOS_PARAMETERS | NETWORK_HAS_QOS_INFORMATION)
+
+#define QOS_QUEUE_NUM                   4
+#define QOS_OUI_LEN                     3
+#define QOS_OUI_TYPE                    2
+#define QOS_ELEMENT_ID                  221
+#define QOS_OUI_INFO_SUB_TYPE           0
+#define QOS_OUI_PARAM_SUB_TYPE          1
+#define QOS_VERSION_1                   1
+#define QOS_AIFSN_MIN_VALUE             2
+
+struct ieee80211_qos_information_element {
+        u8 elementID;
+        u8 length;
+        u8 qui[QOS_OUI_LEN];
+        u8 qui_type;
+        u8 qui_subtype;
+        u8 version;
+        u8 ac_info;
+} __attribute__ ((packed));
+
+struct ieee80211_qos_ac_parameter {
+        u8 aci_aifsn;
+        u8 ecw_min_max;
+        __le16 tx_op_limit;
+} __attribute__ ((packed));
+
+struct ieee80211_qos_parameter_info {
+        struct ieee80211_qos_information_element info_element;
+        u8 reserved;
+        struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM];
+} __attribute__ ((packed));
+
+struct ieee80211_qos_parameters {
+        __le16 cw_min[QOS_QUEUE_NUM];
+        __le16 cw_max[QOS_QUEUE_NUM];
+        u8 aifs[QOS_QUEUE_NUM];
+        u8 flag[QOS_QUEUE_NUM];
+        __le16 tx_op_limit[QOS_QUEUE_NUM];
+} __attribute__ ((packed));
+
+struct ieee80211_qos_data {
+        struct ieee80211_qos_parameters parameters;
+        int active;
+        int supported;
+        u8 param_count;
+        u8 old_param_count;
+};
+
+struct ieee80211_tim_parameters {
+        u8 tim_count;
+        u8 tim_period;
+} __attribute__ ((packed));
+
+/*******************************************************/
 
 struct ieee80211_network {
         /* These entries are used to identify a unique network */
@@ -616,6 +755,8 @@ struct ieee80211_network {
         u8 ssid[IW_ESSID_MAX_SIZE + 1];
         u8 ssid_len;
 
+        struct ieee80211_qos_data qos_data;
+
         /* These are network statistics */
         struct ieee80211_rx_stats stats;
         u16 capability;
@@ -631,10 +772,12 @@ struct ieee80211_network {
         u16 beacon_interval;
         u16 listen_interval;
         u16 atim_window;
+        u8 erp_value;
         u8 wpa_ie[MAX_WPA_IE_LEN];
         size_t wpa_ie_len;
         u8 rsn_ie[MAX_WPA_IE_LEN];
         size_t rsn_ie_len;
+        struct ieee80211_tim_parameters tim;
         struct list_head list;
 };
 
@@ -651,17 +794,52 @@ enum ieee80211_state {
 #define DEFAULT_MAX_SCAN_AGE (15 * HZ)
 #define DEFAULT_FTS 2346
 
-
 #define CFG_IEEE80211_RESERVE_FCS (1<<0)
 #define CFG_IEEE80211_COMPUTE_FCS (1<<1)
+#define CFG_IEEE80211_RTS (1<<2)
+
+#define IEEE80211_24GHZ_MIN_CHANNEL 1
+#define IEEE80211_24GHZ_MAX_CHANNEL 14
+#define IEEE80211_24GHZ_CHANNELS    14
+
+#define IEEE80211_52GHZ_MIN_CHANNEL 36
+#define IEEE80211_52GHZ_MAX_CHANNEL 165
+#define IEEE80211_52GHZ_CHANNELS    32
+
+enum {
+        IEEE80211_CH_PASSIVE_ONLY = (1 << 0),
+        IEEE80211_CH_B_ONLY = (1 << 2),
+        IEEE80211_CH_NO_IBSS = (1 << 3),
+        IEEE80211_CH_UNIFORM_SPREADING = (1 << 4),
+        IEEE80211_CH_RADAR_DETECT = (1 << 5),
+        IEEE80211_CH_INVALID = (1 << 6),
+};
+
+struct ieee80211_channel {
+        u32 freq;
+        u8 channel;
+        u8 flags;
+        u8 max_power;
+};
+
+struct ieee80211_geo {
+        u8 name[4];
+        u8 bg_channels;
+        u8 a_channels;
+        struct ieee80211_channel bg[IEEE80211_24GHZ_CHANNELS];
+        struct ieee80211_channel a[IEEE80211_52GHZ_CHANNELS];
+};
 
 struct ieee80211_device {
         struct net_device *dev;
+        struct ieee80211_security sec;
 
         /* Bookkeeping structures */
         struct net_device_stats stats;
         struct ieee80211_stats ieee_stats;
 
+        struct ieee80211_geo geo;
+
         /* Probe / Beacon management */
         struct list_head network_free_list;
         struct list_head network_list;
@@ -669,62 +847,102 @@ struct ieee80211_device {
         int scans;
         int scan_age;
 
-        int iw_mode; /* operating mode (IW_MODE_*) */
+        int iw_mode;            /* operating mode (IW_MODE_*) */
+        struct iw_spy_data spy_data;    /* iwspy support */
 
         spinlock_t lock;
 
-        int tx_headroom; /* Set to size of any additional room needed at front
-                          * of allocated Tx SKBs */
+        int tx_headroom;        /* Set to size of any additional room needed at front
+                                 * of allocated Tx SKBs */
         u32 config;
 
         /* WEP and other encryption related settings at the device level */
-        int open_wep; /* Set to 1 to allow unencrypted frames */
+        int open_wep;           /* Set to 1 to allow unencrypted frames */
 
-        int reset_on_keychange; /* Set to 1 if the HW needs to be reset on
+        int reset_on_keychange; /* Set to 1 if the HW needs to be reset on
                                  * WEP key changes */
 
         /* If the host performs {en,de}cryption, then set to 1 */
         int host_encrypt;
+        int host_encrypt_msdu;
         int host_decrypt;
-        int ieee802_1x; /* is IEEE 802.1X used */
+        /* host performs multicast decryption */
+        int host_mc_decrypt;
+
+        int host_open_frag;
+        int host_build_iv;
+        int ieee802_1x;         /* is IEEE 802.1X used */
 
         /* WPA data */
         int wpa_enabled;
         int drop_unencrypted;
-        int tkip_countermeasures;
         int privacy_invoked;
         size_t wpa_ie_len;
         u8 *wpa_ie;
 
         struct list_head crypt_deinit_list;
         struct ieee80211_crypt_data *crypt[WEP_KEYS];
-        int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */
+        int tx_keyidx;          /* default TX key index (crypt[tx_keyidx]) */
         struct timer_list crypt_deinit_timer;
+        int crypt_quiesced;
 
-        int bcrx_sta_key; /* use individual keys to override default keys even
-                           * with RX of broad/multicast frames */
+        int bcrx_sta_key;       /* use individual keys to override default keys even
+                                 * with RX of broad/multicast frames */
 
         /* Fragmentation structures */
         struct ieee80211_frag_entry frag_cache[IEEE80211_FRAG_CACHE_LEN];
         unsigned int frag_next_idx;
-        u16 fts; /* Fragmentation Threshold */
+        u16 fts;                /* Fragmentation Threshold */
+        u16 rts;                /* RTS threshold */
 
         /* Association info */
         u8 bssid[ETH_ALEN];
 
         enum ieee80211_state state;
 
-        int mode;       /* A, B, G */
-        int modulation; /* CCK, OFDM */
-        int freq_band;  /* 2.4Ghz, 5.2Ghz, Mixed */
-        int abg_ture;   /* ABG flag              */
+        int mode;               /* A, B, G */
+        int modulation;         /* CCK, OFDM */
+        int freq_band;          /* 2.4Ghz, 5.2Ghz, Mixed */
+        int abg_true;           /* ABG flag              */
+
+        int perfect_rssi;
+        int worst_rssi;
 
         /* Callback functions */
-        void (*set_security)(struct net_device *dev,
-                             struct ieee80211_security *sec);
-        int (*hard_start_xmit)(struct ieee80211_txb *txb,
-                               struct net_device *dev);
-        int (*reset_port)(struct net_device *dev);
+        void (*set_security) (struct net_device * dev,
+                              struct ieee80211_security * sec);
+        int (*hard_start_xmit) (struct ieee80211_txb * txb,
+                                struct net_device * dev, int pri);
+        int (*reset_port) (struct net_device * dev);
+        int (*is_queue_full) (struct net_device * dev, int pri);
+
+        int (*handle_management) (struct net_device * dev,
+                                  struct ieee80211_network * network, u16 type);
+
+        /* Typical STA methods */
+        int (*handle_auth) (struct net_device * dev,
+                            struct ieee80211_auth * auth);
+        int (*handle_deauth) (struct net_device * dev,
+                              struct ieee80211_auth * auth);
+        int (*handle_disassoc) (struct net_device * dev,
+                                struct ieee80211_disassoc * assoc);
+        int (*handle_beacon) (struct net_device * dev,
+                              struct ieee80211_beacon * beacon,
+                              struct ieee80211_network * network);
+        int (*handle_probe_response) (struct net_device * dev,
+                                      struct ieee80211_probe_response * resp,
+                                      struct ieee80211_network * network);
+        int (*handle_probe_request) (struct net_device * dev,
+                                     struct ieee80211_probe_request * req,
+                                     struct ieee80211_rx_stats * stats);
+        int (*handle_assoc_response) (struct net_device * dev,
+                                      struct ieee80211_assoc_response * resp,
+                                      struct ieee80211_network * network);
+
+        /* Typical AP methods */
+        int (*handle_assoc_request) (struct net_device * dev);
+        int (*handle_reassoc_request) (struct net_device * dev,
+                                       struct ieee80211_reassoc_request * req);
 
         /* This must be the last item so that it points to the data
          * allocated beyond this structure by alloc_ieee80211 */
@@ -736,12 +954,12 @@ struct ieee80211_device {
 #define IEEE_G            (1<<2)
 #define IEEE_MODE_MASK    (IEEE_A|IEEE_B|IEEE_G)
 
-extern inline void *ieee80211_priv(struct net_device *dev)
+static inline void *ieee80211_priv(struct net_device *dev)
 {
         return ((struct ieee80211_device *)netdev_priv(dev))->priv;
 }
 
-extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
+static inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
 {
         /* Single white space is for Linksys APs */
         if (essid_len == 1 && essid[0] == ' ')
@@ -757,7 +975,8 @@ extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
         return 1;
 }
 
-extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode)
+static inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee,
+                                          int mode)
 {
         /*
          * It is possible for both access points and our device to support
@@ -783,14 +1002,17 @@ extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mod
         return 0;
 }
 
-extern inline int ieee80211_get_hdrlen(u16 fc)
+static inline int ieee80211_get_hdrlen(u16 fc)
 {
         int hdrlen = IEEE80211_3ADDR_LEN;
+        u16 stype = WLAN_FC_GET_STYPE(fc);
 
         switch (WLAN_FC_GET_TYPE(fc)) {
         case IEEE80211_FTYPE_DATA:
                 if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))
                         hdrlen = IEEE80211_4ADDR_LEN;
+                if (stype & IEEE80211_STYPE_QOS_DATA)
+                        hdrlen += 2;
                 break;
         case IEEE80211_FTYPE_CTL:
                 switch (WLAN_FC_GET_STYPE(fc)) {
@@ -808,7 +1030,48 @@ extern inline int ieee80211_get_hdrlen(u16 fc)
         return hdrlen;
 }
 
+static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr)
+{
+        switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) {
+        case IEEE80211_1ADDR_LEN:
+                return ((struct ieee80211_hdr_1addr *)hdr)->payload;
+        case IEEE80211_2ADDR_LEN:
+                return ((struct ieee80211_hdr_2addr *)hdr)->payload;
+        case IEEE80211_3ADDR_LEN:
+                return ((struct ieee80211_hdr_3addr *)hdr)->payload;
+        case IEEE80211_4ADDR_LEN:
+                return ((struct ieee80211_hdr_4addr *)hdr)->payload;
+        }
+
+}
+
+static inline int ieee80211_is_ofdm_rate(u8 rate)
+{
+        switch (rate & ~IEEE80211_BASIC_RATE_MASK) {
+        case IEEE80211_OFDM_RATE_6MB:
+        case IEEE80211_OFDM_RATE_9MB:
+        case IEEE80211_OFDM_RATE_12MB:
+        case IEEE80211_OFDM_RATE_18MB:
+        case IEEE80211_OFDM_RATE_24MB:
+        case IEEE80211_OFDM_RATE_36MB:
+        case IEEE80211_OFDM_RATE_48MB:
+        case IEEE80211_OFDM_RATE_54MB:
+                return 1;
+        }
+        return 0;
+}
 
+static inline int ieee80211_is_cck_rate(u8 rate)
+{
+        switch (rate & ~IEEE80211_BASIC_RATE_MASK) {
+        case IEEE80211_CCK_RATE_1MB:
+        case IEEE80211_CCK_RATE_2MB:
+        case IEEE80211_CCK_RATE_5MB:
+        case IEEE80211_CCK_RATE_11MB:
+                return 1;
+        }
+        return 0;
+}
 
 /* ieee80211.c */
 extern void free_ieee80211(struct net_device *dev);
@@ -817,18 +1080,30 @@ extern struct net_device *alloc_ieee80211(int sizeof_priv);
 extern int ieee80211_set_encryption(struct ieee80211_device *ieee);
 
 /* ieee80211_tx.c */
-extern int ieee80211_xmit(struct sk_buff *skb,
-                          struct net_device *dev);
+extern int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev);
 extern void ieee80211_txb_free(struct ieee80211_txb *);
-
+extern int ieee80211_tx_frame(struct ieee80211_device *ieee,
+                              struct ieee80211_hdr *frame, int len);
 
 /* ieee80211_rx.c */
 extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
                         struct ieee80211_rx_stats *rx_stats);
 extern void ieee80211_rx_mgt(struct ieee80211_device *ieee,
-                             struct ieee80211_hdr *header,
+                             struct ieee80211_hdr_4addr *header,
                              struct ieee80211_rx_stats *stats);
 
+/* ieee80211_geo.c */
+extern const struct ieee80211_geo *ieee80211_get_geo(struct ieee80211_device
+                                                     *ieee);
+extern int ieee80211_set_geo(struct ieee80211_device *ieee,
+                             const struct ieee80211_geo *geo);
+
+extern int ieee80211_is_valid_channel(struct ieee80211_device *ieee,
+                                      u8 channel);
+extern int ieee80211_channel_to_index(struct ieee80211_device *ieee,
+                                      u8 channel);
+extern u8 ieee80211_freq_to_channel(struct ieee80211_device *ieee, u32 freq);
+
 /* ieee80211_wx.c */
 extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee,
                                  struct iw_request_info *info,
@@ -839,17 +1114,21 @@ extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee,
 extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee,
                                    struct iw_request_info *info,
                                    union iwreq_data *wrqu, char *key);
-
-
-extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
+extern int ieee80211_wx_set_encodeext(struct ieee80211_device *ieee,
+                                      struct iw_request_info *info,
+                                      union iwreq_data *wrqu, char *extra);
+extern int ieee80211_wx_get_encodeext(struct ieee80211_device *ieee,
+                                      struct iw_request_info *info,
+                                      union iwreq_data *wrqu, char *extra);
+
+static inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
 {
         ieee->scans++;
 }
 
-extern inline int ieee80211_get_scans(struct ieee80211_device *ieee)
+static inline int ieee80211_get_scans(struct ieee80211_device *ieee)
 {
         return ieee->scans;
 }
 
-
-#endif /* IEEE80211_H */
+#endif                          /* IEEE80211_H */
diff --git a/include/net/ieee80211_crypt.h b/include/net/ieee80211_crypt.h
index b58a3bcc0dc0..0a1c2d82ca4b 100644
--- a/include/net/ieee80211_crypt.h
+++ b/include/net/ieee80211_crypt.h
@@ -25,16 +25,22 @@
 
 #include <linux/skbuff.h>
 
+enum {
+        IEEE80211_CRYPTO_TKIP_COUNTERMEASURES = (1 << 0),
+};
+
 struct ieee80211_crypto_ops {
         const char *name;
 
         /* init new crypto context (e.g., allocate private data space,
          * select IV, etc.); returns NULL on failure or pointer to allocated
          * private data on success */
-        void * (*init)(int keyidx);
+        void *(*init) (int keyidx);
 
         /* deinitialize crypto context and free allocated private data */
-        void (*deinit)(void *priv);
+        void (*deinit) (void *priv);
+
+        int (*build_iv) (struct sk_buff * skb, int hdr_len, void *priv);
 
         /* encrypt/decrypt return < 0 on error or >= 0 on success. The return
          * value from decrypt_mpdu is passed as the keyidx value for
@@ -42,34 +48,39 @@ struct ieee80211_crypto_ops {
          * encryption; if not, error will be returned; these functions are
          * called for all MPDUs (i.e., fragments).
          */
-        int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
-        int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
+        int (*encrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);
+        int (*decrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);
 
         /* These functions are called for full MSDUs, i.e. full frames.
          * These can be NULL if full MSDU operations are not needed. */
-        int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv);
-        int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len,
-                            void *priv);
+        int (*encrypt_msdu) (struct sk_buff * skb, int hdr_len, void *priv);
+        int (*decrypt_msdu) (struct sk_buff * skb, int keyidx, int hdr_len,
+                             void *priv);
 
-        int (*set_key)(void *key, int len, u8 *seq, void *priv);
-        int (*get_key)(void *key, int len, u8 *seq, void *priv);
+        int (*set_key) (void *key, int len, u8 * seq, void *priv);
+        int (*get_key) (void *key, int len, u8 * seq, void *priv);
 
         /* procfs handler for printing out key information and possible
          * statistics */
-        char * (*print_stats)(char *p, void *priv);
+        char *(*print_stats) (char *p, void *priv);
+
+        /* Crypto specific flag get/set for configuration settings */
+        unsigned long (*get_flags) (void *priv);
+        unsigned long (*set_flags) (unsigned long flags, void *priv);
 
         /* maximum number of bytes added by encryption; encrypt buf is
          * allocated with extra_prefix_len bytes, copy of in_buf, and
          * extra_postfix_len; encrypt need not use all this space, but
          * the result must start at the beginning of the buffer and correct
          * length must be returned */
-        int extra_prefix_len, extra_postfix_len;
+        int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
+        int extra_msdu_prefix_len, extra_msdu_postfix_len;
 
         struct module *owner;
 };
 
 struct ieee80211_crypt_data {
-        struct list_head list; /* delayed deletion list */
+        struct list_head list;  /* delayed deletion list */
         struct ieee80211_crypto_ops *ops;
         void *priv;
         atomic_t refcnt;
@@ -77,10 +88,11 @@ struct ieee80211_crypt_data {
 
 int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops);
 int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops);
-struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name);
+struct ieee80211_crypto_ops *ieee80211_get_crypto_ops(const char *name);
 void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int);
 void ieee80211_crypt_deinit_handler(unsigned long);
 void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee,
                                     struct ieee80211_crypt_data **crypt);
+void ieee80211_crypt_quiescing(struct ieee80211_device *ieee);
 
 #endif
diff --git a/include/net/ieee80211_radiotap.h b/include/net/ieee80211_radiotap.h
new file mode 100644
index 000000000000..429b73892a5f
--- /dev/null
+++ b/include/net/ieee80211_radiotap.h
@@ -0,0 +1,231 @@
+/* $FreeBSD: src/sys/net80211/ieee80211_radiotap.h,v 1.5 2005/01/22 20:12:05 sam Exp $ */
+/* $NetBSD: ieee80211_radiotap.h,v 1.11 2005/06/22 06:16:02 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2003, 2004 David Young.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of David Young may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY DAVID YOUNG ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL DAVID
+ * YOUNG BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+/*
+ * Modifications to fit into the linux IEEE 802.11 stack,
+ * Mike Kershaw (dragorn@kismetwireless.net)
+ */
+
+#ifndef IEEE80211RADIOTAP_H
+#define IEEE80211RADIOTAP_H
+
+#include <linux/if_ether.h>
+#include <linux/kernel.h>
+
+/* Radiotap header version (from official NetBSD feed) */
+#define IEEE80211RADIOTAP_VERSION       "1.5"
+/* Base version of the radiotap packet header data */
+#define PKTHDR_RADIOTAP_VERSION         0
+
+/* A generic radio capture format is desirable. There is one for
+ * Linux, but it is neither rigidly defined (there were not even
+ * units given for some fields) nor easily extensible.
+ *
+ * I suggest the following extensible radio capture format. It is
+ * based on a bitmap indicating which fields are present.
+ *
+ * I am trying to describe precisely what the application programmer
+ * should expect in the following, and for that reason I tell the
+ * units and origin of each measurement (where it applies), or else I
+ * use sufficiently weaselly language ("is a monotonically nondecreasing
+ * function of...") that I cannot set false expectations for lawyerly
+ * readers.
+ */
+
+/* XXX tcpdump/libpcap do not tolerate variable-length headers,
+ * yet, so we pad every radiotap header to 64 bytes. Ugh.
+ */
+#define IEEE80211_RADIOTAP_HDRLEN       64
+
+/* The radio capture header precedes the 802.11 header. */
+struct ieee80211_radiotap_header {
+        u8 it_version;          /* Version 0. Only increases
+                                 * for drastic changes,
+                                 * introduction of compatible
+                                 * new fields does not count.
+                                 */
+        u8 it_pad;
+        u16 it_len;             /* length of the whole
+                                 * header in bytes, including
+                                 * it_version, it_pad,
+                                 * it_len, and data fields.
+                                 */
+        u32 it_present;         /* A bitmap telling which
+                                 * fields are present. Set bit 31
+                                 * (0x80000000) to extend the
+                                 * bitmap by another 32 bits.
+                                 * Additional extensions are made
+                                 * by setting bit 31.
+                                 */
+};
+
+/* Name                                 Data type       Units
+ * ----                                 ---------       -----
+ *
+ * IEEE80211_RADIOTAP_TSFT              u64       microseconds
+ *
+ *      Value in microseconds of the MAC's 64-bit 802.11 Time
+ *      Synchronization Function timer when the first bit of the
+ *      MPDU arrived at the MAC. For received frames, only.
+ *
+ * IEEE80211_RADIOTAP_CHANNEL           2 x u16   MHz, bitmap
+ *
+ *      Tx/Rx frequency in MHz, followed by flags (see below).
+ *
+ * IEEE80211_RADIOTAP_FHSS              u16       see below
+ *
+ *      For frequency-hopping radios, the hop set (first byte)
+ *      and pattern (second byte).
+ *
+ * IEEE80211_RADIOTAP_RATE              u8        500kb/s
+ *
+ *      Tx/Rx data rate
+ *
+ * IEEE80211_RADIOTAP_DBM_ANTSIGNAL     int8_t          decibels from
+ *                                                      one milliwatt (dBm)
+ *
+ *      RF signal power at the antenna, decibel difference from
+ *      one milliwatt.
+ *
+ * IEEE80211_RADIOTAP_DBM_ANTNOISE      int8_t          decibels from
+ *                                                      one milliwatt (dBm)
+ *
+ *      RF noise power at the antenna, decibel difference from one
+ *      milliwatt.
+ *
+ * IEEE80211_RADIOTAP_DB_ANTSIGNAL      u8        decibel (dB)
+ *
+ *      RF signal power at the antenna, decibel difference from an
+ *      arbitrary, fixed reference.
+ *
+ * IEEE80211_RADIOTAP_DB_ANTNOISE       u8        decibel (dB)
+ *
+ *      RF noise power at the antenna, decibel difference from an
+ *      arbitrary, fixed reference point.
+ *
+ * IEEE80211_RADIOTAP_LOCK_QUALITY      u16       unitless
+ *
+ *      Quality of Barker code lock. Unitless. Monotonically
+ *      nondecreasing with "better" lock strength. Called "Signal
+ *      Quality" in datasheets.  (Is there a standard way to measure
+ *      this?)
+ *
+ * IEEE80211_RADIOTAP_TX_ATTENUATION    u16       unitless
+ *
+ *      Transmit power expressed as unitless distance from max
+ *      power set at factory calibration.  0 is max power.
+ *      Monotonically nondecreasing with lower power levels.
+ *
+ * IEEE80211_RADIOTAP_DB_TX_ATTENUATION u16       decibels (dB)
+ *
+ *      Transmit power expressed as decibel distance from max power
+ *      set at factory calibration.  0 is max power.  Monotonically
+ *      nondecreasing with lower power levels.
+ *
+ * IEEE80211_RADIOTAP_DBM_TX_POWER      int8_t          decibels from
+ *                                                      one milliwatt (dBm)
+ *
+ *      Transmit power expressed as dBm (decibels from a 1 milliwatt
+ *      reference). This is the absolute power level measured at
+ *      the antenna port.
+ *
+ * IEEE80211_RADIOTAP_FLAGS             u8        bitmap
+ *
+ *      Properties of transmitted and received frames. See flags
+ *      defined below.
+ *
+ * IEEE80211_RADIOTAP_ANTENNA           u8        antenna index
+ *
+ *      Unitless indication of the Rx/Tx antenna for this packet.
+ *      The first antenna is antenna 0.
+ *
+ * IEEE80211_RADIOTAP_FCS               u32       data
+ *
+ *      FCS from frame in network byte order.
+ */
+enum ieee80211_radiotap_type {
+        IEEE80211_RADIOTAP_TSFT = 0,
+        IEEE80211_RADIOTAP_FLAGS = 1,
+        IEEE80211_RADIOTAP_RATE = 2,
+        IEEE80211_RADIOTAP_CHANNEL = 3,
+        IEEE80211_RADIOTAP_FHSS = 4,
+        IEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5,
+        IEEE80211_RADIOTAP_DBM_ANTNOISE = 6,
+        IEEE80211_RADIOTAP_LOCK_QUALITY = 7,
+        IEEE80211_RADIOTAP_TX_ATTENUATION = 8,
+        IEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9,
+        IEEE80211_RADIOTAP_DBM_TX_POWER = 10,
+        IEEE80211_RADIOTAP_ANTENNA = 11,
+        IEEE80211_RADIOTAP_DB_ANTSIGNAL = 12,
+        IEEE80211_RADIOTAP_DB_ANTNOISE = 13,
+        IEEE80211_RADIOTAP_EXT = 31,
+};
+
+/* Channel flags. */
+#define IEEE80211_CHAN_TURBO    0x0010  /* Turbo channel */
+#define IEEE80211_CHAN_CCK      0x0020  /* CCK channel */
+#define IEEE80211_CHAN_OFDM     0x0040  /* OFDM channel */
+#define IEEE80211_CHAN_2GHZ     0x0080  /* 2 GHz spectrum channel. */
+#define IEEE80211_CHAN_5GHZ     0x0100  /* 5 GHz spectrum channel */
+#define IEEE80211_CHAN_PASSIVE  0x0200  /* Only passive scan allowed */
+#define IEEE80211_CHAN_DYN      0x0400  /* Dynamic CCK-OFDM channel */
+#define IEEE80211_CHAN_GFSK     0x0800  /* GFSK channel (FHSS PHY) */
+
+/* For IEEE80211_RADIOTAP_FLAGS */
+#define IEEE80211_RADIOTAP_F_CFP        0x01    /* sent/received
+                                                 * during CFP
+                                                 */
+#define IEEE80211_RADIOTAP_F_SHORTPRE   0x02    /* sent/received
+                                                 * with short
+                                                 * preamble
+                                                 */
+#define IEEE80211_RADIOTAP_F_WEP        0x04    /* sent/received
+                                                 * with WEP encryption
+                                                 */
+#define IEEE80211_RADIOTAP_F_FRAG       0x08    /* sent/received
+                                                 * with fragmentation
+                                                 */
+#define IEEE80211_RADIOTAP_F_FCS        0x10    /* frame includes FCS */
+#define IEEE80211_RADIOTAP_F_DATAPAD    0x20    /* frame has padding between
+                                                 * 802.11 header and payload
+                                                 * (to 32-bit boundary)
+                                                 */
+
+/* Ugly macro to convert literal channel numbers into their mhz equivalents
+ * There are certianly some conditions that will break this (like feeding it '30')
+ * but they shouldn't arise since nothing talks on channel 30. */
+#define ieee80211chan2mhz(x) \
+        (((x) <= 14) ? \
+        (((x) == 14) ? 2484 : ((x) * 5) + 2407) : \
+        ((x) + 1000) * 5)
+
+#endif                          /* IEEE80211_RADIOTAP_H */
diff --git a/include/net/llc_pdu.h b/include/net/llc_pdu.h
index f45c37d89cf7..c7a959428b4f 100644
--- a/include/net/llc_pdu.h
+++ b/include/net/llc_pdu.h
@@ -254,8 +254,10 @@ static inline void llc_pdu_decode_sa(struct sk_buff *skb, u8 *sa)
 {
         if (skb->protocol == ntohs(ETH_P_802_2))
                 memcpy(sa, eth_hdr(skb)->h_source, ETH_ALEN);
-        else if (skb->protocol == ntohs(ETH_P_TR_802_2))
+        else if (skb->protocol == ntohs(ETH_P_TR_802_2)) {
                 memcpy(sa, tr_hdr(skb)->saddr, ETH_ALEN);
+                *sa &= 0x7F;
+        }
 }
 
 /**
diff --git a/include/net/netrom.h b/include/net/netrom.h
index a6bf6e0f606a..a5ee53bce62f 100644
--- a/include/net/netrom.h
+++ b/include/net/netrom.h
@@ -136,8 +136,7 @@ static __inline__ void nr_node_put(struct nr_node *nr_node)
 static __inline__ void nr_neigh_put(struct nr_neigh *nr_neigh)
 {
         if (atomic_dec_and_test(&nr_neigh->refcount)) {
-                if (nr_neigh->digipeat != NULL)
-                        kfree(nr_neigh->digipeat);
+                kfree(nr_neigh->digipeat);
                 kfree(nr_neigh);
         }
 }
diff --git a/include/net/sctp/user.h b/include/net/sctp/user.h
index 1c5f19f995ad..f1c3bc54526a 100644
--- a/include/net/sctp/user.h
+++ b/include/net/sctp/user.h
@@ -171,10 +171,10 @@ struct sctp_sndrcvinfo {
  */
 
 enum sctp_sinfo_flags {
-        MSG_UNORDERED = 1,  /* Send/receive message unordered. */
-        MSG_ADDR_OVER = 2,  /* Override the primary destination. */
-        MSG_ABORT=4,        /* Send an ABORT message to the peer. */
-        /* MSG_EOF is already defined per socket.h */
+        SCTP_UNORDERED = 1,  /* Send/receive message unordered. */
+        SCTP_ADDR_OVER = 2,  /* Override the primary destination. */
+        SCTP_ABORT=4,        /* Send an ABORT message to the peer. */
+        SCTP_EOF=MSG_FIN,    /* Initiate graceful shutdown process. */  
 };
 
 
diff --git a/include/net/sock.h b/include/net/sock.h
index ecb75526cba0..e0498bd36004 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -207,7 +207,7 @@ struct sock {
         struct sk_buff_head     sk_write_queue;
         int                     sk_wmem_queued;
         int                     sk_forward_alloc;
-        unsigned int            sk_allocation;
+        gfp_t                   sk_allocation;
         int                     sk_sndbuf;
         int                     sk_route_caps;
         unsigned long           sk_flags;
diff --git a/include/net/syncppp.h b/include/net/syncppp.h
index 614cb6ba564e..877efa434700 100644
--- a/include/net/syncppp.h
+++ b/include/net/syncppp.h
@@ -86,7 +86,6 @@ static inline struct sppp *sppp_of(struct net_device *dev)
 
 void sppp_attach (struct ppp_device *pd);
 void sppp_detach (struct net_device *dev);
-void sppp_input (struct net_device *dev, struct sk_buff *m);
 int sppp_do_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd);
 struct sk_buff *sppp_dequeue (struct net_device *dev);
 int sppp_isempty (struct net_device *dev);
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index c8592c7e8eaa..e788bbc5657d 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -17,6 +17,7 @@
 
 #include <linux/config.h>
 #include <linux/device.h>
+#include <linux/sched.h>        /* task_struct, completion */
 
 #include <pcmcia/cs_types.h>
 #include <pcmcia/cs.h>
diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h
index 5308683c8c41..0a9fcd59eb43 100644
--- a/include/rdma/ib_cm.h
+++ b/include/rdma/ib_cm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004, 2005 Intel Corporation.  All rights reserved.
  * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
  * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
@@ -109,7 +109,6 @@ struct ib_cm_id;
 
 struct ib_cm_req_event_param {
         struct ib_cm_id         *listen_id;
-        struct ib_device        *device;
         u8                      port;
 
         struct ib_sa_path_rec   *primary_path;
@@ -220,7 +219,6 @@ struct ib_cm_apr_event_param {
 
 struct ib_cm_sidr_req_event_param {
         struct ib_cm_id         *listen_id;
-        struct ib_device        *device;
         u8                      port;
         u16                     pkey;
 };
@@ -284,6 +282,7 @@ typedef int (*ib_cm_handler)(struct ib_cm_id *cm_id,
 struct ib_cm_id {
         ib_cm_handler           cm_handler;
         void                    *context;
+        struct ib_device        *device;
         __be64                  service_id;
         __be64                  service_mask;
         enum ib_cm_state        state;          /* internal CM/debug use */
@@ -295,6 +294,8 @@ struct ib_cm_id {
 
 /**
  * ib_create_cm_id - Allocate a communication identifier.
+ * @device: Device associated with the cm_id.  All related communication will
+ * be associated with the specified device.
  * @cm_handler: Callback invoked to notify the user of CM events.
  * @context: User specified context associated with the communication
  *   identifier.
@@ -302,7 +303,8 @@ struct ib_cm_id {
  * Communication identifiers are used to track connection states, service
  * ID resolution requests, and listen requests.
  */
-struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler,
+struct ib_cm_id *ib_create_cm_id(struct ib_device *device,
+                                 ib_cm_handler cm_handler,
                                  void *context);
 
 /**
diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h
index 4172e6841e3d..2c133506742b 100644
--- a/include/rdma/ib_mad.h
+++ b/include/rdma/ib_mad.h
@@ -109,10 +109,14 @@
 #define IB_QP_SET_QKEY  0x80000000
 
 enum {
+        IB_MGMT_MAD_HDR = 24,
         IB_MGMT_MAD_DATA = 232,
+        IB_MGMT_RMPP_HDR = 36,
         IB_MGMT_RMPP_DATA = 220,
+        IB_MGMT_VENDOR_HDR = 40,
         IB_MGMT_VENDOR_DATA = 216,
-        IB_MGMT_SA_DATA = 200
+        IB_MGMT_SA_HDR = 56,
+        IB_MGMT_SA_DATA = 200,
 };
 
 struct ib_mad_hdr {
@@ -203,26 +207,25 @@ struct ib_class_port_info
 
 /**
  * ib_mad_send_buf - MAD data buffer and work request for sends.
- * @mad: References an allocated MAD data buffer.  The size of the data
- *   buffer is specified in the @send_wr.length field.
- * @mapping: DMA mapping information.
+ * @next: A pointer used to chain together MADs for posting.
+ * @mad: References an allocated MAD data buffer.
  * @mad_agent: MAD agent that allocated the buffer.
+ * @ah: The address handle to use when sending the MAD.
  * @context: User-controlled context fields.
- * @send_wr: An initialized work request structure used when sending the MAD.
- *   The wr_id field of the work request is initialized to reference this
- *   data structure.
- * @sge: A scatter-gather list referenced by the work request.
+ * @timeout_ms: Time to wait for a response.
+ * @retries: Number of times to retry a request for a response.
  *
  * Users are responsible for initializing the MAD buffer itself, with the
  * exception of specifying the payload length field in any RMPP MAD.
  */
 struct ib_mad_send_buf {
-        struct ib_mad           *mad;
-        DECLARE_PCI_UNMAP_ADDR(mapping)
+        struct ib_mad_send_buf  *next;
+        void                    *mad;
         struct ib_mad_agent     *mad_agent;
+        struct ib_ah            *ah;
         void                    *context[2];
-        struct ib_send_wr       send_wr;
-        struct ib_sge           sge;
+        int                     timeout_ms;
+        int                     retries;
 };
 
 /**
@@ -287,7 +290,7 @@ typedef void (*ib_mad_send_handler)(struct ib_mad_agent *mad_agent,
  * or @mad_send_wc.
  */
 typedef void (*ib_mad_snoop_handler)(struct ib_mad_agent *mad_agent,
-                                     struct ib_send_wr *send_wr,
+                                     struct ib_mad_send_buf *send_buf,
                                      struct ib_mad_send_wc *mad_send_wc);
 
 /**
@@ -334,13 +337,13 @@ struct ib_mad_agent {
 
 /**
  * ib_mad_send_wc - MAD send completion information.
- * @wr_id: Work request identifier associated with the send MAD request.
+ * @send_buf: Send MAD data buffer associated with the send MAD request.
  * @status: Completion status.
  * @vendor_err: Optional vendor error information returned with a failed
  *   request.
  */
 struct ib_mad_send_wc {
-        u64                     wr_id;
+        struct ib_mad_send_buf  *send_buf;
         enum ib_wc_status       status;
         u32                     vendor_err;
 };
@@ -366,7 +369,7 @@ struct ib_mad_recv_buf {
  * @rmpp_list: Specifies a list of RMPP reassembled received MAD buffers.
  * @mad_len: The length of the received MAD, without duplicated headers.
  *
- * For received response, the wr_id field of the wc is set to the wr_id
+ * For received response, the wr_id contains a pointer to the ib_mad_send_buf
  *   for the corresponding send request.
  */
 struct ib_mad_recv_wc {
@@ -463,9 +466,9 @@ int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent);
 /**
  * ib_post_send_mad - Posts MAD(s) to the send queue of the QP associated
  *   with the registered client.
- * @mad_agent: Specifies the associated registration to post the send to.
- * @send_wr: Specifies the information needed to send the MAD(s).
- * @bad_send_wr: Specifies the MAD on which an error was encountered.
+ * @send_buf: Specifies the information needed to send the MAD(s).
+ * @bad_send_buf: Specifies the MAD on which an error was encountered.  This
+ *   parameter is optional if only a single MAD is posted.
  *
  * Sent MADs are not guaranteed to complete in the order that they were posted.
  *
@@ -479,9 +482,8 @@ int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent);
  * defined data being transferred.  The paylen_newwin field should be
  * specified in network-byte order.
  */
-int ib_post_send_mad(struct ib_mad_agent *mad_agent,
-                     struct ib_send_wr *send_wr,
-                     struct ib_send_wr **bad_send_wr);
+int ib_post_send_mad(struct ib_mad_send_buf *send_buf,
+                     struct ib_mad_send_buf **bad_send_buf);
 
 /**
  * ib_coalesce_recv_mad - Coalesces received MAD data into a single buffer.
@@ -507,23 +509,25 @@ void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc);
 /**
  * ib_cancel_mad - Cancels an outstanding send MAD operation.
  * @mad_agent: Specifies the registration associated with sent MAD.
- * @wr_id: Indicates the work request identifier of the MAD to cancel.
+ * @send_buf: Indicates the MAD to cancel.
  *
  * MADs will be returned to the user through the corresponding
  * ib_mad_send_handler.
  */
-void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id);
+void ib_cancel_mad(struct ib_mad_agent *mad_agent,
+                   struct ib_mad_send_buf *send_buf);
 
 /**
  * ib_modify_mad - Modifies an outstanding send MAD operation.
  * @mad_agent: Specifies the registration associated with sent MAD.
- * @wr_id: Indicates the work request identifier of the MAD to modify.
+ * @send_buf: Indicates the MAD to modify.
  * @timeout_ms: New timeout value for sent MAD.
  *
  * This call will reset the timeout value for a sent MAD to the specified
  * value.
  */
-int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms);
+int ib_modify_mad(struct ib_mad_agent *mad_agent,
+                  struct ib_mad_send_buf *send_buf, u32 timeout_ms);
 
 /**
  * ib_redirect_mad_qp - Registers a QP for MAD services.
@@ -572,7 +576,6 @@ int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
  * @remote_qpn: Specifies the QPN of the receiving node.
  * @pkey_index: Specifies which PKey the MAD will be sent using.  This field
  *   is valid only if the remote_qpn is QP 1.
- * @ah: References the address handle used to transfer to the remote node.
  * @rmpp_active: Indicates if the send will enable RMPP.
  * @hdr_len: Indicates the size of the data header of the MAD.  This length
  *   should include the common MAD header, RMPP header, plus any class
@@ -582,11 +585,10 @@ int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
  *   additional padding that may be necessary.
  * @gfp_mask: GFP mask used for the memory allocation.
  *
- * This is a helper routine that may be used to allocate a MAD.  Users are
- * not required to allocate outbound MADs using this call.  The returned
- * MAD send buffer will reference a data buffer usable for sending a MAD, along
+ * This routine allocates a MAD for sending.  The returned MAD send buffer
+ * will reference a data buffer usable for sending a MAD, along
  * with an initialized work request structure.  Users may modify the returned
- * MAD data buffer or work request before posting the send.
+ * MAD data buffer before posting the send.
  *
  * The returned data buffer will be cleared.  Users are responsible for
  * initializing the common MAD and any class specific headers.  If @rmpp_active
@@ -594,7 +596,7 @@ int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
  */
 struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent,
                                             u32 remote_qpn, u16 pkey_index,
-                                            struct ib_ah *ah, int rmpp_active,
+                                            int rmpp_active,
                                             int hdr_len, int data_len,
                                             gfp_t gfp_mask);
 
diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h
index e4d1654276ad..3037588b8464 100644
--- a/include/rdma/ib_user_cm.h
+++ b/include/rdma/ib_user_cm.h
@@ -38,7 +38,7 @@
 
 #include <linux/types.h>
 
-#define IB_USER_CM_ABI_VERSION 2
+#define IB_USER_CM_ABI_VERSION 3
 
 enum {
         IB_USER_CM_CMD_CREATE_ID,
@@ -299,8 +299,6 @@ struct ib_ucm_event_get {
 };
 
 struct ib_ucm_req_event_resp {
-        /* device */
-        /* port */
         struct ib_ucm_path_rec primary_path;
         struct ib_ucm_path_rec alternate_path;
         __be64                 remote_ca_guid;
@@ -316,6 +314,7 @@ struct ib_ucm_req_event_resp {
         __u8  retry_count;
         __u8  rnr_retry_count;
         __u8  srq;
+        __u8  port;
 };
 
 struct ib_ucm_rep_event_resp {
@@ -353,10 +352,9 @@ struct ib_ucm_apr_event_resp {
 };
 
 struct ib_ucm_sidr_req_event_resp {
-        /* device */
-        /* port */
         __u16 pkey;
-        __u8  reserved[2];
+        __u8  port;
+        __u8  reserved;
 };
 
 struct ib_ucm_sidr_rep_event_resp {
diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h
index fd85725391a4..072f3a2edace 100644
--- a/include/rdma/ib_user_verbs.h
+++ b/include/rdma/ib_user_verbs.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2005 Topspin Communications.  All rights reserved.
  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ * Copyright (c) 2005 PathScale, Inc.  All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -42,15 +43,12 @@
  * Increment this value if any changes that break userspace ABI
  * compatibility are made.
  */
-#define IB_USER_VERBS_ABI_VERSION       2
+#define IB_USER_VERBS_ABI_VERSION       3
 
 enum {
-        IB_USER_VERBS_CMD_QUERY_PARAMS,
         IB_USER_VERBS_CMD_GET_CONTEXT,
         IB_USER_VERBS_CMD_QUERY_DEVICE,
         IB_USER_VERBS_CMD_QUERY_PORT,
-        IB_USER_VERBS_CMD_QUERY_GID,
-        IB_USER_VERBS_CMD_QUERY_PKEY,
         IB_USER_VERBS_CMD_ALLOC_PD,
         IB_USER_VERBS_CMD_DEALLOC_PD,
         IB_USER_VERBS_CMD_CREATE_AH,
@@ -65,6 +63,7 @@ enum {
         IB_USER_VERBS_CMD_ALLOC_MW,
         IB_USER_VERBS_CMD_BIND_MW,
         IB_USER_VERBS_CMD_DEALLOC_MW,
+        IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL,
         IB_USER_VERBS_CMD_CREATE_CQ,
         IB_USER_VERBS_CMD_RESIZE_CQ,
         IB_USER_VERBS_CMD_DESTROY_CQ,
@@ -90,8 +89,11 @@ enum {
  * Make sure that all structs defined in this file remain laid out so
  * that they pack the same way on 32-bit and 64-bit architectures (to
  * avoid incompatibility between 32-bit userspace and 64-bit kernels).
- * In particular do not use pointer types -- pass pointers in __u64
- * instead.
+ * Specifically:
+ *  - Do not use pointer types -- pass pointers in __u64 instead.
+ *  - Make sure that any structure larger than 4 bytes is padded to a
+ *    multiple of 8 bytes.  Otherwise the structure size will be
+ *    different between 32-bit and 64-bit architectures.
  */
 
 struct ib_uverbs_async_event_desc {
@@ -118,27 +120,14 @@ struct ib_uverbs_cmd_hdr {
         __u16 out_words;
 };
 
-/*
- * No driver_data for "query params" command, since this is intended
- * to be a core function with no possible device dependence.
- */
-struct ib_uverbs_query_params {
-        __u64 response;
-};
-
-struct ib_uverbs_query_params_resp {
-        __u32 num_cq_events;
-};
-
 struct ib_uverbs_get_context {
         __u64 response;
-        __u64 cq_fd_tab;
         __u64 driver_data[0];
 };
 
 struct ib_uverbs_get_context_resp {
         __u32 async_fd;
-        __u32 reserved;
+        __u32 num_comp_vectors;
 };
 
 struct ib_uverbs_query_device {
@@ -220,31 +209,6 @@ struct ib_uverbs_query_port_resp {
         __u8  reserved[3];
 };
 
-struct ib_uverbs_query_gid {
-        __u64 response;
-        __u8  port_num;
-        __u8  index;
-        __u8  reserved[6];
-        __u64 driver_data[0];
-};
-
-struct ib_uverbs_query_gid_resp {
-        __u8  gid[16];
-};
-
-struct ib_uverbs_query_pkey {
-        __u64 response;
-        __u8  port_num;
-        __u8  index;
-        __u8  reserved[6];
-        __u64 driver_data[0];
-};
-
-struct ib_uverbs_query_pkey_resp {
-        __u16 pkey;
-        __u16 reserved;
-};
-
 struct ib_uverbs_alloc_pd {
         __u64 response;
         __u64 driver_data[0];
@@ -278,11 +242,21 @@ struct ib_uverbs_dereg_mr {
         __u32 mr_handle;
 };
 
+struct ib_uverbs_create_comp_channel {
+        __u64 response;
+};
+
+struct ib_uverbs_create_comp_channel_resp {
+        __u32 fd;
+};
+
 struct ib_uverbs_create_cq {
         __u64 response;
         __u64 user_handle;
         __u32 cqe;
-        __u32 event_handler;
+        __u32 comp_vector;
+        __s32 comp_channel;
+        __u32 reserved;
         __u64 driver_data[0];
 };
 
@@ -291,6 +265,41 @@ struct ib_uverbs_create_cq_resp {
         __u32 cqe;
 };
 
+struct ib_uverbs_poll_cq {
+        __u64 response;
+        __u32 cq_handle;
+        __u32 ne;
+};
+
+struct ib_uverbs_wc {
+        __u64 wr_id;
+        __u32 status;
+        __u32 opcode;
+        __u32 vendor_err;
+        __u32 byte_len;
+        __u32 imm_data;
+        __u32 qp_num;
+        __u32 src_qp;
+        __u32 wc_flags;
+        __u16 pkey_index;
+        __u16 slid;
+        __u8 sl;
+        __u8 dlid_path_bits;
+        __u8 port_num;
+        __u8 reserved;
+};
+
+struct ib_uverbs_poll_cq_resp {
+        __u32 count;
+        __u32 reserved;
+        struct ib_uverbs_wc wc[0];
+};
+
+struct ib_uverbs_req_notify_cq {
+        __u32 cq_handle;
+        __u32 solicited_only;
+};
+
 struct ib_uverbs_destroy_cq {
         __u64 response;
         __u32 cq_handle;
@@ -388,6 +397,127 @@ struct ib_uverbs_destroy_qp_resp {
         __u32 events_reported;
 };
 
+/*
+ * The ib_uverbs_sge structure isn't used anywhere, since we assume
+ * the ib_sge structure is packed the same way on 32-bit and 64-bit
+ * architectures in both kernel and user space.  It's just here to
+ * document the ABI.
+ */
+struct ib_uverbs_sge {
+        __u64 addr;
+        __u32 length;
+        __u32 lkey;
+};
+
+struct ib_uverbs_send_wr {
+        __u64 wr_id; 
+        __u32 num_sge;
+        __u32 opcode;
+        __u32 send_flags;
+        __u32 imm_data;
+        union {
+                struct {
+                        __u64 remote_addr;
+                        __u32 rkey;
+                        __u32 reserved;
+                } rdma;
+                struct {
+                        __u64 remote_addr;
+                        __u64 compare_add;
+                        __u64 swap;
+                        __u32 rkey;
+                        __u32 reserved;
+                } atomic;
+                struct {
+                        __u32 ah;
+                        __u32 remote_qpn;
+                        __u32 remote_qkey;
+                        __u32 reserved;
+                } ud;
+        } wr;
+};
+
+struct ib_uverbs_post_send {
+        __u64 response;
+        __u32 qp_handle;
+        __u32 wr_count;
+        __u32 sge_count;
+        __u32 wqe_size;
+        struct ib_uverbs_send_wr send_wr[0];
+};
+
+struct ib_uverbs_post_send_resp {
+        __u32 bad_wr;
+};
+
+struct ib_uverbs_recv_wr {
+        __u64 wr_id;
+        __u32 num_sge;
+        __u32 reserved;
+};
+
+struct ib_uverbs_post_recv {
+        __u64 response;
+        __u32 qp_handle;
+        __u32 wr_count;
+        __u32 sge_count;
+        __u32 wqe_size;
+        struct ib_uverbs_recv_wr recv_wr[0];
+};
+
+struct ib_uverbs_post_recv_resp {
+        __u32 bad_wr;
+};
+
+struct ib_uverbs_post_srq_recv {
+        __u64 response;
+        __u32 srq_handle;
+        __u32 wr_count;
+        __u32 sge_count;
+        __u32 wqe_size;
+        struct ib_uverbs_recv_wr recv[0];
+};
+
+struct ib_uverbs_post_srq_recv_resp {
+        __u32 bad_wr;
+};
+
+struct ib_uverbs_global_route {
+        __u8  dgid[16];
+        __u32 flow_label;    
+        __u8  sgid_index;
+        __u8  hop_limit;
+        __u8  traffic_class;
+        __u8  reserved;
+};
+
+struct ib_uverbs_ah_attr {
+        struct ib_uverbs_global_route grh;
+        __u16 dlid;
+        __u8  sl;
+        __u8  src_path_bits;
+        __u8  static_rate;
+        __u8  is_global;
+        __u8  port_num;
+        __u8  reserved;
+};
+
+struct ib_uverbs_create_ah {
+        __u64 response;
+        __u64 user_handle;
+        __u32 pd_handle;
+        __u32 reserved;
+        struct ib_uverbs_ah_attr attr;
+};
+
+struct ib_uverbs_create_ah_resp {
+        __u32 ah_handle;
+};
+
+struct ib_uverbs_destroy_ah {
+        __u32 ah_handle;
+};
+
 struct ib_uverbs_attach_mcast {
         __u8  gid[16];
         __u32 qp_handle;
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index e6f4c9e55df7..f72d46d54e0a 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -595,11 +595,8 @@ struct ib_send_wr {
                 } atomic;
                 struct {
                         struct ib_ah *ah;
-                        struct ib_mad_hdr *mad_hdr;
                         u32     remote_qpn;
                         u32     remote_qkey;
-                        int     timeout_ms; /* valid for MADs only */
-                        int     retries;    /* valid for MADs only */
                         u16     pkey_index; /* valid for GSI only */
                         u8      port_num;   /* valid for DR SMPs on switch only */
                 } ud;
@@ -951,6 +948,9 @@ struct ib_device {
                 IB_DEV_UNREGISTERED
         }                            reg_state;
 
+        u64                          uverbs_cmd_mask;
+        int                          uverbs_abi_ver;
+
         u8                           node_type;
         u8                           phys_port_cnt;
 };
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index b361172b576c..6cb1e2788d8b 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -116,6 +116,9 @@ extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE];
 /* values for service action in */
 #define SAI_READ_CAPACITY_16  0x10
 
+/* Values for T10/04-262r7 */
+#define ATA_16                0x85      /* 16-byte pass-thru */
+#define ATA_12                0xa1      /* 12-byte pass-thru */
 
 /*
  *  SCSI Architecture Model (SAM) Status codes. Taken from SAM-3 draft
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index bed4b7c9be99..7529f4388bb4 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -4,6 +4,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/list.h>
 #include <linux/types.h>
+#include <linux/timer.h>
 
 struct request;
 struct scatterlist;
@@ -146,7 +147,7 @@ struct scsi_cmnd {
 #define SCSI_STATE_MLQUEUE         0x100b
 
 
-extern struct scsi_cmnd *scsi_get_command(struct scsi_device *, int);
+extern struct scsi_cmnd *scsi_get_command(struct scsi_device *, gfp_t);
 extern void scsi_put_command(struct scsi_cmnd *);
 extern void scsi_io_completion(struct scsi_cmnd *, unsigned int, unsigned int);
 extern void scsi_finish_command(struct scsi_cmnd *cmd);
diff --git a/include/scsi/scsi_request.h b/include/scsi/scsi_request.h
index 6a140020d7cb..2539debb7993 100644
--- a/include/scsi/scsi_request.h
+++ b/include/scsi/scsi_request.h
@@ -45,7 +45,7 @@ struct scsi_request {
                                            level driver) of this request */
 };
 
-extern struct scsi_request *scsi_allocate_request(struct scsi_device *, int);
+extern struct scsi_request *scsi_allocate_request(struct scsi_device *, gfp_t);
 extern void scsi_release_request(struct scsi_request *);
 extern void scsi_wait_req(struct scsi_request *, const void *cmnd,
                           void *buffer, unsigned bufflen,
diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h
index b0d445437372..c04405bead2d 100644
--- a/include/scsi/scsi_transport_fc.h
+++ b/include/scsi/scsi_transport_fc.h
@@ -28,6 +28,7 @@
 #define SCSI_TRANSPORT_FC_H
 
 #include <linux/config.h>
+#include <linux/sched.h>
 
 struct scsi_transport_template;
 
diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h
index 3a2fd2cc9f19..83489c3abbaf 100644
--- a/include/sound/memalloc.h
+++ b/include/sound/memalloc.h
@@ -111,7 +111,7 @@ size_t snd_dma_get_reserved_buf(struct snd_dma_buffer *dmab, unsigned int id);
 int snd_dma_reserve_buf(struct snd_dma_buffer *dmab, unsigned int id);
 
 /* basic memory allocation functions */
-void *snd_malloc_pages(size_t size, unsigned int gfp_flags);
+void *snd_malloc_pages(size_t size, gfp_t gfp_flags);
 void snd_free_pages(void *ptr, size_t size);
 
 #endif /* __SOUND_MEMALLOC_H */