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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-07-29 13:29:18 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-30 13:49:23 -0400
commita648bf4632628c787abb0514277f2a231fca39ca (patch)
treedd0e9d58f6b21ac88feecc8daf84fec8733df2e1 /include
parentbc588df79ebfb710abc27342fccf336a68ed1216 (diff)
x86, xsave: xsave cpuid feature bits
Add xsave CPU feature bits. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
-rw-r--r--include/asm-x86/cpufeature.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 42afe9ca3a37..c76b3f67cb3f 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -92,6 +92,7 @@
92#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ 92#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
93#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ 93#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
94#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ 94#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
95#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE */
95 96
96/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 97/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
97#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ 98#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -191,6 +192,7 @@ extern const char * const x86_power_flags[32];
191#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) 192#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
192#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) 193#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
193#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) 194#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
195#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
194 196
195#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) 197#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
196# define cpu_has_invlpg 1 198# define cpu_has_invlpg 1