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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-18 12:22:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-18 12:22:36 -0400
commit6f130478e24d810078c3f0ee292bcc4ec034dcce (patch)
tree1c782ccceaf998e9e23862094588c125ee6f38af /include
parent6f128fa344833bf8bf076a51d14401661c146470 (diff)
parent75f2ba8f0006440e720e47ae14c917e07c452d72 (diff)
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (55 commits) regulator: Voltage count for AB3100 mfd: Convert WM8350 to use request_threaded_irq() mfd: Update MAINTAINERS patterns for WM831x mfd: Fix twl4030-power warnings regulator: AB3100 support rtc: AB3100 RTC support mfd: Fix ab3100-otp build failure mfd: OMAP: Board-specifc twl4030 DPS scripts for RX51 board mfd: Print warning for twl4030 out-of-order script loading mfd: Add support for TWL4030/5030 dynamic power switching mfd: AB3100 OTP readout regulator: Add Freescale MC13783 driver mfd: Add Freescale MC13783 driver mfd: AB3100 disable irq nosync mfd: AB3100 alter default setting mfd: AB3100 propagate error mfd: AB3100 accessor function cleanups rtc: Add support for RTCs on Wolfson WM831x devices regulator: get pcap data from the parent device input: PCAP2 misc input driver ...
Diffstat (limited to 'include')
-rw-r--r--include/linux/i2c/twl4030.h94
-rw-r--r--include/linux/mfd/ab3100.h37
-rw-r--r--include/linux/mfd/core.h1
-rw-r--r--include/linux/mfd/ezx-pcap.h7
-rw-r--r--include/linux/mfd/mc13783-private.h396
-rw-r--r--include/linux/mfd/mc13783.h84
-rw-r--r--include/linux/mfd/pcf50633/adc.h3
-rw-r--r--include/linux/mfd/pcf50633/core.h1
-rw-r--r--include/linux/mfd/wm831x/auxadc.h216
-rw-r--r--include/linux/mfd/wm831x/core.h289
-rw-r--r--include/linux/mfd/wm831x/gpio.h55
-rw-r--r--include/linux/mfd/wm831x/irq.h764
-rw-r--r--include/linux/mfd/wm831x/otp.h162
-rw-r--r--include/linux/mfd/wm831x/pdata.h113
-rw-r--r--include/linux/mfd/wm831x/regulator.h1218
-rw-r--r--include/linux/mfd/wm8350/core.h7
-rw-r--r--include/linux/regulator/driver.h2
17 files changed, 3429 insertions, 20 deletions
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl4030.h
index 3fd21d7cb6bf..2d02dfd7076c 100644
--- a/include/linux/i2c/twl4030.h
+++ b/include/linux/i2c/twl4030.h
@@ -223,19 +223,28 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
223 223
224/* Power bus message definitions */ 224/* Power bus message definitions */
225 225
226#define DEV_GRP_NULL 0x0 226/* The TWL4030/5030 splits its power-management resources (the various
227#define DEV_GRP_P1 0x1 227 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
228#define DEV_GRP_P2 0x2 228 * P3. These groups can then be configured to transition between sleep, wait-on
229#define DEV_GRP_P3 0x4 229 * and active states by sending messages to the power bus. See Section 5.4.2
230 * Power Resources of TWL4030 TRM
231 */
230 232
231#define RES_GRP_RES 0x0 233/* Processor groups */
232#define RES_GRP_PP 0x1 234#define DEV_GRP_NULL 0x0
233#define RES_GRP_RC 0x2 235#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
236#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
237#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
238
239/* Resource groups */
240#define RES_GRP_RES 0x0 /* Reserved */
241#define RES_GRP_PP 0x1 /* Power providers */
242#define RES_GRP_RC 0x2 /* Reset and control */
234#define RES_GRP_PP_RC 0x3 243#define RES_GRP_PP_RC 0x3
235#define RES_GRP_PR 0x4 244#define RES_GRP_PR 0x4 /* Power references */
236#define RES_GRP_PP_PR 0x5 245#define RES_GRP_PP_PR 0x5
237#define RES_GRP_RC_PR 0x6 246#define RES_GRP_RC_PR 0x6
238#define RES_GRP_ALL 0x7 247#define RES_GRP_ALL 0x7 /* All resource groups */
239 248
240#define RES_TYPE2_R0 0x0 249#define RES_TYPE2_R0 0x0
241 250
@@ -246,6 +255,41 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
246#define RES_STATE_SLEEP 0x8 255#define RES_STATE_SLEEP 0x8
247#define RES_STATE_OFF 0x0 256#define RES_STATE_OFF 0x0
248 257
258/* Power resources */
259
260/* Power providers */
261#define RES_VAUX1 1
262#define RES_VAUX2 2
263#define RES_VAUX3 3
264#define RES_VAUX4 4
265#define RES_VMMC1 5
266#define RES_VMMC2 6
267#define RES_VPLL1 7
268#define RES_VPLL2 8
269#define RES_VSIM 9
270#define RES_VDAC 10
271#define RES_VINTANA1 11
272#define RES_VINTANA2 12
273#define RES_VINTDIG 13
274#define RES_VIO 14
275#define RES_VDD1 15
276#define RES_VDD2 16
277#define RES_VUSB_1V5 17
278#define RES_VUSB_1V8 18
279#define RES_VUSB_3V1 19
280#define RES_VUSBCP 20
281#define RES_REGEN 21
282/* Reset and control */
283#define RES_NRES_PWRON 22
284#define RES_CLKEN 23
285#define RES_SYSEN 24
286#define RES_HFCLKOUT 25
287#define RES_32KCLKOUT 26
288#define RES_RESET 27
289/* Power Reference */
290#define RES_Main_Ref 28
291
292#define TOTAL_RESOURCES 28
249/* 293/*
250 * Power Bus Message Format ... these can be sent individually by Linux, 294 * Power Bus Message Format ... these can be sent individually by Linux,
251 * but are usually part of downloaded scripts that are run when various 295 * but are usually part of downloaded scripts that are run when various
@@ -327,6 +371,36 @@ struct twl4030_usb_data {
327 enum twl4030_usb_mode usb_mode; 371 enum twl4030_usb_mode usb_mode;
328}; 372};
329 373
374struct twl4030_ins {
375 u16 pmb_message;
376 u8 delay;
377};
378
379struct twl4030_script {
380 struct twl4030_ins *script;
381 unsigned size;
382 u8 flags;
383#define TWL4030_WRST_SCRIPT (1<<0)
384#define TWL4030_WAKEUP12_SCRIPT (1<<1)
385#define TWL4030_WAKEUP3_SCRIPT (1<<2)
386#define TWL4030_SLEEP_SCRIPT (1<<3)
387};
388
389struct twl4030_resconfig {
390 u8 resource;
391 u8 devgroup; /* Processor group that Power resource belongs to */
392 u8 type; /* Power resource addressed, 6 / broadcast message */
393 u8 type2; /* Power resource addressed, 3 / broadcast message */
394};
395
396struct twl4030_power_data {
397 struct twl4030_script **scripts;
398 unsigned num;
399 struct twl4030_resconfig *resource_config;
400};
401
402extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
403
330struct twl4030_platform_data { 404struct twl4030_platform_data {
331 unsigned irq_base, irq_end; 405 unsigned irq_base, irq_end;
332 struct twl4030_bci_platform_data *bci; 406 struct twl4030_bci_platform_data *bci;
@@ -334,6 +408,7 @@ struct twl4030_platform_data {
334 struct twl4030_madc_platform_data *madc; 408 struct twl4030_madc_platform_data *madc;
335 struct twl4030_keypad_data *keypad; 409 struct twl4030_keypad_data *keypad;
336 struct twl4030_usb_data *usb; 410 struct twl4030_usb_data *usb;
411 struct twl4030_power_data *power;
337 412
338 /* LDO regulators */ 413 /* LDO regulators */
339 struct regulator_init_data *vdac; 414 struct regulator_init_data *vdac;
@@ -364,7 +439,6 @@ int twl4030_sih_setup(int module);
364#define TWL4030_VAUX3_DEV_GRP 0x1F 439#define TWL4030_VAUX3_DEV_GRP 0x1F
365#define TWL4030_VAUX3_DEDICATED 0x22 440#define TWL4030_VAUX3_DEDICATED 0x22
366 441
367
368#if defined(CONFIG_TWL4030_BCI_BATTERY) || \ 442#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
369 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE) 443 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
370 extern int twl4030charger_usb_en(int enable); 444 extern int twl4030charger_usb_en(int enable);
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h
index 7a3f316e3848..e9aa4c9d749d 100644
--- a/include/linux/mfd/ab3100.h
+++ b/include/linux/mfd/ab3100.h
@@ -6,6 +6,8 @@
6 */ 6 */
7 7
8#include <linux/device.h> 8#include <linux/device.h>
9#include <linux/workqueue.h>
10#include <linux/regulator/machine.h>
9 11
10#ifndef MFD_AB3100_H 12#ifndef MFD_AB3100_H
11#define MFD_AB3100_H 13#define MFD_AB3100_H
@@ -56,6 +58,14 @@
56#define AB3100_STR_BATT_REMOVAL (0x40) 58#define AB3100_STR_BATT_REMOVAL (0x40)
57#define AB3100_STR_VBUS (0x80) 59#define AB3100_STR_VBUS (0x80)
58 60
61/*
62 * AB3100 contains 8 regulators, one external regulator controller
63 * and a buck converter, further the LDO E and buck converter can
64 * have separate settings if they are in sleep mode, this is
65 * modeled as a separate regulator.
66 */
67#define AB3100_NUM_REGULATORS 10
68
59/** 69/**
60 * struct ab3100 70 * struct ab3100
61 * @access_mutex: lock out concurrent accesses to the AB3100 registers 71 * @access_mutex: lock out concurrent accesses to the AB3100 registers
@@ -86,11 +96,30 @@ struct ab3100 {
86 bool startup_events_read; 96 bool startup_events_read;
87}; 97};
88 98
89int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval); 99/**
90int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval); 100 * struct ab3100_platform_data
91int ab3100_get_register_page(struct ab3100 *ab3100, 101 * Data supplied to initialize board connections to the AB3100
102 * @reg_constraints: regulator constraints for target board
103 * the order of these constraints are: LDO A, C, D, E,
104 * F, G, H, K, EXT and BUCK.
105 * @reg_initvals: initial values for the regulator registers
106 * plus two sleep settings for LDO E and the BUCK converter.
107 * exactly AB3100_NUM_REGULATORS+2 values must be sent in.
108 * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
109 * BUCK sleep, LDO D. (LDO D need to be initialized last.)
110 * @external_voltage: voltage level of the external regulator.
111 */
112struct ab3100_platform_data {
113 struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
114 u8 reg_initvals[AB3100_NUM_REGULATORS+2];
115 int external_voltage;
116};
117
118int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
119int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
120int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
92 u8 first_reg, u8 *regvals, u8 numregs); 121 u8 first_reg, u8 *regvals, u8 numregs);
93int ab3100_mask_and_set_register(struct ab3100 *ab3100, 122int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
94 u8 reg, u8 andmask, u8 ormask); 123 u8 reg, u8 andmask, u8 ormask);
95u8 ab3100_get_chip_type(struct ab3100 *ab3100); 124u8 ab3100_get_chip_type(struct ab3100 *ab3100);
96int ab3100_event_register(struct ab3100 *ab3100, 125int ab3100_event_register(struct ab3100 *ab3100,
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index 49ef857cdb2d..11d740b8831d 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -23,6 +23,7 @@
23 */ 23 */
24struct mfd_cell { 24struct mfd_cell {
25 const char *name; 25 const char *name;
26 int id;
26 27
27 int (*enable)(struct platform_device *dev); 28 int (*enable)(struct platform_device *dev);
28 int (*disable)(struct platform_device *dev); 29 int (*disable)(struct platform_device *dev);
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index c12c3c0932bf..e5124ceea769 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -25,9 +25,12 @@ struct pcap_chip;
25 25
26int ezx_pcap_write(struct pcap_chip *, u8, u32); 26int ezx_pcap_write(struct pcap_chip *, u8, u32);
27int ezx_pcap_read(struct pcap_chip *, u8, u32 *); 27int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
28int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
28int pcap_to_irq(struct pcap_chip *, int); 29int pcap_to_irq(struct pcap_chip *, int);
30int irq_to_pcap(struct pcap_chip *, int);
29int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *); 31int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
30int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]); 32int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
33void pcap_set_ts_bits(struct pcap_chip *, u32);
31 34
32#define PCAP_SECOND_PORT 1 35#define PCAP_SECOND_PORT 1
33#define PCAP_CS_AH 2 36#define PCAP_CS_AH 2
@@ -224,7 +227,6 @@ int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
224#define PCAP_LED1 1 227#define PCAP_LED1 1
225#define PCAP_BL0 2 228#define PCAP_BL0 2
226#define PCAP_BL1 3 229#define PCAP_BL1 3
227#define PCAP_VIB 4
228#define PCAP_LED_3MA 0 230#define PCAP_LED_3MA 0
229#define PCAP_LED_4MA 1 231#define PCAP_LED_4MA 1
230#define PCAP_LED_5MA 2 232#define PCAP_LED_5MA 2
@@ -243,9 +245,6 @@ int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
243#define PCAP_LED0_C_SHIFT 15 245#define PCAP_LED0_C_SHIFT 15
244#define PCAP_LED1_C_SHIFT 17 246#define PCAP_LED1_C_SHIFT 17
245#define PCAP_BL1_SHIFT 20 247#define PCAP_BL1_SHIFT 20
246#define PCAP_VIB_MASK 0x3
247#define PCAP_VIB_SHIFT 20
248#define PCAP_VIB_EN (1 << 19)
249 248
250/* RTC */ 249/* RTC */
251#define PCAP_RTC_DAY_MASK 0x3fff 250#define PCAP_RTC_DAY_MASK 0x3fff
diff --git a/include/linux/mfd/mc13783-private.h b/include/linux/mfd/mc13783-private.h
new file mode 100644
index 000000000000..47e698cb0f16
--- /dev/null
+++ b/include/linux/mfd/mc13783-private.h
@@ -0,0 +1,396 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __LINUX_MFD_MC13783_PRIV_H
23#define __LINUX_MFD_MC13783_PRIV_H
24
25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/workqueue.h>
28#include <linux/mutex.h>
29
30struct mc13783_irq {
31 void (*handler)(int, void *);
32 void *data;
33};
34
35#define MC13783_NUM_IRQ 2
36#define MC13783_IRQ_TS 0
37#define MC13783_IRQ_REGULATOR 1
38
39#define MC13783_ADC_MODE_TS 1
40#define MC13783_ADC_MODE_SINGLE_CHAN 2
41#define MC13783_ADC_MODE_MULT_CHAN 3
42
43struct mc13783 {
44 int revision;
45 struct device *dev;
46 struct spi_device *spi_device;
47
48 int (*read_dev)(void *data, char reg, int count, u32 *dst);
49 int (*write_dev)(void *data, char reg, int count, const u32 *src);
50
51 struct mutex io_lock;
52 void *io_data;
53 int irq;
54 unsigned int flags;
55
56 struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
57 struct work_struct work;
58 struct completion adc_done;
59 unsigned int ts_active;
60 struct mutex adc_conv_lock;
61
62 struct mc13783_regulator_init_data *regulators;
63 int num_regulators;
64};
65
66int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
67int mc13783_reg_write(struct mc13783 *, int, u32);
68int mc13783_set_bits(struct mc13783 *, int, u32, u32);
69int mc13783_free_irq(struct mc13783 *mc13783, int irq);
70int mc13783_register_irq(struct mc13783 *mc13783, int irq,
71 void (*handler) (int, void *), void *data);
72
73#define MC13783_REG_INTERRUPT_STATUS_0 0
74#define MC13783_REG_INTERRUPT_MASK_0 1
75#define MC13783_REG_INTERRUPT_SENSE_0 2
76#define MC13783_REG_INTERRUPT_STATUS_1 3
77#define MC13783_REG_INTERRUPT_MASK_1 4
78#define MC13783_REG_INTERRUPT_SENSE_1 5
79#define MC13783_REG_POWER_UP_MODE_SENSE 6
80#define MC13783_REG_REVISION 7
81#define MC13783_REG_SEMAPHORE 8
82#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
83#define MC13783_REG_ARBITRATION_SWITCHERS 10
84#define MC13783_REG_ARBITRATION_REGULATORS_0 11
85#define MC13783_REG_ARBITRATION_REGULATORS_1 12
86#define MC13783_REG_POWER_CONTROL_0 13
87#define MC13783_REG_POWER_CONTROL_1 14
88#define MC13783_REG_POWER_CONTROL_2 15
89#define MC13783_REG_REGEN_ASSIGNMENT 16
90#define MC13783_REG_CONTROL_SPARE 17
91#define MC13783_REG_MEMORY_A 18
92#define MC13783_REG_MEMORY_B 19
93#define MC13783_REG_RTC_TIME 20
94#define MC13783_REG_RTC_ALARM 21
95#define MC13783_REG_RTC_DAY 22
96#define MC13783_REG_RTC_DAY_ALARM 23
97#define MC13783_REG_SWITCHERS_0 24
98#define MC13783_REG_SWITCHERS_1 25
99#define MC13783_REG_SWITCHERS_2 26
100#define MC13783_REG_SWITCHERS_3 27
101#define MC13783_REG_SWITCHERS_4 28
102#define MC13783_REG_SWITCHERS_5 29
103#define MC13783_REG_REGULATOR_SETTING_0 30
104#define MC13783_REG_REGULATOR_SETTING_1 31
105#define MC13783_REG_REGULATOR_MODE_0 32
106#define MC13783_REG_REGULATOR_MODE_1 33
107#define MC13783_REG_POWER_MISCELLANEOUS 34
108#define MC13783_REG_POWER_SPARE 35
109#define MC13783_REG_AUDIO_RX_0 36
110#define MC13783_REG_AUDIO_RX_1 37
111#define MC13783_REG_AUDIO_TX 38
112#define MC13783_REG_AUDIO_SSI_NETWORK 39
113#define MC13783_REG_AUDIO_CODEC 40
114#define MC13783_REG_AUDIO_STEREO_DAC 41
115#define MC13783_REG_AUDIO_SPARE 42
116#define MC13783_REG_ADC_0 43
117#define MC13783_REG_ADC_1 44
118#define MC13783_REG_ADC_2 45
119#define MC13783_REG_ADC_3 46
120#define MC13783_REG_ADC_4 47
121#define MC13783_REG_CHARGER 48
122#define MC13783_REG_USB 49
123#define MC13783_REG_CHARGE_USB_SPARE 50
124#define MC13783_REG_LED_CONTROL_0 51
125#define MC13783_REG_LED_CONTROL_1 52
126#define MC13783_REG_LED_CONTROL_2 53
127#define MC13783_REG_LED_CONTROL_3 54
128#define MC13783_REG_LED_CONTROL_4 55
129#define MC13783_REG_LED_CONTROL_5 56
130#define MC13783_REG_SPARE 57
131#define MC13783_REG_TRIM_0 58
132#define MC13783_REG_TRIM_1 59
133#define MC13783_REG_TEST_0 60
134#define MC13783_REG_TEST_1 61
135#define MC13783_REG_TEST_2 62
136#define MC13783_REG_TEST_3 63
137#define MC13783_REG_NB 64
138
139
140/*
141 * Interrupt Status
142 */
143#define MC13783_INT_STAT_ADCDONEI (1 << 0)
144#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
145#define MC13783_INT_STAT_TSI (1 << 2)
146#define MC13783_INT_STAT_WHIGHI (1 << 3)
147#define MC13783_INT_STAT_WLOWI (1 << 4)
148#define MC13783_INT_STAT_CHGDETI (1 << 6)
149#define MC13783_INT_STAT_CHGOVI (1 << 7)
150#define MC13783_INT_STAT_CHGREVI (1 << 8)
151#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
152#define MC13783_INT_STAT_CCCVI (1 << 10)
153#define MC13783_INT_STAT_CHGCURRI (1 << 11)
154#define MC13783_INT_STAT_BPONI (1 << 12)
155#define MC13783_INT_STAT_LOBATLI (1 << 13)
156#define MC13783_INT_STAT_LOBATHI (1 << 14)
157#define MC13783_INT_STAT_UDPI (1 << 15)
158#define MC13783_INT_STAT_USBI (1 << 16)
159#define MC13783_INT_STAT_IDI (1 << 19)
160#define MC13783_INT_STAT_Unused (1 << 20)
161#define MC13783_INT_STAT_SE1I (1 << 21)
162#define MC13783_INT_STAT_CKDETI (1 << 22)
163#define MC13783_INT_STAT_UDMI (1 << 23)
164
165/*
166 * Interrupt Mask
167 */
168#define MC13783_INT_MASK_ADCDONEM (1 << 0)
169#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
170#define MC13783_INT_MASK_TSM (1 << 2)
171#define MC13783_INT_MASK_WHIGHM (1 << 3)
172#define MC13783_INT_MASK_WLOWM (1 << 4)
173#define MC13783_INT_MASK_CHGDETM (1 << 6)
174#define MC13783_INT_MASK_CHGOVM (1 << 7)
175#define MC13783_INT_MASK_CHGREVM (1 << 8)
176#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
177#define MC13783_INT_MASK_CCCVM (1 << 10)
178#define MC13783_INT_MASK_CHGCURRM (1 << 11)
179#define MC13783_INT_MASK_BPONM (1 << 12)
180#define MC13783_INT_MASK_LOBATLM (1 << 13)
181#define MC13783_INT_MASK_LOBATHM (1 << 14)
182#define MC13783_INT_MASK_UDPM (1 << 15)
183#define MC13783_INT_MASK_USBM (1 << 16)
184#define MC13783_INT_MASK_IDM (1 << 19)
185#define MC13783_INT_MASK_SE1M (1 << 21)
186#define MC13783_INT_MASK_CKDETM (1 << 22)
187
188/*
189 * Reg Regulator Mode 0
190 */
191#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
192#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
193#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
194#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
195#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
196#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
197#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
198#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
199#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
200#define MC13783_REGCTRL_VDIG_EN (1 << 9)
201#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
202#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
203#define MC13783_REGCTRL_VGEN_EN (1 << 12)
204#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
205#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
206#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
207#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
208#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
209#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
210#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
211#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
212#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
213#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
214#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
215
216/*
217 * Reg Regulator Mode 1
218 */
219#define MC13783_REGCTRL_VSIM_EN (1 << 0)
220#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
221#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
222#define MC13783_REGCTRL_VESIM_EN (1 << 3)
223#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
224#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
225#define MC13783_REGCTRL_VCAM_EN (1 << 6)
226#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
227#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
228#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
229#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
230#define MC13783_REGCTRL_VVIB_EN (1 << 11)
231#define MC13783_REGCTRL_VRF1_EN (1 << 12)
232#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
233#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
234#define MC13783_REGCTRL_VRF2_EN (1 << 15)
235#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
236#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
237#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
238#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
239#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
240#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
241#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
242#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
243
244/*
245 * Reg Regulator Misc.
246 */
247#define MC13783_REGCTRL_GPO1_EN (1 << 6)
248#define MC13783_REGCTRL_GPO2_EN (1 << 8)
249#define MC13783_REGCTRL_GPO3_EN (1 << 10)
250#define MC13783_REGCTRL_GPO4_EN (1 << 12)
251#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
252
253/*
254 * Reg Switcher 4
255 */
256#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
257#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
258#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
259#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
260#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
261#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
262#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
263#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
264#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
265#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
266#define MC13783_SWCTRL_PLL_EN (1 << 18)
267#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
268
269/*
270 * Reg Switcher 5
271 */
272#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
273#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
274#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
275#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
276#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
277#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
278#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
279#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
280#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
281#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
282#define MC13783_SWSET_SW3 (1 << 18)
283#define MC13783_SWCTRL_SW3_EN (1 << 20)
284#define MC13783_SWCTRL_SW3_STBY (1 << 21)
285#define MC13783_SWCTRL_SW3_MODE (1 << 22)
286
287/*
288 * ADC/Touch
289 */
290#define MC13783_ADC0_LICELLCON (1 << 0)
291#define MC13783_ADC0_CHRGICON (1 << 1)
292#define MC13783_ADC0_BATICON (1 << 2)
293#define MC13783_ADC0_RTHEN (1 << 3)
294#define MC13783_ADC0_DTHEN (1 << 4)
295#define MC13783_ADC0_UIDEN (1 << 5)
296#define MC13783_ADC0_ADOUTEN (1 << 6)
297#define MC13783_ADC0_ADOUTPER (1 << 7)
298#define MC13783_ADC0_ADREFEN (1 << 10)
299#define MC13783_ADC0_ADREFMODE (1 << 11)
300#define MC13783_ADC0_TSMOD0 (1 << 12)
301#define MC13783_ADC0_TSMOD1 (1 << 13)
302#define MC13783_ADC0_TSMOD2 (1 << 14)
303#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
304#define MC13783_ADC0_ADINC1 (1 << 16)
305#define MC13783_ADC0_ADINC2 (1 << 17)
306#define MC13783_ADC0_WCOMP (1 << 18)
307#define MC13783_ADC0_ADCBIS0 (1 << 23)
308
309#define MC13783_ADC1_ADEN (1 << 0)
310#define MC13783_ADC1_RAND (1 << 1)
311#define MC13783_ADC1_ADSEL (1 << 3)
312#define MC13783_ADC1_TRIGMASK (1 << 4)
313#define MC13783_ADC1_ADA10 (1 << 5)
314#define MC13783_ADC1_ADA11 (1 << 6)
315#define MC13783_ADC1_ADA12 (1 << 7)
316#define MC13783_ADC1_ADA20 (1 << 8)
317#define MC13783_ADC1_ADA21 (1 << 9)
318#define MC13783_ADC1_ADA22 (1 << 10)
319#define MC13783_ADC1_ATO0 (1 << 11)
320#define MC13783_ADC1_ATO1 (1 << 12)
321#define MC13783_ADC1_ATO2 (1 << 13)
322#define MC13783_ADC1_ATO3 (1 << 14)
323#define MC13783_ADC1_ATO4 (1 << 15)
324#define MC13783_ADC1_ATO5 (1 << 16)
325#define MC13783_ADC1_ATO6 (1 << 17)
326#define MC13783_ADC1_ATO7 (1 << 18)
327#define MC13783_ADC1_ATOX (1 << 19)
328#define MC13783_ADC1_ASC (1 << 20)
329#define MC13783_ADC1_ADTRIGIGN (1 << 21)
330#define MC13783_ADC1_ADONESHOT (1 << 22)
331#define MC13783_ADC1_ADCBIS1 (1 << 23)
332
333#define MC13783_ADC1_CHAN0_SHIFT 5
334#define MC13783_ADC1_CHAN1_SHIFT 8
335
336#define MC13783_ADC2_ADD10 (1 << 2)
337#define MC13783_ADC2_ADD11 (1 << 3)
338#define MC13783_ADC2_ADD12 (1 << 4)
339#define MC13783_ADC2_ADD13 (1 << 5)
340#define MC13783_ADC2_ADD14 (1 << 6)
341#define MC13783_ADC2_ADD15 (1 << 7)
342#define MC13783_ADC2_ADD16 (1 << 8)
343#define MC13783_ADC2_ADD17 (1 << 9)
344#define MC13783_ADC2_ADD18 (1 << 10)
345#define MC13783_ADC2_ADD19 (1 << 11)
346#define MC13783_ADC2_ADD20 (1 << 14)
347#define MC13783_ADC2_ADD21 (1 << 15)
348#define MC13783_ADC2_ADD22 (1 << 16)
349#define MC13783_ADC2_ADD23 (1 << 17)
350#define MC13783_ADC2_ADD24 (1 << 18)
351#define MC13783_ADC2_ADD25 (1 << 19)
352#define MC13783_ADC2_ADD26 (1 << 20)
353#define MC13783_ADC2_ADD27 (1 << 21)
354#define MC13783_ADC2_ADD28 (1 << 22)
355#define MC13783_ADC2_ADD29 (1 << 23)
356
357#define MC13783_ADC3_WHIGH0 (1 << 0)
358#define MC13783_ADC3_WHIGH1 (1 << 1)
359#define MC13783_ADC3_WHIGH2 (1 << 2)
360#define MC13783_ADC3_WHIGH3 (1 << 3)
361#define MC13783_ADC3_WHIGH4 (1 << 4)
362#define MC13783_ADC3_WHIGH5 (1 << 5)
363#define MC13783_ADC3_ICID0 (1 << 6)
364#define MC13783_ADC3_ICID1 (1 << 7)
365#define MC13783_ADC3_ICID2 (1 << 8)
366#define MC13783_ADC3_WLOW0 (1 << 9)
367#define MC13783_ADC3_WLOW1 (1 << 10)
368#define MC13783_ADC3_WLOW2 (1 << 11)
369#define MC13783_ADC3_WLOW3 (1 << 12)
370#define MC13783_ADC3_WLOW4 (1 << 13)
371#define MC13783_ADC3_WLOW5 (1 << 14)
372#define MC13783_ADC3_ADCBIS2 (1 << 23)
373
374#define MC13783_ADC4_ADDBIS10 (1 << 2)
375#define MC13783_ADC4_ADDBIS11 (1 << 3)
376#define MC13783_ADC4_ADDBIS12 (1 << 4)
377#define MC13783_ADC4_ADDBIS13 (1 << 5)
378#define MC13783_ADC4_ADDBIS14 (1 << 6)
379#define MC13783_ADC4_ADDBIS15 (1 << 7)
380#define MC13783_ADC4_ADDBIS16 (1 << 8)
381#define MC13783_ADC4_ADDBIS17 (1 << 9)
382#define MC13783_ADC4_ADDBIS18 (1 << 10)
383#define MC13783_ADC4_ADDBIS19 (1 << 11)
384#define MC13783_ADC4_ADDBIS20 (1 << 14)
385#define MC13783_ADC4_ADDBIS21 (1 << 15)
386#define MC13783_ADC4_ADDBIS22 (1 << 16)
387#define MC13783_ADC4_ADDBIS23 (1 << 17)
388#define MC13783_ADC4_ADDBIS24 (1 << 18)
389#define MC13783_ADC4_ADDBIS25 (1 << 19)
390#define MC13783_ADC4_ADDBIS26 (1 << 20)
391#define MC13783_ADC4_ADDBIS27 (1 << 21)
392#define MC13783_ADC4_ADDBIS28 (1 << 22)
393#define MC13783_ADC4_ADDBIS29 (1 << 23)
394
395#endif /* __LINUX_MFD_MC13783_PRIV_H */
396
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
new file mode 100644
index 000000000000..b3a2a7243573
--- /dev/null
+++ b/include/linux/mfd/mc13783.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __INCLUDE_LINUX_MFD_MC13783_H
23#define __INCLUDE_LINUX_MFD_MC13783_H
24
25struct mc13783;
26struct regulator_init_data;
27
28struct mc13783_regulator_init_data {
29 int id;
30 struct regulator_init_data *init_data;
31};
32
33struct mc13783_platform_data {
34 struct mc13783_regulator_init_data *regulators;
35 int num_regulators;
36 unsigned int flags;
37};
38
39/* mc13783_platform_data flags */
40#define MC13783_USE_TOUCHSCREEN (1 << 0)
41#define MC13783_USE_CODEC (1 << 1)
42#define MC13783_USE_ADC (1 << 2)
43#define MC13783_USE_RTC (1 << 3)
44#define MC13783_USE_REGULATOR (1 << 4)
45
46int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
47 unsigned int channel, unsigned int *sample);
48
49void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
50
51#define MC13783_SW_SW1A 0
52#define MC13783_SW_SW1B 1
53#define MC13783_SW_SW2A 2
54#define MC13783_SW_SW2B 3
55#define MC13783_SW_SW3 4
56#define MC13783_SW_PLL 5
57#define MC13783_REGU_VAUDIO 6
58#define MC13783_REGU_VIOHI 7
59#define MC13783_REGU_VIOLO 8
60#define MC13783_REGU_VDIG 9
61#define MC13783_REGU_VGEN 10
62#define MC13783_REGU_VRFDIG 11
63#define MC13783_REGU_VRFREF 12
64#define MC13783_REGU_VRFCP 13
65#define MC13783_REGU_VSIM 14
66#define MC13783_REGU_VESIM 15
67#define MC13783_REGU_VCAM 16
68#define MC13783_REGU_VRFBG 17
69#define MC13783_REGU_VVIB 18
70#define MC13783_REGU_VRF1 19
71#define MC13783_REGU_VRF2 20
72#define MC13783_REGU_VMMC1 21
73#define MC13783_REGU_VMMC2 22
74#define MC13783_REGU_GPO1 23
75#define MC13783_REGU_GPO2 24
76#define MC13783_REGU_GPO3 25
77#define MC13783_REGU_GPO4 26
78#define MC13783_REGU_V1 27
79#define MC13783_REGU_V2 28
80#define MC13783_REGU_V3 29
81#define MC13783_REGU_V4 30
82
83#endif /* __INCLUDE_LINUX_MFD_MC13783_H */
84
diff --git a/include/linux/mfd/pcf50633/adc.h b/include/linux/mfd/pcf50633/adc.h
index 56669b4183ad..b35e62801ffa 100644
--- a/include/linux/mfd/pcf50633/adc.h
+++ b/include/linux/mfd/pcf50633/adc.h
@@ -25,7 +25,8 @@
25#define PCF50633_REG_ADCS3 0x57 25#define PCF50633_REG_ADCS3 0x57
26 26
27#define PCF50633_ADCC1_ADCSTART 0x01 27#define PCF50633_ADCC1_ADCSTART 0x01
28#define PCF50633_ADCC1_RES_10BIT 0x02 28#define PCF50633_ADCC1_RES_8BIT 0x02
29#define PCF50633_ADCC1_RES_10BIT 0x00
29#define PCF50633_ADCC1_AVERAGE_NO 0x00 30#define PCF50633_ADCC1_AVERAGE_NO 0x00
30#define PCF50633_ADCC1_AVERAGE_4 0x04 31#define PCF50633_ADCC1_AVERAGE_4 0x04
31#define PCF50633_ADCC1_AVERAGE_8 0x08 32#define PCF50633_ADCC1_AVERAGE_8 0x08
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index c8f51c3c0a72..9aba7b779fbc 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -136,6 +136,7 @@ struct pcf50633 {
136 int irq; 136 int irq;
137 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; 137 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
138 struct work_struct irq_work; 138 struct work_struct irq_work;
139 struct workqueue_struct *work_queue;
139 struct mutex lock; 140 struct mutex lock;
140 141
141 u8 mask_regs[5]; 142 u8 mask_regs[5];
diff --git a/include/linux/mfd/wm831x/auxadc.h b/include/linux/mfd/wm831x/auxadc.h
new file mode 100644
index 000000000000..b132067e9e99
--- /dev/null
+++ b/include/linux/mfd/wm831x/auxadc.h
@@ -0,0 +1,216 @@
1/*
2 * include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_AUXADC_H__
16#define __MFD_WM831X_AUXADC_H__
17
18/*
19 * R16429 (0x402D) - AuxADC Data
20 */
21#define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
22#define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */
23#define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */
24#define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
25#define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
26#define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
27
28/*
29 * R16430 (0x402E) - AuxADC Control
30 */
31#define WM831X_AUX_ENA 0x8000 /* AUX_ENA */
32#define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */
33#define WM831X_AUX_ENA_SHIFT 15 /* AUX_ENA */
34#define WM831X_AUX_ENA_WIDTH 1 /* AUX_ENA */
35#define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */
36#define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */
37#define WM831X_AUX_CVT_ENA_SHIFT 14 /* AUX_CVT_ENA */
38#define WM831X_AUX_CVT_ENA_WIDTH 1 /* AUX_CVT_ENA */
39#define WM831X_AUX_SLPENA 0x1000 /* AUX_SLPENA */
40#define WM831X_AUX_SLPENA_MASK 0x1000 /* AUX_SLPENA */
41#define WM831X_AUX_SLPENA_SHIFT 12 /* AUX_SLPENA */
42#define WM831X_AUX_SLPENA_WIDTH 1 /* AUX_SLPENA */
43#define WM831X_AUX_FRC_ENA 0x0800 /* AUX_FRC_ENA */
44#define WM831X_AUX_FRC_ENA_MASK 0x0800 /* AUX_FRC_ENA */
45#define WM831X_AUX_FRC_ENA_SHIFT 11 /* AUX_FRC_ENA */
46#define WM831X_AUX_FRC_ENA_WIDTH 1 /* AUX_FRC_ENA */
47#define WM831X_AUX_RATE_MASK 0x003F /* AUX_RATE - [5:0] */
48#define WM831X_AUX_RATE_SHIFT 0 /* AUX_RATE - [5:0] */
49#define WM831X_AUX_RATE_WIDTH 6 /* AUX_RATE - [5:0] */
50
51/*
52 * R16431 (0x402F) - AuxADC Source
53 */
54#define WM831X_AUX_CAL_SEL 0x8000 /* AUX_CAL_SEL */
55#define WM831X_AUX_CAL_SEL_MASK 0x8000 /* AUX_CAL_SEL */
56#define WM831X_AUX_CAL_SEL_SHIFT 15 /* AUX_CAL_SEL */
57#define WM831X_AUX_CAL_SEL_WIDTH 1 /* AUX_CAL_SEL */
58#define WM831X_AUX_BKUP_BATT_SEL 0x0400 /* AUX_BKUP_BATT_SEL */
59#define WM831X_AUX_BKUP_BATT_SEL_MASK 0x0400 /* AUX_BKUP_BATT_SEL */
60#define WM831X_AUX_BKUP_BATT_SEL_SHIFT 10 /* AUX_BKUP_BATT_SEL */
61#define WM831X_AUX_BKUP_BATT_SEL_WIDTH 1 /* AUX_BKUP_BATT_SEL */
62#define WM831X_AUX_WALL_SEL 0x0200 /* AUX_WALL_SEL */
63#define WM831X_AUX_WALL_SEL_MASK 0x0200 /* AUX_WALL_SEL */
64#define WM831X_AUX_WALL_SEL_SHIFT 9 /* AUX_WALL_SEL */
65#define WM831X_AUX_WALL_SEL_WIDTH 1 /* AUX_WALL_SEL */
66#define WM831X_AUX_BATT_SEL 0x0100 /* AUX_BATT_SEL */
67#define WM831X_AUX_BATT_SEL_MASK 0x0100 /* AUX_BATT_SEL */
68#define WM831X_AUX_BATT_SEL_SHIFT 8 /* AUX_BATT_SEL */
69#define WM831X_AUX_BATT_SEL_WIDTH 1 /* AUX_BATT_SEL */
70#define WM831X_AUX_USB_SEL 0x0080 /* AUX_USB_SEL */
71#define WM831X_AUX_USB_SEL_MASK 0x0080 /* AUX_USB_SEL */
72#define WM831X_AUX_USB_SEL_SHIFT 7 /* AUX_USB_SEL */
73#define WM831X_AUX_USB_SEL_WIDTH 1 /* AUX_USB_SEL */
74#define WM831X_AUX_SYSVDD_SEL 0x0040 /* AUX_SYSVDD_SEL */
75#define WM831X_AUX_SYSVDD_SEL_MASK 0x0040 /* AUX_SYSVDD_SEL */
76#define WM831X_AUX_SYSVDD_SEL_SHIFT 6 /* AUX_SYSVDD_SEL */
77#define WM831X_AUX_SYSVDD_SEL_WIDTH 1 /* AUX_SYSVDD_SEL */
78#define WM831X_AUX_BATT_TEMP_SEL 0x0020 /* AUX_BATT_TEMP_SEL */
79#define WM831X_AUX_BATT_TEMP_SEL_MASK 0x0020 /* AUX_BATT_TEMP_SEL */
80#define WM831X_AUX_BATT_TEMP_SEL_SHIFT 5 /* AUX_BATT_TEMP_SEL */
81#define WM831X_AUX_BATT_TEMP_SEL_WIDTH 1 /* AUX_BATT_TEMP_SEL */
82#define WM831X_AUX_CHIP_TEMP_SEL 0x0010 /* AUX_CHIP_TEMP_SEL */
83#define WM831X_AUX_CHIP_TEMP_SEL_MASK 0x0010 /* AUX_CHIP_TEMP_SEL */
84#define WM831X_AUX_CHIP_TEMP_SEL_SHIFT 4 /* AUX_CHIP_TEMP_SEL */
85#define WM831X_AUX_CHIP_TEMP_SEL_WIDTH 1 /* AUX_CHIP_TEMP_SEL */
86#define WM831X_AUX_AUX4_SEL 0x0008 /* AUX_AUX4_SEL */
87#define WM831X_AUX_AUX4_SEL_MASK 0x0008 /* AUX_AUX4_SEL */
88#define WM831X_AUX_AUX4_SEL_SHIFT 3 /* AUX_AUX4_SEL */
89#define WM831X_AUX_AUX4_SEL_WIDTH 1 /* AUX_AUX4_SEL */
90#define WM831X_AUX_AUX3_SEL 0x0004 /* AUX_AUX3_SEL */
91#define WM831X_AUX_AUX3_SEL_MASK 0x0004 /* AUX_AUX3_SEL */
92#define WM831X_AUX_AUX3_SEL_SHIFT 2 /* AUX_AUX3_SEL */
93#define WM831X_AUX_AUX3_SEL_WIDTH 1 /* AUX_AUX3_SEL */
94#define WM831X_AUX_AUX2_SEL 0x0002 /* AUX_AUX2_SEL */
95#define WM831X_AUX_AUX2_SEL_MASK 0x0002 /* AUX_AUX2_SEL */
96#define WM831X_AUX_AUX2_SEL_SHIFT 1 /* AUX_AUX2_SEL */
97#define WM831X_AUX_AUX2_SEL_WIDTH 1 /* AUX_AUX2_SEL */
98#define WM831X_AUX_AUX1_SEL 0x0001 /* AUX_AUX1_SEL */
99#define WM831X_AUX_AUX1_SEL_MASK 0x0001 /* AUX_AUX1_SEL */
100#define WM831X_AUX_AUX1_SEL_SHIFT 0 /* AUX_AUX1_SEL */
101#define WM831X_AUX_AUX1_SEL_WIDTH 1 /* AUX_AUX1_SEL */
102
103/*
104 * R16432 (0x4030) - Comparator Control
105 */
106#define WM831X_DCOMP4_STS 0x0800 /* DCOMP4_STS */
107#define WM831X_DCOMP4_STS_MASK 0x0800 /* DCOMP4_STS */
108#define WM831X_DCOMP4_STS_SHIFT 11 /* DCOMP4_STS */
109#define WM831X_DCOMP4_STS_WIDTH 1 /* DCOMP4_STS */
110#define WM831X_DCOMP3_STS 0x0400 /* DCOMP3_STS */
111#define WM831X_DCOMP3_STS_MASK 0x0400 /* DCOMP3_STS */
112#define WM831X_DCOMP3_STS_SHIFT 10 /* DCOMP3_STS */
113#define WM831X_DCOMP3_STS_WIDTH 1 /* DCOMP3_STS */
114#define WM831X_DCOMP2_STS 0x0200 /* DCOMP2_STS */
115#define WM831X_DCOMP2_STS_MASK 0x0200 /* DCOMP2_STS */
116#define WM831X_DCOMP2_STS_SHIFT 9 /* DCOMP2_STS */
117#define WM831X_DCOMP2_STS_WIDTH 1 /* DCOMP2_STS */
118#define WM831X_DCOMP1_STS 0x0100 /* DCOMP1_STS */
119#define WM831X_DCOMP1_STS_MASK 0x0100 /* DCOMP1_STS */
120#define WM831X_DCOMP1_STS_SHIFT 8 /* DCOMP1_STS */
121#define WM831X_DCOMP1_STS_WIDTH 1 /* DCOMP1_STS */
122#define WM831X_DCMP4_ENA 0x0008 /* DCMP4_ENA */
123#define WM831X_DCMP4_ENA_MASK 0x0008 /* DCMP4_ENA */
124#define WM831X_DCMP4_ENA_SHIFT 3 /* DCMP4_ENA */
125#define WM831X_DCMP4_ENA_WIDTH 1 /* DCMP4_ENA */
126#define WM831X_DCMP3_ENA 0x0004 /* DCMP3_ENA */
127#define WM831X_DCMP3_ENA_MASK 0x0004 /* DCMP3_ENA */
128#define WM831X_DCMP3_ENA_SHIFT 2 /* DCMP3_ENA */
129#define WM831X_DCMP3_ENA_WIDTH 1 /* DCMP3_ENA */
130#define WM831X_DCMP2_ENA 0x0002 /* DCMP2_ENA */
131#define WM831X_DCMP2_ENA_MASK 0x0002 /* DCMP2_ENA */
132#define WM831X_DCMP2_ENA_SHIFT 1 /* DCMP2_ENA */
133#define WM831X_DCMP2_ENA_WIDTH 1 /* DCMP2_ENA */
134#define WM831X_DCMP1_ENA 0x0001 /* DCMP1_ENA */
135#define WM831X_DCMP1_ENA_MASK 0x0001 /* DCMP1_ENA */
136#define WM831X_DCMP1_ENA_SHIFT 0 /* DCMP1_ENA */
137#define WM831X_DCMP1_ENA_WIDTH 1 /* DCMP1_ENA */
138
139/*
140 * R16433 (0x4031) - Comparator 1
141 */
142#define WM831X_DCMP1_SRC_MASK 0xE000 /* DCMP1_SRC - [15:13] */
143#define WM831X_DCMP1_SRC_SHIFT 13 /* DCMP1_SRC - [15:13] */
144#define WM831X_DCMP1_SRC_WIDTH 3 /* DCMP1_SRC - [15:13] */
145#define WM831X_DCMP1_GT 0x1000 /* DCMP1_GT */
146#define WM831X_DCMP1_GT_MASK 0x1000 /* DCMP1_GT */
147#define WM831X_DCMP1_GT_SHIFT 12 /* DCMP1_GT */
148#define WM831X_DCMP1_GT_WIDTH 1 /* DCMP1_GT */
149#define WM831X_DCMP1_THR_MASK 0x0FFF /* DCMP1_THR - [11:0] */
150#define WM831X_DCMP1_THR_SHIFT 0 /* DCMP1_THR - [11:0] */
151#define WM831X_DCMP1_THR_WIDTH 12 /* DCMP1_THR - [11:0] */
152
153/*
154 * R16434 (0x4032) - Comparator 2
155 */
156#define WM831X_DCMP2_SRC_MASK 0xE000 /* DCMP2_SRC - [15:13] */
157#define WM831X_DCMP2_SRC_SHIFT 13 /* DCMP2_SRC - [15:13] */
158#define WM831X_DCMP2_SRC_WIDTH 3 /* DCMP2_SRC - [15:13] */
159#define WM831X_DCMP2_GT 0x1000 /* DCMP2_GT */
160#define WM831X_DCMP2_GT_MASK 0x1000 /* DCMP2_GT */
161#define WM831X_DCMP2_GT_SHIFT 12 /* DCMP2_GT */
162#define WM831X_DCMP2_GT_WIDTH 1 /* DCMP2_GT */
163#define WM831X_DCMP2_THR_MASK 0x0FFF /* DCMP2_THR - [11:0] */
164#define WM831X_DCMP2_THR_SHIFT 0 /* DCMP2_THR - [11:0] */
165#define WM831X_DCMP2_THR_WIDTH 12 /* DCMP2_THR - [11:0] */
166
167/*
168 * R16435 (0x4033) - Comparator 3
169 */
170#define WM831X_DCMP3_SRC_MASK 0xE000 /* DCMP3_SRC - [15:13] */
171#define WM831X_DCMP3_SRC_SHIFT 13 /* DCMP3_SRC - [15:13] */
172#define WM831X_DCMP3_SRC_WIDTH 3 /* DCMP3_SRC - [15:13] */
173#define WM831X_DCMP3_GT 0x1000 /* DCMP3_GT */
174#define WM831X_DCMP3_GT_MASK 0x1000 /* DCMP3_GT */
175#define WM831X_DCMP3_GT_SHIFT 12 /* DCMP3_GT */
176#define WM831X_DCMP3_GT_WIDTH 1 /* DCMP3_GT */
177#define WM831X_DCMP3_THR_MASK 0x0FFF /* DCMP3_THR - [11:0] */
178#define WM831X_DCMP3_THR_SHIFT 0 /* DCMP3_THR - [11:0] */
179#define WM831X_DCMP3_THR_WIDTH 12 /* DCMP3_THR - [11:0] */
180
181/*
182 * R16436 (0x4034) - Comparator 4
183 */
184#define WM831X_DCMP4_SRC_MASK 0xE000 /* DCMP4_SRC - [15:13] */
185#define WM831X_DCMP4_SRC_SHIFT 13 /* DCMP4_SRC - [15:13] */
186#define WM831X_DCMP4_SRC_WIDTH 3 /* DCMP4_SRC - [15:13] */
187#define WM831X_DCMP4_GT 0x1000 /* DCMP4_GT */
188#define WM831X_DCMP4_GT_MASK 0x1000 /* DCMP4_GT */
189#define WM831X_DCMP4_GT_SHIFT 12 /* DCMP4_GT */
190#define WM831X_DCMP4_GT_WIDTH 1 /* DCMP4_GT */
191#define WM831X_DCMP4_THR_MASK 0x0FFF /* DCMP4_THR - [11:0] */
192#define WM831X_DCMP4_THR_SHIFT 0 /* DCMP4_THR - [11:0] */
193#define WM831X_DCMP4_THR_WIDTH 12 /* DCMP4_THR - [11:0] */
194
195#define WM831X_AUX_CAL_FACTOR 0xfff
196#define WM831X_AUX_CAL_NOMINAL 0x222
197
198enum wm831x_auxadc {
199 WM831X_AUX_CAL = 15,
200 WM831X_AUX_BKUP_BATT = 10,
201 WM831X_AUX_WALL = 9,
202 WM831X_AUX_BATT = 8,
203 WM831X_AUX_USB = 7,
204 WM831X_AUX_SYSVDD = 6,
205 WM831X_AUX_BATT_TEMP = 5,
206 WM831X_AUX_CHIP_TEMP = 4,
207 WM831X_AUX_AUX4 = 3,
208 WM831X_AUX_AUX3 = 2,
209 WM831X_AUX_AUX2 = 1,
210 WM831X_AUX_AUX1 = 0,
211};
212
213int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input);
214int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input);
215
216#endif
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
new file mode 100644
index 000000000000..91eb493bf14c
--- /dev/null
+++ b/include/linux/mfd/wm831x/core.h
@@ -0,0 +1,289 @@
1/*
2 * include/linux/mfd/wm831x/core.h -- Core interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_CORE_H__
16#define __MFD_WM831X_CORE_H__
17
18#include <linux/interrupt.h>
19#include <linux/workqueue.h>
20
21/*
22 * Register values.
23 */
24#define WM831X_RESET_ID 0x00
25#define WM831X_REVISION 0x01
26#define WM831X_PARENT_ID 0x4000
27#define WM831X_SYSVDD_CONTROL 0x4001
28#define WM831X_THERMAL_MONITORING 0x4002
29#define WM831X_POWER_STATE 0x4003
30#define WM831X_WATCHDOG 0x4004
31#define WM831X_ON_PIN_CONTROL 0x4005
32#define WM831X_RESET_CONTROL 0x4006
33#define WM831X_CONTROL_INTERFACE 0x4007
34#define WM831X_SECURITY_KEY 0x4008
35#define WM831X_SOFTWARE_SCRATCH 0x4009
36#define WM831X_OTP_CONTROL 0x400A
37#define WM831X_GPIO_LEVEL 0x400C
38#define WM831X_SYSTEM_STATUS 0x400D
39#define WM831X_ON_SOURCE 0x400E
40#define WM831X_OFF_SOURCE 0x400F
41#define WM831X_SYSTEM_INTERRUPTS 0x4010
42#define WM831X_INTERRUPT_STATUS_1 0x4011
43#define WM831X_INTERRUPT_STATUS_2 0x4012
44#define WM831X_INTERRUPT_STATUS_3 0x4013
45#define WM831X_INTERRUPT_STATUS_4 0x4014
46#define WM831X_INTERRUPT_STATUS_5 0x4015
47#define WM831X_IRQ_CONFIG 0x4017
48#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
49#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
50#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
51#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
52#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
53#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
54#define WM831X_RTC_WRITE_COUNTER 0x4020
55#define WM831X_RTC_TIME_1 0x4021
56#define WM831X_RTC_TIME_2 0x4022
57#define WM831X_RTC_ALARM_1 0x4023
58#define WM831X_RTC_ALARM_2 0x4024
59#define WM831X_RTC_CONTROL 0x4025
60#define WM831X_RTC_TRIM 0x4026
61#define WM831X_TOUCH_CONTROL_1 0x4028
62#define WM831X_TOUCH_CONTROL_2 0x4029
63#define WM831X_TOUCH_DATA_X 0x402A
64#define WM831X_TOUCH_DATA_Y 0x402B
65#define WM831X_TOUCH_DATA_Z 0x402C
66#define WM831X_AUXADC_DATA 0x402D
67#define WM831X_AUXADC_CONTROL 0x402E
68#define WM831X_AUXADC_SOURCE 0x402F
69#define WM831X_COMPARATOR_CONTROL 0x4030
70#define WM831X_COMPARATOR_1 0x4031
71#define WM831X_COMPARATOR_2 0x4032
72#define WM831X_COMPARATOR_3 0x4033
73#define WM831X_COMPARATOR_4 0x4034
74#define WM831X_GPIO1_CONTROL 0x4038
75#define WM831X_GPIO2_CONTROL 0x4039
76#define WM831X_GPIO3_CONTROL 0x403A
77#define WM831X_GPIO4_CONTROL 0x403B
78#define WM831X_GPIO5_CONTROL 0x403C
79#define WM831X_GPIO6_CONTROL 0x403D
80#define WM831X_GPIO7_CONTROL 0x403E
81#define WM831X_GPIO8_CONTROL 0x403F
82#define WM831X_GPIO9_CONTROL 0x4040
83#define WM831X_GPIO10_CONTROL 0x4041
84#define WM831X_GPIO11_CONTROL 0x4042
85#define WM831X_GPIO12_CONTROL 0x4043
86#define WM831X_GPIO13_CONTROL 0x4044
87#define WM831X_GPIO14_CONTROL 0x4045
88#define WM831X_GPIO15_CONTROL 0x4046
89#define WM831X_GPIO16_CONTROL 0x4047
90#define WM831X_CHARGER_CONTROL_1 0x4048
91#define WM831X_CHARGER_CONTROL_2 0x4049
92#define WM831X_CHARGER_STATUS 0x404A
93#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
94#define WM831X_STATUS_LED_1 0x404C
95#define WM831X_STATUS_LED_2 0x404D
96#define WM831X_CURRENT_SINK_1 0x404E
97#define WM831X_CURRENT_SINK_2 0x404F
98#define WM831X_DCDC_ENABLE 0x4050
99#define WM831X_LDO_ENABLE 0x4051
100#define WM831X_DCDC_STATUS 0x4052
101#define WM831X_LDO_STATUS 0x4053
102#define WM831X_DCDC_UV_STATUS 0x4054
103#define WM831X_LDO_UV_STATUS 0x4055
104#define WM831X_DC1_CONTROL_1 0x4056
105#define WM831X_DC1_CONTROL_2 0x4057
106#define WM831X_DC1_ON_CONFIG 0x4058
107#define WM831X_DC1_SLEEP_CONTROL 0x4059
108#define WM831X_DC1_DVS_CONTROL 0x405A
109#define WM831X_DC2_CONTROL_1 0x405B
110#define WM831X_DC2_CONTROL_2 0x405C
111#define WM831X_DC2_ON_CONFIG 0x405D
112#define WM831X_DC2_SLEEP_CONTROL 0x405E
113#define WM831X_DC2_DVS_CONTROL 0x405F
114#define WM831X_DC3_CONTROL_1 0x4060
115#define WM831X_DC3_CONTROL_2 0x4061
116#define WM831X_DC3_ON_CONFIG 0x4062
117#define WM831X_DC3_SLEEP_CONTROL 0x4063
118#define WM831X_DC4_CONTROL 0x4064
119#define WM831X_DC4_SLEEP_CONTROL 0x4065
120#define WM831X_EPE1_CONTROL 0x4066
121#define WM831X_EPE2_CONTROL 0x4067
122#define WM831X_LDO1_CONTROL 0x4068
123#define WM831X_LDO1_ON_CONTROL 0x4069
124#define WM831X_LDO1_SLEEP_CONTROL 0x406A
125#define WM831X_LDO2_CONTROL 0x406B
126#define WM831X_LDO2_ON_CONTROL 0x406C
127#define WM831X_LDO2_SLEEP_CONTROL 0x406D
128#define WM831X_LDO3_CONTROL 0x406E
129#define WM831X_LDO3_ON_CONTROL 0x406F
130#define WM831X_LDO3_SLEEP_CONTROL 0x4070
131#define WM831X_LDO4_CONTROL 0x4071
132#define WM831X_LDO4_ON_CONTROL 0x4072
133#define WM831X_LDO4_SLEEP_CONTROL 0x4073
134#define WM831X_LDO5_CONTROL 0x4074
135#define WM831X_LDO5_ON_CONTROL 0x4075
136#define WM831X_LDO5_SLEEP_CONTROL 0x4076
137#define WM831X_LDO6_CONTROL 0x4077
138#define WM831X_LDO6_ON_CONTROL 0x4078
139#define WM831X_LDO6_SLEEP_CONTROL 0x4079
140#define WM831X_LDO7_CONTROL 0x407A
141#define WM831X_LDO7_ON_CONTROL 0x407B
142#define WM831X_LDO7_SLEEP_CONTROL 0x407C
143#define WM831X_LDO8_CONTROL 0x407D
144#define WM831X_LDO8_ON_CONTROL 0x407E
145#define WM831X_LDO8_SLEEP_CONTROL 0x407F
146#define WM831X_LDO9_CONTROL 0x4080
147#define WM831X_LDO9_ON_CONTROL 0x4081
148#define WM831X_LDO9_SLEEP_CONTROL 0x4082
149#define WM831X_LDO10_CONTROL 0x4083
150#define WM831X_LDO10_ON_CONTROL 0x4084
151#define WM831X_LDO10_SLEEP_CONTROL 0x4085
152#define WM831X_LDO11_ON_CONTROL 0x4087
153#define WM831X_LDO11_SLEEP_CONTROL 0x4088
154#define WM831X_POWER_GOOD_SOURCE_1 0x408E
155#define WM831X_POWER_GOOD_SOURCE_2 0x408F
156#define WM831X_CLOCK_CONTROL_1 0x4090
157#define WM831X_CLOCK_CONTROL_2 0x4091
158#define WM831X_FLL_CONTROL_1 0x4092
159#define WM831X_FLL_CONTROL_2 0x4093
160#define WM831X_FLL_CONTROL_3 0x4094
161#define WM831X_FLL_CONTROL_4 0x4095
162#define WM831X_FLL_CONTROL_5 0x4096
163#define WM831X_UNIQUE_ID_1 0x7800
164#define WM831X_UNIQUE_ID_2 0x7801
165#define WM831X_UNIQUE_ID_3 0x7802
166#define WM831X_UNIQUE_ID_4 0x7803
167#define WM831X_UNIQUE_ID_5 0x7804
168#define WM831X_UNIQUE_ID_6 0x7805
169#define WM831X_UNIQUE_ID_7 0x7806
170#define WM831X_UNIQUE_ID_8 0x7807
171#define WM831X_FACTORY_OTP_ID 0x7808
172#define WM831X_FACTORY_OTP_1 0x7809
173#define WM831X_FACTORY_OTP_2 0x780A
174#define WM831X_FACTORY_OTP_3 0x780B
175#define WM831X_FACTORY_OTP_4 0x780C
176#define WM831X_FACTORY_OTP_5 0x780D
177#define WM831X_CUSTOMER_OTP_ID 0x7810
178#define WM831X_DC1_OTP_CONTROL 0x7811
179#define WM831X_DC2_OTP_CONTROL 0x7812
180#define WM831X_DC3_OTP_CONTROL 0x7813
181#define WM831X_LDO1_2_OTP_CONTROL 0x7814
182#define WM831X_LDO3_4_OTP_CONTROL 0x7815
183#define WM831X_LDO5_6_OTP_CONTROL 0x7816
184#define WM831X_LDO7_8_OTP_CONTROL 0x7817
185#define WM831X_LDO9_10_OTP_CONTROL 0x7818
186#define WM831X_LDO11_EPE_CONTROL 0x7819
187#define WM831X_GPIO1_OTP_CONTROL 0x781A
188#define WM831X_GPIO2_OTP_CONTROL 0x781B
189#define WM831X_GPIO3_OTP_CONTROL 0x781C
190#define WM831X_GPIO4_OTP_CONTROL 0x781D
191#define WM831X_GPIO5_OTP_CONTROL 0x781E
192#define WM831X_GPIO6_OTP_CONTROL 0x781F
193#define WM831X_DBE_CHECK_DATA 0x7827
194
195/*
196 * R0 (0x00) - Reset ID
197 */
198#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
199#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
200#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
201
202/*
203 * R1 (0x01) - Revision
204 */
205#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
206#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
207#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
208#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
209#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
210#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
211
212/*
213 * R16384 (0x4000) - Parent ID
214 */
215#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
216#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
217#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
218
219/*
220 * R16389 (0x4005) - ON Pin Control
221 */
222#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
223#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
224#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
225#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
226#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
227#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
228#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
229#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
230#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
231#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
232#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
233#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
234#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
235
236struct regulator_dev;
237
238struct wm831x {
239 struct mutex io_lock;
240
241 struct device *dev;
242 int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
243 int bytes, void *dest);
244 int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
245 int bytes, void *src);
246
247 void *control_data;
248
249 int irq; /* Our chip IRQ */
250 struct mutex irq_lock;
251 struct workqueue_struct *irq_wq;
252 struct work_struct irq_work;
253 unsigned int irq_base;
254 int irq_masks[5];
255
256 struct mutex auxadc_lock;
257
258 /* The WM831x has a security key blocking access to certain
259 * registers. The mutex is taken by the accessors for locking
260 * and unlocking the security key, locked is used to fail
261 * writes if the lock is held.
262 */
263 struct mutex key_lock;
264 unsigned int locked:1;
265};
266
267/* Device I/O API */
268int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
269int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
270 unsigned short val);
271void wm831x_reg_lock(struct wm831x *wm831x);
272int wm831x_reg_unlock(struct wm831x *wm831x);
273int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
274 unsigned short mask, unsigned short val);
275int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
276 int count, u16 *buf);
277
278int wm831x_irq_init(struct wm831x *wm831x, int irq);
279void wm831x_irq_exit(struct wm831x *wm831x);
280
281int __must_check wm831x_request_irq(struct wm831x *wm831x,
282 unsigned int irq, irq_handler_t handler,
283 unsigned long flags, const char *name,
284 void *dev);
285void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
286void wm831x_disable_irq(struct wm831x *wm831x, int irq);
287void wm831x_enable_irq(struct wm831x *wm831x, int irq);
288
289#endif
diff --git a/include/linux/mfd/wm831x/gpio.h b/include/linux/mfd/wm831x/gpio.h
new file mode 100644
index 000000000000..2835614af0e3
--- /dev/null
+++ b/include/linux/mfd/wm831x/gpio.h
@@ -0,0 +1,55 @@
1/*
2 * include/linux/mfd/wm831x/gpio.h -- GPIO for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_GPIO_H__
16#define __MFD_WM831X_GPIO_H__
17
18/*
19 * R16440-16455 (0x4038-0x4047) - GPIOx Control
20 */
21#define WM831X_GPN_DIR 0x8000 /* GPN_DIR */
22#define WM831X_GPN_DIR_MASK 0x8000 /* GPN_DIR */
23#define WM831X_GPN_DIR_SHIFT 15 /* GPN_DIR */
24#define WM831X_GPN_DIR_WIDTH 1 /* GPN_DIR */
25#define WM831X_GPN_PULL_MASK 0x6000 /* GPN_PULL - [14:13] */
26#define WM831X_GPN_PULL_SHIFT 13 /* GPN_PULL - [14:13] */
27#define WM831X_GPN_PULL_WIDTH 2 /* GPN_PULL - [14:13] */
28#define WM831X_GPN_INT_MODE 0x1000 /* GPN_INT_MODE */
29#define WM831X_GPN_INT_MODE_MASK 0x1000 /* GPN_INT_MODE */
30#define WM831X_GPN_INT_MODE_SHIFT 12 /* GPN_INT_MODE */
31#define WM831X_GPN_INT_MODE_WIDTH 1 /* GPN_INT_MODE */
32#define WM831X_GPN_PWR_DOM 0x0800 /* GPN_PWR_DOM */
33#define WM831X_GPN_PWR_DOM_MASK 0x0800 /* GPN_PWR_DOM */
34#define WM831X_GPN_PWR_DOM_SHIFT 11 /* GPN_PWR_DOM */
35#define WM831X_GPN_PWR_DOM_WIDTH 1 /* GPN_PWR_DOM */
36#define WM831X_GPN_POL 0x0400 /* GPN_POL */
37#define WM831X_GPN_POL_MASK 0x0400 /* GPN_POL */
38#define WM831X_GPN_POL_SHIFT 10 /* GPN_POL */
39#define WM831X_GPN_POL_WIDTH 1 /* GPN_POL */
40#define WM831X_GPN_OD 0x0200 /* GPN_OD */
41#define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */
42#define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */
43#define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */
44#define WM831X_GPN_TRI 0x0080 /* GPN_TRI */
45#define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */
46#define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */
47#define WM831X_GPN_TRI_WIDTH 1 /* GPN_TRI */
48#define WM831X_GPN_FN_MASK 0x000F /* GPN_FN - [3:0] */
49#define WM831X_GPN_FN_SHIFT 0 /* GPN_FN - [3:0] */
50#define WM831X_GPN_FN_WIDTH 4 /* GPN_FN - [3:0] */
51
52#define WM831X_GPIO_PULL_NONE (0 << WM831X_GPN_PULL_SHIFT)
53#define WM831X_GPIO_PULL_DOWN (1 << WM831X_GPN_PULL_SHIFT)
54#define WM831X_GPIO_PULL_UP (2 << WM831X_GPN_PULL_SHIFT)
55#endif
diff --git a/include/linux/mfd/wm831x/irq.h b/include/linux/mfd/wm831x/irq.h
new file mode 100644
index 000000000000..3a8c97656fda
--- /dev/null
+++ b/include/linux/mfd/wm831x/irq.h
@@ -0,0 +1,764 @@
1/*
2 * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_IRQ_H__
16#define __MFD_WM831X_IRQ_H__
17
18/* Interrupt number assignments within Linux */
19#define WM831X_IRQ_TEMP_THW 0
20#define WM831X_IRQ_GPIO_1 1
21#define WM831X_IRQ_GPIO_2 2
22#define WM831X_IRQ_GPIO_3 3
23#define WM831X_IRQ_GPIO_4 4
24#define WM831X_IRQ_GPIO_5 5
25#define WM831X_IRQ_GPIO_6 6
26#define WM831X_IRQ_GPIO_7 7
27#define WM831X_IRQ_GPIO_8 8
28#define WM831X_IRQ_GPIO_9 9
29#define WM831X_IRQ_GPIO_10 10
30#define WM831X_IRQ_GPIO_11 11
31#define WM831X_IRQ_GPIO_12 12
32#define WM831X_IRQ_GPIO_13 13
33#define WM831X_IRQ_GPIO_14 14
34#define WM831X_IRQ_GPIO_15 15
35#define WM831X_IRQ_GPIO_16 16
36#define WM831X_IRQ_ON 17
37#define WM831X_IRQ_PPM_SYSLO 18
38#define WM831X_IRQ_PPM_PWR_SRC 19
39#define WM831X_IRQ_PPM_USB_CURR 20
40#define WM831X_IRQ_WDOG_TO 21
41#define WM831X_IRQ_RTC_PER 22
42#define WM831X_IRQ_RTC_ALM 23
43#define WM831X_IRQ_CHG_BATT_HOT 24
44#define WM831X_IRQ_CHG_BATT_COLD 25
45#define WM831X_IRQ_CHG_BATT_FAIL 26
46#define WM831X_IRQ_CHG_OV 27
47#define WM831X_IRQ_CHG_END 29
48#define WM831X_IRQ_CHG_TO 30
49#define WM831X_IRQ_CHG_MODE 31
50#define WM831X_IRQ_CHG_START 32
51#define WM831X_IRQ_TCHDATA 33
52#define WM831X_IRQ_TCHPD 34
53#define WM831X_IRQ_AUXADC_DATA 35
54#define WM831X_IRQ_AUXADC_DCOMP1 36
55#define WM831X_IRQ_AUXADC_DCOMP2 37
56#define WM831X_IRQ_AUXADC_DCOMP3 38
57#define WM831X_IRQ_AUXADC_DCOMP4 39
58#define WM831X_IRQ_CS1 40
59#define WM831X_IRQ_CS2 41
60#define WM831X_IRQ_HC_DC1 42
61#define WM831X_IRQ_HC_DC2 43
62#define WM831X_IRQ_UV_LDO1 44
63#define WM831X_IRQ_UV_LDO2 45
64#define WM831X_IRQ_UV_LDO3 46
65#define WM831X_IRQ_UV_LDO4 47
66#define WM831X_IRQ_UV_LDO5 48
67#define WM831X_IRQ_UV_LDO6 49
68#define WM831X_IRQ_UV_LDO7 50
69#define WM831X_IRQ_UV_LDO8 51
70#define WM831X_IRQ_UV_LDO9 52
71#define WM831X_IRQ_UV_LDO10 53
72#define WM831X_IRQ_UV_DC1 54
73#define WM831X_IRQ_UV_DC2 55
74#define WM831X_IRQ_UV_DC3 56
75#define WM831X_IRQ_UV_DC4 57
76
77#define WM831X_NUM_IRQS 58
78
79/*
80 * R16400 (0x4010) - System Interrupts
81 */
82#define WM831X_PS_INT 0x8000 /* PS_INT */
83#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
84#define WM831X_PS_INT_SHIFT 15 /* PS_INT */
85#define WM831X_PS_INT_WIDTH 1 /* PS_INT */
86#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
87#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
88#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */
89#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */
90#define WM831X_GP_INT 0x2000 /* GP_INT */
91#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
92#define WM831X_GP_INT_SHIFT 13 /* GP_INT */
93#define WM831X_GP_INT_WIDTH 1 /* GP_INT */
94#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
95#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
96#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */
97#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */
98#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
99#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
100#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */
101#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */
102#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
103#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
104#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */
105#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */
106#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
107#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
108#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */
109#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */
110#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
111#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
112#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */
113#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */
114#define WM831X_PPM_INT 0x0080 /* PPM_INT */
115#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
116#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */
117#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */
118#define WM831X_CS_INT 0x0040 /* CS_INT */
119#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
120#define WM831X_CS_INT_SHIFT 6 /* CS_INT */
121#define WM831X_CS_INT_WIDTH 1 /* CS_INT */
122#define WM831X_RTC_INT 0x0020 /* RTC_INT */
123#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
124#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */
125#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */
126#define WM831X_OTP_INT 0x0010 /* OTP_INT */
127#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
128#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */
129#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */
130#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
131#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
132#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */
133#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */
134#define WM831X_CHG_INT 0x0004 /* CHG_INT */
135#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
136#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */
137#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */
138#define WM831X_HC_INT 0x0002 /* HC_INT */
139#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
140#define WM831X_HC_INT_SHIFT 1 /* HC_INT */
141#define WM831X_HC_INT_WIDTH 1 /* HC_INT */
142#define WM831X_UV_INT 0x0001 /* UV_INT */
143#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
144#define WM831X_UV_INT_SHIFT 0 /* UV_INT */
145#define WM831X_UV_INT_WIDTH 1 /* UV_INT */
146
147/*
148 * R16401 (0x4011) - Interrupt Status 1
149 */
150#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
151#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
152#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */
153#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */
154#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
155#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
156#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */
157#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */
158#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
159#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
160#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */
161#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */
162#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
163#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
164#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */
165#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */
166#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
167#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
168#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */
169#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */
170#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
171#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
172#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */
173#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */
174#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
175#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
176#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */
177#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */
178#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
179#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
180#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */
181#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */
182#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
183#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
184#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */
185#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */
186#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
187#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
188#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */
189#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */
190#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
191#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
192#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */
193#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */
194#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
195#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
196#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */
197#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */
198#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
199#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
200#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */
201#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */
202#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
203#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
204#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */
205#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */
206#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
207#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
208#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */
209#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */
210
211/*
212 * R16402 (0x4012) - Interrupt Status 2
213 */
214#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
215#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
216#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */
217#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */
218#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
219#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
220#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */
221#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */
222#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
223#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
224#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */
225#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */
226#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
227#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
228#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */
229#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */
230#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
231#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
232#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */
233#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */
234#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
235#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
236#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */
237#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */
238#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
239#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
240#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */
241#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */
242#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
243#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
244#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */
245#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */
246#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
247#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
248#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */
249#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */
250#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
251#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
252#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */
253#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */
254#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
255#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
256#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */
257#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */
258#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
259#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
260#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */
261#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */
262#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
263#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
264#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */
265#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */
266#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
267#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
268#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */
269#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */
270#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
271#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
272#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
273#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */
274
275/*
276 * R16403 (0x4013) - Interrupt Status 3
277 */
278#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
279#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
280#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */
281#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */
282#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
283#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
284#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */
285#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */
286#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
287#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
288#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */
289#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */
290#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
291#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
292#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */
293#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */
294#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
295#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
296#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */
297#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */
298#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
299#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
300#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */
301#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */
302#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
303#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
304#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */
305#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */
306#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
307#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
308#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */
309#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */
310#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
311#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
312#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */
313#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */
314#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
315#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
316#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
317#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */
318
319/*
320 * R16404 (0x4014) - Interrupt Status 4
321 */
322#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
323#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
324#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */
325#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */
326#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
327#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
328#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */
329#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */
330#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
331#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
332#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */
333#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */
334#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
335#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
336#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */
337#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */
338#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
339#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
340#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */
341#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */
342#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
343#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
344#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
345#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */
346
347/*
348 * R16405 (0x4015) - Interrupt Status 5
349 */
350#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
351#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
352#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */
353#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */
354#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
355#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
356#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */
357#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */
358#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
359#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
360#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */
361#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */
362#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
363#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
364#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */
365#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */
366#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
367#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
368#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */
369#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */
370#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
371#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
372#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */
373#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */
374#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
375#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
376#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */
377#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */
378#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
379#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
380#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */
381#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */
382#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
383#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
384#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */
385#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */
386#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
387#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
388#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */
389#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */
390#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
391#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
392#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */
393#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */
394#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
395#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
396#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */
397#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */
398#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
399#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
400#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */
401#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */
402#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
403#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
404#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */
405#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */
406#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
407#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
408#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */
409#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */
410#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
411#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
412#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
413#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */
414
415/*
416 * R16407 (0x4017) - IRQ Config
417 */
418#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
419#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
420#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */
421#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */
422#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
423#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
424#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
425#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */
426
427/*
428 * R16408 (0x4018) - System Interrupts Mask
429 */
430#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
431#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
432#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */
433#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */
434#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
435#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
436#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */
437#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */
438#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
439#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
440#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */
441#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */
442#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
443#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
444#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */
445#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */
446#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
447#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
448#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */
449#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */
450#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
451#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
452#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */
453#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */
454#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
455#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
456#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */
457#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */
458#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
459#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
460#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */
461#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */
462#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
463#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
464#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */
465#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */
466#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
467#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
468#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */
469#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */
470#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
471#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
472#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */
473#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */
474#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
475#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
476#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */
477#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */
478#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
479#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
480#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */
481#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */
482#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
483#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
484#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */
485#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */
486#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
487#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
488#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */
489#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */
490#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
491#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
492#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
493#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */
494
495/*
496 * R16409 (0x4019) - Interrupt Status 1 Mask
497 */
498#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
499#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
500#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */
501#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */
502#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
503#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
504#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */
505#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */
506#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
507#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
508#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */
509#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */
510#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
511#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
512#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */
513#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */
514#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
515#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
516#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */
517#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */
518#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
519#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
520#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */
521#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */
522#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
523#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
524#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */
525#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */
526#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
527#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
528#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */
529#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */
530#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
531#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
532#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */
533#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */
534#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
535#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
536#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */
537#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */
538#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
539#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
540#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */
541#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */
542#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
543#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
544#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */
545#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */
546#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
547#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
548#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */
549#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */
550#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
551#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
552#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */
553#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */
554#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
555#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
556#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */
557#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */
558
559/*
560 * R16410 (0x401A) - Interrupt Status 2 Mask
561 */
562#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
563#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
564#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */
565#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */
566#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
567#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
568#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */
569#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */
570#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
571#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
572#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */
573#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */
574#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
575#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
576#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */
577#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */
578#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
579#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
580#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */
581#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */
582#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
583#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
584#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */
585#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */
586#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
587#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
588#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */
589#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */
590#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
591#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
592#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */
593#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */
594#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
595#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
596#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */
597#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */
598#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
599#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
600#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */
601#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */
602#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
603#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
604#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */
605#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */
606#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
607#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
608#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */
609#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */
610#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
611#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
612#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */
613#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */
614#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
615#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
616#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */
617#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */
618#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
619#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
620#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
621#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */
622
623/*
624 * R16411 (0x401B) - Interrupt Status 3 Mask
625 */
626#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
627#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
628#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */
629#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */
630#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
631#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
632#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */
633#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */
634#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
635#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
636#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */
637#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */
638#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
639#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
640#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */
641#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */
642#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
643#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
644#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */
645#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */
646#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
647#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
648#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */
649#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */
650#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
651#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
652#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */
653#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */
654#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
655#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
656#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */
657#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */
658#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
659#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
660#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */
661#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */
662#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
663#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
664#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
665#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */
666
667/*
668 * R16412 (0x401C) - Interrupt Status 4 Mask
669 */
670#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
671#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
672#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */
673#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */
674#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
675#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
676#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */
677#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */
678#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
679#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
680#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */
681#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */
682#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
683#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
684#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */
685#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */
686#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
687#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
688#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */
689#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */
690#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
691#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
692#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
693#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */
694
695/*
696 * R16413 (0x401D) - Interrupt Status 5 Mask
697 */
698#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
699#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
700#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */
701#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */
702#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
703#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
704#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */
705#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */
706#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
707#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
708#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
709#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
710#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
711#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
712#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
713#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
714#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
715#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
716#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
717#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
718#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
719#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
720#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
721#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
722#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
723#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
724#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
725#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
726#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
727#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
728#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
729#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
730#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
731#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
732#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
733#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
734#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
735#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
736#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
737#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
738#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
739#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
740#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
741#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
742#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
743#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
744#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
745#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
746#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
747#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
748#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
749#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
750#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
751#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
752#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
753#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
754#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
755#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
756#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
757#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
758#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
759#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
760#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
761#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
762
763
764#endif
diff --git a/include/linux/mfd/wm831x/otp.h b/include/linux/mfd/wm831x/otp.h
new file mode 100644
index 000000000000..ce1f81a39bfc
--- /dev/null
+++ b/include/linux/mfd/wm831x/otp.h
@@ -0,0 +1,162 @@
1/*
2 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_OTP_H__
16#define __MFD_WM831X_OTP_H__
17
18int wm831x_otp_init(struct wm831x *wm831x);
19void wm831x_otp_exit(struct wm831x *wm831x);
20
21/*
22 * R30720 (0x7800) - Unique ID 1
23 */
24#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
25#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
26#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
27
28/*
29 * R30721 (0x7801) - Unique ID 2
30 */
31#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
32#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
33#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
34
35/*
36 * R30722 (0x7802) - Unique ID 3
37 */
38#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
39#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
40#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
41
42/*
43 * R30723 (0x7803) - Unique ID 4
44 */
45#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
46#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
47#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
48
49/*
50 * R30724 (0x7804) - Unique ID 5
51 */
52#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
53#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
54#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
55
56/*
57 * R30725 (0x7805) - Unique ID 6
58 */
59#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
60#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
61#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
62
63/*
64 * R30726 (0x7806) - Unique ID 7
65 */
66#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
67#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
68#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
69
70/*
71 * R30727 (0x7807) - Unique ID 8
72 */
73#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
74#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
75#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
76
77/*
78 * R30728 (0x7808) - Factory OTP ID
79 */
80#define WM831X_OTP_FACT_ID_MASK 0xFFFE /* OTP_FACT_ID - [15:1] */
81#define WM831X_OTP_FACT_ID_SHIFT 1 /* OTP_FACT_ID - [15:1] */
82#define WM831X_OTP_FACT_ID_WIDTH 15 /* OTP_FACT_ID - [15:1] */
83#define WM831X_OTP_FACT_FINAL 0x0001 /* OTP_FACT_FINAL */
84#define WM831X_OTP_FACT_FINAL_MASK 0x0001 /* OTP_FACT_FINAL */
85#define WM831X_OTP_FACT_FINAL_SHIFT 0 /* OTP_FACT_FINAL */
86#define WM831X_OTP_FACT_FINAL_WIDTH 1 /* OTP_FACT_FINAL */
87
88/*
89 * R30729 (0x7809) - Factory OTP 1
90 */
91#define WM831X_DC3_TRIM_MASK 0xF000 /* DC3_TRIM - [15:12] */
92#define WM831X_DC3_TRIM_SHIFT 12 /* DC3_TRIM - [15:12] */
93#define WM831X_DC3_TRIM_WIDTH 4 /* DC3_TRIM - [15:12] */
94#define WM831X_DC2_TRIM_MASK 0x0FC0 /* DC2_TRIM - [11:6] */
95#define WM831X_DC2_TRIM_SHIFT 6 /* DC2_TRIM - [11:6] */
96#define WM831X_DC2_TRIM_WIDTH 6 /* DC2_TRIM - [11:6] */
97#define WM831X_DC1_TRIM_MASK 0x003F /* DC1_TRIM - [5:0] */
98#define WM831X_DC1_TRIM_SHIFT 0 /* DC1_TRIM - [5:0] */
99#define WM831X_DC1_TRIM_WIDTH 6 /* DC1_TRIM - [5:0] */
100
101/*
102 * R30730 (0x780A) - Factory OTP 2
103 */
104#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
105#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
106#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
107
108/*
109 * R30731 (0x780B) - Factory OTP 3
110 */
111#define WM831X_OSC_TRIM_MASK 0x0780 /* OSC_TRIM - [10:7] */
112#define WM831X_OSC_TRIM_SHIFT 7 /* OSC_TRIM - [10:7] */
113#define WM831X_OSC_TRIM_WIDTH 4 /* OSC_TRIM - [10:7] */
114#define WM831X_BG_TRIM_MASK 0x0078 /* BG_TRIM - [6:3] */
115#define WM831X_BG_TRIM_SHIFT 3 /* BG_TRIM - [6:3] */
116#define WM831X_BG_TRIM_WIDTH 4 /* BG_TRIM - [6:3] */
117#define WM831X_LPBG_TRIM_MASK 0x0007 /* LPBG_TRIM - [2:0] */
118#define WM831X_LPBG_TRIM_SHIFT 0 /* LPBG_TRIM - [2:0] */
119#define WM831X_LPBG_TRIM_WIDTH 3 /* LPBG_TRIM - [2:0] */
120
121/*
122 * R30732 (0x780C) - Factory OTP 4
123 */
124#define WM831X_CHILD_I2C_ADDR_MASK 0x00FE /* CHILD_I2C_ADDR - [7:1] */
125#define WM831X_CHILD_I2C_ADDR_SHIFT 1 /* CHILD_I2C_ADDR - [7:1] */
126#define WM831X_CHILD_I2C_ADDR_WIDTH 7 /* CHILD_I2C_ADDR - [7:1] */
127#define WM831X_CH_AW 0x0001 /* CH_AW */
128#define WM831X_CH_AW_MASK 0x0001 /* CH_AW */
129#define WM831X_CH_AW_SHIFT 0 /* CH_AW */
130#define WM831X_CH_AW_WIDTH 1 /* CH_AW */
131
132/*
133 * R30733 (0x780D) - Factory OTP 5
134 */
135#define WM831X_CHARGE_TRIM_MASK 0x003F /* CHARGE_TRIM - [5:0] */
136#define WM831X_CHARGE_TRIM_SHIFT 0 /* CHARGE_TRIM - [5:0] */
137#define WM831X_CHARGE_TRIM_WIDTH 6 /* CHARGE_TRIM - [5:0] */
138
139/*
140 * R30736 (0x7810) - Customer OTP ID
141 */
142#define WM831X_OTP_AUTO_PROG 0x8000 /* OTP_AUTO_PROG */
143#define WM831X_OTP_AUTO_PROG_MASK 0x8000 /* OTP_AUTO_PROG */
144#define WM831X_OTP_AUTO_PROG_SHIFT 15 /* OTP_AUTO_PROG */
145#define WM831X_OTP_AUTO_PROG_WIDTH 1 /* OTP_AUTO_PROG */
146#define WM831X_OTP_CUST_ID_MASK 0x7FFE /* OTP_CUST_ID - [14:1] */
147#define WM831X_OTP_CUST_ID_SHIFT 1 /* OTP_CUST_ID - [14:1] */
148#define WM831X_OTP_CUST_ID_WIDTH 14 /* OTP_CUST_ID - [14:1] */
149#define WM831X_OTP_CUST_FINAL 0x0001 /* OTP_CUST_FINAL */
150#define WM831X_OTP_CUST_FINAL_MASK 0x0001 /* OTP_CUST_FINAL */
151#define WM831X_OTP_CUST_FINAL_SHIFT 0 /* OTP_CUST_FINAL */
152#define WM831X_OTP_CUST_FINAL_WIDTH 1 /* OTP_CUST_FINAL */
153
154/*
155 * R30759 (0x7827) - DBE CHECK DATA
156 */
157#define WM831X_DBE_VALID_DATA_MASK 0xFFFF /* DBE_VALID_DATA - [15:0] */
158#define WM831X_DBE_VALID_DATA_SHIFT 0 /* DBE_VALID_DATA - [15:0] */
159#define WM831X_DBE_VALID_DATA_WIDTH 16 /* DBE_VALID_DATA - [15:0] */
160
161
162#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
new file mode 100644
index 000000000000..90d820260aad
--- /dev/null
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -0,0 +1,113 @@
1/*
2 * include/linux/mfd/wm831x/pdata.h -- Platform data for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_PDATA_H__
16#define __MFD_WM831X_PDATA_H__
17
18struct wm831x;
19struct regulator_init_data;
20
21struct wm831x_backlight_pdata {
22 int isink; /** ISINK to use, 1 or 2 */
23 int max_uA; /** Maximum current to allow */
24};
25
26struct wm831x_backup_pdata {
27 int charger_enable;
28 int no_constant_voltage; /** Disable constant voltage charging */
29 int vlim; /** Voltage limit in milivolts */
30 int ilim; /** Current limit in microamps */
31};
32
33struct wm831x_battery_pdata {
34 int enable; /** Enable charging */
35 int fast_enable; /** Enable fast charging */
36 int off_mask; /** Mask OFF while charging */
37 int trickle_ilim; /** Trickle charge current limit, in mA */
38 int vsel; /** Target voltage, in mV */
39 int eoc_iterm; /** End of trickle charge current, in mA */
40 int fast_ilim; /** Fast charge current limit, in mA */
41 int timeout; /** Charge cycle timeout, in minutes */
42};
43
44/* Sources for status LED configuration. Values are register values
45 * plus 1 to allow for a zero default for preserve.
46 */
47enum wm831x_status_src {
48 WM831X_STATUS_PRESERVE = 0, /* Keep the current hardware setting */
49 WM831X_STATUS_OTP = 1,
50 WM831X_STATUS_POWER = 2,
51 WM831X_STATUS_CHARGER = 3,
52 WM831X_STATUS_MANUAL = 4,
53};
54
55struct wm831x_status_pdata {
56 enum wm831x_status_src default_src;
57 const char *name;
58 const char *default_trigger;
59};
60
61struct wm831x_touch_pdata {
62 int fivewire; /** 1 for five wire mode, 0 for 4 wire */
63 int isel; /** Current for pen down (uA) */
64 int rpu; /** Pen down sensitivity resistor divider */
65 int pressure; /** Report pressure (boolean) */
66 int data_irq; /** Touch data ready IRQ */
67};
68
69enum wm831x_watchdog_action {
70 WM831X_WDOG_NONE = 0,
71 WM831X_WDOG_INTERRUPT = 1,
72 WM831X_WDOG_RESET = 2,
73 WM831X_WDOG_WAKE = 3,
74};
75
76struct wm831x_watchdog_pdata {
77 enum wm831x_watchdog_action primary, secondary;
78 int update_gpio;
79 unsigned int software:1;
80};
81
82#define WM831X_MAX_STATUS 2
83#define WM831X_MAX_DCDC 4
84#define WM831X_MAX_EPE 2
85#define WM831X_MAX_LDO 11
86#define WM831X_MAX_ISINK 2
87
88struct wm831x_pdata {
89 /** Called before subdevices are set up */
90 int (*pre_init)(struct wm831x *wm831x);
91 /** Called after subdevices are set up */
92 int (*post_init)(struct wm831x *wm831x);
93
94 int gpio_base;
95 struct wm831x_backlight_pdata *backlight;
96 struct wm831x_backup_pdata *backup;
97 struct wm831x_battery_pdata *battery;
98 struct wm831x_touch_pdata *touch;
99 struct wm831x_watchdog_pdata *watchdog;
100
101 /** LED1 = 0 and so on */
102 struct wm831x_status_pdata *status[WM831X_MAX_STATUS];
103 /** DCDC1 = 0 and so on */
104 struct regulator_init_data *dcdc[WM831X_MAX_DCDC];
105 /** EPE1 = 0 and so on */
106 struct regulator_init_data *epe[WM831X_MAX_EPE];
107 /** LDO1 = 0 and so on */
108 struct regulator_init_data *ldo[WM831X_MAX_LDO];
109 /** ISINK1 = 0 and so on*/
110 struct regulator_init_data *isink[WM831X_MAX_ISINK];
111};
112
113#endif
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
new file mode 100644
index 000000000000..f95466343fb2
--- /dev/null
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -0,0 +1,1218 @@
1/*
2 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_REGULATOR_H__
16#define __MFD_WM831X_REGULATOR_H__
17
18/*
19 * R16462 (0x404E) - Current Sink 1
20 */
21#define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
22#define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
23#define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
24#define WM831X_CS1_ENA_WIDTH 1 /* CS1_ENA */
25#define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
26#define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
27#define WM831X_CS1_DRIVE_SHIFT 14 /* CS1_DRIVE */
28#define WM831X_CS1_DRIVE_WIDTH 1 /* CS1_DRIVE */
29#define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
30#define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
31#define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */
32#define WM831X_CS1_SLPENA_WIDTH 1 /* CS1_SLPENA */
33#define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
34#define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */
35#define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */
36#define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
37#define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */
38#define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */
39#define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
40#define WM831X_CS1_ISEL_SHIFT 0 /* CS1_ISEL - [5:0] */
41#define WM831X_CS1_ISEL_WIDTH 6 /* CS1_ISEL - [5:0] */
42
43/*
44 * R16463 (0x404F) - Current Sink 2
45 */
46#define WM831X_CS2_ENA 0x8000 /* CS2_ENA */
47#define WM831X_CS2_ENA_MASK 0x8000 /* CS2_ENA */
48#define WM831X_CS2_ENA_SHIFT 15 /* CS2_ENA */
49#define WM831X_CS2_ENA_WIDTH 1 /* CS2_ENA */
50#define WM831X_CS2_DRIVE 0x4000 /* CS2_DRIVE */
51#define WM831X_CS2_DRIVE_MASK 0x4000 /* CS2_DRIVE */
52#define WM831X_CS2_DRIVE_SHIFT 14 /* CS2_DRIVE */
53#define WM831X_CS2_DRIVE_WIDTH 1 /* CS2_DRIVE */
54#define WM831X_CS2_SLPENA 0x1000 /* CS2_SLPENA */
55#define WM831X_CS2_SLPENA_MASK 0x1000 /* CS2_SLPENA */
56#define WM831X_CS2_SLPENA_SHIFT 12 /* CS2_SLPENA */
57#define WM831X_CS2_SLPENA_WIDTH 1 /* CS2_SLPENA */
58#define WM831X_CS2_OFF_RAMP_MASK 0x0C00 /* CS2_OFF_RAMP - [11:10] */
59#define WM831X_CS2_OFF_RAMP_SHIFT 10 /* CS2_OFF_RAMP - [11:10] */
60#define WM831X_CS2_OFF_RAMP_WIDTH 2 /* CS2_OFF_RAMP - [11:10] */
61#define WM831X_CS2_ON_RAMP_MASK 0x0300 /* CS2_ON_RAMP - [9:8] */
62#define WM831X_CS2_ON_RAMP_SHIFT 8 /* CS2_ON_RAMP - [9:8] */
63#define WM831X_CS2_ON_RAMP_WIDTH 2 /* CS2_ON_RAMP - [9:8] */
64#define WM831X_CS2_ISEL_MASK 0x003F /* CS2_ISEL - [5:0] */
65#define WM831X_CS2_ISEL_SHIFT 0 /* CS2_ISEL - [5:0] */
66#define WM831X_CS2_ISEL_WIDTH 6 /* CS2_ISEL - [5:0] */
67
68/*
69 * R16464 (0x4050) - DCDC Enable
70 */
71#define WM831X_EPE2_ENA 0x0080 /* EPE2_ENA */
72#define WM831X_EPE2_ENA_MASK 0x0080 /* EPE2_ENA */
73#define WM831X_EPE2_ENA_SHIFT 7 /* EPE2_ENA */
74#define WM831X_EPE2_ENA_WIDTH 1 /* EPE2_ENA */
75#define WM831X_EPE1_ENA 0x0040 /* EPE1_ENA */
76#define WM831X_EPE1_ENA_MASK 0x0040 /* EPE1_ENA */
77#define WM831X_EPE1_ENA_SHIFT 6 /* EPE1_ENA */
78#define WM831X_EPE1_ENA_WIDTH 1 /* EPE1_ENA */
79#define WM831X_DC4_ENA 0x0008 /* DC4_ENA */
80#define WM831X_DC4_ENA_MASK 0x0008 /* DC4_ENA */
81#define WM831X_DC4_ENA_SHIFT 3 /* DC4_ENA */
82#define WM831X_DC4_ENA_WIDTH 1 /* DC4_ENA */
83#define WM831X_DC3_ENA 0x0004 /* DC3_ENA */
84#define WM831X_DC3_ENA_MASK 0x0004 /* DC3_ENA */
85#define WM831X_DC3_ENA_SHIFT 2 /* DC3_ENA */
86#define WM831X_DC3_ENA_WIDTH 1 /* DC3_ENA */
87#define WM831X_DC2_ENA 0x0002 /* DC2_ENA */
88#define WM831X_DC2_ENA_MASK 0x0002 /* DC2_ENA */
89#define WM831X_DC2_ENA_SHIFT 1 /* DC2_ENA */
90#define WM831X_DC2_ENA_WIDTH 1 /* DC2_ENA */
91#define WM831X_DC1_ENA 0x0001 /* DC1_ENA */
92#define WM831X_DC1_ENA_MASK 0x0001 /* DC1_ENA */
93#define WM831X_DC1_ENA_SHIFT 0 /* DC1_ENA */
94#define WM831X_DC1_ENA_WIDTH 1 /* DC1_ENA */
95
96/*
97 * R16465 (0x4051) - LDO Enable
98 */
99#define WM831X_LDO11_ENA 0x0400 /* LDO11_ENA */
100#define WM831X_LDO11_ENA_MASK 0x0400 /* LDO11_ENA */
101#define WM831X_LDO11_ENA_SHIFT 10 /* LDO11_ENA */
102#define WM831X_LDO11_ENA_WIDTH 1 /* LDO11_ENA */
103#define WM831X_LDO10_ENA 0x0200 /* LDO10_ENA */
104#define WM831X_LDO10_ENA_MASK 0x0200 /* LDO10_ENA */
105#define WM831X_LDO10_ENA_SHIFT 9 /* LDO10_ENA */
106#define WM831X_LDO10_ENA_WIDTH 1 /* LDO10_ENA */
107#define WM831X_LDO9_ENA 0x0100 /* LDO9_ENA */
108#define WM831X_LDO9_ENA_MASK 0x0100 /* LDO9_ENA */
109#define WM831X_LDO9_ENA_SHIFT 8 /* LDO9_ENA */
110#define WM831X_LDO9_ENA_WIDTH 1 /* LDO9_ENA */
111#define WM831X_LDO8_ENA 0x0080 /* LDO8_ENA */
112#define WM831X_LDO8_ENA_MASK 0x0080 /* LDO8_ENA */
113#define WM831X_LDO8_ENA_SHIFT 7 /* LDO8_ENA */
114#define WM831X_LDO8_ENA_WIDTH 1 /* LDO8_ENA */
115#define WM831X_LDO7_ENA 0x0040 /* LDO7_ENA */
116#define WM831X_LDO7_ENA_MASK 0x0040 /* LDO7_ENA */
117#define WM831X_LDO7_ENA_SHIFT 6 /* LDO7_ENA */
118#define WM831X_LDO7_ENA_WIDTH 1 /* LDO7_ENA */
119#define WM831X_LDO6_ENA 0x0020 /* LDO6_ENA */
120#define WM831X_LDO6_ENA_MASK 0x0020 /* LDO6_ENA */
121#define WM831X_LDO6_ENA_SHIFT 5 /* LDO6_ENA */
122#define WM831X_LDO6_ENA_WIDTH 1 /* LDO6_ENA */
123#define WM831X_LDO5_ENA 0x0010 /* LDO5_ENA */
124#define WM831X_LDO5_ENA_MASK 0x0010 /* LDO5_ENA */
125#define WM831X_LDO5_ENA_SHIFT 4 /* LDO5_ENA */
126#define WM831X_LDO5_ENA_WIDTH 1 /* LDO5_ENA */
127#define WM831X_LDO4_ENA 0x0008 /* LDO4_ENA */
128#define WM831X_LDO4_ENA_MASK 0x0008 /* LDO4_ENA */
129#define WM831X_LDO4_ENA_SHIFT 3 /* LDO4_ENA */
130#define WM831X_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
131#define WM831X_LDO3_ENA 0x0004 /* LDO3_ENA */
132#define WM831X_LDO3_ENA_MASK 0x0004 /* LDO3_ENA */
133#define WM831X_LDO3_ENA_SHIFT 2 /* LDO3_ENA */
134#define WM831X_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
135#define WM831X_LDO2_ENA 0x0002 /* LDO2_ENA */
136#define WM831X_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
137#define WM831X_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
138#define WM831X_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
139#define WM831X_LDO1_ENA 0x0001 /* LDO1_ENA */
140#define WM831X_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
141#define WM831X_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
142#define WM831X_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
143
144/*
145 * R16466 (0x4052) - DCDC Status
146 */
147#define WM831X_EPE2_STS 0x0080 /* EPE2_STS */
148#define WM831X_EPE2_STS_MASK 0x0080 /* EPE2_STS */
149#define WM831X_EPE2_STS_SHIFT 7 /* EPE2_STS */
150#define WM831X_EPE2_STS_WIDTH 1 /* EPE2_STS */
151#define WM831X_EPE1_STS 0x0040 /* EPE1_STS */
152#define WM831X_EPE1_STS_MASK 0x0040 /* EPE1_STS */
153#define WM831X_EPE1_STS_SHIFT 6 /* EPE1_STS */
154#define WM831X_EPE1_STS_WIDTH 1 /* EPE1_STS */
155#define WM831X_DC4_STS 0x0008 /* DC4_STS */
156#define WM831X_DC4_STS_MASK 0x0008 /* DC4_STS */
157#define WM831X_DC4_STS_SHIFT 3 /* DC4_STS */
158#define WM831X_DC4_STS_WIDTH 1 /* DC4_STS */
159#define WM831X_DC3_STS 0x0004 /* DC3_STS */
160#define WM831X_DC3_STS_MASK 0x0004 /* DC3_STS */
161#define WM831X_DC3_STS_SHIFT 2 /* DC3_STS */
162#define WM831X_DC3_STS_WIDTH 1 /* DC3_STS */
163#define WM831X_DC2_STS 0x0002 /* DC2_STS */
164#define WM831X_DC2_STS_MASK 0x0002 /* DC2_STS */
165#define WM831X_DC2_STS_SHIFT 1 /* DC2_STS */
166#define WM831X_DC2_STS_WIDTH 1 /* DC2_STS */
167#define WM831X_DC1_STS 0x0001 /* DC1_STS */
168#define WM831X_DC1_STS_MASK 0x0001 /* DC1_STS */
169#define WM831X_DC1_STS_SHIFT 0 /* DC1_STS */
170#define WM831X_DC1_STS_WIDTH 1 /* DC1_STS */
171
172/*
173 * R16467 (0x4053) - LDO Status
174 */
175#define WM831X_LDO11_STS 0x0400 /* LDO11_STS */
176#define WM831X_LDO11_STS_MASK 0x0400 /* LDO11_STS */
177#define WM831X_LDO11_STS_SHIFT 10 /* LDO11_STS */
178#define WM831X_LDO11_STS_WIDTH 1 /* LDO11_STS */
179#define WM831X_LDO10_STS 0x0200 /* LDO10_STS */
180#define WM831X_LDO10_STS_MASK 0x0200 /* LDO10_STS */
181#define WM831X_LDO10_STS_SHIFT 9 /* LDO10_STS */
182#define WM831X_LDO10_STS_WIDTH 1 /* LDO10_STS */
183#define WM831X_LDO9_STS 0x0100 /* LDO9_STS */
184#define WM831X_LDO9_STS_MASK 0x0100 /* LDO9_STS */
185#define WM831X_LDO9_STS_SHIFT 8 /* LDO9_STS */
186#define WM831X_LDO9_STS_WIDTH 1 /* LDO9_STS */
187#define WM831X_LDO8_STS 0x0080 /* LDO8_STS */
188#define WM831X_LDO8_STS_MASK 0x0080 /* LDO8_STS */
189#define WM831X_LDO8_STS_SHIFT 7 /* LDO8_STS */
190#define WM831X_LDO8_STS_WIDTH 1 /* LDO8_STS */
191#define WM831X_LDO7_STS 0x0040 /* LDO7_STS */
192#define WM831X_LDO7_STS_MASK 0x0040 /* LDO7_STS */
193#define WM831X_LDO7_STS_SHIFT 6 /* LDO7_STS */
194#define WM831X_LDO7_STS_WIDTH 1 /* LDO7_STS */
195#define WM831X_LDO6_STS 0x0020 /* LDO6_STS */
196#define WM831X_LDO6_STS_MASK 0x0020 /* LDO6_STS */
197#define WM831X_LDO6_STS_SHIFT 5 /* LDO6_STS */
198#define WM831X_LDO6_STS_WIDTH 1 /* LDO6_STS */
199#define WM831X_LDO5_STS 0x0010 /* LDO5_STS */
200#define WM831X_LDO5_STS_MASK 0x0010 /* LDO5_STS */
201#define WM831X_LDO5_STS_SHIFT 4 /* LDO5_STS */
202#define WM831X_LDO5_STS_WIDTH 1 /* LDO5_STS */
203#define WM831X_LDO4_STS 0x0008 /* LDO4_STS */
204#define WM831X_LDO4_STS_MASK 0x0008 /* LDO4_STS */
205#define WM831X_LDO4_STS_SHIFT 3 /* LDO4_STS */
206#define WM831X_LDO4_STS_WIDTH 1 /* LDO4_STS */
207#define WM831X_LDO3_STS 0x0004 /* LDO3_STS */
208#define WM831X_LDO3_STS_MASK 0x0004 /* LDO3_STS */
209#define WM831X_LDO3_STS_SHIFT 2 /* LDO3_STS */
210#define WM831X_LDO3_STS_WIDTH 1 /* LDO3_STS */
211#define WM831X_LDO2_STS 0x0002 /* LDO2_STS */
212#define WM831X_LDO2_STS_MASK 0x0002 /* LDO2_STS */
213#define WM831X_LDO2_STS_SHIFT 1 /* LDO2_STS */
214#define WM831X_LDO2_STS_WIDTH 1 /* LDO2_STS */
215#define WM831X_LDO1_STS 0x0001 /* LDO1_STS */
216#define WM831X_LDO1_STS_MASK 0x0001 /* LDO1_STS */
217#define WM831X_LDO1_STS_SHIFT 0 /* LDO1_STS */
218#define WM831X_LDO1_STS_WIDTH 1 /* LDO1_STS */
219
220/*
221 * R16468 (0x4054) - DCDC UV Status
222 */
223#define WM831X_DC2_OV_STS 0x2000 /* DC2_OV_STS */
224#define WM831X_DC2_OV_STS_MASK 0x2000 /* DC2_OV_STS */
225#define WM831X_DC2_OV_STS_SHIFT 13 /* DC2_OV_STS */
226#define WM831X_DC2_OV_STS_WIDTH 1 /* DC2_OV_STS */
227#define WM831X_DC1_OV_STS 0x1000 /* DC1_OV_STS */
228#define WM831X_DC1_OV_STS_MASK 0x1000 /* DC1_OV_STS */
229#define WM831X_DC1_OV_STS_SHIFT 12 /* DC1_OV_STS */
230#define WM831X_DC1_OV_STS_WIDTH 1 /* DC1_OV_STS */
231#define WM831X_DC2_HC_STS 0x0200 /* DC2_HC_STS */
232#define WM831X_DC2_HC_STS_MASK 0x0200 /* DC2_HC_STS */
233#define WM831X_DC2_HC_STS_SHIFT 9 /* DC2_HC_STS */
234#define WM831X_DC2_HC_STS_WIDTH 1 /* DC2_HC_STS */
235#define WM831X_DC1_HC_STS 0x0100 /* DC1_HC_STS */
236#define WM831X_DC1_HC_STS_MASK 0x0100 /* DC1_HC_STS */
237#define WM831X_DC1_HC_STS_SHIFT 8 /* DC1_HC_STS */
238#define WM831X_DC1_HC_STS_WIDTH 1 /* DC1_HC_STS */
239#define WM831X_DC4_UV_STS 0x0008 /* DC4_UV_STS */
240#define WM831X_DC4_UV_STS_MASK 0x0008 /* DC4_UV_STS */
241#define WM831X_DC4_UV_STS_SHIFT 3 /* DC4_UV_STS */
242#define WM831X_DC4_UV_STS_WIDTH 1 /* DC4_UV_STS */
243#define WM831X_DC3_UV_STS 0x0004 /* DC3_UV_STS */
244#define WM831X_DC3_UV_STS_MASK 0x0004 /* DC3_UV_STS */
245#define WM831X_DC3_UV_STS_SHIFT 2 /* DC3_UV_STS */
246#define WM831X_DC3_UV_STS_WIDTH 1 /* DC3_UV_STS */
247#define WM831X_DC2_UV_STS 0x0002 /* DC2_UV_STS */
248#define WM831X_DC2_UV_STS_MASK 0x0002 /* DC2_UV_STS */
249#define WM831X_DC2_UV_STS_SHIFT 1 /* DC2_UV_STS */
250#define WM831X_DC2_UV_STS_WIDTH 1 /* DC2_UV_STS */
251#define WM831X_DC1_UV_STS 0x0001 /* DC1_UV_STS */
252#define WM831X_DC1_UV_STS_MASK 0x0001 /* DC1_UV_STS */
253#define WM831X_DC1_UV_STS_SHIFT 0 /* DC1_UV_STS */
254#define WM831X_DC1_UV_STS_WIDTH 1 /* DC1_UV_STS */
255
256/*
257 * R16469 (0x4055) - LDO UV Status
258 */
259#define WM831X_INTLDO_UV_STS 0x8000 /* INTLDO_UV_STS */
260#define WM831X_INTLDO_UV_STS_MASK 0x8000 /* INTLDO_UV_STS */
261#define WM831X_INTLDO_UV_STS_SHIFT 15 /* INTLDO_UV_STS */
262#define WM831X_INTLDO_UV_STS_WIDTH 1 /* INTLDO_UV_STS */
263#define WM831X_LDO10_UV_STS 0x0200 /* LDO10_UV_STS */
264#define WM831X_LDO10_UV_STS_MASK 0x0200 /* LDO10_UV_STS */
265#define WM831X_LDO10_UV_STS_SHIFT 9 /* LDO10_UV_STS */
266#define WM831X_LDO10_UV_STS_WIDTH 1 /* LDO10_UV_STS */
267#define WM831X_LDO9_UV_STS 0x0100 /* LDO9_UV_STS */
268#define WM831X_LDO9_UV_STS_MASK 0x0100 /* LDO9_UV_STS */
269#define WM831X_LDO9_UV_STS_SHIFT 8 /* LDO9_UV_STS */
270#define WM831X_LDO9_UV_STS_WIDTH 1 /* LDO9_UV_STS */
271#define WM831X_LDO8_UV_STS 0x0080 /* LDO8_UV_STS */
272#define WM831X_LDO8_UV_STS_MASK 0x0080 /* LDO8_UV_STS */
273#define WM831X_LDO8_UV_STS_SHIFT 7 /* LDO8_UV_STS */
274#define WM831X_LDO8_UV_STS_WIDTH 1 /* LDO8_UV_STS */
275#define WM831X_LDO7_UV_STS 0x0040 /* LDO7_UV_STS */
276#define WM831X_LDO7_UV_STS_MASK 0x0040 /* LDO7_UV_STS */
277#define WM831X_LDO7_UV_STS_SHIFT 6 /* LDO7_UV_STS */
278#define WM831X_LDO7_UV_STS_WIDTH 1 /* LDO7_UV_STS */
279#define WM831X_LDO6_UV_STS 0x0020 /* LDO6_UV_STS */
280#define WM831X_LDO6_UV_STS_MASK 0x0020 /* LDO6_UV_STS */
281#define WM831X_LDO6_UV_STS_SHIFT 5 /* LDO6_UV_STS */
282#define WM831X_LDO6_UV_STS_WIDTH 1 /* LDO6_UV_STS */
283#define WM831X_LDO5_UV_STS 0x0010 /* LDO5_UV_STS */
284#define WM831X_LDO5_UV_STS_MASK 0x0010 /* LDO5_UV_STS */
285#define WM831X_LDO5_UV_STS_SHIFT 4 /* LDO5_UV_STS */
286#define WM831X_LDO5_UV_STS_WIDTH 1 /* LDO5_UV_STS */
287#define WM831X_LDO4_UV_STS 0x0008 /* LDO4_UV_STS */
288#define WM831X_LDO4_UV_STS_MASK 0x0008 /* LDO4_UV_STS */
289#define WM831X_LDO4_UV_STS_SHIFT 3 /* LDO4_UV_STS */
290#define WM831X_LDO4_UV_STS_WIDTH 1 /* LDO4_UV_STS */
291#define WM831X_LDO3_UV_STS 0x0004 /* LDO3_UV_STS */
292#define WM831X_LDO3_UV_STS_MASK 0x0004 /* LDO3_UV_STS */
293#define WM831X_LDO3_UV_STS_SHIFT 2 /* LDO3_UV_STS */
294#define WM831X_LDO3_UV_STS_WIDTH 1 /* LDO3_UV_STS */
295#define WM831X_LDO2_UV_STS 0x0002 /* LDO2_UV_STS */
296#define WM831X_LDO2_UV_STS_MASK 0x0002 /* LDO2_UV_STS */
297#define WM831X_LDO2_UV_STS_SHIFT 1 /* LDO2_UV_STS */
298#define WM831X_LDO2_UV_STS_WIDTH 1 /* LDO2_UV_STS */
299#define WM831X_LDO1_UV_STS 0x0001 /* LDO1_UV_STS */
300#define WM831X_LDO1_UV_STS_MASK 0x0001 /* LDO1_UV_STS */
301#define WM831X_LDO1_UV_STS_SHIFT 0 /* LDO1_UV_STS */
302#define WM831X_LDO1_UV_STS_WIDTH 1 /* LDO1_UV_STS */
303
304/*
305 * R16470 (0x4056) - DC1 Control 1
306 */
307#define WM831X_DC1_RATE_MASK 0xC000 /* DC1_RATE - [15:14] */
308#define WM831X_DC1_RATE_SHIFT 14 /* DC1_RATE - [15:14] */
309#define WM831X_DC1_RATE_WIDTH 2 /* DC1_RATE - [15:14] */
310#define WM831X_DC1_PHASE 0x1000 /* DC1_PHASE */
311#define WM831X_DC1_PHASE_MASK 0x1000 /* DC1_PHASE */
312#define WM831X_DC1_PHASE_SHIFT 12 /* DC1_PHASE */
313#define WM831X_DC1_PHASE_WIDTH 1 /* DC1_PHASE */
314#define WM831X_DC1_FREQ_MASK 0x0300 /* DC1_FREQ - [9:8] */
315#define WM831X_DC1_FREQ_SHIFT 8 /* DC1_FREQ - [9:8] */
316#define WM831X_DC1_FREQ_WIDTH 2 /* DC1_FREQ - [9:8] */
317#define WM831X_DC1_FLT 0x0080 /* DC1_FLT */
318#define WM831X_DC1_FLT_MASK 0x0080 /* DC1_FLT */
319#define WM831X_DC1_FLT_SHIFT 7 /* DC1_FLT */
320#define WM831X_DC1_FLT_WIDTH 1 /* DC1_FLT */
321#define WM831X_DC1_SOFT_START_MASK 0x0030 /* DC1_SOFT_START - [5:4] */
322#define WM831X_DC1_SOFT_START_SHIFT 4 /* DC1_SOFT_START - [5:4] */
323#define WM831X_DC1_SOFT_START_WIDTH 2 /* DC1_SOFT_START - [5:4] */
324#define WM831X_DC1_CAP_MASK 0x0003 /* DC1_CAP - [1:0] */
325#define WM831X_DC1_CAP_SHIFT 0 /* DC1_CAP - [1:0] */
326#define WM831X_DC1_CAP_WIDTH 2 /* DC1_CAP - [1:0] */
327
328/*
329 * R16471 (0x4057) - DC1 Control 2
330 */
331#define WM831X_DC1_ERR_ACT_MASK 0xC000 /* DC1_ERR_ACT - [15:14] */
332#define WM831X_DC1_ERR_ACT_SHIFT 14 /* DC1_ERR_ACT - [15:14] */
333#define WM831X_DC1_ERR_ACT_WIDTH 2 /* DC1_ERR_ACT - [15:14] */
334#define WM831X_DC1_HWC_SRC_MASK 0x1800 /* DC1_HWC_SRC - [12:11] */
335#define WM831X_DC1_HWC_SRC_SHIFT 11 /* DC1_HWC_SRC - [12:11] */
336#define WM831X_DC1_HWC_SRC_WIDTH 2 /* DC1_HWC_SRC - [12:11] */
337#define WM831X_DC1_HWC_VSEL 0x0400 /* DC1_HWC_VSEL */
338#define WM831X_DC1_HWC_VSEL_MASK 0x0400 /* DC1_HWC_VSEL */
339#define WM831X_DC1_HWC_VSEL_SHIFT 10 /* DC1_HWC_VSEL */
340#define WM831X_DC1_HWC_VSEL_WIDTH 1 /* DC1_HWC_VSEL */
341#define WM831X_DC1_HWC_MODE_MASK 0x0300 /* DC1_HWC_MODE - [9:8] */
342#define WM831X_DC1_HWC_MODE_SHIFT 8 /* DC1_HWC_MODE - [9:8] */
343#define WM831X_DC1_HWC_MODE_WIDTH 2 /* DC1_HWC_MODE - [9:8] */
344#define WM831X_DC1_HC_THR_MASK 0x0070 /* DC1_HC_THR - [6:4] */
345#define WM831X_DC1_HC_THR_SHIFT 4 /* DC1_HC_THR - [6:4] */
346#define WM831X_DC1_HC_THR_WIDTH 3 /* DC1_HC_THR - [6:4] */
347#define WM831X_DC1_HC_IND_ENA 0x0001 /* DC1_HC_IND_ENA */
348#define WM831X_DC1_HC_IND_ENA_MASK 0x0001 /* DC1_HC_IND_ENA */
349#define WM831X_DC1_HC_IND_ENA_SHIFT 0 /* DC1_HC_IND_ENA */
350#define WM831X_DC1_HC_IND_ENA_WIDTH 1 /* DC1_HC_IND_ENA */
351
352/*
353 * R16472 (0x4058) - DC1 ON Config
354 */
355#define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */
356#define WM831X_DC1_ON_SLOT_SHIFT 13 /* DC1_ON_SLOT - [15:13] */
357#define WM831X_DC1_ON_SLOT_WIDTH 3 /* DC1_ON_SLOT - [15:13] */
358#define WM831X_DC1_ON_MODE_MASK 0x0300 /* DC1_ON_MODE - [9:8] */
359#define WM831X_DC1_ON_MODE_SHIFT 8 /* DC1_ON_MODE - [9:8] */
360#define WM831X_DC1_ON_MODE_WIDTH 2 /* DC1_ON_MODE - [9:8] */
361#define WM831X_DC1_ON_VSEL_MASK 0x007F /* DC1_ON_VSEL - [6:0] */
362#define WM831X_DC1_ON_VSEL_SHIFT 0 /* DC1_ON_VSEL - [6:0] */
363#define WM831X_DC1_ON_VSEL_WIDTH 7 /* DC1_ON_VSEL - [6:0] */
364
365/*
366 * R16473 (0x4059) - DC1 SLEEP Control
367 */
368#define WM831X_DC1_SLP_SLOT_MASK 0xE000 /* DC1_SLP_SLOT - [15:13] */
369#define WM831X_DC1_SLP_SLOT_SHIFT 13 /* DC1_SLP_SLOT - [15:13] */
370#define WM831X_DC1_SLP_SLOT_WIDTH 3 /* DC1_SLP_SLOT - [15:13] */
371#define WM831X_DC1_SLP_MODE_MASK 0x0300 /* DC1_SLP_MODE - [9:8] */
372#define WM831X_DC1_SLP_MODE_SHIFT 8 /* DC1_SLP_MODE - [9:8] */
373#define WM831X_DC1_SLP_MODE_WIDTH 2 /* DC1_SLP_MODE - [9:8] */
374#define WM831X_DC1_SLP_VSEL_MASK 0x007F /* DC1_SLP_VSEL - [6:0] */
375#define WM831X_DC1_SLP_VSEL_SHIFT 0 /* DC1_SLP_VSEL - [6:0] */
376#define WM831X_DC1_SLP_VSEL_WIDTH 7 /* DC1_SLP_VSEL - [6:0] */
377
378/*
379 * R16474 (0x405A) - DC1 DVS Control
380 */
381#define WM831X_DC1_DVS_SRC_MASK 0x1800 /* DC1_DVS_SRC - [12:11] */
382#define WM831X_DC1_DVS_SRC_SHIFT 11 /* DC1_DVS_SRC - [12:11] */
383#define WM831X_DC1_DVS_SRC_WIDTH 2 /* DC1_DVS_SRC - [12:11] */
384#define WM831X_DC1_DVS_VSEL_MASK 0x007F /* DC1_DVS_VSEL - [6:0] */
385#define WM831X_DC1_DVS_VSEL_SHIFT 0 /* DC1_DVS_VSEL - [6:0] */
386#define WM831X_DC1_DVS_VSEL_WIDTH 7 /* DC1_DVS_VSEL - [6:0] */
387
388/*
389 * R16475 (0x405B) - DC2 Control 1
390 */
391#define WM831X_DC2_RATE_MASK 0xC000 /* DC2_RATE - [15:14] */
392#define WM831X_DC2_RATE_SHIFT 14 /* DC2_RATE - [15:14] */
393#define WM831X_DC2_RATE_WIDTH 2 /* DC2_RATE - [15:14] */
394#define WM831X_DC2_PHASE 0x1000 /* DC2_PHASE */
395#define WM831X_DC2_PHASE_MASK 0x1000 /* DC2_PHASE */
396#define WM831X_DC2_PHASE_SHIFT 12 /* DC2_PHASE */
397#define WM831X_DC2_PHASE_WIDTH 1 /* DC2_PHASE */
398#define WM831X_DC2_FREQ_MASK 0x0300 /* DC2_FREQ - [9:8] */
399#define WM831X_DC2_FREQ_SHIFT 8 /* DC2_FREQ - [9:8] */
400#define WM831X_DC2_FREQ_WIDTH 2 /* DC2_FREQ - [9:8] */
401#define WM831X_DC2_FLT 0x0080 /* DC2_FLT */
402#define WM831X_DC2_FLT_MASK 0x0080 /* DC2_FLT */
403#define WM831X_DC2_FLT_SHIFT 7 /* DC2_FLT */
404#define WM831X_DC2_FLT_WIDTH 1 /* DC2_FLT */
405#define WM831X_DC2_SOFT_START_MASK 0x0030 /* DC2_SOFT_START - [5:4] */
406#define WM831X_DC2_SOFT_START_SHIFT 4 /* DC2_SOFT_START - [5:4] */
407#define WM831X_DC2_SOFT_START_WIDTH 2 /* DC2_SOFT_START - [5:4] */
408#define WM831X_DC2_CAP_MASK 0x0003 /* DC2_CAP - [1:0] */
409#define WM831X_DC2_CAP_SHIFT 0 /* DC2_CAP - [1:0] */
410#define WM831X_DC2_CAP_WIDTH 2 /* DC2_CAP - [1:0] */
411
412/*
413 * R16476 (0x405C) - DC2 Control 2
414 */
415#define WM831X_DC2_ERR_ACT_MASK 0xC000 /* DC2_ERR_ACT - [15:14] */
416#define WM831X_DC2_ERR_ACT_SHIFT 14 /* DC2_ERR_ACT - [15:14] */
417#define WM831X_DC2_ERR_ACT_WIDTH 2 /* DC2_ERR_ACT - [15:14] */
418#define WM831X_DC2_HWC_SRC_MASK 0x1800 /* DC2_HWC_SRC - [12:11] */
419#define WM831X_DC2_HWC_SRC_SHIFT 11 /* DC2_HWC_SRC - [12:11] */
420#define WM831X_DC2_HWC_SRC_WIDTH 2 /* DC2_HWC_SRC - [12:11] */
421#define WM831X_DC2_HWC_VSEL 0x0400 /* DC2_HWC_VSEL */
422#define WM831X_DC2_HWC_VSEL_MASK 0x0400 /* DC2_HWC_VSEL */
423#define WM831X_DC2_HWC_VSEL_SHIFT 10 /* DC2_HWC_VSEL */
424#define WM831X_DC2_HWC_VSEL_WIDTH 1 /* DC2_HWC_VSEL */
425#define WM831X_DC2_HWC_MODE_MASK 0x0300 /* DC2_HWC_MODE - [9:8] */
426#define WM831X_DC2_HWC_MODE_SHIFT 8 /* DC2_HWC_MODE - [9:8] */
427#define WM831X_DC2_HWC_MODE_WIDTH 2 /* DC2_HWC_MODE - [9:8] */
428#define WM831X_DC2_HC_THR_MASK 0x0070 /* DC2_HC_THR - [6:4] */
429#define WM831X_DC2_HC_THR_SHIFT 4 /* DC2_HC_THR - [6:4] */
430#define WM831X_DC2_HC_THR_WIDTH 3 /* DC2_HC_THR - [6:4] */
431#define WM831X_DC2_HC_IND_ENA 0x0001 /* DC2_HC_IND_ENA */
432#define WM831X_DC2_HC_IND_ENA_MASK 0x0001 /* DC2_HC_IND_ENA */
433#define WM831X_DC2_HC_IND_ENA_SHIFT 0 /* DC2_HC_IND_ENA */
434#define WM831X_DC2_HC_IND_ENA_WIDTH 1 /* DC2_HC_IND_ENA */
435
436/*
437 * R16477 (0x405D) - DC2 ON Config
438 */
439#define WM831X_DC2_ON_SLOT_MASK 0xE000 /* DC2_ON_SLOT - [15:13] */
440#define WM831X_DC2_ON_SLOT_SHIFT 13 /* DC2_ON_SLOT - [15:13] */
441#define WM831X_DC2_ON_SLOT_WIDTH 3 /* DC2_ON_SLOT - [15:13] */
442#define WM831X_DC2_ON_MODE_MASK 0x0300 /* DC2_ON_MODE - [9:8] */
443#define WM831X_DC2_ON_MODE_SHIFT 8 /* DC2_ON_MODE - [9:8] */
444#define WM831X_DC2_ON_MODE_WIDTH 2 /* DC2_ON_MODE - [9:8] */
445#define WM831X_DC2_ON_VSEL_MASK 0x007F /* DC2_ON_VSEL - [6:0] */
446#define WM831X_DC2_ON_VSEL_SHIFT 0 /* DC2_ON_VSEL - [6:0] */
447#define WM831X_DC2_ON_VSEL_WIDTH 7 /* DC2_ON_VSEL - [6:0] */
448
449/*
450 * R16478 (0x405E) - DC2 SLEEP Control
451 */
452#define WM831X_DC2_SLP_SLOT_MASK 0xE000 /* DC2_SLP_SLOT - [15:13] */
453#define WM831X_DC2_SLP_SLOT_SHIFT 13 /* DC2_SLP_SLOT - [15:13] */
454#define WM831X_DC2_SLP_SLOT_WIDTH 3 /* DC2_SLP_SLOT - [15:13] */
455#define WM831X_DC2_SLP_MODE_MASK 0x0300 /* DC2_SLP_MODE - [9:8] */
456#define WM831X_DC2_SLP_MODE_SHIFT 8 /* DC2_SLP_MODE - [9:8] */
457#define WM831X_DC2_SLP_MODE_WIDTH 2 /* DC2_SLP_MODE - [9:8] */
458#define WM831X_DC2_SLP_VSEL_MASK 0x007F /* DC2_SLP_VSEL - [6:0] */
459#define WM831X_DC2_SLP_VSEL_SHIFT 0 /* DC2_SLP_VSEL - [6:0] */
460#define WM831X_DC2_SLP_VSEL_WIDTH 7 /* DC2_SLP_VSEL - [6:0] */
461
462/*
463 * R16479 (0x405F) - DC2 DVS Control
464 */
465#define WM831X_DC2_DVS_SRC_MASK 0x1800 /* DC2_DVS_SRC - [12:11] */
466#define WM831X_DC2_DVS_SRC_SHIFT 11 /* DC2_DVS_SRC - [12:11] */
467#define WM831X_DC2_DVS_SRC_WIDTH 2 /* DC2_DVS_SRC - [12:11] */
468#define WM831X_DC2_DVS_VSEL_MASK 0x007F /* DC2_DVS_VSEL - [6:0] */
469#define WM831X_DC2_DVS_VSEL_SHIFT 0 /* DC2_DVS_VSEL - [6:0] */
470#define WM831X_DC2_DVS_VSEL_WIDTH 7 /* DC2_DVS_VSEL - [6:0] */
471
472/*
473 * R16480 (0x4060) - DC3 Control 1
474 */
475#define WM831X_DC3_PHASE 0x1000 /* DC3_PHASE */
476#define WM831X_DC3_PHASE_MASK 0x1000 /* DC3_PHASE */
477#define WM831X_DC3_PHASE_SHIFT 12 /* DC3_PHASE */
478#define WM831X_DC3_PHASE_WIDTH 1 /* DC3_PHASE */
479#define WM831X_DC3_FLT 0x0080 /* DC3_FLT */
480#define WM831X_DC3_FLT_MASK 0x0080 /* DC3_FLT */
481#define WM831X_DC3_FLT_SHIFT 7 /* DC3_FLT */
482#define WM831X_DC3_FLT_WIDTH 1 /* DC3_FLT */
483#define WM831X_DC3_SOFT_START_MASK 0x0030 /* DC3_SOFT_START - [5:4] */
484#define WM831X_DC3_SOFT_START_SHIFT 4 /* DC3_SOFT_START - [5:4] */
485#define WM831X_DC3_SOFT_START_WIDTH 2 /* DC3_SOFT_START - [5:4] */
486#define WM831X_DC3_STNBY_LIM_MASK 0x000C /* DC3_STNBY_LIM - [3:2] */
487#define WM831X_DC3_STNBY_LIM_SHIFT 2 /* DC3_STNBY_LIM - [3:2] */
488#define WM831X_DC3_STNBY_LIM_WIDTH 2 /* DC3_STNBY_LIM - [3:2] */
489#define WM831X_DC3_CAP_MASK 0x0003 /* DC3_CAP - [1:0] */
490#define WM831X_DC3_CAP_SHIFT 0 /* DC3_CAP - [1:0] */
491#define WM831X_DC3_CAP_WIDTH 2 /* DC3_CAP - [1:0] */
492
493/*
494 * R16481 (0x4061) - DC3 Control 2
495 */
496#define WM831X_DC3_ERR_ACT_MASK 0xC000 /* DC3_ERR_ACT - [15:14] */
497#define WM831X_DC3_ERR_ACT_SHIFT 14 /* DC3_ERR_ACT - [15:14] */
498#define WM831X_DC3_ERR_ACT_WIDTH 2 /* DC3_ERR_ACT - [15:14] */
499#define WM831X_DC3_HWC_SRC_MASK 0x1800 /* DC3_HWC_SRC - [12:11] */
500#define WM831X_DC3_HWC_SRC_SHIFT 11 /* DC3_HWC_SRC - [12:11] */
501#define WM831X_DC3_HWC_SRC_WIDTH 2 /* DC3_HWC_SRC - [12:11] */
502#define WM831X_DC3_HWC_VSEL 0x0400 /* DC3_HWC_VSEL */
503#define WM831X_DC3_HWC_VSEL_MASK 0x0400 /* DC3_HWC_VSEL */
504#define WM831X_DC3_HWC_VSEL_SHIFT 10 /* DC3_HWC_VSEL */
505#define WM831X_DC3_HWC_VSEL_WIDTH 1 /* DC3_HWC_VSEL */
506#define WM831X_DC3_HWC_MODE_MASK 0x0300 /* DC3_HWC_MODE - [9:8] */
507#define WM831X_DC3_HWC_MODE_SHIFT 8 /* DC3_HWC_MODE - [9:8] */
508#define WM831X_DC3_HWC_MODE_WIDTH 2 /* DC3_HWC_MODE - [9:8] */
509#define WM831X_DC3_OVP 0x0080 /* DC3_OVP */
510#define WM831X_DC3_OVP_MASK 0x0080 /* DC3_OVP */
511#define WM831X_DC3_OVP_SHIFT 7 /* DC3_OVP */
512#define WM831X_DC3_OVP_WIDTH 1 /* DC3_OVP */
513
514/*
515 * R16482 (0x4062) - DC3 ON Config
516 */
517#define WM831X_DC3_ON_SLOT_MASK 0xE000 /* DC3_ON_SLOT - [15:13] */
518#define WM831X_DC3_ON_SLOT_SHIFT 13 /* DC3_ON_SLOT - [15:13] */
519#define WM831X_DC3_ON_SLOT_WIDTH 3 /* DC3_ON_SLOT - [15:13] */
520#define WM831X_DC3_ON_MODE_MASK 0x0300 /* DC3_ON_MODE - [9:8] */
521#define WM831X_DC3_ON_MODE_SHIFT 8 /* DC3_ON_MODE - [9:8] */
522#define WM831X_DC3_ON_MODE_WIDTH 2 /* DC3_ON_MODE - [9:8] */
523#define WM831X_DC3_ON_VSEL_MASK 0x007F /* DC3_ON_VSEL - [6:0] */
524#define WM831X_DC3_ON_VSEL_SHIFT 0 /* DC3_ON_VSEL - [6:0] */
525#define WM831X_DC3_ON_VSEL_WIDTH 7 /* DC3_ON_VSEL - [6:0] */
526
527/*
528 * R16483 (0x4063) - DC3 SLEEP Control
529 */
530#define WM831X_DC3_SLP_SLOT_MASK 0xE000 /* DC3_SLP_SLOT - [15:13] */
531#define WM831X_DC3_SLP_SLOT_SHIFT 13 /* DC3_SLP_SLOT - [15:13] */
532#define WM831X_DC3_SLP_SLOT_WIDTH 3 /* DC3_SLP_SLOT - [15:13] */
533#define WM831X_DC3_SLP_MODE_MASK 0x0300 /* DC3_SLP_MODE - [9:8] */
534#define WM831X_DC3_SLP_MODE_SHIFT 8 /* DC3_SLP_MODE - [9:8] */
535#define WM831X_DC3_SLP_MODE_WIDTH 2 /* DC3_SLP_MODE - [9:8] */
536#define WM831X_DC3_SLP_VSEL_MASK 0x007F /* DC3_SLP_VSEL - [6:0] */
537#define WM831X_DC3_SLP_VSEL_SHIFT 0 /* DC3_SLP_VSEL - [6:0] */
538#define WM831X_DC3_SLP_VSEL_WIDTH 7 /* DC3_SLP_VSEL - [6:0] */
539
540/*
541 * R16484 (0x4064) - DC4 Control
542 */
543#define WM831X_DC4_ERR_ACT_MASK 0xC000 /* DC4_ERR_ACT - [15:14] */
544#define WM831X_DC4_ERR_ACT_SHIFT 14 /* DC4_ERR_ACT - [15:14] */
545#define WM831X_DC4_ERR_ACT_WIDTH 2 /* DC4_ERR_ACT - [15:14] */
546#define WM831X_DC4_HWC_SRC_MASK 0x1800 /* DC4_HWC_SRC - [12:11] */
547#define WM831X_DC4_HWC_SRC_SHIFT 11 /* DC4_HWC_SRC - [12:11] */
548#define WM831X_DC4_HWC_SRC_WIDTH 2 /* DC4_HWC_SRC - [12:11] */
549#define WM831X_DC4_HWC_MODE 0x0100 /* DC4_HWC_MODE */
550#define WM831X_DC4_HWC_MODE_MASK 0x0100 /* DC4_HWC_MODE */
551#define WM831X_DC4_HWC_MODE_SHIFT 8 /* DC4_HWC_MODE */
552#define WM831X_DC4_HWC_MODE_WIDTH 1 /* DC4_HWC_MODE */
553#define WM831X_DC4_RANGE_MASK 0x000C /* DC4_RANGE - [3:2] */
554#define WM831X_DC4_RANGE_SHIFT 2 /* DC4_RANGE - [3:2] */
555#define WM831X_DC4_RANGE_WIDTH 2 /* DC4_RANGE - [3:2] */
556#define WM831X_DC4_FBSRC 0x0001 /* DC4_FBSRC */
557#define WM831X_DC4_FBSRC_MASK 0x0001 /* DC4_FBSRC */
558#define WM831X_DC4_FBSRC_SHIFT 0 /* DC4_FBSRC */
559#define WM831X_DC4_FBSRC_WIDTH 1 /* DC4_FBSRC */
560
561/*
562 * R16485 (0x4065) - DC4 SLEEP Control
563 */
564#define WM831X_DC4_SLPENA 0x0100 /* DC4_SLPENA */
565#define WM831X_DC4_SLPENA_MASK 0x0100 /* DC4_SLPENA */
566#define WM831X_DC4_SLPENA_SHIFT 8 /* DC4_SLPENA */
567#define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */
568
569/*
570 * R16488 (0x4068) - LDO1 Control
571 */
572#define WM831X_LDO1_ERR_ACT_MASK 0xC000 /* LDO1_ERR_ACT - [15:14] */
573#define WM831X_LDO1_ERR_ACT_SHIFT 14 /* LDO1_ERR_ACT - [15:14] */
574#define WM831X_LDO1_ERR_ACT_WIDTH 2 /* LDO1_ERR_ACT - [15:14] */
575#define WM831X_LDO1_HWC_SRC_MASK 0x1800 /* LDO1_HWC_SRC - [12:11] */
576#define WM831X_LDO1_HWC_SRC_SHIFT 11 /* LDO1_HWC_SRC - [12:11] */
577#define WM831X_LDO1_HWC_SRC_WIDTH 2 /* LDO1_HWC_SRC - [12:11] */
578#define WM831X_LDO1_HWC_VSEL 0x0400 /* LDO1_HWC_VSEL */
579#define WM831X_LDO1_HWC_VSEL_MASK 0x0400 /* LDO1_HWC_VSEL */
580#define WM831X_LDO1_HWC_VSEL_SHIFT 10 /* LDO1_HWC_VSEL */
581#define WM831X_LDO1_HWC_VSEL_WIDTH 1 /* LDO1_HWC_VSEL */
582#define WM831X_LDO1_HWC_MODE_MASK 0x0300 /* LDO1_HWC_MODE - [9:8] */
583#define WM831X_LDO1_HWC_MODE_SHIFT 8 /* LDO1_HWC_MODE - [9:8] */
584#define WM831X_LDO1_HWC_MODE_WIDTH 2 /* LDO1_HWC_MODE - [9:8] */
585#define WM831X_LDO1_FLT 0x0080 /* LDO1_FLT */
586#define WM831X_LDO1_FLT_MASK 0x0080 /* LDO1_FLT */
587#define WM831X_LDO1_FLT_SHIFT 7 /* LDO1_FLT */
588#define WM831X_LDO1_FLT_WIDTH 1 /* LDO1_FLT */
589#define WM831X_LDO1_SWI 0x0040 /* LDO1_SWI */
590#define WM831X_LDO1_SWI_MASK 0x0040 /* LDO1_SWI */
591#define WM831X_LDO1_SWI_SHIFT 6 /* LDO1_SWI */
592#define WM831X_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
593#define WM831X_LDO1_LP_MODE 0x0001 /* LDO1_LP_MODE */
594#define WM831X_LDO1_LP_MODE_MASK 0x0001 /* LDO1_LP_MODE */
595#define WM831X_LDO1_LP_MODE_SHIFT 0 /* LDO1_LP_MODE */
596#define WM831X_LDO1_LP_MODE_WIDTH 1 /* LDO1_LP_MODE */
597
598/*
599 * R16489 (0x4069) - LDO1 ON Control
600 */
601#define WM831X_LDO1_ON_SLOT_MASK 0xE000 /* LDO1_ON_SLOT - [15:13] */
602#define WM831X_LDO1_ON_SLOT_SHIFT 13 /* LDO1_ON_SLOT - [15:13] */
603#define WM831X_LDO1_ON_SLOT_WIDTH 3 /* LDO1_ON_SLOT - [15:13] */
604#define WM831X_LDO1_ON_MODE 0x0100 /* LDO1_ON_MODE */
605#define WM831X_LDO1_ON_MODE_MASK 0x0100 /* LDO1_ON_MODE */
606#define WM831X_LDO1_ON_MODE_SHIFT 8 /* LDO1_ON_MODE */
607#define WM831X_LDO1_ON_MODE_WIDTH 1 /* LDO1_ON_MODE */
608#define WM831X_LDO1_ON_VSEL_MASK 0x001F /* LDO1_ON_VSEL - [4:0] */
609#define WM831X_LDO1_ON_VSEL_SHIFT 0 /* LDO1_ON_VSEL - [4:0] */
610#define WM831X_LDO1_ON_VSEL_WIDTH 5 /* LDO1_ON_VSEL - [4:0] */
611
612/*
613 * R16490 (0x406A) - LDO1 SLEEP Control
614 */
615#define WM831X_LDO1_SLP_SLOT_MASK 0xE000 /* LDO1_SLP_SLOT - [15:13] */
616#define WM831X_LDO1_SLP_SLOT_SHIFT 13 /* LDO1_SLP_SLOT - [15:13] */
617#define WM831X_LDO1_SLP_SLOT_WIDTH 3 /* LDO1_SLP_SLOT - [15:13] */
618#define WM831X_LDO1_SLP_MODE 0x0100 /* LDO1_SLP_MODE */
619#define WM831X_LDO1_SLP_MODE_MASK 0x0100 /* LDO1_SLP_MODE */
620#define WM831X_LDO1_SLP_MODE_SHIFT 8 /* LDO1_SLP_MODE */
621#define WM831X_LDO1_SLP_MODE_WIDTH 1 /* LDO1_SLP_MODE */
622#define WM831X_LDO1_SLP_VSEL_MASK 0x001F /* LDO1_SLP_VSEL - [4:0] */
623#define WM831X_LDO1_SLP_VSEL_SHIFT 0 /* LDO1_SLP_VSEL - [4:0] */
624#define WM831X_LDO1_SLP_VSEL_WIDTH 5 /* LDO1_SLP_VSEL - [4:0] */
625
626/*
627 * R16491 (0x406B) - LDO2 Control
628 */
629#define WM831X_LDO2_ERR_ACT_MASK 0xC000 /* LDO2_ERR_ACT - [15:14] */
630#define WM831X_LDO2_ERR_ACT_SHIFT 14 /* LDO2_ERR_ACT - [15:14] */
631#define WM831X_LDO2_ERR_ACT_WIDTH 2 /* LDO2_ERR_ACT - [15:14] */
632#define WM831X_LDO2_HWC_SRC_MASK 0x1800 /* LDO2_HWC_SRC - [12:11] */
633#define WM831X_LDO2_HWC_SRC_SHIFT 11 /* LDO2_HWC_SRC - [12:11] */
634#define WM831X_LDO2_HWC_SRC_WIDTH 2 /* LDO2_HWC_SRC - [12:11] */
635#define WM831X_LDO2_HWC_VSEL 0x0400 /* LDO2_HWC_VSEL */
636#define WM831X_LDO2_HWC_VSEL_MASK 0x0400 /* LDO2_HWC_VSEL */
637#define WM831X_LDO2_HWC_VSEL_SHIFT 10 /* LDO2_HWC_VSEL */
638#define WM831X_LDO2_HWC_VSEL_WIDTH 1 /* LDO2_HWC_VSEL */
639#define WM831X_LDO2_HWC_MODE_MASK 0x0300 /* LDO2_HWC_MODE - [9:8] */
640#define WM831X_LDO2_HWC_MODE_SHIFT 8 /* LDO2_HWC_MODE - [9:8] */
641#define WM831X_LDO2_HWC_MODE_WIDTH 2 /* LDO2_HWC_MODE - [9:8] */
642#define WM831X_LDO2_FLT 0x0080 /* LDO2_FLT */
643#define WM831X_LDO2_FLT_MASK 0x0080 /* LDO2_FLT */
644#define WM831X_LDO2_FLT_SHIFT 7 /* LDO2_FLT */
645#define WM831X_LDO2_FLT_WIDTH 1 /* LDO2_FLT */
646#define WM831X_LDO2_SWI 0x0040 /* LDO2_SWI */
647#define WM831X_LDO2_SWI_MASK 0x0040 /* LDO2_SWI */
648#define WM831X_LDO2_SWI_SHIFT 6 /* LDO2_SWI */
649#define WM831X_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
650#define WM831X_LDO2_LP_MODE 0x0001 /* LDO2_LP_MODE */
651#define WM831X_LDO2_LP_MODE_MASK 0x0001 /* LDO2_LP_MODE */
652#define WM831X_LDO2_LP_MODE_SHIFT 0 /* LDO2_LP_MODE */
653#define WM831X_LDO2_LP_MODE_WIDTH 1 /* LDO2_LP_MODE */
654
655/*
656 * R16492 (0x406C) - LDO2 ON Control
657 */
658#define WM831X_LDO2_ON_SLOT_MASK 0xE000 /* LDO2_ON_SLOT - [15:13] */
659#define WM831X_LDO2_ON_SLOT_SHIFT 13 /* LDO2_ON_SLOT - [15:13] */
660#define WM831X_LDO2_ON_SLOT_WIDTH 3 /* LDO2_ON_SLOT - [15:13] */
661#define WM831X_LDO2_ON_MODE 0x0100 /* LDO2_ON_MODE */
662#define WM831X_LDO2_ON_MODE_MASK 0x0100 /* LDO2_ON_MODE */
663#define WM831X_LDO2_ON_MODE_SHIFT 8 /* LDO2_ON_MODE */
664#define WM831X_LDO2_ON_MODE_WIDTH 1 /* LDO2_ON_MODE */
665#define WM831X_LDO2_ON_VSEL_MASK 0x001F /* LDO2_ON_VSEL - [4:0] */
666#define WM831X_LDO2_ON_VSEL_SHIFT 0 /* LDO2_ON_VSEL - [4:0] */
667#define WM831X_LDO2_ON_VSEL_WIDTH 5 /* LDO2_ON_VSEL - [4:0] */
668
669/*
670 * R16493 (0x406D) - LDO2 SLEEP Control
671 */
672#define WM831X_LDO2_SLP_SLOT_MASK 0xE000 /* LDO2_SLP_SLOT - [15:13] */
673#define WM831X_LDO2_SLP_SLOT_SHIFT 13 /* LDO2_SLP_SLOT - [15:13] */
674#define WM831X_LDO2_SLP_SLOT_WIDTH 3 /* LDO2_SLP_SLOT - [15:13] */
675#define WM831X_LDO2_SLP_MODE 0x0100 /* LDO2_SLP_MODE */
676#define WM831X_LDO2_SLP_MODE_MASK 0x0100 /* LDO2_SLP_MODE */
677#define WM831X_LDO2_SLP_MODE_SHIFT 8 /* LDO2_SLP_MODE */
678#define WM831X_LDO2_SLP_MODE_WIDTH 1 /* LDO2_SLP_MODE */
679#define WM831X_LDO2_SLP_VSEL_MASK 0x001F /* LDO2_SLP_VSEL - [4:0] */
680#define WM831X_LDO2_SLP_VSEL_SHIFT 0 /* LDO2_SLP_VSEL - [4:0] */
681#define WM831X_LDO2_SLP_VSEL_WIDTH 5 /* LDO2_SLP_VSEL - [4:0] */
682
683/*
684 * R16494 (0x406E) - LDO3 Control
685 */
686#define WM831X_LDO3_ERR_ACT_MASK 0xC000 /* LDO3_ERR_ACT - [15:14] */
687#define WM831X_LDO3_ERR_ACT_SHIFT 14 /* LDO3_ERR_ACT - [15:14] */
688#define WM831X_LDO3_ERR_ACT_WIDTH 2 /* LDO3_ERR_ACT - [15:14] */
689#define WM831X_LDO3_HWC_SRC_MASK 0x1800 /* LDO3_HWC_SRC - [12:11] */
690#define WM831X_LDO3_HWC_SRC_SHIFT 11 /* LDO3_HWC_SRC - [12:11] */
691#define WM831X_LDO3_HWC_SRC_WIDTH 2 /* LDO3_HWC_SRC - [12:11] */
692#define WM831X_LDO3_HWC_VSEL 0x0400 /* LDO3_HWC_VSEL */
693#define WM831X_LDO3_HWC_VSEL_MASK 0x0400 /* LDO3_HWC_VSEL */
694#define WM831X_LDO3_HWC_VSEL_SHIFT 10 /* LDO3_HWC_VSEL */
695#define WM831X_LDO3_HWC_VSEL_WIDTH 1 /* LDO3_HWC_VSEL */
696#define WM831X_LDO3_HWC_MODE_MASK 0x0300 /* LDO3_HWC_MODE - [9:8] */
697#define WM831X_LDO3_HWC_MODE_SHIFT 8 /* LDO3_HWC_MODE - [9:8] */
698#define WM831X_LDO3_HWC_MODE_WIDTH 2 /* LDO3_HWC_MODE - [9:8] */
699#define WM831X_LDO3_FLT 0x0080 /* LDO3_FLT */
700#define WM831X_LDO3_FLT_MASK 0x0080 /* LDO3_FLT */
701#define WM831X_LDO3_FLT_SHIFT 7 /* LDO3_FLT */
702#define WM831X_LDO3_FLT_WIDTH 1 /* LDO3_FLT */
703#define WM831X_LDO3_SWI 0x0040 /* LDO3_SWI */
704#define WM831X_LDO3_SWI_MASK 0x0040 /* LDO3_SWI */
705#define WM831X_LDO3_SWI_SHIFT 6 /* LDO3_SWI */
706#define WM831X_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
707#define WM831X_LDO3_LP_MODE 0x0001 /* LDO3_LP_MODE */
708#define WM831X_LDO3_LP_MODE_MASK 0x0001 /* LDO3_LP_MODE */
709#define WM831X_LDO3_LP_MODE_SHIFT 0 /* LDO3_LP_MODE */
710#define WM831X_LDO3_LP_MODE_WIDTH 1 /* LDO3_LP_MODE */
711
712/*
713 * R16495 (0x406F) - LDO3 ON Control
714 */
715#define WM831X_LDO3_ON_SLOT_MASK 0xE000 /* LDO3_ON_SLOT - [15:13] */
716#define WM831X_LDO3_ON_SLOT_SHIFT 13 /* LDO3_ON_SLOT - [15:13] */
717#define WM831X_LDO3_ON_SLOT_WIDTH 3 /* LDO3_ON_SLOT - [15:13] */
718#define WM831X_LDO3_ON_MODE 0x0100 /* LDO3_ON_MODE */
719#define WM831X_LDO3_ON_MODE_MASK 0x0100 /* LDO3_ON_MODE */
720#define WM831X_LDO3_ON_MODE_SHIFT 8 /* LDO3_ON_MODE */
721#define WM831X_LDO3_ON_MODE_WIDTH 1 /* LDO3_ON_MODE */
722#define WM831X_LDO3_ON_VSEL_MASK 0x001F /* LDO3_ON_VSEL - [4:0] */
723#define WM831X_LDO3_ON_VSEL_SHIFT 0 /* LDO3_ON_VSEL - [4:0] */
724#define WM831X_LDO3_ON_VSEL_WIDTH 5 /* LDO3_ON_VSEL - [4:0] */
725
726/*
727 * R16496 (0x4070) - LDO3 SLEEP Control
728 */
729#define WM831X_LDO3_SLP_SLOT_MASK 0xE000 /* LDO3_SLP_SLOT - [15:13] */
730#define WM831X_LDO3_SLP_SLOT_SHIFT 13 /* LDO3_SLP_SLOT - [15:13] */
731#define WM831X_LDO3_SLP_SLOT_WIDTH 3 /* LDO3_SLP_SLOT - [15:13] */
732#define WM831X_LDO3_SLP_MODE 0x0100 /* LDO3_SLP_MODE */
733#define WM831X_LDO3_SLP_MODE_MASK 0x0100 /* LDO3_SLP_MODE */
734#define WM831X_LDO3_SLP_MODE_SHIFT 8 /* LDO3_SLP_MODE */
735#define WM831X_LDO3_SLP_MODE_WIDTH 1 /* LDO3_SLP_MODE */
736#define WM831X_LDO3_SLP_VSEL_MASK 0x001F /* LDO3_SLP_VSEL - [4:0] */
737#define WM831X_LDO3_SLP_VSEL_SHIFT 0 /* LDO3_SLP_VSEL - [4:0] */
738#define WM831X_LDO3_SLP_VSEL_WIDTH 5 /* LDO3_SLP_VSEL - [4:0] */
739
740/*
741 * R16497 (0x4071) - LDO4 Control
742 */
743#define WM831X_LDO4_ERR_ACT_MASK 0xC000 /* LDO4_ERR_ACT - [15:14] */
744#define WM831X_LDO4_ERR_ACT_SHIFT 14 /* LDO4_ERR_ACT - [15:14] */
745#define WM831X_LDO4_ERR_ACT_WIDTH 2 /* LDO4_ERR_ACT - [15:14] */
746#define WM831X_LDO4_HWC_SRC_MASK 0x1800 /* LDO4_HWC_SRC - [12:11] */
747#define WM831X_LDO4_HWC_SRC_SHIFT 11 /* LDO4_HWC_SRC - [12:11] */
748#define WM831X_LDO4_HWC_SRC_WIDTH 2 /* LDO4_HWC_SRC - [12:11] */
749#define WM831X_LDO4_HWC_VSEL 0x0400 /* LDO4_HWC_VSEL */
750#define WM831X_LDO4_HWC_VSEL_MASK 0x0400 /* LDO4_HWC_VSEL */
751#define WM831X_LDO4_HWC_VSEL_SHIFT 10 /* LDO4_HWC_VSEL */
752#define WM831X_LDO4_HWC_VSEL_WIDTH 1 /* LDO4_HWC_VSEL */
753#define WM831X_LDO4_HWC_MODE_MASK 0x0300 /* LDO4_HWC_MODE - [9:8] */
754#define WM831X_LDO4_HWC_MODE_SHIFT 8 /* LDO4_HWC_MODE - [9:8] */
755#define WM831X_LDO4_HWC_MODE_WIDTH 2 /* LDO4_HWC_MODE - [9:8] */
756#define WM831X_LDO4_FLT 0x0080 /* LDO4_FLT */
757#define WM831X_LDO4_FLT_MASK 0x0080 /* LDO4_FLT */
758#define WM831X_LDO4_FLT_SHIFT 7 /* LDO4_FLT */
759#define WM831X_LDO4_FLT_WIDTH 1 /* LDO4_FLT */
760#define WM831X_LDO4_SWI 0x0040 /* LDO4_SWI */
761#define WM831X_LDO4_SWI_MASK 0x0040 /* LDO4_SWI */
762#define WM831X_LDO4_SWI_SHIFT 6 /* LDO4_SWI */
763#define WM831X_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
764#define WM831X_LDO4_LP_MODE 0x0001 /* LDO4_LP_MODE */
765#define WM831X_LDO4_LP_MODE_MASK 0x0001 /* LDO4_LP_MODE */
766#define WM831X_LDO4_LP_MODE_SHIFT 0 /* LDO4_LP_MODE */
767#define WM831X_LDO4_LP_MODE_WIDTH 1 /* LDO4_LP_MODE */
768
769/*
770 * R16498 (0x4072) - LDO4 ON Control
771 */
772#define WM831X_LDO4_ON_SLOT_MASK 0xE000 /* LDO4_ON_SLOT - [15:13] */
773#define WM831X_LDO4_ON_SLOT_SHIFT 13 /* LDO4_ON_SLOT - [15:13] */
774#define WM831X_LDO4_ON_SLOT_WIDTH 3 /* LDO4_ON_SLOT - [15:13] */
775#define WM831X_LDO4_ON_MODE 0x0100 /* LDO4_ON_MODE */
776#define WM831X_LDO4_ON_MODE_MASK 0x0100 /* LDO4_ON_MODE */
777#define WM831X_LDO4_ON_MODE_SHIFT 8 /* LDO4_ON_MODE */
778#define WM831X_LDO4_ON_MODE_WIDTH 1 /* LDO4_ON_MODE */
779#define WM831X_LDO4_ON_VSEL_MASK 0x001F /* LDO4_ON_VSEL - [4:0] */
780#define WM831X_LDO4_ON_VSEL_SHIFT 0 /* LDO4_ON_VSEL - [4:0] */
781#define WM831X_LDO4_ON_VSEL_WIDTH 5 /* LDO4_ON_VSEL - [4:0] */
782
783/*
784 * R16499 (0x4073) - LDO4 SLEEP Control
785 */
786#define WM831X_LDO4_SLP_SLOT_MASK 0xE000 /* LDO4_SLP_SLOT - [15:13] */
787#define WM831X_LDO4_SLP_SLOT_SHIFT 13 /* LDO4_SLP_SLOT - [15:13] */
788#define WM831X_LDO4_SLP_SLOT_WIDTH 3 /* LDO4_SLP_SLOT - [15:13] */
789#define WM831X_LDO4_SLP_MODE 0x0100 /* LDO4_SLP_MODE */
790#define WM831X_LDO4_SLP_MODE_MASK 0x0100 /* LDO4_SLP_MODE */
791#define WM831X_LDO4_SLP_MODE_SHIFT 8 /* LDO4_SLP_MODE */
792#define WM831X_LDO4_SLP_MODE_WIDTH 1 /* LDO4_SLP_MODE */
793#define WM831X_LDO4_SLP_VSEL_MASK 0x001F /* LDO4_SLP_VSEL - [4:0] */
794#define WM831X_LDO4_SLP_VSEL_SHIFT 0 /* LDO4_SLP_VSEL - [4:0] */
795#define WM831X_LDO4_SLP_VSEL_WIDTH 5 /* LDO4_SLP_VSEL - [4:0] */
796
797/*
798 * R16500 (0x4074) - LDO5 Control
799 */
800#define WM831X_LDO5_ERR_ACT_MASK 0xC000 /* LDO5_ERR_ACT - [15:14] */
801#define WM831X_LDO5_ERR_ACT_SHIFT 14 /* LDO5_ERR_ACT - [15:14] */
802#define WM831X_LDO5_ERR_ACT_WIDTH 2 /* LDO5_ERR_ACT - [15:14] */
803#define WM831X_LDO5_HWC_SRC_MASK 0x1800 /* LDO5_HWC_SRC - [12:11] */
804#define WM831X_LDO5_HWC_SRC_SHIFT 11 /* LDO5_HWC_SRC - [12:11] */
805#define WM831X_LDO5_HWC_SRC_WIDTH 2 /* LDO5_HWC_SRC - [12:11] */
806#define WM831X_LDO5_HWC_VSEL 0x0400 /* LDO5_HWC_VSEL */
807#define WM831X_LDO5_HWC_VSEL_MASK 0x0400 /* LDO5_HWC_VSEL */
808#define WM831X_LDO5_HWC_VSEL_SHIFT 10 /* LDO5_HWC_VSEL */
809#define WM831X_LDO5_HWC_VSEL_WIDTH 1 /* LDO5_HWC_VSEL */
810#define WM831X_LDO5_HWC_MODE_MASK 0x0300 /* LDO5_HWC_MODE - [9:8] */
811#define WM831X_LDO5_HWC_MODE_SHIFT 8 /* LDO5_HWC_MODE - [9:8] */
812#define WM831X_LDO5_HWC_MODE_WIDTH 2 /* LDO5_HWC_MODE - [9:8] */
813#define WM831X_LDO5_FLT 0x0080 /* LDO5_FLT */
814#define WM831X_LDO5_FLT_MASK 0x0080 /* LDO5_FLT */
815#define WM831X_LDO5_FLT_SHIFT 7 /* LDO5_FLT */
816#define WM831X_LDO5_FLT_WIDTH 1 /* LDO5_FLT */
817#define WM831X_LDO5_SWI 0x0040 /* LDO5_SWI */
818#define WM831X_LDO5_SWI_MASK 0x0040 /* LDO5_SWI */
819#define WM831X_LDO5_SWI_SHIFT 6 /* LDO5_SWI */
820#define WM831X_LDO5_SWI_WIDTH 1 /* LDO5_SWI */
821#define WM831X_LDO5_LP_MODE 0x0001 /* LDO5_LP_MODE */
822#define WM831X_LDO5_LP_MODE_MASK 0x0001 /* LDO5_LP_MODE */
823#define WM831X_LDO5_LP_MODE_SHIFT 0 /* LDO5_LP_MODE */
824#define WM831X_LDO5_LP_MODE_WIDTH 1 /* LDO5_LP_MODE */
825
826/*
827 * R16501 (0x4075) - LDO5 ON Control
828 */
829#define WM831X_LDO5_ON_SLOT_MASK 0xE000 /* LDO5_ON_SLOT - [15:13] */
830#define WM831X_LDO5_ON_SLOT_SHIFT 13 /* LDO5_ON_SLOT - [15:13] */
831#define WM831X_LDO5_ON_SLOT_WIDTH 3 /* LDO5_ON_SLOT - [15:13] */
832#define WM831X_LDO5_ON_MODE 0x0100 /* LDO5_ON_MODE */
833#define WM831X_LDO5_ON_MODE_MASK 0x0100 /* LDO5_ON_MODE */
834#define WM831X_LDO5_ON_MODE_SHIFT 8 /* LDO5_ON_MODE */
835#define WM831X_LDO5_ON_MODE_WIDTH 1 /* LDO5_ON_MODE */
836#define WM831X_LDO5_ON_VSEL_MASK 0x001F /* LDO5_ON_VSEL - [4:0] */
837#define WM831X_LDO5_ON_VSEL_SHIFT 0 /* LDO5_ON_VSEL - [4:0] */
838#define WM831X_LDO5_ON_VSEL_WIDTH 5 /* LDO5_ON_VSEL - [4:0] */
839
840/*
841 * R16502 (0x4076) - LDO5 SLEEP Control
842 */
843#define WM831X_LDO5_SLP_SLOT_MASK 0xE000 /* LDO5_SLP_SLOT - [15:13] */
844#define WM831X_LDO5_SLP_SLOT_SHIFT 13 /* LDO5_SLP_SLOT - [15:13] */
845#define WM831X_LDO5_SLP_SLOT_WIDTH 3 /* LDO5_SLP_SLOT - [15:13] */
846#define WM831X_LDO5_SLP_MODE 0x0100 /* LDO5_SLP_MODE */
847#define WM831X_LDO5_SLP_MODE_MASK 0x0100 /* LDO5_SLP_MODE */
848#define WM831X_LDO5_SLP_MODE_SHIFT 8 /* LDO5_SLP_MODE */
849#define WM831X_LDO5_SLP_MODE_WIDTH 1 /* LDO5_SLP_MODE */
850#define WM831X_LDO5_SLP_VSEL_MASK 0x001F /* LDO5_SLP_VSEL - [4:0] */
851#define WM831X_LDO5_SLP_VSEL_SHIFT 0 /* LDO5_SLP_VSEL - [4:0] */
852#define WM831X_LDO5_SLP_VSEL_WIDTH 5 /* LDO5_SLP_VSEL - [4:0] */
853
854/*
855 * R16503 (0x4077) - LDO6 Control
856 */
857#define WM831X_LDO6_ERR_ACT_MASK 0xC000 /* LDO6_ERR_ACT - [15:14] */
858#define WM831X_LDO6_ERR_ACT_SHIFT 14 /* LDO6_ERR_ACT - [15:14] */
859#define WM831X_LDO6_ERR_ACT_WIDTH 2 /* LDO6_ERR_ACT - [15:14] */
860#define WM831X_LDO6_HWC_SRC_MASK 0x1800 /* LDO6_HWC_SRC - [12:11] */
861#define WM831X_LDO6_HWC_SRC_SHIFT 11 /* LDO6_HWC_SRC - [12:11] */
862#define WM831X_LDO6_HWC_SRC_WIDTH 2 /* LDO6_HWC_SRC - [12:11] */
863#define WM831X_LDO6_HWC_VSEL 0x0400 /* LDO6_HWC_VSEL */
864#define WM831X_LDO6_HWC_VSEL_MASK 0x0400 /* LDO6_HWC_VSEL */
865#define WM831X_LDO6_HWC_VSEL_SHIFT 10 /* LDO6_HWC_VSEL */
866#define WM831X_LDO6_HWC_VSEL_WIDTH 1 /* LDO6_HWC_VSEL */
867#define WM831X_LDO6_HWC_MODE_MASK 0x0300 /* LDO6_HWC_MODE - [9:8] */
868#define WM831X_LDO6_HWC_MODE_SHIFT 8 /* LDO6_HWC_MODE - [9:8] */
869#define WM831X_LDO6_HWC_MODE_WIDTH 2 /* LDO6_HWC_MODE - [9:8] */
870#define WM831X_LDO6_FLT 0x0080 /* LDO6_FLT */
871#define WM831X_LDO6_FLT_MASK 0x0080 /* LDO6_FLT */
872#define WM831X_LDO6_FLT_SHIFT 7 /* LDO6_FLT */
873#define WM831X_LDO6_FLT_WIDTH 1 /* LDO6_FLT */
874#define WM831X_LDO6_SWI 0x0040 /* LDO6_SWI */
875#define WM831X_LDO6_SWI_MASK 0x0040 /* LDO6_SWI */
876#define WM831X_LDO6_SWI_SHIFT 6 /* LDO6_SWI */
877#define WM831X_LDO6_SWI_WIDTH 1 /* LDO6_SWI */
878#define WM831X_LDO6_LP_MODE 0x0001 /* LDO6_LP_MODE */
879#define WM831X_LDO6_LP_MODE_MASK 0x0001 /* LDO6_LP_MODE */
880#define WM831X_LDO6_LP_MODE_SHIFT 0 /* LDO6_LP_MODE */
881#define WM831X_LDO6_LP_MODE_WIDTH 1 /* LDO6_LP_MODE */
882
883/*
884 * R16504 (0x4078) - LDO6 ON Control
885 */
886#define WM831X_LDO6_ON_SLOT_MASK 0xE000 /* LDO6_ON_SLOT - [15:13] */
887#define WM831X_LDO6_ON_SLOT_SHIFT 13 /* LDO6_ON_SLOT - [15:13] */
888#define WM831X_LDO6_ON_SLOT_WIDTH 3 /* LDO6_ON_SLOT - [15:13] */
889#define WM831X_LDO6_ON_MODE 0x0100 /* LDO6_ON_MODE */
890#define WM831X_LDO6_ON_MODE_MASK 0x0100 /* LDO6_ON_MODE */
891#define WM831X_LDO6_ON_MODE_SHIFT 8 /* LDO6_ON_MODE */
892#define WM831X_LDO6_ON_MODE_WIDTH 1 /* LDO6_ON_MODE */
893#define WM831X_LDO6_ON_VSEL_MASK 0x001F /* LDO6_ON_VSEL - [4:0] */
894#define WM831X_LDO6_ON_VSEL_SHIFT 0 /* LDO6_ON_VSEL - [4:0] */
895#define WM831X_LDO6_ON_VSEL_WIDTH 5 /* LDO6_ON_VSEL - [4:0] */
896
897/*
898 * R16505 (0x4079) - LDO6 SLEEP Control
899 */
900#define WM831X_LDO6_SLP_SLOT_MASK 0xE000 /* LDO6_SLP_SLOT - [15:13] */
901#define WM831X_LDO6_SLP_SLOT_SHIFT 13 /* LDO6_SLP_SLOT - [15:13] */
902#define WM831X_LDO6_SLP_SLOT_WIDTH 3 /* LDO6_SLP_SLOT - [15:13] */
903#define WM831X_LDO6_SLP_MODE 0x0100 /* LDO6_SLP_MODE */
904#define WM831X_LDO6_SLP_MODE_MASK 0x0100 /* LDO6_SLP_MODE */
905#define WM831X_LDO6_SLP_MODE_SHIFT 8 /* LDO6_SLP_MODE */
906#define WM831X_LDO6_SLP_MODE_WIDTH 1 /* LDO6_SLP_MODE */
907#define WM831X_LDO6_SLP_VSEL_MASK 0x001F /* LDO6_SLP_VSEL - [4:0] */
908#define WM831X_LDO6_SLP_VSEL_SHIFT 0 /* LDO6_SLP_VSEL - [4:0] */
909#define WM831X_LDO6_SLP_VSEL_WIDTH 5 /* LDO6_SLP_VSEL - [4:0] */
910
911/*
912 * R16506 (0x407A) - LDO7 Control
913 */
914#define WM831X_LDO7_ERR_ACT_MASK 0xC000 /* LDO7_ERR_ACT - [15:14] */
915#define WM831X_LDO7_ERR_ACT_SHIFT 14 /* LDO7_ERR_ACT - [15:14] */
916#define WM831X_LDO7_ERR_ACT_WIDTH 2 /* LDO7_ERR_ACT - [15:14] */
917#define WM831X_LDO7_HWC_SRC_MASK 0x1800 /* LDO7_HWC_SRC - [12:11] */
918#define WM831X_LDO7_HWC_SRC_SHIFT 11 /* LDO7_HWC_SRC - [12:11] */
919#define WM831X_LDO7_HWC_SRC_WIDTH 2 /* LDO7_HWC_SRC - [12:11] */
920#define WM831X_LDO7_HWC_VSEL 0x0400 /* LDO7_HWC_VSEL */
921#define WM831X_LDO7_HWC_VSEL_MASK 0x0400 /* LDO7_HWC_VSEL */
922#define WM831X_LDO7_HWC_VSEL_SHIFT 10 /* LDO7_HWC_VSEL */
923#define WM831X_LDO7_HWC_VSEL_WIDTH 1 /* LDO7_HWC_VSEL */
924#define WM831X_LDO7_HWC_MODE_MASK 0x0300 /* LDO7_HWC_MODE - [9:8] */
925#define WM831X_LDO7_HWC_MODE_SHIFT 8 /* LDO7_HWC_MODE - [9:8] */
926#define WM831X_LDO7_HWC_MODE_WIDTH 2 /* LDO7_HWC_MODE - [9:8] */
927#define WM831X_LDO7_FLT 0x0080 /* LDO7_FLT */
928#define WM831X_LDO7_FLT_MASK 0x0080 /* LDO7_FLT */
929#define WM831X_LDO7_FLT_SHIFT 7 /* LDO7_FLT */
930#define WM831X_LDO7_FLT_WIDTH 1 /* LDO7_FLT */
931#define WM831X_LDO7_SWI 0x0040 /* LDO7_SWI */
932#define WM831X_LDO7_SWI_MASK 0x0040 /* LDO7_SWI */
933#define WM831X_LDO7_SWI_SHIFT 6 /* LDO7_SWI */
934#define WM831X_LDO7_SWI_WIDTH 1 /* LDO7_SWI */
935
936/*
937 * R16507 (0x407B) - LDO7 ON Control
938 */
939#define WM831X_LDO7_ON_SLOT_MASK 0xE000 /* LDO7_ON_SLOT - [15:13] */
940#define WM831X_LDO7_ON_SLOT_SHIFT 13 /* LDO7_ON_SLOT - [15:13] */
941#define WM831X_LDO7_ON_SLOT_WIDTH 3 /* LDO7_ON_SLOT - [15:13] */
942#define WM831X_LDO7_ON_MODE 0x0100 /* LDO7_ON_MODE */
943#define WM831X_LDO7_ON_MODE_MASK 0x0100 /* LDO7_ON_MODE */
944#define WM831X_LDO7_ON_MODE_SHIFT 8 /* LDO7_ON_MODE */
945#define WM831X_LDO7_ON_MODE_WIDTH 1 /* LDO7_ON_MODE */
946#define WM831X_LDO7_ON_VSEL_MASK 0x001F /* LDO7_ON_VSEL - [4:0] */
947#define WM831X_LDO7_ON_VSEL_SHIFT 0 /* LDO7_ON_VSEL - [4:0] */
948#define WM831X_LDO7_ON_VSEL_WIDTH 5 /* LDO7_ON_VSEL - [4:0] */
949
950/*
951 * R16508 (0x407C) - LDO7 SLEEP Control
952 */
953#define WM831X_LDO7_SLP_SLOT_MASK 0xE000 /* LDO7_SLP_SLOT - [15:13] */
954#define WM831X_LDO7_SLP_SLOT_SHIFT 13 /* LDO7_SLP_SLOT - [15:13] */
955#define WM831X_LDO7_SLP_SLOT_WIDTH 3 /* LDO7_SLP_SLOT - [15:13] */
956#define WM831X_LDO7_SLP_MODE 0x0100 /* LDO7_SLP_MODE */
957#define WM831X_LDO7_SLP_MODE_MASK 0x0100 /* LDO7_SLP_MODE */
958#define WM831X_LDO7_SLP_MODE_SHIFT 8 /* LDO7_SLP_MODE */
959#define WM831X_LDO7_SLP_MODE_WIDTH 1 /* LDO7_SLP_MODE */
960#define WM831X_LDO7_SLP_VSEL_MASK 0x001F /* LDO7_SLP_VSEL - [4:0] */
961#define WM831X_LDO7_SLP_VSEL_SHIFT 0 /* LDO7_SLP_VSEL - [4:0] */
962#define WM831X_LDO7_SLP_VSEL_WIDTH 5 /* LDO7_SLP_VSEL - [4:0] */
963
964/*
965 * R16509 (0x407D) - LDO8 Control
966 */
967#define WM831X_LDO8_ERR_ACT_MASK 0xC000 /* LDO8_ERR_ACT - [15:14] */
968#define WM831X_LDO8_ERR_ACT_SHIFT 14 /* LDO8_ERR_ACT - [15:14] */
969#define WM831X_LDO8_ERR_ACT_WIDTH 2 /* LDO8_ERR_ACT - [15:14] */
970#define WM831X_LDO8_HWC_SRC_MASK 0x1800 /* LDO8_HWC_SRC - [12:11] */
971#define WM831X_LDO8_HWC_SRC_SHIFT 11 /* LDO8_HWC_SRC - [12:11] */
972#define WM831X_LDO8_HWC_SRC_WIDTH 2 /* LDO8_HWC_SRC - [12:11] */
973#define WM831X_LDO8_HWC_VSEL 0x0400 /* LDO8_HWC_VSEL */
974#define WM831X_LDO8_HWC_VSEL_MASK 0x0400 /* LDO8_HWC_VSEL */
975#define WM831X_LDO8_HWC_VSEL_SHIFT 10 /* LDO8_HWC_VSEL */
976#define WM831X_LDO8_HWC_VSEL_WIDTH 1 /* LDO8_HWC_VSEL */
977#define WM831X_LDO8_HWC_MODE_MASK 0x0300 /* LDO8_HWC_MODE - [9:8] */
978#define WM831X_LDO8_HWC_MODE_SHIFT 8 /* LDO8_HWC_MODE - [9:8] */
979#define WM831X_LDO8_HWC_MODE_WIDTH 2 /* LDO8_HWC_MODE - [9:8] */
980#define WM831X_LDO8_FLT 0x0080 /* LDO8_FLT */
981#define WM831X_LDO8_FLT_MASK 0x0080 /* LDO8_FLT */
982#define WM831X_LDO8_FLT_SHIFT 7 /* LDO8_FLT */
983#define WM831X_LDO8_FLT_WIDTH 1 /* LDO8_FLT */
984#define WM831X_LDO8_SWI 0x0040 /* LDO8_SWI */
985#define WM831X_LDO8_SWI_MASK 0x0040 /* LDO8_SWI */
986#define WM831X_LDO8_SWI_SHIFT 6 /* LDO8_SWI */
987#define WM831X_LDO8_SWI_WIDTH 1 /* LDO8_SWI */
988
989/*
990 * R16510 (0x407E) - LDO8 ON Control
991 */
992#define WM831X_LDO8_ON_SLOT_MASK 0xE000 /* LDO8_ON_SLOT - [15:13] */
993#define WM831X_LDO8_ON_SLOT_SHIFT 13 /* LDO8_ON_SLOT - [15:13] */
994#define WM831X_LDO8_ON_SLOT_WIDTH 3 /* LDO8_ON_SLOT - [15:13] */
995#define WM831X_LDO8_ON_MODE 0x0100 /* LDO8_ON_MODE */
996#define WM831X_LDO8_ON_MODE_MASK 0x0100 /* LDO8_ON_MODE */
997#define WM831X_LDO8_ON_MODE_SHIFT 8 /* LDO8_ON_MODE */
998#define WM831X_LDO8_ON_MODE_WIDTH 1 /* LDO8_ON_MODE */
999#define WM831X_LDO8_ON_VSEL_MASK 0x001F /* LDO8_ON_VSEL - [4:0] */
1000#define WM831X_LDO8_ON_VSEL_SHIFT 0 /* LDO8_ON_VSEL - [4:0] */
1001#define WM831X_LDO8_ON_VSEL_WIDTH 5 /* LDO8_ON_VSEL - [4:0] */
1002
1003/*
1004 * R16511 (0x407F) - LDO8 SLEEP Control
1005 */
1006#define WM831X_LDO8_SLP_SLOT_MASK 0xE000 /* LDO8_SLP_SLOT - [15:13] */
1007#define WM831X_LDO8_SLP_SLOT_SHIFT 13 /* LDO8_SLP_SLOT - [15:13] */
1008#define WM831X_LDO8_SLP_SLOT_WIDTH 3 /* LDO8_SLP_SLOT - [15:13] */
1009#define WM831X_LDO8_SLP_MODE 0x0100 /* LDO8_SLP_MODE */
1010#define WM831X_LDO8_SLP_MODE_MASK 0x0100 /* LDO8_SLP_MODE */
1011#define WM831X_LDO8_SLP_MODE_SHIFT 8 /* LDO8_SLP_MODE */
1012#define WM831X_LDO8_SLP_MODE_WIDTH 1 /* LDO8_SLP_MODE */
1013#define WM831X_LDO8_SLP_VSEL_MASK 0x001F /* LDO8_SLP_VSEL - [4:0] */
1014#define WM831X_LDO8_SLP_VSEL_SHIFT 0 /* LDO8_SLP_VSEL - [4:0] */
1015#define WM831X_LDO8_SLP_VSEL_WIDTH 5 /* LDO8_SLP_VSEL - [4:0] */
1016
1017/*
1018 * R16512 (0x4080) - LDO9 Control
1019 */
1020#define WM831X_LDO9_ERR_ACT_MASK 0xC000 /* LDO9_ERR_ACT - [15:14] */
1021#define WM831X_LDO9_ERR_ACT_SHIFT 14 /* LDO9_ERR_ACT - [15:14] */
1022#define WM831X_LDO9_ERR_ACT_WIDTH 2 /* LDO9_ERR_ACT - [15:14] */
1023#define WM831X_LDO9_HWC_SRC_MASK 0x1800 /* LDO9_HWC_SRC - [12:11] */
1024#define WM831X_LDO9_HWC_SRC_SHIFT 11 /* LDO9_HWC_SRC - [12:11] */
1025#define WM831X_LDO9_HWC_SRC_WIDTH 2 /* LDO9_HWC_SRC - [12:11] */
1026#define WM831X_LDO9_HWC_VSEL 0x0400 /* LDO9_HWC_VSEL */
1027#define WM831X_LDO9_HWC_VSEL_MASK 0x0400 /* LDO9_HWC_VSEL */
1028#define WM831X_LDO9_HWC_VSEL_SHIFT 10 /* LDO9_HWC_VSEL */
1029#define WM831X_LDO9_HWC_VSEL_WIDTH 1 /* LDO9_HWC_VSEL */
1030#define WM831X_LDO9_HWC_MODE_MASK 0x0300 /* LDO9_HWC_MODE - [9:8] */
1031#define WM831X_LDO9_HWC_MODE_SHIFT 8 /* LDO9_HWC_MODE - [9:8] */
1032#define WM831X_LDO9_HWC_MODE_WIDTH 2 /* LDO9_HWC_MODE - [9:8] */
1033#define WM831X_LDO9_FLT 0x0080 /* LDO9_FLT */
1034#define WM831X_LDO9_FLT_MASK 0x0080 /* LDO9_FLT */
1035#define WM831X_LDO9_FLT_SHIFT 7 /* LDO9_FLT */
1036#define WM831X_LDO9_FLT_WIDTH 1 /* LDO9_FLT */
1037#define WM831X_LDO9_SWI 0x0040 /* LDO9_SWI */
1038#define WM831X_LDO9_SWI_MASK 0x0040 /* LDO9_SWI */
1039#define WM831X_LDO9_SWI_SHIFT 6 /* LDO9_SWI */
1040#define WM831X_LDO9_SWI_WIDTH 1 /* LDO9_SWI */
1041
1042/*
1043 * R16513 (0x4081) - LDO9 ON Control
1044 */
1045#define WM831X_LDO9_ON_SLOT_MASK 0xE000 /* LDO9_ON_SLOT - [15:13] */
1046#define WM831X_LDO9_ON_SLOT_SHIFT 13 /* LDO9_ON_SLOT - [15:13] */
1047#define WM831X_LDO9_ON_SLOT_WIDTH 3 /* LDO9_ON_SLOT - [15:13] */
1048#define WM831X_LDO9_ON_MODE 0x0100 /* LDO9_ON_MODE */
1049#define WM831X_LDO9_ON_MODE_MASK 0x0100 /* LDO9_ON_MODE */
1050#define WM831X_LDO9_ON_MODE_SHIFT 8 /* LDO9_ON_MODE */
1051#define WM831X_LDO9_ON_MODE_WIDTH 1 /* LDO9_ON_MODE */
1052#define WM831X_LDO9_ON_VSEL_MASK 0x001F /* LDO9_ON_VSEL - [4:0] */
1053#define WM831X_LDO9_ON_VSEL_SHIFT 0 /* LDO9_ON_VSEL - [4:0] */
1054#define WM831X_LDO9_ON_VSEL_WIDTH 5 /* LDO9_ON_VSEL - [4:0] */
1055
1056/*
1057 * R16514 (0x4082) - LDO9 SLEEP Control
1058 */
1059#define WM831X_LDO9_SLP_SLOT_MASK 0xE000 /* LDO9_SLP_SLOT - [15:13] */
1060#define WM831X_LDO9_SLP_SLOT_SHIFT 13 /* LDO9_SLP_SLOT - [15:13] */
1061#define WM831X_LDO9_SLP_SLOT_WIDTH 3 /* LDO9_SLP_SLOT - [15:13] */
1062#define WM831X_LDO9_SLP_MODE 0x0100 /* LDO9_SLP_MODE */
1063#define WM831X_LDO9_SLP_MODE_MASK 0x0100 /* LDO9_SLP_MODE */
1064#define WM831X_LDO9_SLP_MODE_SHIFT 8 /* LDO9_SLP_MODE */
1065#define WM831X_LDO9_SLP_MODE_WIDTH 1 /* LDO9_SLP_MODE */
1066#define WM831X_LDO9_SLP_VSEL_MASK 0x001F /* LDO9_SLP_VSEL - [4:0] */
1067#define WM831X_LDO9_SLP_VSEL_SHIFT 0 /* LDO9_SLP_VSEL - [4:0] */
1068#define WM831X_LDO9_SLP_VSEL_WIDTH 5 /* LDO9_SLP_VSEL - [4:0] */
1069
1070/*
1071 * R16515 (0x4083) - LDO10 Control
1072 */
1073#define WM831X_LDO10_ERR_ACT_MASK 0xC000 /* LDO10_ERR_ACT - [15:14] */
1074#define WM831X_LDO10_ERR_ACT_SHIFT 14 /* LDO10_ERR_ACT - [15:14] */
1075#define WM831X_LDO10_ERR_ACT_WIDTH 2 /* LDO10_ERR_ACT - [15:14] */
1076#define WM831X_LDO10_HWC_SRC_MASK 0x1800 /* LDO10_HWC_SRC - [12:11] */
1077#define WM831X_LDO10_HWC_SRC_SHIFT 11 /* LDO10_HWC_SRC - [12:11] */
1078#define WM831X_LDO10_HWC_SRC_WIDTH 2 /* LDO10_HWC_SRC - [12:11] */
1079#define WM831X_LDO10_HWC_VSEL 0x0400 /* LDO10_HWC_VSEL */
1080#define WM831X_LDO10_HWC_VSEL_MASK 0x0400 /* LDO10_HWC_VSEL */
1081#define WM831X_LDO10_HWC_VSEL_SHIFT 10 /* LDO10_HWC_VSEL */
1082#define WM831X_LDO10_HWC_VSEL_WIDTH 1 /* LDO10_HWC_VSEL */
1083#define WM831X_LDO10_HWC_MODE_MASK 0x0300 /* LDO10_HWC_MODE - [9:8] */
1084#define WM831X_LDO10_HWC_MODE_SHIFT 8 /* LDO10_HWC_MODE - [9:8] */
1085#define WM831X_LDO10_HWC_MODE_WIDTH 2 /* LDO10_HWC_MODE - [9:8] */
1086#define WM831X_LDO10_FLT 0x0080 /* LDO10_FLT */
1087#define WM831X_LDO10_FLT_MASK 0x0080 /* LDO10_FLT */
1088#define WM831X_LDO10_FLT_SHIFT 7 /* LDO10_FLT */
1089#define WM831X_LDO10_FLT_WIDTH 1 /* LDO10_FLT */
1090#define WM831X_LDO10_SWI 0x0040 /* LDO10_SWI */
1091#define WM831X_LDO10_SWI_MASK 0x0040 /* LDO10_SWI */
1092#define WM831X_LDO10_SWI_SHIFT 6 /* LDO10_SWI */
1093#define WM831X_LDO10_SWI_WIDTH 1 /* LDO10_SWI */
1094
1095/*
1096 * R16516 (0x4084) - LDO10 ON Control
1097 */
1098#define WM831X_LDO10_ON_SLOT_MASK 0xE000 /* LDO10_ON_SLOT - [15:13] */
1099#define WM831X_LDO10_ON_SLOT_SHIFT 13 /* LDO10_ON_SLOT - [15:13] */
1100#define WM831X_LDO10_ON_SLOT_WIDTH 3 /* LDO10_ON_SLOT - [15:13] */
1101#define WM831X_LDO10_ON_MODE 0x0100 /* LDO10_ON_MODE */
1102#define WM831X_LDO10_ON_MODE_MASK 0x0100 /* LDO10_ON_MODE */
1103#define WM831X_LDO10_ON_MODE_SHIFT 8 /* LDO10_ON_MODE */
1104#define WM831X_LDO10_ON_MODE_WIDTH 1 /* LDO10_ON_MODE */
1105#define WM831X_LDO10_ON_VSEL_MASK 0x001F /* LDO10_ON_VSEL - [4:0] */
1106#define WM831X_LDO10_ON_VSEL_SHIFT 0 /* LDO10_ON_VSEL - [4:0] */
1107#define WM831X_LDO10_ON_VSEL_WIDTH 5 /* LDO10_ON_VSEL - [4:0] */
1108
1109/*
1110 * R16517 (0x4085) - LDO10 SLEEP Control
1111 */
1112#define WM831X_LDO10_SLP_SLOT_MASK 0xE000 /* LDO10_SLP_SLOT - [15:13] */
1113#define WM831X_LDO10_SLP_SLOT_SHIFT 13 /* LDO10_SLP_SLOT - [15:13] */
1114#define WM831X_LDO10_SLP_SLOT_WIDTH 3 /* LDO10_SLP_SLOT - [15:13] */
1115#define WM831X_LDO10_SLP_MODE 0x0100 /* LDO10_SLP_MODE */
1116#define WM831X_LDO10_SLP_MODE_MASK 0x0100 /* LDO10_SLP_MODE */
1117#define WM831X_LDO10_SLP_MODE_SHIFT 8 /* LDO10_SLP_MODE */
1118#define WM831X_LDO10_SLP_MODE_WIDTH 1 /* LDO10_SLP_MODE */
1119#define WM831X_LDO10_SLP_VSEL_MASK 0x001F /* LDO10_SLP_VSEL - [4:0] */
1120#define WM831X_LDO10_SLP_VSEL_SHIFT 0 /* LDO10_SLP_VSEL - [4:0] */
1121#define WM831X_LDO10_SLP_VSEL_WIDTH 5 /* LDO10_SLP_VSEL - [4:0] */
1122
1123/*
1124 * R16519 (0x4087) - LDO11 ON Control
1125 */
1126#define WM831X_LDO11_ON_SLOT_MASK 0xE000 /* LDO11_ON_SLOT - [15:13] */
1127#define WM831X_LDO11_ON_SLOT_SHIFT 13 /* LDO11_ON_SLOT - [15:13] */
1128#define WM831X_LDO11_ON_SLOT_WIDTH 3 /* LDO11_ON_SLOT - [15:13] */
1129#define WM831X_LDO11_OFFENA 0x1000 /* LDO11_OFFENA */
1130#define WM831X_LDO11_OFFENA_MASK 0x1000 /* LDO11_OFFENA */
1131#define WM831X_LDO11_OFFENA_SHIFT 12 /* LDO11_OFFENA */
1132#define WM831X_LDO11_OFFENA_WIDTH 1 /* LDO11_OFFENA */
1133#define WM831X_LDO11_VSEL_SRC 0x0080 /* LDO11_VSEL_SRC */
1134#define WM831X_LDO11_VSEL_SRC_MASK 0x0080 /* LDO11_VSEL_SRC */
1135#define WM831X_LDO11_VSEL_SRC_SHIFT 7 /* LDO11_VSEL_SRC */
1136#define WM831X_LDO11_VSEL_SRC_WIDTH 1 /* LDO11_VSEL_SRC */
1137#define WM831X_LDO11_ON_VSEL_MASK 0x000F /* LDO11_ON_VSEL - [3:0] */
1138#define WM831X_LDO11_ON_VSEL_SHIFT 0 /* LDO11_ON_VSEL - [3:0] */
1139#define WM831X_LDO11_ON_VSEL_WIDTH 4 /* LDO11_ON_VSEL - [3:0] */
1140
1141/*
1142 * R16520 (0x4088) - LDO11 SLEEP Control
1143 */
1144#define WM831X_LDO11_SLP_SLOT_MASK 0xE000 /* LDO11_SLP_SLOT - [15:13] */
1145#define WM831X_LDO11_SLP_SLOT_SHIFT 13 /* LDO11_SLP_SLOT - [15:13] */
1146#define WM831X_LDO11_SLP_SLOT_WIDTH 3 /* LDO11_SLP_SLOT - [15:13] */
1147#define WM831X_LDO11_SLP_VSEL_MASK 0x000F /* LDO11_SLP_VSEL - [3:0] */
1148#define WM831X_LDO11_SLP_VSEL_SHIFT 0 /* LDO11_SLP_VSEL - [3:0] */
1149#define WM831X_LDO11_SLP_VSEL_WIDTH 4 /* LDO11_SLP_VSEL - [3:0] */
1150
1151/*
1152 * R16526 (0x408E) - Power Good Source 1
1153 */
1154#define WM831X_DC4_OK 0x0008 /* DC4_OK */
1155#define WM831X_DC4_OK_MASK 0x0008 /* DC4_OK */
1156#define WM831X_DC4_OK_SHIFT 3 /* DC4_OK */
1157#define WM831X_DC4_OK_WIDTH 1 /* DC4_OK */
1158#define WM831X_DC3_OK 0x0004 /* DC3_OK */
1159#define WM831X_DC3_OK_MASK 0x0004 /* DC3_OK */
1160#define WM831X_DC3_OK_SHIFT 2 /* DC3_OK */
1161#define WM831X_DC3_OK_WIDTH 1 /* DC3_OK */
1162#define WM831X_DC2_OK 0x0002 /* DC2_OK */
1163#define WM831X_DC2_OK_MASK 0x0002 /* DC2_OK */
1164#define WM831X_DC2_OK_SHIFT 1 /* DC2_OK */
1165#define WM831X_DC2_OK_WIDTH 1 /* DC2_OK */
1166#define WM831X_DC1_OK 0x0001 /* DC1_OK */
1167#define WM831X_DC1_OK_MASK 0x0001 /* DC1_OK */
1168#define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */
1169#define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */
1170
1171/*
1172 * R16527 (0x408F) - Power Good Source 2
1173 */
1174#define WM831X_LDO10_OK 0x0200 /* LDO10_OK */
1175#define WM831X_LDO10_OK_MASK 0x0200 /* LDO10_OK */
1176#define WM831X_LDO10_OK_SHIFT 9 /* LDO10_OK */
1177#define WM831X_LDO10_OK_WIDTH 1 /* LDO10_OK */
1178#define WM831X_LDO9_OK 0x0100 /* LDO9_OK */
1179#define WM831X_LDO9_OK_MASK 0x0100 /* LDO9_OK */
1180#define WM831X_LDO9_OK_SHIFT 8 /* LDO9_OK */
1181#define WM831X_LDO9_OK_WIDTH 1 /* LDO9_OK */
1182#define WM831X_LDO8_OK 0x0080 /* LDO8_OK */
1183#define WM831X_LDO8_OK_MASK 0x0080 /* LDO8_OK */
1184#define WM831X_LDO8_OK_SHIFT 7 /* LDO8_OK */
1185#define WM831X_LDO8_OK_WIDTH 1 /* LDO8_OK */
1186#define WM831X_LDO7_OK 0x0040 /* LDO7_OK */
1187#define WM831X_LDO7_OK_MASK 0x0040 /* LDO7_OK */
1188#define WM831X_LDO7_OK_SHIFT 6 /* LDO7_OK */
1189#define WM831X_LDO7_OK_WIDTH 1 /* LDO7_OK */
1190#define WM831X_LDO6_OK 0x0020 /* LDO6_OK */
1191#define WM831X_LDO6_OK_MASK 0x0020 /* LDO6_OK */
1192#define WM831X_LDO6_OK_SHIFT 5 /* LDO6_OK */
1193#define WM831X_LDO6_OK_WIDTH 1 /* LDO6_OK */
1194#define WM831X_LDO5_OK 0x0010 /* LDO5_OK */
1195#define WM831X_LDO5_OK_MASK 0x0010 /* LDO5_OK */
1196#define WM831X_LDO5_OK_SHIFT 4 /* LDO5_OK */
1197#define WM831X_LDO5_OK_WIDTH 1 /* LDO5_OK */
1198#define WM831X_LDO4_OK 0x0008 /* LDO4_OK */
1199#define WM831X_LDO4_OK_MASK 0x0008 /* LDO4_OK */
1200#define WM831X_LDO4_OK_SHIFT 3 /* LDO4_OK */
1201#define WM831X_LDO4_OK_WIDTH 1 /* LDO4_OK */
1202#define WM831X_LDO3_OK 0x0004 /* LDO3_OK */
1203#define WM831X_LDO3_OK_MASK 0x0004 /* LDO3_OK */
1204#define WM831X_LDO3_OK_SHIFT 2 /* LDO3_OK */
1205#define WM831X_LDO3_OK_WIDTH 1 /* LDO3_OK */
1206#define WM831X_LDO2_OK 0x0002 /* LDO2_OK */
1207#define WM831X_LDO2_OK_MASK 0x0002 /* LDO2_OK */
1208#define WM831X_LDO2_OK_SHIFT 1 /* LDO2_OK */
1209#define WM831X_LDO2_OK_WIDTH 1 /* LDO2_OK */
1210#define WM831X_LDO1_OK 0x0001 /* LDO1_OK */
1211#define WM831X_LDO1_OK_MASK 0x0001 /* LDO1_OK */
1212#define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */
1213#define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */
1214
1215#define WM831X_ISINK_MAX_ISEL 56
1216extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL];
1217
1218#endif
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 42cca672f340..1d595de6a055 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -605,6 +605,11 @@ struct wm8350_irq {
605 void *data; 605 void *data;
606}; 606};
607 607
608struct wm8350_hwmon {
609 struct platform_device *pdev;
610 struct device *classdev;
611};
612
608struct wm8350 { 613struct wm8350 {
609 struct device *dev; 614 struct device *dev;
610 615
@@ -621,7 +626,6 @@ struct wm8350 {
621 struct mutex auxadc_mutex; 626 struct mutex auxadc_mutex;
622 627
623 /* Interrupt handling */ 628 /* Interrupt handling */
624 struct work_struct irq_work;
625 struct mutex irq_mutex; /* IRQ table mutex */ 629 struct mutex irq_mutex; /* IRQ table mutex */
626 struct wm8350_irq irq[WM8350_NUM_IRQ]; 630 struct wm8350_irq irq[WM8350_NUM_IRQ];
627 int chip_irq; 631 int chip_irq;
@@ -629,6 +633,7 @@ struct wm8350 {
629 /* Client devices */ 633 /* Client devices */
630 struct wm8350_codec codec; 634 struct wm8350_codec codec;
631 struct wm8350_gpio gpio; 635 struct wm8350_gpio gpio;
636 struct wm8350_hwmon hwmon;
632 struct wm8350_pmic pmic; 637 struct wm8350_pmic pmic;
633 struct wm8350_power power; 638 struct wm8350_power power;
634 struct wm8350_rtc rtc; 639 struct wm8350_rtc rtc;
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 225f733e7533..ce1be708ca16 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -193,6 +193,8 @@ void *rdev_get_drvdata(struct regulator_dev *rdev);
193struct device *rdev_get_dev(struct regulator_dev *rdev); 193struct device *rdev_get_dev(struct regulator_dev *rdev);
194int rdev_get_id(struct regulator_dev *rdev); 194int rdev_get_id(struct regulator_dev *rdev);
195 195
196int regulator_mode_to_status(unsigned int);
197
196void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); 198void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
197 199
198#endif 200#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 01:41:00 -0500