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authorStephane Eranian <eranian@hpl.hp.com>2006-12-06 20:14:02 -0500
committerAndi Kleen <andi@basil.nowhere.org>2006-12-06 20:14:02 -0500
commitbb0d977ed42c79ed709c79dbab4ff2159941eb2a (patch)
treeef0af6c23743b49c263db36f389433c9a7155367 /include
parent86efef50cfff9905c4e4ec64f3d3d3b299226674 (diff)
[PATCH] i386: add Intel Core related PMU MSRs
- add Intel Precise-Event Based sampling (PEBS) related MSR - add Intel Data Save (DS) Area related MSR - add Intel Core microarchitecure performance counter MSRs Signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include')
-rw-r--r--include/asm-i386/msr.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index 62b76cd96957..1820d9d73af3 100644
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -141,6 +141,10 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
141#define MSR_IA32_MC0_ADDR 0x402 141#define MSR_IA32_MC0_ADDR 0x402
142#define MSR_IA32_MC0_MISC 0x403 142#define MSR_IA32_MC0_MISC 0x403
143 143
144#define MSR_IA32_PEBS_ENABLE 0x3f1
145#define MSR_IA32_DS_AREA 0x600
146#define MSR_IA32_PERF_CAPABILITIES 0x345
147
144/* Pentium IV performance counter MSRs */ 148/* Pentium IV performance counter MSRs */
145#define MSR_P4_BPU_PERFCTR0 0x300 149#define MSR_P4_BPU_PERFCTR0 0x300
146#define MSR_P4_BPU_PERFCTR1 0x301 150#define MSR_P4_BPU_PERFCTR1 0x301
@@ -284,4 +288,13 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
284#define MSR_TMTA_LRTI_READOUT 0x80868018 288#define MSR_TMTA_LRTI_READOUT 0x80868018
285#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 289#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
286 290
291/* Intel Core-based CPU performance counters */
292#define MSR_CORE_PERF_FIXED_CTR0 0x309
293#define MSR_CORE_PERF_FIXED_CTR1 0x30a
294#define MSR_CORE_PERF_FIXED_CTR2 0x30b
295#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
296#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
297#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
298#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
299
287#endif /* __ASM_MSR_H */ 300#endif /* __ASM_MSR_H */