diff options
author | Bjorn Helgaas <bjorn.helgaas@hp.com> | 2006-01-30 18:32:31 -0500 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2006-02-02 16:25:54 -0500 |
commit | a58786917ce23c2a26c3e099c3cdba32a35eeceb (patch) | |
tree | 4740de51febbe16934d24d94cb80432a7547cb26 /include | |
parent | af14aca90e0cdfccd71f9947c45b6ea2cf321dcb (diff) |
[IA64] avoid broken SAL_CACHE_FLUSH implementations
If SAL_CACHE_FLUSH drops interrupts, complain about it and fall back to
using PAL_CACHE_FLUSH instead.
This is to work around a defect in HP rx5670 firmware: when an interrupt
occurs during SAL_CACHE_FLUSH, SAL drops the interrupt but leaves it marked
"in-service", which leaves the interrupt (and others of equal or lower
priority) masked.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-ia64/processor.h | 17 | ||||
-rw-r--r-- | include/asm-ia64/sal.h | 10 |
2 files changed, 18 insertions, 9 deletions
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 09b99029ac1a..23c8e1be1911 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h | |||
@@ -559,6 +559,23 @@ ia64_eoi (void) | |||
559 | 559 | ||
560 | #define cpu_relax() ia64_hint(ia64_hint_pause) | 560 | #define cpu_relax() ia64_hint(ia64_hint_pause) |
561 | 561 | ||
562 | static inline int | ||
563 | ia64_get_irr(unsigned int vector) | ||
564 | { | ||
565 | unsigned int reg = vector / 64; | ||
566 | unsigned int bit = vector % 64; | ||
567 | u64 irr; | ||
568 | |||
569 | switch (reg) { | ||
570 | case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break; | ||
571 | case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break; | ||
572 | case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break; | ||
573 | case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break; | ||
574 | } | ||
575 | |||
576 | return test_bit(bit, &irr); | ||
577 | } | ||
578 | |||
562 | static inline void | 579 | static inline void |
563 | ia64_set_lrr0 (unsigned long val) | 580 | ia64_set_lrr0 (unsigned long val) |
564 | { | 581 | { |
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index 313cad0628d0..0b210abbe003 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h | |||
@@ -658,15 +658,7 @@ ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second, | |||
658 | return isrv.status; | 658 | return isrv.status; |
659 | } | 659 | } |
660 | 660 | ||
661 | /* Flush all the processor and platform level instruction and/or data caches */ | 661 | extern s64 ia64_sal_cache_flush (u64 cache_type); |
662 | static inline s64 | ||
663 | ia64_sal_cache_flush (u64 cache_type) | ||
664 | { | ||
665 | struct ia64_sal_retval isrv; | ||
666 | SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0); | ||
667 | return isrv.status; | ||
668 | } | ||
669 | |||
670 | 662 | ||
671 | /* Initialize all the processor and platform level instruction and data caches */ | 663 | /* Initialize all the processor and platform level instruction and data caches */ |
672 | static inline s64 | 664 | static inline s64 |