Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6

* 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6: (231 commits) [PATCH] i386: Don't delete cpu_devs data to identify different x86 types in late_initcall [PATCH] i386: type may be unused [PATCH] i386: Some additional chipset register values validation. [PATCH] i386: Add missing !X86_PAE dependincy to the 2G/2G split. [PATCH] x86-64: Don't exclude asm-offsets.c in Documentation/dontdiff [PATCH] i386: avoid redundant preempt_disable in __unlazy_fpu [PATCH] i386: white space fixes in i387.h [PATCH] i386: Drop noisy e820 debugging printks [PATCH] x86-64: Fix allnoconfig error in genapic_flat.c [PATCH] x86-64: Shut up warnings for vfat compat ioctls on other file systems [PATCH] x86-64: Share identical video.S between i386 and x86-64 [PATCH] x86-64: Remove CONFIG_REORDER [PATCH] x86-64: Print type and size correctly for unknown compat ioctls [PATCH] i386: Remove copy_*_user BUG_ONs for (size < 0) [PATCH] i386: Little cleanups in smpboot.c [PATCH] x86-64: Don't enable NUMA for a single node in K8 NUMA scanning [PATCH] x86: Use RDTSCP for synchronous get_cycles if possible [PATCH] i386: Add X86_FEATURE_RDTSCP [PATCH] i386: Implement X86_FEATURE_SYNC_RDTSC on i386 [PATCH] i386: Implement alternative_io for i386 ... Fix up trivial conflict in include/linux/highmem.h manually. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
author: Linus Torvalds <torvalds@woody.linux-foundation.org> 2007-05-05 17:55:20 -0400
committer: Linus Torvalds <torvalds@woody.linux-foundation.org> 2007-05-05 17:55:20 -0400
commit: ea62ccd00fd0b6720b033adfc9984f31130ce195 (patch)
tree: 9837b797b2466fffcb0af96c388b06eae9c3df18 /include
parent: 886a0768affe9a32f18c45f8e1393bca9ece5392 (diff)
parent: 35060b6a9a4e1c89bc6fbea61090e302dbc61847 (diff)
125 files changed, 2421 insertions, 1795 deletions
diff --git a/include/asm-alpha/mmu_context.h b/include/asm-alpha/mmu_context.h
index fe249e9d3360..0bd7bd2ccb90 100644
--- a/include/asm-alpha/mmu_context.h
+++ b/include/asm-alpha/mmu_context.h
@@ -10,6 +10,7 @@
 #include <asm/system.h>
 #include <asm/machvec.h>
 #include <asm/compiler.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * Force a context reload. This is needed when we change the page
diff --git a/include/asm-alpha/percpu.h b/include/asm-alpha/percpu.h
index 651ebb141b24..48348fe34c19 100644
--- a/include/asm-alpha/percpu.h
+++ b/include/asm-alpha/percpu.h
@@ -1,20 +1,6 @@
 #ifndef __ALPHA_PERCPU_H
 #define __ALPHA_PERCPU_H
-/*
- * Increase the per cpu area for Alpha so that
- * modules using percpu area can load.
- */
-#ifdef CONFIG_MODULES
-# define PERCPU_MODULE_RESERVE 8192
-#else
-# define PERCPU_MODULE_RESERVE 0
-#endif
-#define PERCPU_ENOUGH_ROOM \
-        (ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES) + \
-         PERCPU_MODULE_RESERVE)
 #include <asm-generic/percpu.h>
 #endif /* __ALPHA_PERCPU_H */
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index d1a65b1edcaa..f8755c818b54 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -16,6 +16,7 @@
 #include <linux/compiler.h>
 #include <asm/cacheflush.h>
 #include <asm/proc-fns.h>
+#include <asm-generic/mm_hooks.h>
 void __check_kvm_seq(struct mm_struct *mm);
diff --git a/include/asm-arm26/mmu_context.h b/include/asm-arm26/mmu_context.h
index 1a929bfe5c3a..16c821f81b8d 100644
--- a/include/asm-arm26/mmu_context.h
+++ b/include/asm-arm26/mmu_context.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARM_MMU_CONTEXT_H
 #define __ASM_ARM_MMU_CONTEXT_H
+#include <asm-generic/mm_hooks.h>
 #define init_new_context(tsk,mm)        0
 #define destroy_context(mm)             do { } while(0)
diff --git a/include/asm-avr32/mmu_context.h b/include/asm-avr32/mmu_context.h
index 31add1ae8089..c37c391faef6 100644
--- a/include/asm-avr32/mmu_context.h
+++ b/include/asm-avr32/mmu_context.h
@@ -15,6 +15,7 @@
 #include <asm/tlbflush.h>
 #include <asm/pgalloc.h>
 #include <asm/sysreg.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * The MMU "context" consists of two things:
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h
index e6e659dc757b..72ba08dcfd18 100644
--- a/include/asm-cris/mmu_context.h
+++ b/include/asm-cris/mmu_context.h
@@ -1,6 +1,8 @@
 #ifndef __CRIS_MMU_CONTEXT_H
 #define __CRIS_MMU_CONTEXT_H
+#include <asm-generic/mm_hooks.h>
 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 extern void get_mmu_context(struct mm_struct *mm);
 extern void destroy_context(struct mm_struct *mm);
diff --git a/include/asm-frv/mmu_context.h b/include/asm-frv/mmu_context.h
index 72edcaaccd5d..c7daa395156a 100644
--- a/include/asm-frv/mmu_context.h
+++ b/include/asm-frv/mmu_context.h
@@ -15,6 +15,7 @@
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-generic/mm_hooks.h b/include/asm-generic/mm_hooks.h
new file mode 100644
index 000000000000..67dea8123683
--- /dev/null
+++ b/include/asm-generic/mm_hooks.h
@@ -0,0 +1,18 @@
+/*
+ * Define generic no-op hooks for arch_dup_mmap and arch_exit_mmap, to
+ * be included in asm-FOO/mmu_context.h for any arch FOO which doesn't
+ * need to hook these.
+ */
+#ifndef _ASM_GENERIC_MM_HOOKS_H
+#define _ASM_GENERIC_MM_HOOKS_H
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+}
+static inline void arch_exit_mmap(struct mm_struct *mm)
+{
+}
+#endif  /* _ASM_GENERIC_MM_HOOKS_H */
diff --git a/include/asm-generic/percpu.h b/include/asm-generic/percpu.h
index 196376262240..d984a9041436 100644
--- a/include/asm-generic/percpu.h
+++ b/include/asm-generic/percpu.h
@@ -1,6 +1,7 @@
 #ifndef _ASM_GENERIC_PERCPU_H_
 #define _ASM_GENERIC_PERCPU_H_
 #include <linux/compiler.h>
+#include <linux/threads.h>
 #define __GENERIC_PER_CPU
 #ifdef CONFIG_SMP
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 9fcc8d9fbb14..f3806a74c478 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -208,7 +208,7 @@
        }
 #define NOTES                                                           \
-                .notes : { *(.note.*) } :note
+        .notes : { *(.note.*) } :note
 #define INITCALLS                                                       \
        *(.initcall0.init)                                              \
diff --git a/include/asm-h8300/mmu_context.h b/include/asm-h8300/mmu_context.h
index 5c165f7bee0e..f44b730da54d 100644
--- a/include/asm-h8300/mmu_context.h
+++ b/include/asm-h8300/mmu_context.h
@@ -4,6 +4,7 @@
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-i386/Kbuild b/include/asm-i386/Kbuild
index 5ae93afc67e1..cbf6e8f1087b 100644
--- a/include/asm-i386/Kbuild
+++ b/include/asm-i386/Kbuild
@@ -3,8 +3,10 @@ include include/asm-generic/Kbuild.asm
 header-y += boot.h
 header-y += debugreg.h
 header-y += ldt.h
+header-y += msr-index.h
 header-y += ptrace-abi.h
 header-y += ucontext.h
+unifdef-y += msr.h
 unifdef-y += mtrr.h
 unifdef-y += vm86.h
diff --git a/include/asm-i386/alternative.h b/include/asm-i386/alternative.h
index b8fa9557c532..0f70b379b029 100644
--- a/include/asm-i386/alternative.h
+++ b/include/asm-i386/alternative.h
@@ -1,8 +1,6 @@
 #ifndef _I386_ALTERNATIVE_H
 #define _I386_ALTERNATIVE_H
-#ifdef __KERNEL__
 #include <asm/types.h>
 #include <linux/stddef.h>
 #include <linux/types.h>
@@ -16,6 +14,7 @@ struct alt_instr {
        u8  pad;
 };
+extern void alternative_instructions(void);
 extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
 struct module;
@@ -31,9 +30,7 @@ static inline void alternatives_smp_module_add(struct module *mod, char *name,
                                        void *text, void *text_end) {}
 static inline void alternatives_smp_module_del(struct module *mod) {}
 static inline void alternatives_smp_switch(int smp) {}
-#endif
+#endif  /* CONFIG_SMP */
-#endif
 /*
 * Alternative instructions for different CPU types or capabilities.
@@ -85,6 +82,21 @@ static inline void alternatives_smp_switch(int smp) {}
                      "663:\n\t" newinstr "\n664:\n"   /* replacement */\
                      ".previous" :: "i" (feature), ##input)
+/* Like alternative_input, but with a single output argument */
+#define alternative_io(oldinstr, newinstr, feature, output, input...) \
+        asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
+                      ".section .altinstructions,\"a\"\n"               \
+                      "  .align 4\n"                                    \
+                      "  .long 661b\n"            /* label */           \
+                      "  .long 663f\n"            /* new instruction */ \
+                      "  .byte %c[feat]\n"        /* feature bit */     \
+                      "  .byte 662b-661b\n"       /* sourcelen */       \
+                      "  .byte 664f-663f\n"       /* replacementlen */  \
+                      ".previous\n"                                     \
+                      ".section .altinstr_replacement,\"ax\"\n"         \
+                      "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
+                      ".previous" : output : [feat] "i" (feature), ##input)
 /*
 * Alternative inline assembly for SMP.
 *
@@ -118,15 +130,17 @@ static inline void alternatives_smp_switch(int smp) {}
 #define LOCK_PREFIX ""
 #endif
-struct paravirt_patch;
+struct paravirt_patch_site;
 #ifdef CONFIG_PARAVIRT
-void apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end);
+void apply_paravirt(struct paravirt_patch_site *start,
+                    struct paravirt_patch_site *end);
 #else
 static inline void
-apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end)
+apply_paravirt(struct paravirt_patch_site *start,
+               struct paravirt_patch_site *end)
 {}
-#define __start_parainstructions NULL
+#define __parainstructions      NULL
-#define __stop_parainstructions NULL
+#define __parainstructions_end  NULL
 #endif
 #endif /* _I386_ALTERNATIVE_H */
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h
index a19810a08ae9..1e8f6f252dd3 100644
--- a/include/asm-i386/apic.h
+++ b/include/asm-i386/apic.h
@@ -2,6 +2,7 @@
 #define __ASM_APIC_H
 #include <linux/pm.h>
+#include <linux/delay.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
 #include <asm/processor.h>
@@ -64,12 +65,8 @@ static __inline fastcall unsigned long native_apic_read(unsigned long reg)
        return *((volatile unsigned long *)(APIC_BASE+reg));
 }
-static __inline__ void apic_wait_icr_idle(void)
+void apic_wait_icr_idle(void);
-{
+unsigned long safe_apic_wait_icr_idle(void);
-        while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
-                cpu_relax();
-}
 int get_physical_broadcast(void);
 #ifdef CONFIG_X86_GOOD_APIC
diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h
index c90c7c499302..d28979ff73be 100644
--- a/include/asm-i386/bugs.h
+++ b/include/asm-i386/bugs.h
@@ -1,198 +1,12 @@
 /*
- *  include/asm-i386/bugs.h
- *
- *  Copyright (C) 1994  Linus Torvalds
- *
- *  Cyrix stuff, June 1998 by:
- *      - Rafael R. Reilova (moved everything from head.S),
- *        <rreilova@ececs.uc.edu>
- *      - Channing Corn (tests & fixes),
- *      - Andrew D. Balsa (code cleanup).
- */
-/*
 * This is included by init/main.c to check for architecture-dependent bugs.
 *
 * Needs:
 *      void check_bugs(void);
 */
+#ifndef _ASM_I386_BUG_H
+#define _ASM_I386_BUG_H
-#include <linux/init.h>
+void check_bugs(void);
-#include <asm/processor.h>
-#include <asm/i387.h>
-#include <asm/msr.h>
-#include <asm/paravirt.h>
-static int __init no_halt(char *s)
-{
-        boot_cpu_data.hlt_works_ok = 0;
-        return 1;
-}
-__setup("no-hlt", no_halt);
-static int __init mca_pentium(char *s)
-{
-        mca_pentium_flag = 1;
-        return 1;
-}
-__setup("mca-pentium", mca_pentium);
-static int __init no_387(char *s)
-{
-        boot_cpu_data.hard_math = 0;
-        write_cr0(0xE | read_cr0());
-        return 1;
-}
-__setup("no387", no_387);
-static double __initdata x = 4195835.0;
-static double __initdata y = 3145727.0;
-/*
- * This used to check for exceptions.. 
- * However, it turns out that to support that,
- * the XMM trap handlers basically had to
- * be buggy. So let's have a correct XMM trap
- * handler, and forget about printing out
- * some status at boot.
- *
- * We should really only care about bugs here
- * anyway. Not features.
- */
-static void __init check_fpu(void)
-{
-        if (!boot_cpu_data.hard_math) {
-#ifndef CONFIG_MATH_EMULATION
-                printk(KERN_EMERG "No coprocessor found and no math emulation present.\n");
-                printk(KERN_EMERG "Giving up.\n");
-                for (;;) ;
-#endif
-                return;
-        }
-/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */
-        /* Test for the divl bug.. */
-        __asm__("fninit\n\t"
-                "fldl %1\n\t"
-                "fdivl %2\n\t"
-                "fmull %2\n\t"
-                "fldl %1\n\t"
-                "fsubp %%st,%%st(1)\n\t"
-                "fistpl %0\n\t"
-                "fwait\n\t"
-                "fninit"
-                : "=m" (*&boot_cpu_data.fdiv_bug)
-                : "m" (*&x), "m" (*&y));
-        if (boot_cpu_data.fdiv_bug)
-                printk("Hmm, FPU with FDIV bug.\n");
-}
-static void __init check_hlt(void)
-{
-        if (paravirt_enabled())
-                return;
-        printk(KERN_INFO "Checking 'hlt' instruction... ");
-        if (!boot_cpu_data.hlt_works_ok) {
-                printk("disabled\n");
-                return;
-        }
-        halt();
-        halt();
-        halt();
-        halt();
-        printk("OK.\n");
-}
-/*
- *      Most 386 processors have a bug where a POPAD can lock the 
- *      machine even from user space.
- */
- 
-static void __init check_popad(void)
-{
-#ifndef CONFIG_X86_POPAD_OK
-        int res, inp = (int) &res;
-        printk(KERN_INFO "Checking for popad bug... ");
-        __asm__ __volatile__( 
-          "movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx "
-          : "=&a" (res)
-          : "d" (inp)
-          : "ecx", "edi" );
-        /* If this fails, it means that any user program may lock the CPU hard. Too bad. */
-        if (res != 12345678) printk( "Buggy.\n" );
-                        else printk( "OK.\n" );
-#endif
-}
-/*
- * Check whether we are able to run this kernel safely on SMP.
- *
- * - In order to run on a i386, we need to be compiled for i386
- *   (for due to lack of "invlpg" and working WP on a i386)
- * - In order to run on anything without a TSC, we need to be
- *   compiled for a i486.
- * - In order to support the local APIC on a buggy Pentium machine,
- *   we need to be compiled with CONFIG_X86_GOOD_APIC disabled,
- *   which happens implicitly if compiled for a Pentium or lower
- *   (unless an advanced selection of CPU features is used) as an
- *   otherwise config implies a properly working local APIC without
- *   the need to do extra reads from the APIC.
-*/
-static void __init check_config(void)
-{
-/*
- * We'd better not be a i386 if we're configured to use some
- * i486+ only features! (WP works in supervisor mode and the
- * new "invlpg" and "bswap" instructions)
- */
-#if defined(CONFIG_X86_WP_WORKS_OK) || defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_BSWAP)
-        if (boot_cpu_data.x86 == 3)
-                panic("Kernel requires i486+ for 'invlpg' and other features");
-#endif
-/*
- * If we configured ourselves for a TSC, we'd better have one!
- */
-#ifdef CONFIG_X86_TSC
-        if (!cpu_has_tsc && !tsc_disable)
-                panic("Kernel compiled for Pentium+, requires TSC feature!");
-#endif
-/*
- * If we were told we had a good local APIC, check for buggy Pentia,
- * i.e. all B steppings and the C2 stepping of P54C when using their
- * integrated APIC (see 11AP erratum in "Pentium Processor
- * Specification Update").
- */
-#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_GOOD_APIC)
-        if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL
-            && cpu_has_apic
-            && boot_cpu_data.x86 == 5
-            && boot_cpu_data.x86_model == 2
-            && (boot_cpu_data.x86_mask < 6 || boot_cpu_data.x86_mask == 11))
-                panic("Kernel compiled for PMMX+, assumes a local APIC without the read-before-write bug!");
-#endif
-}
-extern void alternative_instructions(void);
-static void __init check_bugs(void)
+#endif  /* _ASM_I386_BUG_H */
-{
-        identify_cpu(&boot_cpu_data);
-#ifndef CONFIG_SMP
-        printk("CPU: ");
-        print_cpu_info(&boot_cpu_data);
-#endif
-        check_config();
-        check_fpu();
-        check_hlt();
-        check_popad();
-        init_utsname()->machine[1] = '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
-        alternative_instructions(); 
-}
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index d1b8e4ab6c1a..f514e906643a 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -7,7 +7,10 @@
 #ifndef __ASM_I386_CPUFEATURE_H
 #define __ASM_I386_CPUFEATURE_H
+#ifndef __ASSEMBLY__
 #include <linux/bitops.h>
+#endif
+#include <asm/required-features.h>
 #define NCAPINTS        7       /* N 32-bit words worth of info */
@@ -49,6 +52,7 @@
 #define X86_FEATURE_MP          (1*32+19) /* MP Capable. */
 #define X86_FEATURE_NX          (1*32+20) /* Execute Disable */
 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
 #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
 #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
 #define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
@@ -76,6 +80,7 @@
 #define X86_FEATURE_PEBS        (3*32+12)  /* Precise-Event Based Sampling */
 #define X86_FEATURE_BTS         (3*32+13)  /* Branch Trace Store */
 #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */
+#define X86_FEATURE_SYNC_RDTSC  (3*32+15)  /* RDTSC synchronizes the CPU */
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -103,8 +108,12 @@
 #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
 #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
-#define cpu_has(c, bit)         test_bit(bit, (c)->x86_capability)
+#define cpu_has(c, bit)                                 \
-#define boot_cpu_has(bit)       test_bit(bit, boot_cpu_data.x86_capability)
+        ((__builtin_constant_p(bit) && (bit) < 32 &&    \
+                (1UL << (bit)) & REQUIRED_MASK1) ?      \
+                1 :                                     \
+        test_bit(bit, (c)->x86_capability))
+#define boot_cpu_has(bit)       cpu_has(&boot_cpu_data, bit)
 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
 #define cpu_has_vme             boot_cpu_has(X86_FEATURE_VME)
diff --git a/include/asm-i386/current.h b/include/asm-i386/current.h
index 5252ee0f6d7a..d35248539912 100644
--- a/include/asm-i386/current.h
+++ b/include/asm-i386/current.h
@@ -1,14 +1,15 @@
 #ifndef _I386_CURRENT_H
 #define _I386_CURRENT_H
-#include <asm/pda.h>
 #include <linux/compiler.h>
+#include <asm/percpu.h>
 struct task_struct;
+DECLARE_PER_CPU(struct task_struct *, current_task);
 static __always_inline struct task_struct *get_current(void)
 {
-        return read_pda(pcurrent);
+        return x86_read_percpu(current_task);
 }
 
 #define current get_current()
diff --git a/include/asm-i386/desc.h b/include/asm-i386/desc.h
index 050831f34f71..c547403f341d 100644
--- a/include/asm-i386/desc.h
+++ b/include/asm-i386/desc.h
@@ -12,23 +12,24 @@
 #include <asm/mmu.h>
-extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
 struct Xgt_desc_struct {
        unsigned short size;
        unsigned long address __attribute__((packed));
        unsigned short pad;
 } __attribute__ ((packed));
-extern struct Xgt_desc_struct idt_descr;
+struct gdt_page
-DECLARE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
+{
-extern struct Xgt_desc_struct early_gdt_descr;
+        struct desc_struct gdt[GDT_ENTRIES];
+} __attribute__((aligned(PAGE_SIZE)));
+DECLARE_PER_CPU(struct gdt_page, gdt_page);
 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
 {
-        return (struct desc_struct *)per_cpu(cpu_gdt_descr, cpu).address;
+        return per_cpu(gdt_page, cpu).gdt;
 }
+extern struct Xgt_desc_struct idt_descr;
 extern struct desc_struct idt_table[];
 extern void set_intr_gate(unsigned int irq, void * addr);
@@ -58,45 +59,33 @@ static inline void pack_gate(__u32 *a, __u32 *b,
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
-#define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8))
+#define load_TR_desc() native_load_tr_desc()
+#define load_gdt(dtr) native_load_gdt(dtr)
-#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr))
+#define load_idt(dtr) native_load_idt(dtr)
-#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr))
 #define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
 #define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
+#define store_gdt(dtr) native_store_gdt(dtr)
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
+#define store_idt(dtr) native_store_idt(dtr)
-#define store_tr(tr) __asm__ ("str %0":"=m" (tr))
+#define store_tr(tr) (tr = native_store_tr())
 #define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))
-#if TLS_SIZE != 24
+#define load_TLS(t, cpu) native_load_tls(t, cpu)
-# error update this code.
+#define set_ldt native_set_ldt
-#endif
-static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
-{
-#define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
-        C(0); C(1); C(2);
-#undef C
-}
 #define write_ldt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
 #define write_gdt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
 #define write_idt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
+#endif
-static inline void write_dt_entry(void *dt, int entry, __u32 entry_a, __u32 entry_b)
+static inline void write_dt_entry(struct desc_struct *dt,
+                                  int entry, u32 entry_low, u32 entry_high)
 {
-        __u32 *lp = (__u32 *)((char *)dt + entry*8);
+        dt[entry].a = entry_low;
-        *lp = entry_a;
+        dt[entry].b = entry_high;
-        *(lp+1) = entry_b;
 }
-#define set_ldt native_set_ldt
+static inline void native_set_ldt(const void *addr, unsigned int entries)
-#endif /* CONFIG_PARAVIRT */
-static inline fastcall void native_set_ldt(const void *addr,
-                                           unsigned int entries)
 {
        if (likely(entries == 0))
                __asm__ __volatile__("lldt %w0"::"q" (0));
@@ -112,6 +101,48 @@ static inline fastcall void native_set_ldt(const void *addr,
        }
 }
+static inline void native_load_tr_desc(void)
+{
+        asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
+}
+static inline void native_load_gdt(const struct Xgt_desc_struct *dtr)
+{
+        asm volatile("lgdt %0"::"m" (*dtr));
+}
+static inline void native_load_idt(const struct Xgt_desc_struct *dtr)
+{
+        asm volatile("lidt %0"::"m" (*dtr));
+}
+static inline void native_store_gdt(struct Xgt_desc_struct *dtr)
+{
+        asm ("sgdt %0":"=m" (*dtr));
+}
+static inline void native_store_idt(struct Xgt_desc_struct *dtr)
+{
+        asm ("sidt %0":"=m" (*dtr));
+}
+static inline unsigned long native_store_tr(void)
+{
+        unsigned long tr;
+        asm ("str %0":"=r" (tr));
+        return tr;
+}
+static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
+{
+        unsigned int i;
+        struct desc_struct *gdt = get_cpu_gdt_table(cpu);
+        for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
+                gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
+}
 static inline void _set_gate(int gate, unsigned int type, void *addr, unsigned short seg)
 {
        __u32 a, b;
diff --git a/include/asm-i386/e820.h b/include/asm-i386/e820.h
index c5b8fc6109d6..096a2a8eb1da 100644
--- a/include/asm-i386/e820.h
+++ b/include/asm-i386/e820.h
@@ -38,6 +38,7 @@ extern struct e820map e820;
 extern int e820_all_mapped(unsigned long start, unsigned long end,
                           unsigned type);
+extern int e820_any_mapped(u64 start, u64 end, unsigned type);
 extern void find_max_pfn(void);
 extern void register_bootmem_low_pages(unsigned long max_low_pfn);
 extern void e820_register_memory(void);
diff --git a/include/asm-i386/elf.h b/include/asm-i386/elf.h
index 952b3ee3c9bb..d304ab4161ff 100644
--- a/include/asm-i386/elf.h
+++ b/include/asm-i386/elf.h
@@ -133,39 +133,31 @@ extern int dump_task_extended_fpu (struct task_struct *, struct user_fxsr_struct
 #define ELF_CORE_COPY_XFPREGS(tsk, elf_xfpregs) dump_task_extended_fpu(tsk, elf_xfpregs)
 #define VDSO_HIGH_BASE          (__fix_to_virt(FIX_VDSO))
-#define VDSO_BASE               ((unsigned long)current->mm->context.vdso)
+#define VDSO_CURRENT_BASE       ((unsigned long)current->mm->context.vdso)
+#define VDSO_PRELINK            0
-#ifdef CONFIG_COMPAT_VDSO
-# define VDSO_COMPAT_BASE       VDSO_HIGH_BASE
-# define VDSO_PRELINK           VDSO_HIGH_BASE
-#else
-# define VDSO_COMPAT_BASE       VDSO_BASE
-# define VDSO_PRELINK           0
-#endif
 #define VDSO_SYM(x) \
-                (VDSO_COMPAT_BASE + (unsigned long)(x) - VDSO_PRELINK)
+                (VDSO_CURRENT_BASE + (unsigned long)(x) - VDSO_PRELINK)
 #define VDSO_HIGH_EHDR          ((const struct elfhdr *) VDSO_HIGH_BASE)
-#define VDSO_EHDR               ((const struct elfhdr *) VDSO_COMPAT_BASE)
+#define VDSO_EHDR               ((const struct elfhdr *) VDSO_CURRENT_BASE)
 extern void __kernel_vsyscall;
 #define VDSO_ENTRY              VDSO_SYM(&__kernel_vsyscall)
-#ifndef CONFIG_COMPAT_VDSO
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
 struct linux_binprm;
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                       int executable_stack);
-#endif
 extern unsigned int vdso_enabled;
-#define ARCH_DLINFO                                             \
+#define ARCH_DLINFO                                                     \
-do if (vdso_enabled) {                                          \
+do if (vdso_enabled) {                                                  \
-                NEW_AUX_ENT(AT_SYSINFO, VDSO_ENTRY);            \
+                NEW_AUX_ENT(AT_SYSINFO, VDSO_ENTRY);                    \
-                NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_COMPAT_BASE); \
+                NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_CURRENT_BASE);        \
 } while (0)
 #endif
diff --git a/include/asm-i386/fixmap.h b/include/asm-i386/fixmap.h
index 3e9f610c35df..80ea052ee3a4 100644
--- a/include/asm-i386/fixmap.h
+++ b/include/asm-i386/fixmap.h
@@ -19,13 +19,9 @@
 * Leave one empty page between vmalloc'ed areas and
 * the start of the fixmap.
 */
-#ifndef CONFIG_COMPAT_VDSO
 extern unsigned long __FIXADDR_TOP;
-#else
+#define FIXADDR_USER_START     __fix_to_virt(FIX_VDSO)
-#define __FIXADDR_TOP  0xfffff000
+#define FIXADDR_USER_END       __fix_to_virt(FIX_VDSO - 1)
-#define FIXADDR_USER_START      __fix_to_virt(FIX_VDSO)
-#define FIXADDR_USER_END        __fix_to_virt(FIX_VDSO - 1)
-#endif
 #ifndef __ASSEMBLY__
 #include <linux/kernel.h>
@@ -88,6 +84,9 @@ enum fixed_addresses {
 #ifdef CONFIG_PCI_MMCONFIG
        FIX_PCIE_MCFG,
 #endif
+#ifdef CONFIG_PARAVIRT
+        FIX_PARAVIRT_BOOTMAP,
+#endif
        __end_of_permanent_fixed_addresses,
        /* temporary boot-time mappings, used before ioremap() is functional */
 #define NR_FIX_BTMAPS   16
diff --git a/include/asm-i386/genapic.h b/include/asm-i386/genapic.h
index fd2be593b06e..33e3ffe1766c 100644
--- a/include/asm-i386/genapic.h
+++ b/include/asm-i386/genapic.h
@@ -36,7 +36,7 @@ struct genapic {
        void (*init_apic_ldr)(void);
        physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
-        void (*clustered_apic_check)(void);
+        void (*setup_apic_routing)(void);
        int (*multi_timer_check)(int apic, int irq);
        int (*apicid_to_node)(int logical_apicid); 
        int (*cpu_to_logical_apicid)(int cpu);
@@ -99,7 +99,7 @@ struct genapic {
        APICFUNC(check_apicid_present) \
        APICFUNC(init_apic_ldr) \
        APICFUNC(ioapic_phys_id_map) \
-        APICFUNC(clustered_apic_check) \
+        APICFUNC(setup_apic_routing) \
        APICFUNC(multi_timer_check) \
        APICFUNC(apicid_to_node) \
        APICFUNC(cpu_to_logical_apicid) \
@@ -122,6 +122,6 @@ struct genapic {
        APICFUNC(phys_pkg_id) \
        }
-extern struct genapic *genapic, apic_default;
+extern struct genapic *genapic;
 #endif
diff --git a/include/asm-i386/highmem.h b/include/asm-i386/highmem.h
index e9a34ebc25d5..13cdcd66fff2 100644
--- a/include/asm-i386/highmem.h
+++ b/include/asm-i386/highmem.h
@@ -24,6 +24,7 @@
 #include <linux/threads.h>
 #include <asm/kmap_types.h>
 #include <asm/tlbflush.h>
+#include <asm/paravirt.h>
 /* declarations for highmem.c */
 extern unsigned long highstart_pfn, highend_pfn;
@@ -67,11 +68,16 @@ extern void FASTCALL(kunmap_high(struct page *page));
 void *kmap(struct page *page);
 void kunmap(struct page *page);
+void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot);
 void *kmap_atomic(struct page *page, enum km_type type);
 void kunmap_atomic(void *kvaddr, enum km_type type);
 void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
 struct page *kmap_atomic_to_page(void *ptr);
+#ifndef CONFIG_PARAVIRT
+#define kmap_atomic_pte(page, type)     kmap_atomic(page, type)
+#endif
 #define flush_cache_kmaps()     do { } while (0)
 #endif /* __KERNEL__ */
diff --git a/include/asm-i386/hpet.h b/include/asm-i386/hpet.h
index fc03cf9de5c4..dddeedf504b7 100644
--- a/include/asm-i386/hpet.h
+++ b/include/asm-i386/hpet.h
@@ -28,8 +28,6 @@
 #include <linux/timex.h>
-#include <asm/fixmap.h>
 /*
 * Documentation on HPET can be found at:
 *      http://www.intel.com/ial/home/sp/pcmmspec.htm
diff --git a/include/asm-i386/i387.h b/include/asm-i386/i387.h
index 434936c732d6..cdd1e248e3b4 100644
--- a/include/asm-i386/i387.h
+++ b/include/asm-i386/i387.h
@@ -74,17 +74,18 @@ static inline void __save_init_fpu( struct task_struct *tsk )
        task_thread_info(tsk)->status &= ~TS_USEDFPU;
 }
-#define __unlazy_fpu( tsk ) do { \
+#define __unlazy_fpu( tsk ) do {                                \
-        if (task_thread_info(tsk)->status & TS_USEDFPU) \
+        if (task_thread_info(tsk)->status & TS_USEDFPU) {       \
-                save_init_fpu( tsk );                   \
+                __save_init_fpu(tsk);                           \
-        else                                            \
+                stts();                                         \
-                tsk->fpu_counter = 0;                   \
+        } else                                                  \
+                tsk->fpu_counter = 0;                           \
 } while (0)
 #define __clear_fpu( tsk )                                      \
 do {                                                            \
-        if (task_thread_info(tsk)->status & TS_USEDFPU) {               \
+        if (task_thread_info(tsk)->status & TS_USEDFPU) {       \
-                asm volatile("fnclex ; fwait");                         \
+                asm volatile("fnclex ; fwait");                 \
                task_thread_info(tsk)->status &= ~TS_USEDFPU;   \
                stts();                                         \
        }                                                       \
@@ -113,7 +114,7 @@ static inline void save_init_fpu( struct task_struct *tsk )
        __clear_fpu( tsk );     \
        preempt_enable();       \
 } while (0)
-                                        \
 /*
 * FPU state interaction...
 */
diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h
index 59fe616933c4..e797586a5bfc 100644
--- a/include/asm-i386/io.h
+++ b/include/asm-i386/io.h
@@ -250,19 +250,22 @@ static inline void flush_write_buffers(void)
 #endif /* __KERNEL__ */
+static inline void native_io_delay(void)
+{
+        asm volatile("outb %%al,$0x80" : : : "memory");
+}
 #if defined(CONFIG_PARAVIRT)
 #include <asm/paravirt.h>
 #else
-#define __SLOW_DOWN_IO "outb %%al,$0x80;"
 static inline void slow_down_io(void) {
-        __asm__ __volatile__(
+        native_io_delay();
-                __SLOW_DOWN_IO
 #ifdef REALLY_SLOW_IO
-                __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO
+        native_io_delay();
+        native_io_delay();
+        native_io_delay();
 #endif
-                : : );
 }
 #endif
diff --git a/include/asm-i386/irq.h b/include/asm-i386/irq.h
index 11761cdaae19..9e15ce0006eb 100644
--- a/include/asm-i386/irq.h
+++ b/include/asm-i386/irq.h
@@ -37,8 +37,6 @@ static __inline__ int irq_canonicalize(int irq)
 extern int irqbalance_disable(char *str);
 #endif
-extern void quirk_intel_irqbalance(void);
 #ifdef CONFIG_HOTPLUG_CPU
 extern void fixup_irqs(cpumask_t map);
 #endif
diff --git a/include/asm-i386/irq_regs.h b/include/asm-i386/irq_regs.h
index a1b3f7f594a2..3368b20c0b48 100644
--- a/include/asm-i386/irq_regs.h
+++ b/include/asm-i386/irq_regs.h
@@ -1,25 +1,27 @@
 /*
 * Per-cpu current frame pointer - the location of the last exception frame on
- * the stack, stored in the PDA.
+ * the stack, stored in the per-cpu area.
 *
 * Jeremy Fitzhardinge <jeremy@goop.org>
 */
 #ifndef _ASM_I386_IRQ_REGS_H
 #define _ASM_I386_IRQ_REGS_H
-#include <asm/pda.h>
+#include <asm/percpu.h>
+DECLARE_PER_CPU(struct pt_regs *, irq_regs);
 static inline struct pt_regs *get_irq_regs(void)
 {
-        return read_pda(irq_regs);
+        return x86_read_percpu(irq_regs);
 }
 static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
 {
        struct pt_regs *old_regs;
-        old_regs = read_pda(irq_regs);
+        old_regs = get_irq_regs();
-        write_pda(irq_regs, new_regs);
+        x86_write_percpu(irq_regs, new_regs);
        return old_regs;
 }
diff --git a/include/asm-i386/irqflags.h b/include/asm-i386/irqflags.h
index 17b18cf4fe9d..eff8585cb741 100644
--- a/include/asm-i386/irqflags.h
+++ b/include/asm-i386/irqflags.h
@@ -9,6 +9,43 @@
 */
 #ifndef _ASM_IRQFLAGS_H
 #define _ASM_IRQFLAGS_H
+#include <asm/processor-flags.h>
+#ifndef __ASSEMBLY__
+static inline unsigned long native_save_fl(void)
+{
+        unsigned long f;
+        asm volatile("pushfl ; popl %0":"=g" (f): /* no input */);
+        return f;
+}
+static inline void native_restore_fl(unsigned long f)
+{
+        asm volatile("pushl %0 ; popfl": /* no output */
+                             :"g" (f)
+                             :"memory", "cc");
+}
+static inline void native_irq_disable(void)
+{
+        asm volatile("cli": : :"memory");
+}
+static inline void native_irq_enable(void)
+{
+        asm volatile("sti": : :"memory");
+}
+static inline void native_safe_halt(void)
+{
+        asm volatile("sti; hlt": : :"memory");
+}
+static inline void native_halt(void)
+{
+        asm volatile("hlt": : :"memory");
+}
+#endif  /* __ASSEMBLY__ */
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
@@ -17,35 +54,22 @@
 static inline unsigned long __raw_local_save_flags(void)
 {
-        unsigned long flags;
+        return native_save_fl();
-        __asm__ __volatile__(
-                "pushfl ; popl %0"
-                : "=g" (flags)
-                : /* no input */
-        );
-        return flags;
 }
 static inline void raw_local_irq_restore(unsigned long flags)
 {
-        __asm__ __volatile__(
+        native_restore_fl(flags);
-                "pushl %0 ; popfl"
-                : /* no output */
-                :"g" (flags)
-                :"memory", "cc"
-        );
 }
 static inline void raw_local_irq_disable(void)
 {
-        __asm__ __volatile__("cli" : : : "memory");
+        native_irq_disable();
 }
 static inline void raw_local_irq_enable(void)
 {
-        __asm__ __volatile__("sti" : : : "memory");
+        native_irq_enable();
 }
 /*
@@ -54,7 +78,7 @@ static inline void raw_local_irq_enable(void)
 */
 static inline void raw_safe_halt(void)
 {
-        __asm__ __volatile__("sti; hlt" : : : "memory");
+        native_safe_halt();
 }
 /*
@@ -63,7 +87,7 @@ static inline void raw_safe_halt(void)
 */
 static inline void halt(void)
 {
-        __asm__ __volatile__("hlt": : :"memory");
+        native_halt();
 }
 /*
@@ -96,7 +120,7 @@ static inline unsigned long __raw_local_irq_save(void)
 static inline int raw_irqs_disabled_flags(unsigned long flags)
 {
-        return !(flags & (1 << 9));
+        return !(flags & X86_EFLAGS_IF);
 }
 static inline int raw_irqs_disabled(void)
diff --git a/include/asm-i386/kexec.h b/include/asm-i386/kexec.h
index 4dfc9f5ed031..bcb5b21de2d2 100644
--- a/include/asm-i386/kexec.h
+++ b/include/asm-i386/kexec.h
@@ -21,7 +21,6 @@
 #ifndef __ASSEMBLY__
-#include <asm/fixmap.h>
 #include <asm/ptrace.h>
 #include <asm/string.h>
@@ -29,10 +28,6 @@
 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
 * I.e. Maximum page that is mapped directly into kernel memory,
 * and kmap is not required.
- *
- * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
- * calculation for the amount of memory directly mappable into the
- * kernel memory space.
 */
 /* Maximum physical address we can use pages from */
@@ -47,6 +42,9 @@
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_386
+/* We can also handle crash dumps from 64 bit kernel. */
+#define vmcore_elf_check_arch_cross(x) ((x)->e_machine == EM_X86_64)
 #define MAX_NOTE_BYTES 1024
 /* CPU does not save ss and esp on stack if execution is already
diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-i386/mach-bigsmp/mach_apic.h
index 18b19a773440..ebd319f838ab 100644
--- a/include/asm-i386/mach-bigsmp/mach_apic.h
+++ b/include/asm-i386/mach-bigsmp/mach_apic.h
@@ -71,7 +71,7 @@ static inline void init_apic_ldr(void)
        apic_write_around(APIC_LDR, val);
 }
-static inline void clustered_apic_check(void)
+static inline void setup_apic_routing(void)
 {
        printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
                "Physflat", nr_ioapics);
diff --git a/include/asm-i386/mach-default/mach_apic.h b/include/asm-i386/mach-default/mach_apic.h
index 3ef6292db780..6db1c3babe9a 100644
--- a/include/asm-i386/mach-default/mach_apic.h
+++ b/include/asm-i386/mach-default/mach_apic.h
@@ -54,7 +54,7 @@ static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
        return phys_map;
 }
-static inline void clustered_apic_check(void)
+static inline void setup_apic_routing(void)
 {
        printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
                                        "Flat", nr_ioapics);
diff --git a/include/asm-i386/mach-es7000/mach_apic.h b/include/asm-i386/mach-es7000/mach_apic.h
index 26333685a7fb..2d978928a395 100644
--- a/include/asm-i386/mach-es7000/mach_apic.h
+++ b/include/asm-i386/mach-es7000/mach_apic.h
@@ -73,15 +73,8 @@ static inline void init_apic_ldr(void)
        apic_write_around(APIC_LDR, val);
 }
-extern void es7000_sw_apic(void);
-static inline void enable_apic_mode(void)
-{
-        es7000_sw_apic();
-        return;
-}
 extern int apic_version [MAX_APICS];
-static inline void clustered_apic_check(void)
+static inline void setup_apic_routing(void)
 {
        int apic = bios_cpu_apicid[smp_processor_id()];
        printk("Enabling APIC mode:  %s.  Using %d I/O APICs, target cpus %lx\n",
diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h
index 24990e546da3..b9fb784e1fd5 100644
--- a/include/asm-i386/mach-es7000/mach_mpparse.h
+++ b/include/asm-i386/mach-es7000/mach_mpparse.h
@@ -18,18 +18,6 @@ extern int parse_unisys_oem (char *oemptr);
 extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
 extern void setup_unisys(void);
-static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
-                char *productid)
-{
-        if (mpc->mpc_oemptr) {
-                struct mp_config_oemtable *oem_table =
-                        (struct mp_config_oemtable *)mpc->mpc_oemptr;
-                if (!strncmp(oem, "UNISYS", 6))
-                        return parse_unisys_oem((char *)oem_table);
-        }
-        return 0;
-}
 #ifdef CONFIG_ACPI
 static inline int es7000_check_dsdt(void)
@@ -41,26 +29,6 @@ static inline int es7000_check_dsdt(void)
                return 1;
        return 0;
 }
-/* Hook from generic ACPI tables.c */
-static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        unsigned long oem_addr;
-        if (!find_unisys_acpi_oem_table(&oem_addr)) {
-                if (es7000_check_dsdt())
-                        return parse_unisys_oem((char *)oem_addr);
-                else {
-                        setup_unisys();
-                        return 1;
-                }
-        }
-        return 0;
-}
-#else
-static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        return 0;
-}
 #endif
 #endif /* __ASM_MACH_MPPARSE_H */
diff --git a/include/asm-i386/mach-generic/mach_apic.h b/include/asm-i386/mach-generic/mach_apic.h
index d9dc039da94a..a236e7021528 100644
--- a/include/asm-i386/mach-generic/mach_apic.h
+++ b/include/asm-i386/mach-generic/mach_apic.h
@@ -13,7 +13,7 @@
 #define apic_id_registered (genapic->apic_id_registered)
 #define init_apic_ldr (genapic->init_apic_ldr)
 #define ioapic_phys_id_map (genapic->ioapic_phys_id_map)
-#define clustered_apic_check (genapic->clustered_apic_check) 
+#define setup_apic_routing (genapic->setup_apic_routing)
 #define multi_timer_check (genapic->multi_timer_check)
 #define apicid_to_node (genapic->apicid_to_node)
 #define cpu_to_logical_apicid (genapic->cpu_to_logical_apicid) 
diff --git a/include/asm-i386/mach-numaq/mach_apic.h b/include/asm-i386/mach-numaq/mach_apic.h
index 9d158095da82..5e5e7dd2692e 100644
--- a/include/asm-i386/mach-numaq/mach_apic.h
+++ b/include/asm-i386/mach-numaq/mach_apic.h
@@ -34,7 +34,7 @@ static inline void init_apic_ldr(void)
        /* Already done in NUMA-Q firmware */
 }
-static inline void clustered_apic_check(void)
+static inline void setup_apic_routing(void)
 {
        printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
                "NUMA-Q", nr_ioapics);
diff --git a/include/asm-i386/mach-summit/mach_apic.h b/include/asm-i386/mach-summit/mach_apic.h
index 43e5bd8f4a19..732f776aab8e 100644
--- a/include/asm-i386/mach-summit/mach_apic.h
+++ b/include/asm-i386/mach-summit/mach_apic.h
@@ -80,7 +80,7 @@ static inline int apic_id_registered(void)
        return 1;
 }
-static inline void clustered_apic_check(void)
+static inline void setup_apic_routing(void)
 {
        printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
                                                nr_ioapics);
diff --git a/include/asm-i386/mach-summit/mach_mpparse.h b/include/asm-i386/mach-summit/mach_mpparse.h
index 94268399170d..c2520539d934 100644
--- a/include/asm-i386/mach-summit/mach_mpparse.h
+++ b/include/asm-i386/mach-summit/mach_mpparse.h
@@ -30,7 +30,7 @@ static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                        (!strncmp(productid, "VIGIL SMP", 9) 
                         || !strncmp(productid, "EXA", 3)
                         || !strncmp(productid, "RUTHLESS SMP", 12))){
-                mark_tsc_unstable();
+                mark_tsc_unstable("Summit based system");
                use_cyclone = 1; /*enable cyclone-timer*/
                setup_summit();
                return 1;
@@ -44,7 +44,7 @@ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
        if (!strncmp(oem_id, "IBM", 3) &&
            (!strncmp(oem_table_id, "SERVIGIL", 8)
             || !strncmp(oem_table_id, "EXA", 3))){
-                mark_tsc_unstable();
+                mark_tsc_unstable("Summit based system");
                use_cyclone = 1; /*enable cyclone-timer*/
                setup_summit();
                return 1;
diff --git a/include/asm-i386/mach-visws/mach_apic.h b/include/asm-i386/mach-visws/mach_apic.h
index 18afe6b6fc4d..efac6f0d139f 100644
--- a/include/asm-i386/mach-visws/mach_apic.h
+++ b/include/asm-i386/mach-visws/mach_apic.h
@@ -47,7 +47,7 @@ static inline void summit_check(char *oem, char *productid)
 {
 }
-static inline void clustered_apic_check(void)
+static inline void setup_apic_routing(void)
 {
 }
diff --git a/include/asm-i386/mmu_context.h b/include/asm-i386/mmu_context.h
index e6aa30f8de5b..8198d1cca1f3 100644
--- a/include/asm-i386/mmu_context.h
+++ b/include/asm-i386/mmu_context.h
@@ -5,6 +5,16 @@
 #include <asm/atomic.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
+#include <asm/paravirt.h>
+#ifndef CONFIG_PARAVIRT
+#include <asm-generic/mm_hooks.h>
+static inline void paravirt_activate_mm(struct mm_struct *prev,
+                                        struct mm_struct *next)
+{
+}
+#endif  /* !CONFIG_PARAVIRT */
 /*
 * Used for LDT copy/destruction.
@@ -65,7 +75,10 @@ static inline void switch_mm(struct mm_struct *prev,
 #define deactivate_mm(tsk, mm)                  \
        asm("movl %0,%%gs": :"r" (0));
-#define activate_mm(prev, next) \
+#define activate_mm(prev, next)                         \
-        switch_mm((prev),(next),NULL)
+        do {                                            \
+                paravirt_activate_mm(prev, next);       \
+                switch_mm((prev),(next),NULL);          \
+        } while(0);
 #endif
diff --git a/include/asm-i386/module.h b/include/asm-i386/module.h
index 02f8f541cbe0..7e5fda6c3976 100644
--- a/include/asm-i386/module.h
+++ b/include/asm-i386/module.h
@@ -54,6 +54,8 @@ struct mod_arch_specific
 #define MODULE_PROC_FAMILY "CYRIXIII "
 #elif defined CONFIG_MVIAC3_2
 #define MODULE_PROC_FAMILY "VIAC3-2 "
+#elif defined CONFIG_MVIAC7
+#define MODULE_PROC_FAMILY "VIAC7 "
 #elif defined CONFIG_MGEODEGX1
 #define MODULE_PROC_FAMILY "GEODEGX1 "
 #elif defined CONFIG_MGEODE_LX
diff --git a/include/asm-i386/msr-index.h b/include/asm-i386/msr-index.h
new file mode 100644
index 000000000000..a02eb2991349
--- /dev/null
+++ b/include/asm-i386/msr-index.h
@@ -0,0 +1,278 @@
+#ifndef __ASM_MSR_INDEX_H
+#define __ASM_MSR_INDEX_H
+/* CPU model specific register (MSR) numbers */
+/* x86-64 specific MSRs */
+#define MSR_EFER                0xc0000080 /* extended feature register */
+#define MSR_STAR                0xc0000081 /* legacy mode SYSCALL target */
+#define MSR_LSTAR               0xc0000082 /* long mode SYSCALL target */
+#define MSR_CSTAR               0xc0000083 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK        0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE             0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE             0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE      0xc0000102 /* SwapGS GS shadow */
+/* EFER bits: */
+#define _EFER_SCE               0  /* SYSCALL/SYSRET */
+#define _EFER_LME               8  /* Long mode enable */
+#define _EFER_LMA               10 /* Long mode active (read-only) */
+#define _EFER_NX                11 /* No execute enable */
+#define EFER_SCE                (1<<_EFER_SCE)
+#define EFER_LME                (1<<_EFER_LME)
+#define EFER_LMA                (1<<_EFER_LMA)
+#define EFER_NX                 (1<<_EFER_NX)
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0               0x000000c1
+#define MSR_IA32_PERFCTR1               0x000000c2
+#define MSR_FSB_FREQ                    0x000000cd
+#define MSR_MTRRcap                     0x000000fe
+#define MSR_IA32_BBL_CR_CTL             0x00000119
+#define MSR_IA32_SYSENTER_CS            0x00000174
+#define MSR_IA32_SYSENTER_ESP           0x00000175
+#define MSR_IA32_SYSENTER_EIP           0x00000176
+#define MSR_IA32_MCG_CAP                0x00000179
+#define MSR_IA32_MCG_STATUS             0x0000017a
+#define MSR_IA32_MCG_CTL                0x0000017b
+#define MSR_IA32_PEBS_ENABLE            0x000003f1
+#define MSR_IA32_DS_AREA                0x00000600
+#define MSR_IA32_PERF_CAPABILITIES      0x00000345
+#define MSR_MTRRfix64K_00000            0x00000250
+#define MSR_MTRRfix16K_80000            0x00000258
+#define MSR_MTRRfix16K_A0000            0x00000259
+#define MSR_MTRRfix4K_C0000             0x00000268
+#define MSR_MTRRfix4K_C8000             0x00000269
+#define MSR_MTRRfix4K_D0000             0x0000026a
+#define MSR_MTRRfix4K_D8000             0x0000026b
+#define MSR_MTRRfix4K_E0000             0x0000026c
+#define MSR_MTRRfix4K_E8000             0x0000026d
+#define MSR_MTRRfix4K_F0000             0x0000026e
+#define MSR_MTRRfix4K_F8000             0x0000026f
+#define MSR_MTRRdefType                 0x000002ff
+#define MSR_IA32_DEBUGCTLMSR            0x000001d9
+#define MSR_IA32_LASTBRANCHFROMIP       0x000001db
+#define MSR_IA32_LASTBRANCHTOIP         0x000001dc
+#define MSR_IA32_LASTINTFROMIP          0x000001dd
+#define MSR_IA32_LASTINTTOIP            0x000001de
+#define MSR_IA32_MC0_CTL                0x00000400
+#define MSR_IA32_MC0_STATUS             0x00000401
+#define MSR_IA32_MC0_ADDR               0x00000402
+#define MSR_IA32_MC0_MISC               0x00000403
+#define MSR_P6_PERFCTR0                 0x000000c1
+#define MSR_P6_PERFCTR1                 0x000000c2
+#define MSR_P6_EVNTSEL0                 0x00000186
+#define MSR_P6_EVNTSEL1                 0x00000187
+/* K7/K8 MSRs. Not complete. See the architecture manual for a more
+   complete list. */
+#define MSR_K7_EVNTSEL0                 0xc0010000
+#define MSR_K7_PERFCTR0                 0xc0010004
+#define MSR_K7_EVNTSEL1                 0xc0010001
+#define MSR_K7_PERFCTR1                 0xc0010005
+#define MSR_K7_EVNTSEL2                 0xc0010002
+#define MSR_K7_PERFCTR2                 0xc0010006
+#define MSR_K7_EVNTSEL3                 0xc0010003
+#define MSR_K7_PERFCTR3                 0xc0010007
+#define MSR_K8_TOP_MEM1                 0xc001001a
+#define MSR_K7_CLK_CTL                  0xc001001b
+#define MSR_K8_TOP_MEM2                 0xc001001d
+#define MSR_K8_SYSCFG                   0xc0010010
+#define K8_MTRRFIXRANGE_DRAM_ENABLE     0x00040000 /* MtrrFixDramEn bit    */
+#define K8_MTRRFIXRANGE_DRAM_MODIFY     0x00080000 /* MtrrFixDramModEn bit */
+#define K8_MTRR_RDMEM_WRMEM_MASK        0x18181818 /* Mask: RdMem|WrMem    */
+#define MSR_K7_HWCR                     0xc0010015
+#define MSR_K8_HWCR                     0xc0010015
+#define MSR_K7_FID_VID_CTL              0xc0010041
+#define MSR_K7_FID_VID_STATUS           0xc0010042
+#define MSR_K8_ENABLE_C1E               0xc0010055
+/* K6 MSRs */
+#define MSR_K6_EFER                     0xc0000080
+#define MSR_K6_STAR                     0xc0000081
+#define MSR_K6_WHCR                     0xc0000082
+#define MSR_K6_UWCCR                    0xc0000085
+#define MSR_K6_EPMR                     0xc0000086
+#define MSR_K6_PSOR                     0xc0000087
+#define MSR_K6_PFIR                     0xc0000088
+/* Centaur-Hauls/IDT defined MSRs. */
+#define MSR_IDT_FCR1                    0x00000107
+#define MSR_IDT_FCR2                    0x00000108
+#define MSR_IDT_FCR3                    0x00000109
+#define MSR_IDT_FCR4                    0x0000010a
+#define MSR_IDT_MCR0                    0x00000110
+#define MSR_IDT_MCR1                    0x00000111
+#define MSR_IDT_MCR2                    0x00000112
+#define MSR_IDT_MCR3                    0x00000113
+#define MSR_IDT_MCR4                    0x00000114
+#define MSR_IDT_MCR5                    0x00000115
+#define MSR_IDT_MCR6                    0x00000116
+#define MSR_IDT_MCR7                    0x00000117
+#define MSR_IDT_MCR_CTRL                0x00000120
+/* VIA Cyrix defined MSRs*/
+#define MSR_VIA_FCR                     0x00001107
+#define MSR_VIA_LONGHAUL                0x0000110a
+#define MSR_VIA_RNG                     0x0000110b
+#define MSR_VIA_BCR2                    0x00001147
+/* Transmeta defined MSRs */
+#define MSR_TMTA_LONGRUN_CTRL           0x80868010
+#define MSR_TMTA_LONGRUN_FLAGS          0x80868011
+#define MSR_TMTA_LRTI_READOUT           0x80868018
+#define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
+/* Intel defined MSRs. */
+#define MSR_IA32_P5_MC_ADDR             0x00000000
+#define MSR_IA32_P5_MC_TYPE             0x00000001
+#define MSR_IA32_TSC                    0x00000010
+#define MSR_IA32_PLATFORM_ID            0x00000017
+#define MSR_IA32_EBL_CR_POWERON         0x0000002a
+#define MSR_IA32_APICBASE               0x0000001b
+#define MSR_IA32_APICBASE_BSP           (1<<8)
+#define MSR_IA32_APICBASE_ENABLE        (1<<11)
+#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
+#define MSR_IA32_UCODE_WRITE            0x00000079
+#define MSR_IA32_UCODE_REV              0x0000008b
+#define MSR_IA32_PERF_STATUS            0x00000198
+#define MSR_IA32_PERF_CTL               0x00000199
+#define MSR_IA32_MPERF                  0x000000e7
+#define MSR_IA32_APERF                  0x000000e8
+#define MSR_IA32_THERM_CONTROL          0x0000019a
+#define MSR_IA32_THERM_INTERRUPT        0x0000019b
+#define MSR_IA32_THERM_STATUS           0x0000019c
+#define MSR_IA32_MISC_ENABLE            0x000001a0
+/* Intel Model 6 */
+#define MSR_P6_EVNTSEL0                 0x00000186
+#define MSR_P6_EVNTSEL1                 0x00000187
+/* P4/Xeon+ specific */
+#define MSR_IA32_MCG_EAX                0x00000180
+#define MSR_IA32_MCG_EBX                0x00000181
+#define MSR_IA32_MCG_ECX                0x00000182
+#define MSR_IA32_MCG_EDX                0x00000183
+#define MSR_IA32_MCG_ESI                0x00000184
+#define MSR_IA32_MCG_EDI                0x00000185
+#define MSR_IA32_MCG_EBP                0x00000186
+#define MSR_IA32_MCG_ESP                0x00000187
+#define MSR_IA32_MCG_EFLAGS             0x00000188
+#define MSR_IA32_MCG_EIP                0x00000189
+#define MSR_IA32_MCG_RESERVED           0x0000018a
+/* Pentium IV performance counter MSRs */
+#define MSR_P4_BPU_PERFCTR0             0x00000300
+#define MSR_P4_BPU_PERFCTR1             0x00000301
+#define MSR_P4_BPU_PERFCTR2             0x00000302
+#define MSR_P4_BPU_PERFCTR3             0x00000303
+#define MSR_P4_MS_PERFCTR0              0x00000304
+#define MSR_P4_MS_PERFCTR1              0x00000305
+#define MSR_P4_MS_PERFCTR2              0x00000306
+#define MSR_P4_MS_PERFCTR3              0x00000307
+#define MSR_P4_FLAME_PERFCTR0           0x00000308
+#define MSR_P4_FLAME_PERFCTR1           0x00000309
+#define MSR_P4_FLAME_PERFCTR2           0x0000030a
+#define MSR_P4_FLAME_PERFCTR3           0x0000030b
+#define MSR_P4_IQ_PERFCTR0              0x0000030c
+#define MSR_P4_IQ_PERFCTR1              0x0000030d
+#define MSR_P4_IQ_PERFCTR2              0x0000030e
+#define MSR_P4_IQ_PERFCTR3              0x0000030f
+#define MSR_P4_IQ_PERFCTR4              0x00000310
+#define MSR_P4_IQ_PERFCTR5              0x00000311
+#define MSR_P4_BPU_CCCR0                0x00000360
+#define MSR_P4_BPU_CCCR1                0x00000361
+#define MSR_P4_BPU_CCCR2                0x00000362
+#define MSR_P4_BPU_CCCR3                0x00000363
+#define MSR_P4_MS_CCCR0                 0x00000364
+#define MSR_P4_MS_CCCR1                 0x00000365
+#define MSR_P4_MS_CCCR2                 0x00000366
+#define MSR_P4_MS_CCCR3                 0x00000367
+#define MSR_P4_FLAME_CCCR0              0x00000368
+#define MSR_P4_FLAME_CCCR1              0x00000369
+#define MSR_P4_FLAME_CCCR2              0x0000036a
+#define MSR_P4_FLAME_CCCR3              0x0000036b
+#define MSR_P4_IQ_CCCR0                 0x0000036c
+#define MSR_P4_IQ_CCCR1                 0x0000036d
+#define MSR_P4_IQ_CCCR2                 0x0000036e
+#define MSR_P4_IQ_CCCR3                 0x0000036f
+#define MSR_P4_IQ_CCCR4                 0x00000370
+#define MSR_P4_IQ_CCCR5                 0x00000371
+#define MSR_P4_ALF_ESCR0                0x000003ca
+#define MSR_P4_ALF_ESCR1                0x000003cb
+#define MSR_P4_BPU_ESCR0                0x000003b2
+#define MSR_P4_BPU_ESCR1                0x000003b3
+#define MSR_P4_BSU_ESCR0                0x000003a0
+#define MSR_P4_BSU_ESCR1                0x000003a1
+#define MSR_P4_CRU_ESCR0                0x000003b8
+#define MSR_P4_CRU_ESCR1                0x000003b9
+#define MSR_P4_CRU_ESCR2                0x000003cc
+#define MSR_P4_CRU_ESCR3                0x000003cd
+#define MSR_P4_CRU_ESCR4                0x000003e0
+#define MSR_P4_CRU_ESCR5                0x000003e1
+#define MSR_P4_DAC_ESCR0                0x000003a8
+#define MSR_P4_DAC_ESCR1                0x000003a9
+#define MSR_P4_FIRM_ESCR0               0x000003a4
+#define MSR_P4_FIRM_ESCR1               0x000003a5
+#define MSR_P4_FLAME_ESCR0              0x000003a6
+#define MSR_P4_FLAME_ESCR1              0x000003a7
+#define MSR_P4_FSB_ESCR0                0x000003a2
+#define MSR_P4_FSB_ESCR1                0x000003a3
+#define MSR_P4_IQ_ESCR0                 0x000003ba
+#define MSR_P4_IQ_ESCR1                 0x000003bb
+#define MSR_P4_IS_ESCR0                 0x000003b4
+#define MSR_P4_IS_ESCR1                 0x000003b5
+#define MSR_P4_ITLB_ESCR0               0x000003b6
+#define MSR_P4_ITLB_ESCR1               0x000003b7
+#define MSR_P4_IX_ESCR0                 0x000003c8
+#define MSR_P4_IX_ESCR1                 0x000003c9
+#define MSR_P4_MOB_ESCR0                0x000003aa
+#define MSR_P4_MOB_ESCR1                0x000003ab
+#define MSR_P4_MS_ESCR0                 0x000003c0
+#define MSR_P4_MS_ESCR1                 0x000003c1
+#define MSR_P4_PMH_ESCR0                0x000003ac
+#define MSR_P4_PMH_ESCR1                0x000003ad
+#define MSR_P4_RAT_ESCR0                0x000003bc
+#define MSR_P4_RAT_ESCR1                0x000003bd
+#define MSR_P4_SAAT_ESCR0               0x000003ae
+#define MSR_P4_SAAT_ESCR1               0x000003af
+#define MSR_P4_SSU_ESCR0                0x000003be
+#define MSR_P4_SSU_ESCR1                0x000003bf /* guess: not in manual */
+#define MSR_P4_TBPU_ESCR0               0x000003c2
+#define MSR_P4_TBPU_ESCR1               0x000003c3
+#define MSR_P4_TC_ESCR0                 0x000003c4
+#define MSR_P4_TC_ESCR1                 0x000003c5
+#define MSR_P4_U2L_ESCR0                0x000003b0
+#define MSR_P4_U2L_ESCR1                0x000003b1
+/* Intel Core-based CPU performance counters */
+#define MSR_CORE_PERF_FIXED_CTR0        0x00000309
+#define MSR_CORE_PERF_FIXED_CTR1        0x0000030a
+#define MSR_CORE_PERF_FIXED_CTR2        0x0000030b
+#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x0000038d
+#define MSR_CORE_PERF_GLOBAL_STATUS     0x0000038e
+#define MSR_CORE_PERF_GLOBAL_CTRL       0x0000038f
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x00000390
+/* Geode defined MSRs */
+#define MSR_GEODE_BUSCONT_CONF0         0x00001900
+#endif /* __ASM_MSR_INDEX_H */
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index 2ad3f30b1a68..9559894c7658 100644
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -1,6 +1,79 @@
 #ifndef __ASM_MSR_H
 #define __ASM_MSR_H
+#include <asm/msr-index.h>
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <asm/errno.h>
+static inline unsigned long long native_read_msr(unsigned int msr)
+{
+        unsigned long long val;
+        asm volatile("rdmsr" : "=A" (val) : "c" (msr));
+        return val;
+}
+static inline unsigned long long native_read_msr_safe(unsigned int msr,
+                                                      int *err)
+{
+        unsigned long long val;
+        asm volatile("2: rdmsr ; xorl %0,%0\n"
+                     "1:\n\t"
+                     ".section .fixup,\"ax\"\n\t"
+                     "3:  movl %3,%0 ; jmp 1b\n\t"
+                     ".previous\n\t"
+                     ".section __ex_table,\"a\"\n"
+                     "   .align 4\n\t"
+                     "   .long  2b,3b\n\t"
+                     ".previous"
+                     : "=r" (*err), "=A" (val)
+                     : "c" (msr), "i" (-EFAULT));
+        return val;
+}
+static inline void native_write_msr(unsigned int msr, unsigned long long val)
+{
+        asm volatile("wrmsr" : : "c" (msr), "A"(val));
+}
+static inline int native_write_msr_safe(unsigned int msr,
+                                        unsigned long long val)
+{
+        int err;
+        asm volatile("2: wrmsr ; xorl %0,%0\n"
+                     "1:\n\t"
+                     ".section .fixup,\"ax\"\n\t"
+                     "3:  movl %4,%0 ; jmp 1b\n\t"
+                     ".previous\n\t"
+                     ".section __ex_table,\"a\"\n"
+                     "   .align 4\n\t"
+                     "   .long  2b,3b\n\t"
+                     ".previous"
+                     : "=a" (err)
+                     : "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
+                       "i" (-EFAULT));
+        return err;
+}
+static inline unsigned long long native_read_tsc(void)
+{
+        unsigned long long val;
+        asm volatile("rdtsc" : "=A" (val));
+        return val;
+}
+static inline unsigned long long native_read_pmc(void)
+{
+        unsigned long long val;
+        asm volatile("rdpmc" : "=A" (val));
+        return val;
+}
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
@@ -11,22 +84,20 @@
 * pointer indirection), this allows gcc to optimize better
 */
-#define rdmsr(msr,val1,val2) \
+#define rdmsr(msr,val1,val2)                                            \
-        __asm__ __volatile__("rdmsr" \
+        do {                                                            \
-                          : "=a" (val1), "=d" (val2) \
+                unsigned long long __val = native_read_msr(msr);        \
-                          : "c" (msr))
+                val1 = __val;                                           \
+                val2 = __val >> 32;                                     \
+        } while(0)
-#define wrmsr(msr,val1,val2) \
+#define wrmsr(msr,val1,val2)                                            \
-        __asm__ __volatile__("wrmsr" \
+        native_write_msr(msr, ((unsigned long long)val2 << 32) | val1)
-                          : /* no outputs */ \
-                          : "c" (msr), "a" (val1), "d" (val2))
-#define rdmsrl(msr,val) do { \
+#define rdmsrl(msr,val)                                 \
-        unsigned long l__,h__; \
+        do {                                            \
-        rdmsr (msr, l__, h__);  \
+                (val) = native_read_msr(msr);           \
-        val = l__;  \
+        } while(0)
-        val |= ((u64)h__<<32);  \
-} while(0)
 static inline void wrmsrl (unsigned long msr, unsigned long long val)
 {
@@ -37,50 +108,41 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 }
 /* wrmsr with exception handling */
-#define wrmsr_safe(msr,a,b) ({ int ret__;                                               \
+#define wrmsr_safe(msr,val1,val2)                                               \
-        asm volatile("2: wrmsr ; xorl %0,%0\n"                                          \
+        (native_write_msr_safe(msr, ((unsigned long long)val2 << 32) | val1))
-                     "1:\n\t"                                                           \
-                     ".section .fixup,\"ax\"\n\t"                                       \
-                     "3:  movl %4,%0 ; jmp 1b\n\t"                                      \
-                     ".previous\n\t"                                                    \
-                     ".section __ex_table,\"a\"\n"                                      \
-                     "   .align 4\n\t"                                                  \
-                     "   .long  2b,3b\n\t"                                              \
-                     ".previous"                                                        \
-                     : "=a" (ret__)                                                     \
-                     : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
-        ret__; })
 /* rdmsr with exception handling */
-#define rdmsr_safe(msr,a,b) ({ int ret__;                                               \
+#define rdmsr_safe(msr,p1,p2)                                           \
-        asm volatile("2: rdmsr ; xorl %0,%0\n"                                          \
+        ({                                                              \
-                     "1:\n\t"                                                           \
+                int __err;                                              \
-                     ".section .fixup,\"ax\"\n\t"                                       \
+                unsigned long long __val = native_read_msr_safe(msr, &__err);\
-                     "3:  movl %4,%0 ; jmp 1b\n\t"                                      \
+                (*p1) = __val;                                          \
-                     ".previous\n\t"                                                    \
+                (*p2) = __val >> 32;                                    \
-                     ".section __ex_table,\"a\"\n"                                      \
+                __err;                                                  \
-                     "   .align 4\n\t"                                                  \
+        })
-                     "   .long  2b,3b\n\t"                                              \
-                     ".previous"                                                        \
+#define rdtsc(low,high)                                         \
-                     : "=r" (ret__), "=a" (*(a)), "=d" (*(b))                           \
+        do {                                                    \
-                     : "c" (msr), "i" (-EFAULT));\
+                u64 _l = native_read_tsc();                     \
-        ret__; })
+                (low) = (u32)_l;                                \
+                (high) = _l >> 32;                              \
-#define rdtsc(low,high) \
+        } while(0)
-     __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
+#define rdtscl(low)                                             \
-#define rdtscl(low) \
+        do {                                                    \
-     __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
+                (low) = native_read_tsc();                      \
+        } while(0)
-#define rdtscll(val) \
-     __asm__ __volatile__("rdtsc" : "=A" (val))
+#define rdtscll(val) ((val) = native_read_tsc())
 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
-#define rdpmc(counter,low,high) \
+#define rdpmc(counter,low,high)                                 \
-     __asm__ __volatile__("rdpmc" \
+        do {                                                    \
-                          : "=a" (low), "=d" (high) \
+                u64 _l = native_read_pmc();                     \
-                          : "c" (counter))
+                low = (u32)_l;                                  \
+                high = _l >> 32;                                \
+        } while(0)
 #endif  /* !CONFIG_PARAVIRT */
 #ifdef CONFIG_SMP
@@ -96,234 +158,6 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
        wrmsr(msr_no, l, h);
 }
 #endif  /*  CONFIG_SMP  */
+#endif
-/* symbolic names for some interesting MSRs */
+#endif
-/* Intel defined MSRs. */
-#define MSR_IA32_P5_MC_ADDR             0
-#define MSR_IA32_P5_MC_TYPE             1
-#define MSR_IA32_PLATFORM_ID            0x17
-#define MSR_IA32_EBL_CR_POWERON         0x2a
-#define MSR_IA32_APICBASE               0x1b
-#define MSR_IA32_APICBASE_BSP           (1<<8)
-#define MSR_IA32_APICBASE_ENABLE        (1<<11)
-#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
-#define MSR_IA32_UCODE_WRITE            0x79
-#define MSR_IA32_UCODE_REV              0x8b
-#define MSR_P6_PERFCTR0         0xc1
-#define MSR_P6_PERFCTR1         0xc2
-#define MSR_FSB_FREQ            0xcd
-#define MSR_IA32_BBL_CR_CTL             0x119
-#define MSR_IA32_SYSENTER_CS            0x174
-#define MSR_IA32_SYSENTER_ESP           0x175
-#define MSR_IA32_SYSENTER_EIP           0x176
-#define MSR_IA32_MCG_CAP                0x179
-#define MSR_IA32_MCG_STATUS             0x17a
-#define MSR_IA32_MCG_CTL                0x17b
-/* P4/Xeon+ specific */
-#define MSR_IA32_MCG_EAX                0x180
-#define MSR_IA32_MCG_EBX                0x181
-#define MSR_IA32_MCG_ECX                0x182
-#define MSR_IA32_MCG_EDX                0x183
-#define MSR_IA32_MCG_ESI                0x184
-#define MSR_IA32_MCG_EDI                0x185
-#define MSR_IA32_MCG_EBP                0x186
-#define MSR_IA32_MCG_ESP                0x187
-#define MSR_IA32_MCG_EFLAGS             0x188
-#define MSR_IA32_MCG_EIP                0x189
-#define MSR_IA32_MCG_RESERVED           0x18A
-#define MSR_P6_EVNTSEL0                 0x186
-#define MSR_P6_EVNTSEL1                 0x187
-#define MSR_IA32_PERF_STATUS            0x198
-#define MSR_IA32_PERF_CTL               0x199
-#define MSR_IA32_MPERF                  0xE7
-#define MSR_IA32_APERF                  0xE8
-#define MSR_IA32_THERM_CONTROL          0x19a
-#define MSR_IA32_THERM_INTERRUPT        0x19b
-#define MSR_IA32_THERM_STATUS           0x19c
-#define MSR_IA32_MISC_ENABLE            0x1a0
-#define MSR_IA32_DEBUGCTLMSR            0x1d9
-#define MSR_IA32_LASTBRANCHFROMIP       0x1db
-#define MSR_IA32_LASTBRANCHTOIP         0x1dc
-#define MSR_IA32_LASTINTFROMIP          0x1dd
-#define MSR_IA32_LASTINTTOIP            0x1de
-#define MSR_IA32_MC0_CTL                0x400
-#define MSR_IA32_MC0_STATUS             0x401
-#define MSR_IA32_MC0_ADDR               0x402
-#define MSR_IA32_MC0_MISC               0x403
-#define MSR_IA32_PEBS_ENABLE            0x3f1
-#define MSR_IA32_DS_AREA                0x600
-#define MSR_IA32_PERF_CAPABILITIES      0x345
-/* Pentium IV performance counter MSRs */
-#define MSR_P4_BPU_PERFCTR0             0x300
-#define MSR_P4_BPU_PERFCTR1             0x301
-#define MSR_P4_BPU_PERFCTR2             0x302
-#define MSR_P4_BPU_PERFCTR3             0x303
-#define MSR_P4_MS_PERFCTR0              0x304
-#define MSR_P4_MS_PERFCTR1              0x305
-#define MSR_P4_MS_PERFCTR2              0x306
-#define MSR_P4_MS_PERFCTR3              0x307
-#define MSR_P4_FLAME_PERFCTR0           0x308
-#define MSR_P4_FLAME_PERFCTR1           0x309
-#define MSR_P4_FLAME_PERFCTR2           0x30a
-#define MSR_P4_FLAME_PERFCTR3           0x30b
-#define MSR_P4_IQ_PERFCTR0              0x30c
-#define MSR_P4_IQ_PERFCTR1              0x30d
-#define MSR_P4_IQ_PERFCTR2              0x30e
-#define MSR_P4_IQ_PERFCTR3              0x30f
-#define MSR_P4_IQ_PERFCTR4              0x310
-#define MSR_P4_IQ_PERFCTR5              0x311
-#define MSR_P4_BPU_CCCR0                0x360
-#define MSR_P4_BPU_CCCR1                0x361
-#define MSR_P4_BPU_CCCR2                0x362
-#define MSR_P4_BPU_CCCR3                0x363
-#define MSR_P4_MS_CCCR0                 0x364
-#define MSR_P4_MS_CCCR1                 0x365
-#define MSR_P4_MS_CCCR2                 0x366
-#define MSR_P4_MS_CCCR3                 0x367
-#define MSR_P4_FLAME_CCCR0              0x368
-#define MSR_P4_FLAME_CCCR1              0x369
-#define MSR_P4_FLAME_CCCR2              0x36a
-#define MSR_P4_FLAME_CCCR3              0x36b
-#define MSR_P4_IQ_CCCR0                 0x36c
-#define MSR_P4_IQ_CCCR1                 0x36d
-#define MSR_P4_IQ_CCCR2                 0x36e
-#define MSR_P4_IQ_CCCR3                 0x36f
-#define MSR_P4_IQ_CCCR4                 0x370
-#define MSR_P4_IQ_CCCR5                 0x371
-#define MSR_P4_ALF_ESCR0                0x3ca
-#define MSR_P4_ALF_ESCR1                0x3cb
-#define MSR_P4_BPU_ESCR0                0x3b2
-#define MSR_P4_BPU_ESCR1                0x3b3
-#define MSR_P4_BSU_ESCR0                0x3a0
-#define MSR_P4_BSU_ESCR1                0x3a1
-#define MSR_P4_CRU_ESCR0                0x3b8
-#define MSR_P4_CRU_ESCR1                0x3b9
-#define MSR_P4_CRU_ESCR2                0x3cc
-#define MSR_P4_CRU_ESCR3                0x3cd
-#define MSR_P4_CRU_ESCR4                0x3e0
-#define MSR_P4_CRU_ESCR5                0x3e1
-#define MSR_P4_DAC_ESCR0                0x3a8
-#define MSR_P4_DAC_ESCR1                0x3a9
-#define MSR_P4_FIRM_ESCR0               0x3a4
-#define MSR_P4_FIRM_ESCR1               0x3a5
-#define MSR_P4_FLAME_ESCR0              0x3a6
-#define MSR_P4_FLAME_ESCR1              0x3a7
-#define MSR_P4_FSB_ESCR0                0x3a2
-#define MSR_P4_FSB_ESCR1                0x3a3
-#define MSR_P4_IQ_ESCR0                 0x3ba
-#define MSR_P4_IQ_ESCR1                 0x3bb
-#define MSR_P4_IS_ESCR0                 0x3b4
-#define MSR_P4_IS_ESCR1                 0x3b5
-#define MSR_P4_ITLB_ESCR0               0x3b6
-#define MSR_P4_ITLB_ESCR1               0x3b7
-#define MSR_P4_IX_ESCR0                 0x3c8
-#define MSR_P4_IX_ESCR1                 0x3c9
-#define MSR_P4_MOB_ESCR0                0x3aa
-#define MSR_P4_MOB_ESCR1                0x3ab
-#define MSR_P4_MS_ESCR0                 0x3c0
-#define MSR_P4_MS_ESCR1                 0x3c1
-#define MSR_P4_PMH_ESCR0                0x3ac
-#define MSR_P4_PMH_ESCR1                0x3ad
-#define MSR_P4_RAT_ESCR0                0x3bc
-#define MSR_P4_RAT_ESCR1                0x3bd
-#define MSR_P4_SAAT_ESCR0               0x3ae
-#define MSR_P4_SAAT_ESCR1               0x3af
-#define MSR_P4_SSU_ESCR0                0x3be
-#define MSR_P4_SSU_ESCR1                0x3bf    /* guess: not defined in manual */
-#define MSR_P4_TBPU_ESCR0               0x3c2
-#define MSR_P4_TBPU_ESCR1               0x3c3
-#define MSR_P4_TC_ESCR0                 0x3c4
-#define MSR_P4_TC_ESCR1                 0x3c5
-#define MSR_P4_U2L_ESCR0                0x3b0
-#define MSR_P4_U2L_ESCR1                0x3b1
-/* AMD Defined MSRs */
-#define MSR_K6_EFER                     0xC0000080
-#define MSR_K6_STAR                     0xC0000081
-#define MSR_K6_WHCR                     0xC0000082
-#define MSR_K6_UWCCR                    0xC0000085
-#define MSR_K6_EPMR                     0xC0000086
-#define MSR_K6_PSOR                     0xC0000087
-#define MSR_K6_PFIR                     0xC0000088
-#define MSR_K7_EVNTSEL0                 0xC0010000
-#define MSR_K7_EVNTSEL1                 0xC0010001
-#define MSR_K7_EVNTSEL2                 0xC0010002
-#define MSR_K7_EVNTSEL3                 0xC0010003
-#define MSR_K7_PERFCTR0                 0xC0010004
-#define MSR_K7_PERFCTR1                 0xC0010005
-#define MSR_K7_PERFCTR2                 0xC0010006
-#define MSR_K7_PERFCTR3                 0xC0010007
-#define MSR_K7_HWCR                     0xC0010015
-#define MSR_K7_CLK_CTL                  0xC001001b
-#define MSR_K7_FID_VID_CTL              0xC0010041
-#define MSR_K7_FID_VID_STATUS           0xC0010042
-#define MSR_K8_ENABLE_C1E               0xC0010055
-/* extended feature register */
-#define MSR_EFER                        0xc0000080
-/* EFER bits: */
-/* Execute Disable enable */
-#define _EFER_NX                        11
-#define EFER_NX                         (1<<_EFER_NX)
-/* Centaur-Hauls/IDT defined MSRs. */
-#define MSR_IDT_FCR1                    0x107
-#define MSR_IDT_FCR2                    0x108
-#define MSR_IDT_FCR3                    0x109
-#define MSR_IDT_FCR4                    0x10a
-#define MSR_IDT_MCR0                    0x110
-#define MSR_IDT_MCR1                    0x111
-#define MSR_IDT_MCR2                    0x112
-#define MSR_IDT_MCR3                    0x113
-#define MSR_IDT_MCR4                    0x114
-#define MSR_IDT_MCR5                    0x115
-#define MSR_IDT_MCR6                    0x116
-#define MSR_IDT_MCR7                    0x117
-#define MSR_IDT_MCR_CTRL                0x120
-/* VIA Cyrix defined MSRs*/
-#define MSR_VIA_FCR                     0x1107
-#define MSR_VIA_LONGHAUL                0x110a
-#define MSR_VIA_RNG                     0x110b
-#define MSR_VIA_BCR2                    0x1147
-/* Transmeta defined MSRs */
-#define MSR_TMTA_LONGRUN_CTRL           0x80868010
-#define MSR_TMTA_LONGRUN_FLAGS          0x80868011
-#define MSR_TMTA_LRTI_READOUT           0x80868018
-#define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
-/* Intel Core-based CPU performance counters */
-#define MSR_CORE_PERF_FIXED_CTR0        0x309
-#define MSR_CORE_PERF_FIXED_CTR1        0x30a
-#define MSR_CORE_PERF_FIXED_CTR2        0x30b
-#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
-#define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
-#define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
-#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
-/* Geode defined MSRs */
-#define MSR_GEODE_BUSCONT_CONF0         0x1900
 #endif /* __ASM_MSR_H */
diff --git a/include/asm-i386/mtrr.h b/include/asm-i386/mtrr.h
index 07f063ae26ea..7e9c7ccbdcfe 100644
--- a/include/asm-i386/mtrr.h
+++ b/include/asm-i386/mtrr.h
@@ -69,6 +69,8 @@ struct mtrr_gentry
 /*  The following functions are for use by other drivers  */
 # ifdef CONFIG_MTRR
+extern void mtrr_save_fixed_ranges(void *);
+extern void mtrr_save_state(void);
 extern int mtrr_add (unsigned long base, unsigned long size,
                     unsigned int type, char increment);
 extern int mtrr_add_page (unsigned long base, unsigned long size,
@@ -79,6 +81,8 @@ extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
 extern void mtrr_ap_init(void);
 extern void mtrr_bp_init(void);
 #  else
+#define mtrr_save_fixed_ranges(arg) do {} while (0)
+#define mtrr_save_state() do {} while (0)
 static __inline__ int mtrr_add (unsigned long base, unsigned long size,
                                unsigned int type, char increment)
 {
diff --git a/include/asm-i386/nmi.h b/include/asm-i386/nmi.h
index b04333ea6f31..fb1e133efd9f 100644
--- a/include/asm-i386/nmi.h
+++ b/include/asm-i386/nmi.h
@@ -50,4 +50,12 @@ void __trigger_all_cpu_backtrace(void);
 #endif
+void lapic_watchdog_stop(void);
+int lapic_watchdog_init(unsigned nmi_hz);
+int lapic_wd_event(unsigned nmi_hz);
+unsigned lapic_adjust_nmi_hz(unsigned hz);
+int lapic_watchdog_ok(void);
+void disable_lapic_nmi_watchdog(void);
+void enable_lapic_nmi_watchdog(void);
 #endif /* ASM_NMI_H */
diff --git a/include/asm-i386/page.h b/include/asm-i386/page.h
index 7b19f454761d..818ac8bf01e2 100644
--- a/include/asm-i386/page.h
+++ b/include/asm-i386/page.h
@@ -12,7 +12,6 @@
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_X86_USE_3DNOW
 #include <asm/mmx.h>
@@ -42,26 +41,81 @@
 * These are used to make use of C type-checking..
 */
 extern int nx_enabled;
 #ifdef CONFIG_X86_PAE
 extern unsigned long long __supported_pte_mask;
 typedef struct { unsigned long pte_low, pte_high; } pte_t;
 typedef struct { unsigned long long pmd; } pmd_t;
 typedef struct { unsigned long long pgd; } pgd_t;
 typedef struct { unsigned long long pgprot; } pgprot_t;
-#define pmd_val(x)      ((x).pmd)
-#define pte_val(x)      ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+static inline unsigned long long native_pgd_val(pgd_t pgd)
-#define __pmd(x) ((pmd_t) { (x) } )
+{
+        return pgd.pgd;
+}
+static inline unsigned long long native_pmd_val(pmd_t pmd)
+{
+        return pmd.pmd;
+}
+static inline unsigned long long native_pte_val(pte_t pte)
+{
+        return pte.pte_low | ((unsigned long long)pte.pte_high << 32);
+}
+static inline pgd_t native_make_pgd(unsigned long long val)
+{
+        return (pgd_t) { val };
+}
+static inline pmd_t native_make_pmd(unsigned long long val)
+{
+        return (pmd_t) { val };
+}
+static inline pte_t native_make_pte(unsigned long long val)
+{
+        return (pte_t) { .pte_low = val, .pte_high = (val >> 32) } ;
+}
+#ifndef CONFIG_PARAVIRT
+#define pmd_val(x)      native_pmd_val(x)
+#define __pmd(x)        native_make_pmd(x)
+#endif
 #define HPAGE_SHIFT     21
 #include <asm-generic/pgtable-nopud.h>
-#else
+#else  /* !CONFIG_X86_PAE */
 typedef struct { unsigned long pte_low; } pte_t;
 typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
 #define boot_pte_t pte_t /* or would you rather have a typedef */
-#define pte_val(x)      ((x).pte_low)
+static inline unsigned long native_pgd_val(pgd_t pgd)
+{
+        return pgd.pgd;
+}
+static inline unsigned long native_pte_val(pte_t pte)
+{
+        return pte.pte_low;
+}
+static inline pgd_t native_make_pgd(unsigned long val)
+{
+        return (pgd_t) { val };
+}
+static inline pte_t native_make_pte(unsigned long val)
+{
+        return (pte_t) { .pte_low = val };
+}
 #define HPAGE_SHIFT     22
 #include <asm-generic/pgtable-nopmd.h>
-#endif
+#endif  /* CONFIG_X86_PAE */
 #define PTE_MASK        PAGE_MASK
 #ifdef CONFIG_HUGETLB_PAGE
@@ -71,13 +125,16 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
 #endif
-#define pgd_val(x)      ((x).pgd)
 #define pgprot_val(x)   ((x).pgprot)
-#define __pte(x) ((pte_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
+#ifndef CONFIG_PARAVIRT
+#define pgd_val(x)      native_pgd_val(x)
+#define __pgd(x)        native_make_pgd(x)
+#define pte_val(x)      native_pte_val(x)
+#define __pte(x)        native_make_pte(x)
+#endif
 #endif /* !__ASSEMBLY__ */
 /* to align the pointer to the (next) page boundary */
@@ -143,9 +200,7 @@ extern int page_is_ram(unsigned long pagenr);
 #include <asm-generic/memory_model.h>
 #include <asm-generic/page.h>
-#ifndef CONFIG_COMPAT_VDSO
 #define __HAVE_ARCH_GATE_AREA 1
-#endif
 #endif /* __KERNEL__ */
 #endif /* _I386_PAGE_H */
diff --git a/include/asm-i386/paravirt.h b/include/asm-i386/paravirt.h
index e63f1e444fcf..e2e7f98723c5 100644
--- a/include/asm-i386/paravirt.h
+++ b/include/asm-i386/paravirt.h
@@ -2,20 +2,9 @@
 #define __ASM_PARAVIRT_H
 /* Various instructions on x86 need to be replaced for
 * para-virtualization: those hooks are defined here. */
-#include <linux/linkage.h>
-#include <linux/stringify.h>
-#include <asm/page.h>
 #ifdef CONFIG_PARAVIRT
-/* These are the most performance critical ops, so we want to be able to patch
+#include <asm/page.h>
- * callers */
-#define PARAVIRT_IRQ_DISABLE 0
-#define PARAVIRT_IRQ_ENABLE 1
-#define PARAVIRT_RESTORE_FLAGS 2
-#define PARAVIRT_SAVE_FLAGS 3
-#define PARAVIRT_SAVE_FLAGS_IRQ_DISABLE 4
-#define PARAVIRT_INTERRUPT_RETURN 5
-#define PARAVIRT_STI_SYSEXIT 6
 /* Bitmask of what can be clobbered: usually at least eax. */
 #define CLBR_NONE 0x0
@@ -25,13 +14,29 @@
 #define CLBR_ANY 0x7
 #ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <linux/cpumask.h>
+#include <asm/kmap_types.h>
+struct page;
 struct thread_struct;
 struct Xgt_desc_struct;
 struct tss_struct;
 struct mm_struct;
+struct desc_struct;
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+        PARAVIRT_LAZY_NONE = 0,
+        PARAVIRT_LAZY_MMU = 1,
+        PARAVIRT_LAZY_CPU = 2,
+        PARAVIRT_LAZY_FLUSH = 3,
+};
 struct paravirt_ops
 {
        unsigned int kernel_rpl;
+        int shared_kernel_pmd;
        int paravirt_enabled;
        const char *name;
@@ -44,24 +49,33 @@ struct paravirt_ops
         */
        unsigned (*patch)(u8 type, u16 clobber, void *firstinsn, unsigned len);
+        /* Basic arch-specific setup */
        void (*arch_setup)(void);
        char *(*memory_setup)(void);
        void (*init_IRQ)(void);
+        void (*time_init)(void);
+        /*
+         * Called before/after init_mm pagetable setup. setup_start
+         * may reset %cr3, and may pre-install parts of the pagetable;
+         * pagetable setup is expected to preserve any existing
+         * mapping.
+         */
+        void (*pagetable_setup_start)(pgd_t *pgd_base);
+        void (*pagetable_setup_done)(pgd_t *pgd_base);
+        /* Print a banner to identify the environment */
        void (*banner)(void);
+        /* Set and set time of day */
        unsigned long (*get_wallclock)(void);
        int (*set_wallclock)(unsigned long);
-        void (*time_init)(void);
-        /* All the function pointers here are declared as "fastcall"
-           so that we get a specific register-based calling
-           convention.  This makes it easier to implement inline
-           assembler replacements. */
+        /* cpuid emulation, mostly so that caps bits can be disabled */
        void (*cpuid)(unsigned int *eax, unsigned int *ebx,
                      unsigned int *ecx, unsigned int *edx);
+        /* hooks for various privileged instructions */
        unsigned long (*get_debugreg)(int regno);
        void (*set_debugreg)(int regno, unsigned long value);
@@ -80,15 +94,23 @@ struct paravirt_ops
        unsigned long (*read_cr4)(void);
        void (*write_cr4)(unsigned long);
+        /*
+         * Get/set interrupt state.  save_fl and restore_fl are only
+         * expected to use X86_EFLAGS_IF; all other bits
+         * returned from save_fl are undefined, and may be ignored by
+         * restore_fl.
+         */
        unsigned long (*save_fl)(void);
        void (*restore_fl)(unsigned long);
        void (*irq_disable)(void);
        void (*irq_enable)(void);
        void (*safe_halt)(void);
        void (*halt)(void);
        void (*wbinvd)(void);
-        /* err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
+        /* MSR, PMC and TSR operations.
+           err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
        u64 (*read_msr)(unsigned int msr, int *err);
        int (*write_msr)(unsigned int msr, u64 val);
@@ -97,6 +119,7 @@ struct paravirt_ops
        u64 (*get_scheduled_cycles)(void);
        unsigned long (*get_cpu_khz)(void);
+        /* Segment descriptor handling */
        void (*load_tr_desc)(void);
        void (*load_gdt)(const struct Xgt_desc_struct *);
        void (*load_idt)(const struct Xgt_desc_struct *);
@@ -105,59 +128,98 @@ struct paravirt_ops
        void (*set_ldt)(const void *desc, unsigned entries);
        unsigned long (*store_tr)(void);
        void (*load_tls)(struct thread_struct *t, unsigned int cpu);
-        void (*write_ldt_entry)(void *dt, int entrynum,
+        void (*write_ldt_entry)(struct desc_struct *,
-                                         u32 low, u32 high);
+                                int entrynum, u32 low, u32 high);
-        void (*write_gdt_entry)(void *dt, int entrynum,
+        void (*write_gdt_entry)(struct desc_struct *,
-                                         u32 low, u32 high);
+                                int entrynum, u32 low, u32 high);
-        void (*write_idt_entry)(void *dt, int entrynum,
+        void (*write_idt_entry)(struct desc_struct *,
-                                         u32 low, u32 high);
+                                int entrynum, u32 low, u32 high);
-        void (*load_esp0)(struct tss_struct *tss,
+        void (*load_esp0)(struct tss_struct *tss, struct thread_struct *t);
-                                   struct thread_struct *thread);
        void (*set_iopl_mask)(unsigned mask);
        void (*io_delay)(void);
+        /*
+         * Hooks for intercepting the creation/use/destruction of an
+         * mm_struct.
+         */
+        void (*activate_mm)(struct mm_struct *prev,
+                            struct mm_struct *next);
+        void (*dup_mmap)(struct mm_struct *oldmm,
+                         struct mm_struct *mm);
+        void (*exit_mmap)(struct mm_struct *mm);
 #ifdef CONFIG_X86_LOCAL_APIC
+        /*
+         * Direct APIC operations, principally for VMI.  Ideally
+         * these shouldn't be in this interface.
+         */
        void (*apic_write)(unsigned long reg, unsigned long v);
        void (*apic_write_atomic)(unsigned long reg, unsigned long v);
        unsigned long (*apic_read)(unsigned long reg);
        void (*setup_boot_clock)(void);
        void (*setup_secondary_clock)(void);
+        void (*startup_ipi_hook)(int phys_apicid,
+                                 unsigned long start_eip,
+                                 unsigned long start_esp);
 #endif
+        /* TLB operations */
        void (*flush_tlb_user)(void);
        void (*flush_tlb_kernel)(void);
-        void (*flush_tlb_single)(u32 addr);
+        void (*flush_tlb_single)(unsigned long addr);
+        void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
-        void (*map_pt_hook)(int type, pte_t *va, u32 pfn);
+                                 unsigned long va);
+        /* Hooks for allocating/releasing pagetable pages */
        void (*alloc_pt)(u32 pfn);
        void (*alloc_pd)(u32 pfn);
        void (*alloc_pd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
        void (*release_pt)(u32 pfn);
        void (*release_pd)(u32 pfn);
+        /* Pagetable manipulation functions */
        void (*set_pte)(pte_t *ptep, pte_t pteval);
-        void (*set_pte_at)(struct mm_struct *mm, u32 addr, pte_t *ptep, pte_t pteval);
+        void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
+                           pte_t *ptep, pte_t pteval);
        void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
-        void (*pte_update)(struct mm_struct *mm, u32 addr, pte_t *ptep);
+        void (*pte_update)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
-        void (*pte_update_defer)(struct mm_struct *mm, u32 addr, pte_t *ptep);
+        void (*pte_update_defer)(struct mm_struct *mm,
+                                 unsigned long addr, pte_t *ptep);
+#ifdef CONFIG_HIGHPTE
+        void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
+#endif
 #ifdef CONFIG_X86_PAE
        void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
-        void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte);
+        void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte);
        void (*set_pud)(pud_t *pudp, pud_t pudval);
-        void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
+        void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
        void (*pmd_clear)(pmd_t *pmdp);
+        unsigned long long (*pte_val)(pte_t);
+        unsigned long long (*pmd_val)(pmd_t);
+        unsigned long long (*pgd_val)(pgd_t);
+        pte_t (*make_pte)(unsigned long long pte);
+        pmd_t (*make_pmd)(unsigned long long pmd);
+        pgd_t (*make_pgd)(unsigned long long pgd);
+#else
+        unsigned long (*pte_val)(pte_t);
+        unsigned long (*pgd_val)(pgd_t);
+        pte_t (*make_pte)(unsigned long pte);
+        pgd_t (*make_pgd)(unsigned long pgd);
 #endif
-        void (*set_lazy_mode)(int mode);
+        /* Set deferred update mode, used for batching operations. */
+        void (*set_lazy_mode)(enum paravirt_lazy_mode mode);
        /* These two are jmp to, not actually called. */
        void (*irq_enable_sysexit)(void);
        void (*iret)(void);
-        void (*startup_ipi_hook)(int phys_apicid, unsigned long start_eip, unsigned long start_esp);
 };
 /* Mark a paravirt probe function. */
@@ -167,23 +229,202 @@ struct paravirt_ops
 extern struct paravirt_ops paravirt_ops;
-#define paravirt_enabled() (paravirt_ops.paravirt_enabled)
+#define PARAVIRT_PATCH(x)                                       \
+        (offsetof(struct paravirt_ops, x) / sizeof(void *))
+#define paravirt_type(type)                                     \
+        [paravirt_typenum] "i" (PARAVIRT_PATCH(type))
+#define paravirt_clobber(clobber)               \
+        [paravirt_clobber] "i" (clobber)
+/*
+ * Generate some code, and mark it as patchable by the
+ * apply_paravirt() alternate instruction patcher.
+ */
+#define _paravirt_alt(insn_string, type, clobber)       \
+        "771:\n\t" insn_string "\n" "772:\n"            \
+        ".pushsection .parainstructions,\"a\"\n"        \
+        "  .long 771b\n"                                \
+        "  .byte " type "\n"                            \
+        "  .byte 772b-771b\n"                           \
+        "  .short " clobber "\n"                        \
+        ".popsection\n"
+/* Generate patchable code, with the default asm parameters. */
+#define paravirt_alt(insn_string)                                       \
+        _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
+unsigned paravirt_patch_nop(void);
+unsigned paravirt_patch_ignore(unsigned len);
+unsigned paravirt_patch_call(void *target, u16 tgt_clobbers,
+                             void *site, u16 site_clobbers,
+                             unsigned len);
+unsigned paravirt_patch_jmp(void *target, void *site, unsigned len);
+unsigned paravirt_patch_default(u8 type, u16 clobbers, void *site, unsigned len);
+unsigned paravirt_patch_insns(void *site, unsigned len,
+                              const char *start, const char *end);
+/*
+ * This generates an indirect call based on the operation type number.
+ * The type number, computed in PARAVIRT_PATCH, is derived from the
+ * offset into the paravirt_ops structure, and can therefore be freely
+ * converted back into a structure offset.
+ */
+#define PARAVIRT_CALL   "call *(paravirt_ops+%c[paravirt_typenum]*4);"
+/*
+ * These macros are intended to wrap calls into a paravirt_ops
+ * operation, so that they can be later identified and patched at
+ * runtime.
+ *
+ * Normally, a call to a pv_op function is a simple indirect call:
+ * (paravirt_ops.operations)(args...).
+ *
+ * Unfortunately, this is a relatively slow operation for modern CPUs,
+ * because it cannot necessarily determine what the destination
+ * address is.  In this case, the address is a runtime constant, so at
+ * the very least we can patch the call to e a simple direct call, or
+ * ideally, patch an inline implementation into the callsite.  (Direct
+ * calls are essentially free, because the call and return addresses
+ * are completely predictable.)
+ *
+ * These macros rely on the standard gcc "regparm(3)" calling
+ * convention, in which the first three arguments are placed in %eax,
+ * %edx, %ecx (in that order), and the remaining arguments are placed
+ * on the stack.  All caller-save registers (eax,edx,ecx) are expected
+ * to be modified (either clobbered or used for return values).
+ *
+ * The call instruction itself is marked by placing its start address
+ * and size into the .parainstructions section, so that
+ * apply_paravirt() in arch/i386/kernel/alternative.c can do the
+ * appropriate patching under the control of the backend paravirt_ops
+ * implementation.
+ *
+ * Unfortunately there's no way to get gcc to generate the args setup
+ * for the call, and then allow the call itself to be generated by an
+ * inline asm.  Because of this, we must do the complete arg setup and
+ * return value handling from within these macros.  This is fairly
+ * cumbersome.
+ *
+ * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
+ * It could be extended to more arguments, but there would be little
+ * to be gained from that.  For each number of arguments, there are
+ * the two VCALL and CALL variants for void and non-void functions.
+ *
+ * When there is a return value, the invoker of the macro must specify
+ * the return type.  The macro then uses sizeof() on that type to
+ * determine whether its a 32 or 64 bit value, and places the return
+ * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
+ * 64-bit).
+ *
+ * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
+ * in low,high order.
+ *
+ * Small structures are passed and returned in registers.  The macro
+ * calling convention can't directly deal with this, so the wrapper
+ * functions must do this.
+ *
+ * These PVOP_* macros are only defined within this header.  This
+ * means that all uses must be wrapped in inline functions.  This also
+ * makes sure the incoming and outgoing types are always correct.
+ */
+#define __PVOP_CALL(rettype, op, pre, post, ...)                        \
+        ({                                                              \
+                rettype __ret;                                          \
+                unsigned long __eax, __edx, __ecx;                      \
+                if (sizeof(rettype) > sizeof(unsigned long)) {          \
+                        asm volatile(pre                                \
+                                     paravirt_alt(PARAVIRT_CALL)        \
+                                     post                               \
+                                     : "=a" (__eax), "=d" (__edx),      \
+                                       "=c" (__ecx)                     \
+                                     : paravirt_type(op),               \
+                                       paravirt_clobber(CLBR_ANY),      \
+                                       ##__VA_ARGS__                    \
+                                     : "memory", "cc");                 \
+                        __ret = (rettype)((((u64)__edx) << 32) | __eax); \
+                } else {                                                \
+                        asm volatile(pre                                \
+                                     paravirt_alt(PARAVIRT_CALL)        \
+                                     post                               \
+                                     : "=a" (__eax), "=d" (__edx),      \
+                                       "=c" (__ecx)                     \
+                                     : paravirt_type(op),               \
+                                       paravirt_clobber(CLBR_ANY),      \
+                                       ##__VA_ARGS__                    \
+                                     : "memory", "cc");                 \
+                        __ret = (rettype)__eax;                         \
+                }                                                       \
+                __ret;                                                  \
+        })
+#define __PVOP_VCALL(op, pre, post, ...)                                \
+        ({                                                              \
+                unsigned long __eax, __edx, __ecx;                      \
+                asm volatile(pre                                        \
+                             paravirt_alt(PARAVIRT_CALL)                \
+                             post                                       \
+                             : "=a" (__eax), "=d" (__edx), "=c" (__ecx) \
+                             : paravirt_type(op),                       \
+                               paravirt_clobber(CLBR_ANY),              \
+                               ##__VA_ARGS__                            \
+                             : "memory", "cc");                         \
+        })
+#define PVOP_CALL0(rettype, op)                                         \
+        __PVOP_CALL(rettype, op, "", "")
+#define PVOP_VCALL0(op)                                                 \
+        __PVOP_VCALL(op, "", "")
+#define PVOP_CALL1(rettype, op, arg1)                                   \
+        __PVOP_CALL(rettype, op, "", "", "0" ((u32)(arg1)))
+#define PVOP_VCALL1(op, arg1)                                           \
+        __PVOP_VCALL(op, "", "", "0" ((u32)(arg1)))
+#define PVOP_CALL2(rettype, op, arg1, arg2)                             \
+        __PVOP_CALL(rettype, op, "", "", "0" ((u32)(arg1)), "1" ((u32)(arg2)))
+#define PVOP_VCALL2(op, arg1, arg2)                                     \
+        __PVOP_VCALL(op, "", "", "0" ((u32)(arg1)), "1" ((u32)(arg2)))
+#define PVOP_CALL3(rettype, op, arg1, arg2, arg3)                       \
+        __PVOP_CALL(rettype, op, "", "", "0" ((u32)(arg1)),             \
+                    "1"((u32)(arg2)), "2"((u32)(arg3)))
+#define PVOP_VCALL3(op, arg1, arg2, arg3)                               \
+        __PVOP_VCALL(op, "", "", "0" ((u32)(arg1)), "1"((u32)(arg2)),   \
+                     "2"((u32)(arg3)))
+#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)                 \
+        __PVOP_CALL(rettype, op,                                        \
+                    "push %[_arg4];", "lea 4(%%esp),%%esp;",            \
+                    "0" ((u32)(arg1)), "1" ((u32)(arg2)),               \
+                    "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
+#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)                         \
+        __PVOP_VCALL(op,                                                \
+                    "push %[_arg4];", "lea 4(%%esp),%%esp;",            \
+                    "0" ((u32)(arg1)), "1" ((u32)(arg2)),               \
+                    "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
+static inline int paravirt_enabled(void)
+{
+        return paravirt_ops.paravirt_enabled;
+}
 static inline void load_esp0(struct tss_struct *tss,
                             struct thread_struct *thread)
 {
-        paravirt_ops.load_esp0(tss, thread);
+        PVOP_VCALL2(load_esp0, tss, thread);
 }
 #define ARCH_SETUP                      paravirt_ops.arch_setup();
 static inline unsigned long get_wallclock(void)
 {
-        return paravirt_ops.get_wallclock();
+        return PVOP_CALL0(unsigned long, get_wallclock);
 }
 static inline int set_wallclock(unsigned long nowtime)
 {
-        return paravirt_ops.set_wallclock(nowtime);
+        return PVOP_CALL1(int, set_wallclock, nowtime);
 }
 static inline void (*choose_time_init(void))(void)
@@ -195,113 +436,208 @@ static inline void (*choose_time_init(void))(void)
 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
                           unsigned int *ecx, unsigned int *edx)
 {
-        paravirt_ops.cpuid(eax, ebx, ecx, edx);
+        PVOP_VCALL4(cpuid, eax, ebx, ecx, edx);
 }
 /*
 * These special macros can be used to get or set a debugging register
 */
-#define get_debugreg(var, reg) var = paravirt_ops.get_debugreg(reg)
+static inline unsigned long paravirt_get_debugreg(int reg)
-#define set_debugreg(val, reg) paravirt_ops.set_debugreg(reg, val)
+{
+        return PVOP_CALL1(unsigned long, get_debugreg, reg);
+}
+#define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
+static inline void set_debugreg(unsigned long val, int reg)
+{
+        PVOP_VCALL2(set_debugreg, reg, val);
+}
+static inline void clts(void)
+{
+        PVOP_VCALL0(clts);
+}
-#define clts() paravirt_ops.clts()
+static inline unsigned long read_cr0(void)
+{
+        return PVOP_CALL0(unsigned long, read_cr0);
+}
-#define read_cr0() paravirt_ops.read_cr0()
+static inline void write_cr0(unsigned long x)
-#define write_cr0(x) paravirt_ops.write_cr0(x)
+{
+        PVOP_VCALL1(write_cr0, x);
+}
-#define read_cr2() paravirt_ops.read_cr2()
+static inline unsigned long read_cr2(void)
-#define write_cr2(x) paravirt_ops.write_cr2(x)
+{
+        return PVOP_CALL0(unsigned long, read_cr2);
+}
-#define read_cr3() paravirt_ops.read_cr3()
+static inline void write_cr2(unsigned long x)
-#define write_cr3(x) paravirt_ops.write_cr3(x)
+{
+        PVOP_VCALL1(write_cr2, x);
+}
-#define read_cr4() paravirt_ops.read_cr4()
+static inline unsigned long read_cr3(void)
-#define read_cr4_safe(x) paravirt_ops.read_cr4_safe()
+{
-#define write_cr4(x) paravirt_ops.write_cr4(x)
+        return PVOP_CALL0(unsigned long, read_cr3);
+}
+static inline void write_cr3(unsigned long x)
+{
+        PVOP_VCALL1(write_cr3, x);
+}
+static inline unsigned long read_cr4(void)
+{
+        return PVOP_CALL0(unsigned long, read_cr4);
+}
+static inline unsigned long read_cr4_safe(void)
+{
+        return PVOP_CALL0(unsigned long, read_cr4_safe);
+}
+static inline void write_cr4(unsigned long x)
+{
+        PVOP_VCALL1(write_cr4, x);
+}
 static inline void raw_safe_halt(void)
 {
-        paravirt_ops.safe_halt();
+        PVOP_VCALL0(safe_halt);
 }
 static inline void halt(void)
 {
-        paravirt_ops.safe_halt();
+        PVOP_VCALL0(safe_halt);
+}
+static inline void wbinvd(void)
+{
+        PVOP_VCALL0(wbinvd);
 }
-#define wbinvd() paravirt_ops.wbinvd()
 #define get_kernel_rpl()  (paravirt_ops.kernel_rpl)
-#define rdmsr(msr,val1,val2) do {                               \
+static inline u64 paravirt_read_msr(unsigned msr, int *err)
-        int _err;                                               \
+{
-        u64 _l = paravirt_ops.read_msr(msr,&_err);              \
+        return PVOP_CALL2(u64, read_msr, msr, err);
-        val1 = (u32)_l;                                         \
+}
-        val2 = _l >> 32;                                        \
+static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
+{
+        return PVOP_CALL3(int, write_msr, msr, low, high);
+}
+/* These should all do BUG_ON(_err), but our headers are too tangled. */
+#define rdmsr(msr,val1,val2) do {               \
+        int _err;                               \
+        u64 _l = paravirt_read_msr(msr, &_err); \
+        val1 = (u32)_l;                         \
+        val2 = _l >> 32;                        \
 } while(0)
-#define wrmsr(msr,val1,val2) do {                               \
+#define wrmsr(msr,val1,val2) do {               \
-        u64 _l = ((u64)(val2) << 32) | (val1);                  \
+        paravirt_write_msr(msr, val1, val2);    \
-        paravirt_ops.write_msr((msr), _l);                      \
 } while(0)
-#define rdmsrl(msr,val) do {                                    \
+#define rdmsrl(msr,val) do {                    \
-        int _err;                                               \
+        int _err;                               \
-        val = paravirt_ops.read_msr((msr),&_err);               \
+        val = paravirt_read_msr(msr, &_err);    \
 } while(0)
-#define wrmsrl(msr,val) (paravirt_ops.write_msr((msr),(val)))
+#define wrmsrl(msr,val)         ((void)paravirt_write_msr(msr, val, 0))
-#define wrmsr_safe(msr,a,b) ({                                  \
+#define wrmsr_safe(msr,a,b)     paravirt_write_msr(msr, a, b)
-        u64 _l = ((u64)(b) << 32) | (a);                        \
-        paravirt_ops.write_msr((msr),_l);                       \
-})
 /* rdmsr with exception handling */
-#define rdmsr_safe(msr,a,b) ({                                  \
+#define rdmsr_safe(msr,a,b) ({                  \
-        int _err;                                               \
+        int _err;                               \
-        u64 _l = paravirt_ops.read_msr(msr,&_err);              \
+        u64 _l = paravirt_read_msr(msr, &_err); \
-        (*a) = (u32)_l;                                         \
+        (*a) = (u32)_l;                         \
-        (*b) = _l >> 32;                                        \
+        (*b) = _l >> 32;                        \
        _err; })
-#define rdtsc(low,high) do {                                    \
-        u64 _l = paravirt_ops.read_tsc();                       \
+static inline u64 paravirt_read_tsc(void)
-        low = (u32)_l;                                          \
+{
-        high = _l >> 32;                                        \
+        return PVOP_CALL0(u64, read_tsc);
+}
+#define rdtsc(low,high) do {                    \
+        u64 _l = paravirt_read_tsc();           \
+        low = (u32)_l;                          \
+        high = _l >> 32;                        \
 } while(0)
-#define rdtscl(low) do {                                        \
+#define rdtscl(low) do {                        \
-        u64 _l = paravirt_ops.read_tsc();                       \
+        u64 _l = paravirt_read_tsc();           \
-        low = (int)_l;                                          \
+        low = (int)_l;                          \
 } while(0)
-#define rdtscll(val) (val = paravirt_ops.read_tsc())
+#define rdtscll(val) (val = paravirt_read_tsc())
 #define get_scheduled_cycles(val) (val = paravirt_ops.get_scheduled_cycles())
 #define calculate_cpu_khz() (paravirt_ops.get_cpu_khz())
 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
-#define rdpmc(counter,low,high) do {                            \
+static inline unsigned long long paravirt_read_pmc(int counter)
-        u64 _l = paravirt_ops.read_pmc();                       \
+{
-        low = (u32)_l;                                          \
+        return PVOP_CALL1(u64, read_pmc, counter);
-        high = _l >> 32;                                        \
+}
+#define rdpmc(counter,low,high) do {            \
+        u64 _l = paravirt_read_pmc(counter);    \
+        low = (u32)_l;                          \
+        high = _l >> 32;                        \
 } while(0)
-#define load_TR_desc() (paravirt_ops.load_tr_desc())
+static inline void load_TR_desc(void)
-#define load_gdt(dtr) (paravirt_ops.load_gdt(dtr))
+{
-#define load_idt(dtr) (paravirt_ops.load_idt(dtr))
+        PVOP_VCALL0(load_tr_desc);
-#define set_ldt(addr, entries) (paravirt_ops.set_ldt((addr), (entries)))
+}
-#define store_gdt(dtr) (paravirt_ops.store_gdt(dtr))
+static inline void load_gdt(const struct Xgt_desc_struct *dtr)
-#define store_idt(dtr) (paravirt_ops.store_idt(dtr))
+{
-#define store_tr(tr) ((tr) = paravirt_ops.store_tr())
+        PVOP_VCALL1(load_gdt, dtr);
-#define load_TLS(t,cpu) (paravirt_ops.load_tls((t),(cpu)))
+}
-#define write_ldt_entry(dt, entry, low, high)                           \
+static inline void load_idt(const struct Xgt_desc_struct *dtr)
-        (paravirt_ops.write_ldt_entry((dt), (entry), (low), (high)))
+{
-#define write_gdt_entry(dt, entry, low, high)                           \
+        PVOP_VCALL1(load_idt, dtr);
-        (paravirt_ops.write_gdt_entry((dt), (entry), (low), (high)))
+}
-#define write_idt_entry(dt, entry, low, high)                           \
+static inline void set_ldt(const void *addr, unsigned entries)
-        (paravirt_ops.write_idt_entry((dt), (entry), (low), (high)))
+{
-#define set_iopl_mask(mask) (paravirt_ops.set_iopl_mask(mask))
+        PVOP_VCALL2(set_ldt, addr, entries);
+}
+static inline void store_gdt(struct Xgt_desc_struct *dtr)
+{
+        PVOP_VCALL1(store_gdt, dtr);
+}
+static inline void store_idt(struct Xgt_desc_struct *dtr)
+{
+        PVOP_VCALL1(store_idt, dtr);
+}
+static inline unsigned long paravirt_store_tr(void)
+{
+        return PVOP_CALL0(unsigned long, store_tr);
+}
+#define store_tr(tr)    ((tr) = paravirt_store_tr())
+static inline void load_TLS(struct thread_struct *t, unsigned cpu)
+{
+        PVOP_VCALL2(load_tls, t, cpu);
+}
+static inline void write_ldt_entry(void *dt, int entry, u32 low, u32 high)
+{
+        PVOP_VCALL4(write_ldt_entry, dt, entry, low, high);
+}
+static inline void write_gdt_entry(void *dt, int entry, u32 low, u32 high)
+{
+        PVOP_VCALL4(write_gdt_entry, dt, entry, low, high);
+}
+static inline void write_idt_entry(void *dt, int entry, u32 low, u32 high)
+{
+        PVOP_VCALL4(write_idt_entry, dt, entry, low, high);
+}
+static inline void set_iopl_mask(unsigned mask)
+{
+        PVOP_VCALL1(set_iopl_mask, mask);
+}
 /* The paravirtualized I/O functions */
 static inline void slow_down_io(void) {
@@ -319,215 +655,390 @@ static inline void slow_down_io(void) {
 */
 static inline void apic_write(unsigned long reg, unsigned long v)
 {
-        paravirt_ops.apic_write(reg,v);
+        PVOP_VCALL2(apic_write, reg, v);
 }
 static inline void apic_write_atomic(unsigned long reg, unsigned long v)
 {
-        paravirt_ops.apic_write_atomic(reg,v);
+        PVOP_VCALL2(apic_write_atomic, reg, v);
 }
 static inline unsigned long apic_read(unsigned long reg)
 {
-        return paravirt_ops.apic_read(reg);
+        return PVOP_CALL1(unsigned long, apic_read, reg);
 }
 static inline void setup_boot_clock(void)
 {
-        paravirt_ops.setup_boot_clock();
+        PVOP_VCALL0(setup_boot_clock);
 }
 static inline void setup_secondary_clock(void)
 {
-        paravirt_ops.setup_secondary_clock();
+        PVOP_VCALL0(setup_secondary_clock);
 }
 #endif
+static inline void paravirt_pagetable_setup_start(pgd_t *base)
+{
+        if (paravirt_ops.pagetable_setup_start)
+                (*paravirt_ops.pagetable_setup_start)(base);
+}
+static inline void paravirt_pagetable_setup_done(pgd_t *base)
+{
+        if (paravirt_ops.pagetable_setup_done)
+                (*paravirt_ops.pagetable_setup_done)(base);
+}
 #ifdef CONFIG_SMP
 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
                                    unsigned long start_esp)
 {
-        return paravirt_ops.startup_ipi_hook(phys_apicid, start_eip, start_esp);
+        PVOP_VCALL3(startup_ipi_hook, phys_apicid, start_eip, start_esp);
 }
 #endif
-#define __flush_tlb() paravirt_ops.flush_tlb_user()
+static inline void paravirt_activate_mm(struct mm_struct *prev,
-#define __flush_tlb_global() paravirt_ops.flush_tlb_kernel()
+                                        struct mm_struct *next)
-#define __flush_tlb_single(addr) paravirt_ops.flush_tlb_single(addr)
+{
+        PVOP_VCALL2(activate_mm, prev, next);
+}
-#define paravirt_map_pt_hook(type, va, pfn) paravirt_ops.map_pt_hook(type, va, pfn)
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+        PVOP_VCALL2(dup_mmap, oldmm, mm);
+}
-#define paravirt_alloc_pt(pfn) paravirt_ops.alloc_pt(pfn)
+static inline void arch_exit_mmap(struct mm_struct *mm)
-#define paravirt_release_pt(pfn) paravirt_ops.release_pt(pfn)
+{
+        PVOP_VCALL1(exit_mmap, mm);
+}
-#define paravirt_alloc_pd(pfn) paravirt_ops.alloc_pd(pfn)
+static inline void __flush_tlb(void)
-#define paravirt_alloc_pd_clone(pfn, clonepfn, start, count) \
+{
-        paravirt_ops.alloc_pd_clone(pfn, clonepfn, start, count)
+        PVOP_VCALL0(flush_tlb_user);
-#define paravirt_release_pd(pfn) paravirt_ops.release_pd(pfn)
+}
+static inline void __flush_tlb_global(void)
+{
+        PVOP_VCALL0(flush_tlb_kernel);
+}
+static inline void __flush_tlb_single(unsigned long addr)
+{
+        PVOP_VCALL1(flush_tlb_single, addr);
+}
-static inline void set_pte(pte_t *ptep, pte_t pteval)
+static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
+                                    unsigned long va)
 {
-        paravirt_ops.set_pte(ptep, pteval);
+        PVOP_VCALL3(flush_tlb_others, &cpumask, mm, va);
 }
-static inline void set_pte_at(struct mm_struct *mm, u32 addr, pte_t *ptep, pte_t pteval)
+static inline void paravirt_alloc_pt(unsigned pfn)
 {
-        paravirt_ops.set_pte_at(mm, addr, ptep, pteval);
+        PVOP_VCALL1(alloc_pt, pfn);
+}
+static inline void paravirt_release_pt(unsigned pfn)
+{
+        PVOP_VCALL1(release_pt, pfn);
 }
-static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval)
+static inline void paravirt_alloc_pd(unsigned pfn)
 {
-        paravirt_ops.set_pmd(pmdp, pmdval);
+        PVOP_VCALL1(alloc_pd, pfn);
 }
-static inline void pte_update(struct mm_struct *mm, u32 addr, pte_t *ptep)
+static inline void paravirt_alloc_pd_clone(unsigned pfn, unsigned clonepfn,
+                                           unsigned start, unsigned count)
 {
-        paravirt_ops.pte_update(mm, addr, ptep);
+        PVOP_VCALL4(alloc_pd_clone, pfn, clonepfn, start, count);
+}
+static inline void paravirt_release_pd(unsigned pfn)
+{
+        PVOP_VCALL1(release_pd, pfn);
 }
-static inline void pte_update_defer(struct mm_struct *mm, u32 addr, pte_t *ptep)
+#ifdef CONFIG_HIGHPTE
+static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
 {
-        paravirt_ops.pte_update_defer(mm, addr, ptep);
+        unsigned long ret;
+        ret = PVOP_CALL2(unsigned long, kmap_atomic_pte, page, type);
+        return (void *)ret;
+}
+#endif
+static inline void pte_update(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep)
+{
+        PVOP_VCALL3(pte_update, mm, addr, ptep);
+}
+static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
+                                    pte_t *ptep)
+{
+        PVOP_VCALL3(pte_update_defer, mm, addr, ptep);
 }
 #ifdef CONFIG_X86_PAE
+static inline pte_t __pte(unsigned long long val)
+{
+        unsigned long long ret = PVOP_CALL2(unsigned long long, make_pte,
+                                            val, val >> 32);
+        return (pte_t) { ret, ret >> 32 };
+}
+static inline pmd_t __pmd(unsigned long long val)
+{
+        return (pmd_t) { PVOP_CALL2(unsigned long long, make_pmd, val, val >> 32) };
+}
+static inline pgd_t __pgd(unsigned long long val)
+{
+        return (pgd_t) { PVOP_CALL2(unsigned long long, make_pgd, val, val >> 32) };
+}
+static inline unsigned long long pte_val(pte_t x)
+{
+        return PVOP_CALL2(unsigned long long, pte_val, x.pte_low, x.pte_high);
+}
+static inline unsigned long long pmd_val(pmd_t x)
+{
+        return PVOP_CALL2(unsigned long long, pmd_val, x.pmd, x.pmd >> 32);
+}
+static inline unsigned long long pgd_val(pgd_t x)
+{
+        return PVOP_CALL2(unsigned long long, pgd_val, x.pgd, x.pgd >> 32);
+}
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        PVOP_VCALL3(set_pte, ptep, pteval.pte_low, pteval.pte_high);
+}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pteval)
+{
+        /* 5 arg words */
+        paravirt_ops.set_pte_at(mm, addr, ptep, pteval);
+}
 static inline void set_pte_atomic(pte_t *ptep, pte_t pteval)
 {
-        paravirt_ops.set_pte_atomic(ptep, pteval);
+        PVOP_VCALL3(set_pte_atomic, ptep, pteval.pte_low, pteval.pte_high);
 }
-static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
 {
+        /* 5 arg words */
        paravirt_ops.set_pte_present(mm, addr, ptep, pte);
 }
+static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval)
+{
+        PVOP_VCALL3(set_pmd, pmdp, pmdval.pmd, pmdval.pmd >> 32);
+}
 static inline void set_pud(pud_t *pudp, pud_t pudval)
 {
-        paravirt_ops.set_pud(pudp, pudval);
+        PVOP_VCALL3(set_pud, pudp, pudval.pgd.pgd, pudval.pgd.pgd >> 32);
 }
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
-        paravirt_ops.pte_clear(mm, addr, ptep);
+        PVOP_VCALL3(pte_clear, mm, addr, ptep);
 }
 static inline void pmd_clear(pmd_t *pmdp)
 {
-        paravirt_ops.pmd_clear(pmdp);
+        PVOP_VCALL1(pmd_clear, pmdp);
 }
-#endif
-/* Lazy mode for batching updates / context switch */
+#else  /* !CONFIG_X86_PAE */
-#define PARAVIRT_LAZY_NONE 0
-#define PARAVIRT_LAZY_MMU  1
+static inline pte_t __pte(unsigned long val)
-#define PARAVIRT_LAZY_CPU  2
+{
-#define PARAVIRT_LAZY_FLUSH 3
+        return (pte_t) { PVOP_CALL1(unsigned long, make_pte, val) };
+}
+static inline pgd_t __pgd(unsigned long val)
+{
+        return (pgd_t) { PVOP_CALL1(unsigned long, make_pgd, val) };
+}
+static inline unsigned long pte_val(pte_t x)
+{
+        return PVOP_CALL1(unsigned long, pte_val, x.pte_low);
+}
+static inline unsigned long pgd_val(pgd_t x)
+{
+        return PVOP_CALL1(unsigned long, pgd_val, x.pgd);
+}
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        PVOP_VCALL2(set_pte, ptep, pteval.pte_low);
+}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pteval)
+{
+        PVOP_VCALL4(set_pte_at, mm, addr, ptep, pteval.pte_low);
+}
+static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval)
+{
+        PVOP_VCALL2(set_pmd, pmdp, pmdval.pud.pgd.pgd);
+}
+#endif  /* CONFIG_X86_PAE */
 #define  __HAVE_ARCH_ENTER_LAZY_CPU_MODE
-#define arch_enter_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_CPU)
+static inline void arch_enter_lazy_cpu_mode(void)
-#define arch_leave_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_NONE)
+{
-#define arch_flush_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_FLUSH)
+        PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_CPU);
+}
+static inline void arch_leave_lazy_cpu_mode(void)
+{
+        PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_NONE);
+}
+static inline void arch_flush_lazy_cpu_mode(void)
+{
+        PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_FLUSH);
+}
 #define  __HAVE_ARCH_ENTER_LAZY_MMU_MODE
-#define arch_enter_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_MMU)
+static inline void arch_enter_lazy_mmu_mode(void)
-#define arch_leave_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_NONE)
+{
-#define arch_flush_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_FLUSH)
+        PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_MMU);
+}
+static inline void arch_leave_lazy_mmu_mode(void)
+{
+        PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_NONE);
+}
+static inline void arch_flush_lazy_mmu_mode(void)
+{
+        PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_FLUSH);
+}
+void _paravirt_nop(void);
+#define paravirt_nop    ((void *)_paravirt_nop)
 /* These all sit in the .parainstructions section to tell us what to patch. */
-struct paravirt_patch {
+struct paravirt_patch_site {
        u8 *instr;              /* original instructions */
        u8 instrtype;           /* type of this instruction */
        u8 len;                 /* length of original instruction */
        u16 clobbers;           /* what registers you may clobber */
 };
-#define paravirt_alt(insn_string, typenum, clobber)     \
+extern struct paravirt_patch_site __parainstructions[],
-        "771:\n\t" insn_string "\n" "772:\n"            \
+        __parainstructions_end[];
-        ".pushsection .parainstructions,\"a\"\n"        \
-        "  .long 771b\n"                                \
-        "  .byte " __stringify(typenum) "\n"            \
-        "  .byte 772b-771b\n"                           \
-        "  .short " __stringify(clobber) "\n"           \
-        ".popsection"
 static inline unsigned long __raw_local_save_flags(void)
 {
        unsigned long f;
-        __asm__ __volatile__(paravirt_alt( "pushl %%ecx; pushl %%edx;"
+        asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;"
-                                           "call *%1;"
+                                  PARAVIRT_CALL
-                                           "popl %%edx; popl %%ecx",
+                                  "popl %%edx; popl %%ecx")
-                                          PARAVIRT_SAVE_FLAGS, CLBR_NONE)
+                     : "=a"(f)
-                             : "=a"(f): "m"(paravirt_ops.save_fl)
+                     : paravirt_type(save_fl),
-                             : "memory", "cc");
+                       paravirt_clobber(CLBR_EAX)
+                     : "memory", "cc");
        return f;
 }
 static inline void raw_local_irq_restore(unsigned long f)
 {
-        __asm__ __volatile__(paravirt_alt( "pushl %%ecx; pushl %%edx;"
+        asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;"
-                                           "call *%1;"
+                                  PARAVIRT_CALL
-                                           "popl %%edx; popl %%ecx",
+                                  "popl %%edx; popl %%ecx")
-                                          PARAVIRT_RESTORE_FLAGS, CLBR_EAX)
+                     : "=a"(f)
-                             : "=a"(f) : "m" (paravirt_ops.restore_fl), "0"(f)
+                     : "0"(f),
-                             : "memory", "cc");
+                       paravirt_type(restore_fl),
+                       paravirt_clobber(CLBR_EAX)
+                     : "memory", "cc");
 }
 static inline void raw_local_irq_disable(void)
 {
-        __asm__ __volatile__(paravirt_alt( "pushl %%ecx; pushl %%edx;"
+        asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;"
-                                           "call *%0;"
+                                  PARAVIRT_CALL
-                                           "popl %%edx; popl %%ecx",
+                                  "popl %%edx; popl %%ecx")
-                                          PARAVIRT_IRQ_DISABLE, CLBR_EAX)
+                     :
-                             : : "m" (paravirt_ops.irq_disable)
+                     : paravirt_type(irq_disable),
-                             : "memory", "eax", "cc");
+                       paravirt_clobber(CLBR_EAX)
+                     : "memory", "eax", "cc");
 }
 static inline void raw_local_irq_enable(void)
 {
-        __asm__ __volatile__(paravirt_alt( "pushl %%ecx; pushl %%edx;"
+        asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;"
-                                           "call *%0;"
+                                  PARAVIRT_CALL
-                                           "popl %%edx; popl %%ecx",
+                                  "popl %%edx; popl %%ecx")
-                                          PARAVIRT_IRQ_ENABLE, CLBR_EAX)
+                     :
-                             : : "m" (paravirt_ops.irq_enable)
+                     : paravirt_type(irq_enable),
-                             : "memory", "eax", "cc");
+                       paravirt_clobber(CLBR_EAX)
+                     : "memory", "eax", "cc");
 }
 static inline unsigned long __raw_local_irq_save(void)
 {
        unsigned long f;
-        __asm__ __volatile__(paravirt_alt( "pushl %%ecx; pushl %%edx;"
+        f = __raw_local_save_flags();
-                                           "call *%1; pushl %%eax;"
+        raw_local_irq_disable();
-                                           "call *%2; popl %%eax;"
-                                           "popl %%edx; popl %%ecx",
-                                          PARAVIRT_SAVE_FLAGS_IRQ_DISABLE,
-                                          CLBR_NONE)
-                             : "=a"(f)
-                             : "m" (paravirt_ops.save_fl),
-                               "m" (paravirt_ops.irq_disable)
-                             : "memory", "cc");
        return f;
 }
-#define CLI_STRING paravirt_alt("pushl %%ecx; pushl %%edx;"             \
+#define CLI_STRING                                                      \
-                     "call *paravirt_ops+%c[irq_disable];"              \
+        _paravirt_alt("pushl %%ecx; pushl %%edx;"                       \
-                     "popl %%edx; popl %%ecx",                          \
+                      "call *paravirt_ops+%c[paravirt_cli_type]*4;"     \
-                     PARAVIRT_IRQ_DISABLE, CLBR_EAX)
+                      "popl %%edx; popl %%ecx",                         \
+                      "%c[paravirt_cli_type]", "%c[paravirt_clobber]")
+#define STI_STRING                                                      \
+        _paravirt_alt("pushl %%ecx; pushl %%edx;"                       \
+                      "call *paravirt_ops+%c[paravirt_sti_type]*4;"     \
+                      "popl %%edx; popl %%ecx",                         \
+                      "%c[paravirt_sti_type]", "%c[paravirt_clobber]")
-#define STI_STRING paravirt_alt("pushl %%ecx; pushl %%edx;"             \
-                     "call *paravirt_ops+%c[irq_enable];"               \
-                     "popl %%edx; popl %%ecx",                          \
-                     PARAVIRT_IRQ_ENABLE, CLBR_EAX)
 #define CLI_STI_CLOBBERS , "%eax"
-#define CLI_STI_INPUT_ARGS \
+#define CLI_STI_INPUT_ARGS                                              \
        ,                                                               \
-        [irq_disable] "i" (offsetof(struct paravirt_ops, irq_disable)), \
+        [paravirt_cli_type] "i" (PARAVIRT_PATCH(irq_disable)),          \
-        [irq_enable] "i" (offsetof(struct paravirt_ops, irq_enable))
+        [paravirt_sti_type] "i" (PARAVIRT_PATCH(irq_enable)),           \
+        paravirt_clobber(CLBR_EAX)
+/* Make sure as little as possible of this mess escapes. */
+#undef PARAVIRT_CALL
+#undef __PVOP_CALL
+#undef __PVOP_VCALL
+#undef PVOP_VCALL0
+#undef PVOP_CALL0
+#undef PVOP_VCALL1
+#undef PVOP_CALL1
+#undef PVOP_VCALL2
+#undef PVOP_CALL2
+#undef PVOP_VCALL3
+#undef PVOP_CALL3
+#undef PVOP_VCALL4
+#undef PVOP_CALL4
 #else  /* __ASSEMBLY__ */
-#define PARA_PATCH(ptype, clobbers, ops)        \
+#define PARA_PATCH(off) ((off) / 4)
+#define PARA_SITE(ptype, clobbers, ops)         \
 771:;                                           \
        ops;                                    \
 772:;                                           \
@@ -538,28 +1049,30 @@ static inline unsigned long __raw_local_irq_save(void)
         .short clobbers;                       \
        .popsection
-#define INTERRUPT_RETURN                                \
+#define INTERRUPT_RETURN                                        \
-        PARA_PATCH(PARAVIRT_INTERRUPT_RETURN, CLBR_ANY, \
+        PARA_SITE(PARA_PATCH(PARAVIRT_iret), CLBR_NONE,         \
-        jmp *%cs:paravirt_ops+PARAVIRT_iret)
+                  jmp *%cs:paravirt_ops+PARAVIRT_iret)
-#define DISABLE_INTERRUPTS(clobbers)                    \
+#define DISABLE_INTERRUPTS(clobbers)                                    \
-        PARA_PATCH(PARAVIRT_IRQ_DISABLE, clobbers,      \
+        PARA_SITE(PARA_PATCH(PARAVIRT_irq_disable), clobbers,           \
-        pushl %ecx; pushl %edx;                         \
+                  pushl %eax; pushl %ecx; pushl %edx;                   \
-        call *paravirt_ops+PARAVIRT_irq_disable;        \
+                  call *%cs:paravirt_ops+PARAVIRT_irq_disable;          \
-        popl %edx; popl %ecx)                           \
+                  popl %edx; popl %ecx; popl %eax)                      \
-#define ENABLE_INTERRUPTS(clobbers)                     \
+#define ENABLE_INTERRUPTS(clobbers)                                     \
-        PARA_PATCH(PARAVIRT_IRQ_ENABLE, clobbers,       \
+        PARA_SITE(PARA_PATCH(PARAVIRT_irq_enable), clobbers,            \
-        pushl %ecx; pushl %edx;                         \
+                  pushl %eax; pushl %ecx; pushl %edx;                   \
-        call *%cs:paravirt_ops+PARAVIRT_irq_enable;     \
+                  call *%cs:paravirt_ops+PARAVIRT_irq_enable;           \
-        popl %edx; popl %ecx)
+                  popl %edx; popl %ecx; popl %eax)
-#define ENABLE_INTERRUPTS_SYSEXIT                       \
+#define ENABLE_INTERRUPTS_SYSEXIT                                       \
-        PARA_PATCH(PARAVIRT_STI_SYSEXIT, CLBR_ANY,      \
+        PARA_SITE(PARA_PATCH(PARAVIRT_irq_enable_sysexit), CLBR_NONE,   \
-        jmp *%cs:paravirt_ops+PARAVIRT_irq_enable_sysexit)
+                  jmp *%cs:paravirt_ops+PARAVIRT_irq_enable_sysexit)
 #define GET_CR0_INTO_EAX                        \
-        call *paravirt_ops+PARAVIRT_read_cr0
+        push %ecx; push %edx;                   \
+        call *paravirt_ops+PARAVIRT_read_cr0;   \
+        pop %edx; pop %ecx
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_PARAVIRT */
diff --git a/include/asm-i386/pda.h b/include/asm-i386/pda.h
deleted file mode 100644
index b12d59a318b7..000000000000
--- a/include/asm-i386/pda.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
-   Per-processor Data Areas
-   Jeremy Fitzhardinge <jeremy@goop.org> 2006
-   Based on asm-x86_64/pda.h by Andi Kleen.
- */
-#ifndef _I386_PDA_H
-#define _I386_PDA_H
-#include <linux/stddef.h>
-#include <linux/types.h>
-struct i386_pda
-{
-        struct i386_pda *_pda;          /* pointer to self */
-        int cpu_number;
-        struct task_struct *pcurrent;   /* current process */
-        struct pt_regs *irq_regs;
-};
-extern struct i386_pda *_cpu_pda[];
-#define cpu_pda(i)      (_cpu_pda[i])
-#define pda_offset(field) offsetof(struct i386_pda, field)
-extern void __bad_pda_field(void);
-/* This variable is never instantiated.  It is only used as a stand-in
-   for the real per-cpu PDA memory, so that gcc can understand what
-   memory operations the inline asms() below are performing.  This
-   eliminates the need to make the asms volatile or have memory
-   clobbers, so gcc can readily analyse them. */
-extern struct i386_pda _proxy_pda;
-#define pda_to_op(op,field,val)                                         \
-        do {                                                            \
-                typedef typeof(_proxy_pda.field) T__;                   \
-                if (0) { T__ tmp__; tmp__ = (val); }                    \
-                switch (sizeof(_proxy_pda.field)) {                     \
-                case 1:                                                 \
-                        asm(op "b %1,%%fs:%c2"                          \
-                            : "+m" (_proxy_pda.field)                   \
-                            :"ri" ((T__)val),                           \
-                             "i"(pda_offset(field)));                   \
-                        break;                                          \
-                case 2:                                                 \
-                        asm(op "w %1,%%fs:%c2"                          \
-                            : "+m" (_proxy_pda.field)                   \
-                            :"ri" ((T__)val),                           \
-                             "i"(pda_offset(field)));                   \
-                        break;                                          \
-                case 4:                                                 \
-                        asm(op "l %1,%%fs:%c2"                          \
-                            : "+m" (_proxy_pda.field)                   \
-                            :"ri" ((T__)val),                           \
-                             "i"(pda_offset(field)));                   \
-                        break;                                          \
-                default: __bad_pda_field();                             \
-                }                                                       \
-        } while (0)
-#define pda_from_op(op,field)                                           \
-        ({                                                              \
-                typeof(_proxy_pda.field) ret__;                         \
-                switch (sizeof(_proxy_pda.field)) {                     \
-                case 1:                                                 \
-                        asm(op "b %%fs:%c1,%0"                          \
-                            : "=r" (ret__)                              \
-                            : "i" (pda_offset(field)),                  \
-                              "m" (_proxy_pda.field));                  \
-                        break;                                          \
-                case 2:                                                 \
-                        asm(op "w %%fs:%c1,%0"                          \
-                            : "=r" (ret__)                              \
-                            : "i" (pda_offset(field)),                  \
-                              "m" (_proxy_pda.field));                  \
-                        break;                                          \
-                case 4:                                                 \
-                        asm(op "l %%fs:%c1,%0"                          \
-                            : "=r" (ret__)                              \
-                            : "i" (pda_offset(field)),                  \
-                              "m" (_proxy_pda.field));                  \
-                        break;                                          \
-                default: __bad_pda_field();                             \
-                }                                                       \
-                ret__; })
-/* Return a pointer to a pda field */
-#define pda_addr(field)                                                 \
-        ((typeof(_proxy_pda.field) *)((unsigned char *)read_pda(_pda) + \
-                                      pda_offset(field)))
-#define read_pda(field) pda_from_op("mov",field)
-#define write_pda(field,val) pda_to_op("mov",field,val)
-#define add_pda(field,val) pda_to_op("add",field,val)
-#define sub_pda(field,val) pda_to_op("sub",field,val)
-#define or_pda(field,val) pda_to_op("or",field,val)
-#endif  /* _I386_PDA_H */
diff --git a/include/asm-i386/percpu.h b/include/asm-i386/percpu.h
index 510ae1d3486c..f54830b5d5ac 100644
--- a/include/asm-i386/percpu.h
+++ b/include/asm-i386/percpu.h
@@ -1,9 +1,32 @@
 #ifndef __ARCH_I386_PERCPU__
 #define __ARCH_I386_PERCPU__
-#ifndef __ASSEMBLY__
+#ifdef __ASSEMBLY__
-#include <asm-generic/percpu.h>
-#else
+/*
+ * PER_CPU finds an address of a per-cpu variable.
+ *
+ * Args:
+ *    var - variable name
+ *    reg - 32bit register
+ *
+ * The resulting address is stored in the "reg" argument.
+ *
+ * Example:
+ *    PER_CPU(cpu_gdt_descr, %ebx)
+ */
+#ifdef CONFIG_SMP
+#define PER_CPU(var, reg)                               \
+        movl %fs:per_cpu__##this_cpu_off, reg;          \
+        lea per_cpu__##var(reg), reg
+#define PER_CPU_VAR(var)        %fs:per_cpu__##var
+#else /* ! SMP */
+#define PER_CPU(var, reg)                       \
+        movl $per_cpu__##var, reg
+#define PER_CPU_VAR(var)        per_cpu__##var
+#endif  /* SMP */
+#else /* ...!ASSEMBLY */
 /*
 * PER_CPU finds an address of a per-cpu variable.
@@ -18,14 +41,109 @@
 *    PER_CPU(cpu_gdt_descr, %ebx)
 */
 #ifdef CONFIG_SMP
-#define PER_CPU(var, cpu) \
+/* Same as generic implementation except for optimized local access. */
-        movl __per_cpu_offset(,cpu,4), cpu;     \
+#define __GENERIC_PER_CPU
-        addl $per_cpu__/**/var, cpu;
-#else /* ! SMP */
+/* This is used for other cpus to find our section. */
-#define PER_CPU(var, cpu) \
+extern unsigned long __per_cpu_offset[];
-        movl $per_cpu__/**/var, cpu;
+#define per_cpu_offset(x) (__per_cpu_offset[x])
+/* Separate out the type, so (int[3], foo) works. */
+#define DECLARE_PER_CPU(type, name) extern __typeof__(type) per_cpu__##name
+#define DEFINE_PER_CPU(type, name) \
+    __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name
+/* We can use this directly for local CPU (faster). */
+DECLARE_PER_CPU(unsigned long, this_cpu_off);
+/* var is in discarded region: offset to particular copy we want */
+#define per_cpu(var, cpu) (*({                          \
+        extern int simple_indentifier_##var(void);      \
+        RELOC_HIDE(&per_cpu__##var, __per_cpu_offset[cpu]); }))
+#define __raw_get_cpu_var(var) (*({                                     \
+        extern int simple_indentifier_##var(void);                      \
+        RELOC_HIDE(&per_cpu__##var, x86_read_percpu(this_cpu_off));     \
+}))
+#define __get_cpu_var(var) __raw_get_cpu_var(var)
+/* A macro to avoid #include hell... */
+#define percpu_modcopy(pcpudst, src, size)                      \
+do {                                                            \
+        unsigned int __i;                                       \
+        for_each_possible_cpu(__i)                              \
+                memcpy((pcpudst)+__per_cpu_offset[__i],         \
+                       (src), (size));                          \
+} while (0)
+#define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(per_cpu__##var)
+#define EXPORT_PER_CPU_SYMBOL_GPL(var) EXPORT_SYMBOL_GPL(per_cpu__##var)
+/* fs segment starts at (positive) offset == __per_cpu_offset[cpu] */
+#define __percpu_seg "%%fs:"
+#else  /* !SMP */
+#include <asm-generic/percpu.h>
+#define __percpu_seg ""
 #endif  /* SMP */
+/* For arch-specific code, we can use direct single-insn ops (they
+ * don't give an lvalue though). */
+extern void __bad_percpu_size(void);
+#define percpu_to_op(op,var,val)                                \
+        do {                                                    \
+                typedef typeof(var) T__;                        \
+                if (0) { T__ tmp__; tmp__ = (val); }            \
+                switch (sizeof(var)) {                          \
+                case 1:                                         \
+                        asm(op "b %1,"__percpu_seg"%0"          \
+                            : "+m" (var)                        \
+                            :"ri" ((T__)val));                  \
+                        break;                                  \
+                case 2:                                         \
+                        asm(op "w %1,"__percpu_seg"%0"          \
+                            : "+m" (var)                        \
+                            :"ri" ((T__)val));                  \
+                        break;                                  \
+                case 4:                                         \
+                        asm(op "l %1,"__percpu_seg"%0"          \
+                            : "+m" (var)                        \
+                            :"ri" ((T__)val));                  \
+                        break;                                  \
+                default: __bad_percpu_size();                   \
+                }                                               \
+        } while (0)
+#define percpu_from_op(op,var)                                  \
+        ({                                                      \
+                typeof(var) ret__;                              \
+                switch (sizeof(var)) {                          \
+                case 1:                                         \
+                        asm(op "b "__percpu_seg"%1,%0"          \
+                            : "=r" (ret__)                      \
+                            : "m" (var));                       \
+                        break;                                  \
+                case 2:                                         \
+                        asm(op "w "__percpu_seg"%1,%0"          \
+                            : "=r" (ret__)                      \
+                            : "m" (var));                       \
+                        break;                                  \
+                case 4:                                         \
+                        asm(op "l "__percpu_seg"%1,%0"          \
+                            : "=r" (ret__)                      \
+                            : "m" (var));                       \
+                        break;                                  \
+                default: __bad_percpu_size();                   \
+                }                                               \
+                ret__; })
+#define x86_read_percpu(var) percpu_from_op("mov", per_cpu__##var)
+#define x86_write_percpu(var,val) percpu_to_op("mov", per_cpu__##var, val)
+#define x86_add_percpu(var,val) percpu_to_op("add", per_cpu__##var, val)
+#define x86_sub_percpu(var,val) percpu_to_op("sub", per_cpu__##var, val)
+#define x86_or_percpu(var,val) percpu_to_op("or", per_cpu__##var, val)
 #endif /* !__ASSEMBLY__ */
 #endif /* __ARCH_I386_PERCPU__ */
diff --git a/include/asm-i386/pgalloc.h b/include/asm-i386/pgalloc.h
index c8dc2d0141a7..47430175b75f 100644
--- a/include/asm-i386/pgalloc.h
+++ b/include/asm-i386/pgalloc.h
@@ -1,7 +1,6 @@
 #ifndef _I386_PGALLOC_H
 #define _I386_PGALLOC_H
-#include <asm/fixmap.h>
 #include <linux/threads.h>
 #include <linux/mm.h>           /* for struct page */
diff --git a/include/asm-i386/pgtable-2level-defs.h b/include/asm-i386/pgtable-2level-defs.h
index 02518079f816..0f71c9f13da4 100644
--- a/include/asm-i386/pgtable-2level-defs.h
+++ b/include/asm-i386/pgtable-2level-defs.h
@@ -1,6 +1,8 @@
 #ifndef _I386_PGTABLE_2LEVEL_DEFS_H
 #define _I386_PGTABLE_2LEVEL_DEFS_H
+#define SHARED_KERNEL_PMD       0
 /*
 * traditional i386 two-level paging structure:
 */
diff --git a/include/asm-i386/pgtable-2level.h b/include/asm-i386/pgtable-2level.h
index 38c3fcc0676d..a50fd1773de8 100644
--- a/include/asm-i386/pgtable-2level.h
+++ b/include/asm-i386/pgtable-2level.h
@@ -11,10 +11,23 @@
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
+static inline void native_set_pte(pte_t *ptep , pte_t pte)
+{
+        *ptep = pte;
+}
+static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr,
+                                     pte_t *ptep , pte_t pte)
+{
+        native_set_pte(ptep, pte);
+}
+static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
+{
+        *pmdp = pmd;
+}
 #ifndef CONFIG_PARAVIRT
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#define set_pte(pteptr, pteval)         native_set_pte(pteptr, pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+#define set_pte_at(mm,addr,ptep,pteval) native_set_pte_at(mm, addr, ptep, pteval)
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
+#define set_pmd(pmdptr, pmdval)         native_set_pmd(pmdptr, pmdval)
 #endif
 #define set_pte_atomic(pteptr, pteval) set_pte(pteptr,pteval)
@@ -23,11 +36,23 @@
 #define pte_clear(mm,addr,xp)   do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
 #define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
-#define raw_ptep_get_and_clear(xp)      __pte(xchg(&(xp)->pte_low, 0))
+static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *xp)
+{
+        *xp = __pte(0);
+}
+#ifdef CONFIG_SMP
+static inline pte_t native_ptep_get_and_clear(pte_t *xp)
+{
+        return __pte(xchg(&xp->pte_low, 0));
+}
+#else
+#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
+#endif
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 #define pte_none(x)             (!(x).pte_low)
-#define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
+#define pte_pfn(x)              (pte_val(x) >> PAGE_SHIFT)
 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
@@ -66,6 +91,4 @@ static inline int pte_exec_kernel(pte_t pte)
 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { (pte).pte_low })
 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
-void vmalloc_sync_all(void);
 #endif /* _I386_PGTABLE_2LEVEL_H */
diff --git a/include/asm-i386/pgtable-3level-defs.h b/include/asm-i386/pgtable-3level-defs.h
index eb3a1ea88671..c0df89f66e8b 100644
--- a/include/asm-i386/pgtable-3level-defs.h
+++ b/include/asm-i386/pgtable-3level-defs.h
@@ -1,6 +1,12 @@
 #ifndef _I386_PGTABLE_3LEVEL_DEFS_H
 #define _I386_PGTABLE_3LEVEL_DEFS_H
+#ifdef CONFIG_PARAVIRT
+#define SHARED_KERNEL_PMD       (paravirt_ops.shared_kernel_pmd)
+#else
+#define SHARED_KERNEL_PMD       1
+#endif
 /*
 * PGDIR_SHIFT determines what a top-level page table entry can map
 */
diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h
index 7a2318f38303..eb0f1d7e96a1 100644
--- a/include/asm-i386/pgtable-3level.h
+++ b/include/asm-i386/pgtable-3level.h
@@ -42,20 +42,23 @@ static inline int pte_exec_kernel(pte_t pte)
        return pte_x(pte);
 }
-#ifndef CONFIG_PARAVIRT
 /* Rules for using set_pte: the pte being assigned *must* be
 * either not present or in a state where the hardware will
 * not attempt to update the pte.  In places where this is
 * not possible, use pte_get_and_clear to obtain the old pte
 * value and then use set_pte to update it.  -ben
 */
-static inline void set_pte(pte_t *ptep, pte_t pte)
+static inline void native_set_pte(pte_t *ptep, pte_t pte)
 {
        ptep->pte_high = pte.pte_high;
        smp_wmb();
        ptep->pte_low = pte.pte_low;
 }
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr,
+                                     pte_t *ptep , pte_t pte)
+{
+        native_set_pte(ptep, pte);
+}
 /*
 * Since this is only called on user PTEs, and the page fault handler
@@ -63,7 +66,8 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
 * we are justified in merely clearing the PTE present bit, followed
 * by a set.  The ordering here is important.
 */
-static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+static inline void native_set_pte_present(struct mm_struct *mm, unsigned long addr,
+                                          pte_t *ptep, pte_t pte)
 {
        ptep->pte_low = 0;
        smp_wmb();
@@ -72,32 +76,48 @@ static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte
        ptep->pte_low = pte.pte_low;
 }
-#define set_pte_atomic(pteptr,pteval) \
+static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
-                set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
+{
-#define set_pmd(pmdptr,pmdval) \
+        set_64bit((unsigned long long *)(ptep),native_pte_val(pte));
-                set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
+}
-#define set_pud(pudptr,pudval) \
+static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
-                (*(pudptr) = (pudval))
+{
+        set_64bit((unsigned long long *)(pmdp),native_pmd_val(pmd));
+}
+static inline void native_set_pud(pud_t *pudp, pud_t pud)
+{
+        *pudp = pud;
+}
 /*
 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
 * entry, so clear the bottom half first and enforce ordering with a compiler
 * barrier.
 */
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
        ptep->pte_low = 0;
        smp_wmb();
        ptep->pte_high = 0;
 }
-static inline void pmd_clear(pmd_t *pmd)
+static inline void native_pmd_clear(pmd_t *pmd)
 {
        u32 *tmp = (u32 *)pmd;
        *tmp = 0;
        smp_wmb();
        *(tmp + 1) = 0;
 }
+#ifndef CONFIG_PARAVIRT
+#define set_pte(ptep, pte)                      native_set_pte(ptep, pte)
+#define set_pte_at(mm, addr, ptep, pte)         native_set_pte_at(mm, addr, ptep, pte)
+#define set_pte_present(mm, addr, ptep, pte)    native_set_pte_present(mm, addr, ptep, pte)
+#define set_pte_atomic(ptep, pte)               native_set_pte_atomic(ptep, pte)
+#define set_pmd(pmdp, pmd)                      native_set_pmd(pmdp, pmd)
+#define set_pud(pudp, pud)                      native_set_pud(pudp, pud)
+#define pte_clear(mm, addr, ptep)               native_pte_clear(mm, addr, ptep)
+#define pmd_clear(pmd)                          native_pmd_clear(pmd)
 #endif
 /*
@@ -119,7 +139,8 @@ static inline void pud_clear (pud_t * pud) { }
 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
                        pmd_index(address))
-static inline pte_t raw_ptep_get_and_clear(pte_t *ptep)
+#ifdef CONFIG_SMP
+static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
 {
        pte_t res;
@@ -130,6 +151,9 @@ static inline pte_t raw_ptep_get_and_clear(pte_t *ptep)
        return res;
 }
+#else
+#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
+#endif
 #define __HAVE_ARCH_PTE_SAME
 static inline int pte_same(pte_t a, pte_t b)
@@ -146,28 +170,21 @@ static inline int pte_none(pte_t pte)
 static inline unsigned long pte_pfn(pte_t pte)
 {
-        return (pte.pte_low >> PAGE_SHIFT) |
+        return pte_val(pte) >> PAGE_SHIFT;
-                (pte.pte_high << (32 - PAGE_SHIFT));
 }
 extern unsigned long long __supported_pte_mask;
 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
 {
-        pte_t pte;
+        return __pte((((unsigned long long)page_nr << PAGE_SHIFT) |
+                      pgprot_val(pgprot)) & __supported_pte_mask);
-        pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
-                                        (pgprot_val(pgprot) >> 32);
-        pte.pte_high &= (__supported_pte_mask >> 32);
-        pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
-                                                        __supported_pte_mask;
-        return pte;
 }
 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
 {
-        return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
+        return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) |
-                        pgprot_val(pgprot)) & __supported_pte_mask);
+                      pgprot_val(pgprot)) & __supported_pte_mask);
 }
 /*
@@ -187,6 +204,4 @@ static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
 #define __pmd_free_tlb(tlb, x)          do { } while (0)
-#define vmalloc_sync_all() ((void)0)
 #endif /* _I386_PGTABLE_3LEVEL_H */
diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h
index c3b58d473a55..c6b8b944120c 100644
--- a/include/asm-i386/pgtable.h
+++ b/include/asm-i386/pgtable.h
@@ -159,6 +159,7 @@ void paging_init(void);
 extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
 #define __PAGE_KERNEL_RO                (__PAGE_KERNEL & ~_PAGE_RW)
+#define __PAGE_KERNEL_RX                (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
 #define __PAGE_KERNEL_NOCACHE           (__PAGE_KERNEL | _PAGE_PCD)
 #define __PAGE_KERNEL_LARGE             (__PAGE_KERNEL | _PAGE_PSE)
 #define __PAGE_KERNEL_LARGE_EXEC        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
@@ -166,6 +167,7 @@ extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
 #define PAGE_KERNEL             __pgprot(__PAGE_KERNEL)
 #define PAGE_KERNEL_RO          __pgprot(__PAGE_KERNEL_RO)
 #define PAGE_KERNEL_EXEC        __pgprot(__PAGE_KERNEL_EXEC)
+#define PAGE_KERNEL_RX          __pgprot(__PAGE_KERNEL_RX)
 #define PAGE_KERNEL_NOCACHE     __pgprot(__PAGE_KERNEL_NOCACHE)
 #define PAGE_KERNEL_LARGE       __pgprot(__PAGE_KERNEL_LARGE)
 #define PAGE_KERNEL_LARGE_EXEC  __pgprot(__PAGE_KERNEL_LARGE_EXEC)
@@ -241,6 +243,8 @@ static inline pte_t pte_mkyoung(pte_t pte)	{ (pte).pte_low |= _PAGE_ACCESSED; re
 static inline pte_t pte_mkwrite(pte_t pte)      { (pte).pte_low |= _PAGE_RW; return pte; }
 static inline pte_t pte_mkhuge(pte_t pte)       { (pte).pte_low |= _PAGE_PSE; return pte; }
+extern void vmalloc_sync_all(void);
 #ifdef CONFIG_X86_PAE
 # include <asm/pgtable-3level.h>
 #else
@@ -263,9 +267,18 @@ static inline pte_t pte_mkhuge(pte_t pte)	{ (pte).pte_low |= _PAGE_PSE; return p
 */
 #define pte_update(mm, addr, ptep)              do { } while (0)
 #define pte_update_defer(mm, addr, ptep)        do { } while (0)
-#define paravirt_map_pt_hook(slot, va, pfn)     do { } while (0)
 #endif
+/* local pte updates need not use xchg for locking */
+static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
+{
+        pte_t res = *ptep;
+        /* Pure native function needs no input for mm, addr */
+        native_pte_clear(NULL, 0, ptep);
+        return res;
+}
 /*
 * We only update the dirty/accessed state if we set
 * the dirty bit by hand in the kernel, since the hardware
@@ -330,7 +343,7 @@ do {									\
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
-        pte_t pte = raw_ptep_get_and_clear(ptep);
+        pte_t pte = native_ptep_get_and_clear(ptep);
        pte_update(mm, addr, ptep);
        return pte;
 }
@@ -340,8 +353,11 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long
 {
        pte_t pte;
        if (full) {
-                pte = *ptep;
+                /*
-                pte_clear(mm, addr, ptep);
+                 * Full address destruction in progress; paravirt does not
+                 * care about updates and native needs no locking
+                 */
+                pte = native_local_ptep_get_and_clear(ptep);
        } else {
                pte = ptep_get_and_clear(mm, addr, ptep);
        }
@@ -470,24 +486,10 @@ extern pte_t *lookup_address(unsigned long address);
 #endif
 #if defined(CONFIG_HIGHPTE)
-#define pte_offset_map(dir, address)                            \
+#define pte_offset_map(dir, address) \
-({                                                              \
+        ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
-        pte_t *__ptep;                                          \
+#define pte_offset_map_nested(dir, address) \
-        unsigned pfn = pmd_val(*(dir)) >> PAGE_SHIFT;           \
+        ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
-        __ptep = (pte_t *)kmap_atomic(pfn_to_page(pfn),KM_PTE0);\
-        paravirt_map_pt_hook(KM_PTE0,__ptep, pfn);              \
-        __ptep = __ptep + pte_index(address);                   \
-        __ptep;                                                 \
-})
-#define pte_offset_map_nested(dir, address)                     \
-({                                                              \
-        pte_t *__ptep;                                          \
-        unsigned pfn = pmd_val(*(dir)) >> PAGE_SHIFT;           \
-        __ptep = (pte_t *)kmap_atomic(pfn_to_page(pfn),KM_PTE1);\
-        paravirt_map_pt_hook(KM_PTE1,__ptep, pfn);              \
-        __ptep = __ptep + pte_index(address);                   \
-        __ptep;                                                 \
-})
 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
 #else
@@ -510,6 +512,22 @@ do {									\
 * tables contain all the necessary information.
 */
 #define update_mmu_cache(vma,address,pte) do { } while (0)
+void native_pagetable_setup_start(pgd_t *base);
+void native_pagetable_setup_done(pgd_t *base);
+#ifndef CONFIG_PARAVIRT
+static inline void paravirt_pagetable_setup_start(pgd_t *base)
+{
+        native_pagetable_setup_start(base);
+}
+static inline void paravirt_pagetable_setup_done(pgd_t *base)
+{
+        native_pagetable_setup_done(base);
+}
+#endif  /* !CONFIG_PARAVIRT */
 #endif /* !__ASSEMBLY__ */
 #ifdef CONFIG_FLATMEM
diff --git a/include/asm-i386/processor-flags.h b/include/asm-i386/processor-flags.h
new file mode 100644
index 000000000000..5404e90edd57
--- /dev/null
+++ b/include/asm-i386/processor-flags.h
@@ -0,0 +1,91 @@
+#ifndef __ASM_I386_PROCESSOR_FLAGS_H
+#define __ASM_I386_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
+#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
+#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE      0x00000001 /* Protection Enable */
+#define X86_CR0_MP      0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM      0x00000004 /* Emulation */
+#define X86_CR0_TS      0x00000008 /* Task Switched */
+#define X86_CR0_ET      0x00000010 /* Extension Type */
+#define X86_CR0_NE      0x00000020 /* Numeric Error */
+#define X86_CR0_WP      0x00010000 /* Write Protect */
+#define X86_CR0_AM      0x00040000 /* Alignment Mask */
+#define X86_CR0_NW      0x20000000 /* Not Write-through */
+#define X86_CR0_CD      0x40000000 /* Cache Disable */
+#define X86_CR0_PG      0x80000000 /* Paging */
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT     0x00000008 /* Page Write Through */
+#define X86_CR3_PCD     0x00000010 /* Page Cache Disable */
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME     0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI     0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD     0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE      0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE     0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE     0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE     0x00000040 /* Machine check enable */
+#define X86_CR4_PGE     0x00000080 /* enable global pages */
+#define X86_CR4_PCE     0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR  0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR     0x00000007 /* task priority register */
+/*
+ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
+ */
+/*
+ *      NSC/Cyrix CPU configuration register indexes
+ */
+#define CX86_PCR0       0x20
+#define CX86_GCR        0xb8
+#define CX86_CCR0       0xc0
+#define CX86_CCR1       0xc1
+#define CX86_CCR2       0xc2
+#define CX86_CCR3       0xc3
+#define CX86_CCR4       0xe8
+#define CX86_CCR5       0xe9
+#define CX86_CCR6       0xea
+#define CX86_CCR7       0xeb
+#define CX86_PCR1       0xf0
+#define CX86_DIR0       0xfe
+#define CX86_DIR1       0xff
+#define CX86_ARR_BASE   0xc4
+#define CX86_RCR_BASE   0xdc
+#endif  /* __ASM_I386_PROCESSOR_FLAGS_H */
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index 11bf899de8aa..70f3515c3db0 100644
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -21,6 +21,7 @@
 #include <asm/percpu.h>
 #include <linux/cpumask.h>
 #include <linux/init.h>
+#include <asm/processor-flags.h>
 /* flag for disabling the tsc */
 extern int tsc_disable;
@@ -115,7 +116,8 @@ extern char ignore_fpu_irq;
 void __init cpu_detect(struct cpuinfo_x86 *c);
-extern void identify_cpu(struct cpuinfo_x86 *);
+extern void identify_boot_cpu(void);
+extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 extern void print_cpu_info(struct cpuinfo_x86 *);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
@@ -126,28 +128,7 @@ extern void detect_ht(struct cpuinfo_x86 *c);
 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 #endif
-/*
+static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
- * EFLAGS bits
- */
-#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
-#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
-#define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
-#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
-#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
-#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
-#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
-#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
-#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
-#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
-#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
-#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
-#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
-#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
-#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
-#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
-#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
-static inline fastcall void native_cpuid(unsigned int *eax, unsigned int *ebx,
                                         unsigned int *ecx, unsigned int *edx)
 {
        /* ecx is often an input as well as an output. */
@@ -162,21 +143,6 @@ static inline fastcall void native_cpuid(unsigned int *eax, unsigned int *ebx,
 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
 /*
- * Intel CPU features in CR4
- */
-#define X86_CR4_VME             0x0001  /* enable vm86 extensions */
-#define X86_CR4_PVI             0x0002  /* virtual interrupts flag enable */
-#define X86_CR4_TSD             0x0004  /* disable time stamp at ipl 3 */
-#define X86_CR4_DE              0x0008  /* enable debugging extensions */
-#define X86_CR4_PSE             0x0010  /* enable page size extensions */
-#define X86_CR4_PAE             0x0020  /* enable physical address extensions */
-#define X86_CR4_MCE             0x0040  /* Machine check enable */
-#define X86_CR4_PGE             0x0080  /* enable global pages */
-#define X86_CR4_PCE             0x0100  /* enable performance counters at ipl 3 */
-#define X86_CR4_OSFXSR          0x0200  /* enable fast FPU save and restore */
-#define X86_CR4_OSXMMEXCPT      0x0400  /* enable unmasked SSE exceptions */
-/*
 * Save the cr4 feature set we're using (ie
 * Pentium 4MB enable and PPro Global page
 * enable), so that any CPU's that boot up
@@ -203,26 +169,6 @@ static inline void clear_in_cr4 (unsigned long mask)
 }
 /*
- *      NSC/Cyrix CPU configuration register indexes
- */
-#define CX86_PCR0 0x20
-#define CX86_GCR  0xb8
-#define CX86_CCR0 0xc0
-#define CX86_CCR1 0xc1
-#define CX86_CCR2 0xc2
-#define CX86_CCR3 0xc3
-#define CX86_CCR4 0xe8
-#define CX86_CCR5 0xe9
-#define CX86_CCR6 0xea
-#define CX86_CCR7 0xeb
-#define CX86_PCR1 0xf0
-#define CX86_DIR0 0xfe
-#define CX86_DIR1 0xff
-#define CX86_ARR_BASE 0xc4
-#define CX86_RCR_BASE 0xdc
-/*
 *      NSC/Cyrix CPU indexed register access macros
 */
@@ -345,7 +291,8 @@ typedef struct {
 struct thread_struct;
-struct tss_struct {
+/* This is the TSS defined by the hardware. */
+struct i386_hw_tss {
        unsigned short  back_link,__blh;
        unsigned long   esp0;
        unsigned short  ss0,__ss0h;
@@ -369,6 +316,11 @@ struct tss_struct {
        unsigned short  gs, __gsh;
        unsigned short  ldt, __ldth;
        unsigned short  trace, io_bitmap_base;
+} __attribute__((packed));
+struct tss_struct {
+        struct i386_hw_tss x86_tss;
        /*
         * The extra 1 is there because the CPU will access an
         * additional byte beyond the end of the IO permission
@@ -421,10 +373,11 @@ struct thread_struct {
 };
 #define INIT_THREAD  {                                                  \
+        .esp0 = sizeof(init_stack) + (long)&init_stack,                 \
        .vm86_info = NULL,                                              \
        .sysenter_cs = __KERNEL_CS,                                     \
        .io_bitmap_ptr = NULL,                                          \
-        .fs = __KERNEL_PDA,                                             \
+        .fs = __KERNEL_PERCPU,                                          \
 }
 /*
@@ -434,10 +387,12 @@ struct thread_struct {
 * be within the limit.
 */
 #define INIT_TSS  {                                                     \
-        .esp0           = sizeof(init_stack) + (long)&init_stack,       \
+        .x86_tss = {                                                    \
-        .ss0            = __KERNEL_DS,                                  \
+                .esp0           = sizeof(init_stack) + (long)&init_stack, \
-        .ss1            = __KERNEL_CS,                                  \
+                .ss0            = __KERNEL_DS,                          \
-        .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,                     \
+                .ss1            = __KERNEL_CS,                          \
+                .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
+         },                                                             \
        .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 }
@@ -544,40 +499,70 @@ static inline void rep_nop(void)
 #define cpu_relax()     rep_nop()
-#ifdef CONFIG_PARAVIRT
+static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
-#include <asm/paravirt.h>
-#else
-#define paravirt_enabled() 0
-#define __cpuid native_cpuid
-static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 {
-        tss->esp0 = thread->esp0;
+        tss->x86_tss.esp0 = thread->esp0;
        /* This can only happen when SEP is enabled, no need to test "SEP"arately */
-        if (unlikely(tss->ss1 != thread->sysenter_cs)) {
+        if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
-                tss->ss1 = thread->sysenter_cs;
+                tss->x86_tss.ss1 = thread->sysenter_cs;
                wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
        }
 }
-/*
- * These special macros can be used to get or set a debugging register
- */
-#define get_debugreg(var, register)                             \
-                __asm__("movl %%db" #register ", %0"            \
-                        :"=r" (var))
-#define set_debugreg(value, register)                   \
-                __asm__("movl %0,%%db" #register                \
-                        : /* no output */                       \
-                        :"r" (value))
-#define set_iopl_mask native_set_iopl_mask
+static inline unsigned long native_get_debugreg(int regno)
-#endif /* CONFIG_PARAVIRT */
+{
+        unsigned long val = 0;  /* Damn you, gcc! */
+        switch (regno) {
+        case 0:
+                asm("movl %%db0, %0" :"=r" (val)); break;
+        case 1:
+                asm("movl %%db1, %0" :"=r" (val)); break;
+        case 2:
+                asm("movl %%db2, %0" :"=r" (val)); break;
+        case 3:
+                asm("movl %%db3, %0" :"=r" (val)); break;
+        case 6:
+                asm("movl %%db6, %0" :"=r" (val)); break;
+        case 7:
+                asm("movl %%db7, %0" :"=r" (val)); break;
+        default:
+                BUG();
+        }
+        return val;
+}
+static inline void native_set_debugreg(int regno, unsigned long value)
+{
+        switch (regno) {
+        case 0:
+                asm("movl %0,%%db0"     : /* no output */ :"r" (value));
+                break;
+        case 1:
+                asm("movl %0,%%db1"     : /* no output */ :"r" (value));
+                break;
+        case 2:
+                asm("movl %0,%%db2"     : /* no output */ :"r" (value));
+                break;
+        case 3:
+                asm("movl %0,%%db3"     : /* no output */ :"r" (value));
+                break;
+        case 6:
+                asm("movl %0,%%db6"     : /* no output */ :"r" (value));
+                break;
+        case 7:
+                asm("movl %0,%%db7"     : /* no output */ :"r" (value));
+                break;
+        default:
+                BUG();
+        }
+}
 /*
 * Set IOPL bits in EFLAGS from given mask
 */
-static fastcall inline void native_set_iopl_mask(unsigned mask)
+static inline void native_set_iopl_mask(unsigned mask)
 {
        unsigned int reg;
        __asm__ __volatile__ ("pushfl;"
@@ -590,6 +575,28 @@ static fastcall inline void native_set_iopl_mask(unsigned mask)
                                : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 }
+#ifdef CONFIG_PARAVIRT
+#include <asm/paravirt.h>
+#else
+#define paravirt_enabled() 0
+#define __cpuid native_cpuid
+static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
+{
+        native_load_esp0(tss, thread);
+}
+/*
+ * These special macros can be used to get or set a debugging register
+ */
+#define get_debugreg(var, register)                             \
+        (var) = native_get_debugreg(register)
+#define set_debugreg(value, register)                           \
+        native_set_debugreg(register, value)
+#define set_iopl_mask native_set_iopl_mask
+#endif /* CONFIG_PARAVIRT */
 /*
 * Generic CPUID function
 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
@@ -742,8 +749,10 @@ extern unsigned long boot_option_idle_override;
 extern void enable_sep_cpu(void);
 extern int sysenter_setup(void);
-extern int init_gdt(int cpu, struct task_struct *idle);
 extern void cpu_set_gdt(int);
-extern void secondary_cpu_init(void);
+extern void switch_to_new_gdt(void);
+extern void cpu_init(void);
+extern int force_mwait;
 #endif /* __ASM_I386_PROCESSOR_H */
diff --git a/include/asm-i386/reboot.h b/include/asm-i386/reboot.h
new file mode 100644
index 000000000000..e9e3ffc22c07
--- /dev/null
+++ b/include/asm-i386/reboot.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+struct pt_regs;
+struct machine_ops
+{
+        void (*restart)(char *cmd);
+        void (*halt)(void);
+        void (*power_off)(void);
+        void (*shutdown)(void);
+        void (*crash_shutdown)(struct pt_regs *);
+        void (*emergency_restart)(void);
+};
+extern struct machine_ops machine_ops;
+void machine_real_restart(unsigned char *code, int length);
+#endif  /* _ASM_REBOOT_H */
diff --git a/include/linux/reboot_fixups.h b/include/asm-i386/reboot_fixups.h
index 480ea2d489d8..0cb7d87c2b68 100644
--- a/include/linux/reboot_fixups.h
+++ b/include/asm-i386/reboot_fixups.h
@@ -1,10 +1,6 @@
 #ifndef _LINUX_REBOOT_FIXUPS_H
 #define _LINUX_REBOOT_FIXUPS_H
-#ifdef CONFIG_X86_REBOOTFIXUPS
 extern void mach_reboot_fixups(void);
-#else
-#define mach_reboot_fixups() ((void)(0))
-#endif
 #endif /* _LINUX_REBOOT_FIXUPS_H */
diff --git a/include/asm-i386/required-features.h b/include/asm-i386/required-features.h
new file mode 100644
index 000000000000..9db866c1e64c
--- /dev/null
+++ b/include/asm-i386/required-features.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_REQUIRED_FEATURES_H
+#define _ASM_REQUIRED_FEATURES_H 1
+/* Define minimum CPUID feature set for kernel These bits are checked
+   really early to actually display a visible error message before the
+   kernel dies.  Only add word 0 bits here
+   Some requirements that are not in CPUID yet are also in the
+   CONFIG_X86_MINIMUM_CPU mode which is checked too.
+   The real information is in arch/i386/Kconfig.cpu, this just converts
+   the CONFIGs into a bitmask */
+#ifdef CONFIG_X86_PAE
+#define NEED_PAE        (1<<X86_FEATURE_PAE)
+#else
+#define NEED_PAE        0
+#endif
+#ifdef CONFIG_X86_CMOV
+#define NEED_CMOV       (1<<X86_FEATURE_CMOV)
+#else
+#define NEED_CMOV       0
+#endif
+#ifdef CONFIG_X86_CMPXCHG64
+#define NEED_CMPXCHG64  (1<<X86_FEATURE_CX8)
+#else
+#define NEED_CMPXCHG64  0
+#endif
+#define REQUIRED_MASK1  (NEED_PAE|NEED_CMOV|NEED_CMPXCHG64)
+#endif
diff --git a/include/asm-i386/segment.h b/include/asm-i386/segment.h
index 065f10bfa487..597a47c2515f 100644
--- a/include/asm-i386/segment.h
+++ b/include/asm-i386/segment.h
@@ -39,7 +39,7 @@
 *  25 - APM BIOS support 
 *
 *  26 - ESPFIX small SS
- *  27 - PDA                            [ per-cpu private data area ]
+ *  27 - per-cpu                        [ offset to per-cpu data area ]
 *  28 - unused
 *  29 - unused
 *  30 - unused
@@ -74,8 +74,12 @@
 #define GDT_ENTRY_ESPFIX_SS             (GDT_ENTRY_KERNEL_BASE + 14)
 #define __ESPFIX_SS (GDT_ENTRY_ESPFIX_SS * 8)
-#define GDT_ENTRY_PDA                   (GDT_ENTRY_KERNEL_BASE + 15)
+#define GDT_ENTRY_PERCPU                        (GDT_ENTRY_KERNEL_BASE + 15)
-#define __KERNEL_PDA (GDT_ENTRY_PDA * 8)
+#ifdef CONFIG_SMP
+#define __KERNEL_PERCPU (GDT_ENTRY_PERCPU * 8)
+#else
+#define __KERNEL_PERCPU 0
+#endif
 #define GDT_ENTRY_DOUBLEFAULT_TSS       31
diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h
index 6bf0033a301c..090abc1da32a 100644
--- a/include/asm-i386/smp.h
+++ b/include/asm-i386/smp.h
@@ -8,19 +8,15 @@
 #include <linux/kernel.h>
 #include <linux/threads.h>
 #include <linux/cpumask.h>
-#include <asm/pda.h>
 #endif
-#ifdef CONFIG_X86_LOCAL_APIC
+#if defined(CONFIG_X86_LOCAL_APIC) && !defined(__ASSEMBLY__)
-#ifndef __ASSEMBLY__
-#include <asm/fixmap.h>
 #include <asm/bitops.h>
 #include <asm/mpspec.h>
+#include <asm/apic.h>
 #ifdef CONFIG_X86_IO_APIC
 #include <asm/io_apic.h>
 #endif
-#include <asm/apic.h>
-#endif
 #endif
 #define BAD_APICID 0xFFu
@@ -52,6 +48,59 @@ extern void cpu_exit_clear(void);
 extern void cpu_uninit(void);
 #endif
+struct smp_ops
+{
+        void (*smp_prepare_boot_cpu)(void);
+        void (*smp_prepare_cpus)(unsigned max_cpus);
+        int (*cpu_up)(unsigned cpu);
+        void (*smp_cpus_done)(unsigned max_cpus);
+        void (*smp_send_stop)(void);
+        void (*smp_send_reschedule)(int cpu);
+        int (*smp_call_function_mask)(cpumask_t mask,
+                                      void (*func)(void *info), void *info,
+                                      int wait);
+};
+extern struct smp_ops smp_ops;
+static inline void smp_prepare_boot_cpu(void)
+{
+        smp_ops.smp_prepare_boot_cpu();
+}
+static inline void smp_prepare_cpus(unsigned int max_cpus)
+{
+        smp_ops.smp_prepare_cpus(max_cpus);
+}
+static inline int __cpu_up(unsigned int cpu)
+{
+        return smp_ops.cpu_up(cpu);
+}
+static inline void smp_cpus_done(unsigned int max_cpus)
+{
+        smp_ops.smp_cpus_done(max_cpus);
+}
+static inline void smp_send_stop(void)
+{
+        smp_ops.smp_send_stop();
+}
+static inline void smp_send_reschedule(int cpu)
+{
+        smp_ops.smp_send_reschedule(cpu);
+}
+static inline int smp_call_function_mask(cpumask_t mask,
+                                         void (*func) (void *info), void *info,
+                                         int wait)
+{
+        return smp_ops.smp_call_function_mask(mask, func, info, wait);
+}
+void native_smp_prepare_boot_cpu(void);
+void native_smp_prepare_cpus(unsigned int max_cpus);
+int native_cpu_up(unsigned int cpunum);
+void native_smp_cpus_done(unsigned int max_cpus);
 #ifndef CONFIG_PARAVIRT
 #define startup_ipi_hook(phys_apicid, start_eip, start_esp)             \
 do { } while (0)
@@ -62,7 +111,8 @@ do { } while (0)
 * from the initial startup. We map APIC_BASE very early in page_setup(),
 * so this is correct in the x86 case.
 */
-#define raw_smp_processor_id() (read_pda(cpu_number))
+DECLARE_PER_CPU(int, cpu_number);
+#define raw_smp_processor_id() (x86_read_percpu(cpu_number))
 extern cpumask_t cpu_callout_map;
 extern cpumask_t cpu_callin_map;
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index a6d20d9a1a30..c3a58c08c495 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -88,65 +88,96 @@ __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 #define savesegment(seg, value) \
        asm volatile("mov %%" #seg ",%0":"=rm" (value))
+static inline void native_clts(void)
+{
+        asm volatile ("clts");
+}
+static inline unsigned long native_read_cr0(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
+        return val;
+}
+static inline void native_write_cr0(unsigned long val)
+{
+        asm volatile("movl %0,%%cr0": :"r" (val));
+}
+static inline unsigned long native_read_cr2(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
+        return val;
+}
+static inline void native_write_cr2(unsigned long val)
+{
+        asm volatile("movl %0,%%cr2": :"r" (val));
+}
+static inline unsigned long native_read_cr3(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
+        return val;
+}
+static inline void native_write_cr3(unsigned long val)
+{
+        asm volatile("movl %0,%%cr3": :"r" (val));
+}
+static inline unsigned long native_read_cr4(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
+        return val;
+}
+static inline unsigned long native_read_cr4_safe(void)
+{
+        unsigned long val;
+        /* This could fault if %cr4 does not exist */
+        asm("1: movl %%cr4, %0          \n"
+                "2:                             \n"
+                ".section __ex_table,\"a\"      \n"
+                ".long 1b,2b                    \n"
+                ".previous                      \n"
+                : "=r" (val): "0" (0));
+        return val;
+}
+static inline void native_write_cr4(unsigned long val)
+{
+        asm volatile("movl %0,%%cr4": :"r" (val));
+}
+static inline void native_wbinvd(void)
+{
+        asm volatile("wbinvd": : :"memory");
+}
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
-#define read_cr0() ({ \
+#define read_cr0()      (native_read_cr0())
-        unsigned int __dummy; \
+#define write_cr0(x)    (native_write_cr0(x))
-        __asm__ __volatile__( \
+#define read_cr2()      (native_read_cr2())
-                "movl %%cr0,%0\n\t" \
+#define write_cr2(x)    (native_write_cr2(x))
-                :"=r" (__dummy)); \
+#define read_cr3()      (native_read_cr3())
-        __dummy; \
+#define write_cr3(x)    (native_write_cr3(x))
-})
+#define read_cr4()      (native_read_cr4())
-#define write_cr0(x) \
+#define read_cr4_safe() (native_read_cr4_safe())
-        __asm__ __volatile__("movl %0,%%cr0": :"r" (x))
+#define write_cr4(x)    (native_write_cr4(x))
+#define wbinvd()        (native_wbinvd())
-#define read_cr2() ({ \
-        unsigned int __dummy; \
-        __asm__ __volatile__( \
-                "movl %%cr2,%0\n\t" \
-                :"=r" (__dummy)); \
-        __dummy; \
-})
-#define write_cr2(x) \
-        __asm__ __volatile__("movl %0,%%cr2": :"r" (x))
-#define read_cr3() ({ \
-        unsigned int __dummy; \
-        __asm__ ( \
-                "movl %%cr3,%0\n\t" \
-                :"=r" (__dummy)); \
-        __dummy; \
-})
-#define write_cr3(x) \
-        __asm__ __volatile__("movl %0,%%cr3": :"r" (x))
-#define read_cr4() ({ \
-        unsigned int __dummy; \
-        __asm__( \
-                "movl %%cr4,%0\n\t" \
-                :"=r" (__dummy)); \
-        __dummy; \
-})
-#define read_cr4_safe() ({                            \
-        unsigned int __dummy;                         \
-        /* This could fault if %cr4 does not exist */ \
-        __asm__("1: movl %%cr4, %0              \n"   \
-                "2:                             \n"   \
-                ".section __ex_table,\"a\"      \n"   \
-                ".long 1b,2b                    \n"   \
-                ".previous                      \n"   \
-                : "=r" (__dummy): "0" (0));           \
-        __dummy;                                      \
-})
-#define write_cr4(x) \
-        __asm__ __volatile__("movl %0,%%cr4": :"r" (x))
-#define wbinvd() \
-        __asm__ __volatile__ ("wbinvd": : :"memory")
 /* Clear the 'TS' bit */
-#define clts() __asm__ __volatile__ ("clts")
+#define clts()          (native_clts())
 #endif/* CONFIG_PARAVIRT */
 /* Set the 'TS' bit */
diff --git a/include/asm-i386/timer.h b/include/asm-i386/timer.h
index 12dd67bf760f..153770e25faa 100644
--- a/include/asm-i386/timer.h
+++ b/include/asm-i386/timer.h
@@ -9,8 +9,6 @@ void setup_pit_timer(void);
 unsigned long long native_sched_clock(void);
 unsigned long native_calculate_cpu_khz(void);
-/* Modifiers for buggy PIT handling */
-extern int pit_latch_buggy;
 extern int timer_ack;
 extern int no_timer_check;
 extern int no_sync_cmos_clock;
diff --git a/include/asm-i386/tlbflush.h b/include/asm-i386/tlbflush.h
index 4dd82840d53b..db7f77eacfa0 100644
--- a/include/asm-i386/tlbflush.h
+++ b/include/asm-i386/tlbflush.h
@@ -79,11 +79,15 @@
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
 *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
+ *  - flush_tlb_others(cpumask, mm, va) flushes a TLBs on other cpus
 *
 * ..but the i386 has somewhat limited tlb flushing capabilities,
 * and page-granular flushes are available only on i486 and up.
 */
+#define TLB_FLUSH_ALL   0xffffffff
 #ifndef CONFIG_SMP
 #define flush_tlb() __flush_tlb()
@@ -110,7 +114,12 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
                __flush_tlb();
 }
-#else
+static inline void native_flush_tlb_others(const cpumask_t *cpumask,
+                                           struct mm_struct *mm, unsigned long va)
+{
+}
+#else  /* SMP */
 #include <asm/smp.h>
@@ -129,6 +138,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
        flush_tlb_mm(vma->vm_mm);
 }
+void native_flush_tlb_others(const cpumask_t *cpumask, struct mm_struct *mm,
+                             unsigned long va);
 #define TLBSTATE_OK     1
 #define TLBSTATE_LAZY   2
@@ -139,8 +151,11 @@ struct tlb_state
        char __cacheline_padding[L1_CACHE_BYTES-8];
 };
 DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
+#endif  /* SMP */
+#ifndef CONFIG_PARAVIRT
+#define flush_tlb_others(mask, mm, va)          \
+        native_flush_tlb_others(&mask, mm, va)
 #endif
 #define flush_tlb_kernel_range(start, end) flush_tlb_all()
diff --git a/include/asm-i386/tsc.h b/include/asm-i386/tsc.h
index 84016ff481b9..3f3c1fa000b4 100644
--- a/include/asm-i386/tsc.h
+++ b/include/asm-i386/tsc.h
@@ -35,25 +35,30 @@ static inline cycles_t get_cycles(void)
 static __always_inline cycles_t get_cycles_sync(void)
 {
        unsigned long long ret;
-#ifdef X86_FEATURE_SYNC_RDTSC
        unsigned eax;
        /*
+         * Use RDTSCP if possible; it is guaranteed to be synchronous
+         * and doesn't cause a VMEXIT on Hypervisors
+         */
+        alternative_io(ASM_NOP3, ".byte 0x0f,0x01,0xf9", X86_FEATURE_RDTSCP,
+                                 "=A" (ret), "0" (0ULL) : "ecx", "memory");
+        if (ret)
+                return ret;
+        /*
         * Don't do an additional sync on CPUs where we know
         * RDTSC is already synchronous:
         */
        alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC,
                          "=a" (eax), "0" (1) : "ebx","ecx","edx","memory");
-#else
-        sync_core();
-#endif
        rdtscll(ret);
        return ret;
 }
 extern void tsc_init(void);
-extern void mark_tsc_unstable(void);
+extern void mark_tsc_unstable(char *reason);
 extern int unsynchronized_tsc(void);
 extern void init_tsc_clocksource(void);
diff --git a/include/asm-i386/uaccess.h b/include/asm-i386/uaccess.h
index 70829ae3ad52..e2aa5e0d0cc7 100644
--- a/include/asm-i386/uaccess.h
+++ b/include/asm-i386/uaccess.h
@@ -397,7 +397,19 @@ unsigned long __must_check __copy_from_user_ll_nocache(void *to,
 unsigned long __must_check __copy_from_user_ll_nocache_nozero(void *to,
                                const void __user *from, unsigned long n);
-/*
+/**
+ * __copy_to_user_inatomic: - Copy a block of data into user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.
+ *
+ * Copy data from kernel space to user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ * The caller should also make sure he pins the user space address
+ * so that the we don't result in page fault and sleep.
+ *
 * Here we special-case 1, 2 and 4-byte copy_*_user invocations.  On a fault
 * we return the initial request size (1, 2 or 4), as copy_*_user should do.
 * If a store crosses a page boundary and gets a fault, the x86 will not write
diff --git a/include/asm-i386/vmi_time.h b/include/asm-i386/vmi_time.h
index c3a1fcf66c96..213930b995cb 100644
--- a/include/asm-i386/vmi_time.h
+++ b/include/asm-i386/vmi_time.h
@@ -53,22 +53,8 @@ extern unsigned long long vmi_get_sched_cycles(void);
 extern unsigned long vmi_cpu_khz(void);
 #ifdef CONFIG_X86_LOCAL_APIC
-extern void __init vmi_timer_setup_boot_alarm(void);
+extern void __devinit vmi_time_bsp_init(void);
-extern void __devinit vmi_timer_setup_secondary_alarm(void);
+extern void __devinit vmi_time_ap_init(void);
-extern void apic_vmi_timer_interrupt(void);
-#endif
-#ifdef CONFIG_NO_IDLE_HZ
-extern int vmi_stop_hz_timer(void);
-extern void vmi_account_time_restart_hz_timer(void);
-#else
-static inline int vmi_stop_hz_timer(void)
-{
-        return 0;
-}
-static inline void vmi_account_time_restart_hz_timer(void)
-{
-}
 #endif
 /*
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index b5c65081a3aa..cef2400983fa 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -29,6 +29,7 @@
 #include <linux/spinlock.h>
 #include <asm/processor.h>
+#include <asm-generic/mm_hooks.h>
 struct ia64_ctx {
        spinlock_t lock;
diff --git a/include/asm-m32r/mmu_context.h b/include/asm-m32r/mmu_context.h
index 1f40d4a0acf1..91909e5dd9d0 100644
--- a/include/asm-m32r/mmu_context.h
+++ b/include/asm-m32r/mmu_context.h
@@ -15,6 +15,7 @@
 #include <asm/pgalloc.h>
 #include <asm/mmu.h>
 #include <asm/tlbflush.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * Cache of MMU context last used.
diff --git a/include/asm-m68k/mmu_context.h b/include/asm-m68k/mmu_context.h
index 231d11bd8e32..894dacbcee14 100644
--- a/include/asm-m68k/mmu_context.h
+++ b/include/asm-m68k/mmu_context.h
@@ -1,6 +1,7 @@
 #ifndef __M68K_MMU_CONTEXT_H
 #define __M68K_MMU_CONTEXT_H
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-m68knommu/mmu_context.h b/include/asm-m68knommu/mmu_context.h
index 6c077d3a2572..9ccee4278c97 100644
--- a/include/asm-m68knommu/mmu_context.h
+++ b/include/asm-m68knommu/mmu_context.h
@@ -4,6 +4,7 @@
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index fe065d6070ca..65024ffd7879 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -20,6 +20,7 @@
 #include <asm/mipsmtregs.h>
 #include <asm/smtc.h>
 #endif /* SMTC */
+#include <asm-generic/mm_hooks.h>
 /*
 * For the fast tlb miss handlers, we keep a per cpu array of pointers
diff --git a/include/asm-parisc/mmu_context.h b/include/asm-parisc/mmu_context.h
index 9c05836239a2..bad690298f0c 100644
--- a/include/asm-parisc/mmu_context.h
+++ b/include/asm-parisc/mmu_context.h
@@ -5,6 +5,7 @@
 #include <asm/atomic.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-powerpc/mmu_context.h b/include/asm-powerpc/mmu_context.h
index 083ac917bd29..c0d7795e3d25 100644
--- a/include/asm-powerpc/mmu_context.h
+++ b/include/asm-powerpc/mmu_context.h
@@ -10,6 +10,7 @@
 #include <linux/mm.h>   
 #include <asm/mmu.h>    
 #include <asm/cputable.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index 2bc8589cc451..a6441a063e5d 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -6,6 +6,7 @@
 #include <asm/bitops.h>
 #include <asm/mmu.h>
 #include <asm/cputable.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
diff --git a/include/asm-s390/mmu_context.h b/include/asm-s390/mmu_context.h
index 1d21da220d49..501cb9b06314 100644
--- a/include/asm-s390/mmu_context.h
+++ b/include/asm-s390/mmu_context.h
@@ -10,6 +10,8 @@
 #define __S390_MMU_CONTEXT_H
 #include <asm/pgalloc.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * get a new mmu context.. S390 don't know about contexts.
 */
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index 342024425b7d..01acaaae9751 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -12,6 +12,7 @@
 #include <asm/tlbflush.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * The MMU "context" consists of two things:
diff --git a/include/asm-sh64/mmu_context.h b/include/asm-sh64/mmu_context.h
index 8c860dab2d0e..507bf72bb8e1 100644
--- a/include/asm-sh64/mmu_context.h
+++ b/include/asm-sh64/mmu_context.h
@@ -27,7 +27,7 @@
 extern unsigned long mmu_context_cache;
 #include <asm/page.h>
+#include <asm-generic/mm_hooks.h>
 /* Current mm's pgd */
 extern pgd_t *mmu_pdtp_cache;
diff --git a/include/asm-sparc/mmu_context.h b/include/asm-sparc/mmu_context.h
index ed1e01d04d21..671a997b9e69 100644
--- a/include/asm-sparc/mmu_context.h
+++ b/include/asm-sparc/mmu_context.h
@@ -5,6 +5,8 @@
 #ifndef __ASSEMBLY__
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
index 2337eb487719..8d129032013e 100644
--- a/include/asm-sparc64/mmu_context.h
+++ b/include/asm-sparc64/mmu_context.h
@@ -9,6 +9,7 @@
 #include <linux/spinlock.h>
 #include <asm/system.h>
 #include <asm/spitfire.h>
+#include <asm-generic/mm_hooks.h>
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-sparc64/percpu.h b/include/asm-sparc64/percpu.h
index 0d3df76aa47f..ced8cbde046d 100644
--- a/include/asm-sparc64/percpu.h
+++ b/include/asm-sparc64/percpu.h
@@ -5,16 +5,6 @@
 #ifdef CONFIG_SMP
-#ifdef CONFIG_MODULES
-# define PERCPU_MODULE_RESERVE 8192
-#else
-# define PERCPU_MODULE_RESERVE 0
-#endif
-#define PERCPU_ENOUGH_ROOM \
-        (ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES) + \
-         PERCPU_MODULE_RESERVE)
 extern void setup_per_cpu_areas(void);
 extern unsigned long __per_cpu_base;
diff --git a/include/asm-um/mmu_context.h b/include/asm-um/mmu_context.h
index f709c784bf12..9aa4b44e8cc1 100644
--- a/include/asm-um/mmu_context.h
+++ b/include/asm-um/mmu_context.h
@@ -6,6 +6,8 @@
 #ifndef __UM_MMU_CONTEXT_H
 #define __UM_MMU_CONTEXT_H
+#include <asm-generic/mm_hooks.h>
 #include "linux/sched.h"
 #include "choose-mode.h"
 #include "um_mmu.h"
diff --git a/include/asm-v850/mmu_context.h b/include/asm-v850/mmu_context.h
index f521c8050d3c..01daacd5474e 100644
--- a/include/asm-v850/mmu_context.h
+++ b/include/asm-v850/mmu_context.h
@@ -1,6 +1,8 @@
 #ifndef __V850_MMU_CONTEXT_H__
 #define __V850_MMU_CONTEXT_H__
+#include <asm-generic/mm_hooks.h>
 #define destroy_context(mm)             ((void)0)
 #define init_new_context(tsk,mm)        0
 #define switch_mm(prev,next,tsk)        ((void)0)
diff --git a/include/asm-x86_64/Kbuild b/include/asm-x86_64/Kbuild
index ebd7117782a6..89ad1fc27c8b 100644
--- a/include/asm-x86_64/Kbuild
+++ b/include/asm-x86_64/Kbuild
@@ -8,7 +8,7 @@ header-y += boot.h
 header-y += bootsetup.h
 header-y += debugreg.h
 header-y += ldt.h
-header-y += msr.h
+header-y += msr-index.h
 header-y += prctl.h
 header-y += ptrace-abi.h
 header-y += sigcontext32.h
@@ -16,5 +16,7 @@ header-y += ucontext.h
 header-y += vsyscall32.h
 unifdef-y += mce.h
+unifdef-y += msr.h
 unifdef-y += mtrr.h
 unifdef-y += vsyscall.h
+unifdef-y += const.h
diff --git a/include/asm-x86_64/alternative.h b/include/asm-x86_64/alternative.h
index a6657b4f3e0e..a09fe85c268e 100644
--- a/include/asm-x86_64/alternative.h
+++ b/include/asm-x86_64/alternative.h
@@ -16,6 +16,7 @@ struct alt_instr {
        u8  pad[5];
 };
+extern void alternative_instructions(void);
 extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
 struct module;
@@ -141,8 +142,8 @@ void apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end);
 static inline void
 apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end)
 {}
-#define __start_parainstructions NULL
+#define __parainstructions NULL
-#define __stop_parainstructions NULL
+#define __parainstructions_end NULL
 #endif
 #endif /* _X86_64_ALTERNATIVE_H */
diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h
index 7cfb39cbd918..45e9fca1febc 100644
--- a/include/asm-x86_64/apic.h
+++ b/include/asm-x86_64/apic.h
@@ -2,6 +2,7 @@
 #define __ASM_APIC_H
 #include <linux/pm.h>
+#include <linux/delay.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
 #include <asm/system.h>
@@ -47,11 +48,8 @@ static __inline unsigned int apic_read(unsigned long reg)
        return *((volatile unsigned int *)(APIC_BASE+reg));
 }
-static __inline__ void apic_wait_icr_idle(void)
+extern void apic_wait_icr_idle(void);
-{
+extern unsigned int safe_apic_wait_icr_idle(void);
-        while (apic_read( APIC_ICR ) & APIC_ICR_BUSY)
-                cpu_relax();
-}
 static inline void ack_APIC_irq(void)
 {
@@ -83,7 +81,7 @@ extern void setup_secondary_APIC_clock (void);
 extern int APIC_init_uniprocessor (void);
 extern void disable_APIC_timer(void);
 extern void enable_APIC_timer(void);
-extern void clustered_apic_check(void);
+extern void setup_apic_routing(void);
 extern void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector,
                                   unsigned char msg_type, unsigned char mask);
diff --git a/include/asm-x86_64/bugs.h b/include/asm-x86_64/bugs.h
index d86c5dd689fa..b33dc04d8f42 100644
--- a/include/asm-x86_64/bugs.h
+++ b/include/asm-x86_64/bugs.h
@@ -1,28 +1,6 @@
-/*
+#ifndef _ASM_X86_64_BUGS_H
- *  include/asm-x86_64/bugs.h
+#define _ASM_X86_64_BUGS_H
- *
- *  Copyright (C) 1994  Linus Torvalds
- *  Copyright (C) 2000  SuSE
- *
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *      void check_bugs(void);
- */
-#include <asm/processor.h>
+void check_bugs(void);
-#include <asm/i387.h>
-#include <asm/msr.h>
-#include <asm/pda.h>
-extern void alternative_instructions(void);
+#endif  /* _ASM_X86_64_BUGS_H */
-static void __init check_bugs(void)
-{
-        identify_cpu(&boot_cpu_data);
-#if !defined(CONFIG_SMP)
-        printk("CPU: ");
-        print_cpu_info(&boot_cpu_data);
-#endif
-        alternative_instructions(); 
-}
diff --git a/include/asm-x86_64/const.h b/include/asm-x86_64/const.h
new file mode 100644
index 000000000000..54fb08f3db9b
--- /dev/null
+++ b/include/asm-x86_64/const.h
@@ -0,0 +1,20 @@
+/* const.h: Macros for dealing with constants.  */
+#ifndef _X86_64_CONST_H
+#define _X86_64_CONST_H
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specificers unilaterally.  We
+ * use the following macros to deal with this.
+ */
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)        X
+#else
+#define __AC(X,Y)       (X##Y)
+#define _AC(X,Y)        __AC(X,Y)
+#endif
+#endif /* !(_X86_64_CONST_H) */
diff --git a/include/asm-x86_64/desc.h b/include/asm-x86_64/desc.h
index 913d6ac00033..ac991b5ca0fd 100644
--- a/include/asm-x86_64/desc.h
+++ b/include/asm-x86_64/desc.h
@@ -107,16 +107,6 @@ static inline void set_ldt_desc(unsigned cpu, void *addr, int size)
                              DESC_LDT, size * 8 - 1);
 }
-static inline void set_seg_base(unsigned cpu, int entry, void *base)
-{ 
-        struct desc_struct *d = &cpu_gdt(cpu)[entry];
-        u32 addr = (u32)(u64)base;
-        BUG_ON((u64)base >> 32); 
-        d->base0 = addr & 0xffff;
-        d->base1 = (addr >> 16) & 0xff;
-        d->base2 = (addr >> 24) & 0xff;
-} 
 #define LDT_entry_a(info) \
        ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
 /* Don't allow setting of the lm bit. It is useless anyways because 
@@ -145,16 +135,13 @@ static inline void set_seg_base(unsigned cpu, int entry, void *base)
        (info)->useable         == 0    && \
        (info)->lm              == 0)
-#if TLS_SIZE != 24
-# error update this code.
-#endif
 static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
 {
+        unsigned int i;
        u64 *gdt = (u64 *)(cpu_gdt(cpu) + GDT_ENTRY_TLS_MIN);
-        gdt[0] = t->tls_array[0];
-        gdt[1] = t->tls_array[1];
+        for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
-        gdt[2] = t->tls_array[2];
+                gdt[i] = t->tls_array[i];
 } 
 /*
diff --git a/include/asm-x86_64/dma-mapping.h b/include/asm-x86_64/dma-mapping.h
index d2af227f06d0..6897e2a436e5 100644
--- a/include/asm-x86_64/dma-mapping.h
+++ b/include/asm-x86_64/dma-mapping.h
@@ -52,7 +52,7 @@ struct dma_mapping_ops {
 };
 extern dma_addr_t bad_dma_address;
-extern struct dma_mapping_ops* dma_ops;
+extern const struct dma_mapping_ops* dma_ops;
 extern int iommu_merge;
 static inline int dma_mapping_error(dma_addr_t dma_addr)
diff --git a/include/asm-x86_64/fixmap.h b/include/asm-x86_64/fixmap.h
index 1b620db5b9e3..e90e1677531b 100644
--- a/include/asm-x86_64/fixmap.h
+++ b/include/asm-x86_64/fixmap.h
@@ -15,7 +15,6 @@
 #include <asm/apicdef.h>
 #include <asm/page.h>
 #include <asm/vsyscall.h>
-#include <asm/vsyscall32.h>
 /*
 * Here we define all the compile-time 'special' virtual
diff --git a/include/asm-x86_64/genapic.h b/include/asm-x86_64/genapic.h
index b80f4bb5f273..d7e516ccbaa4 100644
--- a/include/asm-x86_64/genapic.h
+++ b/include/asm-x86_64/genapic.h
@@ -29,7 +29,9 @@ struct genapic {
        unsigned int (*phys_pkg_id)(int index_msb);
 };
+extern struct genapic *genapic;
-extern struct genapic *genapic, *genapic_force, apic_flat;
+extern struct genapic apic_flat;
+extern struct genapic apic_physflat;
 #endif
diff --git a/include/asm-x86_64/ipi.h b/include/asm-x86_64/ipi.h
index 2a5c162b7d92..a7c75ea408a8 100644
--- a/include/asm-x86_64/ipi.h
+++ b/include/asm-x86_64/ipi.h
@@ -18,10 +18,8 @@
 * Subject to the GNU Public License, v.2
 */
-#include <asm/fixmap.h>
 #include <asm/hw_irq.h>
-#include <asm/apicdef.h>
+#include <asm/apic.h>
-#include <asm/genapic.h>
 /*
 * the following functions deal with sending IPIs between CPUs.
@@ -76,10 +74,42 @@ static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, unsign
        apic_write(APIC_ICR, cfg);
 }
+/*
+ * This is used to send an IPI with no shorthand notation (the destination is
+ * specified in bits 56 to 63 of the ICR).
+ */
+static inline void __send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest)
+{
+        unsigned long cfg;
+        /*
+         * Wait for idle.
+         */
+        if (unlikely(vector == NMI_VECTOR))
+                safe_apic_wait_icr_idle();
+        else
+                apic_wait_icr_idle();
+        /*
+         * prepare target chip field
+         */
+        cfg = __prepare_ICR2(mask);
+        apic_write(APIC_ICR2, cfg);
+        /*
+         * program the ICR
+         */
+        cfg = __prepare_ICR(0, vector, dest);
+        /*
+         * Send the IPI. The write to APIC_ICR fires this off.
+         */
+        apic_write(APIC_ICR, cfg);
+}
 static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
 {
-        unsigned long cfg, flags;
+        unsigned long flags;
        unsigned long query_cpu;
        /*
@@ -88,28 +118,9 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
         * - mbligh
         */
        local_irq_save(flags);
        for_each_cpu_mask(query_cpu, mask) {
-                /*
+                __send_IPI_dest_field(x86_cpu_to_apicid[query_cpu],
-                 * Wait for idle.
+                                      vector, APIC_DEST_PHYSICAL);
-                 */
-                apic_wait_icr_idle();
-                /*
-                 * prepare target chip field
-                 */
-                cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
-                apic_write(APIC_ICR2, cfg);
-                /*
-                 * program the ICR
-                 */
-                cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
-                /*
-                 * Send the IPI. The write to APIC_ICR fires this off.
-                 */
-                apic_write(APIC_ICR, cfg);
        }
        local_irq_restore(flags);
 }
diff --git a/include/asm-x86_64/irqflags.h b/include/asm-x86_64/irqflags.h
index cce6937e87c0..86e70fe23659 100644
--- a/include/asm-x86_64/irqflags.h
+++ b/include/asm-x86_64/irqflags.h
@@ -9,6 +9,7 @@
 */
 #ifndef _ASM_IRQFLAGS_H
 #define _ASM_IRQFLAGS_H
+#include <asm/processor-flags.h>
 #ifndef __ASSEMBLY__
 /*
@@ -53,19 +54,19 @@ static inline void raw_local_irq_disable(void)
 {
        unsigned long flags = __raw_local_save_flags();
-        raw_local_irq_restore((flags & ~(1 << 9)) | (1 << 18));
+        raw_local_irq_restore((flags & ~X86_EFLAGS_IF) | X86_EFLAGS_AC);
 }
 static inline void raw_local_irq_enable(void)
 {
        unsigned long flags = __raw_local_save_flags();
-        raw_local_irq_restore((flags | (1 << 9)) & ~(1 << 18));
+        raw_local_irq_restore((flags | X86_EFLAGS_IF) & (~X86_EFLAGS_AC));
 }
 static inline int raw_irqs_disabled_flags(unsigned long flags)
 {
-        return !(flags & (1<<9)) || (flags & (1 << 18));
+        return !(flags & X86_EFLAGS_IF) || (flags & X86_EFLAGS_AC);
 }
 #else /* CONFIG_X86_VSMP */
@@ -82,7 +83,7 @@ static inline void raw_local_irq_enable(void)
 static inline int raw_irqs_disabled_flags(unsigned long flags)
 {
-        return !(flags & (1 << 9));
+        return !(flags & X86_EFLAGS_IF);
 }
 #endif
diff --git a/include/asm-x86_64/mmu_context.h b/include/asm-x86_64/mmu_context.h
index af03b9f852d6..0cce83a78378 100644
--- a/include/asm-x86_64/mmu_context.h
+++ b/include/asm-x86_64/mmu_context.h
@@ -7,6 +7,7 @@
 #include <asm/pda.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
+#include <asm-generic/mm_hooks.h>
 /*
 * possibly do the LDT unload here?
diff --git a/include/asm-x86_64/mmzone.h b/include/asm-x86_64/mmzone.h
index fb558fb1d211..19a89377b123 100644
--- a/include/asm-x86_64/mmzone.h
+++ b/include/asm-x86_64/mmzone.h
@@ -49,7 +49,7 @@ extern int pfn_valid(unsigned long pfn);
 #ifdef CONFIG_NUMA_EMU
 #define FAKE_NODE_MIN_SIZE      (64*1024*1024)
-#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1ul))
+#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1uL))
 #endif
 #endif
diff --git a/include/asm-x86_64/msr-index.h b/include/asm-x86_64/msr-index.h
new file mode 100644
index 000000000000..d77a63f1ddf2
--- /dev/null
+++ b/include/asm-x86_64/msr-index.h
@@ -0,0 +1 @@
+#include <asm-i386/msr-index.h>
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index 902f9a58617e..a524f0325673 100644
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -1,6 +1,8 @@
 #ifndef X86_64_MSR_H
 #define X86_64_MSR_H 1
+#include <asm/msr-index.h>
 #ifndef __ASSEMBLY__
 /*
 * Access to machine-specific registers (available on 586 and better only)
@@ -157,9 +159,6 @@ static inline unsigned int cpuid_edx(unsigned int op)
        return edx;
 }
-#define MSR_IA32_UCODE_WRITE            0x79
-#define MSR_IA32_UCODE_REV              0x8b
 #ifdef CONFIG_SMP
 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
@@ -172,269 +171,6 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
        wrmsr(msr_no, l, h);
 }
-#endif  /*  CONFIG_SMP  */
+#endif  /* CONFIG_SMP */
+#endif /* __ASSEMBLY__ */
-#endif
+#endif  /* X86_64_MSR_H */
-/* AMD/K8 specific MSRs */ 
-#define MSR_EFER 0xc0000080             /* extended feature register */
-#define MSR_STAR 0xc0000081             /* legacy mode SYSCALL target */
-#define MSR_LSTAR 0xc0000082            /* long mode SYSCALL target */
-#define MSR_CSTAR 0xc0000083            /* compatibility mode SYSCALL target */
-#define MSR_SYSCALL_MASK 0xc0000084     /* EFLAGS mask for syscall */
-#define MSR_FS_BASE 0xc0000100          /* 64bit FS base */
-#define MSR_GS_BASE 0xc0000101          /* 64bit GS base */
-#define MSR_KERNEL_GS_BASE  0xc0000102  /* SwapGS GS shadow (or USER_GS from kernel) */ 
-/* EFER bits: */ 
-#define _EFER_SCE 0  /* SYSCALL/SYSRET */
-#define _EFER_LME 8  /* Long mode enable */
-#define _EFER_LMA 10 /* Long mode active (read-only) */
-#define _EFER_NX 11  /* No execute enable */
-#define EFER_SCE (1<<_EFER_SCE)
-#define EFER_LME (1<<_EFER_LME)
-#define EFER_LMA (1<<_EFER_LMA)
-#define EFER_NX (1<<_EFER_NX)
-/* Intel MSRs. Some also available on other CPUs */
-#define MSR_IA32_TSC            0x10
-#define MSR_IA32_PLATFORM_ID    0x17
-#define MSR_IA32_PERFCTR0      0xc1
-#define MSR_IA32_PERFCTR1      0xc2
-#define MSR_FSB_FREQ            0xcd
-#define MSR_MTRRcap             0x0fe
-#define MSR_IA32_BBL_CR_CTL        0x119
-#define MSR_IA32_SYSENTER_CS    0x174
-#define MSR_IA32_SYSENTER_ESP   0x175
-#define MSR_IA32_SYSENTER_EIP   0x176
-#define MSR_IA32_MCG_CAP       0x179
-#define MSR_IA32_MCG_STATUS        0x17a
-#define MSR_IA32_MCG_CTL       0x17b
-#define MSR_IA32_EVNTSEL0      0x186
-#define MSR_IA32_EVNTSEL1      0x187
-#define MSR_IA32_DEBUGCTLMSR       0x1d9
-#define MSR_IA32_LASTBRANCHFROMIP  0x1db
-#define MSR_IA32_LASTBRANCHTOIP        0x1dc
-#define MSR_IA32_LASTINTFROMIP     0x1dd
-#define MSR_IA32_LASTINTTOIP       0x1de
-#define MSR_IA32_PEBS_ENABLE            0x3f1
-#define MSR_IA32_DS_AREA                0x600
-#define MSR_IA32_PERF_CAPABILITIES      0x345
-#define MSR_MTRRfix64K_00000    0x250
-#define MSR_MTRRfix16K_80000    0x258
-#define MSR_MTRRfix16K_A0000    0x259
-#define MSR_MTRRfix4K_C0000     0x268
-#define MSR_MTRRfix4K_C8000     0x269
-#define MSR_MTRRfix4K_D0000     0x26a
-#define MSR_MTRRfix4K_D8000     0x26b
-#define MSR_MTRRfix4K_E0000     0x26c
-#define MSR_MTRRfix4K_E8000     0x26d
-#define MSR_MTRRfix4K_F0000     0x26e
-#define MSR_MTRRfix4K_F8000     0x26f
-#define MSR_MTRRdefType         0x2ff
-#define MSR_IA32_MC0_CTL       0x400
-#define MSR_IA32_MC0_STATUS        0x401
-#define MSR_IA32_MC0_ADDR      0x402
-#define MSR_IA32_MC0_MISC      0x403
-#define MSR_P6_PERFCTR0                 0xc1
-#define MSR_P6_PERFCTR1                 0xc2
-#define MSR_P6_EVNTSEL0                 0x186
-#define MSR_P6_EVNTSEL1                 0x187
-/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
-#define MSR_K7_EVNTSEL0            0xC0010000
-#define MSR_K7_PERFCTR0            0xC0010004
-#define MSR_K7_EVNTSEL1            0xC0010001
-#define MSR_K7_PERFCTR1            0xC0010005
-#define MSR_K7_EVNTSEL2            0xC0010002
-#define MSR_K7_PERFCTR2            0xC0010006
-#define MSR_K7_EVNTSEL3            0xC0010003
-#define MSR_K7_PERFCTR3            0xC0010007
-#define MSR_K8_TOP_MEM1            0xC001001A
-#define MSR_K8_TOP_MEM2            0xC001001D
-#define MSR_K8_SYSCFG              0xC0010010
-#define MSR_K8_HWCR                0xC0010015
-/* K6 MSRs */
-#define MSR_K6_EFER                     0xC0000080
-#define MSR_K6_STAR                     0xC0000081
-#define MSR_K6_WHCR                     0xC0000082
-#define MSR_K6_UWCCR                    0xC0000085
-#define MSR_K6_PSOR                     0xC0000087
-#define MSR_K6_PFIR                     0xC0000088
-/* Centaur-Hauls/IDT defined MSRs. */
-#define MSR_IDT_FCR1                    0x107
-#define MSR_IDT_FCR2                    0x108
-#define MSR_IDT_FCR3                    0x109
-#define MSR_IDT_FCR4                    0x10a
-#define MSR_IDT_MCR0                    0x110
-#define MSR_IDT_MCR1                    0x111
-#define MSR_IDT_MCR2                    0x112
-#define MSR_IDT_MCR3                    0x113
-#define MSR_IDT_MCR4                    0x114
-#define MSR_IDT_MCR5                    0x115
-#define MSR_IDT_MCR6                    0x116
-#define MSR_IDT_MCR7                    0x117
-#define MSR_IDT_MCR_CTRL                0x120
-/* VIA Cyrix defined MSRs*/
-#define MSR_VIA_FCR                     0x1107
-#define MSR_VIA_LONGHAUL                0x110a
-#define MSR_VIA_RNG                     0x110b
-#define MSR_VIA_BCR2                    0x1147
-/* Intel defined MSRs. */
-#define MSR_IA32_P5_MC_ADDR             0
-#define MSR_IA32_P5_MC_TYPE             1
-#define MSR_IA32_PLATFORM_ID            0x17
-#define MSR_IA32_EBL_CR_POWERON         0x2a
-#define MSR_IA32_APICBASE               0x1b
-#define MSR_IA32_APICBASE_BSP           (1<<8)
-#define MSR_IA32_APICBASE_ENABLE        (1<<11)
-#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
-/* P4/Xeon+ specific */
-#define MSR_IA32_MCG_EAX                0x180
-#define MSR_IA32_MCG_EBX                0x181
-#define MSR_IA32_MCG_ECX                0x182
-#define MSR_IA32_MCG_EDX                0x183
-#define MSR_IA32_MCG_ESI                0x184
-#define MSR_IA32_MCG_EDI                0x185
-#define MSR_IA32_MCG_EBP                0x186
-#define MSR_IA32_MCG_ESP                0x187
-#define MSR_IA32_MCG_EFLAGS             0x188
-#define MSR_IA32_MCG_EIP                0x189
-#define MSR_IA32_MCG_RESERVED           0x18A
-#define MSR_P6_EVNTSEL0                 0x186
-#define MSR_P6_EVNTSEL1                 0x187
-#define MSR_IA32_PERF_STATUS            0x198
-#define MSR_IA32_PERF_CTL               0x199
-#define MSR_IA32_MPERF                  0xE7
-#define MSR_IA32_APERF                  0xE8
-#define MSR_IA32_THERM_CONTROL          0x19a
-#define MSR_IA32_THERM_INTERRUPT        0x19b
-#define MSR_IA32_THERM_STATUS           0x19c
-#define MSR_IA32_MISC_ENABLE            0x1a0
-#define MSR_IA32_DEBUGCTLMSR            0x1d9
-#define MSR_IA32_LASTBRANCHFROMIP       0x1db
-#define MSR_IA32_LASTBRANCHTOIP         0x1dc
-#define MSR_IA32_LASTINTFROMIP          0x1dd
-#define MSR_IA32_LASTINTTOIP            0x1de
-#define MSR_IA32_MC0_CTL                0x400
-#define MSR_IA32_MC0_STATUS             0x401
-#define MSR_IA32_MC0_ADDR               0x402
-#define MSR_IA32_MC0_MISC               0x403
-/* Pentium IV performance counter MSRs */
-#define MSR_P4_BPU_PERFCTR0             0x300
-#define MSR_P4_BPU_PERFCTR1             0x301
-#define MSR_P4_BPU_PERFCTR2             0x302
-#define MSR_P4_BPU_PERFCTR3             0x303
-#define MSR_P4_MS_PERFCTR0              0x304
-#define MSR_P4_MS_PERFCTR1              0x305
-#define MSR_P4_MS_PERFCTR2              0x306
-#define MSR_P4_MS_PERFCTR3              0x307
-#define MSR_P4_FLAME_PERFCTR0           0x308
-#define MSR_P4_FLAME_PERFCTR1           0x309
-#define MSR_P4_FLAME_PERFCTR2           0x30a
-#define MSR_P4_FLAME_PERFCTR3           0x30b
-#define MSR_P4_IQ_PERFCTR0              0x30c
-#define MSR_P4_IQ_PERFCTR1              0x30d
-#define MSR_P4_IQ_PERFCTR2              0x30e
-#define MSR_P4_IQ_PERFCTR3              0x30f
-#define MSR_P4_IQ_PERFCTR4              0x310
-#define MSR_P4_IQ_PERFCTR5              0x311
-#define MSR_P4_BPU_CCCR0                0x360
-#define MSR_P4_BPU_CCCR1                0x361
-#define MSR_P4_BPU_CCCR2                0x362
-#define MSR_P4_BPU_CCCR3                0x363
-#define MSR_P4_MS_CCCR0                 0x364
-#define MSR_P4_MS_CCCR1                 0x365
-#define MSR_P4_MS_CCCR2                 0x366
-#define MSR_P4_MS_CCCR3                 0x367
-#define MSR_P4_FLAME_CCCR0              0x368
-#define MSR_P4_FLAME_CCCR1              0x369
-#define MSR_P4_FLAME_CCCR2              0x36a
-#define MSR_P4_FLAME_CCCR3              0x36b
-#define MSR_P4_IQ_CCCR0                 0x36c
-#define MSR_P4_IQ_CCCR1                 0x36d
-#define MSR_P4_IQ_CCCR2                 0x36e
-#define MSR_P4_IQ_CCCR3                 0x36f
-#define MSR_P4_IQ_CCCR4                 0x370
-#define MSR_P4_IQ_CCCR5                 0x371
-#define MSR_P4_ALF_ESCR0                0x3ca
-#define MSR_P4_ALF_ESCR1                0x3cb
-#define MSR_P4_BPU_ESCR0                0x3b2
-#define MSR_P4_BPU_ESCR1                0x3b3
-#define MSR_P4_BSU_ESCR0                0x3a0
-#define MSR_P4_BSU_ESCR1                0x3a1
-#define MSR_P4_CRU_ESCR0                0x3b8
-#define MSR_P4_CRU_ESCR1                0x3b9
-#define MSR_P4_CRU_ESCR2                0x3cc
-#define MSR_P4_CRU_ESCR3                0x3cd
-#define MSR_P4_CRU_ESCR4                0x3e0
-#define MSR_P4_CRU_ESCR5                0x3e1
-#define MSR_P4_DAC_ESCR0                0x3a8
-#define MSR_P4_DAC_ESCR1                0x3a9
-#define MSR_P4_FIRM_ESCR0               0x3a4
-#define MSR_P4_FIRM_ESCR1               0x3a5
-#define MSR_P4_FLAME_ESCR0              0x3a6
-#define MSR_P4_FLAME_ESCR1              0x3a7
-#define MSR_P4_FSB_ESCR0                0x3a2
-#define MSR_P4_FSB_ESCR1                0x3a3
-#define MSR_P4_IQ_ESCR0                 0x3ba
-#define MSR_P4_IQ_ESCR1                 0x3bb
-#define MSR_P4_IS_ESCR0                 0x3b4
-#define MSR_P4_IS_ESCR1                 0x3b5
-#define MSR_P4_ITLB_ESCR0               0x3b6
-#define MSR_P4_ITLB_ESCR1               0x3b7
-#define MSR_P4_IX_ESCR0                 0x3c8
-#define MSR_P4_IX_ESCR1                 0x3c9
-#define MSR_P4_MOB_ESCR0                0x3aa
-#define MSR_P4_MOB_ESCR1                0x3ab
-#define MSR_P4_MS_ESCR0                 0x3c0
-#define MSR_P4_MS_ESCR1                 0x3c1
-#define MSR_P4_PMH_ESCR0                0x3ac
-#define MSR_P4_PMH_ESCR1                0x3ad
-#define MSR_P4_RAT_ESCR0                0x3bc
-#define MSR_P4_RAT_ESCR1                0x3bd
-#define MSR_P4_SAAT_ESCR0               0x3ae
-#define MSR_P4_SAAT_ESCR1               0x3af
-#define MSR_P4_SSU_ESCR0                0x3be
-#define MSR_P4_SSU_ESCR1                0x3bf    /* guess: not defined in manual */
-#define MSR_P4_TBPU_ESCR0               0x3c2
-#define MSR_P4_TBPU_ESCR1               0x3c3
-#define MSR_P4_TC_ESCR0                 0x3c4
-#define MSR_P4_TC_ESCR1                 0x3c5
-#define MSR_P4_U2L_ESCR0                0x3b0
-#define MSR_P4_U2L_ESCR1                0x3b1
-/* Intel Core-based CPU performance counters */
-#define MSR_CORE_PERF_FIXED_CTR0        0x309
-#define MSR_CORE_PERF_FIXED_CTR1        0x30a
-#define MSR_CORE_PERF_FIXED_CTR2        0x30b
-#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
-#define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
-#define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
-#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
-#endif
diff --git a/include/asm-x86_64/mtrr.h b/include/asm-x86_64/mtrr.h
index d6135b2549bf..b557c486bef8 100644
--- a/include/asm-x86_64/mtrr.h
+++ b/include/asm-x86_64/mtrr.h
@@ -135,6 +135,18 @@ struct mtrr_gentry32
 #endif /* CONFIG_COMPAT */
+#ifdef CONFIG_MTRR
+extern void mtrr_ap_init(void);
+extern void mtrr_bp_init(void);
+extern void mtrr_save_fixed_ranges(void *);
+extern void mtrr_save_state(void);
+#else
+#define mtrr_ap_init() do {} while (0)
+#define mtrr_bp_init() do {} while (0)
+#define mtrr_save_fixed_ranges(arg) do {} while (0)
+#define mtrr_save_state() do {} while (0)
+#endif
 #endif /* __KERNEL__ */
 #endif  /*  _LINUX_MTRR_H  */
diff --git a/include/asm-x86_64/nmi.h b/include/asm-x86_64/nmi.h
index 72375e7d32a8..d0a7f53b1497 100644
--- a/include/asm-x86_64/nmi.h
+++ b/include/asm-x86_64/nmi.h
@@ -80,4 +80,13 @@ extern int unknown_nmi_panic;
 void __trigger_all_cpu_backtrace(void);
 #define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
+void lapic_watchdog_stop(void);
+int lapic_watchdog_init(unsigned nmi_hz);
+int lapic_wd_event(unsigned nmi_hz);
+unsigned lapic_adjust_nmi_hz(unsigned hz);
+int lapic_watchdog_ok(void);
+void disable_lapic_nmi_watchdog(void);
+void enable_lapic_nmi_watchdog(void);
 #endif /* ASM_NMI_H */
diff --git a/include/asm-x86_64/page.h b/include/asm-x86_64/page.h
index 10f346165cab..b17fc16ec2eb 100644
--- a/include/asm-x86_64/page.h
+++ b/include/asm-x86_64/page.h
@@ -1,14 +1,11 @@
 #ifndef _X86_64_PAGE_H
 #define _X86_64_PAGE_H
+#include <asm/const.h>
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT      12
-#ifdef __ASSEMBLY__
+#define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_SIZE       (0x1 << PAGE_SHIFT)
-#else
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#endif
 #define PAGE_MASK       (~(PAGE_SIZE-1))
 #define PHYSICAL_PAGE_MASK      (~(PAGE_SIZE-1) & __PHYSICAL_MASK)
@@ -33,10 +30,10 @@
 #define N_EXCEPTION_STACKS 5  /* hw limit: 7 */
 #define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE-1))
-#define LARGE_PAGE_SIZE (1UL << PMD_SHIFT)
+#define LARGE_PAGE_SIZE (_AC(1,UL) << PMD_SHIFT)
 #define HPAGE_SHIFT PMD_SHIFT
-#define HPAGE_SIZE      ((1UL) << HPAGE_SHIFT)
+#define HPAGE_SIZE      (_AC(1,UL) << HPAGE_SHIFT)
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
@@ -64,6 +61,8 @@ typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
+extern unsigned long phys_base;
 #define pte_val(x)      ((x).pte)
 #define pmd_val(x)      ((x).pmd)
 #define pud_val(x)      ((x).pud)
@@ -76,29 +75,25 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define __pgd(x) ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
-#define __PHYSICAL_START        ((unsigned long)CONFIG_PHYSICAL_START)
+#endif /* !__ASSEMBLY__ */
-#define __START_KERNEL          (__START_KERNEL_map + __PHYSICAL_START)
-#define __START_KERNEL_map      0xffffffff80000000UL
-#define __PAGE_OFFSET           0xffff810000000000UL
-#else
 #define __PHYSICAL_START        CONFIG_PHYSICAL_START
+#define __KERNEL_ALIGN          0x200000
 #define __START_KERNEL          (__START_KERNEL_map + __PHYSICAL_START)
 #define __START_KERNEL_map      0xffffffff80000000
 #define __PAGE_OFFSET           0xffff810000000000
-#endif /* !__ASSEMBLY__ */
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
 /* See Documentation/x86_64/mm.txt for a description of the memory map. */
 #define __PHYSICAL_MASK_SHIFT   46
-#define __PHYSICAL_MASK         ((1UL << __PHYSICAL_MASK_SHIFT) - 1)
+#define __PHYSICAL_MASK         ((_AC(1,UL) << __PHYSICAL_MASK_SHIFT) - 1)
 #define __VIRTUAL_MASK_SHIFT    48
-#define __VIRTUAL_MASK          ((1UL << __VIRTUAL_MASK_SHIFT) - 1)
+#define __VIRTUAL_MASK          ((_AC(1,UL) << __VIRTUAL_MASK_SHIFT) - 1)
-#define KERNEL_TEXT_SIZE  (40UL*1024*1024)
+#define KERNEL_TEXT_SIZE  (40*1024*1024)
-#define KERNEL_TEXT_START 0xffffffff80000000UL 
+#define KERNEL_TEXT_START 0xffffffff80000000
 #ifndef __ASSEMBLY__
@@ -106,21 +101,19 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #endif /* __ASSEMBLY__ */
-#define PAGE_OFFSET             ((unsigned long)__PAGE_OFFSET)
+#define PAGE_OFFSET             __PAGE_OFFSET
 /* Note: __pa(&symbol_visible_to_c) should be always replaced with __pa_symbol.
-   Otherwise you risk miscompilation. */ 
+   Otherwise you risk miscompilation. */
-#define __pa(x)                 (((unsigned long)(x)>=__START_KERNEL_map)?(unsigned long)(x) - (unsigned long)__START_KERNEL_map:(unsigned long)(x) - PAGE_OFFSET)
+#define __pa(x)                 ((unsigned long)(x) - PAGE_OFFSET)
 /* __pa_symbol should be used for C visible symbols.
   This seems to be the official gcc blessed way to do such arithmetic. */ 
 #define __pa_symbol(x)          \
        ({unsigned long v;  \
          asm("" : "=r" (v) : "0" (x)); \
-          __pa(v); })
+          ((v - __START_KERNEL_map) + phys_base); })
 #define __va(x)                 ((void *)((unsigned long)(x)+PAGE_OFFSET))
-#define __boot_va(x)            __va(x)
-#define __boot_pa(x)            __pa(x)
 #ifdef CONFIG_FLATMEM
 #define pfn_valid(pfn)          ((pfn) < end_pfn)
 #endif
diff --git a/include/asm-x86_64/percpu.h b/include/asm-x86_64/percpu.h
index 5ed0ef340842..c6fbb67eac90 100644
--- a/include/asm-x86_64/percpu.h
+++ b/include/asm-x86_64/percpu.h
@@ -11,16 +11,6 @@
 #include <asm/pda.h>
-#ifdef CONFIG_MODULES
-# define PERCPU_MODULE_RESERVE 8192
-#else
-# define PERCPU_MODULE_RESERVE 0
-#endif
-#define PERCPU_ENOUGH_ROOM \
-        (ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES) + \
-         PERCPU_MODULE_RESERVE)
 #define __per_cpu_offset(cpu) (cpu_pda(cpu)->data_offset)
 #define __my_cpu_offset() read_pda(data_offset)
diff --git a/include/asm-x86_64/pgalloc.h b/include/asm-x86_64/pgalloc.h
index 4e28b6060a5e..8bb564687860 100644
--- a/include/asm-x86_64/pgalloc.h
+++ b/include/asm-x86_64/pgalloc.h
@@ -1,7 +1,6 @@
 #ifndef _X86_64_PGALLOC_H
 #define _X86_64_PGALLOC_H
-#include <asm/fixmap.h>
 #include <asm/pda.h>
 #include <linux/threads.h>
 #include <linux/mm.h>
@@ -45,24 +44,16 @@ static inline void pgd_list_add(pgd_t *pgd)
        struct page *page = virt_to_page(pgd);
        spin_lock(&pgd_lock);
-        page->index = (pgoff_t)pgd_list;
+        list_add(&page->lru, &pgd_list);
-        if (pgd_list)
-                pgd_list->private = (unsigned long)&page->index;
-        pgd_list = page;
-        page->private = (unsigned long)&pgd_list;
        spin_unlock(&pgd_lock);
 }
 static inline void pgd_list_del(pgd_t *pgd)
 {
-        struct page *next, **pprev, *page = virt_to_page(pgd);
+        struct page *page = virt_to_page(pgd);
        spin_lock(&pgd_lock);
-        next = (struct page *)page->index;
+        list_del(&page->lru);
-        pprev = (struct page **)page->private;
-        *pprev = next;
-        if (next)
-                next->private = (unsigned long)pprev;
        spin_unlock(&pgd_lock);
 }
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index 730bd6028416..599993f6ba84 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -1,25 +1,25 @@
 #ifndef _X86_64_PGTABLE_H
 #define _X86_64_PGTABLE_H
+#include <asm/const.h>
+#ifndef __ASSEMBLY__
 /*
 * This file contains the functions and defines necessary to modify and use
 * the x86-64 page table tree.
 */
 #include <asm/processor.h>
-#include <asm/fixmap.h>
 #include <asm/bitops.h>
 #include <linux/threads.h>
 #include <asm/pda.h>
 extern pud_t level3_kernel_pgt[512];
-extern pud_t level3_physmem_pgt[512];
 extern pud_t level3_ident_pgt[512];
 extern pmd_t level2_kernel_pgt[512];
 extern pgd_t init_level4_pgt[];
-extern pgd_t boot_level4_pgt[];
 extern unsigned long __supported_pte_mask;
-#define swapper_pg_dir init_level4_pgt
+#define swapper_pg_dir ((pgd_t *)NULL)
 extern void paging_init(void);
 extern void clear_kernel_mapping(unsigned long addr, unsigned long size);
@@ -29,7 +29,9 @@ extern void clear_kernel_mapping(unsigned long addr, unsigned long size);
 * for zero-mapped memory areas etc..
 */
 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+#define ZERO_PAGE(vaddr) (pfn_to_page(__pa_symbol(&empty_zero_page) >> PAGE_SHIFT))
+#endif /* !__ASSEMBLY__ */
 /*
 * PGDIR_SHIFT determines what a top-level page table entry can map
@@ -55,6 +57,8 @@ extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 */
 #define PTRS_PER_PTE    512
+#ifndef __ASSEMBLY__
 #define pte_ERROR(e) \
        printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
 #define pmd_ERROR(e) \
@@ -118,22 +122,23 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long
 #define pte_pgprot(a)   (__pgprot((a).pte & ~PHYSICAL_PAGE_MASK))
-#define PMD_SIZE        (1UL << PMD_SHIFT)
+#endif /* !__ASSEMBLY__ */
+#define PMD_SIZE        (_AC(1,UL) << PMD_SHIFT)
 #define PMD_MASK        (~(PMD_SIZE-1))
-#define PUD_SIZE        (1UL << PUD_SHIFT)
+#define PUD_SIZE        (_AC(1,UL) << PUD_SHIFT)
 #define PUD_MASK        (~(PUD_SIZE-1))
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_SIZE      (_AC(1,UL) << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 #define USER_PTRS_PER_PGD       ((TASK_SIZE-1)/PGDIR_SIZE+1)
 #define FIRST_USER_ADDRESS      0
-#ifndef __ASSEMBLY__
+#define MAXMEM           0x3fffffffffff
-#define MAXMEM           0x3fffffffffffUL
+#define VMALLOC_START    0xffffc20000000000
-#define VMALLOC_START    0xffffc20000000000UL
+#define VMALLOC_END      0xffffe1ffffffffff
-#define VMALLOC_END      0xffffe1ffffffffffUL
+#define MODULES_VADDR    0xffffffff88000000
-#define MODULES_VADDR    0xffffffff88000000UL
+#define MODULES_END      0xfffffffffff00000
-#define MODULES_END      0xfffffffffff00000UL
 #define MODULES_LEN   (MODULES_END - MODULES_VADDR)
 #define _PAGE_BIT_PRESENT       0
@@ -159,7 +164,7 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long
 #define _PAGE_GLOBAL    0x100   /* Global TLB entry */
 #define _PAGE_PROTNONE  0x080   /* If not present */
-#define _PAGE_NX        (1UL<<_PAGE_BIT_NX)
+#define _PAGE_NX        (_AC(1,UL)<<_PAGE_BIT_NX)
 #define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
 #define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
@@ -221,6 +226,8 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long
 #define __S110  PAGE_SHARED_EXEC
 #define __S111  PAGE_SHARED_EXEC
+#ifndef __ASSEMBLY__
 static inline unsigned long pgd_bad(pgd_t pgd)
 {
        return pgd_val(pgd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
@@ -403,11 +410,9 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 extern spinlock_t pgd_lock;
-extern struct page *pgd_list;
+extern struct list_head pgd_list;
 void vmalloc_sync_all(void);
-#endif /* !__ASSEMBLY__ */
 extern int kern_addr_valid(unsigned long addr); 
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
@@ -437,5 +442,6 @@ extern int kern_addr_valid(unsigned long addr);
 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 #define __HAVE_ARCH_PTE_SAME
 #include <asm-generic/pgtable.h>
+#endif /* !__ASSEMBLY__ */
 #endif /* _X86_64_PGTABLE_H */
diff --git a/include/asm-x86_64/processor-flags.h b/include/asm-x86_64/processor-flags.h
new file mode 100644
index 000000000000..ec99a57b2c6a
--- /dev/null
+++ b/include/asm-x86_64/processor-flags.h
@@ -0,0 +1 @@
+#include <asm-i386/processor-flags.h>
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index 76552d72804c..461ffe4c1fcc 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -20,6 +20,7 @@
 #include <asm/percpu.h>
 #include <linux/personality.h>
 #include <linux/cpumask.h>
+#include <asm/processor-flags.h>
 #define TF_MASK         0x00000100
 #define IF_MASK         0x00000200
@@ -103,42 +104,6 @@ extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
 /*
- * EFLAGS bits
- */
-#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
-#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
-#define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
-#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
-#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
-#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
-#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
-#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
-#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
-#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
-#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
-#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
-#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
-#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
-#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
-#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
-#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
-/*
- * Intel CPU features in CR4
- */
-#define X86_CR4_VME             0x0001  /* enable vm86 extensions */
-#define X86_CR4_PVI             0x0002  /* virtual interrupts flag enable */
-#define X86_CR4_TSD             0x0004  /* disable time stamp at ipl 3 */
-#define X86_CR4_DE              0x0008  /* enable debugging extensions */
-#define X86_CR4_PSE             0x0010  /* enable page size extensions */
-#define X86_CR4_PAE             0x0020  /* enable physical address extensions */
-#define X86_CR4_MCE             0x0040  /* Machine check enable */
-#define X86_CR4_PGE             0x0080  /* enable global pages */
-#define X86_CR4_PCE             0x0100  /* enable performance counters at ipl 3 */
-#define X86_CR4_OSFXSR          0x0200  /* enable fast FPU save and restore */
-#define X86_CR4_OSXMMEXCPT      0x0400  /* enable unmasked SSE exceptions */
-/*
 * Save the cr4 feature set we're using (ie
 * Pentium 4MB enable and PPro Global page
 * enable), so that any CPU's that boot up
@@ -201,7 +166,7 @@ struct i387_fxsave_struct {
        u32     mxcsr;
        u32     mxcsr_mask;
        u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
-        u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 128 bytes */
+        u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 256 bytes */
        u32     padding[24];
 } __attribute__ ((aligned (16)));
@@ -427,22 +392,6 @@ static inline void prefetchw(void *x)
 #define cpu_relax()   rep_nop()
 /*
- *      NSC/Cyrix CPU configuration register indexes
- */
-#define CX86_CCR0 0xc0
-#define CX86_CCR1 0xc1
-#define CX86_CCR2 0xc2
-#define CX86_CCR3 0xc3
-#define CX86_CCR4 0xe8
-#define CX86_CCR5 0xe9
-#define CX86_CCR6 0xea
-#define CX86_CCR7 0xeb
-#define CX86_DIR0 0xfe
-#define CX86_DIR1 0xff
-#define CX86_ARR_BASE 0xc4
-#define CX86_RCR_BASE 0xdc
-/*
 *      NSC/Cyrix CPU indexed register access macros
 */
diff --git a/include/asm-x86_64/proto.h b/include/asm-x86_64/proto.h
index b6e65a699f2a..85255db1e82d 100644
--- a/include/asm-x86_64/proto.h
+++ b/include/asm-x86_64/proto.h
@@ -11,18 +11,9 @@ struct pt_regs;
 extern void start_kernel(void);
 extern void pda_init(int); 
-extern void zap_low_mappings(int cpu);
 extern void early_idt_handler(void);
 extern void mcheck_init(struct cpuinfo_x86 *c);
-#ifdef CONFIG_MTRR
-extern void mtrr_ap_init(void);
-extern void mtrr_bp_init(void);
-#else
-#define mtrr_ap_init() do {} while (0)
-#define mtrr_bp_init() do {} while (0)
-#endif
 extern void init_memory_mapping(unsigned long start, unsigned long end);
 extern void system_call(void); 
@@ -82,7 +73,6 @@ extern void syscall32_cpu_init(void);
 extern void setup_node_bootmem(int nodeid, unsigned long start, unsigned long end);
 extern void early_quirks(void);
-extern void quirk_intel_irqbalance(void);
 extern void check_efer(void);
 extern int unhandled_signal(struct task_struct *tsk, int sig);
@@ -93,6 +83,7 @@ extern unsigned long table_start, table_end;
 extern int exception_trace;
 extern unsigned cpu_khz;
+extern unsigned tsc_khz;
 extern void no_iommu_init(void);
 extern int force_iommu, no_iommu;
@@ -121,8 +112,12 @@ extern int gsi_irq_sharing(int gsi);
 extern void smp_local_timer_interrupt(void);
+extern int force_mwait;
 long do_arch_prctl(struct task_struct *task, int code, unsigned long addr);
+void i8254_timer_resume(void);
 #define round_up(x,y) (((x) + (y) - 1) & ~((y)-1))
 #define round_down(x,y) ((x) & ~((y)-1))
diff --git a/include/asm-x86_64/segment.h b/include/asm-x86_64/segment.h
index 334ddcdd8f92..adf2bf1e187c 100644
--- a/include/asm-x86_64/segment.h
+++ b/include/asm-x86_64/segment.h
@@ -6,7 +6,7 @@
 #define __KERNEL_CS     0x10
 #define __KERNEL_DS     0x18
-#define __KERNEL32_CS   0x38
+#define __KERNEL32_CS   0x08
 /* 
 * we cannot use the same code segment descriptor for user and kernel
diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h
index de592a408c07..d5704421456b 100644
--- a/include/asm-x86_64/smp.h
+++ b/include/asm-x86_64/smp.h
@@ -10,10 +10,9 @@
 #include <linux/init.h>
 extern int disable_apic;
-#include <asm/fixmap.h>
 #include <asm/mpspec.h>
-#include <asm/io_apic.h>
 #include <asm/apic.h>
+#include <asm/io_apic.h>
 #include <asm/thread_info.h>
 #ifdef CONFIG_SMP
@@ -38,7 +37,6 @@ extern void lock_ipi_call_lock(void);
 extern void unlock_ipi_call_lock(void);
 extern int smp_num_siblings;
 extern void smp_send_reschedule(int cpu);
-void smp_stop_cpu(void);
 extern cpumask_t cpu_sibling_map[NR_CPUS];
 extern cpumask_t cpu_core_map[NR_CPUS];
diff --git a/include/asm-x86_64/suspend.h b/include/asm-x86_64/suspend.h
index bc7f81715e5e..9c3f8de90d2d 100644
--- a/include/asm-x86_64/suspend.h
+++ b/include/asm-x86_64/suspend.h
@@ -17,6 +17,7 @@ struct saved_context {
        u16 ds, es, fs, gs, ss;
        unsigned long gs_base, gs_kernel_base, fs_base;
        unsigned long cr0, cr2, cr3, cr4, cr8;
+        unsigned long efer;
        u16 gdt_pad;
        u16 gdt_limit;
        unsigned long gdt_base;
@@ -44,12 +45,12 @@ extern unsigned long saved_context_eflags;
 extern void fix_processor_context(void);
 #ifdef CONFIG_ACPI_SLEEP
-extern unsigned long saved_eip;
+extern unsigned long saved_rip;
-extern unsigned long saved_esp;
+extern unsigned long saved_rsp;
-extern unsigned long saved_ebp;
+extern unsigned long saved_rbp;
-extern unsigned long saved_ebx;
+extern unsigned long saved_rbx;
-extern unsigned long saved_esi;
+extern unsigned long saved_rsi;
-extern unsigned long saved_edi;
+extern unsigned long saved_rdi;
 /* routines for saving/restoring kernel state */
 extern int acpi_save_state_mem(void);
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index bd376bc8c4ab..213b7fe5d998 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -89,6 +89,11 @@ static inline unsigned long read_cr3(void)
        return cr3;
 } 
+static inline void write_cr3(unsigned long val)
+{
+        asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
+}
 static inline unsigned long read_cr4(void)
 { 
        unsigned long cr4;
@@ -98,7 +103,7 @@ static inline unsigned long read_cr4(void)
 static inline void write_cr4(unsigned long val)
 { 
-        asm volatile("movq %0,%%cr4" :: "r" (val));
+        asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
 } 
 #define stts() write_cr0(8 | read_cr0())
diff --git a/include/asm-x86_64/timex.h b/include/asm-x86_64/timex.h
index 8c6808a3fba4..f6527e1b6c1c 100644
--- a/include/asm-x86_64/timex.h
+++ b/include/asm-x86_64/timex.h
@@ -27,6 +27,6 @@ extern int read_current_timer(unsigned long *timer_value);
 #define NS_SCALE        10 /* 2^10, carefully chosen */
 #define US_SCALE        32 /* 2^32, arbitralrily chosen */
-extern void mark_tsc_unstable(void);
+extern void mark_tsc_unstable(char *msg);
 extern void set_cyc2ns_scale(unsigned long khz);
 #endif
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index 983bd296c81a..512401b8725f 100644
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -3,41 +3,18 @@
 #include <linux/mm.h>
 #include <asm/processor.h>
+#include <asm/system.h>
-static inline unsigned long get_cr3(void)
-{
-        unsigned long cr3;
-        asm volatile("mov %%cr3,%0" : "=r" (cr3));
-        return cr3;
-}
-static inline void set_cr3(unsigned long cr3)
-{
-        asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory");
-}
 static inline void __flush_tlb(void)
 {
-        set_cr3(get_cr3());
+        write_cr3(read_cr3());
-}
-static inline unsigned long get_cr4(void)
-{
-        unsigned long cr4;
-        asm volatile("mov %%cr4,%0" : "=r" (cr4));
-        return cr4;
-}
-static inline void set_cr4(unsigned long cr4)
-{
-        asm volatile("mov %0,%%cr4" :: "r" (cr4) : "memory");
 }
 static inline void __flush_tlb_all(void)
 {
-        unsigned long cr4 = get_cr4();
+        unsigned long cr4 = read_cr4();
-        set_cr4(cr4 & ~X86_CR4_PGE);    /* clear PGE */
+        write_cr4(cr4 & ~X86_CR4_PGE);  /* clear PGE */
-        set_cr4(cr4);                   /* write old PGE again and flush TLBs */
+        write_cr4(cr4);                 /* write old PGE again and flush TLBs */
 }
 #define __flush_tlb_one(addr) \
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index c5f596e71faa..26e23e01c54a 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -620,8 +620,6 @@ __SYSCALL(__NR_vmsplice, sys_vmsplice)
 #define __NR_move_pages         279
 __SYSCALL(__NR_move_pages, sys_move_pages)
-#define __NR_syscall_max __NR_move_pages
 #ifndef __NO_STUBS
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_OLD_STAT
@@ -655,7 +653,6 @@ __SYSCALL(__NR_move_pages, sys_move_pages)
 #include <asm/ptrace.h>
 asmlinkage long sys_iopl(unsigned int level, struct pt_regs *regs);
-asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-xtensa/mmu_context.h b/include/asm-xtensa/mmu_context.h
index f14851f086c3..92f948392ebc 100644
--- a/include/asm-xtensa/mmu_context.h
+++ b/include/asm-xtensa/mmu_context.h
@@ -18,6 +18,7 @@
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
+#include <asm-generic/mm_hooks.h>
 #define XCHAL_MMU_ASID_BITS     8
diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h
index 81c07cd18643..0365ec9fc0c9 100644
--- a/include/linux/bootmem.h
+++ b/include/linux/bootmem.h
@@ -122,9 +122,9 @@ extern void *alloc_large_system_hash(const char *tablename,
 #define HASH_EARLY      0x00000001      /* Allocating during early boot? */
 /* Only NUMA needs hash distribution.
- * IA64 is known to have sufficient vmalloc space.
+ * IA64 and x86_64 have sufficient vmalloc space.
 */
-#if defined(CONFIG_NUMA) && defined(CONFIG_IA64)
+#if defined(CONFIG_NUMA) && (defined(CONFIG_IA64) || defined(CONFIG_X86_64))
 #define HASHDIST_DEFAULT 1
 #else
 #define HASHDIST_DEFAULT 0
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 3ec6e7ff5fbd..963051a967d6 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -32,7 +32,15 @@
 *                     CPUFREQ NOTIFIER INTERFACE                    *
 *********************************************************************/
+#ifdef CONFIG_CPU_FREQ
 int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list);
+#else
+static inline int cpufreq_register_notifier(struct notifier_block *nb,
+                                                unsigned int list)
+{
+        return 0;
+}
+#endif
 int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list);
 #define CPUFREQ_TRANSITION_NOTIFIER     (0)
@@ -260,17 +268,22 @@ struct freq_attr {
 int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu);
 int cpufreq_update_policy(unsigned int cpu);
-/* query the current CPU frequency (in kHz). If zero, cpufreq couldn't detect it */
-unsigned int cpufreq_get(unsigned int cpu);
-/* query the last known CPU freq (in kHz). If zero, cpufreq couldn't detect it */
+/*
+ * query the last known CPU freq (in kHz). If zero, cpufreq couldn't detect it
+ */
 #ifdef CONFIG_CPU_FREQ
 unsigned int cpufreq_quick_get(unsigned int cpu);
+unsigned int cpufreq_get(unsigned int cpu);
 #else
 static inline unsigned int cpufreq_quick_get(unsigned int cpu)
 {
        return 0;
 }
+static inline unsigned int cpufreq_get(unsigned int cpu)
+{
+        return 0;
+}
 #endif
diff --git a/include/linux/crash_dump.h b/include/linux/crash_dump.h
index 32503657f14f..22c7ac5cd80c 100644
--- a/include/linux/crash_dump.h
+++ b/include/linux/crash_dump.h
@@ -14,5 +14,13 @@ extern ssize_t copy_oldmem_page(unsigned long, char *, size_t,
 extern const struct file_operations proc_vmcore_operations;
 extern struct proc_dir_entry *proc_vmcore;
+/* Architecture code defines this if there are other possible ELF
+ * machine types, e.g. on bi-arch capable hardware. */
+#ifndef vmcore_elf_check_arch_cross
+#define vmcore_elf_check_arch_cross(x) 0
+#endif
+#define vmcore_elf_check_arch(x) (elf_check_arch(x) || vmcore_elf_check_arch_cross(x))
 #endif /* CONFIG_CRASH_DUMP */
 #endif /* LINUX_CRASHDUMP_H */
diff --git a/include/linux/elf.h b/include/linux/elf.h
index 60713e6ea297..8b17ffe222c4 100644
--- a/include/linux/elf.h
+++ b/include/linux/elf.h
@@ -83,6 +83,23 @@ typedef __s64	Elf64_Sxword;
 #define DT_DEBUG        21
 #define DT_TEXTREL      22
 #define DT_JMPREL       23
+#define DT_ENCODING     32
+#define OLD_DT_LOOS     0x60000000
+#define DT_LOOS         0x6000000d
+#define DT_HIOS         0x6ffff000
+#define DT_VALRNGLO     0x6ffffd00
+#define DT_VALRNGHI     0x6ffffdff
+#define DT_ADDRRNGLO    0x6ffffe00
+#define DT_ADDRRNGHI    0x6ffffeff
+#define DT_VERSYM       0x6ffffff0
+#define DT_RELACOUNT    0x6ffffff9
+#define DT_RELCOUNT     0x6ffffffa
+#define DT_FLAGS_1      0x6ffffffb
+#define DT_VERDEF       0x6ffffffc
+#define DT_VERDEFNUM    0x6ffffffd
+#define DT_VERNEED      0x6ffffffe
+#define DT_VERNEEDNUM   0x6fffffff
+#define OLD_DT_HIOS     0x6fffffff
 #define DT_LOPROC       0x70000000
 #define DT_HIPROC       0x7fffffff
diff --git a/include/linux/elfnote.h b/include/linux/elfnote.h
index 67396db141e8..9a1e0674e56c 100644
--- a/include/linux/elfnote.h
+++ b/include/linux/elfnote.h
@@ -39,12 +39,12 @@
 *      ELFNOTE(XYZCo, 12, .long, 0xdeadbeef)
 */
 #define ELFNOTE(name, type, desctype, descdata) \
-.pushsection .note.name                 ;       \
+.pushsection .note.name, "",@note       ;       \
  .align 4                              ;       \
  .long 2f - 1f         /* namesz */    ;       \
  .long 4f - 3f         /* descsz */    ;       \
  .long type                            ;       \
-1:.asciz "name"                         ;       \
+1:.asciz #name                          ;       \
 2:.align 4                              ;       \
 3:desctype descdata                     ;       \
 4:.align 4                              ;       \
diff --git a/include/linux/highmem.h b/include/linux/highmem.h
index 7bab8eae2341..a515eb0afdfb 100644
--- a/include/linux/highmem.h
+++ b/include/linux/highmem.h
@@ -27,6 +27,8 @@ static inline void flush_kernel_dcache_page(struct page *page)
 unsigned int nr_free_highpages(void);
 extern unsigned long totalhigh_pages;
+void kmap_flush_unused(void);
 #else /* CONFIG_HIGHMEM */
 static inline unsigned int nr_free_highpages(void) { return 0; }
@@ -49,10 +51,13 @@ static inline void *kmap_atomic(struct page *page, enum km_type idx)
        pagefault_disable();
        return page_address(page);
 }
+#define kmap_atomic_prot(page, idx, prot)       kmap_atomic(page, idx)
 #define kunmap_atomic(addr, idx)        do { pagefault_enable(); } while (0)
 #define kmap_atomic_pfn(pfn, idx)       kmap_atomic(pfn_to_page(pfn), (idx))
 #define kmap_atomic_to_page(ptr)        virt_to_page(ptr)
+#define kmap_flush_unused()     do {} while(0)
 #endif
 #endif /* CONFIG_HIGHMEM */
diff --git a/include/linux/init.h b/include/linux/init.h
index e290a010e3f2..9abf120ec9f8 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -52,9 +52,14 @@
 #endif
 /* For assembly routines */
+#ifdef CONFIG_HOTPLUG_CPU
+#define __INIT          .section        ".text","ax"
+#define __INITDATA      .section        ".data","aw"
+#else
 #define __INIT          .section        ".init.text","ax"
-#define __FINIT         .previous
 #define __INITDATA      .section        ".init.data","aw"
+#endif
+#define __FINIT         .previous
 #ifndef __ASSEMBLY__
 /*
diff --git a/include/linux/percpu.h b/include/linux/percpu.h
index 600e3d387ffc..b72be2f79e6a 100644
--- a/include/linux/percpu.h
+++ b/include/linux/percpu.h
@@ -11,9 +11,16 @@
 /* Enough to cover all DEFINE_PER_CPUs in kernel, including modules. */
 #ifndef PERCPU_ENOUGH_ROOM
-#define PERCPU_ENOUGH_ROOM 32768
+#ifdef CONFIG_MODULES
+#define PERCPU_MODULE_RESERVE   8192
+#else
+#define PERCPU_MODULE_RESERVE   0
 #endif
+#define PERCPU_ENOUGH_ROOM                                              \
+        (__per_cpu_end - __per_cpu_start + PERCPU_MODULE_RESERVE)
+#endif  /* PERCPU_ENOUGH_ROOM */
 /*
 * Must be an lvalue. Since @var must be a simple identifier,
 * we force a syntax error here if it isn't.
diff --git a/include/linux/poison.h b/include/linux/poison.h
index 3e628f990fdf..89580b764959 100644
--- a/include/linux/poison.h
+++ b/include/linux/poison.h
@@ -26,9 +26,6 @@
 /********** arch/$ARCH/mm/init.c **********/
 #define POISON_FREE_INITMEM     0xcc
-/********** arch/x86_64/mm/init.c **********/
-#define POISON_FREE_INITDATA    0xba
 /********** arch/ia64/hp/common/sba_iommu.c **********/
 /*
 * arch/ia64/hp/common/sba_iommu.c uses a 16-byte poison string with a
author	Linus Torvalds <torvalds@woody.linux-foundation.org>	2007-05-05 17:55:20 -0400
committer	Linus Torvalds <torvalds@woody.linux-foundation.org>	2007-05-05 17:55:20 -0400
commit	ea62ccd00fd0b6720b033adfc9984f31130ce195 (patch)
tree	9837b797b2466fffcb0af96c388b06eae9c3df18 /include
parent	886a0768affe9a32f18c45f8e1393bca9ece5392 (diff)
parent	35060b6a9a4e1c89bc6fbea61090e302dbc61847 (diff)