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authorCatalin Marinas <catalin.marinas@arm.com>2007-02-05 08:48:24 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-15 10:08:54 -0500
commit7770bddb27ea84519486d8bb5d35d36d580c451b (patch)
treec2f08880317f4e4d102ec3e06e8e169ec62a89b0 /include
parent4ba9dcbeba042b7a1a1366f0dc683a2947ca5577 (diff)
[ARM] 4130/1: Add L220 support to RealView/EB
This patch enables the L220 on the RealView/EB MPCore platform. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-realview/platform.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 87acd9c191e6..6e0eab95a3a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -213,6 +213,7 @@
213#define REALVIEW_TWD_BASE 0x10100700 213#define REALVIEW_TWD_BASE 0x10100700
214#define REALVIEW_TWD_SIZE 0x00000100 214#define REALVIEW_TWD_SIZE 0x00000100
215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ 215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
216#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ 217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
217#else 218#else
218#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */ 219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
@@ -220,6 +221,7 @@
220#define REALVIEW_TWD_BASE 0x1F000700 221#define REALVIEW_TWD_BASE 0x1F000700
221#define REALVIEW_TWD_SIZE 0x00000100 222#define REALVIEW_TWD_SIZE 0x00000100
222#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ 223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
223#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ 225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
224#endif 226#endif
225#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */