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authorBruce Losure <blosure@americas.sgi.com>2005-09-02 16:16:35 -0400
committerTony Luck <tony.luck@intel.com>2005-09-06 17:16:01 -0400
commit25732ad493b22b7d9f0d250c5a9ad17219f96a47 (patch)
tree6d2c753c248977fdca4b5d423b65d7fbf2f70186 /include
parent4706df3d3c42af802597d82c8b1542c3d52eab23 (diff)
[IA64] Altix patch for fpga reset
1) workaround a h/w reset issue 2) to improve the determination of FPGA-based h/w in the arch/ia64/sn/kernel/tiocx code. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ia64/sn/l1.h12
-rw-r--r--include/asm-ia64/sn/sn_sal.h43
-rw-r--r--include/asm-ia64/sn/tiocx.h3
3 files changed, 57 insertions, 1 deletions
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 2e5f0aa38889..e3b819110d47 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -35,4 +35,16 @@
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */ 35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */ 36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
37 37
38/* board type response codes */
39#define L1_BOARDTYPE_IP69 0x0100 /* CA */
40#define L1_BOARDTYPE_IP63 0x0200 /* CB */
41#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
42#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
43#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
44#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
45#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
46#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
47#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
48
49
38#endif /* _ASM_IA64_SN_L1_H */ 50#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index e67825ad1930..6f96ae8b4fbe 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -47,6 +47,7 @@
47#define SN_SAL_CONSOLE_PUTB 0x02000028 47#define SN_SAL_CONSOLE_PUTB 0x02000028
48#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a 48#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a
49#define SN_SAL_CONSOLE_READC 0x0200002b 49#define SN_SAL_CONSOLE_READC 0x0200002b
50#define SN_SAL_SYSCTL_OP 0x02000030
50#define SN_SAL_SYSCTL_MODID_GET 0x02000031 51#define SN_SAL_SYSCTL_MODID_GET 0x02000031
51#define SN_SAL_SYSCTL_GET 0x02000032 52#define SN_SAL_SYSCTL_GET 0x02000032
52#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033 53#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033
@@ -98,6 +99,13 @@
98#define SAL_INTR_FREE 2 99#define SAL_INTR_FREE 2
99 100
100/* 101/*
102 * operations available on the generic SN_SAL_SYSCTL_OP
103 * runtime service
104 */
105#define SAL_SYSCTL_OP_IOBOARD 0x0001 /* retrieve board type */
106#define SAL_SYSCTL_OP_TIO_JLCK_RST 0x0002 /* issue TIO clock reset */
107
108/*
101 * IRouter (i.e. generalized system controller) operations 109 * IRouter (i.e. generalized system controller) operations
102 */ 110 */
103#define SAL_IROUTER_OPEN 0 /* open a subchannel */ 111#define SAL_IROUTER_OPEN 0 /* open a subchannel */
@@ -876,6 +884,41 @@ ia64_sn_sysctl_event_init(nasid_t nasid)
876 return (int) rv.v0; 884 return (int) rv.v0;
877} 885}
878 886
887/*
888 * Ask the system controller on the specified nasid to reset
889 * the CX corelet clock. Only valid on TIO nodes.
890 */
891static inline int
892ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
893{
894 struct ia64_sal_retval rv;
895 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
896 nasid, 0, 0, 0, 0, 0);
897 if (rv.status != 0)
898 return (int)rv.status;
899 if (rv.v0 != 0)
900 return (int)rv.v0;
901
902 return 0;
903}
904
905/*
906 * Get the associated ioboard type for a given nasid.
907 */
908static inline int
909ia64_sn_sysctl_ioboard_get(nasid_t nasid)
910{
911 struct ia64_sal_retval rv;
912 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
913 nasid, 0, 0, 0, 0, 0);
914 if (rv.v0 != 0)
915 return (int)rv.v0;
916 if (rv.v1 != 0)
917 return (int)rv.v1;
918
919 return 0;
920}
921
879/** 922/**
880 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header 923 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
881 * @nasid: NASID of node to read 924 * @nasid: NASID of node to read
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
index c5447a504509..5699e75e5024 100644
--- a/include/asm-ia64/sn/tiocx.h
+++ b/include/asm-ia64/sn/tiocx.h
@@ -19,6 +19,7 @@ struct cx_id_s {
19 19
20struct cx_dev { 20struct cx_dev {
21 struct cx_id_s cx_id; 21 struct cx_id_s cx_id;
22 int bt; /* board/blade type */
22 void *soft; /* driver specific */ 23 void *soft; /* driver specific */
23 struct hubdev_info *hubdev; 24 struct hubdev_info *hubdev;
24 struct device dev; 25 struct device dev;
@@ -59,7 +60,7 @@ struct cx_drv {
59extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int); 60extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
60extern void tiocx_irq_free(struct sn_irq_info *); 61extern void tiocx_irq_free(struct sn_irq_info *);
61extern int cx_device_unregister(struct cx_dev *); 62extern int cx_device_unregister(struct cx_dev *);
62extern int cx_device_register(nasid_t, int, int, struct hubdev_info *); 63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
63extern int cx_driver_unregister(struct cx_drv *); 64extern int cx_driver_unregister(struct cx_drv *);
64extern int cx_driver_register(struct cx_drv *); 65extern int cx_driver_register(struct cx_drv *);
65extern uint64_t tiocx_dma_addr(uint64_t addr); 66extern uint64_t tiocx_dma_addr(uint64_t addr);