diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-12 21:11:33 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-12 21:11:33 -0400 |
commit | f7d02ae76ebbf5b8a9531fe150c49e126a397704 (patch) | |
tree | bcfdcab6e70658d55a3c843694e04e938bf9168f /include | |
parent | 78db2ad6f4df9145bfd6aab1c0f1c56d615288ec (diff) | |
parent | 158304ef09a28c7f2dd37d78f536a4e09ba084a1 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (30 commits)
[ARM] Use new get_irqnr_preamble
[ARM] Ensure machine class menu is sorted alphabetically
[ARM] 4333/2: KS8695: Micrel Development board
[ARM] 4332/2: KS8695: Serial driver
[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
[ARM] 4371/1: AT91: Support for Atmel AT91SAM9RL-EK development board
[ARM] 4372/1: Define byte sizes in asm-arm/sizes.h
[ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
[ARM] Update mach-types
[ARM] export symbol csum_partial_copy_from_user
[ARM] iop13xx: msi support
[ARM] stacktrace fix
[ARM] Spinlock initializer cleanup
[ARM] remove useless config option GENERIC_BUST_SPINLOCK
[ARM] 4303/3: base kernel support for TI DaVinci
[ARM] 4369/1: AT91: Fix circular dependency in header files
[ARM] 4368/1: S3C24xx: build fix
[ARM] 4364/1: AT91: LEDS on AT91SAM9261-EK
[ARM] Fix iop32x/iop33x build
[ARM] EBSA110: fix build errors caused by missing "const"
...
Diffstat (limited to 'include')
66 files changed, 2078 insertions, 56 deletions
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h new file mode 100644 index 000000000000..8a9708a370c6 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91/at91sam9260.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Atmel Corporation | ||
5 | * | ||
6 | * Common definitions. | ||
7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) | ||
8 | * | ||
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file COPYING in the main directory of this archive for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef AT91SAM9RL_H | ||
15 | #define AT91SAM9RL_H | ||
16 | |||
17 | /* | ||
18 | * Peripheral identifiers/interrupts. | ||
19 | */ | ||
20 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
21 | #define AT91_ID_SYS 1 /* System Controller */ | ||
22 | #define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ | ||
23 | #define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ | ||
24 | #define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ | ||
25 | #define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ | ||
26 | #define AT91SAM9RL_ID_US0 6 /* USART 0 */ | ||
27 | #define AT91SAM9RL_ID_US1 7 /* USART 1 */ | ||
28 | #define AT91SAM9RL_ID_US2 8 /* USART 2 */ | ||
29 | #define AT91SAM9RL_ID_US3 9 /* USART 3 */ | ||
30 | #define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ | ||
31 | #define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ | ||
32 | #define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ | ||
33 | #define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ | ||
34 | #define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
35 | #define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
36 | #define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ | ||
37 | #define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ | ||
38 | #define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ | ||
39 | #define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ | ||
40 | #define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ | ||
41 | #define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ | ||
42 | #define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ | ||
43 | #define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ | ||
44 | #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ | ||
45 | #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ | ||
46 | |||
47 | |||
48 | /* | ||
49 | * User Peripheral physical base addresses. | ||
50 | */ | ||
51 | #define AT91SAM9RL_BASE_TCB0 0xfffa0000 | ||
52 | #define AT91SAM9RL_BASE_TC0 0xfffa0000 | ||
53 | #define AT91SAM9RL_BASE_TC1 0xfffa0040 | ||
54 | #define AT91SAM9RL_BASE_TC2 0xfffa0080 | ||
55 | #define AT91SAM9RL_BASE_MCI 0xfffa4000 | ||
56 | #define AT91SAM9RL_BASE_TWI0 0xfffa8000 | ||
57 | #define AT91SAM9RL_BASE_TWI1 0xfffac000 | ||
58 | #define AT91SAM9RL_BASE_US0 0xfffb0000 | ||
59 | #define AT91SAM9RL_BASE_US1 0xfffb4000 | ||
60 | #define AT91SAM9RL_BASE_US2 0xfffb8000 | ||
61 | #define AT91SAM9RL_BASE_US3 0xfffbc000 | ||
62 | #define AT91SAM9RL_BASE_SSC0 0xfffc0000 | ||
63 | #define AT91SAM9RL_BASE_SSC1 0xfffc4000 | ||
64 | #define AT91SAM9RL_BASE_PWMC 0xfffc8000 | ||
65 | #define AT91SAM9RL_BASE_SPI 0xfffcc000 | ||
66 | #define AT91SAM9RL_BASE_TSC 0xfffd0000 | ||
67 | #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 | ||
68 | #define AT91SAM9RL_BASE_AC97C 0xfffd8000 | ||
69 | #define AT91_BASE_SYS 0xffffc000 | ||
70 | |||
71 | |||
72 | /* | ||
73 | * System Peripherals (offset from AT91_BASE_SYS) | ||
74 | */ | ||
75 | #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) | ||
76 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
77 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
78 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
79 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
80 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
81 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
82 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
83 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
84 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
85 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
86 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) | ||
87 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
88 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
89 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
90 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
91 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
92 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
93 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | ||
94 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
95 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) | ||
96 | |||
97 | |||
98 | /* | ||
99 | * Internal Memory. | ||
100 | */ | ||
101 | #define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
102 | #define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ | ||
103 | |||
104 | #define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
105 | #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ | ||
106 | |||
107 | #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
108 | #define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ | ||
109 | |||
110 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h new file mode 100644 index 000000000000..b15f11b7c08d --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h | |||
@@ -0,0 +1,96 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91/at91sam9rl_matrix.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Atmel Corporation | ||
5 | * | ||
6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) | ||
8 | * | ||
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file COPYING in the main directory of this archive for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef AT91SAM9RL_MATRIX_H | ||
15 | #define AT91SAM9RL_MATRIX_H | ||
16 | |||
17 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
18 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
19 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
20 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
21 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
22 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
23 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
24 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
25 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
26 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
27 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
28 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
29 | |||
30 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
31 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
32 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
33 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
34 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
35 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
36 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
37 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
38 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
39 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
40 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
41 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
42 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
43 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
44 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
45 | |||
46 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
47 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
48 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
49 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
50 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
51 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
52 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
53 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
54 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
55 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
56 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
57 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
58 | |||
59 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
60 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
61 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
62 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
63 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
64 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
65 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
66 | |||
67 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | ||
68 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
69 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
70 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
71 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
72 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
73 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
74 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
75 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
76 | |||
77 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | ||
78 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
79 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
80 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
81 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
82 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
83 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
84 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
85 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
86 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
87 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
88 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
89 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
90 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
91 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
92 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
93 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
94 | |||
95 | |||
96 | #endif | ||
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index 7ef4eebe9f8e..ef93c30a9c5f 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h | |||
@@ -26,6 +26,8 @@ | |||
26 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | 26 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 |
27 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 | 27 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 |
28 | 28 | ||
29 | #define ARCH_ID_AT91SAM9RL64 0x019b03a0 | ||
30 | |||
29 | static inline unsigned long at91_cpu_identify(void) | 31 | static inline unsigned long at91_cpu_identify(void) |
30 | { | 32 | { |
31 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | 33 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); |
@@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void) | |||
68 | #define cpu_is_at91sam9263() (0) | 70 | #define cpu_is_at91sam9263() (0) |
69 | #endif | 71 | #endif |
70 | 72 | ||
73 | #ifdef CONFIG_ARCH_AT91SAM9RL | ||
74 | #define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) | ||
75 | #else | ||
76 | #define cpu_is_at91sam9rl() (0) | ||
77 | #endif | ||
78 | |||
79 | |||
71 | /* | 80 | /* |
72 | * Since this is ARM, we will never run on any AVR32 CPU. But these | 81 | * Since this is ARM, we will never run on any AVR32 CPU. But these |
73 | * definitions may reduce clutter in common drivers. | 82 | * definitions may reduce clutter in common drivers. |
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154dd..46835e945aea 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h | |||
@@ -24,6 +24,8 @@ | |||
24 | #include <asm/arch/at91sam9261.h> | 24 | #include <asm/arch/at91sam9261.h> |
25 | #elif defined(CONFIG_ARCH_AT91SAM9263) | 25 | #elif defined(CONFIG_ARCH_AT91SAM9263) |
26 | #include <asm/arch/at91sam9263.h> | 26 | #include <asm/arch/at91sam9263.h> |
27 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
28 | #include <asm/arch/at91sam9rl.h> | ||
27 | #else | 29 | #else |
28 | #error "Unsupported AT91 processor" | 30 | #error "Unsupported AT91 processor" |
29 | #endif | 31 | #endif |
@@ -69,22 +71,5 @@ | |||
69 | /* Clocks */ | 71 | /* Clocks */ |
70 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | 72 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ |
71 | 73 | ||
72 | #ifndef __ASSEMBLY__ | ||
73 | #include <asm/io.h> | ||
74 | |||
75 | static inline unsigned int at91_sys_read(unsigned int reg_offset) | ||
76 | { | ||
77 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
78 | |||
79 | return __raw_readl(addr + reg_offset); | ||
80 | } | ||
81 | |||
82 | static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) | ||
83 | { | ||
84 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
85 | |||
86 | __raw_writel(value, addr + reg_offset); | ||
87 | } | ||
88 | #endif | ||
89 | 74 | ||
90 | #endif | 75 | #endif |
diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 401f327ec047..80073fd36b8e 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h | |||
@@ -29,4 +29,22 @@ | |||
29 | #define __mem_pci(a) (a) | 29 | #define __mem_pci(a) (a) |
30 | 30 | ||
31 | 31 | ||
32 | #ifndef __ASSEMBLY__ | ||
33 | |||
34 | static inline unsigned int at91_sys_read(unsigned int reg_offset) | ||
35 | { | ||
36 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
37 | |||
38 | return __raw_readl(addr + reg_offset); | ||
39 | } | ||
40 | |||
41 | static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) | ||
42 | { | ||
43 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
44 | |||
45 | __raw_writel(value, addr + reg_offset); | ||
46 | } | ||
47 | |||
48 | #endif | ||
49 | |||
32 | #endif | 50 | #endif |
diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1ffa3bb9a9c1..1127a3b5e928 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h | |||
@@ -21,6 +21,7 @@ | |||
21 | #ifndef __ASM_ARCH_IRQS_H | 21 | #ifndef __ASM_ARCH_IRQS_H |
22 | #define __ASM_ARCH_IRQS_H | 22 | #define __ASM_ARCH_IRQS_H |
23 | 23 | ||
24 | #include <asm/io.h> | ||
24 | #include <asm/arch/at91_aic.h> | 25 | #include <asm/arch/at91_aic.h> |
25 | 26 | ||
26 | #define NR_AIC_IRQS 32 | 27 | #define NR_AIC_IRQS 32 |
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index f41636d607a2..2df1ee12dfb7 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h | |||
@@ -37,6 +37,11 @@ | |||
37 | #define AT91SAM9_MASTER_CLOCK 99959500 | 37 | #define AT91SAM9_MASTER_CLOCK 99959500 |
38 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | 38 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) |
39 | 39 | ||
40 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
41 | |||
42 | #define AT91SAM9_MASTER_CLOCK 100000000 | ||
43 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
44 | |||
40 | #endif | 45 | #endif |
41 | 46 | ||
42 | #endif | 47 | #endif |
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index a193d28304b6..30ac587b3b41 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h | |||
@@ -21,7 +21,7 @@ | |||
21 | #ifndef __ASM_ARCH_UNCOMPRESS_H | 21 | #ifndef __ASM_ARCH_UNCOMPRESS_H |
22 | #define __ASM_ARCH_UNCOMPRESS_H | 22 | #define __ASM_ARCH_UNCOMPRESS_H |
23 | 23 | ||
24 | #include <asm/hardware.h> | 24 | #include <asm/io.h> |
25 | #include <asm/arch/at91_dbgu.h> | 25 | #include <asm/arch/at91_dbgu.h> |
26 | 26 | ||
27 | /* | 27 | /* |
diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S index 0cfb89b229d1..038b761fdadc 100644 --- a/include/asm-arm/arch-cl7500/entry-macro.S +++ b/include/asm-arm/arch-cl7500/entry-macro.S | |||
@@ -1,6 +1,14 @@ | |||
1 | #include <asm/hardware.h> | 1 | #include <asm/hardware.h> |
2 | #include <asm/hardware/entry-macro-iomd.S> | 2 | #include <asm/hardware/entry-macro-iomd.S> |
3 | |||
4 | .equ ioc_base_high, IOC_BASE & 0xff000000 | ||
5 | .equ ioc_base_low, IOC_BASE & 0x00ff0000 | ||
6 | |||
3 | .macro get_irqnr_preamble, base, tmp | 7 | .macro get_irqnr_preamble, base, tmp |
8 | mov \base, #ioc_base_high @ point at IOC | ||
9 | .if ioc_base_low | ||
10 | orr \base, \base, #ioc_base_low | ||
11 | .endif | ||
4 | .endm | 12 | .endm |
5 | 13 | ||
6 | .macro arch_ret_to_user, tmp1, tmp2 | 14 | .macro arch_ret_to_user, tmp1, tmp2 |
diff --git a/include/asm-arm/arch-davinci/common.h b/include/asm-arm/arch-davinci/common.h new file mode 100644 index 000000000000..a97dfbb15e57 --- /dev/null +++ b/include/asm-arm/arch-davinci/common.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * Header for code common to all DaVinci machines. | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H | ||
13 | #define __ARCH_ARM_MACH_DAVINCI_COMMON_H | ||
14 | |||
15 | struct sys_timer; | ||
16 | |||
17 | extern struct sys_timer davinci_timer; | ||
18 | |||
19 | #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ | ||
diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/include/asm-arm/arch-davinci/debug-macro.S new file mode 100644 index 000000000000..e6c0f0d5d062 --- /dev/null +++ b/include/asm-arm/arch-davinci/debug-macro.S | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Debugging macro for DaVinci | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | .macro addruart, rx | ||
13 | mrc p15, 0, \rx, c1, c0 | ||
14 | tst \rx, #1 @ MMU enabled? | ||
15 | moveq \rx, #0x01000000 @ physical base address | ||
16 | movne \rx, #0xfe000000 @ virtual base | ||
17 | orr \rx, \rx, #0x00c20000 @ UART 0 | ||
18 | .endm | ||
19 | |||
20 | #define UART_SHIFT 2 | ||
21 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-davinci/dma.h b/include/asm-arm/arch-davinci/dma.h new file mode 100644 index 000000000000..8e2f2d0ba667 --- /dev/null +++ b/include/asm-arm/arch-davinci/dma.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * DaVinci DMA definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_DMA_H | ||
12 | #define __ASM_ARCH_DMA_H | ||
13 | |||
14 | #define MAX_DMA_ADDRESS 0xffffffff | ||
15 | |||
16 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S new file mode 100644 index 000000000000..3ebfcc5cb58e --- /dev/null +++ b/include/asm-arm/arch-davinci/entry-macro.S | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * Low-level IRQ helper macros for TI DaVinci-based platforms | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #include <asm/arch/io.h> | ||
12 | #include <asm/arch/irqs.h> | ||
13 | |||
14 | .macro disable_fiq | ||
15 | .endm | ||
16 | |||
17 | .macro get_irqnr_preamble, base, tmp | ||
18 | ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) | ||
19 | .endm | ||
20 | |||
21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
22 | .endm | ||
23 | |||
24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
25 | ldr \tmp, [\base, #0x14] | ||
26 | mov \tmp, \tmp, lsr #2 | ||
27 | sub \irqnr, \tmp, #1 | ||
28 | cmp \tmp, #0 | ||
29 | .endm | ||
30 | |||
31 | .macro irq_prio_table | ||
32 | .endm | ||
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 000000000000..60362d80229e --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h | |||
@@ -0,0 +1,14 @@ | |||
1 | /* | ||
2 | * Common hardware definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
12 | #define __ASM_ARCH_HARDWARE_H | ||
13 | |||
14 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h new file mode 100644 index 000000000000..e7accb910864 --- /dev/null +++ b/include/asm-arm/arch-davinci/io.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * DaVinci IO address definitions | ||
3 | * | ||
4 | * Copied from include/asm/arm/arch-omap/io.h | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_IO_H | ||
12 | #define __ASM_ARCH_IO_H | ||
13 | |||
14 | #define IO_SPACE_LIMIT 0xffffffff | ||
15 | |||
16 | /* | ||
17 | * ---------------------------------------------------------------------------- | ||
18 | * I/O mapping | ||
19 | * ---------------------------------------------------------------------------- | ||
20 | */ | ||
21 | #define IO_PHYS 0x01c00000 | ||
22 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ | ||
23 | #define IO_SIZE 0x00400000 | ||
24 | #define IO_VIRT (IO_PHYS + IO_OFFSET) | ||
25 | #define io_p2v(pa) ((pa) + IO_OFFSET) | ||
26 | #define io_v2p(va) ((va) - IO_OFFSET) | ||
27 | #define IO_ADDRESS(x) io_p2v(x) | ||
28 | |||
29 | /* | ||
30 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
31 | * drivers out there that might just work if we fake them... | ||
32 | */ | ||
33 | #define PCIO_BASE 0 | ||
34 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | ||
35 | #define __mem_pci(a) (a) | ||
36 | #define __mem_isa(a) (a) | ||
37 | |||
38 | #ifndef __ASSEMBLER__ | ||
39 | |||
40 | /* | ||
41 | * Functions to access the DaVinci IO region | ||
42 | * | ||
43 | * NOTE: - Use davinci_read/write[bwl] for physical register addresses | ||
44 | * - Use __raw_read/write[bwl]() for virtual register addresses | ||
45 | * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses | ||
46 | * - DO NOT use hardcoded virtual addresses to allow changing the | ||
47 | * IO address space again if needed | ||
48 | */ | ||
49 | #define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) | ||
50 | #define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) | ||
51 | #define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) | ||
52 | |||
53 | #define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) | ||
54 | #define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) | ||
55 | #define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) | ||
56 | |||
57 | /* 16 bit uses LDRH/STRH, base +/- offset_8 */ | ||
58 | typedef struct { volatile u16 offset[256]; } __regbase16; | ||
59 | #define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ | ||
60 | ->offset[((vaddr)&0xff)>>1] | ||
61 | #define __REG16(paddr) __REGV16(io_p2v(paddr)) | ||
62 | |||
63 | /* 8/32 bit uses LDR/STR, base +/- offset_12 */ | ||
64 | typedef struct { volatile u8 offset[4096]; } __regbase8; | ||
65 | #define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ | ||
66 | ->offset[((vaddr)&4095)>>0] | ||
67 | #define __REG8(paddr) __REGV8(io_p2v(paddr)) | ||
68 | |||
69 | typedef struct { volatile u32 offset[4096]; } __regbase32; | ||
70 | #define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ | ||
71 | ->offset[((vaddr)&4095)>>2] | ||
72 | |||
73 | #define __REG(paddr) __REGV32(io_p2v(paddr)) | ||
74 | #else | ||
75 | |||
76 | #define __REG(x) (*((volatile unsigned long *)io_p2v(x))) | ||
77 | |||
78 | #endif /* __ASSEMBLER__ */ | ||
79 | #endif /* __ASM_ARCH_IO_H */ | ||
diff --git a/include/asm-arm/arch-davinci/irqs.h b/include/asm-arm/arch-davinci/irqs.h new file mode 100644 index 000000000000..f4c5ca6da9f4 --- /dev/null +++ b/include/asm-arm/arch-davinci/irqs.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /* | ||
2 | * DaVinci interrupt controller definitions | ||
3 | * | ||
4 | * Copyright (C) 2006 Texas Instruments. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License along | ||
23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
25 | * | ||
26 | */ | ||
27 | #ifndef __ASM_ARCH_IRQS_H | ||
28 | #define __ASM_ARCH_IRQS_H | ||
29 | |||
30 | /* Base address */ | ||
31 | #define DAVINCI_ARM_INTC_BASE 0x01C48000 | ||
32 | |||
33 | /* Interrupt lines */ | ||
34 | #define IRQ_VDINT0 0 | ||
35 | #define IRQ_VDINT1 1 | ||
36 | #define IRQ_VDINT2 2 | ||
37 | #define IRQ_HISTINT 3 | ||
38 | #define IRQ_H3AINT 4 | ||
39 | #define IRQ_PRVUINT 5 | ||
40 | #define IRQ_RSZINT 6 | ||
41 | #define IRQ_VFOCINT 7 | ||
42 | #define IRQ_VENCINT 8 | ||
43 | #define IRQ_ASQINT 9 | ||
44 | #define IRQ_IMXINT 10 | ||
45 | #define IRQ_VLCDINT 11 | ||
46 | #define IRQ_USBINT 12 | ||
47 | #define IRQ_EMACINT 13 | ||
48 | |||
49 | #define IRQ_CCINT0 16 | ||
50 | #define IRQ_CCERRINT 17 | ||
51 | #define IRQ_TCERRINT0 18 | ||
52 | #define IRQ_TCERRINT 19 | ||
53 | #define IRQ_PSCIN 20 | ||
54 | |||
55 | #define IRQ_IDE 22 | ||
56 | #define IRQ_HPIINT 23 | ||
57 | #define IRQ_MBXINT 24 | ||
58 | #define IRQ_MBRINT 25 | ||
59 | #define IRQ_MMCINT 26 | ||
60 | #define IRQ_SDIOINT 27 | ||
61 | #define IRQ_MSINT 28 | ||
62 | #define IRQ_DDRINT 29 | ||
63 | #define IRQ_AEMIFINT 30 | ||
64 | #define IRQ_VLQINT 31 | ||
65 | #define IRQ_TINT0_TINT12 32 | ||
66 | #define IRQ_TINT0_TINT34 33 | ||
67 | #define IRQ_TINT1_TINT12 34 | ||
68 | #define IRQ_TINT1_TINT34 35 | ||
69 | #define IRQ_PWMINT0 36 | ||
70 | #define IRQ_PWMINT1 37 | ||
71 | #define IRQ_PWMINT2 38 | ||
72 | #define IRQ_I2C 39 | ||
73 | #define IRQ_UARTINT0 40 | ||
74 | #define IRQ_UARTINT1 41 | ||
75 | #define IRQ_UARTINT2 42 | ||
76 | #define IRQ_SPINT0 43 | ||
77 | #define IRQ_SPINT1 44 | ||
78 | |||
79 | #define IRQ_DSP2ARM0 46 | ||
80 | #define IRQ_DSP2ARM1 47 | ||
81 | #define IRQ_GPIO0 48 | ||
82 | #define IRQ_GPIO1 49 | ||
83 | #define IRQ_GPIO2 50 | ||
84 | #define IRQ_GPIO3 51 | ||
85 | #define IRQ_GPIO4 52 | ||
86 | #define IRQ_GPIO5 53 | ||
87 | #define IRQ_GPIO6 54 | ||
88 | #define IRQ_GPIO7 55 | ||
89 | #define IRQ_GPIOBNK0 56 | ||
90 | #define IRQ_GPIOBNK1 57 | ||
91 | #define IRQ_GPIOBNK2 58 | ||
92 | #define IRQ_GPIOBNK3 59 | ||
93 | #define IRQ_GPIOBNK4 60 | ||
94 | #define IRQ_COMMTX 61 | ||
95 | #define IRQ_COMMRX 62 | ||
96 | #define IRQ_EMUINT 63 | ||
97 | |||
98 | #define DAVINCI_N_AINTC_IRQ 64 | ||
99 | #define DAVINCI_N_GPIO 71 | ||
100 | |||
101 | #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) | ||
102 | |||
103 | #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 | ||
104 | |||
105 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/include/asm-arm/arch-davinci/memory.h b/include/asm-arm/arch-davinci/memory.h new file mode 100644 index 000000000000..dd1625c23cf4 --- /dev/null +++ b/include/asm-arm/arch-davinci/memory.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * DaVinci memory space definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_MEMORY_H | ||
12 | #define __ASM_ARCH_MEMORY_H | ||
13 | |||
14 | /************************************************************************** | ||
15 | * Included Files | ||
16 | **************************************************************************/ | ||
17 | #include <asm/page.h> | ||
18 | #include <asm/sizes.h> | ||
19 | |||
20 | /************************************************************************** | ||
21 | * Definitions | ||
22 | **************************************************************************/ | ||
23 | #define DAVINCI_DDR_BASE 0x80000000 | ||
24 | #define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ | ||
25 | |||
26 | #define PHYS_OFFSET DAVINCI_DDR_BASE | ||
27 | |||
28 | /* | ||
29 | * Increase size of DMA-consistent memory region | ||
30 | */ | ||
31 | #define CONSISTENT_DMA_SIZE (14<<20) | ||
32 | |||
33 | #ifndef __ASSEMBLY__ | ||
34 | /* | ||
35 | * Restrict DMA-able region to workaround silicon bug. The bug | ||
36 | * restricts buffers available for DMA to video hardware to be | ||
37 | * below 128M | ||
38 | */ | ||
39 | static inline void | ||
40 | __arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) | ||
41 | { | ||
42 | unsigned int sz = (128<<20) >> PAGE_SHIFT; | ||
43 | |||
44 | if (node != 0) | ||
45 | sz = 0; | ||
46 | |||
47 | size[1] = size[0] - sz; | ||
48 | size[0] = sz; | ||
49 | } | ||
50 | |||
51 | #define arch_adjust_zones(node, zone_size, holes) \ | ||
52 | if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) | ||
53 | |||
54 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) | ||
55 | |||
56 | #endif | ||
57 | |||
58 | /* | ||
59 | * Bus address is physical address | ||
60 | */ | ||
61 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
62 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
63 | |||
64 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/include/asm-arm/arch-davinci/psc.h b/include/asm-arm/arch-davinci/psc.h new file mode 100644 index 000000000000..4977aa071e1e --- /dev/null +++ b/include/asm-arm/arch-davinci/psc.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* | ||
2 | * DaVinci Power & Sleep Controller (PSC) defines | ||
3 | * | ||
4 | * Copyright (C) 2006 Texas Instruments. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License along | ||
23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
25 | * | ||
26 | */ | ||
27 | #ifndef __ASM_ARCH_PSC_H | ||
28 | #define __ASM_ARCH_PSC_H | ||
29 | |||
30 | /* Power and Sleep Controller (PSC) Domains */ | ||
31 | #define DAVINCI_GPSC_ARMDOMAIN 0 | ||
32 | #define DAVINCI_GPSC_DSPDOMAIN 1 | ||
33 | |||
34 | #define DAVINCI_LPSC_VPSSMSTR 0 | ||
35 | #define DAVINCI_LPSC_VPSSSLV 1 | ||
36 | #define DAVINCI_LPSC_TPCC 2 | ||
37 | #define DAVINCI_LPSC_TPTC0 3 | ||
38 | #define DAVINCI_LPSC_TPTC1 4 | ||
39 | #define DAVINCI_LPSC_EMAC 5 | ||
40 | #define DAVINCI_LPSC_EMAC_WRAPPER 6 | ||
41 | #define DAVINCI_LPSC_MDIO 7 | ||
42 | #define DAVINCI_LPSC_IEEE1394 8 | ||
43 | #define DAVINCI_LPSC_USB 9 | ||
44 | #define DAVINCI_LPSC_ATA 10 | ||
45 | #define DAVINCI_LPSC_VLYNQ 11 | ||
46 | #define DAVINCI_LPSC_UHPI 12 | ||
47 | #define DAVINCI_LPSC_DDR_EMIF 13 | ||
48 | #define DAVINCI_LPSC_AEMIF 14 | ||
49 | #define DAVINCI_LPSC_MMC_SD 15 | ||
50 | #define DAVINCI_LPSC_MEMSTICK 16 | ||
51 | #define DAVINCI_LPSC_McBSP 17 | ||
52 | #define DAVINCI_LPSC_I2C 18 | ||
53 | #define DAVINCI_LPSC_UART0 19 | ||
54 | #define DAVINCI_LPSC_UART1 20 | ||
55 | #define DAVINCI_LPSC_UART2 21 | ||
56 | #define DAVINCI_LPSC_SPI 22 | ||
57 | #define DAVINCI_LPSC_PWM0 23 | ||
58 | #define DAVINCI_LPSC_PWM1 24 | ||
59 | #define DAVINCI_LPSC_PWM2 25 | ||
60 | #define DAVINCI_LPSC_GPIO 26 | ||
61 | #define DAVINCI_LPSC_TIMER0 27 | ||
62 | #define DAVINCI_LPSC_TIMER1 28 | ||
63 | #define DAVINCI_LPSC_TIMER2 29 | ||
64 | #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 | ||
65 | #define DAVINCI_LPSC_ARM 31 | ||
66 | #define DAVINCI_LPSC_SCR2 32 | ||
67 | #define DAVINCI_LPSC_SCR3 33 | ||
68 | #define DAVINCI_LPSC_SCR4 34 | ||
69 | #define DAVINCI_LPSC_CROSSBAR 35 | ||
70 | #define DAVINCI_LPSC_CFG27 36 | ||
71 | #define DAVINCI_LPSC_CFG3 37 | ||
72 | #define DAVINCI_LPSC_CFG5 38 | ||
73 | #define DAVINCI_LPSC_GEM 39 | ||
74 | #define DAVINCI_LPSC_IMCOP 40 | ||
75 | |||
76 | #endif /* __ASM_ARCH_PSC_H */ | ||
diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h new file mode 100644 index 000000000000..ed418ef76805 --- /dev/null +++ b/include/asm-arm/arch-davinci/serial.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * DaVinci serial device definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_SERIAL_H | ||
12 | #define __ASM_ARCH_SERIAL_H | ||
13 | |||
14 | #include <asm/arch/io.h> | ||
15 | |||
16 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) | ||
17 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) | ||
18 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) | ||
19 | |||
20 | #endif /* __ASM_ARCH_SERIAL_H */ | ||
diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h new file mode 100644 index 000000000000..440ac515804b --- /dev/null +++ b/include/asm-arm/arch-davinci/system.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * DaVinci system defines | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
12 | #define __ASM_ARCH_SYSTEM_H | ||
13 | |||
14 | #include <asm/io.h> | ||
15 | #include <asm/hardware.h> | ||
16 | |||
17 | extern void davinci_watchdog_reset(void); | ||
18 | |||
19 | static void arch_idle(void) | ||
20 | { | ||
21 | cpu_do_idle(); | ||
22 | } | ||
23 | |||
24 | static void arch_reset(char mode) | ||
25 | { | ||
26 | davinci_watchdog_reset(); | ||
27 | } | ||
28 | |||
29 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/include/asm-arm/arch-davinci/timex.h b/include/asm-arm/arch-davinci/timex.h new file mode 100644 index 000000000000..52827567841d --- /dev/null +++ b/include/asm-arm/arch-davinci/timex.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* | ||
2 | * DaVinci timer defines | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_TIMEX_H | ||
12 | #define __ASM_ARCH_TIMEX_H | ||
13 | |||
14 | /* The source frequency for the timers is the 27MHz clock */ | ||
15 | #define CLOCK_TICK_RATE 27000000 | ||
16 | |||
17 | #endif /* __ASM_ARCH_TIMEX_H__ */ | ||
diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h new file mode 100644 index 000000000000..f6d1570f7206 --- /dev/null +++ b/include/asm-arm/arch-davinci/uncompress.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * Serial port stubs for kernel decompress status messages | ||
3 | * | ||
4 | * Author: Anant Gole | ||
5 | * (C) Copyright (C) 2006, Texas Instruments, Inc | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public License | ||
8 | * version 2. This program is licensed "as is" without any warranty of any | ||
9 | * kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | #include <linux/serial_reg.h> | ||
14 | #include <asm/arch/serial.h> | ||
15 | |||
16 | /* PORT_16C550A, in polled non-fifo mode */ | ||
17 | |||
18 | static void putc(char c) | ||
19 | { | ||
20 | volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; | ||
21 | |||
22 | while (!(uart[UART_LSR] & UART_LSR_THRE)) | ||
23 | barrier(); | ||
24 | uart[UART_TX] = c; | ||
25 | } | ||
26 | |||
27 | static inline void flush(void) | ||
28 | { | ||
29 | volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; | ||
30 | while (!(uart[UART_LSR] & UART_LSR_THRE)) | ||
31 | barrier(); | ||
32 | } | ||
33 | |||
34 | #define arch_decomp_setup() | ||
35 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h new file mode 100644 index 000000000000..9b47fa89b333 --- /dev/null +++ b/include/asm-arm/arch-davinci/vmalloc.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * DaVinci vmalloc definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #include <asm/memory.h> | ||
12 | #include <asm/arch/io.h> | ||
13 | |||
14 | /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ | ||
15 | #define VMALLOC_END (IO_VIRT - (2<<20)) | ||
diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S index aa23c5d6c69e..f242be5c49ba 100644 --- a/include/asm-arm/arch-ebsa110/entry-macro.S +++ b/include/asm-arm/arch-ebsa110/entry-macro.S | |||
@@ -16,13 +16,13 @@ | |||
16 | .endm | 16 | .endm |
17 | 17 | ||
18 | .macro get_irqnr_preamble, base, tmp | 18 | .macro get_irqnr_preamble, base, tmp |
19 | mov \base, #IRQ_STAT | ||
19 | .endm | 20 | .endm |
20 | 21 | ||
21 | .macro arch_ret_to_user, tmp1, tmp2 | 22 | .macro arch_ret_to_user, tmp1, tmp2 |
22 | .endm | 23 | .endm |
23 | 24 | ||
24 | .macro get_irqnr_and_base, irqnr, stat, base, tmp | 25 | .macro get_irqnr_and_base, irqnr, stat, base, tmp |
25 | mov \base, #IRQ_STAT | ||
26 | ldrb \stat, [\base] @ get interrupts | 26 | ldrb \stat, [\base] @ get interrupts |
27 | mov \irqnr, #0 | 27 | mov \irqnr, #0 |
28 | tst \stat, #15 | 28 | tst \stat, #15 |
diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S index 4203dbf10662..e63064edb734 100644 --- a/include/asm-arm/arch-ebsa285/entry-macro.S +++ b/include/asm-arm/arch-ebsa285/entry-macro.S | |||
@@ -11,24 +11,24 @@ | |||
11 | #include <asm/arch/irqs.h> | 11 | #include <asm/arch/irqs.h> |
12 | #include <asm/hardware/dec21285.h> | 12 | #include <asm/hardware/dec21285.h> |
13 | 13 | ||
14 | .equ dc21285_high, ARMCSR_BASE & 0xff000000 | ||
15 | .equ dc21285_low, ARMCSR_BASE & 0x00ffffff | ||
16 | |||
14 | .macro disable_fiq | 17 | .macro disable_fiq |
15 | .endm | 18 | .endm |
16 | 19 | ||
17 | .macro get_irqnr_preamble, base, tmp | 20 | .macro get_irqnr_preamble, base, tmp |
21 | mov \base, #dc21285_high | ||
22 | .if dc21285_low | ||
23 | orr \base, \base, #dc21285_low | ||
24 | .endif | ||
18 | .endm | 25 | .endm |
19 | 26 | ||
20 | .macro arch_ret_to_user, tmp1, tmp2 | 27 | .macro arch_ret_to_user, tmp1, tmp2 |
21 | .endm | 28 | .endm |
22 | 29 | ||
23 | .equ dc21285_high, ARMCSR_BASE & 0xff000000 | ||
24 | .equ dc21285_low, ARMCSR_BASE & 0x00ffffff | ||
25 | |||
26 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 30 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
27 | mov r4, #dc21285_high | 31 | ldr \irqstat, [\base, #0x180] @ get interrupts |
28 | .if dc21285_low | ||
29 | orr r4, r4, #dc21285_low | ||
30 | .endif | ||
31 | ldr \irqstat, [r4, #0x180] @ get interrupts | ||
32 | 32 | ||
33 | mov \irqnr, #IRQ_SDRAMPARITY | 33 | mov \irqnr, #IRQ_SDRAMPARITY |
34 | tst \irqstat, #IRQ_MASK_SDRAMPARITY | 34 | tst \irqstat, #IRQ_MASK_SDRAMPARITY |
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h index 7dfff4ad82b3..a6e0f9e6ddcf 100644 --- a/include/asm-arm/arch-iop13xx/io.h +++ b/include/asm-arm/arch-iop13xx/io.h | |||
@@ -27,7 +27,7 @@ | |||
27 | 27 | ||
28 | extern void __iomem * __iop13xx_io(unsigned long io_addr); | 28 | extern void __iomem * __iop13xx_io(unsigned long io_addr); |
29 | extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, | 29 | extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, |
30 | unsigned long flags); | 30 | unsigned int mtype); |
31 | extern void __iop13xx_iounmap(void __iomem *addr); | 31 | extern void __iop13xx_iounmap(void __iomem *addr); |
32 | 32 | ||
33 | extern u32 iop13xx_atue_mem_base; | 33 | extern u32 iop13xx_atue_mem_base; |
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index 85707e9c3325..e6736c3d1f7f 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h | |||
@@ -181,6 +181,7 @@ static inline int iop13xx_cpu_id(void) | |||
181 | #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 | 181 | #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 |
182 | #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 | 182 | #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 |
183 | #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 | 183 | #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 |
184 | #define IOP13XX_MU_PMMR_OFFSET 0x00004000 | ||
184 | #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 | 185 | #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 |
185 | #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) | 186 | #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) |
186 | 187 | ||
@@ -412,6 +413,34 @@ static inline int iop13xx_cpu_id(void) | |||
412 | #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) | 413 | #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) |
413 | /*=======================================================================*/ | 414 | /*=======================================================================*/ |
414 | 415 | ||
416 | /*============================MESSAGING UNIT=============================*/ | ||
417 | #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ | ||
418 | (ofs)) | ||
419 | |||
420 | #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) | ||
421 | #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) | ||
422 | #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) | ||
423 | #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) | ||
424 | #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) | ||
425 | #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) | ||
426 | #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) | ||
427 | #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) | ||
428 | #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) | ||
429 | #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) | ||
430 | #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) | ||
431 | #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) | ||
432 | #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) | ||
433 | #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) | ||
434 | #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) | ||
435 | #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) | ||
436 | |||
437 | #define IOP13XX_MU_WINDOW_SIZE (8 * 1024) | ||
438 | #define IOP13XX_MU_BASE_PHYS (0xff000000) | ||
439 | #define IOP13XX_MU_BASE_PCI (0xff000000) | ||
440 | #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) | ||
441 | #define IOP13XX_MU_MIMR_CORE_SELECT (15) | ||
442 | /*=======================================================================*/ | ||
443 | |||
415 | /*==============================ADMA UNITS===============================*/ | 444 | /*==============================ADMA UNITS===============================*/ |
416 | #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) | 445 | #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) |
417 | #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) | 446 | #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) |
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 5c6fac2a4004..054e7acb5bfa 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h | |||
@@ -168,7 +168,7 @@ static inline u32 read_intpnd_3(void) | |||
168 | #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ | 168 | #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ |
169 | #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ | 169 | #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ |
170 | #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ | 170 | #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ |
171 | #define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ | 171 | #define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ |
172 | #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ | 172 | #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ |
173 | #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ | 173 | #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ |
174 | #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ | 174 | #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ |
@@ -184,7 +184,13 @@ static inline u32 read_intpnd_3(void) | |||
184 | #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ | 184 | #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ |
185 | #define IRQ_IOP13XX_HPI (127) /* 31 */ | 185 | #define IRQ_IOP13XX_HPI (127) /* 31 */ |
186 | 186 | ||
187 | #ifdef CONFIG_PCI_MSI | ||
188 | #define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) | ||
189 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) | ||
190 | #else | ||
187 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) | 191 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) |
192 | #endif | ||
193 | |||
188 | #define NR_IRQS NR_IOP13XX_IRQS | 194 | #define NR_IRQS NR_IOP13XX_IRQS |
189 | 195 | ||
190 | #endif /* _IOP13XX_IRQ_H_ */ | 196 | #endif /* _IOP13XX_IRQ_H_ */ |
diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h new file mode 100644 index 000000000000..b80c5ae17e99 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/msi.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef _IOP13XX_MSI_H_ | ||
2 | #define _IOP13XX_MSI_H_ | ||
3 | #ifdef CONFIG_PCI_MSI | ||
4 | void iop13xx_msi_init(void); | ||
5 | #else | ||
6 | static inline void iop13xx_msi_init(void) | ||
7 | { | ||
8 | return; | ||
9 | } | ||
10 | #endif | ||
11 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 994f16af5057..958af751a484 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
15 | 15 | ||
16 | extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, | 16 | extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, |
17 | unsigned long flags); | 17 | unsigned int mtype); |
18 | extern void __iop3xx_iounmap(void __iomem *addr); | 18 | extern void __iop3xx_iounmap(void __iomem *addr); |
19 | 19 | ||
20 | #define IO_SPACE_LIMIT 0xffffffff | 20 | #define IO_SPACE_LIMIT 0xffffffff |
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index 993f7589b29f..fec9c53e2b10 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
15 | 15 | ||
16 | extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, | 16 | extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, |
17 | unsigned long flags); | 17 | unsigned int mtype); |
18 | extern void __iop3xx_iounmap(void __iomem *addr); | 18 | extern void __iop3xx_iounmap(void __iomem *addr); |
19 | 19 | ||
20 | #define IO_SPACE_LIMIT 0xffffffff | 20 | #define IO_SPACE_LIMIT 0xffffffff |
diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S new file mode 100644 index 000000000000..cd5f2fb1f06e --- /dev/null +++ b/include/asm-arm/arch-ks8695/debug-macro.S | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/debug-macro.S | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Debug macros | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <asm/hardware.h> | ||
15 | #include <asm/arch/regs-uart.h> | ||
16 | |||
17 | .macro addruart, rx | ||
18 | mrc p15, 0, \rx, c1, c0 | ||
19 | tst \rx, #1 @ MMU enabled? | ||
20 | ldreq \rx, =KS8695_UART_PA @ physical base address | ||
21 | ldrne \rx, =KS8695_UART_VA @ virtual base address | ||
22 | .endm | ||
23 | |||
24 | .macro senduart, rd, rx | ||
25 | str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register | ||
26 | .endm | ||
27 | |||
28 | .macro busyuart, rd, rx | ||
29 | 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register | ||
30 | tst \rd, #URLS_URTE @ Holding & Shift registers empty? | ||
31 | beq 1001b | ||
32 | .endm | ||
33 | |||
34 | .macro waituart, rd, rx | ||
35 | 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register | ||
36 | tst \rd, #URLS_URTHRE @ Holding Register empty? | ||
37 | beq 1001b | ||
38 | .endm | ||
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h new file mode 100644 index 000000000000..b0364dce463f --- /dev/null +++ b/include/asm-arm/arch-ks8695/devices.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/devices.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_DEVICES_H | ||
12 | #define __ASM_ARCH_DEVICES_H | ||
13 | |||
14 | #include <linux/pci.h> | ||
15 | |||
16 | /* Ethernet */ | ||
17 | extern void __init ks8695_add_device_wan(void); | ||
18 | extern void __init ks8695_add_device_lan(void); | ||
19 | extern void __init ks8695_add_device_hpna(void); | ||
20 | |||
21 | /* PCI */ | ||
22 | #define KS8695_MODE_PCI 0 | ||
23 | #define KS8695_MODE_MINIPCI 1 | ||
24 | #define KS8695_MODE_CARDBUS 2 | ||
25 | |||
26 | struct ks8695_pci_cfg { | ||
27 | short mode; | ||
28 | int (*map_irq)(struct pci_dev *, u8, u8); | ||
29 | }; | ||
30 | extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); | ||
31 | |||
32 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h new file mode 100644 index 000000000000..e5159ed42a4b --- /dev/null +++ b/include/asm-arm/arch-ks8695/dma.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/dma.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S new file mode 100644 index 000000000000..e34bdf85920e --- /dev/null +++ b/include/asm-arm/arch-ks8695/entry-macro.S | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/entry-macro.S | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * Low-level IRQ helper macros for KS8695 | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <asm/hardware.h> | ||
15 | #include <asm/arch/regs-irq.h> | ||
16 | |||
17 | .macro disable_fiq | ||
18 | .endm | ||
19 | |||
20 | .macro get_irqnr_preamble, base, tmp | ||
21 | ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller | ||
22 | .endm | ||
23 | |||
24 | .macro arch_ret_to_user, tmp1, tmp2 | ||
25 | .endm | ||
26 | |||
27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
28 | ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register | ||
29 | |||
30 | teq \irqstat, #0 | ||
31 | beq 1001f | ||
32 | |||
33 | mov \irqnr, #0 | ||
34 | |||
35 | tst \irqstat, #0xff | ||
36 | moveq \irqstat, \irqstat, lsr #8 | ||
37 | addeq \irqnr, \irqnr, #8 | ||
38 | tsteq \irqstat, #0xff | ||
39 | moveq \irqstat, \irqstat, lsr #8 | ||
40 | addeq \irqnr, \irqnr, #8 | ||
41 | tsteq \irqstat, #0xff | ||
42 | moveq \irqstat, \irqstat, lsr #8 | ||
43 | addeq \irqnr, \irqnr, #8 | ||
44 | tst \irqstat, #0x0f | ||
45 | moveq \irqstat, \irqstat, lsr #4 | ||
46 | addeq \irqnr, \irqnr, #4 | ||
47 | tst \irqstat, #0x03 | ||
48 | moveq \irqstat, \irqstat, lsr #2 | ||
49 | addeq \irqnr, \irqnr, #2 | ||
50 | tst \irqstat, #0x01 | ||
51 | addeqs \irqnr, \irqnr, #1 | ||
52 | 1001: | ||
53 | .endm | ||
diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h new file mode 100644 index 000000000000..cb732bff3288 --- /dev/null +++ b/include/asm-arm/arch-ks8695/hardware.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/hardware.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Memory Map definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
15 | #define __ASM_ARCH_HARDWARE_H | ||
16 | |||
17 | #include <asm/sizes.h> | ||
18 | |||
19 | /* | ||
20 | * Physical RAM address. | ||
21 | */ | ||
22 | #define KS8695_SDRAM_PA 0x00000000 | ||
23 | |||
24 | |||
25 | /* | ||
26 | * We map an entire MiB with the System Configuration Registers in even | ||
27 | * though only 64KiB is needed. This makes it easier for use with the | ||
28 | * head debug code as the initial MMU setup only deals in L1 sections. | ||
29 | */ | ||
30 | #define KS8695_IO_PA 0x03F00000 | ||
31 | #define KS8695_IO_VA 0xF0000000 | ||
32 | #define KS8695_IO_SIZE SZ_1M | ||
33 | |||
34 | #define KS8695_PCIMEM_PA 0x60000000 | ||
35 | #define KS8695_PCIMEM_SIZE SZ_512M | ||
36 | |||
37 | #define KS8695_PCIIO_PA 0x80000000 | ||
38 | #define KS8695_PCIIO_SIZE SZ_64K | ||
39 | |||
40 | |||
41 | /* | ||
42 | * PCI support | ||
43 | */ | ||
44 | #define pcibios_assign_all_busses() 1 | ||
45 | |||
46 | #define PCIBIOS_MIN_IO 0 | ||
47 | #define PCIBIOS_MIN_MEM 0 | ||
48 | |||
49 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h new file mode 100644 index 000000000000..8edc4bd6aadf --- /dev/null +++ b/include/asm-arm/arch-ks8695/io.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/io.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_IO_H | ||
12 | #define __ASM_ARCH_IO_H | ||
13 | |||
14 | #define IO_SPACE_LIMIT 0xffffffff | ||
15 | |||
16 | #define __io(a) ((void __iomem *)(a)) | ||
17 | #define __mem_pci(a) (a) | ||
18 | |||
19 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h new file mode 100644 index 000000000000..8b1c4fe96a81 --- /dev/null +++ b/include/asm-arm/arch-ks8695/irqs.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-ks8695/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_IRQS_H | ||
13 | #define __ASM_ARCH_IRQS_H | ||
14 | |||
15 | |||
16 | #define NR_IRQS 32 | ||
17 | |||
18 | /* | ||
19 | * IRQ definitions | ||
20 | */ | ||
21 | #define KS8695_IRQ_COMM_RX 0 | ||
22 | #define KS8695_IRQ_COMM_TX 1 | ||
23 | #define KS8695_IRQ_EXTERN0 2 | ||
24 | #define KS8695_IRQ_EXTERN1 3 | ||
25 | #define KS8695_IRQ_EXTERN2 4 | ||
26 | #define KS8695_IRQ_EXTERN3 5 | ||
27 | #define KS8695_IRQ_TIMER0 6 | ||
28 | #define KS8695_IRQ_TIMER1 7 | ||
29 | #define KS8695_IRQ_UART_TX 8 | ||
30 | #define KS8695_IRQ_UART_RX 9 | ||
31 | #define KS8695_IRQ_UART_LINE_STATUS 10 | ||
32 | #define KS8695_IRQ_UART_MODEM_STATUS 11 | ||
33 | #define KS8695_IRQ_LAN_RX_STOP 12 | ||
34 | #define KS8695_IRQ_LAN_TX_STOP 13 | ||
35 | #define KS8695_IRQ_LAN_RX_BUF 14 | ||
36 | #define KS8695_IRQ_LAN_TX_BUF 15 | ||
37 | #define KS8695_IRQ_LAN_RX_STATUS 16 | ||
38 | #define KS8695_IRQ_LAN_TX_STATUS 17 | ||
39 | #define KS8695_IRQ_HPNA_RX_STOP 18 | ||
40 | #define KS8695_IRQ_HPNA_TX_STOP 19 | ||
41 | #define KS8695_IRQ_HPNA_RX_BUF 20 | ||
42 | #define KS8695_IRQ_HPNA_TX_BUF 21 | ||
43 | #define KS8695_IRQ_HPNA_RX_STATUS 22 | ||
44 | #define KS8695_IRQ_HPNA_TX_STATUS 23 | ||
45 | #define KS8695_IRQ_BUS_ERROR 24 | ||
46 | #define KS8695_IRQ_WAN_RX_STOP 25 | ||
47 | #define KS8695_IRQ_WAN_TX_STOP 26 | ||
48 | #define KS8695_IRQ_WAN_RX_BUF 27 | ||
49 | #define KS8695_IRQ_WAN_TX_BUF 28 | ||
50 | #define KS8695_IRQ_WAN_RX_STATUS 29 | ||
51 | #define KS8695_IRQ_WAN_TX_STATUS 30 | ||
52 | #define KS8695_IRQ_WAN_LINK 31 | ||
53 | |||
54 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h new file mode 100644 index 000000000000..24f6a6e4a302 --- /dev/null +++ b/include/asm-arm/arch-ks8695/memory.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/memory.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 Memory definitions | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MEMORY_H | ||
14 | #define __ASM_ARCH_MEMORY_H | ||
15 | |||
16 | #include <asm/hardware.h> | ||
17 | |||
18 | /* | ||
19 | * Physical SRAM offset. | ||
20 | */ | ||
21 | #define PHYS_OFFSET KS8695_SDRAM_PA | ||
22 | |||
23 | #ifndef __ASSEMBLY__ | ||
24 | |||
25 | #ifdef CONFIG_PCI | ||
26 | |||
27 | /* PCI mappings */ | ||
28 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) | ||
29 | #define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) | ||
30 | |||
31 | /* Platform-bus mapping */ | ||
32 | extern struct bus_type platform_bus_type; | ||
33 | #define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) | ||
34 | #define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \ | ||
35 | __phys_to_virt(x) : __bus_to_virt(x); }) | ||
36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ | ||
37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) | ||
38 | #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) | ||
39 | |||
40 | #else | ||
41 | |||
42 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
43 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
44 | |||
45 | #endif | ||
46 | |||
47 | #endif | ||
48 | |||
49 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h new file mode 100644 index 000000000000..57fcf9fc82e4 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-gpio.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-gpio.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - GPIO control registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_GPIO_H | ||
14 | #define KS8695_GPIO_H | ||
15 | |||
16 | #define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) | ||
17 | #define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) | ||
18 | #define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) | ||
19 | |||
20 | |||
21 | #define KS8695_IOPM (0x00) /* I/O Port Mode Register */ | ||
22 | #define KS8695_IOPC (0x04) /* I/O Port Control Register */ | ||
23 | #define KS8695_IOPD (0x08) /* I/O Port Data Register */ | ||
24 | |||
25 | |||
26 | /* Port Mode Register */ | ||
27 | #define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ | ||
28 | |||
29 | /* Port Control Register */ | ||
30 | #define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ | ||
31 | #define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ | ||
32 | #define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ | ||
33 | #define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ | ||
34 | #define IOPC_IOEINT3_MODE(x) ((x) << 12) | ||
35 | #define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ | ||
36 | #define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ | ||
37 | #define IOPC_IOEINT2_MODE(x) ((x) << 8) | ||
38 | #define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ | ||
39 | #define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ | ||
40 | #define IOPC_IOEINT1_MODE(x) ((x) << 4) | ||
41 | #define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ | ||
42 | #define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ | ||
43 | #define IOPC_IOEINT0_MODE(x) ((x) << 0) | ||
44 | |||
45 | /* Trigger Modes */ | ||
46 | #define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ | ||
47 | #define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ | ||
48 | #define IOPC_TM_RISING (2) /* Rising Edge Detection */ | ||
49 | #define IOPC_TM_FALLING (4) /* Falling Edge Detection */ | ||
50 | #define IOPC_TM_EDGE (6) /* Both Edge Detection */ | ||
51 | |||
52 | |||
53 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h new file mode 100644 index 000000000000..14091cdec103 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-hpna.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - HPNA Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_HPNA_H | ||
14 | #define KS8695_HPNA_H | ||
15 | |||
16 | #define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) | ||
17 | #define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) | ||
18 | #define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * HPNA registers | ||
23 | */ | ||
24 | |||
25 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h new file mode 100644 index 000000000000..70b193f6b756 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-irq.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-irq.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - IRQ registers and bit definitions | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_IRQ_H | ||
15 | #define KS8695_IRQ_H | ||
16 | |||
17 | #define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) | ||
18 | #define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) | ||
19 | #define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) | ||
20 | |||
21 | |||
22 | /* | ||
23 | * Interrupt Controller registers | ||
24 | */ | ||
25 | #define KS8695_INTMC (0x00) /* Mode Control Register */ | ||
26 | #define KS8695_INTEN (0x04) /* Interrupt Enable Register */ | ||
27 | #define KS8695_INTST (0x08) /* Interrupt Status Register */ | ||
28 | #define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ | ||
29 | #define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ | ||
30 | #define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ | ||
31 | #define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ | ||
32 | #define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ | ||
33 | #define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ | ||
34 | #define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ | ||
35 | #define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ | ||
36 | #define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ | ||
37 | #define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ | ||
38 | #define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ | ||
39 | |||
40 | |||
41 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h new file mode 100644 index 000000000000..a63bd61c64ed --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-lan.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-lan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - LAN Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_LAN_H | ||
14 | #define KS8695_LAN_H | ||
15 | |||
16 | #define KS8695_LAN_OFFSET (0xF0000 + 0x8000) | ||
17 | #define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) | ||
18 | #define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * LAN registers | ||
23 | */ | ||
24 | #define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ | ||
25 | #define KS8695_LMDRXC (0x04) /* DMA Receive Control */ | ||
26 | #define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ | ||
27 | #define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ | ||
28 | #define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
29 | #define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
30 | #define KS8695_LMAL (0x18) /* MAC Station Address Low */ | ||
31 | #define KS8695_LMAH (0x1c) /* MAC Station Address High */ | ||
32 | #define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
33 | #define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
34 | |||
35 | |||
36 | /* DMA Transmit Control Register */ | ||
37 | #define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ | ||
38 | #define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
39 | #define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
40 | #define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
41 | #define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
42 | #define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
43 | #define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ | ||
44 | #define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ | ||
45 | #define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ | ||
46 | #define LMDTXC_LMTE (1 << 0) /* TX Enable */ | ||
47 | |||
48 | /* DMA Receive Control Register */ | ||
49 | #define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ | ||
50 | #define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
51 | #define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
52 | #define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ | ||
53 | #define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
54 | #define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ | ||
55 | #define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ | ||
56 | #define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ | ||
57 | #define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ | ||
58 | #define LMDRXC_LMRA (1 << 2) /* Receive All */ | ||
59 | #define LMDRXC_LMRE (1 << 1) /* RX Enable */ | ||
60 | |||
61 | /* Additional Station Address High */ | ||
62 | #define LMAAH_E (1 << 31) /* Address Enabled */ | ||
63 | |||
64 | |||
65 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h new file mode 100644 index 000000000000..76b38e0862e6 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-mem.h | |||
@@ -0,0 +1,89 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-mem.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - Memory Controller registers and bit definitions | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_MEM_H | ||
14 | #define KS8695_MEM_H | ||
15 | |||
16 | #define KS8695_MEM_OFFSET (0xF0000 + 0x4000) | ||
17 | #define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) | ||
18 | #define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * Memory Controller Registers | ||
23 | */ | ||
24 | #define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ | ||
25 | #define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ | ||
26 | #define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ | ||
27 | #define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ | ||
28 | #define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ | ||
29 | #define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ | ||
30 | #define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ | ||
31 | #define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ | ||
32 | #define KS8695_SDGCON (0x38) /* SDRAM General Control */ | ||
33 | #define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ | ||
34 | #define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ | ||
35 | |||
36 | |||
37 | /* External I/O Access Control Registers */ | ||
38 | #define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ | ||
39 | #define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ | ||
40 | #define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ | ||
41 | #define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ | ||
42 | #define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ | ||
43 | #define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ | ||
44 | |||
45 | /* ROM/SRAM/Flash Control Register */ | ||
46 | #define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ | ||
47 | #define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ | ||
48 | #define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ | ||
49 | #define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ | ||
50 | #define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ | ||
51 | #define PMC_NORMAL (0 << 0) | ||
52 | #define PMC_4WORD (1 << 0) | ||
53 | #define PMC_8WORD (2 << 0) | ||
54 | #define PMC_16WORD (3 << 0) | ||
55 | |||
56 | /* External I/O and ROM/SRAM/Flash General Register */ | ||
57 | #define ERGCON_TMULT (3 << 28) /* Time Multiplier */ | ||
58 | #define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ | ||
59 | #define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ | ||
60 | #define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ | ||
61 | #define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ | ||
62 | #define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ | ||
63 | |||
64 | /* SDRAM Control Register */ | ||
65 | #define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ | ||
66 | #define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ | ||
67 | #define SDCON_DBCAB (3 << 8) /* Column Address Bits */ | ||
68 | #define SDCON_DBBNUM (1 << 3) /* Number of Banks */ | ||
69 | #define SDCON_DBDBW (3 << 1) /* Data Bus Width */ | ||
70 | |||
71 | /* SDRAM General Control Register */ | ||
72 | #define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ | ||
73 | #define SDGCON_SDCAS (3 << 0) /* CAS latency */ | ||
74 | |||
75 | /* SDRAM Buffer Control Register */ | ||
76 | #define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ | ||
77 | #define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ | ||
78 | #define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ | ||
79 | #define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ | ||
80 | #define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ | ||
81 | #define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ | ||
82 | #define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ | ||
83 | #define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ | ||
84 | |||
85 | /* SDRAM Refresh Timer Register */ | ||
86 | #define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ | ||
87 | |||
88 | |||
89 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h new file mode 100644 index 000000000000..632ca6601a94 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-misc.h | |||
@@ -0,0 +1,97 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-misc.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - Miscellaneous Registers | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_MISC_H | ||
14 | #define KS8695_MISC_H | ||
15 | |||
16 | #define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) | ||
17 | #define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) | ||
18 | #define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * Miscellaneous registers | ||
23 | */ | ||
24 | #define KS8695_DID (0x00) /* Device ID */ | ||
25 | #define KS8695_RID (0x04) /* Revision ID */ | ||
26 | #define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ | ||
27 | #define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ | ||
28 | #define KS8695_WPPM (0x10) /* WAN PHY Power Management */ | ||
29 | #define KS8695_PPS (0x1c) /* PHY PowerSave */ | ||
30 | |||
31 | /* Device ID Register */ | ||
32 | #define DID_ID (0xffff << 0) /* Device ID */ | ||
33 | |||
34 | /* Revision ID Register */ | ||
35 | #define RID_SUBID (0xf << 4) /* Sub-Device ID */ | ||
36 | #define RID_REVISION (0xf << 0) /* Revision ID */ | ||
37 | |||
38 | /* HPNA Miscellaneous Control Register */ | ||
39 | #define HMC_HSS (1 << 1) /* Speed */ | ||
40 | #define HMC_HDS (1 << 0) /* Duplex */ | ||
41 | |||
42 | /* WAN Miscellaneous Control Register */ | ||
43 | #define WMC_WANC (1 << 30) /* Auto-negotiation complete */ | ||
44 | #define WMC_WANR (1 << 29) /* Auto-negotiation restart */ | ||
45 | #define WMC_WANAP (1 << 28) /* Advertise Pause */ | ||
46 | #define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ | ||
47 | #define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ | ||
48 | #define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ | ||
49 | #define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ | ||
50 | #define WMC_WLS (1 << 23) /* Link status */ | ||
51 | #define WMC_WDS (1 << 22) /* Duplex status */ | ||
52 | #define WMC_WSS (1 << 21) /* Speed status */ | ||
53 | #define WMC_WLPP (1 << 20) /* Link Partner Pause */ | ||
54 | #define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ | ||
55 | #define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ | ||
56 | #define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ | ||
57 | #define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ | ||
58 | #define WMC_WAND (1 << 15) /* Auto-negotiation disable */ | ||
59 | #define WMC_WANF100 (1 << 14) /* Force 100 */ | ||
60 | #define WMC_WANFF (1 << 13) /* Force FDX */ | ||
61 | #define WMC_WLED1S (7 << 4) /* LED1 Select */ | ||
62 | #define WLED1S_SPEED (0 << 4) | ||
63 | #define WLED1S_LINK (1 << 4) | ||
64 | #define WLED1S_DUPLEX (2 << 4) | ||
65 | #define WLED1S_COLLISION (3 << 4) | ||
66 | #define WLED1S_ACTIVITY (4 << 4) | ||
67 | #define WLED1S_FDX_COLLISION (5 << 4) | ||
68 | #define WLED1S_LINK_ACTIVITY (6 << 4) | ||
69 | #define WMC_WLED0S (7 << 0) /* LED0 Select */ | ||
70 | #define WLED0S_SPEED (0 << 0) | ||
71 | #define WLED0S_LINK (1 << 0) | ||
72 | #define WLED0S_DUPLEX (2 << 0) | ||
73 | #define WLED0S_COLLISION (3 << 0) | ||
74 | #define WLED0S_ACTIVITY (4 << 0) | ||
75 | #define WLED0S_FDX_COLLISION (5 << 0) | ||
76 | #define WLED0S_LINK_ACTIVITY (6 << 0) | ||
77 | |||
78 | /* WAN PHY Power Management Register */ | ||
79 | #define WPPM_WLPBK (1 << 14) /* Local Loopback */ | ||
80 | #define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ | ||
81 | #define WPPM_WPI (1 << 12) /* PHY isolate */ | ||
82 | #define WPPM_WFL (1 << 10) /* Force link */ | ||
83 | #define WPPM_MDIXS (1 << 9) /* MDIX Status */ | ||
84 | #define WPPM_FEF (1 << 8) /* Far End Fault */ | ||
85 | #define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ | ||
86 | #define WPPM_TXDIS (1 << 6) /* Disable transmitter */ | ||
87 | #define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ | ||
88 | #define WPPM_PD (1 << 4) /* Power Down */ | ||
89 | #define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ | ||
90 | #define WPPM_FMDX (1 << 2) /* Force MDIX */ | ||
91 | #define WPPM_LPBK (1 << 1) /* MAX Loopback */ | ||
92 | |||
93 | /* PHY Power Save Register */ | ||
94 | #define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ | ||
95 | |||
96 | |||
97 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h new file mode 100644 index 000000000000..286d6d488df8 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-pci.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-pci.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - PCI bridge registers and bit definitions. | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #define KS8695_PCI_OFFSET (0xF0000 + 0x2000) | ||
15 | #define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) | ||
16 | #define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) | ||
17 | |||
18 | |||
19 | #define KS8695_CRCFID (0x000) /* Configuration: Identification */ | ||
20 | #define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ | ||
21 | #define KS8695_CRCFRV (0x008) /* Configuration: Revision */ | ||
22 | #define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ | ||
23 | #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ | ||
24 | #define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ | ||
25 | #define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ | ||
26 | #define KS8695_PBCA (0x100) /* Bridge Configuration Address */ | ||
27 | #define KS8695_PBCD (0x104) /* Bridge Configuration Data */ | ||
28 | #define KS8695_PBM (0x200) /* Bridge Mode */ | ||
29 | #define KS8695_PBCS (0x204) /* Bridge Control and Status */ | ||
30 | #define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ | ||
31 | #define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ | ||
32 | #define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ | ||
33 | #define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ | ||
34 | #define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ | ||
35 | #define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ | ||
36 | #define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ | ||
37 | #define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ | ||
38 | |||
39 | |||
40 | /* Configuration: Identification */ | ||
41 | |||
42 | /* Configuration: Command and Status */ | ||
43 | |||
44 | /* Configuration: Revision */ | ||
45 | |||
46 | |||
47 | |||
48 | #define CFRV_GUEST (1 << 23) | ||
49 | |||
50 | #define PBCA_TYPE1 (1) | ||
51 | #define PBCA_ENABLE (1 << 31) | ||
52 | |||
53 | |||
diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h new file mode 100644 index 000000000000..5f37be3f2f60 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-switch.h | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-switch.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - Switch Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_SWITCH_H | ||
14 | #define KS8695_SWITCH_H | ||
15 | |||
16 | #define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) | ||
17 | #define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) | ||
18 | #define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * Switch registers | ||
23 | */ | ||
24 | #define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ | ||
25 | #define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ | ||
26 | #define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ | ||
27 | |||
28 | #define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ | ||
29 | |||
30 | #define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ | ||
31 | #define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ | ||
32 | #define KS8695_SEIAC (0x50) /* Indirect Access Control */ | ||
33 | #define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ | ||
34 | #define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ | ||
35 | #define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ | ||
36 | #define KS8695_SEAFC (0x60) /* Advance Feature Control */ | ||
37 | #define KS8695_SEDSCPH (0x64) /* TOS Priority High */ | ||
38 | #define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ | ||
39 | #define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ | ||
40 | #define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ | ||
41 | #define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ | ||
42 | #define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ | ||
43 | |||
44 | |||
45 | /* Switch Engine Control 0 */ | ||
46 | #define SEC0_LLED1S (7 << 25) /* LED1 Select */ | ||
47 | #define LLED1S_SPEED (0 << 25) | ||
48 | #define LLED1S_LINK (1 << 25) | ||
49 | #define LLED1S_DUPLEX (2 << 25) | ||
50 | #define LLED1S_COLLISION (3 << 25) | ||
51 | #define LLED1S_ACTIVITY (4 << 25) | ||
52 | #define LLED1S_FDX_COLLISION (5 << 25) | ||
53 | #define LLED1S_LINK_ACTIVITY (6 << 25) | ||
54 | #define SEC0_LLED0S (7 << 22) /* LED0 Select */ | ||
55 | #define LLED0S_SPEED (0 << 22) | ||
56 | #define LLED0S_LINK (1 << 22) | ||
57 | #define LLED0S_DUPLEX (2 << 22) | ||
58 | #define LLED0S_COLLISION (3 << 22) | ||
59 | #define LLED0S_ACTIVITY (4 << 22) | ||
60 | #define LLED0S_FDX_COLLISION (5 << 22) | ||
61 | #define LLED0S_LINK_ACTIVITY (6 << 22) | ||
62 | #define SEC0_ENABLE (1 << 0) /* Enable Switch */ | ||
63 | |||
64 | |||
65 | |||
66 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h new file mode 100644 index 000000000000..f3179815b8ee --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-sys.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-sys.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - System control registers and bit definitions | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_SYS_H | ||
15 | #define KS8695_SYS_H | ||
16 | |||
17 | #define KS8695_SYS_OFFSET (0xF0000 + 0x0000) | ||
18 | #define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) | ||
19 | #define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) | ||
20 | |||
21 | |||
22 | #define KS8695_SYSCFG (0x00) /* System Configuration Register */ | ||
23 | #define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ | ||
24 | |||
25 | |||
26 | /* System Configuration Register */ | ||
27 | #define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ | ||
28 | |||
29 | /* System Clock and Bus Control Register */ | ||
30 | #define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ | ||
31 | #define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ | ||
32 | |||
33 | |||
34 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h new file mode 100644 index 000000000000..0a9f7f99ec52 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-timer.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-timer.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Timer registers and bit definitions. | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_TIMER_H | ||
15 | #define KS8695_TIMER_H | ||
16 | |||
17 | #define KS8695_TMR_OFFSET (0xF0000 + 0xE400) | ||
18 | #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) | ||
19 | #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) | ||
20 | |||
21 | |||
22 | /* | ||
23 | * Timer registers | ||
24 | */ | ||
25 | #define KS8695_TMCON (0x00) /* Timer Control Register */ | ||
26 | #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ | ||
27 | #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ | ||
28 | #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ | ||
29 | #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ | ||
30 | |||
31 | |||
32 | /* Timer Control Register */ | ||
33 | #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ | ||
34 | #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ | ||
35 | |||
36 | /* Timer0 Timeout Counter Register */ | ||
37 | #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ | ||
38 | |||
39 | |||
40 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h new file mode 100644 index 000000000000..a27cb20502a3 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-uart.h | |||
@@ -0,0 +1,92 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-ks8695/regs-uart.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - UART register and bit definitions. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_UART_H | ||
15 | #define KS8695_UART_H | ||
16 | |||
17 | #define KS8695_UART_OFFSET (0xF0000 + 0xE000) | ||
18 | #define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) | ||
19 | #define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) | ||
20 | |||
21 | |||
22 | /* | ||
23 | * UART registers | ||
24 | */ | ||
25 | #define KS8695_URRB (0x00) /* Receive Buffer Register */ | ||
26 | #define KS8695_URTH (0x04) /* Transmit Holding Register */ | ||
27 | #define KS8695_URFC (0x08) /* FIFO Control Register */ | ||
28 | #define KS8695_URLC (0x0C) /* Line Control Register */ | ||
29 | #define KS8695_URMC (0x10) /* Modem Control Register */ | ||
30 | #define KS8695_URLS (0x14) /* Line Status Register */ | ||
31 | #define KS8695_URMS (0x18) /* Modem Status Register */ | ||
32 | #define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ | ||
33 | #define KS8695_USR (0x20) /* Status Register */ | ||
34 | |||
35 | |||
36 | /* FIFO Control Register */ | ||
37 | #define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ | ||
38 | #define URFC_URFRT_1 (0 << 6) | ||
39 | #define URFC_URFRT_4 (1 << 6) | ||
40 | #define URFC_URFRT_8 (2 << 6) | ||
41 | #define URFC_URFRT_14 (3 << 6) | ||
42 | #define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ | ||
43 | #define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ | ||
44 | #define URFC_URFE (1 << 0) /* FIFO Enable */ | ||
45 | |||
46 | /* Line Control Register */ | ||
47 | #define URLC_URSBC (1 << 6) /* Set Break Condition */ | ||
48 | #define URLC_PARITY (7 << 3) /* Parity */ | ||
49 | #define URPE_NONE (0 << 3) | ||
50 | #define URPE_ODD (1 << 3) | ||
51 | #define URPE_EVEN (3 << 3) | ||
52 | #define URPE_MARK (5 << 3) | ||
53 | #define URPE_SPACE (7 << 3) | ||
54 | #define URLC_URSB (1 << 2) /* Stop Bits */ | ||
55 | #define URLC_URCL (3 << 0) /* Character Length */ | ||
56 | #define URCL_5 (0 << 0) | ||
57 | #define URCL_6 (1 << 0) | ||
58 | #define URCL_7 (2 << 0) | ||
59 | #define URCL_8 (3 << 0) | ||
60 | |||
61 | /* Modem Control Register */ | ||
62 | #define URMC_URLB (1 << 4) /* Loop-back mode */ | ||
63 | #define URMC_UROUT2 (1 << 3) /* OUT2 signal */ | ||
64 | #define URMC_UROUT1 (1 << 2) /* OUT1 signal */ | ||
65 | #define URMC_URRTS (1 << 1) /* Request to Send */ | ||
66 | #define URMC_URDTR (1 << 0) /* Data Terminal Ready */ | ||
67 | |||
68 | /* Line Status Register */ | ||
69 | #define URLS_URRFE (1 << 7) /* Receive FIFO Error */ | ||
70 | #define URLS_URTE (1 << 6) /* Transmit Empty */ | ||
71 | #define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ | ||
72 | #define URLS_URBI (1 << 4) /* Break Interrupt */ | ||
73 | #define URLS_URFE (1 << 3) /* Framing Error */ | ||
74 | #define URLS_URPE (1 << 2) /* Parity Error */ | ||
75 | #define URLS_URROE (1 << 1) /* Receive Overrun Error */ | ||
76 | #define URLS_URDR (1 << 0) /* Receive Data Ready */ | ||
77 | |||
78 | /* Modem Status Register */ | ||
79 | #define URMS_URDCD (1 << 7) /* Data Carrier Detect */ | ||
80 | #define URMS_URRI (1 << 6) /* Ring Indicator */ | ||
81 | #define URMS_URDSR (1 << 5) /* Data Set Ready */ | ||
82 | #define URMS_URCTS (1 << 4) /* Clear to Send */ | ||
83 | #define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ | ||
84 | #define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ | ||
85 | #define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ | ||
86 | #define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ | ||
87 | |||
88 | /* Status Register */ | ||
89 | #define USR_UTI (1 << 0) /* Timeout Indication */ | ||
90 | |||
91 | |||
92 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h new file mode 100644 index 000000000000..52e35b0d65e4 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-wan.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - WAN Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_WAN_H | ||
14 | #define KS8695_WAN_H | ||
15 | |||
16 | #define KS8695_WAN_OFFSET (0xF0000 + 0x6000) | ||
17 | #define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) | ||
18 | #define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * WAN registers | ||
23 | */ | ||
24 | #define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ | ||
25 | #define KS8695_WMDRXC (0x04) /* DMA Receive Control */ | ||
26 | #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ | ||
27 | #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ | ||
28 | #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
29 | #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
30 | #define KS8695_WMAL (0x18) /* MAC Station Address Low */ | ||
31 | #define KS8695_WMAH (0x1c) /* MAC Station Address High */ | ||
32 | #define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
33 | #define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
34 | |||
35 | |||
36 | /* DMA Transmit Control Register */ | ||
37 | #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ | ||
38 | #define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
39 | #define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
40 | #define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
41 | #define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
42 | #define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
43 | #define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ | ||
44 | #define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ | ||
45 | #define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ | ||
46 | #define WMDTXC_WMTE (1 << 0) /* TX Enable */ | ||
47 | |||
48 | /* DMA Receive Control Register */ | ||
49 | #define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ | ||
50 | #define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
51 | #define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
52 | #define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ | ||
53 | #define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
54 | #define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ | ||
55 | #define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ | ||
56 | #define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ | ||
57 | #define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ | ||
58 | #define WMDRXC_WMRA (1 << 2) /* Receive All */ | ||
59 | #define WMDRXC_WMRE (1 << 0) /* RX Enable */ | ||
60 | |||
61 | /* Additional Station Address High */ | ||
62 | #define WMAAH_E (1 << 31) /* Address Enabled */ | ||
63 | |||
64 | |||
65 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h new file mode 100644 index 000000000000..3bc28106d937 --- /dev/null +++ b/include/asm-arm/arch-ks8695/system.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-s3c2410/system.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * KS8695 - System function defines and includes | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_SYSTEM_H | ||
15 | #define __ASM_ARCH_SYSTEM_H | ||
16 | |||
17 | #include <asm/io.h> | ||
18 | #include <asm/arch/regs-timer.h> | ||
19 | |||
20 | static void arch_idle(void) | ||
21 | { | ||
22 | /* | ||
23 | * This should do all the clock switching | ||
24 | * and wait for interrupt tricks, | ||
25 | */ | ||
26 | cpu_do_idle(); | ||
27 | |||
28 | } | ||
29 | |||
30 | static void arch_reset(char mode) | ||
31 | { | ||
32 | unsigned int reg; | ||
33 | |||
34 | if (mode == 's') | ||
35 | cpu_reset(0); | ||
36 | |||
37 | /* disable timer0 */ | ||
38 | reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | ||
39 | __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | ||
40 | |||
41 | /* enable watchdog mode */ | ||
42 | __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); | ||
43 | |||
44 | /* re-enable timer0 */ | ||
45 | __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | ||
46 | } | ||
47 | |||
48 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h new file mode 100644 index 000000000000..8320d528b903 --- /dev/null +++ b/include/asm-arm/arch-ks8695/timex.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/timex.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * KS8695 - Time Parameters | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_TIMEX_H | ||
15 | #define __ASM_ARCH_TIMEX_H | ||
16 | |||
17 | /* timers are derived from MCLK, which is 25MHz */ | ||
18 | #define CLOCK_TICK_RATE 25000000 | ||
19 | |||
20 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h new file mode 100644 index 000000000000..733a50855b5d --- /dev/null +++ b/include/asm-arm/arch-ks8695/uncompress.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/uncompress.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Kernel uncompressor | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
15 | #define __ASM_ARCH_UNCOMPRESS_H | ||
16 | |||
17 | #include <asm/io.h> | ||
18 | #include <asm/arch/regs-uart.h> | ||
19 | |||
20 | static void putc(char c) | ||
21 | { | ||
22 | while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) | ||
23 | barrier(); | ||
24 | |||
25 | __raw_writel(c, KS8695_UART_PA + KS8695_URTH); | ||
26 | } | ||
27 | |||
28 | static inline void flush(void) | ||
29 | { | ||
30 | while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) | ||
31 | barrier(); | ||
32 | } | ||
33 | |||
34 | #define arch_decomp_setup() | ||
35 | #define arch_decomp_wdog() | ||
36 | |||
37 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h new file mode 100644 index 000000000000..d1d88e58117d --- /dev/null +++ b/include/asm-arm/arch-ks8695/vmalloc.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/vmalloc.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks | ||
5 | * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk> | ||
6 | * | ||
7 | * KS8695 vmalloc definition | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_VMALLOC_H | ||
15 | #define __ASM_ARCH_VMALLOC_H | ||
16 | |||
17 | #define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK) | ||
18 | |||
19 | #endif | ||
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 828cc5c114e1..f1ec2edd4040 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h | |||
@@ -421,7 +421,9 @@ enum omap24xx_index { | |||
421 | /* 24xx clock */ | 421 | /* 24xx clock */ |
422 | W14_24XX_SYS_CLKOUT, | 422 | W14_24XX_SYS_CLKOUT, |
423 | 423 | ||
424 | /* 24xx GPMC wait pin monitoring */ | 424 | /* 24xx GPMC chipselects, wait pin monitoring */ |
425 | E2_GPMC_NCS2, | ||
426 | L2_GPMC_NCS7, | ||
425 | L3_GPMC_WAIT0, | 427 | L3_GPMC_WAIT0, |
426 | N7_GPMC_WAIT1, | 428 | N7_GPMC_WAIT1, |
427 | M1_GPMC_WAIT2, | 429 | M1_GPMC_WAIT2, |
@@ -435,6 +437,7 @@ enum omap24xx_index { | |||
435 | 437 | ||
436 | /* 24xx GPIO */ | 438 | /* 24xx GPIO */ |
437 | M21_242X_GPIO11, | 439 | M21_242X_GPIO11, |
440 | P21_242X_GPIO12, | ||
438 | AA10_242X_GPIO13, | 441 | AA10_242X_GPIO13, |
439 | AA6_242X_GPIO14, | 442 | AA6_242X_GPIO14, |
440 | AA4_242X_GPIO15, | 443 | AA4_242X_GPIO15, |
@@ -444,7 +447,9 @@ enum omap24xx_index { | |||
444 | Y20_24XX_GPIO60, | 447 | Y20_24XX_GPIO60, |
445 | W4__24XX_GPIO74, | 448 | W4__24XX_GPIO74, |
446 | M15_24XX_GPIO92, | 449 | M15_24XX_GPIO92, |
450 | J15_24XX_GPIO99, | ||
447 | V14_24XX_GPIO117, | 451 | V14_24XX_GPIO117, |
452 | P14_24XX_GPIO125, | ||
448 | 453 | ||
449 | /* 242x DBG GPIO */ | 454 | /* 242x DBG GPIO */ |
450 | V4_242X_GPIO49, | 455 | V4_242X_GPIO49, |
@@ -486,6 +491,30 @@ enum omap24xx_index { | |||
486 | G18_24XX_MMC_CMD_DIR, | 491 | G18_24XX_MMC_CMD_DIR, |
487 | H15_24XX_MMC_CLKI, | 492 | H15_24XX_MMC_CLKI, |
488 | 493 | ||
494 | /* Full speed USB */ | ||
495 | J20_24XX_USB0_PUEN, | ||
496 | J19_24XX_USB0_VP, | ||
497 | K20_24XX_USB0_VM, | ||
498 | J18_24XX_USB0_RCV, | ||
499 | K19_24XX_USB0_TXEN, | ||
500 | J14_24XX_USB0_SE0, | ||
501 | K18_24XX_USB0_DAT, | ||
502 | |||
503 | N14_24XX_USB1_SE0, | ||
504 | W12_24XX_USB1_SE0, | ||
505 | P15_24XX_USB1_DAT, | ||
506 | R13_24XX_USB1_DAT, | ||
507 | W20_24XX_USB1_TXEN, | ||
508 | P13_24XX_USB1_TXEN, | ||
509 | V19_24XX_USB1_RCV, | ||
510 | V12_24XX_USB1_RCV, | ||
511 | |||
512 | AA10_24XX_USB2_SE0, | ||
513 | Y11_24XX_USB2_DAT, | ||
514 | AA12_24XX_USB2_TXEN, | ||
515 | AA6_24XX_USB2_RCV, | ||
516 | AA4_24XX_USB2_TLLSE0, | ||
517 | |||
489 | /* Keypad GPIO*/ | 518 | /* Keypad GPIO*/ |
490 | T19_24XX_KBR0, | 519 | T19_24XX_KBR0, |
491 | R19_24XX_KBR1, | 520 | R19_24XX_KBR1, |
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 138838d4ad75..3b4e2076603a 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S | |||
@@ -14,6 +14,7 @@ | |||
14 | .endm | 14 | .endm |
15 | 15 | ||
16 | .macro get_irqnr_preamble, base, tmp | 16 | .macro get_irqnr_preamble, base, tmp |
17 | ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) | ||
17 | .endm | 18 | .endm |
18 | 19 | ||
19 | .macro arch_ret_to_user, tmp1, tmp2 | 20 | .macro arch_ret_to_user, tmp1, tmp2 |
@@ -40,7 +41,6 @@ | |||
40 | 41 | ||
41 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 42 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
42 | 43 | ||
43 | ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) | ||
44 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | 44 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ |
45 | 45 | ||
46 | ldr \tmp, =1021 | 46 | ldr \tmp, =1021 |
diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S index 0cfb89b229d1..038b761fdadc 100644 --- a/include/asm-arm/arch-rpc/entry-macro.S +++ b/include/asm-arm/arch-rpc/entry-macro.S | |||
@@ -1,6 +1,14 @@ | |||
1 | #include <asm/hardware.h> | 1 | #include <asm/hardware.h> |
2 | #include <asm/hardware/entry-macro-iomd.S> | 2 | #include <asm/hardware/entry-macro-iomd.S> |
3 | |||
4 | .equ ioc_base_high, IOC_BASE & 0xff000000 | ||
5 | .equ ioc_base_low, IOC_BASE & 0x00ff0000 | ||
6 | |||
3 | .macro get_irqnr_preamble, base, tmp | 7 | .macro get_irqnr_preamble, base, tmp |
8 | mov \base, #ioc_base_high @ point at IOC | ||
9 | .if ioc_base_low | ||
10 | orr \base, \base, #ioc_base_low | ||
11 | .endif | ||
4 | .endm | 12 | .endm |
5 | 13 | ||
6 | .macro arch_ret_to_user, tmp1, tmp2 | 14 | .macro arch_ret_to_user, tmp1, tmp2 |
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h index cd9e26568f85..c1414658d1c5 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | |||
@@ -129,6 +129,7 @@ | |||
129 | #define S3C2443_PCLKCON_IIC (1<<4) | 129 | #define S3C2443_PCLKCON_IIC (1<<4) |
130 | #define S3C2443_PCLKCON_SDI (1<<5) | 130 | #define S3C2443_PCLKCON_SDI (1<<5) |
131 | #define S3C2443_PCLKCON_ADC (1<<7) | 131 | #define S3C2443_PCLKCON_ADC (1<<7) |
132 | #define S3C2443_PCLKCON_AC97 (1<<8) | ||
132 | #define S3C2443_PCLKCON_IIS (1<<9) | 133 | #define S3C2443_PCLKCON_IIS (1<<9) |
133 | #define S3C2443_PCLKCON_PWMT (1<<10) | 134 | #define S3C2443_PCLKCON_PWMT (1<<10) |
134 | #define S3C2443_PCLKCON_WDT (1<<11) | 135 | #define S3C2443_PCLKCON_WDT (1<<11) |
diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S index 028967629340..127db4aaf4f2 100644 --- a/include/asm-arm/arch-sa1100/entry-macro.S +++ b/include/asm-arm/arch-sa1100/entry-macro.S | |||
@@ -12,16 +12,16 @@ | |||
12 | .endm | 12 | .endm |
13 | 13 | ||
14 | .macro get_irqnr_preamble, base, tmp | 14 | .macro get_irqnr_preamble, base, tmp |
15 | mov \base, #0xfa000000 @ ICIP = 0xfa050000 | ||
16 | add \base, \base, #0x00050000 | ||
15 | .endm | 17 | .endm |
16 | 18 | ||
17 | .macro arch_ret_to_user, tmp1, tmp2 | 19 | .macro arch_ret_to_user, tmp1, tmp2 |
18 | .endm | 20 | .endm |
19 | 21 | ||
20 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
21 | mov r4, #0xfa000000 @ ICIP = 0xfa050000 | 23 | ldr \irqstat, [\base] @ get irqs |
22 | add r4, r4, #0x00050000 | 24 | ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 |
23 | ldr \irqstat, [r4] @ get irqs | ||
24 | ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004 | ||
25 | ands \irqstat, \irqstat, \irqnr | 25 | ands \irqstat, \irqstat, \irqnr |
26 | mov \irqnr, #0 | 26 | mov \irqnr, #0 |
27 | beq 1001f | 27 | beq 1001f |
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S index 0fae002637a0..924d1a8fe360 100644 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ b/include/asm-arm/arch-versatile/entry-macro.S | |||
@@ -14,13 +14,13 @@ | |||
14 | .endm | 14 | .endm |
15 | 15 | ||
16 | .macro get_irqnr_preamble, base, tmp | 16 | .macro get_irqnr_preamble, base, tmp |
17 | ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) | ||
17 | .endm | 18 | .endm |
18 | 19 | ||
19 | .macro arch_ret_to_user, tmp1, tmp2 | 20 | .macro arch_ret_to_user, tmp1, tmp2 |
20 | .endm | 21 | .endm |
21 | 22 | ||
22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
23 | ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) | ||
24 | ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status | 24 | ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status |
25 | mov \irqnr, #0 | 25 | mov \irqnr, #0 |
26 | teq \irqstat, #0 | 26 | teq \irqstat, #0 |
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 3a6d3eb27622..684fe0645239 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h | |||
@@ -121,7 +121,7 @@ struct in_ecid { /* Packed card ID information */ | |||
121 | typedef struct expansion_card ecard_t; | 121 | typedef struct expansion_card ecard_t; |
122 | typedef unsigned long *loader_t; | 122 | typedef unsigned long *loader_t; |
123 | 123 | ||
124 | typedef struct { /* Card handler routines */ | 124 | typedef struct expansion_card_ops { /* Card handler routines */ |
125 | void (*irqenable)(ecard_t *ec, int irqnr); | 125 | void (*irqenable)(ecard_t *ec, int irqnr); |
126 | void (*irqdisable)(ecard_t *ec, int irqnr); | 126 | void (*irqdisable)(ecard_t *ec, int irqnr); |
127 | int (*irqpending)(ecard_t *ec); | 127 | int (*irqpending)(ecard_t *ec); |
@@ -179,6 +179,8 @@ struct expansion_card { | |||
179 | u64 dma_mask; | 179 | u64 dma_mask; |
180 | }; | 180 | }; |
181 | 181 | ||
182 | void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); | ||
183 | |||
182 | struct in_chunk_dir { | 184 | struct in_chunk_dir { |
183 | unsigned int start_offset; | 185 | unsigned int start_offset; |
184 | union { | 186 | union { |
@@ -224,6 +226,10 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) | |||
224 | extern int ecard_request_resources(struct expansion_card *ec); | 226 | extern int ecard_request_resources(struct expansion_card *ec); |
225 | extern void ecard_release_resources(struct expansion_card *ec); | 227 | extern void ecard_release_resources(struct expansion_card *ec); |
226 | 228 | ||
229 | void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, | ||
230 | unsigned long offset, unsigned long maxsize); | ||
231 | #define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) | ||
232 | |||
227 | extern struct bus_type ecard_bus_type; | 233 | extern struct bus_type ecard_bus_type; |
228 | 234 | ||
229 | #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) | 235 | #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) |
diff --git a/include/asm-arm/hardware/entry-macro-iomd.S b/include/asm-arm/hardware/entry-macro-iomd.S index fbed08f298d0..9bb580a5b15e 100644 --- a/include/asm-arm/hardware/entry-macro-iomd.S +++ b/include/asm-arm/hardware/entry-macro-iomd.S | |||
@@ -11,8 +11,6 @@ | |||
11 | /* IOC / IOMD based hardware */ | 11 | /* IOC / IOMD based hardware */ |
12 | #include <asm/hardware/iomd.h> | 12 | #include <asm/hardware/iomd.h> |
13 | 13 | ||
14 | .equ ioc_base_high, IOC_BASE & 0xff000000 | ||
15 | .equ ioc_base_low, IOC_BASE & 0x00ff0000 | ||
16 | .macro disable_fiq | 14 | .macro disable_fiq |
17 | mov r12, #ioc_base_high | 15 | mov r12, #ioc_base_high |
18 | .if ioc_base_low | 16 | .if ioc_base_low |
@@ -22,33 +20,29 @@ | |||
22 | .endm | 20 | .endm |
23 | 21 | ||
24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
25 | mov r4, #ioc_base_high @ point at IOC | 23 | ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first |
26 | .if ioc_base_low | 24 | ldr \tmp, =irq_prio_h |
27 | orr r4, r4, #ioc_base_low | ||
28 | .endif | ||
29 | ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first | ||
30 | ldr \base, =irq_prio_h | ||
31 | teq \irqstat, #0 | 25 | teq \irqstat, #0 |
32 | #ifdef IOMD_BASE | 26 | #ifdef IOMD_BASE |
33 | ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma | 27 | ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma |
34 | addeq \base, \base, #256 @ irq_prio_h table size | 28 | addeq \tmp, \tmp, #256 @ irq_prio_h table size |
35 | teqeq \irqstat, #0 | 29 | teqeq \irqstat, #0 |
36 | bne 2406f | 30 | bne 2406f |
37 | #endif | 31 | #endif |
38 | ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority | 32 | ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority |
39 | addeq \base, \base, #256 @ irq_prio_d table size | 33 | addeq \tmp, \tmp, #256 @ irq_prio_d table size |
40 | teqeq \irqstat, #0 | 34 | teqeq \irqstat, #0 |
41 | #ifdef IOMD_IRQREQC | 35 | #ifdef IOMD_IRQREQC |
42 | ldreqb \irqstat, [r4, #IOMD_IRQREQC] | 36 | ldreqb \irqstat, [\base, #IOMD_IRQREQC] |
43 | addeq \base, \base, #256 @ irq_prio_l table size | 37 | addeq \tmp, \tmp, #256 @ irq_prio_l table size |
44 | teqeq \irqstat, #0 | 38 | teqeq \irqstat, #0 |
45 | #endif | 39 | #endif |
46 | #ifdef IOMD_IRQREQD | 40 | #ifdef IOMD_IRQREQD |
47 | ldreqb \irqstat, [r4, #IOMD_IRQREQD] | 41 | ldreqb \irqstat, [\base, #IOMD_IRQREQD] |
48 | addeq \base, \base, #256 @ irq_prio_lc table size | 42 | addeq \tmp, \tmp, #256 @ irq_prio_lc table size |
49 | teqeq \irqstat, #0 | 43 | teqeq \irqstat, #0 |
50 | #endif | 44 | #endif |
51 | 2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number | 45 | 2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number |
52 | .endm | 46 | .endm |
53 | 47 | ||
54 | /* | 48 | /* |
diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h index 7f50ae0edf1b..503843db1565 100644 --- a/include/asm-arm/sizes.h +++ b/include/asm-arm/sizes.h | |||
@@ -24,6 +24,10 @@ | |||
24 | #define __sizes_h 1 | 24 | #define __sizes_h 1 |
25 | 25 | ||
26 | /* handy sizes */ | 26 | /* handy sizes */ |
27 | #define SZ_16 0x00000010 | ||
28 | #define SZ_256 0x00000100 | ||
29 | #define SZ_512 0x00000200 | ||
30 | |||
27 | #define SZ_1K 0x00000400 | 31 | #define SZ_1K 0x00000400 |
28 | #define SZ_4K 0x00001000 | 32 | #define SZ_4K 0x00001000 |
29 | #define SZ_8K 0x00002000 | 33 | #define SZ_8K 0x00002000 |
diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h index 2bdc5bd6f793..a762f42cbb71 100644 --- a/include/asm-avr32/arch-at32ap/cpu.h +++ b/include/asm-avr32/arch-at32ap/cpu.h | |||
@@ -29,5 +29,6 @@ | |||
29 | #define cpu_is_at91sam9260() (0) | 29 | #define cpu_is_at91sam9260() (0) |
30 | #define cpu_is_at91sam9261() (0) | 30 | #define cpu_is_at91sam9261() (0) |
31 | #define cpu_is_at91sam9263() (0) | 31 | #define cpu_is_at91sam9263() (0) |
32 | #define cpu_is_at91sam9rl() (0) | ||
32 | 33 | ||
33 | #endif /* __ASM_ARCH_CPU_H */ | 34 | #endif /* __ASM_ARCH_CPU_H */ |
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index aa2653a159f4..a3ac4c896831 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h | |||
@@ -139,6 +139,10 @@ | |||
139 | /* Blackfin bf5xx */ | 139 | /* Blackfin bf5xx */ |
140 | #define PORT_BFIN 75 | 140 | #define PORT_BFIN 75 |
141 | 141 | ||
142 | /* Micrel KS8695 */ | ||
143 | #define PORT_KS8695 76 | ||
144 | |||
145 | |||
142 | #ifdef __KERNEL__ | 146 | #ifdef __KERNEL__ |
143 | 147 | ||
144 | #include <linux/compiler.h> | 148 | #include <linux/compiler.h> |