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authorRobert Schwebel <robert@schwebel.de>2008-03-28 05:59:08 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-03-31 14:46:48 -0400
commitf304fc422d9f159badb0edfa5921611a2fa371c7 (patch)
tree1ee85d115cdcf7b80b7a6e811da02c526ea91278 /include
parent05dda977f2574c3341abef9b74c27d2b362e1e3a (diff)
[ARM] 4876/1: i.MXC family: Clean up
From: Juergen Beisert <j.beisert@pengutronix.de> Clean up current header files from doxygen style comments. There are probably more such comments left, but we start with these. Things happend since last review: - needless blank lines removed (note by Russell King) - re-format comments (note by Ross Wille) Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Ross Wille <wille@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h124
-rw-r--r--include/asm-arm/arch-mxc/dma.h7
-rw-r--r--include/asm-arm/arch-mxc/hardware.h8
-rw-r--r--include/asm-arm/arch-mxc/io.h15
-rw-r--r--include/asm-arm/arch-mxc/irqs.h17
-rw-r--r--include/asm-arm/arch-mxc/memory.h13
-rw-r--r--include/asm-arm/arch-mxc/mxc.h6
-rw-r--r--include/asm-arm/arch-mxc/system.h18
-rw-r--r--include/asm-arm/arch-mxc/vmalloc.h14
9 files changed, 61 insertions, 161 deletions
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index be29b83ad4ae..8590127760a8 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -11,107 +11,77 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13 13
14/*! 14/* Base address of PBC controller */
15 * @name PBC Controller parameters
16 */
17/*! @{ */
18/*!
19 * Base address of PBC controller
20 */
21#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 15#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
22/* Offsets for the PBC Controller register */ 16/* Offsets for the PBC Controller register */
23/*! 17
24 * PBC Board status register offset 18/* PBC Board status register offset */
25 */
26#define PBC_BSTAT 0x000002 19#define PBC_BSTAT 0x000002
27/*! 20
28 * PBC Board control register 1 set address. 21/* PBC Board control register 1 set address */
29 */
30#define PBC_BCTRL1_SET 0x000004 22#define PBC_BCTRL1_SET 0x000004
31/*! 23
32 * PBC Board control register 1 clear address. 24/* PBC Board control register 1 clear address */
33 */
34#define PBC_BCTRL1_CLEAR 0x000006 25#define PBC_BCTRL1_CLEAR 0x000006
35/*! 26
36 * PBC Board control register 2 set address. 27/* PBC Board control register 2 set address */
37 */
38#define PBC_BCTRL2_SET 0x000008 28#define PBC_BCTRL2_SET 0x000008
39/*! 29
40 * PBC Board control register 2 clear address. 30/* PBC Board control register 2 clear address */
41 */
42#define PBC_BCTRL2_CLEAR 0x00000A 31#define PBC_BCTRL2_CLEAR 0x00000A
43/*! 32
44 * PBC Board control register 3 set address. 33/* PBC Board control register 3 set address */
45 */
46#define PBC_BCTRL3_SET 0x00000C 34#define PBC_BCTRL3_SET 0x00000C
47/*! 35
48 * PBC Board control register 3 clear address. 36/* PBC Board control register 3 clear address */
49 */
50#define PBC_BCTRL3_CLEAR 0x00000E 37#define PBC_BCTRL3_CLEAR 0x00000E
51/*! 38
52 * PBC Board control register 4 set address. 39/* PBC Board control register 4 set address */
53 */
54#define PBC_BCTRL4_SET 0x000010 40#define PBC_BCTRL4_SET 0x000010
55/*! 41
56 * PBC Board control register 4 clear address. 42/* PBC Board control register 4 clear address */
57 */
58#define PBC_BCTRL4_CLEAR 0x000012 43#define PBC_BCTRL4_CLEAR 0x000012
59/*! 44
60 * PBC Board status register 1. 45/* PBC Board status register 1 */
61 */
62#define PBC_BSTAT1 0x000014 46#define PBC_BSTAT1 0x000014
63/*! 47
64 * PBC Board interrupt status register. 48/* PBC Board interrupt status register */
65 */
66#define PBC_INTSTATUS 0x000016 49#define PBC_INTSTATUS 0x000016
67/*! 50
68 * PBC Board interrupt current status register. 51/* PBC Board interrupt current status register */
69 */
70#define PBC_INTCURR_STATUS 0x000018 52#define PBC_INTCURR_STATUS 0x000018
71/*! 53
72 * PBC Interrupt mask register set address. 54/* PBC Interrupt mask register set address */
73 */
74#define PBC_INTMASK_SET 0x00001A 55#define PBC_INTMASK_SET 0x00001A
75/*! 56
76 * PBC Interrupt mask register clear address. 57/* PBC Interrupt mask register clear address */
77 */
78#define PBC_INTMASK_CLEAR 0x00001C 58#define PBC_INTMASK_CLEAR 0x00001C
79 59
80/*! 60/* External UART A */
81 * External UART A.
82 */
83#define PBC_SC16C652_UARTA 0x010000 61#define PBC_SC16C652_UARTA 0x010000
84/*! 62
85 * External UART B. 63/* External UART B */
86 */
87#define PBC_SC16C652_UARTB 0x010010 64#define PBC_SC16C652_UARTB 0x010010
88/*! 65
89 * Ethernet Controller IO base address. 66/* Ethernet Controller IO base address */
90 */
91#define PBC_CS8900A_IOBASE 0x020000 67#define PBC_CS8900A_IOBASE 0x020000
92/*! 68
93 * Ethernet Controller Memory base address. 69/* Ethernet Controller Memory base address */
94 */
95#define PBC_CS8900A_MEMBASE 0x021000 70#define PBC_CS8900A_MEMBASE 0x021000
96/*! 71
97 * Ethernet Controller DMA base address. 72/* Ethernet Controller DMA base address */
98 */
99#define PBC_CS8900A_DMABASE 0x022000 73#define PBC_CS8900A_DMABASE 0x022000
100/*! 74
101 * External chip select 0. 75/* External chip select 0 */
102 */
103#define PBC_XCS0 0x040000 76#define PBC_XCS0 0x040000
104/*! 77
105 * LCD Display enable. 78/* LCD Display enable */
106 */
107#define PBC_LCD_EN_B 0x060000 79#define PBC_LCD_EN_B 0x060000
108/*! 80
109 * Code test debug enable. 81/* Code test debug enable */
110 */
111#define PBC_CODE_B 0x070000 82#define PBC_CODE_B 0x070000
112/*! 83
113 * PSRAM memory select. 84/* PSRAM memory select */
114 */
115#define PBC_PSRAM_B 0x5000000 85#define PBC_PSRAM_B 0x5000000
116 86
117#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) 87#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
@@ -139,4 +109,4 @@
139 109
140#define MXC_MAX_EXP_IO_LINES 16 110#define MXC_MAX_EXP_IO_LINES 16
141 111
142#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ 112#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
index 65e639d51d2b..c822d569a05e 100644
--- a/include/asm-arm/arch-mxc/dma.h
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -11,11 +11,4 @@
11#ifndef __ASM_ARCH_MXC_DMA_H__ 11#ifndef __ASM_ARCH_MXC_DMA_H__
12#define __ASM_ARCH_MXC_DMA_H__ 12#define __ASM_ARCH_MXC_DMA_H__
13 13
14/*!
15 * @file dma.h
16 * @brief This file contains Unified DMA API for all MXC platforms.
17 * The API is platform independent.
18 *
19 * @ingroup SDMA
20 */
21#endif 14#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index 3c09b92fef0d..e70387e91b77 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -8,12 +8,6 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11/*!
12 * @file hardware.h
13 * @brief This file contains the hardware definitions of the board.
14 *
15 * @ingroup System
16 */
17#ifndef __ASM_ARCH_MXC_HARDWARE_H__ 11#ifndef __ASM_ARCH_MXC_HARDWARE_H__
18#define __ASM_ARCH_MXC_HARDWARE_H__ 12#define __ASM_ARCH_MXC_HARDWARE_H__
19 13
@@ -49,4 +43,4 @@
49 MXC_MAX_EXP_IO_LINES + \ 43 MXC_MAX_EXP_IO_LINES + \
50 MXC_MAX_VIRTUAL_INTS) 44 MXC_MAX_VIRTUAL_INTS)
51 45
52#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 46#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
index cf6c83a4b9f7..65b6810124c1 100644
--- a/include/asm-arm/arch-mxc/io.h
+++ b/include/asm-arm/arch-mxc/io.h
@@ -8,24 +8,13 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11/*!
12 * @file io.h
13 * @brief This file contains some memory mapping macros.
14 * @note There is no real ISA or PCI buses. But have to define these macros
15 * for some drivers to compile.
16 *
17 * @ingroup System
18 */
19
20#ifndef __ASM_ARCH_MXC_IO_H__ 11#ifndef __ASM_ARCH_MXC_IO_H__
21#define __ASM_ARCH_MXC_IO_H__ 12#define __ASM_ARCH_MXC_IO_H__
22 13
23/*! Allow IO space to be anywhere in the memory */ 14/* Allow IO space to be anywhere in the memory */
24#define IO_SPACE_LIMIT 0xffffffff 15#define IO_SPACE_LIMIT 0xffffffff
25 16
26/*! 17/* io address mapping macro */
27 * io address mapping macro
28 */
29#define __io(a) ((void __iomem *)(a)) 18#define __io(a) ((void __iomem *)(a))
30 19
31#define __mem_pci(a) (a) 20#define __mem_pci(a) (a)
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index e4686c6bc4bf..a64e66ba4ae4 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,26 +13,15 @@
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16/*!
17 * @file irqs.h
18 * @brief This file defines the number of normal interrupts and fast interrupts
19 *
20 * @ingroup Interrupt
21 */
22
23#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) 16#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
24 17
25#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE) 18#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
26#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x) 19#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
27 20
28/*! 21/* Number of normal interrupts */
29 * Number of normal interrupts
30 */
31#define NR_IRQS MXC_MAX_INTS 22#define NR_IRQS MXC_MAX_INTS
32 23
33/*! 24/* Number of fast interrupts */
34 * Number of fast interrupts
35 */
36#define NR_FIQS MXC_MAX_INTS 25#define NR_FIQS MXC_MAX_INTS
37 26
38#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 27#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
index c89aac83a407..059f83023a10 100644
--- a/include/asm-arm/arch-mxc/memory.h
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -13,24 +13,17 @@
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16/*! 16/*
17 * @file memory.h
18 * @brief This file contains macros needed by the Linux kernel and drivers.
19 *
20 * @ingroup Memory
21 */
22
23/*!
24 * Virtual view <-> DMA view memory address translations 17 * Virtual view <-> DMA view memory address translations
25 * This macro is used to translate the virtual address to an address 18 * This macro is used to translate the virtual address to an address
26 * suitable to be passed to set_dma_addr() 19 * suitable to be passed to set_dma_addr()
27 */ 20 */
28#define __virt_to_bus(a) __virt_to_phys(a) 21#define __virt_to_bus(a) __virt_to_phys(a)
29 22
30/*! 23/*
31 * Used to convert an address for DMA operations to an address that the 24 * Used to convert an address for DMA operations to an address that the
32 * kernel can use. 25 * kernel can use.
33 */ 26 */
34#define __bus_to_virt(a) __phys_to_virt(a) 27#define __bus_to_virt(a) __phys_to_virt(a)
35 28
36#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ 29#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 0837f1f9ca31..f1349734b8af 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -31,9 +31,7 @@
31#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20) 31#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
32#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24) 32#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
33 33
34/*! 34/* GPT Control register bit definitions */
35 * GPT Control register bit definitions
36 */
37#define GPTCR_FO3 (1 << 31) 35#define GPTCR_FO3 (1 << 31)
38#define GPTCR_FO2 (1 << 30) 36#define GPTCR_FO2 (1 << 30)
39#define GPTCR_FO1 (1 << 29) 37#define GPTCR_FO1 (1 << 29)
@@ -146,4 +144,4 @@
146#define IIM_PROD_REV_SH 3 144#define IIM_PROD_REV_SH 3
147#define IIM_PROD_REV_LEN 5 145#define IIM_PROD_REV_LEN 5
148 146
149#endif /* __ASM_ARCH_MXC_H__ */ 147#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
index 109956b41aca..bbfc37465fc5 100644
--- a/include/asm-arm/arch-mxc/system.h
+++ b/include/asm-arm/arch-mxc/system.h
@@ -21,30 +21,14 @@
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 21#ifndef __ASM_ARCH_MXC_SYSTEM_H__
22#define __ASM_ARCH_MXC_SYSTEM_H__ 22#define __ASM_ARCH_MXC_SYSTEM_H__
23 23
24/*!
25 * @file system.h
26 * @brief This file contains idle and reset functions.
27 *
28 * @ingroup System
29 */
30
31/*!
32 * This function puts the CPU into idle mode. It is called by default_idle()
33 * in process.c file.
34 */
35static inline void arch_idle(void) 24static inline void arch_idle(void)
36{ 25{
37 cpu_do_idle(); 26 cpu_do_idle();
38} 27}
39 28
40/*
41 * This function resets the system. It is called by machine_restart().
42 *
43 * @param mode indicates different kinds of resets
44 */
45static inline void arch_reset(char mode) 29static inline void arch_reset(char mode)
46{ 30{
47 cpu_reset(0); 31 cpu_reset(0);
48} 32}
49 33
50#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ 34#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
index 83a73da895eb..62d97623412f 100644
--- a/include/asm-arm/arch-mxc/vmalloc.h
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -20,17 +20,7 @@
20#ifndef __ASM_ARCH_MXC_VMALLOC_H__ 20#ifndef __ASM_ARCH_MXC_VMALLOC_H__
21#define __ASM_ARCH_MXC_VMALLOC_H__ 21#define __ASM_ARCH_MXC_VMALLOC_H__
22 22
23/*! 23/* vmalloc ending address */
24 * @file vmalloc.h
25 *
26 * @brief This file contains platform specific macros for vmalloc.
27 *
28 * @ingroup System
29 */
30
31/*!
32 * vmalloc ending address
33 */
34#define VMALLOC_END 0xF4000000 24#define VMALLOC_END 0xF4000000
35 25
36#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ 26#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */